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-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package int_types is
type small_int is range 0 to 255;
end package int_types;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package int_types is
type small_int is range 0 to 255;
end package int_types;
|
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`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect begin_protected
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`protect begin_protected
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`protect end_protected
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:42:09 10/21/2015
-- Design Name:
-- Module Name: four_bit_full_adder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity four_bit_full_adder is
Port ( x : in STD_LOGIC_VECTOR (3 downto 0);
y : in STD_LOGIC_VECTOR (3 downto 0);
cin : in STD_LOGIC;
msb_cin: out STD_LOGIC;
sum : out STD_LOGIC_VECTOR (3 downto 0);
cout : out STD_LOGIC);
end four_bit_full_adder;
architecture Behavioral of four_bit_full_adder is
--Use the one bit adder
component one_bit_full_adder
Port( x : in STD_LOGIC;
y : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end component;
--Internal Signals
signal i_carry: STD_LOGIC_VECTOR(2 downto 0);
begin
cell_1: one_bit_full_adder
port map(x(0), y(0), cin, sum(0), i_carry(0));
cell_2: one_bit_full_adder
port map(x(1), y(1), i_carry(0), sum(1), i_carry(1));
cell_3: one_bit_full_adder
port map(x(2), y(2), i_carry(1), sum(2), i_carry(2));
cell_4: one_bit_full_adder
port map(x(3), y(3), i_carry(2), sum(3), cout);
--Used for XORb
msb_cin <= i_carry(2);
end Behavioral;
|
entity snum03 is
port (ok : out boolean);
end snum03;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of snum03 is
-- add uns nat
constant a1 : unsigned (7 downto 0) := x"1d";
constant b1 : integer := 3;
constant r1 : unsigned (7 downto 0) := a1 + b1;
signal er1 : unsigned (7 downto 0) := x"20";
begin
-- ok <= r1 = x"20";
ok <= r1 = er1;
end behav;
|
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity neuron_model is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
step_once_complete : out STD_LOGIC; --signals to the core that a time step has finished
eventport_in_spike_aggregate : in STD_LOGIC_VECTOR(511 downto 0);
eventport_out_spike : out STD_LOGIC;
param_voltage_v0 : in sfixed (2 downto -22);
param_voltage_thresh : in sfixed (2 downto -22);
param_capacitance_C : in sfixed (-33 downto -47);
param_capacitance_inv_C_inv : in sfixed (47 downto 33);
exposure_voltage_v : out sfixed (2 downto -22);
statevariable_voltage_v_out : out sfixed (2 downto -22);
statevariable_voltage_v_in : in sfixed (2 downto -22);
statevariable_none_spiking_out : out sfixed (18 downto -13);
statevariable_none_spiking_in : in sfixed (18 downto -13);
param_none_leak_number : in sfixed (18 downto -13);
param_voltage_leak_erev : in sfixed (2 downto -22);
exposure_current_leak_i : out sfixed (-28 downto -53);
derivedvariable_current_leak_i_out : out sfixed (-28 downto -53);
derivedvariable_current_leak_i_in : in sfixed (-28 downto -53);
param_conductance_leak_passive_conductance : in sfixed (-22 downto -53);
exposure_conductance_leak_passive_g : out sfixed (-22 downto -53);
derivedvariable_conductance_leak_passive_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_leak_passive_g_in : in sfixed (-22 downto -53);
param_none_naChans_number : in sfixed (18 downto -13);
param_voltage_naChans_erev : in sfixed (2 downto -22);
exposure_current_naChans_i : out sfixed (-28 downto -53);
derivedvariable_current_naChans_i_out : out sfixed (-28 downto -53);
derivedvariable_current_naChans_i_in : in sfixed (-28 downto -53);
param_conductance_naChans_na_conductance : in sfixed (-22 downto -53);
exposure_conductance_naChans_na_g : out sfixed (-22 downto -53);
derivedvariable_conductance_naChans_na_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_naChans_na_g_in : in sfixed (-22 downto -53);
param_none_naChans_na_m_instances : in sfixed (18 downto -13);
exposure_none_naChans_na_m_fcond : out sfixed (18 downto -13);
exposure_none_naChans_na_m_q : out sfixed (18 downto -13);
statevariable_none_naChans_na_m_q_out : out sfixed (18 downto -13);
statevariable_none_naChans_na_m_q_in : in sfixed (18 downto -13);
derivedvariable_none_naChans_na_m_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_naChans_na_m_fcond_in : in sfixed (18 downto -13);
param_per_time_naChans_na_m_forwardRatem1_rate : in sfixed (18 downto -2);
param_voltage_naChans_na_m_forwardRatem1_midpoint : in sfixed (2 downto -22);
param_voltage_naChans_na_m_forwardRatem1_scale : in sfixed (2 downto -22);
param_voltage_inv_naChans_na_m_forwardRatem1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_naChans_na_m_forwardRatem1_r : out sfixed (18 downto -2);
derivedvariable_per_time_naChans_na_m_forwardRatem1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_naChans_na_m_forwardRatem1_r_in : in sfixed (18 downto -2);
param_per_time_naChans_na_m_reverseRatem1_rate : in sfixed (18 downto -2);
param_voltage_naChans_na_m_reverseRatem1_midpoint : in sfixed (2 downto -22);
param_voltage_naChans_na_m_reverseRatem1_scale : in sfixed (2 downto -22);
param_voltage_inv_naChans_na_m_reverseRatem1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_naChans_na_m_reverseRatem1_r : out sfixed (18 downto -2);
derivedvariable_per_time_naChans_na_m_reverseRatem1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_naChans_na_m_reverseRatem1_r_in : in sfixed (18 downto -2);
param_none_naChans_na_h_instances : in sfixed (18 downto -13);
exposure_none_naChans_na_h_fcond : out sfixed (18 downto -13);
exposure_none_naChans_na_h_q : out sfixed (18 downto -13);
statevariable_none_naChans_na_h_q_out : out sfixed (18 downto -13);
statevariable_none_naChans_na_h_q_in : in sfixed (18 downto -13);
derivedvariable_none_naChans_na_h_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_naChans_na_h_fcond_in : in sfixed (18 downto -13);
param_per_time_naChans_na_h_forwardRateh1_rate : in sfixed (18 downto -2);
param_voltage_naChans_na_h_forwardRateh1_midpoint : in sfixed (2 downto -22);
param_voltage_naChans_na_h_forwardRateh1_scale : in sfixed (2 downto -22);
param_voltage_inv_naChans_na_h_forwardRateh1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_naChans_na_h_forwardRateh1_r : out sfixed (18 downto -2);
derivedvariable_per_time_naChans_na_h_forwardRateh1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_naChans_na_h_forwardRateh1_r_in : in sfixed (18 downto -2);
param_per_time_naChans_na_h_reverseRateh1_rate : in sfixed (18 downto -2);
param_voltage_naChans_na_h_reverseRateh1_midpoint : in sfixed (2 downto -22);
param_voltage_naChans_na_h_reverseRateh1_scale : in sfixed (2 downto -22);
param_voltage_inv_naChans_na_h_reverseRateh1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_naChans_na_h_reverseRateh1_r : out sfixed (18 downto -2);
derivedvariable_per_time_naChans_na_h_reverseRateh1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_naChans_na_h_reverseRateh1_r_in : in sfixed (18 downto -2);
param_none_kChans_number : in sfixed (18 downto -13);
param_voltage_kChans_erev : in sfixed (2 downto -22);
exposure_current_kChans_i : out sfixed (-28 downto -53);
derivedvariable_current_kChans_i_out : out sfixed (-28 downto -53);
derivedvariable_current_kChans_i_in : in sfixed (-28 downto -53);
param_conductance_kChans_k_conductance : in sfixed (-22 downto -53);
exposure_conductance_kChans_k_g : out sfixed (-22 downto -53);
derivedvariable_conductance_kChans_k_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_kChans_k_g_in : in sfixed (-22 downto -53);
param_none_kChans_k_n_instances : in sfixed (18 downto -13);
exposure_none_kChans_k_n_fcond : out sfixed (18 downto -13);
exposure_none_kChans_k_n_q : out sfixed (18 downto -13);
statevariable_none_kChans_k_n_q_out : out sfixed (18 downto -13);
statevariable_none_kChans_k_n_q_in : in sfixed (18 downto -13);
derivedvariable_none_kChans_k_n_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_kChans_k_n_fcond_in : in sfixed (18 downto -13);
param_per_time_kChans_k_n_forwardRaten1_rate : in sfixed (18 downto -2);
param_voltage_kChans_k_n_forwardRaten1_midpoint : in sfixed (2 downto -22);
param_voltage_kChans_k_n_forwardRaten1_scale : in sfixed (2 downto -22);
param_voltage_inv_kChans_k_n_forwardRaten1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_kChans_k_n_forwardRaten1_r : out sfixed (18 downto -2);
derivedvariable_per_time_kChans_k_n_forwardRaten1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_kChans_k_n_forwardRaten1_r_in : in sfixed (18 downto -2);
param_per_time_kChans_k_n_reverseRaten1_rate : in sfixed (18 downto -2);
param_voltage_kChans_k_n_reverseRaten1_midpoint : in sfixed (2 downto -22);
param_voltage_kChans_k_n_reverseRaten1_scale : in sfixed (2 downto -22);
param_voltage_inv_kChans_k_n_reverseRaten1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_kChans_k_n_reverseRaten1_r : out sfixed (18 downto -2);
derivedvariable_per_time_kChans_k_n_reverseRaten1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_kChans_k_n_reverseRaten1_r_in : in sfixed (18 downto -2);
param_time_synapsemodel_tauDecay : in sfixed (6 downto -18);
param_conductance_synapsemodel_gbase : in sfixed (-22 downto -53);
param_voltage_synapsemodel_erev : in sfixed (2 downto -22);
param_time_inv_synapsemodel_tauDecay_inv : in sfixed (18 downto -6);
exposure_current_synapsemodel_i : out sfixed (-28 downto -53);
exposure_conductance_synapsemodel_g : out sfixed (-22 downto -53);
statevariable_conductance_synapsemodel_g_out : out sfixed (-22 downto -53);
statevariable_conductance_synapsemodel_g_in : in sfixed (-22 downto -53);
derivedvariable_current_synapsemodel_i_out : out sfixed (-28 downto -53);
derivedvariable_current_synapsemodel_i_in : in sfixed (-28 downto -53);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end neuron_model;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of neuron_model is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';signal synapsemodel_step_once_complete_fired : STD_LOGIC := '1';
signal step_once_complete_fired : STD_LOGIC := '1';
signal Component_done : STD_LOGIC := '0';
constant cNSpikeSources : integer := 512; -- The number of spike sources.
constant cNOutputs : integer := 512; -- The number of Synapses in the neuron model.
constant cNSelectBits : integer := 9; -- Log2(NOutputs), rounded up.
signal SpikeOut : Std_logic_vector((cNOutputs-1) downto 0);
signal statevariable_voltage_noregime_v_temp_1 : sfixed (2 downto -22);
signal statevariable_voltage_noregime_v_temp_1_next : sfixed (2 downto -22);
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_current_iChannels : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_iChannels_next : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_iSyn : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_iSyn_next : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_iMemb : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_iMemb_next : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
signal statevariable_voltage_v_next : sfixed (2 downto -22);
signal statevariable_none_spiking_next : sfixed (18 downto -13);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
signal EventPort_out_spike_internal : std_logic := '0';
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
component leak
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_none_number : in sfixed (18 downto -13);
param_voltage_erev : in sfixed (2 downto -22);
exposure_current_i : out sfixed (-28 downto -53);
derivedvariable_current_i_out : out sfixed (-28 downto -53);
derivedvariable_current_i_in : in sfixed (-28 downto -53);
param_conductance_passive_conductance : in sfixed (-22 downto -53);
exposure_conductance_passive_g : out sfixed (-22 downto -53);
derivedvariable_conductance_passive_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_passive_g_in : in sfixed (-22 downto -53);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal leak_Component_done : STD_LOGIC ; signal Exposure_current_leak_i_internal : sfixed (-28 downto -53);
signal Exposure_conductance_leak_passive_g_internal : sfixed (-22 downto -53);
---------------------------------------------------------------------
component naChans
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_none_number : in sfixed (18 downto -13);
param_voltage_erev : in sfixed (2 downto -22);
exposure_current_i : out sfixed (-28 downto -53);
derivedvariable_current_i_out : out sfixed (-28 downto -53);
derivedvariable_current_i_in : in sfixed (-28 downto -53);
param_conductance_na_conductance : in sfixed (-22 downto -53);
exposure_conductance_na_g : out sfixed (-22 downto -53);
derivedvariable_conductance_na_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_na_g_in : in sfixed (-22 downto -53);
param_none_na_m_instances : in sfixed (18 downto -13);
exposure_none_na_m_fcond : out sfixed (18 downto -13);
exposure_none_na_m_q : out sfixed (18 downto -13);
statevariable_none_na_m_q_out : out sfixed (18 downto -13);
statevariable_none_na_m_q_in : in sfixed (18 downto -13);
derivedvariable_none_na_m_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_na_m_fcond_in : in sfixed (18 downto -13);
param_per_time_na_m_forwardRatem1_rate : in sfixed (18 downto -2);
param_voltage_na_m_forwardRatem1_midpoint : in sfixed (2 downto -22);
param_voltage_na_m_forwardRatem1_scale : in sfixed (2 downto -22);
param_voltage_inv_na_m_forwardRatem1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_na_m_forwardRatem1_r : out sfixed (18 downto -2);
derivedvariable_per_time_na_m_forwardRatem1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_na_m_forwardRatem1_r_in : in sfixed (18 downto -2);
param_per_time_na_m_reverseRatem1_rate : in sfixed (18 downto -2);
param_voltage_na_m_reverseRatem1_midpoint : in sfixed (2 downto -22);
param_voltage_na_m_reverseRatem1_scale : in sfixed (2 downto -22);
param_voltage_inv_na_m_reverseRatem1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_na_m_reverseRatem1_r : out sfixed (18 downto -2);
derivedvariable_per_time_na_m_reverseRatem1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_na_m_reverseRatem1_r_in : in sfixed (18 downto -2);
param_none_na_h_instances : in sfixed (18 downto -13);
exposure_none_na_h_fcond : out sfixed (18 downto -13);
exposure_none_na_h_q : out sfixed (18 downto -13);
statevariable_none_na_h_q_out : out sfixed (18 downto -13);
statevariable_none_na_h_q_in : in sfixed (18 downto -13);
derivedvariable_none_na_h_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_na_h_fcond_in : in sfixed (18 downto -13);
param_per_time_na_h_forwardRateh1_rate : in sfixed (18 downto -2);
param_voltage_na_h_forwardRateh1_midpoint : in sfixed (2 downto -22);
param_voltage_na_h_forwardRateh1_scale : in sfixed (2 downto -22);
param_voltage_inv_na_h_forwardRateh1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_na_h_forwardRateh1_r : out sfixed (18 downto -2);
derivedvariable_per_time_na_h_forwardRateh1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_na_h_forwardRateh1_r_in : in sfixed (18 downto -2);
param_per_time_na_h_reverseRateh1_rate : in sfixed (18 downto -2);
param_voltage_na_h_reverseRateh1_midpoint : in sfixed (2 downto -22);
param_voltage_na_h_reverseRateh1_scale : in sfixed (2 downto -22);
param_voltage_inv_na_h_reverseRateh1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_na_h_reverseRateh1_r : out sfixed (18 downto -2);
derivedvariable_per_time_na_h_reverseRateh1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_na_h_reverseRateh1_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal naChans_Component_done : STD_LOGIC ; signal Exposure_current_naChans_i_internal : sfixed (-28 downto -53);
signal Exposure_conductance_naChans_na_g_internal : sfixed (-22 downto -53);
signal Exposure_none_naChans_na_m_fcond_internal : sfixed (18 downto -13);
signal Exposure_none_naChans_na_m_q_internal : sfixed (18 downto -13);
signal Exposure_per_time_naChans_na_m_forwardRatem1_r_internal : sfixed (18 downto -2);
signal Exposure_per_time_naChans_na_m_reverseRatem1_r_internal : sfixed (18 downto -2);
signal Exposure_none_naChans_na_h_fcond_internal : sfixed (18 downto -13);
signal Exposure_none_naChans_na_h_q_internal : sfixed (18 downto -13);
signal Exposure_per_time_naChans_na_h_forwardRateh1_r_internal : sfixed (18 downto -2);
signal Exposure_per_time_naChans_na_h_reverseRateh1_r_internal : sfixed (18 downto -2);
---------------------------------------------------------------------
component kChans
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_none_number : in sfixed (18 downto -13);
param_voltage_erev : in sfixed (2 downto -22);
exposure_current_i : out sfixed (-28 downto -53);
derivedvariable_current_i_out : out sfixed (-28 downto -53);
derivedvariable_current_i_in : in sfixed (-28 downto -53);
param_conductance_k_conductance : in sfixed (-22 downto -53);
exposure_conductance_k_g : out sfixed (-22 downto -53);
derivedvariable_conductance_k_g_out : out sfixed (-22 downto -53);
derivedvariable_conductance_k_g_in : in sfixed (-22 downto -53);
param_none_k_n_instances : in sfixed (18 downto -13);
exposure_none_k_n_fcond : out sfixed (18 downto -13);
exposure_none_k_n_q : out sfixed (18 downto -13);
statevariable_none_k_n_q_out : out sfixed (18 downto -13);
statevariable_none_k_n_q_in : in sfixed (18 downto -13);
derivedvariable_none_k_n_fcond_out : out sfixed (18 downto -13);
derivedvariable_none_k_n_fcond_in : in sfixed (18 downto -13);
param_per_time_k_n_forwardRaten1_rate : in sfixed (18 downto -2);
param_voltage_k_n_forwardRaten1_midpoint : in sfixed (2 downto -22);
param_voltage_k_n_forwardRaten1_scale : in sfixed (2 downto -22);
param_voltage_inv_k_n_forwardRaten1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_k_n_forwardRaten1_r : out sfixed (18 downto -2);
derivedvariable_per_time_k_n_forwardRaten1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_k_n_forwardRaten1_r_in : in sfixed (18 downto -2);
param_per_time_k_n_reverseRaten1_rate : in sfixed (18 downto -2);
param_voltage_k_n_reverseRaten1_midpoint : in sfixed (2 downto -22);
param_voltage_k_n_reverseRaten1_scale : in sfixed (2 downto -22);
param_voltage_inv_k_n_reverseRaten1_scale_inv : in sfixed (22 downto -2);
exposure_per_time_k_n_reverseRaten1_r : out sfixed (18 downto -2);
derivedvariable_per_time_k_n_reverseRaten1_r_out : out sfixed (18 downto -2);
derivedvariable_per_time_k_n_reverseRaten1_r_in : in sfixed (18 downto -2);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal kChans_Component_done : STD_LOGIC ; signal Exposure_current_kChans_i_internal : sfixed (-28 downto -53);
signal Exposure_conductance_kChans_k_g_internal : sfixed (-22 downto -53);
signal Exposure_none_kChans_k_n_fcond_internal : sfixed (18 downto -13);
signal Exposure_none_kChans_k_n_q_internal : sfixed (18 downto -13);
signal Exposure_per_time_kChans_k_n_forwardRaten1_r_internal : sfixed (18 downto -2);
signal Exposure_per_time_kChans_k_n_reverseRaten1_r_internal : sfixed (18 downto -2);
---------------------------------------------------------------------
component synapsemodel
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC;
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
Component_done : out STD_LOGIC;
eventport_in_in : in STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_time_tauDecay : in sfixed (6 downto -18);
param_conductance_gbase : in sfixed (-22 downto -53);
param_voltage_erev : in sfixed (2 downto -22);
param_time_inv_tauDecay_inv : in sfixed (18 downto -6);
exposure_current_i : out sfixed (-28 downto -53);
exposure_conductance_g : out sfixed (-22 downto -53);
statevariable_conductance_g_out : out sfixed (-22 downto -53);
statevariable_conductance_g_in : in sfixed (-22 downto -53);
derivedvariable_current_i_out : out sfixed (-28 downto -53);
derivedvariable_current_i_in : in sfixed (-28 downto -53);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end component;
signal synapsemodel_Component_done : STD_LOGIC ; signal Exposure_current_synapsemodel_i_internal : sfixed (-28 downto -53);
signal Exposure_conductance_synapsemodel_g_internal : sfixed (-22 downto -53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
leak_uut : leak
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => leak_Component_done,
param_none_number => param_none_leak_number,
param_voltage_erev => param_voltage_leak_erev,
requirement_voltage_v => statevariable_voltage_v_in,
Exposure_current_i => Exposure_current_leak_i_internal,
derivedvariable_current_i_out => derivedvariable_current_leak_i_out,
derivedvariable_current_i_in => derivedvariable_current_leak_i_in,
param_conductance_passive_conductance => param_conductance_leak_passive_conductance,
Exposure_conductance_passive_g => Exposure_conductance_leak_passive_g_internal,
derivedvariable_conductance_passive_g_out => derivedvariable_conductance_leak_passive_g_out,
derivedvariable_conductance_passive_g_in => derivedvariable_conductance_leak_passive_g_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_current_leak_i <= Exposure_current_leak_i_internal;
naChans_uut : naChans
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => naChans_Component_done,
param_none_number => param_none_naChans_number,
param_voltage_erev => param_voltage_naChans_erev,
requirement_voltage_v => statevariable_voltage_v_in,
Exposure_current_i => Exposure_current_naChans_i_internal,
derivedvariable_current_i_out => derivedvariable_current_naChans_i_out,
derivedvariable_current_i_in => derivedvariable_current_naChans_i_in,
param_conductance_na_conductance => param_conductance_naChans_na_conductance,
Exposure_conductance_na_g => Exposure_conductance_naChans_na_g_internal,
derivedvariable_conductance_na_g_out => derivedvariable_conductance_naChans_na_g_out,
derivedvariable_conductance_na_g_in => derivedvariable_conductance_naChans_na_g_in,
param_none_na_m_instances => param_none_naChans_na_m_instances,
Exposure_none_na_m_fcond => Exposure_none_naChans_na_m_fcond_internal,
Exposure_none_na_m_q => Exposure_none_naChans_na_m_q_internal,
statevariable_none_na_m_q_out => statevariable_none_naChans_na_m_q_out,
statevariable_none_na_m_q_in => statevariable_none_naChans_na_m_q_in,
derivedvariable_none_na_m_fcond_out => derivedvariable_none_naChans_na_m_fcond_out,
derivedvariable_none_na_m_fcond_in => derivedvariable_none_naChans_na_m_fcond_in,
param_per_time_na_m_forwardRatem1_rate => param_per_time_naChans_na_m_forwardRatem1_rate,
param_voltage_na_m_forwardRatem1_midpoint => param_voltage_naChans_na_m_forwardRatem1_midpoint,
param_voltage_na_m_forwardRatem1_scale => param_voltage_naChans_na_m_forwardRatem1_scale,
param_voltage_inv_na_m_forwardRatem1_scale_inv => param_voltage_inv_naChans_na_m_forwardRatem1_scale_inv,
Exposure_per_time_na_m_forwardRatem1_r => Exposure_per_time_naChans_na_m_forwardRatem1_r_internal,
derivedvariable_per_time_na_m_forwardRatem1_r_out => derivedvariable_per_time_naChans_na_m_forwardRatem1_r_out,
derivedvariable_per_time_na_m_forwardRatem1_r_in => derivedvariable_per_time_naChans_na_m_forwardRatem1_r_in,
param_per_time_na_m_reverseRatem1_rate => param_per_time_naChans_na_m_reverseRatem1_rate,
param_voltage_na_m_reverseRatem1_midpoint => param_voltage_naChans_na_m_reverseRatem1_midpoint,
param_voltage_na_m_reverseRatem1_scale => param_voltage_naChans_na_m_reverseRatem1_scale,
param_voltage_inv_na_m_reverseRatem1_scale_inv => param_voltage_inv_naChans_na_m_reverseRatem1_scale_inv,
Exposure_per_time_na_m_reverseRatem1_r => Exposure_per_time_naChans_na_m_reverseRatem1_r_internal,
derivedvariable_per_time_na_m_reverseRatem1_r_out => derivedvariable_per_time_naChans_na_m_reverseRatem1_r_out,
derivedvariable_per_time_na_m_reverseRatem1_r_in => derivedvariable_per_time_naChans_na_m_reverseRatem1_r_in,
param_none_na_h_instances => param_none_naChans_na_h_instances,
Exposure_none_na_h_fcond => Exposure_none_naChans_na_h_fcond_internal,
Exposure_none_na_h_q => Exposure_none_naChans_na_h_q_internal,
statevariable_none_na_h_q_out => statevariable_none_naChans_na_h_q_out,
statevariable_none_na_h_q_in => statevariable_none_naChans_na_h_q_in,
derivedvariable_none_na_h_fcond_out => derivedvariable_none_naChans_na_h_fcond_out,
derivedvariable_none_na_h_fcond_in => derivedvariable_none_naChans_na_h_fcond_in,
param_per_time_na_h_forwardRateh1_rate => param_per_time_naChans_na_h_forwardRateh1_rate,
param_voltage_na_h_forwardRateh1_midpoint => param_voltage_naChans_na_h_forwardRateh1_midpoint,
param_voltage_na_h_forwardRateh1_scale => param_voltage_naChans_na_h_forwardRateh1_scale,
param_voltage_inv_na_h_forwardRateh1_scale_inv => param_voltage_inv_naChans_na_h_forwardRateh1_scale_inv,
Exposure_per_time_na_h_forwardRateh1_r => Exposure_per_time_naChans_na_h_forwardRateh1_r_internal,
derivedvariable_per_time_na_h_forwardRateh1_r_out => derivedvariable_per_time_naChans_na_h_forwardRateh1_r_out,
derivedvariable_per_time_na_h_forwardRateh1_r_in => derivedvariable_per_time_naChans_na_h_forwardRateh1_r_in,
param_per_time_na_h_reverseRateh1_rate => param_per_time_naChans_na_h_reverseRateh1_rate,
param_voltage_na_h_reverseRateh1_midpoint => param_voltage_naChans_na_h_reverseRateh1_midpoint,
param_voltage_na_h_reverseRateh1_scale => param_voltage_naChans_na_h_reverseRateh1_scale,
param_voltage_inv_na_h_reverseRateh1_scale_inv => param_voltage_inv_naChans_na_h_reverseRateh1_scale_inv,
Exposure_per_time_na_h_reverseRateh1_r => Exposure_per_time_naChans_na_h_reverseRateh1_r_internal,
derivedvariable_per_time_na_h_reverseRateh1_r_out => derivedvariable_per_time_naChans_na_h_reverseRateh1_r_out,
derivedvariable_per_time_na_h_reverseRateh1_r_in => derivedvariable_per_time_naChans_na_h_reverseRateh1_r_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_current_naChans_i <= Exposure_current_naChans_i_internal;
kChans_uut : kChans
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => kChans_Component_done,
param_none_number => param_none_kChans_number,
param_voltage_erev => param_voltage_kChans_erev,
requirement_voltage_v => statevariable_voltage_v_in,
Exposure_current_i => Exposure_current_kChans_i_internal,
derivedvariable_current_i_out => derivedvariable_current_kChans_i_out,
derivedvariable_current_i_in => derivedvariable_current_kChans_i_in,
param_conductance_k_conductance => param_conductance_kChans_k_conductance,
Exposure_conductance_k_g => Exposure_conductance_kChans_k_g_internal,
derivedvariable_conductance_k_g_out => derivedvariable_conductance_kChans_k_g_out,
derivedvariable_conductance_k_g_in => derivedvariable_conductance_kChans_k_g_in,
param_none_k_n_instances => param_none_kChans_k_n_instances,
Exposure_none_k_n_fcond => Exposure_none_kChans_k_n_fcond_internal,
Exposure_none_k_n_q => Exposure_none_kChans_k_n_q_internal,
statevariable_none_k_n_q_out => statevariable_none_kChans_k_n_q_out,
statevariable_none_k_n_q_in => statevariable_none_kChans_k_n_q_in,
derivedvariable_none_k_n_fcond_out => derivedvariable_none_kChans_k_n_fcond_out,
derivedvariable_none_k_n_fcond_in => derivedvariable_none_kChans_k_n_fcond_in,
param_per_time_k_n_forwardRaten1_rate => param_per_time_kChans_k_n_forwardRaten1_rate,
param_voltage_k_n_forwardRaten1_midpoint => param_voltage_kChans_k_n_forwardRaten1_midpoint,
param_voltage_k_n_forwardRaten1_scale => param_voltage_kChans_k_n_forwardRaten1_scale,
param_voltage_inv_k_n_forwardRaten1_scale_inv => param_voltage_inv_kChans_k_n_forwardRaten1_scale_inv,
Exposure_per_time_k_n_forwardRaten1_r => Exposure_per_time_kChans_k_n_forwardRaten1_r_internal,
derivedvariable_per_time_k_n_forwardRaten1_r_out => derivedvariable_per_time_kChans_k_n_forwardRaten1_r_out,
derivedvariable_per_time_k_n_forwardRaten1_r_in => derivedvariable_per_time_kChans_k_n_forwardRaten1_r_in,
param_per_time_k_n_reverseRaten1_rate => param_per_time_kChans_k_n_reverseRaten1_rate,
param_voltage_k_n_reverseRaten1_midpoint => param_voltage_kChans_k_n_reverseRaten1_midpoint,
param_voltage_k_n_reverseRaten1_scale => param_voltage_kChans_k_n_reverseRaten1_scale,
param_voltage_inv_k_n_reverseRaten1_scale_inv => param_voltage_inv_kChans_k_n_reverseRaten1_scale_inv,
Exposure_per_time_k_n_reverseRaten1_r => Exposure_per_time_kChans_k_n_reverseRaten1_r_internal,
derivedvariable_per_time_k_n_reverseRaten1_r_out => derivedvariable_per_time_kChans_k_n_reverseRaten1_r_out,
derivedvariable_per_time_k_n_reverseRaten1_r_in => derivedvariable_per_time_kChans_k_n_reverseRaten1_r_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_current_kChans_i <= Exposure_current_kChans_i_internal;
synapsemodel_uut : synapsemodel
port map (
clk => clk,
init_model => init_model,
step_once_go => step_once_go,
Component_done => synapsemodel_Component_done,
eventport_in_in => EventPort_in_spike_aggregate(0),
param_time_tauDecay => param_time_synapsemodel_tauDecay,
param_conductance_gbase => param_conductance_synapsemodel_gbase,
param_voltage_erev => param_voltage_synapsemodel_erev,
param_time_inv_tauDecay_inv => param_time_inv_synapsemodel_tauDecay_inv,
requirement_voltage_v => statevariable_voltage_v_in,
Exposure_current_i => Exposure_current_synapsemodel_i_internal,
Exposure_conductance_g => Exposure_conductance_synapsemodel_g_internal,
statevariable_conductance_g_out => statevariable_conductance_synapsemodel_g_out,
statevariable_conductance_g_in => statevariable_conductance_synapsemodel_g_in,
derivedvariable_current_i_out => derivedvariable_current_synapsemodel_i_out,
derivedvariable_current_i_in => derivedvariable_current_synapsemodel_i_in,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
Exposure_current_synapsemodel_i <= Exposure_current_synapsemodel_i_internal;
Exposure_conductance_synapsemodel_g <= Exposure_conductance_synapsemodel_g_internal;
derived_variable_pre_process_comb :process ( sysparam_time_timestep,exposure_current_leak_i_internal,exposure_current_naChans_i_internal,exposure_current_kChans_i_internal,exposure_current_synapsemodel_i_internal, derivedvariable_current_iChannels_next , derivedvariable_current_iSyn_next )
begin
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
--no complex steps in derived variables
subprocess_der_int_ready <= '1';
derived_variable_process_comb :process ( sysparam_time_timestep,exposure_current_leak_i_internal,exposure_current_naChans_i_internal,exposure_current_kChans_i_internal,exposure_current_synapsemodel_i_internal, derivedvariable_current_iChannels_next , derivedvariable_current_iSyn_next )
begin
derivedvariable_current_iChannels_next <= resize(( ( ( exposure_current_leak_i_internal + exposure_current_naChans_i_internal ) + exposure_current_kChans_i_internal ) ),-28,-53);
derivedvariable_current_iSyn_next <= resize(( exposure_current_synapsemodel_i_internal ),-28,-53);
derivedvariable_current_iMemb_next <= resize(( derivedvariable_current_iChannels_next + derivedvariable_current_iSyn_next ),-28,-53);
subprocess_der_ready <= '1';
end process derived_variable_process_comb;
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_current_iChannels <= derivedvariable_current_iChannels_next;
derivedvariable_current_iSyn <= derivedvariable_current_iSyn_next;
derivedvariable_current_iMemb <= derivedvariable_current_iMemb_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep, derivedvariable_current_iMemb , param_capacitance_C,param_capacitance_inv_C_inv )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep, derivedvariable_current_iMemb , param_capacitance_C,param_capacitance_inv_C_inv ,statevariable_voltage_v_in)
begin
statevariable_voltage_noregime_v_temp_1_next <= resize(statevariable_voltage_v_in + ( derivedvariable_current_iMemb * param_capacitance_inv_C_inv ) * sysparam_time_timestep,2,-22);
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
statevariable_voltage_noregime_v_temp_1 <= statevariable_voltage_noregime_v_temp_1_next;
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState variable: $par.name Driver Process
---------------------------------------------------------------------
state_variable_process_comb_0 :process (sysparam_time_timestep,init_model,param_voltage_v0,statevariable_voltage_noregime_v_temp_1,derivedvariable_current_iMemb,param_capacitance_C,param_capacitance_inv_C_inv)
variable statevariable_voltage_v_temp_1 : sfixed (2 downto -22);
begin
statevariable_voltage_v_temp_1 := statevariable_voltage_noregime_v_temp_1; statevariable_voltage_v_next <= statevariable_voltage_v_temp_1;
end process;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState variable: $par.name Driver Process
---------------------------------------------------------------------
state_variable_process_comb_1 :process (sysparam_time_timestep,init_model,param_voltage_v0,param_voltage_thresh,statevariable_voltage_v_in,statevariable_none_spiking_in,param_voltage_thresh,statevariable_voltage_v_in)
variable statevariable_none_spiking_temp_1 : sfixed (18 downto -13);
variable statevariable_none_spiking_temp_2 : sfixed (18 downto -13);
begin
if To_slv ( resize ( statevariable_voltage_v_in - ( param_voltage_thresh ) ,2,-18))(20) = '0' AND To_slv ( resize ( statevariable_none_spiking_in - ( to_sfixed ( 0.5 ,0 , -1 ) ) ,2,-18))(20) = '1' then
statevariable_none_spiking_temp_1 := resize( to_sfixed ( 1 ,1 , -1 ) ,18,-13);
else
statevariable_none_spiking_temp_1 := statevariable_none_spiking_in;
end if;
if To_slv ( resize ( statevariable_voltage_v_in - ( param_voltage_thresh ) ,2,-18))(20) = '1' then
statevariable_none_spiking_temp_2 := resize( to_sfixed ( 0 ,0 , -1 ) ,18,-13);
else
statevariable_none_spiking_temp_2 := statevariable_none_spiking_temp_1;
end if;
statevariable_none_spiking_next <= statevariable_none_spiking_temp_2;
end process;
---------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
eventport_driver0 :process ( clk,sysparam_time_timestep,init_model, param_voltage_thresh, statevariable_voltage_v_in , statevariable_none_spiking_in )
variable eventport_out_spike_temp_1 : std_logic;
variable eventport_out_spike_temp_2 : std_logic;
begin
if rising_edge(clk) and subprocess_all_ready_shot = '1' then
if To_slv ( resize ( statevariable_voltage_v_in - ( param_voltage_thresh ) ,2,-18))(20) = '0' AND To_slv ( resize ( statevariable_none_spiking_in - ( to_sfixed ( 0.5 ,0 , -1 ) ) ,2,-18))(20) = '1' then
eventport_out_spike_temp_1 := '1';
else
eventport_out_spike_temp_1 := '0';
end if;eventport_out_spike_internal <= eventport_out_spike_temp_1;
end if;
end process;
---------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
exposure_voltage_v <= statevariable_voltage_v_in;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
statevariable_voltage_v_out <= statevariable_voltage_v_next;statevariable_none_spiking_out <= statevariable_none_spiking_next;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
childrenCombined_component_done_process:process(leak_component_done,naChans_component_done,kChans_component_done,synapsemodel_component_done,CLK)
begin
if (leak_component_done = '1' and naChans_component_done = '1' and kChans_component_done = '1' and synapsemodel_component_done = '1') then
childrenCombined_component_done <= '1';
else
childrenCombined_component_done <= '0';
end if;
end process childrenCombined_component_done_process;
component_done <= component_done_int and childrenCombined_component_done;
---------------------------------------------------------------------
-- Control the done signal
---------------------------------------------------------------------
step_once_complete_synch:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then step_once_complete <= '0';
step_once_complete_fired <= '1';
else if component_done = '1' and step_once_complete_fired = '0' then
step_once_complete <= '1';
step_once_complete_fired <= '1';
---------------------------------------------------------------------
-- Assign event ports to exposures
---------------------------------------------------------------------
eventport_out_spike <= eventport_out_spike_internal ;
---------------------------------------------------------------------
elsif component_done = '0' then
step_once_complete <= '0';
step_once_complete_fired <= '0';
---------------------------------------------------------------------
-- Assign event ports to exposures
---------------------------------------------------------------------
eventport_out_spike <= '0';
---------------------------------------------------------------------
else
step_once_complete <= '0';
---------------------------------------------------------------------
-- Assign event ports to exposures
---------------------------------------------------------------------
eventport_out_spike <= '0';
---------------------------------------------------------------------
end if;
end if;
end if;
end process step_once_complete_synch;
---------------------------------------------------------------------
end RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use work.aua_types.all;
entity if_tb is
end if_tb;
architecture if_test of if_tb is
component ent_if is
port (
clk : in std_logic;
reset : in std_logic;
-- pipeline register outputs
opcode : out opcode_t;
dest : out reg_t;
pc_out : out word_t;
rega : out reg_t;
regb : out reg_t;
imm : out std_logic_vector(7 downto 0);
-- asynchron register outputs
async_rega : out reg_t;
async_regb : out reg_t;
-- branches (from ID)
pc_in : in word_t;
branch : in std_logic;
-- mmu
instr_addr : out word_t;
instr_data : in word_t
);
end component;
signal clk : std_logic;
signal reset : std_logic;
-- pipeline register outputs
signal opcode : opcode_t;
signal dest : reg_t;
signal pc_out : word_t;
signal rega : reg_t;
signal regb : reg_t;
signal imm : std_logic_vector(7 downto 0);
signal async_rega : reg_t;
signal async_regb : reg_t;
-- branches (from ID)
signal pc_in : word_t;
signal branch : std_logic;
-- mmu
signal instr_addr : word_t;
signal instr_data : word_t;
begin
if1: ent_if
port map(clk, reset, opcode, dest, pc_out, rega, regb, imm, async_rega, async_regb, pc_in, branch, instr_addr, instr_data);
CLKGEN: process
begin
clk <= '1';
wait for 5 ns;
clk <= '0';
wait for 5 ns;
end process CLKGEN;
TEST: process
procedure icwait(cycles : natural) is
begin
for i in 1 to cycles loop
wait until clk = '0' and clk'event;
end loop;
end;
begin
reset <= '1';
pc_in <= "1111111111111111";
branch <= '0';
instr_data <= "1100110010101010";
icwait(2);
--
reset <= '0';
icwait(1);
--
branch <= '1';
icwait(1);
--
branch <= '0';
instr_data <= "0000110010101010";
icwait(100);
--
end process TEST;
end if_test; |
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY tb_ctrl_filter IS
END tb_ctrl_filter;
ARCHITECTURE behavior OF tb_ctrl_filter IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ctrl_filter
port (Clk : in std_logic;
Rst : in std_logic;
PktIn : in std_logic;
DataIn : in std_logic_vector (7 downto 0);
PktOut : out std_logic;
DataOut : out std_logic_vector (7 downto 0);
CtrlEn : out std_logic;
CtrlData : out std_logic_vector (7 downto 0));
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Rst : std_logic := '0';
signal PktIn : std_logic := '0';
signal ByteIn : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal PktOut : std_logic;
signal ByteOut : std_logic_vector(7 downto 0);
signal CtrlEn : std_logic;
signal CtrlData : std_logic_vector(7 downto 0);
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ctrl_filter PORT MAP (
Clk => Clk,
Rst => Rst,
PktIn => PktIn,
DataIn => ByteIn,
PktOut => PktOut,
DataOut => ByteOut,
CtrlEn => CtrlEn,
CtrlData => CtrlData
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for Clk_period*10;
for j in 0 to 15 loop
PktIn <= '1';
for i in 1 to 7 loop
ByteIn <= x"55";
wait for Clk_period;
end loop;
ByteIn <= x"d5";
wait for Clk_period;
ByteIn <= x"00";
wait for Clk_period * 9;
for i in 1 to 15 loop
ByteIn <= CONV_std_logic_vector(i, 8);
wait for Clk_period;
end loop;
PktIn <= '0';
wait for Clk_period*10;
end loop;
wait;
end process;
END;
|
--============================================================================
--!
--! \file example_package
--!
--! \project libhdl
--!
--! \author Andreas Muller
--!
--! \date 2015-04-20
--!
--! \version 1.0
--!
--! \brief Brief package description in one or two sentences.
--!
--! \details More detailed description. This should focus on the kind of
--! functions, procedures and operators which are offered by the
--! package.
--!
--! \bug No bugs or known issues.
--!
--! \see List of references useful for the understanding of this
--! package e.g. standards, RFCs, papers, book chapters, web links
--! &cetera.
--!
--! \copyright Copyright (C) 2015, Andreas Muller
--! GNU General Public License Version 2
--!
--! This program is free software; you can redistribute it and/or
--! modify it under the terms of the GNU General Public License as
--! published by the Free Software Foundation; either version 2 of
--! the License, or (at your option) any later version.
--! This program is distributed in the hope that it will be useful,
--! but WITHOUT ANY WARRANTY; without even the implied warranty of
--! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--! GNU General Public License for more details.
--!
--============================================================================
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
package template_package is
constant MY_WORD_WIDTH : integer := 12;
subtype t_my_word is std_logic_vector(MY_WORD_WIDTH-1 downto 0);
type t_my_answers is (YES, NO, MAYBE, GLURPNARD);
type t_my_saying is record
unique_id : integer;
word : t_my_word;
some_bits : bit_vector(3 downto 0);
end record;
function "+"(op1 : t_my_word; op2 : t_my_word) return t_my_word;
procedure equalZero(signal op : in t_my_word; signal result : out boolean);
end package template_package;
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
package body template_package is
function "+"(op1 : t_my_word; op2 : t_my_word) return t_my_word is
variable reval : t_my_word;
begin
reval := std_logic_vector(unsigned(op1) + unsigned(op2));
return reval;
end function "+";
procedure equalZero(signal op : in t_my_word; signal result : out boolean) is
constant ZERO_WORD : t_my_word := (others => '0');
begin
result <= (op = ZERO_WORD);
end procedure equalZero;
end package body template_package;
|
--==========================================================================================================================
-- FILE NAME : issue_unit.vhd
-- DESCRIPTION : issue unit helps to issue one instruction at a time even when multiple instructions are ready to be issued.
-- the priority depends on LRU bit and also the latency of instruction, long latency instructions are given
-- priority , so the priority order is - div, mult, ( int type and lw/sw depending on LRU bit).
-- AUTHOR : PRASANJEET DAS, VAIBHAV DHOTRE
-- DATE : 6/17/10, 6/23/06
-- TASK : COMPLETE THE SIX TODO SECTIONS.
--===========================================================================================================================
-------------------------------------------
-- LIBRARY DECLARATION
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use work.tmslopkg.all
--ENTITY DECLARATION
entity issue_unit is
generic(
Resetb_ACTIVE_VALUE : std_logic := '0' -- ACTIVE LOW Resetb
);
port(
Clk : in std_logic;
Resetb : in std_logic;
-- ready signals from each of the queues
IssInt_Rdy : in std_logic;
IssMul_Rdy : in std_logic;
IssDiv_Rdy : in std_logic;
IssLsb_Rdy : in std_logic;
-- signal from the division execution unit to indicate that it is currently available
Div_ExeRdy : in std_logic;
--issue signals as acknowledgement from issue unit to each of the queues
Iss_Int : out std_logic;
Iss_Mult : out std_logic;
Iss_Div : out std_logic;
Iss_Lsb : out std_logic
);
end issue_unit;
-- ARCHITECTURE DECLARATION
architecture Behavioral of issue_unit is
signal CDB_Slot : std_logic_vector(5 downto 0); -- the CDB reservation register
signal LRU_bit : std_logic;
-- you can declare your own signals here
begin
--NOTE:
--================================================================================================================================================================================================
-- 1. simple approach to decide priority between int type and "lw/sw" type instructions
-- depending on the LRU bit issue the Least recently used instruction, use a LRU bit for the same which gets updated every time
-- and instruction is issued.
-- FOR SIMPLICITY ASSUME LRU BIT WHEN AN INT TYPE INSTRUCTION IS ISSUED IS "0" AND WHEN A LW/SW TYPE INSTRUCTION IS ISSUED IS "1"
-- PRECAUTION to be taken only issue the one whose corresponding issueque_ready signal is asserted ( = '1')
--2. issue mult insturction when the CDB_slot (3) is free and the corresponding issueque_ready signal is asserted (= '1') --remember the 4 clock latency
--3. issue div instruction when the Div_ExeRdy indicates that divider execution unit is ready and corresponding issueque_ready signal is asserted (= '1') -- remember the 7 clock latency
--4. don't forget to update the CDB register on every clock as per the required conditions.
--==================================================================================================================================================================================================
process(Resetb, Clk)
begin
if (Resetb = '0') then
-- TODO 1: INITIALIZE CDB and LRU Bit
CDB_Slot <= (others => '0');
LRU_bit <= '0';
elsif ( Clk'event and Clk = '1' ) then
--CDB_Slot <= -- TODO 2: COMPLETE THE SHIFT MECHANISM
CDB_Slot(5) <= '0'; --Iss_Div;
CDB_Slot(4) <= CDB_Slot(5);
CDB_Slot(3) <= CDB_Slot(4);
CDB_Slot(2) <= CDB_Slot(3); -- when (Iss_Mult = '0') else '1';
CDB_Slot(1) <= CDB_Slot(2);
CDB_Slot(0) <= CDB_Slot(1);
if (CDB_Slot(0) = '0') then -- TODO 3: -- FILLUP THE LRU UPDATION MECHANISM WHEN ISSUING TO EITHER INT QUE OR LW/SW QUE
-- Three cases to be considered here:
-- Case 1: when only int type instructions get ready
if (IssInt_Rdy = '1' and IssLsb_Rdy = '0') then
LRU_bit <= '0';
-- Case 2: when only lw/sw type instructions get ready
elsif (IssInt_Rdy = '0' and IssLsb_Rdy = '1') then
LRU_bit <= '1';
-- Case 3: when both int type and lw/sw instructions get ready
elsif (IssInt_Rdy = '1' and IssLsb_Rdy = '1') then
if (LRU_bit = '1') then --toggle LRU_bit
LRU_bit <= '0';
else
LRU_bit <= '1';
end if;
end if;
end if;
-- TODO 4: reserve CDB slot for issuing a div instruction -- 7 CLOCK LATENCY
if (IssDiv_Rdy = '1') then
CDB_Slot(5) <= '1';
end if;
-- TODO 5: reserve CDB slot for issuing a mult instruction -- 4 CLOCK LATENCY
if (CDB_Slot(3) = '0' and IssMul_Rdy = '1') then
CDB_Slot(2) <= '1';
end if;
-- NOTE: THE LATENCY CALCULATION IS INSIDE A CLOCKED PROCESS SO 1 CLOCK LATENCY WILL BE AUTOMATICALLY TAKEN CARE OF.
-- IN OTHER WORDS YOU NEED TO FIGURE OUT THAT IF YOU NEED TO HAVE A LATENCY OF "N" WHICH CDB REGISTER NEEDS TO BE UPDATED
-- IS IT REGISTER "N", REGISTER "N+1" OR REGISTER "N - 1 " ????
end if;
end process;
process(LRU_bit, IssLsb_Rdy, IssInt_Rdy, IssDiv_Rdy, IssMul_Rdy, Div_ExeRdy, CDB_Slot) -- TODO 6: GENERATE THE ISSUE SIGNALS
begin
-- FILL UP THE CODE FOR ISSUING EITHER LW/SW OR INT TYPE INSTRUCTION DEPENDING ON LRU BIT
-- MULTIPLE CASES NEED TO BE CONSIDERED SUCH AS WHEN ONLY ONE TYPE OF INSTRUCTION IS READY
-- OR WHEN BOTH TYPES OF INSTRUCTIONS ARE READY SIMULTANEOUSLY.
-- REFER TO THE THREE CASES MENTIONED IN THE SECTION "TODO 3"
if (IssInt_Rdy = '1' and IssLsb_Rdy = '0') then --Case 1
Iss_Int <= '1';
Iss_Lsb <= '0';
elsif (IssInt_Rdy = '0' and IssLsb_Rdy = '1') then --Case 2
Iss_Int <= '0';
Iss_Lsb <= '1';
elsif (IssInt_Rdy = '1' and IssLsb_Rdy = '1') then --Case 3
if(LRU_bit = '1') then
Iss_Int <= '0'; --should be switched?
Iss_Lsb <= '1';
else
Iss_Int <= '1';
Iss_Lsb <= '0';
end if;
else
Iss_Int <= '0';
Iss_Lsb <= '0';
end if;
-- FILL UP THE CODE TO ISSUE A DIV TYPE INSTRUCTION
if (IssDiv_Rdy = '1' and Div_ExeRdy = '1') then
Iss_Div <= '1';
else
Iss_Div <= '0';
end if;
-- FILL UP THE CODE TO ISSUE A MULT TYPE INSTRUCTION
if (IssMul_Rdy = '1') then -- and CDB_Slot(3) = '0') then
Iss_Mult <= '1';
else
Iss_Mult <= '0';
end if;
end process;
end Behavioral; |
--==========================================================================================================================
-- FILE NAME : issue_unit.vhd
-- DESCRIPTION : issue unit helps to issue one instruction at a time even when multiple instructions are ready to be issued.
-- the priority depends on LRU bit and also the latency of instruction, long latency instructions are given
-- priority , so the priority order is - div, mult, ( int type and lw/sw depending on LRU bit).
-- AUTHOR : PRASANJEET DAS, VAIBHAV DHOTRE
-- DATE : 6/17/10, 6/23/06
-- TASK : COMPLETE THE SIX TODO SECTIONS.
--===========================================================================================================================
-------------------------------------------
-- LIBRARY DECLARATION
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use work.tmslopkg.all
--ENTITY DECLARATION
entity issue_unit is
generic(
Resetb_ACTIVE_VALUE : std_logic := '0' -- ACTIVE LOW Resetb
);
port(
Clk : in std_logic;
Resetb : in std_logic;
-- ready signals from each of the queues
IssInt_Rdy : in std_logic;
IssMul_Rdy : in std_logic;
IssDiv_Rdy : in std_logic;
IssLsb_Rdy : in std_logic;
-- signal from the division execution unit to indicate that it is currently available
Div_ExeRdy : in std_logic;
--issue signals as acknowledgement from issue unit to each of the queues
Iss_Int : out std_logic;
Iss_Mult : out std_logic;
Iss_Div : out std_logic;
Iss_Lsb : out std_logic
);
end issue_unit;
-- ARCHITECTURE DECLARATION
architecture Behavioral of issue_unit is
signal CDB_Slot : std_logic_vector(5 downto 0); -- the CDB reservation register
signal LRU_bit : std_logic;
-- you can declare your own signals here
begin
--NOTE:
--================================================================================================================================================================================================
-- 1. simple approach to decide priority between int type and "lw/sw" type instructions
-- depending on the LRU bit issue the Least recently used instruction, use a LRU bit for the same which gets updated every time
-- and instruction is issued.
-- FOR SIMPLICITY ASSUME LRU BIT WHEN AN INT TYPE INSTRUCTION IS ISSUED IS "0" AND WHEN A LW/SW TYPE INSTRUCTION IS ISSUED IS "1"
-- PRECAUTION to be taken only issue the one whose corresponding issueque_ready signal is asserted ( = '1')
--2. issue mult insturction when the CDB_slot (3) is free and the corresponding issueque_ready signal is asserted (= '1') --remember the 4 clock latency
--3. issue div instruction when the Div_ExeRdy indicates that divider execution unit is ready and corresponding issueque_ready signal is asserted (= '1') -- remember the 7 clock latency
--4. don't forget to update the CDB register on every clock as per the required conditions.
--==================================================================================================================================================================================================
process(Resetb, Clk)
begin
if (Resetb = '0') then
-- TODO 1: INITIALIZE CDB and LRU Bit
CDB_Slot <= (others => '0');
LRU_bit <= '0';
elsif ( Clk'event and Clk = '1' ) then
--CDB_Slot <= -- TODO 2: COMPLETE THE SHIFT MECHANISM
CDB_Slot(5) <= '0'; --Iss_Div;
CDB_Slot(4) <= CDB_Slot(5);
CDB_Slot(3) <= CDB_Slot(4);
CDB_Slot(2) <= CDB_Slot(3); -- when (Iss_Mult = '0') else '1';
CDB_Slot(1) <= CDB_Slot(2);
CDB_Slot(0) <= CDB_Slot(1);
if (CDB_Slot(0) = '0') then -- TODO 3: -- FILLUP THE LRU UPDATION MECHANISM WHEN ISSUING TO EITHER INT QUE OR LW/SW QUE
-- Three cases to be considered here:
-- Case 1: when only int type instructions get ready
if (IssInt_Rdy = '1' and IssLsb_Rdy = '0') then
LRU_bit <= '0';
-- Case 2: when only lw/sw type instructions get ready
elsif (IssInt_Rdy = '0' and IssLsb_Rdy = '1') then
LRU_bit <= '1';
-- Case 3: when both int type and lw/sw instructions get ready
elsif (IssInt_Rdy = '1' and IssLsb_Rdy = '1') then
if (LRU_bit = '1') then --toggle LRU_bit
LRU_bit <= '0';
else
LRU_bit <= '1';
end if;
end if;
end if;
-- TODO 4: reserve CDB slot for issuing a div instruction -- 7 CLOCK LATENCY
if (IssDiv_Rdy = '1') then
CDB_Slot(5) <= '1';
end if;
-- TODO 5: reserve CDB slot for issuing a mult instruction -- 4 CLOCK LATENCY
if (CDB_Slot(3) = '0' and IssMul_Rdy = '1') then
CDB_Slot(2) <= '1';
end if;
-- NOTE: THE LATENCY CALCULATION IS INSIDE A CLOCKED PROCESS SO 1 CLOCK LATENCY WILL BE AUTOMATICALLY TAKEN CARE OF.
-- IN OTHER WORDS YOU NEED TO FIGURE OUT THAT IF YOU NEED TO HAVE A LATENCY OF "N" WHICH CDB REGISTER NEEDS TO BE UPDATED
-- IS IT REGISTER "N", REGISTER "N+1" OR REGISTER "N - 1 " ????
end if;
end process;
process(LRU_bit, IssLsb_Rdy, IssInt_Rdy, IssDiv_Rdy, IssMul_Rdy, Div_ExeRdy, CDB_Slot) -- TODO 6: GENERATE THE ISSUE SIGNALS
begin
-- FILL UP THE CODE FOR ISSUING EITHER LW/SW OR INT TYPE INSTRUCTION DEPENDING ON LRU BIT
-- MULTIPLE CASES NEED TO BE CONSIDERED SUCH AS WHEN ONLY ONE TYPE OF INSTRUCTION IS READY
-- OR WHEN BOTH TYPES OF INSTRUCTIONS ARE READY SIMULTANEOUSLY.
-- REFER TO THE THREE CASES MENTIONED IN THE SECTION "TODO 3"
if (IssInt_Rdy = '1' and IssLsb_Rdy = '0') then --Case 1
Iss_Int <= '1';
Iss_Lsb <= '0';
elsif (IssInt_Rdy = '0' and IssLsb_Rdy = '1') then --Case 2
Iss_Int <= '0';
Iss_Lsb <= '1';
elsif (IssInt_Rdy = '1' and IssLsb_Rdy = '1') then --Case 3
if(LRU_bit = '1') then
Iss_Int <= '0'; --should be switched?
Iss_Lsb <= '1';
else
Iss_Int <= '1';
Iss_Lsb <= '0';
end if;
else
Iss_Int <= '0';
Iss_Lsb <= '0';
end if;
-- FILL UP THE CODE TO ISSUE A DIV TYPE INSTRUCTION
if (IssDiv_Rdy = '1' and Div_ExeRdy = '1') then
Iss_Div <= '1';
else
Iss_Div <= '0';
end if;
-- FILL UP THE CODE TO ISSUE A MULT TYPE INSTRUCTION
if (IssMul_Rdy = '1') then -- and CDB_Slot(3) = '0') then
Iss_Mult <= '1';
else
Iss_Mult <= '0';
end if;
end process;
end Behavioral; |
----------------------------------------------------------------
-- Nombre : ROM.vhd
-- Descripcion : Memoria de programa del PIC
----------------------------------------------------------------
-- Version : 1.0
----------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.PIC_pkg.all;
entity ROM is
port (
Instruction : out std_logic_vector(11 downto 0); -- Instruction bus
Program_counter : in std_logic_vector(11 downto 0));
end ROM;
architecture AUTOMATIC of ROM is
constant W0 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W1 : std_logic_vector(11 downto 0) := X"003";
constant W2 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W3 : std_logic_vector(11 downto 0) := X"0FF";
constant W4 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPL;
constant W5 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W6 : std_logic_vector(11 downto 0) :=X"000";
constant W7 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_ACC;
constant W8 : std_logic_vector(11 downto 0) := X"000";
constant W9 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W10 : std_logic_vector(11 downto 0) := X"003";
constant W11 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W12 : std_logic_vector(11 downto 0) := X"000";
constant W13 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W14 : std_logic_vector(11 downto 0) := X"041";
constant W15 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W16 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W17 : std_logic_vector(11 downto 0) :=X"045";
constant W18 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W19 : std_logic_vector(11 downto 0) := X"049";
constant W20 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W21 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W22 : std_logic_vector(11 downto 0) :=X"02E";
constant W23 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W24 : std_logic_vector(11 downto 0) := X"054";
constant W25 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W26 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W27 : std_logic_vector(11 downto 0) :=X"05C";
constant W28 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W29 : std_logic_vector(11 downto 0) := X"053";
constant W30 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W31 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W32 : std_logic_vector(11 downto 0) :=X"07E";
constant W33 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W34 : std_logic_vector(11 downto 0) :=X"0D6";
constant W35 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_ACC;
constant W36 : std_logic_vector(11 downto 0) := X"04F";
constant W37 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W38 : std_logic_vector(11 downto 0) := X"004";
constant W39 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_ACC;
constant W40 : std_logic_vector(11 downto 0) := X"04B";
constant W41 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W42 : std_logic_vector(11 downto 0) := X"005";
constant W43 : std_logic_vector(11 downto 0) :=X"0" & TYPE_4 & "000000";
constant W44 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W45 : std_logic_vector(11 downto 0) :=X"000";
constant W46 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W47 : std_logic_vector(11 downto 0) := X"001";
constant W48 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ASCII2BIN;
constant W49 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_INDX;
constant W50 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W51 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W52 : std_logic_vector(11 downto 0) := X"007";
constant W53 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPG;
constant W54 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W55 : std_logic_vector(11 downto 0) :=X"0D6";
constant W56 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W57 : std_logic_vector(11 downto 0) := X"002";
constant W58 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ASCII2BIN;
constant W59 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W60 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W61 : std_logic_vector(11 downto 0) := X"001";
constant W62 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPG;
constant W63 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W64 : std_logic_vector(11 downto 0) :=X"0D6";
constant W65 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_INDXD_MEM;
constant W66 : std_logic_vector(11 downto 0) := X"010";
constant W67 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W68 : std_logic_vector(11 downto 0) :=X"023";
constant W69 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W70 : std_logic_vector(11 downto 0) := X"001";
constant W71 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ASCII2BIN;
constant W72 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W73 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_INDX;
constant W74 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W75 : std_logic_vector(11 downto 0) := X"0FF";
constant W76 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W77 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W78 : std_logic_vector(11 downto 0) :=X"0D6";
constant W79 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W80 : std_logic_vector(11 downto 0) := X"002";
constant W81 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ASCII2BIN;
constant W82 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W83 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W84 : std_logic_vector(11 downto 0) := X"009";
constant W85 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPG;
constant W86 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W87 : std_logic_vector(11 downto 0) :=X"0D6";
constant W88 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_INDXD_MEM;
constant W89 : std_logic_vector(11 downto 0) := X"020";
constant W90 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W91 : std_logic_vector(11 downto 0) :=X"023";
constant W92 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W93 : std_logic_vector(11 downto 0) := X"001";
constant W94 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ASCII2BIN;
constant W95 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W96 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W97 : std_logic_vector(11 downto 0) := X"002";
constant W98 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPG;
constant W99 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W100 : std_logic_vector(11 downto 0) :=X"0D6";
constant W101 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W102 : std_logic_vector(11 downto 0) := X"000";
constant W103 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ADD;
constant W104 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_SHIFTL;
constant W105 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_SHIFTL;
constant W106 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_SHIFTL;
constant W107 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_SHIFTL;
constant W108 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W109 : std_logic_vector(11 downto 0) := X"041";
constant W110 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W111 : std_logic_vector(11 downto 0) := X"002";
constant W112 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ASCII2BIN;
constant W113 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W114 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W115 : std_logic_vector(11 downto 0) := X"0FF";
constant W116 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W117 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W118 : std_logic_vector(11 downto 0) :=X"0D6";
constant W119 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_B;
constant W120 : std_logic_vector(11 downto 0) := X"041";
constant W121 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ADD;
constant W122 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W123 : std_logic_vector(11 downto 0) := X"031";
constant W124 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W125 : std_logic_vector(11 downto 0) :=X"023";
constant W126 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W127 : std_logic_vector(11 downto 0) := X"001";
constant W128 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W129 : std_logic_vector(11 downto 0) := X"041";
constant W130 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W131 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W132 : std_logic_vector(11 downto 0) :=X"091";
constant W133 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W134 : std_logic_vector(11 downto 0) := X"049";
constant W135 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W136 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W137 : std_logic_vector(11 downto 0) :=X"0A7";
constant W138 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W139 : std_logic_vector(11 downto 0) := X"054";
constant W140 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPE;
constant W141 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W142 : std_logic_vector(11 downto 0) :=X"0BD";
constant W143 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W144 : std_logic_vector(11 downto 0) :=X"0D6";
constant W145 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W146 : std_logic_vector(11 downto 0) := X"002";
constant W147 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ASCII2BIN;
constant W148 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W149 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_INDX;
constant W150 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W151 : std_logic_vector(11 downto 0) := X"009";
constant W152 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPG;
constant W153 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W154 : std_logic_vector(11 downto 0) :=X"0D6";
constant W155 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_INDXD_MEM & DST_A;
constant W156 : std_logic_vector(11 downto 0) := X"020";
constant W157 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_BIN2ASCII;
constant W158 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W159 : std_logic_vector(11 downto 0) := X"005";
constant W160 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_ACC;
constant W161 : std_logic_vector(11 downto 0) := X"041";
constant W162 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W163 : std_logic_vector(11 downto 0) := X"004";
constant W164 : std_logic_vector(11 downto 0) :=X"0" & TYPE_4 & "000000";
constant W165 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W166 : std_logic_vector(11 downto 0) :=X"000";
constant W167 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W168 : std_logic_vector(11 downto 0) := X"002";
constant W169 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_ASCII2BIN;
constant W170 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W171 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_INDX;
constant W172 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W173 : std_logic_vector(11 downto 0) := X"007";
constant W174 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_CMPG;
constant W175 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_COND;
constant W176 : std_logic_vector(11 downto 0) :=X"0D6";
constant W177 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_INDXD_MEM & DST_A;
constant W178 : std_logic_vector(11 downto 0) := X"010";
constant W179 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_BIN2ASCII;
constant W180 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W181 : std_logic_vector(11 downto 0) := X"005";
constant W182 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_ACC;
constant W183 : std_logic_vector(11 downto 0) := X"053";
constant W184 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W185 : std_logic_vector(11 downto 0) := X"004";
constant W186 : std_logic_vector(11 downto 0) :=X"0" & TYPE_4 & "000000";
constant W187 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W188 : std_logic_vector(11 downto 0) :=X"000";
constant W189 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W190 : std_logic_vector(11 downto 0) := X"031";
constant W191 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W192 : std_logic_vector(11 downto 0) :="000011110000";
constant W193 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_AND;
constant W194 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_SHIFTR;
constant W195 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_SHIFTR;
constant W196 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_SHIFTR;
constant W197 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_SHIFTR;
constant W198 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W199 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_BIN2ASCII;
constant W200 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W201 : std_logic_vector(11 downto 0) := X"004";
constant W202 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_MEM & DST_A;
constant W203 : std_logic_vector(11 downto 0) := X"031";
constant W204 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_B;
constant W205 : std_logic_vector(11 downto 0) :="000000001111";
constant W206 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_AND;
constant W207 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_ACC & DST_A;
constant W208 : std_logic_vector(11 downto 0) :=X"0" & TYPE_1 & ALU_BIN2ASCII;
constant W209 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W210 : std_logic_vector(11 downto 0) := X"005";
constant W211 : std_logic_vector(11 downto 0) :=X"0" & TYPE_4 & "000000";
constant W212 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W213 : std_logic_vector(11 downto 0) :=X"000";
constant W214 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_ACC;
constant W215 : std_logic_vector(11 downto 0) := X"045";
constant W216 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W217 : std_logic_vector(11 downto 0) := X"004";
constant W218 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & LD & SRC_CONSTANT & DST_ACC;
constant W219 : std_logic_vector(11 downto 0) := X"052";
constant W220 : std_logic_vector(11 downto 0) :=X"0" & TYPE_3 & WR & SRC_ACC & DST_MEM;
constant W221 : std_logic_vector(11 downto 0) := X"005";
constant W222 : std_logic_vector(11 downto 0) :=X"0" & TYPE_4 & "000000";
constant W223 : std_logic_vector(11 downto 0) :=X"0" & TYPE_2 & JMP_UNCOND;
constant W224 : std_logic_vector(11 downto 0) :=X"000";
begin -- AUTOMATIC
with Program_counter select
Instruction <=
W0 when X"000",
W1 when X"001",
W2 when X"002",
W3 when X"003",
W4 when X"004",
W5 when X"005",
W6 when X"006",
W7 when X"007",
W8 when X"008",
W9 when X"009",
W10 when X"00A",
W11 when X"00B",
W12 when X"00C",
W13 when X"00D",
W14 when X"00E",
W15 when X"00F",
W16 when X"010",
W17 when X"011",
W18 when X"012",
W19 when X"013",
W20 when X"014",
W21 when X"015",
W22 when X"016",
W23 when X"017",
W24 when X"018",
W25 when X"019",
W26 when X"01A",
W27 when X"01B",
W28 when X"01C",
W29 when X"01D",
W30 when X"01E",
W31 when X"01F",
W32 when X"020",
W33 when X"021",
W34 when X"022",
W35 when X"023",
W36 when X"024",
W37 when X"025",
W38 when X"026",
W39 when X"027",
W40 when X"028",
W41 when X"029",
W42 when X"02A",
W43 when X"02B",
W44 when X"02C",
W45 when X"02D",
W46 when X"02E",
W47 when X"02F",
W48 when X"030",
W49 when X"031",
W50 when X"032",
W51 when X"033",
W52 when X"034",
W53 when X"035",
W54 when X"036",
W55 when X"037",
W56 when X"038",
W57 when X"039",
W58 when X"03A",
W59 when X"03B",
W60 when X"03C",
W61 when X"03D",
W62 when X"03E",
W63 when X"03F",
W64 when X"040",
W65 when X"041",
W66 when X"042",
W67 when X"043",
W68 when X"044",
W69 when X"045",
W70 when X"046",
W71 when X"047",
W72 when X"048",
W73 when X"049",
W74 when X"04A",
W75 when X"04B",
W76 when X"04C",
W77 when X"04D",
W78 when X"04E",
W79 when X"04F",
W80 when X"050",
W81 when X"051",
W82 when X"052",
W83 when X"053",
W84 when X"054",
W85 when X"055",
W86 when X"056",
W87 when X"057",
W88 when X"058",
W89 when X"059",
W90 when X"05A",
W91 when X"05B",
W92 when X"05C",
W93 when X"05D",
W94 when X"05E",
W95 when X"05F",
W96 when X"060",
W97 when X"061",
W98 when X"062",
W99 when X"063",
W100 when X"064",
W101 when X"065",
W102 when X"066",
W103 when X"067",
W104 when X"068",
W105 when X"069",
W106 when X"06A",
W107 when X"06B",
W108 when X"06C",
W109 when X"06D",
W110 when X"06E",
W111 when X"06F",
W112 when X"070",
W113 when X"071",
W114 when X"072",
W115 when X"073",
W116 when X"074",
W117 when X"075",
W118 when X"076",
W119 when X"077",
W120 when X"078",
W121 when X"079",
W122 when X"07A",
W123 when X"07B",
W124 when X"07C",
W125 when X"07D",
W126 when X"07E",
W127 when X"07F",
W128 when X"080",
W129 when X"081",
W130 when X"082",
W131 when X"083",
W132 when X"084",
W133 when X"085",
W134 when X"086",
W135 when X"087",
W136 when X"088",
W137 when X"089",
W138 when X"08A",
W139 when X"08B",
W140 when X"08C",
W141 when X"08D",
W142 when X"08E",
W143 when X"08F",
W144 when X"090",
W145 when X"091",
W146 when X"092",
W147 when X"093",
W148 when X"094",
W149 when X"095",
W150 when X"096",
W151 when X"097",
W152 when X"098",
W153 when X"099",
W154 when X"09A",
W155 when X"09B",
W156 when X"09C",
W157 when X"09D",
W158 when X"09E",
W159 when X"09F",
W160 when X"0A0",
W161 when X"0A1",
W162 when X"0A2",
W163 when X"0A3",
W164 when X"0A4",
W165 when X"0A5",
W166 when X"0A6",
W167 when X"0A7",
W168 when X"0A8",
W169 when X"0A9",
W170 when X"0AA",
W171 when X"0AB",
W172 when X"0AC",
W173 when X"0AD",
W174 when X"0AE",
W175 when X"0AF",
W176 when X"0B0",
W177 when X"0B1",
W178 when X"0B2",
W179 when X"0B3",
W180 when X"0B4",
W181 when X"0B5",
W182 when X"0B6",
W183 when X"0B7",
W184 when X"0B8",
W185 when X"0B9",
W186 when X"0BA",
W187 when X"0BB",
W188 when X"0BC",
W189 when X"0BD",
W190 when X"0BE",
W191 when X"0BF",
W192 when X"0C0",
W193 when X"0C1",
W194 when X"0C2",
W195 when X"0C3",
W196 when X"0C4",
W197 when X"0C5",
W198 when X"0C6",
W199 when X"0C7",
W200 when X"0C8",
W201 when X"0C9",
W202 when X"0CA",
W203 when X"0CB",
W204 when X"0CC",
W205 when X"0CD",
W206 when X"0CE",
W207 when X"0CF",
W208 when X"0D0",
W209 when X"0D1",
W210 when X"0D2",
W211 when X"0D3",
W212 when X"0D4",
W213 when X"0D5",
W214 when X"0D6",
W215 when X"0D7",
W216 when X"0D8",
W217 when X"0D9",
W218 when X"0DA",
W219 when X"0DB",
W220 when X"0DC",
W221 when X"0DD",
W222 when X"0DE",
W223 when X"0DF",
W224 when X"0E0",
X"0" & TYPE_1 & ALU_ADD when others;
end AUTOMATIC;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_test is end;
architecture arch_tb of tb_test is
-- signal reset_s, clk_s : std_logic;
signal i_s : integer := -1;
-- signal j_s : integer := -2;
-- Here, as it should, an error will be raised during compilation
-- signal u_s : unsigned(7 downto 0) := to_unsigned(-1, 8);
--
signal v_s : unsigned(7 downto 0);
-- signal w_s : unsigned(7 downto 0);
begin
-- Here, as it should, a bound check failure will be raised during simulation
-- w_s <= to_unsigned(j_s, 8);
--
-- Here it won't have any error during simulation, but it should
v_s <= to_unsigned(i_s, 8);
--
end architecture arch_tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_test is end;
architecture arch_tb of tb_test is
-- signal reset_s, clk_s : std_logic;
signal i_s : integer := -1;
-- signal j_s : integer := -2;
-- Here, as it should, an error will be raised during compilation
-- signal u_s : unsigned(7 downto 0) := to_unsigned(-1, 8);
--
signal v_s : unsigned(7 downto 0);
-- signal w_s : unsigned(7 downto 0);
begin
-- Here, as it should, a bound check failure will be raised during simulation
-- w_s <= to_unsigned(j_s, 8);
--
-- Here it won't have any error during simulation, but it should
v_s <= to_unsigned(i_s, 8);
--
end architecture arch_tb;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_test is end;
architecture arch_tb of tb_test is
-- signal reset_s, clk_s : std_logic;
signal i_s : integer := -1;
-- signal j_s : integer := -2;
-- Here, as it should, an error will be raised during compilation
-- signal u_s : unsigned(7 downto 0) := to_unsigned(-1, 8);
--
signal v_s : unsigned(7 downto 0);
-- signal w_s : unsigned(7 downto 0);
begin
-- Here, as it should, a bound check failure will be raised during simulation
-- w_s <= to_unsigned(j_s, 8);
--
-- Here it won't have any error during simulation, but it should
v_s <= to_unsigned(i_s, 8);
--
end architecture arch_tb;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex2;
constant CFG_MEMTECH : integer := virtex2;
constant CFG_PADTECH : integer := virtex2;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex2;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (4);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0034#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000006#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- PCI interface
constant CFG_PCI : integer := 0;
constant CFG_PCIVID : integer := 16#0#;
constant CFG_PCIDID : integer := 16#0#;
constant CFG_PCIDEPTH : integer := 8;
constant CFG_PCI_MTF : integer := 1;
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 1;
constant CFG_UART2_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#00FE#;
constant CFG_GRGPIO_WIDTH : integer := (16);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 20:37:26 11/15/2015
-- Design Name:
-- Module Name: CPU_TOP - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.Vcomponents.all;
entity CPU_TOP is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
RAM1ADDR : out STD_LOGIC_VECTOR (17 downto 0);
RAM1DATA : inout STD_LOGIC_VECTOR (15 downto 0);
RAM1EN : out STD_LOGIC;
RAM1OE : out STD_LOGIC;
RAM1RW : out STD_LOGIC;
RAM2ADDR : out STD_LOGIC_VECTOR (17 downto 0);
RAM2DATA : inout STD_LOGIC_VECTOR (15 downto 0);
RAM2EN : out STD_LOGIC;
RAM2OE : out STD_LOGIC;
RAM2RW : out STD_LOGIC;
-- Serial Port
SERIAL_DATA_READY : in STD_LOGIC;
SERIAL_RDN : out STD_LOGIC;
SERIAL_TBRE : in STD_LOGIC;
SERIAL_TSRE : in STD_LOGIC;
SERIAL_WRN : out STD_LOGIC;
-- For Debug
LED : out STD_LOGIC_VECTOR (15 downto 0);
SW : in STD_LOGIC_VECTOR (15 downto 0);
DLED_RIGHT : out STD_LOGIC_VECTOR (6 downto 0)
);
end CPU_TOP;
architecture Behavioral of CPU_TOP is
-- Universal component
component ClockDiv
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
clk_2t : out STD_LOGIC;
clk_4t : out STD_LOGIC
);
end component;
signal clock_2t : STD_LOGIC;
signal clock_4t : STD_LOGIC;
component TwoInMuxer_16bit
Port ( input1 : in STD_LOGIC_VECTOR (15 downto 0);
input2 : in STD_LOGIC_VECTOR (15 downto 0);
opcode : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component FourInMuxer_16bit
Port ( input1 : in STD_LOGIC_VECTOR (15 downto 0);
input2 : in STD_LOGIC_VECTOR (15 downto 0);
input3 : in STD_LOGIC_VECTOR (15 downto 0);
input4 : in STD_LOGIC_VECTOR (15 downto 0);
opcode : in STD_LOGIC_VECTOR (1 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0));
end component;
component BubbleUnit
Port ( RegOpA : in STD_LOGIC_VECTOR (3 downto 0);
RegOpB : in STD_LOGIC_VECTOR (3 downto 0);
RegWE_EXE : in STD_LOGIC;
RegDest_EXE : in STD_LOGIC_VECTOR (3 downto 0);
RegWE_MEM: in STD_LOGIC;
RegDest_MEM : in STD_LOGIC_VECTOR (3 downto 0);
RegMemDIn_EXE : in STD_LOGIC_VECTOR (3 downto 0);
MemRead_EXE : in STD_LOGIC;
MemWrite_EXE : in STD_LOGIC;
MemRead_MEM : in STD_LOGIC;
MemWrite_MEM : in STD_LOGIC;
MemAddr : in STD_LOGIC_VECTOR (15 downto 0);
pc_sel: in STD_LOGIC_VECTOR (1 downto 0);
CReg : in STD_LOGIC;
CRegA : in STD_LOGIC_VECTOR (3 downto 0);
CRegB : in STD_LOGIC_VECTOR (3 downto 0);
SerialFinish : in STD_LOGIC;
pc_stall : out STD_LOGIC;
InstAddrSel : out STD_LOGIC;
InstMemRead : out STD_LOGIC;
InstMemWrite : out STD_LOGIC;
Mem_Result_Sel : out STD_LOGIC;
IF_ID_stall : out STD_LOGIC;
ID_EXE_stall : out STD_LOGIC;
EXE_MEM_stall : out STD_LOGIC;
IF_ID_clear: out STD_LOGIC;
ID_EXE_clear : out STD_LOGIC;
EXE_MEM_clear: out STD_LOGIC
);
end component;
signal IF_ID_REG_STALL : STD_LOGIC;
signal IF_ID_REG_CLEAR : STD_LOGIC;
signal ID_EXE_REG_STALL : STD_LOGIC;
signal ID_EXE_REG_CLEAR : STD_LOGIC;
signal EXE_MEM_REG_STALL : STD_LOGIC;
signal EXE_MEM_REG_CLEAR : STD_LOGIC;
component ForwardingUnit
Port ( RegOpA : in STD_LOGIC_VECTOR (3 downto 0);
RegOpB : in STD_LOGIC_VECTOR (3 downto 0);
RegWE_MEM: in STD_LOGIC;
RegDest_MEM : in STD_LOGIC_VECTOR (3 downto 0);
RegWE_WB : in STD_LOGIC;
RegDest_WB : STD_LOGIC_VECTOR (3 downto 0);
MemRead_EXE : in STD_LOGIC;
MemRead_WB : in STD_LOGIC;
CReg : in STD_LOGIC;
CRegA : in STD_LOGIC_VECTOR (3 downto 0);
CRegB : in STD_LOGIC_VECTOR (3 downto 0);
RegMemDIn_EXE : in STD_LOGIC_VECTOR (3 downto 0);
RegMemDIn_MEM : in STD_LOGIC_VECTOR (3 downto 0);
RegAValSel : out STD_LOGIC;
RegBValSel : out STD_LOGIC;
RegRAValSel : out STD_LOGIC;
OperandASel : out STD_LOGIC_VECTOR (1 downto 0);
OperandBSel : out STD_LOGIC_VECTOR (1 downto 0);
MemDInSel_EXE : out STD_LOGIC_VECTOR (1 downto 0);
MemDInSel_MEM : out STD_LOGIC
);
end component;
-- IF Section
component PC_REG
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
stall : in STD_LOGIC;
PC_in : in STD_LOGIC_VECTOR (15 downto 0);
PC_out : out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
component PCAdder
Port ( A : in STD_LOGIC_VECTOR (15 downto 0);
B : in STD_LOGIC_VECTOR (15 downto 0);
result : out STD_LOGIC_VECTOR (15 downto 0));
end component;
COMPONENT InstMemoryControl
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
MemRead : in STD_LOGIC;
MemWrite: in STD_LOGIC;
MemAddr : in STD_LOGIC_VECTOR (15 downto 0);
MemData : in STD_LOGIC_VECTOR (15 downto 0);
MemOut : out STD_LOGIC_VECTOR (15 downto 0);
RAM2Addr : out STD_LOGIC_VECTOR (17 downto 0);
RAM2Data : inout STD_LOGIC_VECTOR (15 downto 0);
RAM2EN : out STD_LOGIC;
RAM2OE : out STD_LOGIC;
RAM2RW : out STD_LOGIC
);
end COMPONENT;
component IF_ID_REG
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
pc_in : in STD_LOGIC_VECTOR (15 downto 0);
inst_in : in STD_LOGIC_VECTOR (15 downto 0);
stall : in STD_LOGIC;
clear : in STD_LOGIC;
pc_out : out STD_LOGIC_VECTOR (15 downto 0);
inst_out : out STD_LOGIC_VECTOR (15 downto 0);
rx : out STD_LOGIC_VECTOR (3 downto 0);
ry : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;
-- PC Register
signal PC_REG_IN : STD_LOGIC_VECTOR (15 downto 0);
signal PC_REG_OUT : STD_LOGIC_VECTOR (15 downto 0);
signal PC_REG_STALL : STD_LOGIC;
-- Instruction Selector
signal INST_ADDR_OUT : STD_LOGIC_VECTOR (15 downto 0);
signal INST_ADDR_SEL : STD_LOGIC;
-- Instruction Memory
signal INST_MEM_READ : STD_LOGIC;
signal INST_MEM_WRITE : STD_LOGIC;
signal INST_MEM_OUT : STD_LOGIC_VECTOR (15 downto 0);
-- PC Incr & PC Selector
signal PC_INCR_OUT : STD_LOGIC_VECTOR (15 downto 0);
-- signal PC_JUMP : STD_LOGIC_VECTOR (15 downto 0);
-- signal PC_SEL : STD_LOGIC_VECTOR (1 downto 0);
signal PC_INCR : STD_LOGIC_VECTOR (15 downto 0) := ( 0 => '1', others => '0');
-- IF/ID Register
-- ID Section
COMPONENT InstDecoder
PORT(
pc : IN std_logic_vector(15 downto 0);
inst : IN std_logic_vector(15 downto 0);
RegAVal : IN std_logic_vector(15 downto 0);
RegBVal : IN std_logic_vector(15 downto 0);
RAVal : IN std_logic_vector(15 downto 0);
SPVal : IN std_logic_vector(15 downto 0);
IHVal : IN std_logic_vector(15 downto 0);
pc_imm : OUT std_logic_vector(15 downto 0);
pc_sel : OUT std_logic_vector(1 downto 0);
T_in : in STD_LOGIC;
T_out : out STD_LOGIC;
CReg : OUT std_logic;
CRegA : OUT std_logic_vector(3 downto 0);
CRegB : OUT std_logic_vector(3 downto 0);
RegWE : OUT std_logic;
RegDest : OUT std_logic_vector(3 downto 0);
MemRd : OUT std_logic;
MemDIn : OUT std_logic_vector(15 downto 0);
RegMemDIn : out STD_LOGIC_VECTOR (3 downto 0);
MemWE : OUT std_logic;
opcode : OUT std_logic_vector(3 downto 0);
RegOpA : OUT std_logic_vector(3 downto 0);
RegOpB : OUT std_logic_vector(3 downto 0);
operandA : OUT std_logic_vector(15 downto 0);
operandB : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT T_REG
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
T_in : in STD_LOGIC;
T_out : out STD_LOGIC
);
END COMPONENT;
COMPONENT Register_Files
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
ASel : in STD_LOGIC_VECTOR (3 downto 0);
BSel : in STD_LOGIC_VECTOR (3 downto 0);
WSel : in STD_LOGIC_VECTOR (3 downto 0);
WE : in STD_LOGIC;
WVal : in STD_LOGIC_VECTOR (15 downto 0);
AVal : out STD_LOGIC_VECTOR (15 downto 0);
BVal : out STD_LOGIC_VECTOR (15 downto 0);
RAVal : out STD_LOGIC_VECTOR (15 downto 0);
SPVal : out STD_LOGIC_VECTOR (15 downto 0);
IHVal : out STD_LOGIC_VECTOR (15 downto 0)
);
end COMPONENT;
COMPONENT ID_EXE_REG
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
clear : in STD_LOGIC;
stall : in STD_LOGIC;
RegWE_in : in STD_LOGIC;
RegDest_in : in STD_LOGIC_VECTOR (3 downto 0);
MemRd_in : in STD_LOGIC;
MemWE_in : in STD_LOGIC;
MemDIn_in : in STD_LOGIC_VECTOR (15 downto 0);
opcode_in : in STD_LOGIC_VECTOR (3 downto 0);
operandA_in : in STD_LOGIC_VECTOR (15 downto 0);
operandB_in : in STD_LOGIC_VECTOR (15 downto 0);
RegOpA_in : in STD_LOGIC_VECTOR (3 downto 0);
RegOpB_in : in STD_LOGIC_VECTOR (3 downto 0);
RegMemDIn_in : in STD_LOGIC_VECTOR (3 downto 0);
RegWE_out : out STD_LOGIC;
RegDest_out : out STD_LOGIC_VECTOR (3 downto 0);
MemRd_out : out STD_LOGIC;
MemWE_out : out STD_LOGIC;
MemDIn_out : out STD_LOGIC_VECTOR (15 downto 0);
opcode_out : out STD_LOGIC_VECTOR (3 downto 0);
operandA_out : out STD_LOGIC_VECTOR (15 downto 0);
operandB_out : out STD_LOGIC_VECTOR (15 downto 0);
RegOpA_out : out STD_LOGIC_VECTOR (3 downto 0);
RegOpB_out : out STD_LOGIC_VECTOR (3 downto 0);
RegMemDIn_out : out STD_LOGIC_VECTOR (3 downto 0)
);
end COMPONENT;
-- IF/ID Register Out
signal IF_ID_PC : STD_LOGIC_VECTOR (15 downto 0);
signal IF_ID_INST : STD_LOGIC_VECTOR (15 downto 0);
signal IF_ID_REGX : STD_LOGIC_VECTOR (3 downto 0);
signal IF_ID_REGY : STD_LOGIC_VECTOR (3 downto 0);
-- T Register & Instruction Decoder
signal T_REG_OUT : STD_LOGIC;
signal T_REG_IN : STD_LOGIC;
signal Decoder_PC_Imm: STD_LOGIC_VECTOR (15 downto 0);
signal Decoder_PC_Sel : STD_LOGIC_VECTOR (1 downto 0);
signal Decoder_RegDest : STD_LOGIC_VECTOR (3 downto 0);
signal Decoder_RegWrite : STD_LOGIC;
signal Decoder_MemRead : STD_LOGIC;
signal Decoder_MemDIn : STD_LOGIC_VECTOR (15 downto 0);
signal Decoder_RegMemDIn : STD_LOGIC_VECTOR (3 downto 0);
signal Decoder_MemWrite : STD_LOGIC;
signal Decoder_OpCode : STD_LOGIC_VECTOR (3 downto 0);
signal Decoder_OperandA : STD_LOGIC_VECTOR (15 downto 0);
signal Decoder_OperandB : STD_LOGIC_VECTOR (15 downto 0);
signal Decoder_RegOpA : STD_LOGIC_VECTOR (3 downto 0);
signal Decoder_RegOpB : STD_LOGIC_VECTOR (3 downto 0);
signal Decoder_CReg : STD_LOGIC;
signal Decoder_CRegA : STD_LOGIC_VECTOR (3 downto 0);
signal Decoder_CRegB : STD_LOGIC_VECTOR (3 downto 0);
-- Register Files
signal Regs_RegAVal : STD_LOGIC_VECTOR (15 downto 0);
signal Regs_RegBVal : STD_LOGIC_VECTOR (15 downto 0);
signal Regs_RAVal : STD_LOGIC_VECTOR (15 downto 0);
signal Regs_SPVal : STD_LOGIC_VECTOR (15 downto 0);
signal Regs_IHVal : STD_LOGIC_VECTOR (15 downto 0);
-- PC Adder
signal PC_JUMP_ADDR : STD_LOGIC_VECTOR (15 downto 0);
-- EXE Section
COMPONENT ALU
Port ( op : in STD_LOGIC_VECTOR (3 downto 0);
A : in STD_LOGIC_VECTOR (15 downto 0);
B : in STD_LOGIC_VECTOR (15 downto 0);
result : out STD_LOGIC_VECTOR (15 downto 0));
end COMPONENT;
COMPONENT EXE_MEM_REG
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
clear : in STD_LOGIC;
stall : in STD_LOGIC;
RegWE_in : in STD_LOGIC;
RegDest_in : in STD_LOGIC_VECTOR (3 downto 0);
RegMemDIn_in : in STD_LOGIC_VECTOR (3 downto 0);
MemRd_in : in STD_LOGIC;
MemWE_in : in STD_LOGIC;
MemDIn_in : in STD_LOGIC_VECTOR (15 downto 0);
ALUout_in : in STD_LOGIC_VECTOR (15 downto 0);
RegWE_out : out STD_LOGIC;
RegDest_out : out STD_LOGIC_VECTOR (3 downto 0);
RegMemDIn_out : out STD_LOGIC_VECTOR (3 downto 0);
MemRd_out : out STD_LOGIC;
MemWE_out : out STD_LOGIC;
MemDIn_out : out STD_LOGIC_VECTOR (15 downto 0);
ALUout_out : out STD_LOGIC_VECTOR (15 downto 0)
);
end COMPONENT;
-- ID/EXE Register
signal ID_EXE_RegWrite : STD_LOGIC;
signal ID_EXE_RegDest : STD_LOGIC_VECTOR (3 downto 0);
signal ID_EXE_MemRead : STD_LOGIC;
signal ID_EXE_MemDIn : STD_LOGIC_VECTOR (15 downto 0);
signal ID_EXE_MemWrite : STD_LOGIC;
signal ID_EXE_RegMemDIn : STD_LOGIC_VECTOR (3 downto 0);
signal ID_EXE_OpCode : STD_LOGIC_VECTOR (3 downto 0);
signal ID_EXE_OperandA : STD_LOGIC_VECTOR (15 downto 0);
signal ID_EXE_OperandB : STD_LOGIC_VECTOR (15 downto 0);
signal ID_EXE_RegOpA : STD_LOGIC_VECTOR (3 downto 0);
signal ID_EXE_RegOpB : STD_LOGIC_VECTOR (3 downto 0);
-- Operand A Selector
signal OpA_MUX_OUT : STD_LOGIC_VECTOR (15 downto 0);
-- Operand B Selector
signal OpB_MUX_OUT : STD_LOGIC_VECTOR (15 downto 0);
-- ALU
signal ALU_RESULT : STD_LOGIC_VECTOR (15 downto 0);
-- EXE/MEM Register
signal MemDIn_MUX_OUT : STD_LOGIC_VECTOR (15 downto 0);
-- Forwarding Unit
signal OpA_MUX_SEL : STD_LOGIC_VECTOR (1 downto 0);
signal OpB_MUX_SEL : STD_LOGIC_VECTOR (1 downto 0);
signal RegRA_MUX_SEL : STD_LOGIC;
signal RegAVal_MUX_SEL : STD_LOGIC;
signal RegBVal_MUX_SEL : STD_LOGIC;
signal EXE_MemDIn_MUX_SEL : STD_LOGIC_VECTOR (1 downto 0);
signal MEM_MemDIn_MUX_SEL : STD_LOGIC;
signal RegAVal_MUX_OUT : STD_LOGIC_VECTOR (15 downto 0);
signal RegBVal_MUX_OUT : STD_LOGIC_VECTOR (15 downto 0);
signal RegRA_MUX_OUT : STD_LOGIC_VECTOR (15 downto 0);
-- MEM Section
COMPONENT DataMemoryControl
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
MemRead : in STD_LOGIC;
MemWrite: in STD_LOGIC;
MemAddr : in STD_LOGIC_VECTOR (15 downto 0);
MemData : in STD_LOGIC_VECTOR (15 downto 0);
MemOut : out STD_LOGIC_VECTOR (15 downto 0);
SerialFinish : out STD_LOGIC;
RAM1Addr : out STD_LOGIC_VECTOR (17 downto 0);
RAM1Data : inout STD_LOGIC_VECTOR (15 downto 0);
RAM1EN : out STD_LOGIC;
RAM1OE : out STD_LOGIC;
RAM1RW : out STD_LOGIC;
Serial_dataready : in STD_LOGIC;
Serial_rdn : out STD_LOGIC;
Serial_tbre : in STD_LOGIC;
Serial_tsre : in STD_LOGIC;
Serial_wrn : out STD_LOGIC;
DLED_Right : out STD_LOGIC_VECTOR (6 downto 0)
);
end COMPONENT;
COMPONENT MEM_WB_REG is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
RegWE_in : in STD_LOGIC;
RegDest_in : in STD_LOGIC_VECTOR (3 downto 0);
RegWriteVal_in : in STD_LOGIC_VECTOR (15 downto 0);
MemRd_in : in STD_LOGIC;
RegWE_out : out STD_LOGIC;
RegDest_out : out STD_LOGIC_VECTOR (3 downto 0);
RegWriteVal_out : out STD_LOGIC_VECTOR (15 downto 0);
MemRd_out : out STD_LOGIC
);
end COMPONENT;
-- EXE/MEM Register
signal EXE_MEM_RegWrite : STD_LOGIC;
signal EXE_MEM_RegDest : STD_LOGIC_VECTOR (3 downto 0);
signal EXE_MEM_RegMemDIn : STD_LOGIC_VECTOR (3 downto 0);
signal EXE_MEM_MemRead : STD_LOGIC;
signal EXE_MEM_MemDIn : STD_LOGIC_VECTOR (15 downto 0);
signal EXE_MEM_MemWrite : STD_LOGIC;
signal EXE_MEM_ALUOUT : STD_LOGIC_VECTOR (15 downto 0);
-- Data Memory & Serial Port
signal MEM_MemDIn_MUX_OUT : STD_LOGIC_VECTOR (15 downto 0);
signal DATA_MEM_OUT : STD_LOGIC_VECTOR (15 downto 0);
signal DATA_MEM_MUX_OUT : STD_LOGIC_VECTOR (15 downto 0);
signal MEM_RESULT_MUX_OUT : STD_LOGIC_VECTOR (15 downto 0);
signal MEM_RESULT_SEL : STD_LOGIC;
signal DATA_MEM_SERIAL_FINISH : STD_LOGIC;
-- WB Section
-- MEM/WB Register
signal MEM_WB_RegWrite : STD_LOGIC;
signal MEM_WB_RegDest : STD_LOGIC_VECTOR (3 downto 0);
signal MEM_WB_RegWriteVal : STD_LOGIC_VECTOR (15 downto 0);
signal MEM_WB_MemRead : STD_LOGIC;
begin
-- Universal
--LED <= ALU_RESULT;
LED <=
PC_REG_OUT when (SW = "0000000000000000") else
INST_ADDR_OUT when (SW = "0000000000000001") else
INST_MEM_OUT when (SW = "0000000000000010") else
Decoder_PC_Imm when (SW = "0000000000000011") else
PC_JUMP_ADDR when (SW = "0000000000000100") else
PC_REG_IN when (SW = "0000000000000101") else
IF_ID_PC when (SW = "0000000000010000") else
IF_ID_INST when (SW = "0000000000010001") else
"00000000" & IF_ID_REGX & IF_ID_REGY when (SW = "0000000000011001") else
(PC_REG_STALL & INST_ADDR_SEL & IF_ID_REG_STALL & IF_ID_REG_CLEAR
& ID_EXE_REG_STALL & ID_EXE_REG_CLEAR
& EXE_MEM_REG_STALL & EXE_MEM_REG_CLEAR & "00000000") when (SW = "0000000000011011") else
Decoder_OperandA when (SW = "0000000000010010") else
Decoder_OperandB when (SW = "0000000000010011") else
Decoder_RegOpA & Decoder_RegOpB & Decoder_CRegA & Decoder_CRegB when (SW = "0000000000010111") else
Decoder_RegDest & Decoder_RegWrite & Decoder_CReg & Decoder_MemRead & Decoder_MemWrite
& Decoder_PC_Sel & RegAVal_MUX_SEL & RegBVal_MUX_SEL & "0000" when (SW = "0000000000010110") else
RegAVal_MUX_OUT when (SW = "0000000000011110") else
RegBVal_MUX_OUT when (SW = "0000000000011100") else
ALU_RESULT when (SW = "0000000000100000") else
OpA_MUX_SEL & OpB_MUX_SEL & EXE_MemDIn_MUX_SEL & ID_EXE_RegOpA & ID_EXE_RegOpB & "00" when (SW = "0000000000100001") else
ID_EXE_OpCode & ID_EXE_MemRead & ID_EXE_MemWrite & ID_EXE_RegWrite & ID_EXE_RegDest & "00000" when (SW = "0000000000100011") else
ID_EXE_MemDIn when (SW = "0000000000100111") else
ID_EXE_RegMemDIn & "000000000000" when (SW = "0000000000100110") else
EXE_MEM_RegWrite & EXE_MEM_RegDest & EXE_MEM_MemRead & EXE_MEM_MemWrite
& SERIAL_DATA_READY & SERIAL_TBRE & SERIAL_TSRE & DATA_MEM_SERIAL_FINISH & "00000" when (SW = "0000000001000001") else
DATA_MEM_OUT when (SW = "0000000001000011") else
DATA_MEM_MUX_OUT when (SW = "0000000001000010") else
MEM_MemDIn_MUX_OUT when (SW = "0000000001000111") else
MEM_WB_RegWriteVal when (SW = "0000000010000000") else
MEM_WB_RegDest & MEM_WB_RegWrite & "00000000000" when (SW = "0000000010000001") else
(others => '0');
ClockDiv_0 : ClockDiv PORT MAP (
clk => clock,
reset => reset,
clk_2t => clock_2t,
clk_4t => clock_4t
);
BubbleUnit_0 : BubbleUnit PORT MAP (
RegOpA => Decoder_RegOpA,
RegOpB => Decoder_RegOpB,
RegWE_EXE => ID_EXE_RegWrite,
RegDest_EXE => ID_EXE_RegDest,
RegWE_MEM=> EXE_MEM_RegWrite,
RegDest_MEM => EXE_MEM_RegDest,
RegMemDIn_EXE => ID_EXE_RegMemDIn,
MemRead_EXE => ID_EXE_MemRead,
MemWrite_EXE => ID_EXE_MemWrite,
MemRead_MEM => EXE_MEM_MemRead,
MemWrite_MEM => EXE_MEM_MemWrite,
MemAddr => EXE_MEM_ALUOUT,
pc_sel=> Decoder_PC_Sel,
CReg => Decoder_CReg,
CRegA => Decoder_CRegA,
CRegB => Decoder_CRegB,
SerialFinish => DATA_MEM_SERIAL_FINISH,
pc_stall => PC_REG_STALL,
InstAddrSel => INST_ADDR_SEL,
InstMemRead => INST_MEM_READ,
InstMemWrite => INST_MEM_WRITE,
Mem_Result_Sel => MEM_RESULT_SEL,
IF_ID_stall => IF_ID_REG_STALL,
ID_EXE_stall => ID_EXE_REG_STALL,
EXE_MEM_stall => EXE_MEM_REG_STALL,
IF_ID_clear => IF_ID_REG_CLEAR,
ID_EXE_clear => ID_EXE_REG_CLEAR,
EXE_MEM_clear => EXE_MEM_REG_CLEAR
);
-- IF Section
PC_REG_0 : PC_REG PORT MAP (
clk => clock_4t,
reset => reset,
stall => PC_REG_STALL,
PC_in => PC_REG_IN,
PC_out => PC_REG_OUT
);
INST_ADDR_MUX : TwoInMuxer_16bit PORT MAP (
input1 => PC_REG_OUT,
input2 => EXE_MEM_ALUOUT,
opcode => INST_ADDR_SEL,
output => INST_ADDR_OUT
);
INST_MEMORY_0 : InstMemoryControl PORT MAP (
clk => clock,
reset => reset,
MemRead => INST_MEM_READ,
MemWrite => INST_MEM_WRITE,
MemAddr => INST_ADDR_OUT,
MemData => MEM_MemDIn_MUX_OUT,
MemOut => INST_MEM_OUT,
RAM2Addr => RAM2ADDR,
RAM2Data => RAM2DATA,
RAM2EN => RAM2EN,
RAM2OE => RAM2OE,
RAM2RW => RAM2RW
);
PCAdder_0 : PCAdder PORT MAP (
A => PC_REG_OUT,
B => PC_INCR,
result => PC_INCR_OUT
);
PC_REG_MUX : FourInMuxer_16bit PORT MAP (
input1 => PC_INCR_OUT,
input2 => Regs_RAVal,
input3 => Regs_RegAVal,
input4 => PC_JUMP_ADDR,
opcode => Decoder_PC_Sel,
output => PC_REG_IN
);
IF_ID_REG_0 : IF_ID_REG PORT MAP (
clk => clock_4t,
reset => reset,
pc_in => PC_INCR_OUT,
inst_in => INST_MEM_OUT,
stall => IF_ID_REG_STALL,
clear => IF_ID_REG_CLEAR,
pc_out => IF_ID_PC,
inst_out => IF_ID_INST,
rx => IF_ID_REGX,
ry => IF_ID_REGY
);
-- ID Section
PCAdder_1 : PCAdder PORT MAP (
A => IF_ID_PC,
B => Decoder_PC_Imm,
result => PC_JUMP_ADDR
);
InstDecoder_0 : InstDecoder PORT MAP (
pc => IF_ID_PC,
inst => IF_ID_INST,
RegAVal => RegAVal_MUX_OUT,
RegBVal => RegBVal_MUX_OUT,
RAVal => RegRA_MUX_OUT,
SPVal => Regs_SPVal,
IHVal => Regs_IHVal,
T_in => T_REG_OUT,
T_out => T_REG_IN,
pc_imm => Decoder_PC_Imm,
pc_sel => Decoder_PC_Sel,
RegWE => Decoder_RegWrite,
RegDest => Decoder_RegDest,
MemRd => Decoder_MemRead,
MemDIn => Decoder_MemDIn,
RegMemDIn => Decoder_RegMemDIn,
MemWE => Decoder_MemWrite,
opcode => Decoder_OpCode,
RegOpA => Decoder_RegOpA,
RegOpB => Decoder_RegOpB,
CReg => Decoder_CReg,
CRegA => Decoder_CRegA,
CRegB => Decoder_CRegB,
operandA => Decoder_OperandA,
operandB => Decoder_OperandB
);
Register_Files_0 : Register_Files PORT MAP (
clk => clock,
reset => reset,
ASel => IF_ID_REGX,
BSel => IF_ID_REGY,
WSel => MEM_WB_RegDest,
WE => MEM_WB_RegWrite,
WVal => MEM_WB_RegWriteVal,
AVal => Regs_RegAVal,
BVal => Regs_RegBVal,
RAVal => Regs_RAVal,
SPVal => Regs_SPVal,
IHVal => Regs_IHVal
);
T_REG_0 : T_REG PORT MAP (
clk => clock,
reset => reset,
T_in => T_REG_IN,
T_out => T_REG_OUT
);
ID_EXE_REG_0 : ID_EXE_REG PORT MAP (
clk => clock_4t,
reset => reset,
clear => ID_EXE_REG_CLEAR,
stall => ID_EXE_REG_STALL,
RegWE_in => Decoder_RegWrite,
RegDest_in => Decoder_RegDest,
RegMemDIn_in => Decoder_RegMemDIn,
MemRd_in => Decoder_MemRead,
MemWE_in => Decoder_MemWrite,
MemDIn_in => Decoder_MemDIn,
opcode_in => Decoder_OpCode,
operandA_in => Decoder_OperandA,
operandB_in => Decoder_OperandB,
RegOpA_in => Decoder_RegOpA,
RegOpB_in => Decoder_RegOpB,
RegWE_out => ID_EXE_RegWrite,
RegDest_out => ID_EXE_RegDest,
RegMemDIn_out => ID_EXE_RegMemDIn,
MemRd_out => ID_EXE_MemRead,
MemWE_out => ID_EXE_MemWrite,
MemDIn_out => ID_EXE_MemDIn,
opcode_out => ID_EXE_OpCode,
operandA_out => ID_EXE_OperandA,
operandB_out => ID_EXE_OperandB,
RegOpA_out => ID_EXE_RegOpA,
RegOpB_out => ID_EXE_RegOpB
);
RegAVal_MUX : TwoInMuxer_16bit PORT MAP (
input1 => Regs_RegAVal,
input2 => EXE_MEM_ALUOUT,
opcode => RegAVal_MUX_SEL,
output => RegAVal_MUX_OUT
);
RegBVal_MUX : TwoInMuxer_16bit PORT MAP (
input1 => Regs_RegBVal,
input2 => EXE_MEM_ALUOUT,
opcode => RegBVal_MUX_SEL,
output => RegBVal_MUX_OUT
);
RegRA_MUX : TwoInMuxer_16bit PORT MAP (
input1 => Regs_RAVal,
input2 => EXE_MEM_ALUOUT,
opcode => RegRA_MUX_SEL,
output => RegRA_MUX_OUT
);
-- EXE Section
ALU_0 : ALU PORT MAP (
op => ID_EXE_OpCode,
A => OpA_MUX_OUT,
B => OpB_MUX_OUT,
result => ALU_RESULT
);
OpA_MUX : FourInMuxer_16bit PORT MAP (
input1 => ID_EXE_OperandA,
input2 => EXE_MEM_ALUOUT,
input3 => MEM_WB_RegWriteVal,
input4 => "0000000000000000",
opcode => OpA_MUX_SEL,
output => OpA_MUX_OUT
);
OpB_MUX : FourInMuxer_16bit PORT MAP (
input1 => ID_EXE_OperandB,
input2 => EXE_MEM_ALUOUT,
input3 => MEM_WB_RegWriteVal,
input4 => "0000000000000000",
opcode => OpB_MUX_SEL,
output => OpB_MUX_OUT
);
MemDIn_MUX : FourInMuxer_16bit PORT MAP (
input1 => ID_EXE_MemDIn,
input2 => EXE_MEM_ALUOUT,
input3 => MEM_WB_RegWriteVal,
input4 => "0000000000000000",
opcode => EXE_MemDIn_MUX_SEL,
output => MemDIn_MUX_OUT
);
EXE_MEM_REG_0 : EXE_MEM_REG PORT MAP (
clk => clock_4t,
reset => reset,
clear => EXE_MEM_REG_CLEAR,
stall => EXE_MEM_REG_STALL,
RegWE_in => ID_EXE_RegWrite,
RegDest_in => ID_EXE_RegDest,
RegMemDIn_in => ID_EXE_RegMemDIn,
MemRd_in => ID_EXE_MemRead,
MemWE_in => ID_EXE_MemWrite,
MemDIn_in => MemDIn_MUX_OUT,
ALUout_in => ALU_RESULT,
RegWE_out => EXE_MEM_RegWrite,
RegDest_out => EXE_MEM_RegDest,
RegMemDIn_out => EXE_MEM_RegMemDIn,
MemRd_out => EXE_MEM_MemRead,
MemWE_out => EXE_MEM_MemWrite,
MemDIn_out => EXE_MEM_MemDIn,
ALUout_out => EXE_MEM_ALUOUT
);
ForwardingUnit_0 : ForwardingUnit PORT MAP (
RegOpA => ID_EXE_RegOpA,
RegOpB => ID_EXE_RegOpB,
RegWE_WB => MEM_WB_RegWrite,
RegDest_WB => MEM_WB_RegDest,
RegWE_MEM => EXE_MEM_RegWrite,
RegDest_MEM => EXE_MEM_RegDest,
MemRead_EXE => ID_EXE_MemRead,
MemRead_WB => MEM_WB_MemRead,
CReg => Decoder_CReg,
CRegA => Decoder_CRegA,
CRegB => Decoder_CRegB,
RegMemDIn_EXE => ID_EXE_RegMemDIn,
RegMemDIn_MEM => EXE_MEM_RegMemDIn,
RegAValSel => RegAVal_MUX_SEL,
RegBValSel => RegBVal_MUX_SEL,
RegRAValSel => RegRA_MUX_SEL,
OperandASel => OpA_MUX_SEL,
OperandBSel => OpB_MUX_SEL,
MemDInSel_EXE => EXE_MemDIn_MUX_SEL,
MemDInSel_MEM => MEM_MemDIn_MUX_SEL
);
-- MEM Section
DATA_MEMORY_0 : DataMemoryControl PORT MAP (
clk => clock,
reset => reset,
MemRead => EXE_MEM_MemRead,
MemWrite=> EXE_MEM_MemWrite,
MemAddr => EXE_MEM_ALUOUT,
MemData => MEM_MemDIn_MUX_OUT,
MemOut => DATA_MEM_OUT,
SerialFinish => DATA_MEM_SERIAL_FINISH,
RAM1Addr => RAM1ADDR,
RAM1Data => RAM1DATA,
RAM1EN => RAM1EN,
RAM1OE => RAM1OE,
RAM1RW => RAM1RW,
Serial_dataready => SERIAL_DATA_READY,
Serial_rdn => SERIAL_RDN,
Serial_tbre => SERIAL_TBRE,
Serial_tsre => SERIAL_TSRE,
Serial_wrn => SERIAL_WRN,
DLED_Right => DLED_RIGHT
);
MEM_MemDIn_MUX : TwoInMuxer_16bit PORT MAP (
input1 => EXE_MEM_MemDIn,
input2 => MEM_WB_RegWriteVal,
opcode => MEM_MemDIn_MUX_SEL,
output => MEM_MemDIn_MUX_OUT
);
MEM_MUX : TwoInMuxer_16bit PORT MAP (
input1 => DATA_MEM_OUT,
input2 => INST_MEM_OUT,
opcode => MEM_RESULT_SEL,
output => DATA_MEM_MUX_OUT
);
MEM_RESULT_MUX : TwoInMuxer_16bit PORT MAP (
input1 => EXE_MEM_ALUOUT,
input2 => DATA_MEM_MUX_OUT,
opcode => EXE_MEM_MemRead,
output => MEM_RESULT_MUX_OUT
);
MEM_WB_REG_0 : MEM_WB_REG PORT MAP (
clk => clock_4t,
reset => reset,
RegWE_in => EXE_MEM_RegWrite,
RegDest_in => EXE_MEM_RegDest,
RegWriteVal_in => MEM_RESULT_MUX_OUT,
MemRd_in => EXE_MEM_MemRead,
RegWE_out => MEM_WB_RegWrite,
RegDest_out => MEM_WB_RegDest,
RegWriteVal_out => MEM_WB_RegWriteVal,
MemRd_out => MEM_WB_MemRead
);
-- WB Section
end Behavioral;
|
-- NEED RESULT: ENT00024: Associated scalar ports with static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00024
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (4)
-- 1.1.1.2 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00024(ARCH00024)
-- ENT00024_Test_Bench(ARCH00024_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00024 is
port (
i_boolean_1, i_boolean_2 : in boolean
:= c_boolean_1
;
i_bit_1, i_bit_2 : in bit
:= c_bit_1
;
i_severity_level_1, i_severity_level_2 : in severity_level
:= c_severity_level_1
;
i_character_1, i_character_2 : in character
:= c_character_1
;
i_t_enum1_1, i_t_enum1_2 : in t_enum1
:= c_t_enum1_1
;
i_st_enum1_1, i_st_enum1_2 : in st_enum1
:= c_st_enum1_1
;
i_integer_1, i_integer_2 : in integer
:= c_integer_1
;
i_t_int1_1, i_t_int1_2 : in t_int1
:= c_t_int1_1
;
i_st_int1_1, i_st_int1_2 : in st_int1
:= c_st_int1_1
;
i_time_1, i_time_2 : in time
:= c_time_1
;
i_t_phys1_1, i_t_phys1_2 : in t_phys1
:= c_t_phys1_1
;
i_st_phys1_1, i_st_phys1_2 : in st_phys1
:= c_st_phys1_1
;
i_real_1, i_real_2 : in real
:= c_real_1
;
i_t_real1_1, i_t_real1_2 : in t_real1
:= c_t_real1_1
;
i_st_real1_1, i_st_real1_2 : in st_real1
:= c_st_real1_1
) ;
begin
end ENT00024 ;
--
architecture ARCH00024 of ENT00024 is
begin
process
variable correct : boolean := true ;
begin
correct := correct and i_boolean_1 = c_boolean_1
and i_boolean_2 = c_boolean_1 ;
correct := correct and i_bit_1 = c_bit_1
and i_bit_2 = c_bit_1 ;
correct := correct and i_severity_level_1 = c_severity_level_1
and i_severity_level_2 = c_severity_level_1 ;
correct := correct and i_character_1 = c_character_1
and i_character_2 = c_character_1 ;
correct := correct and i_t_enum1_1 = c_t_enum1_1
and i_t_enum1_2 = c_t_enum1_1 ;
correct := correct and i_st_enum1_1 = c_st_enum1_1
and i_st_enum1_2 = c_st_enum1_1 ;
correct := correct and i_integer_1 = c_integer_1
and i_integer_2 = c_integer_1 ;
correct := correct and i_t_int1_1 = c_t_int1_1
and i_t_int1_2 = c_t_int1_1 ;
correct := correct and i_st_int1_1 = c_st_int1_1
and i_st_int1_2 = c_st_int1_1 ;
correct := correct and i_time_1 = c_time_1
and i_time_2 = c_time_1 ;
correct := correct and i_t_phys1_1 = c_t_phys1_1
and i_t_phys1_2 = c_t_phys1_1 ;
correct := correct and i_st_phys1_1 = c_st_phys1_1
and i_st_phys1_2 = c_st_phys1_1 ;
correct := correct and i_real_1 = c_real_1
and i_real_2 = c_real_1 ;
correct := correct and i_t_real1_1 = c_t_real1_1
and i_t_real1_2 = c_t_real1_1 ;
correct := correct and i_st_real1_1 = c_st_real1_1
and i_st_real1_2 = c_st_real1_1 ;
test_report ( "ENT00024" ,
"Associated scalar ports with static subtypes" ,
correct) ;
wait ;
end process ;
end ARCH00024 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00024_Test_Bench is
end ENT00024_Test_Bench ;
--
architecture ARCH00024_Test_Bench of ENT00024_Test_Bench is
begin
L1:
block
signal i_boolean_1, i_boolean_2 : boolean
:= c_boolean_1 ;
signal i_bit_1, i_bit_2 : bit
:= c_bit_1 ;
signal i_severity_level_1, i_severity_level_2 : severity_level
:= c_severity_level_1 ;
signal i_character_1, i_character_2 : character
:= c_character_1 ;
signal i_t_enum1_1, i_t_enum1_2 : t_enum1
:= c_t_enum1_1 ;
signal i_st_enum1_1, i_st_enum1_2 : st_enum1
:= c_st_enum1_1 ;
signal i_integer_1, i_integer_2 : integer
:= c_integer_1 ;
signal i_t_int1_1, i_t_int1_2 : t_int1
:= c_t_int1_1 ;
signal i_st_int1_1, i_st_int1_2 : st_int1
:= c_st_int1_1 ;
signal i_time_1, i_time_2 : time
:= c_time_1 ;
signal i_t_phys1_1, i_t_phys1_2 : t_phys1
:= c_t_phys1_1 ;
signal i_st_phys1_1, i_st_phys1_2 : st_phys1
:= c_st_phys1_1 ;
signal i_real_1, i_real_2 : real
:= c_real_1 ;
signal i_t_real1_1, i_t_real1_2 : t_real1
:= c_t_real1_1 ;
signal i_st_real1_1, i_st_real1_2 : st_real1
:= c_st_real1_1 ;
component UUT
port (
i_boolean_1, i_boolean_2 : in boolean
:= c_boolean_1
;
i_bit_1, i_bit_2 : in bit
:= c_bit_1
;
i_severity_level_1, i_severity_level_2 : in severity_level
:= c_severity_level_1
;
i_character_1, i_character_2 : in character
:= c_character_1
;
i_t_enum1_1, i_t_enum1_2 : in t_enum1
:= c_t_enum1_1
;
i_st_enum1_1, i_st_enum1_2 : in st_enum1
:= c_st_enum1_1
;
i_integer_1, i_integer_2 : in integer
:= c_integer_1
;
i_t_int1_1, i_t_int1_2 : in t_int1
:= c_t_int1_1
;
i_st_int1_1, i_st_int1_2 : in st_int1
:= c_st_int1_1
;
i_time_1, i_time_2 : in time
:= c_time_1
;
i_t_phys1_1, i_t_phys1_2 : in t_phys1
:= c_t_phys1_1
;
i_st_phys1_1, i_st_phys1_2 : in st_phys1
:= c_st_phys1_1
;
i_real_1, i_real_2 : in real
:= c_real_1
;
i_t_real1_1, i_t_real1_2 : in t_real1
:= c_t_real1_1
;
i_st_real1_1, i_st_real1_2 : in st_real1
:= c_st_real1_1
) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00024 (ARCH00024) ;
begin
CIS1 : UUT
port map (
i_boolean_1, i_boolean_2,
i_bit_1, i_bit_2,
i_severity_level_1, i_severity_level_2,
i_character_1, i_character_2,
i_t_enum1_1, i_t_enum1_2,
i_st_enum1_1, i_st_enum1_2,
i_integer_1, i_integer_2,
i_t_int1_1, i_t_int1_2,
i_st_int1_1, i_st_int1_2,
i_time_1, i_time_2,
i_t_phys1_1, i_t_phys1_2,
i_st_phys1_1, i_st_phys1_2,
i_real_1, i_real_2,
i_t_real1_1, i_t_real1_2,
i_st_real1_1, i_st_real1_2
) ;
end block L1 ;
end ARCH00024_Test_Bench ;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr3ram
-- File: ddr3ram.vhd
-- Author: Magnus Hjorth, Aeroflex Gaisler
-- Description: Generic simulation model of DDR3 SDRAM (JESD79-3)
------------------------------------------------------------------------------
--pragma translate_off
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdio.hread;
use grlib.stdlib.all;
entity ddr3ram is
generic (
width: integer := 32;
abits: integer range 13 to 16 := 13;
colbits: integer range 9 to 12 := 10;
rowbits: integer range 1 to 16 := 13;
implbanks: integer range 1 to 8 := 1;
fname: string;
lddelay: time := (0 ns);
ldguard: integer range 0 to 1 := 0; -- 1: wait for doload input before
-- loading RAM
-- Speed bins: 0-1:800E-D, 2-4:1066G-E 5-8:1333J-F 9-12:1600K-G
speedbin: integer range 0 to 12 := 0;
density: integer range 2 to 6 := 3; -- 2:512M 3:1G 4:2G 5:4G 6:8G bits/chip
pagesize: integer range 1 to 2 := 1; -- 1K/2K page size (controls tRRD)
changeendian: integer range 0 to 32 := 0
);
port (
ck: in std_ulogic;
ckn: in std_ulogic;
cke: in std_ulogic;
csn: in std_ulogic;
odt: in std_ulogic;
rasn: in std_ulogic;
casn: in std_ulogic;
wen: in std_ulogic;
dm: in std_logic_vector(width/8-1 downto 0);
ba: in std_logic_vector(2 downto 0);
a: in std_logic_vector(abits-1 downto 0);
resetn: in std_ulogic;
dq: inout std_logic_vector(width-1 downto 0);
dqs: inout std_logic_vector(width/8-1 downto 0);
dqsn: inout std_logic_vector(width/8-1 downto 0);
doload: in std_ulogic := '1'
);
end;
architecture sim of ddr3ram is
type moderegs is record
-- Mode register (0)
ppd: std_ulogic;
wr: std_logic_vector(2 downto 0);
dllres: std_ulogic;
tm: std_ulogic;
rbt: std_ulogic;
caslat: std_logic_vector(3 downto 0);
blen: std_logic_vector(1 downto 0);
-- Extended mode register 1
qoff: std_ulogic;
tdqsen: std_ulogic;
level: std_ulogic;
al: std_logic_vector(1 downto 0);
rtt_nom: std_logic_vector(2 downto 0);
dic: std_logic_vector(1 downto 0);
dlldis: std_ulogic;
-- Extended mode register 2
rtt_wr: std_logic_vector(1 downto 0);
srt: std_ulogic;
asr: std_ulogic;
cwl: std_logic_vector(2 downto 0);
pasr: std_logic_vector(2 downto 0);
-- Extended mode register 3
mpr: std_ulogic;
mprloc: std_logic_vector(1 downto 0);
end record;
-- Mode registers as signal, useful for debugging
signal mr: moderegs;
-- Handshaking between command and DQ/DQS processes
signal read_en, write_en, dqscal_en: boolean := false;
signal read_data, write_data: std_logic_vector(2*width-1 downto 0);
signal write_mask: std_logic_vector(width/4-1 downto 0);
signal initdone: boolean := false;
-- Small delta-t to adjust calculations for jitter tol.
constant deltat: time := 50 ps;
-- Timing parameters
constant tWR: time := 15 ns;
constant tMRD_ck: integer := 4;
constant tRTP_ck: integer := 4;
constant tRTP_t: time := 7.5 ns;
function tRTP(tper: time) return time is
begin
if tRTP_ck*tper > tRTP_t then return tRTP_ck*tper; else return tRTP_t; end if;
end tRTP;
constant tMOD_ck: integer := 12;
constant tMOD_t: time := 15 ns;
type timetab is array (0 to 12) of time;
-- 800E 800D 1066G 1066H 1066E 1333J 1333H 1333G 1333F 1600K 1600J 1600H 1600G
constant tRAS : timetab :=
(37.5 ns, 37.5 ns, 37.5 ns, 37.5 ns, 37.5 ns, 36 ns, 36 ns, 36 ns, 36 ns, 35 ns, 35 ns, 35 ns, 35 ns);
constant tRP : timetab :=
(15 ns, 12.5 ns, 15 ns, 13.125 ns, 11.25 ns, 15 ns, 13.5 ns, 12 ns, 10.5 ns, 13.75 ns, 12.5 ns, 11.25 ns, 10 ns);
constant tRCD: timetab := tRP;
type timetab2 is array(2 to 6) of time;
constant tRFC: timetab2 := (90 ns, 110 ns, 160 ns, 300 ns, 350 ns);
function tRRD(tper: time; speedbin: integer range 0 to 12) return time is
variable t: time;
begin
case speedbin is
when 0 to 1 => t:=10 ns;
when 2 to 4 => if pagesize<2 then t:=7.5 ns; else t:=10 ns; end if;
when 5 to 12 => if pagesize<2 then t:=6 ns; else t:=7.5 ns; end if;
end case;
if t < 4*tper then t:=4*tper; end if;
return t;
end tRRD;
function pick(t,f: integer; b: boolean) return integer is
begin
if b then return t; else return f; end if;
end pick;
begin
-----------------------------------------------------------------------------
-- Init sequence checker
-----------------------------------------------------------------------------
initp: process
procedure checkcmd(crasn,ccasn,cwen: std_ulogic;
cba: std_logic_vector(2 downto 0);
ca: std_logic_vector(15 downto 0)) is
variable amatch: boolean;
begin
wait until rising_edge(ck);
while cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1')) loop
wait until rising_edge(ck);
end loop;
amatch := true;
for x in a'range loop
if ca(x)/='-' and ca(x)/=a(x) then amatch:=false; end if;
end loop;
assert cke='1' and csn='0' and rasn=crasn and casn=ccasn and wen=cwen and
(cba="---" or cba=ba) and amatch
report "Wrong command during init sequence" severity warning;
end checkcmd;
variable t,t2: time;
variable i: integer;
begin
initdone <= false;
-- Allow resetn to be X or U for a while during sim start
if resetn /= '0' then
wait until resetn='0' for 1 us;
end if;
assert resetn='0' report "RESETn not asserted on power-up" severity warning;
wait until resetn/='0' for 200 us;
assert resetn='0' report "RESETn raised with less than 200 us init delay" severity warning;
l0: loop
initdone <= false;
wait until resetn/='0';
assert cke='0' report "CKE not low when RESETn deasserted" severity warning;
wait until (resetn='0' or cke/='0') for 500 us;
if resetn='0' then next; end if;
assert cke='0' report "CKE raised with less than 500 us delay after RESETn deasserted" severity warning;
wait until (resetn='0' or cke/='0') and rising_edge(ck);
if resetn='0' then next; end if;
assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1'));
t := now;
t2 := t+tRFC(density)+(10 ns);
i := 0;
while i<5 and now<t2 loop
wait until (resetn='0' or rising_edge(ck));
if resetn='0' then next l0; end if;
assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1'));
i := i+1;
end loop;
-- EMRS EMR2
checkcmd('0','0','0',"010","----------------");
if resetn='0' then next; end if;
-- EMRS EMR3
checkcmd('0','0','0',"011","----------------");
if resetn='0' then next; end if;
-- EMRS EMR1 enable DLL
checkcmd('0','0','0',"001","---------------0");
if resetn='0' then next; end if;
-- EMRS EMR0 reset DLL
checkcmd('0','0','0',"000","-------1--------");
if resetn='0' then next; end if;
-- ZQCL
checkcmd('1','1','0',"---","-----1----------");
if resetn='0' then next; end if;
for x in 1 to 512 loop
wait until (resetn='0' or rising_edge(ck));
if resetn='0' then next l0; end if;
assert cke='1' and (csn='1' or (rasn='1' and casn='1' and wen='1'));
end loop;
initdone <= true;
wait until resetn='0';
end loop;
end process;
-----------------------------------------------------------------------------
-- Command state machine
-----------------------------------------------------------------------------
cmdp: process(ck)
-- Data split by bank to avoid exceeding 4G
constant b0size: integer := (2**(colbits+rowbits)) * ((width+15)/16);
constant b1size: integer := pick(b0size, 1, implbanks>1);
constant b2size: integer := pick(b0size, 1, implbanks>2);
constant b3size: integer := pick(b0size, 1, implbanks>3);
constant b4size: integer := pick(b0size, 1, implbanks>4);
constant b5size: integer := pick(b0size, 1, implbanks>5);
constant b6size: integer := pick(b0size, 1, implbanks>6);
constant b7size: integer := pick(b0size, 1, implbanks>7);
subtype coldata is std_logic_vector(width-1 downto 0);
subtype idata is integer range 0 to (2**20)-1; -- 16 data bits + 2x2 X/U state
type idata_arr is array(natural range <>) of idata;
variable memdata0: idata_arr(0 to b0size-1);
variable memdata1: idata_arr(0 to b1size-1);
variable memdata2: idata_arr(0 to b2size-1);
variable memdata3: idata_arr(0 to b3size-1);
variable memdata4: idata_arr(0 to b4size-1);
variable memdata5: idata_arr(0 to b5size-1);
variable memdata6: idata_arr(0 to b6size-1);
variable memdata7: idata_arr(0 to b7size-1);
function reversedata(data : std_logic_vector; step : integer)
return std_logic_vector is
variable rdata: std_logic_vector(data'length-1 downto 0);
begin
for i in 0 to (data'length/step-1) loop
rdata(i*step+step-1 downto i*step) := data(data'length-i*step-1 downto data'length-i*step-step);
end loop;
return rdata;
end function reversedata;
impure function memdata_get(bank,idx: integer) return coldata is
variable r: coldata;
variable x: idata;
variable p: std_logic_vector(19 downto 0);
variable iidx: integer;
begin
iidx := (idx*width)/16;
for q in 0 to (width+15)/16-1 loop
case bank is
when 0 => x := memdata0(iidx+q);
when 1 => x := memdata1(iidx+q);
when 2 => x := memdata2(iidx+q);
when 3 => x := memdata3(iidx+q);
when 4 => x := memdata4(iidx+q);
when 5 => x := memdata5(iidx+q);
when 6 => x := memdata6(iidx+q);
when others => x := memdata7(iidx+q);
end case;
p := std_logic_vector(to_unsigned(x,20));
if p(18)='0' then p(15 downto 8) := "UUUUUUUU";
elsif p(19)='1' then p(15 downto 8) := "XXXXXXXX"; end if;
if p(16)='0' then p(7 downto 0) := "UUUUUUUU";
elsif p(17)='1' then p(7 downto 0) := "XXXXXXXX"; end if;
if width < 16 then
r := p(7 downto 0);
else
r(width-16*q-1 downto width-16*q-16) := p(15 downto 0);
end if;
end loop;
if changeendian /= 0 then
r := reversedata(r, changeendian);
end if;
return r;
end memdata_get;
procedure memdata_set(bank,idx: integer; v: coldata) is
variable n: coldata;
variable x: idata;
variable p: std_logic_vector(19 downto 0);
variable iidx: integer;
begin
-- assert false
-- report ("memdata_set: bank " & tost(bank) & " idx " & tost(idx) & " data " & tost(v))
-- severity note;
n := v;
if changeendian /= 0 then
n := reversedata(n, changeendian);
end if;
iidx := (idx*width)/16;
for q in 0 to (width+15)/16-1 loop
p := "0101" & x"0000";
if width < 16 then
p(7 downto 0) := n;
else
p(15 downto 0) := n(width-16*q-1 downto width-16*q-16);
end if;
if p(15 downto 8)="UUUUUUUU" then p(18):='0'; p(15 downto 8):=x"00";
elsif is_x(p(15 downto 8)) then p(19):='1'; p(15 downto 8):=x"00"; end if;
if p(7 downto 0)="UUUUUUUU" then p(16):='0'; p(7 downto 0):=x"00";
elsif is_x(p(7 downto 0)) then p(17):='1'; p(7 downto 0):=x"00"; end if;
x := to_integer(unsigned(p));
case bank is
when 0 => memdata0(iidx+q) := x;
when 1 => memdata1(iidx+q) := x;
when 2 => memdata2(iidx+q) := x;
when 3 => memdata3(iidx+q) := x;
when 4 => memdata4(iidx+q) := x;
when 5 => memdata5(iidx+q) := x;
when 6 => memdata6(iidx+q) := x;
when others => memdata7(iidx+q) := x;
end case;
end loop;
end memdata_set;
procedure load_srec is
file TCF : text open read_mode is fname;
variable L1: line;
variable CH : character;
variable rectype : std_logic_vector(3 downto 0);
variable recaddr : std_logic_vector(31 downto 0);
variable reclen : std_logic_vector(7 downto 0);
variable recdata : std_logic_vector(0 to 16*8-1);
variable idx, coloffs, len: integer;
begin
L1:= new string'("");
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := to_integer(unsigned(reclen))-1;
recaddr := (others => '0');
case rectype is
when "0001" => hread(L1, recaddr(15 downto 0)); len := len - 2;
when "0010" => hread(L1, recaddr(23 downto 0)); len := len - 3;
when "0011" => hread(L1, recaddr); len := len - 4;
when others => next;
end case;
hread(L1, recdata(0 to len*8-1));
if width < 16 then
idx := to_integer(unsigned(recaddr(rowbits+colbits-1 downto 0)));
while len > 1 loop
memdata0(idx) := 16#10000# + to_integer(unsigned(recdata(0 to 7)));
idx := idx+1;
len := len-1;
recdata(0 to recdata'length-8-1) := recdata(8 to recdata'length-1);
end loop;
else
assert recaddr(0)='0'; -- Assume 16-bit alignment on SREC entry
idx := to_integer(unsigned(recaddr(rowbits+colbits+log2(width/16) downto 1)));
while len > 1 loop
memdata0(idx) := 16#50000# + to_integer(unsigned(recdata(0 to 15)));
idx := idx+1;
len := len-2;
recdata(0 to recdata'length-16-1) := recdata(16 to recdata'length-1);
end loop;
if len > 0 then
memdata0(idx) := 16#40000# + to_integer(unsigned(recdata(0 to 15)));
end if;
end if;
end if;
end if;
end if;
end loop;
end load_srec;
variable vmr: moderegs;
type bankstate is record
openrow: integer;
opentime: time;
closetime: time;
writetime: time;
readtime: time;
autopch: integer;
pchpush: boolean;
end record;
type bankstate_arr is array(natural range <>) of bankstate;
variable banks: bankstate_arr(7 downto 0) := (others => (-1, 0 ns, 0 ns, 0 ns, 0 ns, -1, false));
type int_arr is array(natural range <>) of integer;
type dataacc is record
r,w: boolean;
col: int_arr(0 to 1);
bank: integer;
first,wchop: boolean;
end record;
type dataacc_arr is array(natural range <>) of dataacc;
variable accpipe: dataacc_arr(0 to 25);
variable cmd: std_logic_vector(2 downto 0);
variable bank: integer;
variable colv: unsigned(a'high-2 downto 0);
variable alow: unsigned(2 downto 0);
variable col: integer;
variable prev_re, re: time;
variable blen, wblen: integer;
variable lastref: time := 0 ns;
variable i, al, cl, cwl, wrap: integer;
variable b: boolean;
variable mrscount: integer := 100;
variable mrstime: time;
variable loaded: boolean := false;
variable cold: coldata;
procedure checktime(got, exp: time; gt: boolean; req: string) is
begin
assert (got + deltat > exp and gt) or (got-deltat < exp and not gt)
report (req & " violation, got: " & tost(got/(1 ps)) & " ps, exp: " & tost(exp/(1 ps)) & "ps")
severity warning;
end checktime;
begin
if rising_edge(ck) and resetn='1' then
-- Update pipe regs
prev_re := re;
re := now;
accpipe(1 to accpipe'high) := accpipe(0 to accpipe'high-1);
accpipe(0).r:=false; accpipe(0).w:=false; accpipe(0).first:=false;
-- Parse MR fields
cmd := rasn & casn & wen;
if is_x(vmr.caslat) then cl:=0; else cl:=to_integer(unsigned(vmr.caslat(3 downto 1)))+4; end if;
if cl<5 or cl>11 then cl:=0; end if;
case vmr.al is
when "00" => al:=0;
when "01" => al:=cl-1;
when "10" => al:=cl-2;
when others => al:=-1;
end case;
if is_x(vmr.cwl) then cwl:=0; else cwl:=to_integer(unsigned(vmr.cwl))+5; end if;
if cwl>8 then cwl:=0; end if;
if is_x(vmr.wr) then wrap:=0; else wrap:=to_integer(unsigned(vmr.wr))+4; end if;
if wrap<5 or wrap>12 then wrap:=0; end if;
-- Checks for all-bank commands
mrscount := mrscount+1;
assert (mrscount >= tMRD_ck) or (cke='1' and (csn='1' or cmd="111"))
report "tMRD violation!" severity warning;
assert (mrscount > tMOD_ck and now > mrstime+tMOD_t-deltat) or
(cke='1' and (csn='1' or cmd="111" or cmd="000"))
report "tMOD violation!" severity warning;
if cke='1' and csn='0' and cmd/="111" then
checktime(now-lastref, tRFC(density), true, "tRFC");
end if;
if vmr.mpr='1' then
assert cke='0' or csn='1' or cmd="111" or cmd="101"
report "Command other than read in MPR mode!" severity warning;
for x in 7 downto 0 loop
assert banks(x).openrow<0
report "Row opened in MPR mode!" severity warning;
end loop;
end if;
-- Main command handler
if cke='1' and csn='0' then
case cmd is
when "111" => -- NOP
when "011" => -- RAS
assert initdone report "Opening row before init sequence done!" severity warning;
bank := to_integer(unsigned(ba));
assert banks(bank).openrow < 0
report "Row already open" severity warning;
checktime(now-banks(bank).closetime, tRP(speedbin), true, "tRP");
for x in 0 to 7 loop
checktime(now-banks(x).opentime, tRRD(re-prev_re, speedbin), true, "tRRD");
end loop;
banks(bank).openrow := to_integer(unsigned(a(rowbits-1 downto 0)));
banks(bank).opentime := now;
when "101" | "100" => -- Read/Write
bank := to_integer(unsigned(ba));
assert banks(bank).openrow >= 0 or vmr.mpr='1'
report "Row not open" severity error;
checktime(now-banks(bank).opentime+al*(re-prev_re), tRCD(speedbin), true, "tRCD");
for x in 0 to 3 loop
assert not accpipe(x).r and not accpipe(x).w;
end loop;
if cmd(0)='1' then accpipe(3).r:=true; else accpipe(3).w:=true; end if;
colv := unsigned(std_logic_vector'(a(a'high downto 13) & a(11) & a(9 downto 0)));
wblen := 8;
case vmr.blen is
when "00" => blen := 8;
when "01" => if a(12)='1' then blen:=8; else blen:=4; end if;
when "11" => blen := 4; wblen:=4;
when others => assert false report "Invalid burst length setting in MR!" severity error;
end case;
alow := unsigned(a(2 downto 0));
if cmd(0)='0' then
alow(1 downto 0) := "00";
if blen=8 then alow(2):='0'; end if;
end if;
for x in 0 to blen-1 loop
accpipe(3-x/2).bank := bank;
if cmd(0)='1' then accpipe(3-x/2).r:=true; else accpipe(3-x/2).w:=true; end if;
if vmr.rbt='0' then -- Sequential
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) + x;
else -- Interleaved
colv(log2(blen)-1 downto 0) := alow(log2(blen)-1 downto 0) xor to_unsigned(x,log2(blen));
end if;
col := banks(bank).openrow * (2**colbits) + to_integer(colv(colbits-1 downto 0));
accpipe(3-x/2).col(x mod 2) := col;
accpipe(3-x/2).wchop := (blen<wblen);
end loop;
accpipe(3).first := true;
-- Auto precharge
if a(10)='1' then
if cmd(0)='1' then
banks(bank).autopch := al+tRTP_ck;
else
banks(bank).autopch := al+cwl+wblen/2+wrap;
end if;
banks(bank).pchpush := true;
end if;
when "110" => -- ZQInit
for x in 0 to 7 loop
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
for x in 3+cl+al downto 0 loop
assert not accpipe(x).r severity warning;
end loop;
for x in 4+cwl+al downto 0 loop
assert not accpipe(x).w severity warning;
end loop;
-- Currently does not check TZQCoper/TZQCs
when "010" => -- Precharge
if a(10)='0' then bank := to_integer(unsigned(ba)); else bank:=0; end if;
for x in 6+cwl+al downto 0 loop
assert ( (not ((accpipe(x).r and x<=3+al) or accpipe(x).w)) or
(a(10)='0' and accpipe(x).bank/=bank) )
report "Precharging bank with access in progress" severity warning;
end loop;
for x in 0 to 7 loop
if a(10)='1' or ba=std_logic_vector(to_unsigned(x,3)) then
assert banks(x).autopch<0
report "Precharging bank that is auto-precharged!" severity note;
assert a(10)='1' or banks(x).openrow >= 0
report "Precharging single bank that is in idle state!" severity note;
banks(x).autopch := 0; -- Handled below case statement
banks(x).pchpush := false;
end if;
end loop;
when "001" => -- Auto refresh
for x in 0 to 7 loop
assert banks(x).openrow < 0
report "Bank in wrong state for auto refresh!" severity warning;
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
lastref := now;
when "000" => -- MRS
for x in 0 to 7 loop
checktime(now-banks(x).closetime, tRP(speedbin), true, "tRP");
end loop;
bank := to_integer(unsigned(ba));
case bank is
when 0 =>
vmr.ppd := a(12);
vmr.wr := a(11 downto 9);
vmr.dllres := a(8);
vmr.tm := a(7);
vmr.caslat := a(6 downto 4) & a(2);
vmr.rbt := a(3);
vmr.blen := a(1 downto 0);
when 1 =>
vmr.qoff := a(12);
vmr.tdqsen := a(11);
vmr.level := a(7);
vmr.al := a(4 downto 3);
vmr.rtt_nom := a(9) & a(6) & a(2);
vmr.dic := a(5) & a(1);
vmr.dlldis := a(0);
when 2 =>
vmr.rtt_wr := a(10 downto 9);
vmr.srt := a(7);
vmr.asr := a(6);
vmr.cwl := a(5 downto 3);
vmr.pasr := a(2 downto 0);
when 3 =>
vmr.mpr := a(2);
vmr.mprloc := a(1 downto 0);
when others =>
assert false report ("MRS to invalid bank addr: " & std_logic'image(ba(1)) & std_logic'image(ba(0))) severity warning;
end case;
mrscount := 0;
mrstime := now;
when others =>
assert false report ("Invalid command: " & std_logic'image(rasn) & std_logic'image(casn) & std_logic'image(wen)) severity warning;
end case;
end if;
-- Manual or auto precharge handling
for x in 0 to 7 loop
if banks(x).autopch=0 then
if banks(x).pchpush and
((now-banks(x).readtime-deltat) < tRTP_t or
(now-banks(x).opentime-deltat) < tRAS(speedbin)) then
-- Auto delay auto-precharge to satisfy tRTP_t
-- NOTE: According to Micron's datasheets, their DDR3 memories
-- automatically hold off the auto precharge so that also tRAS is satisfied,
-- and the MIG controller seems to depend on this. It is not clear in the
-- JEDEC standard (rev F) whether this is guaranteed behavior for all DDR3
-- RAMs, but we emulate that behavior here.
banks(x).autopch := banks(x).autopch+1;
else
checktime(now-banks(x).writetime, tWR, true, "tWR");
checktime(now-banks(x).opentime, tRAS(speedbin), true, "tRAS");
checktime(now-banks(x).readtime, tRTP(re-prev_re), true, "tRTP");
banks(x).openrow := -1;
banks(x).closetime := now;
end if;
end if;
if banks(x).autopch >= 0 then
banks(x).autopch := banks(x).autopch - 1;
end if;
end loop;
-- Read/write management
if not loaded and lddelay < now and (ldguard=0 or doload='1') then
load_srec;
loaded := true;
end if;
if accpipe(2+cl+al).r then
assert cl>1 report "Incorrect CL setting!" severity warning;
read_en <= true;
-- print("Reading from col " & tost(accpipe(2+i).col(0)) & " and " & tost(accpipe(2+i).col(1)));
-- col0 <= accpipe(2+i).col(0); col1 <= accpipe(2+i).col(1);
if vmr.mpr='1' then
assert vmr.mprloc="00" report "Read from undefined MPR!" severity warning;
read_data <= (others => '0');
for x in width/8-1 downto 0 loop
read_data(x*8) <= '1';
end loop;
else
read_data <= memdata_get(accpipe(2+cl+al).bank, accpipe(2+cl+al).col(0)) &
memdata_get(accpipe(2+cl+al).bank, accpipe(2+cl+al).col(1));
end if;
else
read_en <= false;
end if;
if accpipe(3+al).r and accpipe(3+al).first then
banks(accpipe(3+al).bank).readtime := now;
end if;
write_en <= accpipe(2+cwl+al).w or accpipe(3+cwl+al).w;
if accpipe(4+cwl+al).w then
assert not is_x(write_mask) report "Write error!";
for x in 0 to 1 loop
cold := memdata_get(accpipe(4+cwl+al).bank, accpipe(4+cwl+al).col(x));
for b in width/8-1 downto 0 loop
if write_mask((1-x)*width/8+b)='0' then
cold(8*b+7 downto 8*b) :=
write_data( (1-x)*width+b*8+7 downto (1-x)*width+b*8);
end if;
end loop;
memdata_set(accpipe(4+cwl+al).bank, accpipe(4+cwl+al).col(x), cold);
end loop;
banks(accpipe(4+cwl+al).bank).writetime := now;
end if;
if accpipe(6+cwl+al).w and accpipe(6+cwl+al).wchop then
banks(accpipe(6+cwl+al).bank).writetime := now;
end if;
dqscal_en <= (vmr.level='1');
elsif resetn='0' then
for x in banks'range loop
banks(x).openrow := -1;
end loop;
end if;
mr <= vmr;
end process;
-----------------------------------------------------------------------------
-- DQS/DQ handling and data sampling process
-----------------------------------------------------------------------------
dqproc: process
variable rdata: std_logic_vector(2*width-1 downto 0);
variable hdata: std_logic_vector(width-1 downto 0);
variable hmask: std_logic_vector(width/8-1 downto 0);
variable prevdqs: std_logic_vector(width/8-1 downto 0);
begin
dq <= (others => 'Z');
dqs <= (others => 'Z');
dqsn <= (others => 'Z');
wait until read_en or write_en or dqscal_en;
assert not (read_en and write_en);
if dqscal_en then
while dqscal_en loop
prevdqs := dqs;
wait on dqs,dqscal_en;
for x in dqs'range loop
if dqs(x)='1' and prevdqs(x)='0' then
dq(8*x+7 downto 8*x) <= "0000000" & ck;
end if;
end loop;
end loop;
elsif read_en then
dqs <= (others => '0');
dqsn <= (others => '1');
wait until falling_edge(ck);
while read_en loop
rdata := read_data;
wait until rising_edge(ck);
dqs <= (others => '1');
dqsn <= (others => '0');
dq <= rdata(2*width-1 downto width);
wait until falling_edge(ck);
dqs <= (others => '0');
dqsn <= (others => '1');
dq <= rdata(width-1 downto 0);
end loop;
wait until rising_edge(ck);
else
wait until falling_edge(ck);
while write_en loop
prevdqs := to_X01(dqs);
wait until to_X01(dqs) /= prevdqs or not write_en or rising_edge(ck);
if rising_edge(ck) then
write_data <= (others => 'X');
write_mask <= (others => 'X');
end if;
for x in dqs'range loop
if prevdqs(x)='0' and to_X01(dqs(x))='1' then
hdata(8*x+7 downto 8*x) := dq(8*x+7 downto 8*x);
hmask(x) := dm(x);
elsif prevdqs(x)='1' and to_X01(dqs(x))='0' then
write_data(width+8*x+7 downto width+8*x) <= hdata(8*x+7 downto 8*x);
write_data(8*x+7 downto 8*x) <= dq(8*x+7 downto 8*x);
write_mask(width/8+x) <= hmask(x);
write_mask(x) <= dm(x);
end if;
end loop;
end loop;
end if;
end process;
end;
-- pragma translate_on
|
---------------------------------------
-- 7/JUL/2015 - Pedro Morales Hernandez
-- Modulo del Estimador
---------------------------------------
-- Importacion de librerias
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Declaracion de la Entidad
entity ESTIMADOR is PORT(
clk : IN STD_LOGIC; -- Reloj
rst : IN STD_LOGIC; -- Reset asincrono, activo a nivel alto
start : IN STD_LOGIC; -- Seal que indica el inicio del proceso de estimacion
fin : OUT STD_LOGIC; -- Seal que indica el fin de la estimacion
addr_y : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); -- Lectura de Simbolo
addr_h : OUT STD_LOGIC_VECTOR(10 DOWNTO 0); -- Escritura de Ecualizacion
y_data : IN STD_LOGIC_VECTOR(19 DOWNTO 0); -- Dato de Entrada
h_data : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); -- Dato de Salida
write_h : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)); -- Seal que indica que se escriba el dato
end ESTIMADOR;
architecture Behavioral of ESTIMADOR is
SUBTYPE addr IS STD_LOGIC_VECTOR(10 DOWNTO 0); -- Por si es necesario redefinir el tamao de las direcciones
-- Submodulos
COMPONENT PRBS IS
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable : in STD_LOGIC;
output : out STD_LOGIC);
END COMPONENT;
-- Tipos Complejos
TYPE complex10 IS RECORD -- De 10 bits
re: SIGNED(9 DOWNTO 0);
im: SIGNED(9 DOWNTO 0);
END RECORD;
TYPE complex12 IS RECORD -- De 12 bits
re: SIGNED(11 DOWNTO 0);
im: SIGNED(11 DOWNTO 0);
END RECORD;
TYPE context_t IS RECORD -- Almacena el estado del sistema
h_dir : addr; -- Direccion H (Estimacion)
y_dir : addr; -- Direccion Y (Simbolo)
valor : complex10; -- Valor calculado de un piloto
h_est : complex12; -- H estimada en una posicion
piloto_inf : complex10; -- Piloto Inferior
piloto_sup : complex10; -- Piloto Superior
modulo : INTEGER; -- Indica la posicion con respecto al piloto anterior (0-12)
END RECORD;
-- Esta funcion calcula el valor de un
-- piloto en funcion del valor actual del PRBS
FUNCTION CALCULA_H_PILOTO(piloto : complex10; prbs_val : STD_LOGIC) RETURN complex10 IS
VARIABLE H : complex10 := (re => (OTHERS => '0'), im => (OTHERS => '0'));
BEGIN
IF(prbs_val = '1') THEN -- Si vale 1, negamos el piloto, no es necesario escalar
H.re := -piloto.re;
H.im := -piloto.im;
ELSE -- Si vale 0 lo dejamos igual
H.re := piloto.re;
H.im := piloto.im;
END IF;
RETURN H;
END CALCULA_H_PILOTO;
-- Estados posibles
TYPE estados IS (reposo,ini_lee,ini_calcula,avance,lee,calcula,actualiza_piloto_1,actualiza_piloto_2,actualiza_piloto_3,escribe,terminado);
-- Reposo : El sistema se encuentra en reposo y no espera la seal START
-- ini_* : Proceso de inicializacion, para llevar el PRBS al valor deseado
-- ini_lee : Leemos de la memoria el valor de un piloto
-- ini_calcula : Calculamos el valor de H en esa posicion
-- avance : Avanzamos el PRBS sin realizar ninguna accion
-- lee : Esperamos si es necesario para leer un piloto, siempre se ejecuta
-- calcula: Calculamos el valor de un piloto en un punto dado
-- escribe: Escribimos el valor calculado en la memoria
-- actualiza_piloto_* : Nos permite actualizar el valor de los pilotos
-- terminado : Indica que el proceso ha finalizado exitosamente
SIGNAL p_context,context : context_t; -- Contexto actual y proximo
SIGNAL prbs_val,prbs_next: STD_LOGIC := '0'; -- Valores del PRBS
SIGNAL estado,p_estado : estados; -- Estado actual y proximo
BEGIN
-- Modelos Instanciados
prbs_c: COMPONENT PRBS
PORT MAP(
clk => clk,
rst => rst,
enable => prbs_next,
output => prbs_val
);
-- Conexiones de seales
addr_y <= context.y_dir;
addr_h <= context.h_dir;
-- Proceso Combinacional
comb : PROCESS(start,estado,context,y_data,prbs_val)
VARIABLE aux_re,aux_im : SIGNED(19 DOWNTO 0); -- Variables auxiliares para calcular el valor del canal
BEGIN
-- Valores por defecto en todos los estados
p_context <= context;
write_h <= "0";
prbs_next <= '0';
h_data <= (OTHERS => '0');
fin <= '0';
CASE estado IS
WHEN reposo =>
-- Inicializamos las variables a cero
p_context.h_dir <= (OTHERS => '0');
p_context.y_dir <= (OTHERS => '0');
p_context.piloto_inf <= (re => (OTHERS => '0'), im => (OTHERS => '0'));
p_context.piloto_sup <= (re => (OTHERS => '0'), im => (OTHERS => '0'));
p_context.h_est <= (re => (OTHERS => '0'), im => (OTHERS => '0'));
p_context.valor <= (re => (OTHERS => '0'), im => (OTHERS => '0'));
p_context.modulo <= 0;
-- Cambio de estado
IF(start = '1') THEN
p_estado <= ini_lee;
ELSE
p_estado <= reposo;
END IF;
WHEN ini_lee =>
p_context.valor.re <= SIGNED(y_data(19 DOWNTO 10)); -- Leemos una seal de la entrada
p_context.valor.im <= SIGNED(y_data(9 DOWNTO 0));
p_estado <= ini_calcula;
WHEN ini_calcula =>
p_context.piloto_sup <= CALCULA_H_PILOTO(context.valor,prbs_val);
p_context.piloto_inf <= context.piloto_sup; -- Actualizamos el contexto
IF(context.y_dir = STD_LOGIC_VECTOR(TO_UNSIGNED(12,11))) THEN -- Si estamos en la posicion 12
-- Fin de la inicializacion, vamos a la posicion 1
p_context.y_dir <= "00000000001";
p_context.h_dir <= "00000000001";
p_context.modulo <= 1; -- El modulo se inicia en 1
p_estado <= lee;
ELSE
p_context.y_dir <= STD_LOGIC_VECTOR(TO_UNSIGNED(12,11)); -- Vamos a la posicion 12
p_estado <= avance;
END IF;
WHEN avance =>
prbs_next <= '1'; -- Activamos el PRBS
p_context.h_dir <= STD_LOGIC_VECTOR(UNSIGNED(context.h_dir)+1);
p_context.modulo <= context.modulo + 1; -- Esto nos permite contar cuantas veces estamos en este estado
IF(context.modulo = 11) THEN -- 12 ciclos en total
p_estado <= ini_lee; -- Volvemos a ini_lee
ELSE
p_estado <= avance; -- Seguimos en avance
END IF;
WHEN lee =>
prbs_next <= '1'; -- Avanzamos el PRBS
IF(context.modulo = 12) THEN -- Si estamos en un piloto
p_context.modulo <= 0; -- Modulo a 0
IF(context.h_dir = STD_LOGIC_VECTOR(TO_UNSIGNED(1704,11))) THEN -- Si es la ultima posicion termina directamente
p_estado <= terminado;
ELSE
p_estado <= actualiza_piloto_1; -- Actualizamos en valor de los pilotos
END IF;
ELSE -- Si no estamos en un piloto
p_estado <= calcula;
END IF;
WHEN calcula =>
-- Calculamos el valor de los pilotos
aux_re := (12-context.modulo)*context.piloto_inf.re+context.modulo*context.piloto_sup.re;
aux_im := (12-context.modulo)*context.piloto_inf.im+context.modulo*context.piloto_sup.im;
p_context.h_est.re <= aux_re(13 DOWNTO 2);
p_context.h_est.im <= aux_im(13 DOWNTO 2);
p_estado <= escribe;
WHEN escribe =>
-- Escribimos el valor estimado
write_h <= "1";
h_data(23 DOWNTO 12) <= STD_LOGIC_VECTOR(context.h_est.re); -- Parte Real
h_data(11 DOWNTO 0) <= STD_LOGIC_VECTOR(context.h_est.im); -- Parte Imaginaria
IF(context.modulo = 11) THEN -- El siguiente ser un piloto
p_context.y_dir <= STD_LOGIC_VECTOR(UNSIGNED(context.y_dir)+13); -- Cargamos la direccion, ahorrando un ciclo
ELSE -- Si no, seguimos con el siguiente valor
p_context.y_dir <= STD_LOGIC_VECTOR(UNSIGNED(context.y_dir)+1);
END IF;
p_context.h_dir <= STD_LOGIC_VECTOR(UNSIGNED(context.h_dir)+1); -- Siguiente valor
p_context.modulo <= context.modulo + 1; -- Aumentamos el modulo en 1
p_estado <= lee; -- Siempre volvemos a lee
WHEN actualiza_piloto_1 =>
p_context.valor.re <= SIGNED(y_data(19 DOWNTO 10)); -- Leemos la parte Real
p_context.valor.im <= SIGNED(y_data(9 DOWNTO 0)); -- Leemos la parte Imaginaria
p_estado <= actualiza_piloto_2;
WHEN actualiza_piloto_2 =>
p_context.piloto_sup <= CALCULA_H_PILOTO(context.valor,prbs_val); -- Calculamos el valor del piloto
p_context.piloto_inf <= context.piloto_sup; -- Actualizamos los valores
p_estado <= actualiza_piloto_3;
WHEN actualiza_piloto_3 =>
p_context.y_dir <= STD_LOGIC_VECTOR(UNSIGNED(context.y_dir)-11); -- Vamos a la siguiente posicion y_dir-12+1
p_context.h_dir <= STD_LOGIC_VECTOR(UNSIGNED(context.h_dir)+1); -- Siguiente posicion
p_context.modulo <= 1; -- Reinicializamos el modulo
p_estado <= lee;
WHEN terminado =>
fin <= '1'; -- Indicamos FIN
p_estado <= reposo;
END CASE;
END PROCESS;
-- Proceso sincrono
sinc : PROCESS(clk,rst)
BEGIN
IF(rst = '1') THEN
estado <= reposo; -- Reset asincrono
context.h_dir <= (OTHERS => '0');
context.y_dir <= (OTHERS => '0');
context.valor <= (re => (OTHERS => '0'), im => (OTHERS => '0'));
context.h_est <= (re => (OTHERS => '0'), im => (OTHERS => '0'));
context.piloto_inf <= (re => (OTHERS => '0'), im => (OTHERS => '0'));
context.piloto_sup <= (re => (OTHERS => '0'), im => (OTHERS => '0'));
ELSIF(rising_edge(clk)) THEN
estado <= p_estado;
context <= p_context;
END IF;
END PROCESS;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:08:42 06/05/2016
-- Design Name:
-- Module Name: Unidad_de_Control - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Unidad_de_Control is
Port ( IR : in STD_LOGIC_VECTOR (7 downto 0);
clk : in STD_LOGIC;
sal_control : out STD_LOGIC_VECTOR (24 downto 0)
);
end Unidad_de_Control;
architecture Behavioral of Unidad_de_Control is
component Cntrl_cont is
port(
clk : in std_logic;
reset : in std_logic;
sal_cont : out std_logic_vector(2 downto 0)
);
end component;
component mem_control is
port(
IR: in std_logic_vector(7 downto 0);
CONT: in std_logic_vector(2 downto 0);
salida_mem_control: out std_logic_vector(24 downto 0)
);
end component;
signal sal_cont_temp: std_logic_vector(24 downto 0);
signal sal_contador_temp: std_logic_vector(2 downto 0);
signal rst : std_logic;
begin
rst <= sal_cont_temp(23);
c0: Cntrl_cont port map(clk, rst, sal_contador_temp);
mem0: mem_control port map(IR, sal_contador_temp, sal_cont_temp);
sal_control <= sal_cont_temp(24 downto 0);
end Behavioral;
|
-------------------------------------------------------------------------------
-- xps_timer_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_timer_v1_02_a;
use xps_timer_v1_02_a.all;
entity xps_timer_0_wrapper is
port (
CaptureTrig0 : in std_logic;
CaptureTrig1 : in std_logic;
GenerateOut0 : out std_logic;
GenerateOut1 : out std_logic;
PWM0 : out std_logic;
Interrupt : out std_logic;
Freeze : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 3);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrDBus : in std_logic_vector(0 to 31);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 31);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MWrErr : out std_logic_vector(0 to 1);
Sl_MRdErr : out std_logic_vector(0 to 1);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_MSize : in std_logic_vector(0 to 1);
PLB_lockErr : in std_logic;
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_wrBTerm : out std_logic;
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdBTerm : out std_logic;
Sl_MIRQ : out std_logic_vector(0 to 1)
);
attribute x_core_info : STRING;
attribute x_core_info of xps_timer_0_wrapper : entity is "xps_timer_v1_02_a";
end xps_timer_0_wrapper;
architecture STRUCTURE of xps_timer_0_wrapper is
component xps_timer is
generic (
C_FAMILY : STRING;
C_COUNT_WIDTH : INTEGER;
C_ONE_TIMER_ONLY : INTEGER;
C_TRIG0_ASSERT : std_logic;
C_TRIG1_ASSERT : std_logic;
C_GEN0_ASSERT : std_logic;
C_GEN1_ASSERT : std_logic;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_SPLB_AWIDTH : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_SPLB_P2P : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_SUPPORT_BURSTS : INTEGER;
C_SPLB_NATIVE_DWIDTH : INTEGER
);
port (
CaptureTrig0 : in std_logic;
CaptureTrig1 : in std_logic;
GenerateOut0 : out std_logic;
GenerateOut1 : out std_logic;
PWM0 : out std_logic;
Interrupt : out std_logic;
Freeze : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to C_SPLB_AWIDTH-1);
PLB_PAValid : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
PLB_UABus : in std_logic_vector(0 to C_SPLB_AWIDTH-1);
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_MSize : in std_logic_vector(0 to 1);
PLB_lockErr : in std_logic;
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_wrBTerm : out std_logic;
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdBTerm : out std_logic;
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1))
);
end component;
begin
xps_timer_0 : xps_timer
generic map (
C_FAMILY => "spartan6",
C_COUNT_WIDTH => 32,
C_ONE_TIMER_ONLY => 1,
C_TRIG0_ASSERT => '1',
C_TRIG1_ASSERT => '1',
C_GEN0_ASSERT => '1',
C_GEN1_ASSERT => '1',
C_BASEADDR => X"83c00000",
C_HIGHADDR => X"83c0ffff",
C_SPLB_AWIDTH => 32,
C_SPLB_DWIDTH => 32,
C_SPLB_P2P => 0,
C_SPLB_MID_WIDTH => 1,
C_SPLB_NUM_MASTERS => 2,
C_SPLB_SUPPORT_BURSTS => 0,
C_SPLB_NATIVE_DWIDTH => 32
)
port map (
CaptureTrig0 => CaptureTrig0,
CaptureTrig1 => CaptureTrig1,
GenerateOut0 => GenerateOut0,
GenerateOut1 => GenerateOut1,
PWM0 => PWM0,
Interrupt => Interrupt,
Freeze => Freeze,
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_PAValid => PLB_PAValid,
PLB_masterID => PLB_masterID,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrDBus => PLB_wrDBus,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_rdDBus => Sl_rdDBus,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
PLB_UABus => PLB_UABus,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_MSize => PLB_MSize,
PLB_lockErr => PLB_lockErr,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MIRQ => Sl_MIRQ
);
end architecture STRUCTURE;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkgen
-- File: clkgen.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Clock generator with tech selection
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
entity clkgen is
generic (
tech : integer := DEFFABTECH;
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 1;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000; -- clock frequency in KHz
clk2xen : integer := 0;
clksel : integer := 0; -- enable clock select
clk_odiv : integer := 1; -- Proasic3/Fusion output divider clkA
clkb_odiv: integer := 0; -- Proasic3/Fusion output divider clkB
clkc_odiv: integer := 0); -- Proasic3/Fusion output divider clkC
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic; -- unscaled 2X clock
clkb : out std_logic; -- Proasic3/Fusion clkB
clkc : out std_logic; -- Proasic3/Fusion clkC
clk8x : out std_logic); -- 8x clock
end;
architecture struct of clkgen is
signal intclk, sdintclk : std_ulogic;
signal lock : std_ulogic;
begin
gen : if (has_clkgen(tech) = 0) generate
sdintclk <= pciclkin when (PCISYSCLK = 1 and PCIEN /= 0) else clkin;
sdclk <= sdintclk; intclk <= sdintclk
-- pragma translate_off
after 1 ns -- create 1 ns skew between clk and sdclk
-- pragma translate_on
;
clk1xu <= intclk; pciclk <= pciclkin; clk <= intclk; clkn <= not intclk;
cgo.clklock <= '1'; cgo.pcilock <= '1'; clk2x <= '0'; clk4x <= '0';
clkb <= '0'; clkc <= '0'; clk8x <= '0';
end generate;
xc2v : if (tech = virtex2) or (tech = virtex4) generate
v : clkgen_virtex2
generic map (clk_mul, clk_div, sdramen, noclkfb, pcien, pcidll, pcisysclk, freq, clk2xen, clksel)
port map (clkin, pciclkin, clk, clkn, clk2x, sdclk, pciclk, cgi, cgo, clk1xu, clk2xu);
end generate;
xc5l : if (tech = virtex5) or (tech = virtex6) generate
v : clkgen_virtex5
generic map (clk_mul, clk_div, sdramen, noclkfb, pcien, pcidll, pcisysclk, freq, clk2xen, clksel)
port map (clkin, pciclkin, clk, clkn, clk2x, sdclk, pciclk, cgi, cgo, clk1xu, clk2xu);
end generate;
xc7l : if (tech =virtex7) or (tech =kintex7) or (tech =artix7) or (tech =zynq7000) generate
v : clkgen_virtex7
generic map (clk_mul, clk_div, freq)
port map (clkin, clk, clkn, clk2x ,cgi, cgo);
end generate;
xc3s : if (tech = spartan3) or (tech = spartan3e) or (tech = spartan6) generate
v : clkgen_spartan3
generic map (clk_mul, clk_div, sdramen, noclkfb, pcien, pcidll, pcisysclk, freq, clk2xen, clksel)
port map (clkin, pciclkin, clk, clkn, clk2x, sdclk, pciclk, cgi, cgo, clk1xu, clk2xu);
end generate;
alt : if (tech = altera) or (tech = stratix1) generate
v : clkgen_altera_mf
generic map (clk_mul, clk_div, sdramen, noclkfb, pcien, pcidll, pcisysclk, freq, clk2xen)
port map (clkin, pciclkin, clk, clkn, clk2x, sdclk, pciclk, cgi, cgo);
end generate;
strat2 : if (tech = stratix2) generate
v : clkgen_stratixii
generic map (clk_mul, clk_div, sdramen, noclkfb, pcien, pcidll, pcisysclk, freq, clk2xen)
port map (clkin, pciclkin, clk, clkn, clk2x, sdclk, pciclk, cgi, cgo);
end generate;
cyc3 : if (tech = cyclone3) generate
v : clkgen_cycloneiii
generic map (clk_mul, clk_div, sdramen, noclkfb, pcien, pcidll, pcisysclk, freq, clk2xen)
port map (clkin, pciclkin, clk, clkn, clk2x, sdclk, pciclk, cgi, cgo);
end generate;
stra3 : if (tech = stratix3) or (tech = stratix4) generate
v : clkgen_stratixiii
generic map (clk_mul, clk_div, sdramen, noclkfb, pcien, pcidll, pcisysclk, freq, clk2xen)
port map (clkin, pciclkin, clk, clkn, clk2x, sdclk, pciclk, cgi, cgo);
end generate;
act : if (tech = axdsp) or (tech = proasic) generate
intclk <= pciclkin when (PCISYSCLK = 1 and PCIEN /= 0) else clkin;
sdclk <= '0'; pciclk <= pciclkin; clk <= intclk; clkn <= '0';
cgo.clklock <= '1'; cgo.pcilock <= '1'; clk2x <= '0';
end generate;
axc : if (tech = axcel) generate
pll_disabled : if (clk_mul = clk_div) generate
intclk <= pciclkin when (PCISYSCLK = 1 and PCIEN /= 0) else clkin;
sdclk <= '0'; pciclk <= pciclkin; clk <= intclk; clkn <= '0';
cgo.clklock <= '1'; cgo.pcilock <= '1'; clk2x <= '0';
end generate;
pll_enabled : if (clk_mul /= clk_div) generate
clk2x <= '0';
pll : clkgen_axcelerator
generic map (
clk_mul => clk_mul,
clk_div => clk_div,
sdramen => sdramen,
sdinvclk => 0,
pcien => pcien,
pcidll => pcidll,
pcisysclk => pcisysclk,
freq => freq)
port map(
clkin => clkin,
pciclkin => pciclkin,
clk => clk,
clkn => clkn,
sdclk => sdclk,
pciclk => pciclk,
cgi => cgi,
cgo => cgo);
end generate;
end generate;
lib18t : if (tech = rhlib18t) generate
v : clkgen_rh_lib18t
generic map (clk_mul, clk_div)
port map (cgi.pllrst, intclk, clk, sdclk, clk2x, clk4x);
intclk <= pciclkin when (PCISYSCLK = 1 and PCIEN /= 0) else clkin;
pciclk <= pciclkin; clkn <= '0';
cgo.clklock <= '1'; cgo.pcilock <= '1';
end generate;
ap3 : if tech = apa3 generate
v : clkgen_proasic3
generic map (clk_mul, clk_div, clk_odiv, pcien, pcisysclk, freq, clkb_odiv, clkc_odiv)
port map (clkin, pciclkin, clk, sdclk, pciclk, cgi, cgo, clkb, clkc);
clk2x <= '0';
end generate;
ap3e : if tech = apa3e generate
v : clkgen_proasic3e
generic map (clk_mul, clk_div, clk_odiv, pcien, pcisysclk, freq, clkb_odiv, clkc_odiv)
port map (clkin, pciclkin, clk, sdclk, pciclk, cgi, cgo, clkb, clkc);
clk2x <= '0';
end generate;
ap3l : if tech = apa3l generate
v : clkgen_proasic3l
generic map (clk_mul, clk_div, clk_odiv, pcien, pcisysclk, freq, clkb_odiv, clkc_odiv)
port map (clkin, pciclkin, clk, sdclk, pciclk, cgi, cgo, clkb, clkc);
clk2x <= '0';
end generate;
fus : if tech = actfus generate
v : clkgen_fusion
generic map (clk_mul, clk_div, clk_odiv, pcien, pcisysclk, freq, clkb_odiv, clkc_odiv)
port map (clkin, pciclkin, clk, sdclk, pciclk, cgi, cgo, clkb, clkc);
clk2x <= '0';
end generate;
dr : if (tech = rhumc) generate
v : clkgen_rhumc
port map (clkin, clk, clk2x, sdclk, pciclk,
cgi, cgo, clk4x, clk1xu, clk2xu);
clk8x <= '0';
end generate;
saed : if (tech = saed32) generate
v : clkgen_saed32
port map (clkin, clk, clk2x, sdclk, pciclk,
cgi, cgo, clk4x, clk1xu, clk2xu);
end generate;
dar : if (tech = dare) generate
v : clkgen_dare
generic map (noclkfb)
port map (clkin, clk, clk2x, sdclk, pciclk,
cgi, cgo, clk4x, clk1xu, clk2xu, clk8x);
end generate;
nextreme90 : if tech = easic90 generate
pll0 : clkgen_easic90
generic map (
clk_mul => clk_mul,
clk_div => clk_div,
freq => freq,
pcisysclk => pcisysclk,
pcien => pcien)
port map (clkin, pciclkin, clk, clk2x, clk4x, clkn, lock);
cgo.clklock <= lock;
cgo.pcilock <= lock;
end generate;
n2x : if tech = easic45 generate
v : clkgen_n2x
generic map (clk_mul, clk_div, sdramen, noclkfb, pcien, pcidll,
pcisysclk, freq, clk2xen, clksel, 0)
port map (clkin, pciclkin, clk, clkn, clk2x, sdclk, pciclk, cgi,
cgo, clk1xu, clk2xu, open);
end generate;
ut13 : if (tech = ut130) generate
v : clkgen_ut130hbd
generic map (clk_mul, clk_div, sdramen, noclkfb, pcien, pcidll, pcisysclk, freq, clk2xen, clksel)
port map (clkin, pciclkin, clk, clkn, clk2x, clk4x, clk8x, sdclk, pciclk, cgi, cgo, clk1xu, clk2xu);
end generate;
ut90nhbd : if (tech = ut90) generate
v : clkgen_ut90nhbd
generic map (clk_mul, clk_div, sdramen, noclkfb, pcien, pcidll, pcisysclk, freq, clk2xen, clksel)
port map (clkin, pciclkin, clk, clkn, clk2x, sdclk, pciclk, cgi, cgo, clk1xu, clk2xu);
end generate;
end;
|
-------------------------------------------------------------------------------
-- qspi_core_interface Module - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_core_interface.vhd
-- Version: v3.0
-- Description: Serial Peripheral Interface (SPI) Module for interfacing
-- with a 32-bit AXI bus.
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.async_fifo_fg;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
library lib_cdc_v1_0_2;
use lib_cdc_v1_0_2.cdc_sync;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.all;
use lib_pkg_v1_0_2.lib_pkg.log2;
-- use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
use lib_pkg_v1_0_2.lib_pkg.RESET_ACTIVE;
library interrupt_control_v3_1_4;
library axi_quad_spi_v3_2_8;
use axi_quad_spi_v3_2_8.all;
-------------------------------------------------------------------------------
entity qspi_core_interface is
generic(
C_FAMILY : string;
C_SUB_FAMILY : string;
C_SELECT_XPM : integer := 1;
C_UC_FAMILY : integer;
C_S_AXI_DATA_WIDTH : integer;
Async_Clk : integer;
----------------------
-- local parameters
C_NUM_CE_SIGNALS : integer;
----------------------
-- SPI parameters
--C_AXI4_CLK_PS : integer;
--C_EXT_SPI_CLK_PS : integer;
C_FIFO_DEPTH : integer;
C_SCK_RATIO : integer;
C_NUM_SS_BITS : integer;
C_NUM_TRANSFER_BITS : integer;
C_SPI_MODE : integer;
C_USE_STARTUP : integer;
C_SPI_MEMORY : integer;
C_SHARED_STARTUP : integer range 0 to 1 := 0;
C_TYPE_OF_AXI4_INTERFACE : integer;
----------------------
-- local constants
C_FIFO_EXIST : integer;
C_SPI_NUM_BITS_REG : integer;
C_OCCUPANCY_NUM_BITS : integer;
----------------------
-- local constants
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE;
----------------------
-- local constants
C_SPICR_REG_WIDTH : integer;
C_SPISR_REG_WIDTH : integer;
C_LSB_STUP : integer
);
port(
EXT_SPI_CLK : in std_logic;
------------------------------------------------
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
------------------------------------------------
Bus2IP_BE : in std_logic_vector(0 to ((C_S_AXI_DATA_WIDTH/8)-1));
Bus2IP_RdCE : in std_logic_vector(0 to (C_NUM_CE_SIGNALS-1));
Bus2IP_WrCE : in std_logic_vector(0 to (C_NUM_CE_SIGNALS-1));
Bus2IP_Data : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
------------------------------------------------
IP2Bus_Data : out std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
IP2Bus_WrAck : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_Error : out std_logic;
------------------------------------------------
burst_tr : in std_logic;
rready : in std_logic;
WVALID : in std_logic;
--SPI Ports
SCK_I : in std_logic;
SCK_O : out std_logic;
SCK_T : out std_logic;
------------------------------------------------
IO0_I : in std_logic;
IO0_O : out std_logic;
IO0_T : out std_logic;
------------------------------------------------
IO1_I : in std_logic;
IO1_O : out std_logic;
IO1_T : out std_logic;
------------------------------------------------
IO2_I : in std_logic;
IO2_O : out std_logic;
IO2_T : out std_logic;
------------------------------------------------
IO3_I : in std_logic;
IO3_O : out std_logic;
IO3_T : out std_logic;
------------------------------------------------
SPISEL : in std_logic;
------------------------------------------------
SS_I : in std_logic_vector((C_NUM_SS_BITS-1) downto C_LSB_STUP);
SS_O : out std_logic_vector((C_NUM_SS_BITS-1) downto C_LSB_STUP);
SS_T : out std_logic;
------------------------------------------------
IP2INTC_Irpt : out std_logic;
------------------------------------------------
------------------------
-- STARTUP INTERFACE
------------------------
cfgclk : out std_logic; -- FGCLK , -- 1-bit output: Configuration main clock output
cfgmclk : out std_logic; -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
eos : out std_logic; -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
preq : out std_logic; -- REQ , -- 1-bit output: PROGRAM request to fabric output
di : out std_logic_vector(1 downto 0); -- output
dts : in std_logic_vector(1 downto 0); -- input
do : in std_logic_vector(1 downto 0); -- input
-- fcsbo : in std_logic; -- input
-- fcsbts : in std_logic; -- input
clk : in std_logic; -- input
gsr : in std_logic; -- input
gts : in std_logic; -- input
keyclearb : in std_logic; -- input
pack : in std_logic; -- input
usrcclkts : in std_logic; -- input
usrdoneo : in std_logic; -- input
usrdonets : in std_logic -- input
);
end entity qspi_core_interface;
-------------------------------------------------------------------------------
------------
architecture imp of qspi_core_interface is
------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- function definition
----------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- constant definition
constant NEW_LOGIC : integer := 0;
-- These constants are indices into the "CE" arrays for the various registers.
constant INTR_LO : natural := 0;
constant INTR_HI : natural := 15;
constant SWRESET : natural := 16; -- at address C_BASEADDR + 40 h
constant SPICR : natural := 24; -- 17; -- at address C_BASEADDR + 60 h
constant SPISR : natural := 25; -- 18;
constant SPIDTR : natural := 26; -- 19;
constant SPIDRR : natural := 27; -- 20;
constant SPISSR : natural := 28; -- 21;
constant SPITFOR : natural := 29; -- 22;
constant SPIRFOR : natural := 30; -- 23; -- at address C_BASEADDR + 78 h
constant REG_HOLE : natural := 31; -- 24; -- at address C_BASEADDR + 7C h
--Startup Signals
signal str_IO0_I : std_logic;
signal str_IO0_O : std_logic;
signal str_IO0_T : std_logic;
signal str_IO1_I : std_logic;
signal str_IO1_O : std_logic;
signal str_IO1_T : std_logic;
signal di_int : std_logic_vector(3 downto 0); -- output
signal di_int_sync : std_logic_vector(3 downto 0); -- output
signal dts_int : std_logic_vector(3 downto 0); -- input
signal do_int : std_logic_vector(3 downto 0); -- input
--SPI MODULE SIGNALS
signal spiXfer_done_int : std_logic;
signal dtr_underrun_int : std_logic;
signal modf_strobe_int : std_logic;
signal slave_MODF_strobe_int : std_logic;
--OR REGISTER/FIFO SIGNALS
--TO/FROM REG/FIFO DATA
signal receive_Data_int : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_int : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
--Extra bit required for signal Register_Data_ctrl
signal register_Data_cntrl_int :std_logic_vector(0 to (C_SPI_NUM_BITS_REG+1));
signal register_Data_slvsel_int:std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal IP2Bus_SPICR_Data_int :std_logic_vector(0 to (C_SPICR_REG_WIDTH-1));
signal IP2Bus_SPISR_Data_int :std_logic_vector(0 to (C_SPISR_REG_WIDTH-1));
signal IP2Bus_Receive_Reg_Data_int :std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal IP2Bus_Data_received_int:
std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
signal IP2Bus_SPISSR_Data_int : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal IP2Bus_Tx_FIFO_OCC_Reg_Data_int:
std_logic_vector(0 to (C_OCCUPANCY_NUM_BITS-1));
signal IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1:
std_logic_vector((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1:
std_logic_vector((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal IP2Bus_Rx_FIFO_OCC_Reg_Data_int:
std_logic_vector(0 to (C_OCCUPANCY_NUM_BITS-1));
--STATUS REGISTER SIGNALS
signal sr_3_MODF_int : std_logic;
signal Tx_FIFO_Full_int : std_logic;
signal sr_5_Tx_Empty_int : std_logic;
signal tx_empty_signal_handshake_req : std_logic;
signal tx_empty_signal_handshake_gnt : std_logic;
signal sr_6_Rx_Full_int : std_logic;
signal Rc_FIFO_Empty_int : std_logic;
--RECEIVE AND TRANSMIT REGISTER SIGNALS
signal drr_Overrun_int : std_logic;
signal dtr_Underrun_strobe_int : std_logic;
--FIFO SIGNALS
signal rc_FIFO_Full_strobe_int : std_logic;
signal rc_FIFO_occ_Reversed_int :std_logic_vector
((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal rc_FIFO_occ_Reversed_int_2 :std_logic_vector
((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal rc_FIFO_Data_Out_int : std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1));
signal sr_6_Rx_Full_int_1 : std_logic;
signal FIFO_Empty_rx_1 : std_logic;
signal FIFO_Empty_rx : std_logic;
signal data_Exists_RcFIFO_int : std_logic;
signal tx_FIFO_Empty_strobe_int : std_logic;
signal tx_FIFO_occ_Reversed_int : std_logic_vector
((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal tx_FIFO_occ_Reversed_int_2 : std_logic_vector
((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal data_Exists_TxFIFO_int : std_logic;
signal data_Exists_TxFIFO_int_1 : std_logic;
signal data_From_TxFIFO_int : std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1));
signal tx_FIFO_less_half_int : std_logic;
signal Tx_FIFO_Full_int_1 : std_logic;
signal FIFO_Empty_tx : std_logic;
signal data_From_TxFIFO_int_1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal tx_occ_msb : std_logic;
signal tx_occ_msb_1 : std_logic:= '0';
signal tx_occ_msb_2 : std_logic;
signal tx_occ_msb_3 : std_logic;
signal tx_occ_msb_4 : std_logic;
signal reset_TxFIFO_ptr_int : std_logic;
signal reset_TxFIFO_ptr_int_to_spi : std_logic;
signal reset_RcFIFO_ptr_int : std_logic;
signal reset_RcFIFO_ptr_to_spi_clk : std_logic;
signal ip2Bus_Data_Reg_int : std_logic_vector
(0 to (C_S_AXI_DATA_WIDTH-1));
signal ip2Bus_Data_occupancy_int: std_logic_vector
(0 to (C_S_AXI_DATA_WIDTH-1));
signal ip2Bus_Data_SS_int : std_logic_vector
(0 to (C_S_AXI_DATA_WIDTH-1));
-- interface between signals on instance basis
signal bus2IP_Reset_int : std_logic;
signal bus2IP_Data_for_interrupt_core : std_logic_vector
(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2Bus_Error_int : std_logic;
signal ip2Bus_WrAck_int : std_logic;-- := '0';
signal ip2Bus_RdAck_int : std_logic;-- := '0';
signal ip2Bus_IntrEvent_int : std_logic_vector
(0 to (C_IP_INTR_MODE_ARRAY'length-1));
signal transmit_ip2bus_error : std_logic;
signal receive_ip2bus_error : std_logic;
-- SOFT RESET SIGNALS
signal reset2ip_reset_int : std_logic;
signal rst_ip2bus_wrack : std_logic;
signal rst_ip2bus_error : std_logic;
signal rst_ip2bus_rdack : std_logic;
-- INTERRUPT SIGNALS
signal intr_ip2bus_data : std_logic_vector
(0 to (C_S_AXI_DATA_WIDTH-1));
signal intr_ip2bus_rdack : std_logic;
signal intr_ip2bus_wrack : std_logic;
signal intr_ip2bus_error : std_logic;
signal ip2bus_error_RdWr : std_logic;
--
signal wr_ce_reduce_ack_gen: std_logic;
--
signal rd_ce_reduce_ack_gen : std_logic;
--
signal control_bit_7_8_int : std_logic_vector(0 to 1);
signal spisel_pulse_o_int : std_logic;
signal Interrupt_WrCE_sig : std_logic_vector(0 to 1);
signal IPIF_Lvl_Interrupts_sig : std_logic;
signal spisel_d1_reg : std_logic;
signal Mst_N_Slv_mode : std_logic;
-----
signal bus2ip_intr_rdce : std_logic_vector(INTR_LO to INTR_HI);
signal bus2ip_intr_wrce : std_logic_vector(INTR_LO to INTR_HI);
signal ip2Bus_RdAck_intr_reg_hole : std_logic;
signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic;
signal ip2Bus_WrAck_intr_reg_hole : std_logic;
signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic;
signal intr_controller_rd_ce_or_reduce : std_logic;
signal intr_controller_wr_ce_or_reduce : std_logic;
signal wr_ce_or_reduce_core_cmb : std_logic;
signal ip2Bus_WrAck_core_reg_d1 : std_logic;
signal ip2Bus_WrAck_core_reg : std_logic;
signal rd_ce_or_reduce_core_cmb : std_logic;
signal ip2Bus_RdAck_core_reg_d1 : std_logic;
signal ip2Bus_RdAck_core_reg : std_logic;
signal SPISR_0_CMD_Error_int : std_logic;
signal SPISR_1_LOOP_Back_Error_int : std_logic;
signal SPISR_2_MSB_Error_int : std_logic;
signal SPISR_3_Slave_Mode_Error_int : std_logic;
signal SPISR_4_CPOL_CPHA_Error_int : std_logic;
signal SPISR_Ext_SPISEL_slave_int : std_logic;
signal SPICR_5_TXFIFO_RST_int : std_logic;
-- signal SPICR_6_RXFIFO_RST_int : std_logic;
signal pr_state_idle_int : std_logic;
signal Quad_Phase_int : std_logic;
signal SPICR_0_LOOP_frm_axi :std_logic;
signal SPICR_0_LOOP_to_spi :std_logic;
signal SPICR_1_SPE_frm_axi :std_logic;
signal SPICR_1_SPE_to_spi :std_logic;
signal SPICR_2_MST_N_SLV_frm_axi :std_logic;
signal SPICR_2_MST_N_SLV_to_spi :std_logic;
signal SPICR_3_CPOL_frm_axi :std_logic;
signal SPICR_3_CPOL_to_spi :std_logic;
signal SPICR_4_CPHA_frm_axi :std_logic;
signal SPICR_4_CPHA_to_spi :std_logic;
signal SPICR_5_TXFIFO_frm_axi :std_logic;
signal SPICR_5_TXFIFO_to_spi :std_logic;
--signal SPICR_6_RXFIFO_RST_frm_axi:std_logic;
--signal SPICR_6_RXFIFO_RST_to_spi :std_logic;
signal SPICR_7_SS_frm_axi :std_logic;
signal SPICR_7_SS_to_spi :std_logic;
signal SPICR_8_TR_INHIBIT_frm_axi:std_logic;
signal SPICR_8_TR_INHIBIT_to_spi :std_logic;
signal SPICR_9_LSB_frm_axi :std_logic;
signal SPICR_9_LSB_to_spi :std_logic;
signal SPICR_bits_7_8_frm_spi :std_logic;
signal SPICR_bits_7_8_to_axi :std_logic;
signal Rx_FIFO_Empty : std_logic;
signal Rx_FIFO_Empty_Synced_in_SPI_domain : std_logic;
signal rx_fifo_full_to_spi_clk : std_logic;
signal tx_fifo_empty_to_axi_clk : std_logic;
signal tx_fifo_full : std_logic;
signal spisel_d1_reg_to_axi_clk : std_logic;
signal spicr_bits_7_8_frm_axi_clk : std_logic_vector(1 downto 0);
signal spicr_8_tr_inhibit_to_spi_clk : std_logic;
signal spicr_9_lsb_to_spi_clk : std_logic;
signal spicr_bits_7_8_to_spi_clk : std_logic_vector(0 to 1);
signal spicr_0_loop_frm_axi_clk : std_logic;
signal spicr_1_spe_frm_axi_clk : std_logic;
signal spicr_2_mst_n_slv_frm_axi_clk : std_logic;
signal spicr_3_cpol_frm_axi_clk : std_logic;
signal spicr_4_cpha_frm_axi_clk : std_logic;
signal spicr_5_txfifo_rst_frm_axi_clk : std_logic;
signal spicr_6_rxfifo_rst_frm_axi_clk : std_logic;
signal spicr_7_ss_frm_axi_clk : std_logic;
signal spicr_8_tr_inhibit_frm_axi_clk : std_logic;
signal spicr_9_lsb_frm_axi_clk : std_logic;
signal Tx_FIFO_wr_ack_1 : std_logic;
signal rst_to_spi_int : std_logic;
signal spicr_0_loop_to_spi_clk : std_logic;
signal spicr_1_spe_to_spi_clk : std_logic;
signal spicr_2_mas_n_slv_to_spi_clk : std_logic;
signal spicr_3_cpol_to_spi_clk : std_logic;
signal spicr_4_cpha_to_spi_clk : std_logic;
signal spicr_5_txfifo_rst_to_spi_clk : std_logic;
signal spicr_6_rxfifo_rst_to_spi_clk : std_logic;
signal spicr_7_ss_to_spi_clk : std_logic;
signal sr_3_modf_to_spi_clk : std_logic;
signal sr_3_modf_frm_axi_clk : std_logic;
signal data_from_txfifo : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal Bus2IP_WrCE_d1 : std_logic;
signal Bus2IP_WrCE_d2 : std_logic;
signal Bus2IP_WrCE_d3 : std_logic;
signal Bus2IP_WrCE_pulse_1 : std_logic;
signal Bus2IP_WrCE_pulse_2 : std_logic;
signal Bus2IP_WrCE_pulse_3 : std_logic;
signal data_to_txfifo : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal tx_fifo_wr_ack : std_logic;
-- signal ext_spi_clk : std_logic;
signal tx_fifo_rd_ack_open : std_logic;
signal tx_fifo_empty : std_logic;
signal tx_fifo_almost_full : std_logic;
signal tx_fifo_almost_empty : std_logic;
signal tx_fifo_occ_reversed : std_logic_vector((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal c_wr_count_width : std_logic;
signal rx_fifo_wr_ack_open : std_logic;
signal data_from_rx_fifo : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal rx_fifo_rd_ack : std_logic;
signal rx_fifo_full : std_logic;
signal rx_fifo_almost_full : std_logic;
signal rx_fifo_almost_empty : std_logic;
signal rx_fifo_occ_reversed : std_logic_vector((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal SPISSR_frm_axi_clk : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal modf_strobe_frm_spi_clk : std_logic;
signal modf_strobe_to_axi_clk : std_logic;
signal dtr_underrun_frm_spi_clk : std_logic;
signal dtr_underrun_to_axi_clk : std_logic;
signal data_to_rx_fifo : std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1));
signal spisel_d1_reg_frm_spi_clk : std_logic;
signal Mst_N_Slv_mode_frm_spi_clk: std_logic;
signal Mst_N_Slv_mode_to_axi_clk : std_logic;
signal SPICR_2_MST_N_SLV_to_spi_clk : std_logic;
signal spicr_5_txfifo_frm_axi_clk : std_logic;
signal spicr_5_txfifo_to_spi_clk: std_logic;
signal reset_RcFIFO_ptr_frm_axi_clk : std_logic;
-- signal reset_RcFIFO_ptr_to_spi_clk : std_logic;
signal Data_To_Rx_FIFO_1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal SPIXfer_done_Rx_Wr_en, SPIXfer_done_rd_tx_en: std_logic;
signal Tx_FIFO_Empty_SPISR_frm_spi_clk : std_logic;
signal Tx_FIFO_Empty_SPISR_to_axi_clk : std_logic;
signal Tx_FIFO_Empty_frm_spi_clk : std_logic;
signal Rx_FIFO_Full_frm_axi_clk : std_logic;
signal Rx_FIFO_Full_int,Rx_FIFO_Full_i,RX_one_less_than_full, not_Tx_FIFO_FULL : std_logic;
signal updown_cnt_en_tx, updown_cnt_en_rx : std_logic;
signal TX_one_less_than_full : std_logic;
signal tx_cntr_xfer_done : std_logic;
signal Tx_FIFO_one_less_to_Empty, Tx_FIFO_Full_i: std_logic;
signal Tx_FIFO_Empty_i, Tx_FIFO_Empty_int : std_logic;
signal Tx_FIFO_Empty_frm_axi_clk : std_logic;
signal rx_fifo_empty_i : std_logic;
signal Rx_FIFO_Empty_int : std_logic;
signal IP2Bus_WrAck_1 : std_logic;
signal ip2Bus_WrAck_core_reg_1 : std_logic;
signal IP2Bus_RdAck_1 : std_logic;
signal ip2Bus_RdAck_core_reg_1 : std_logic;
signal IP2Bus_Error_1 : std_logic;
signal ip2Bus_Data_1 : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1)) ;
signal SPISR_0_CMD_Error_frm_spi_clk : std_logic;
signal SPISR_0_CMD_Error_to_axi_clk : std_logic;
signal rx_fifo_reset, tx_fifo_reset : std_logic;
signal reg_hole_wr_ack: std_logic;
signal reg_hole_rd_ack: std_logic;
signal read_ack_delay_1: std_logic;
signal read_ack_delay_2: std_logic;
signal read_ack_delay_3: std_logic;
signal read_ack_delay_4: std_logic;
signal read_ack_delay_5: std_logic;
signal read_ack_delay_6: std_logic;
signal read_ack_delay_7: std_logic;
signal read_ack_delay_8: std_logic;
signal write_ack_delay_1: std_logic;
signal write_ack_delay_2: std_logic;
signal write_ack_delay_3: std_logic;
signal write_ack_delay_4: std_logic;
signal write_ack_delay_5: std_logic;
signal write_ack_delay_6: std_logic;
signal write_ack_delay_7: std_logic;
signal write_ack_delay_8: std_logic;
signal error_ack_delay_1: std_logic;
signal error_ack_delay_2: std_logic;
signal error_ack_delay_3: std_logic;
signal error_ack_delay_4: std_logic;
signal error_ack_delay_5: std_logic;
signal error_ack_delay_6: std_logic;
signal error_ack_delay_7: std_logic;
signal error_ack_delay_8: std_logic;
signal IO2_O_int : std_logic;
signal IO2_T_int : std_logic;
signal IO3_O_int : std_logic;
signal IO3_T_int : std_logic;
signal IO2_I_int : std_logic;
signal IO3_I_int : std_logic;
signal fcsbo_int : std_logic;
signal SS_O_int : std_logic_vector((C_NUM_SS_BITS-1) downto 0);
signal SS_T_int : std_logic;
signal SS_I_int : std_logic_vector((C_NUM_SS_BITS-1) downto 0);
signal fcsbts_int : std_logic;
----RX_FIFO_FULL Logic signals
signal Rx_FIFO_Full_Fifo_org : std_logic;
signal Rx_FIFO_Full_Fifo : std_logic;
signal Rx_FIFO_Full_Fifo_d1 : std_logic;
signal Rx_FIFO_Full_Fifo_d1_synced : std_logic;
signal Rx_FIFO_Full_Fifo_d1_synced_i : std_logic;
signal Rx_FIFO_Full_Fifo_d1_flag : std_logic;
signal Rx_FIFO_Full_Fifo_pos_flag : std_logic;
signal Rx_FIFO_Full_Fifo_d1_sig : std_logic;
--------------------------------------------------------------------------------
begin
-----
DATA_STARTUP_EN : if (C_USE_STARTUP = 1 and C_UC_FAMILY = 1)
generate
-----
begin
-----
---
DI_INT_IO3_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => di_int_sync(3),
C => EXT_SPI_CLK,
D => di_int(3) --MOSI_I
);
DI_INT_IO2_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => di_int_sync(2),
C => EXT_SPI_CLK,
D => di_int(2) -- MISO_I
);
DI_INT_IO1_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => di_int_sync(1),
C => EXT_SPI_CLK,
D => di_int(1)
);
-----------------------
DI_INT_IO0_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => di_int_sync(0),
C => EXT_SPI_CLK,
D => di_int(0)
);
---
fcsbo_int <= SS_O_int(0);
fcsbts_int <= SS_T_int;
NUM_SS : if (C_NUM_SS_BITS = 1) generate
begin
SS_O <= (others => '0');
SS_T <= '0';
end generate NUM_SS;
NUM_SS_G1 : if (C_NUM_SS_BITS > 1) generate
begin
SS_I_int <= SS_I((C_NUM_SS_BITS-1) downto 1) & '1';
SS_O <= SS_O_int((C_NUM_SS_BITS-1) downto 1);
SS_T <= SS_T_int;
end generate NUM_SS_G1;
str_IO0_I <= di_int_sync(0);
do_int(0) <= str_IO0_O;
dts_int(0) <= str_IO0_T ;
str_IO1_I <= di_int_sync(1);
do_int(1) <= str_IO1_O;
dts_int(1) <= str_IO1_T;
DATA_OUT_NQUAD: if C_SPI_MODE = 0 or C_SPI_MODE = 1 generate
begin
di <= di_int_sync(3) & di_int_sync(2);
do_int(2) <= do(0);
do_int(3) <= do(1);
dts_int(2) <= dts(0);
dts_int(3) <= dts(1);
--do <= do_int(3) & do_int(1);
--dts <= dts_int(3) & dts_int(1);
end generate DATA_OUT_NQUAD;
DATA_OUT_QUAD: if C_SPI_MODE = 2 generate
begin
--di <= "00";--di_int_sync(3) & di_int_sync(2);
IO2_I_int <= di_int_sync(2);
do_int(2) <= IO2_O_int;--do(2);
do_int(3) <= IO3_O_int;--do(1);
--do <= do_int(3) & do_int(1);
IO3_I_int <= di_int_sync(3);
dts_int(2) <= IO2_T_int;--dts_int(3) & dts_int(1);
dts_int(3) <= IO3_T_int;--dts_int(3) & dts_int(1);
end generate DATA_OUT_QUAD;
end generate DATA_STARTUP_EN;
DATA_STARTUP_DIS : if (C_USE_STARTUP = 0 or (C_USE_STARTUP = 1 and C_UC_FAMILY = 0))
generate
-----
begin
-----
str_IO0_I <= IO0_I;
IO0_O <= str_IO0_O;
IO0_T <= str_IO0_T;
str_IO1_I <= IO1_I;
IO1_O <= str_IO1_O;
IO1_T <= str_IO1_T;
fcsbo_int <= '0';
fcsbts_int <= '0';
SS_O <= SS_O_int;
SS_T <= SS_T_int;
SS_I_int <= SS_I;
end generate DATA_STARTUP_DIS;
-----------------------------------
-- Combinatorial operations for SPI
-----------------------------------
---- A write to read only register wont have any effect on register.
---- The transaction is completed by generating WrAck only.
not_Tx_FIFO_FULL <= not Tx_FIFO_Full;
Interrupt_WrCE_sig <= "00";
IPIF_Lvl_Interrupts_sig <= '0';
LEGACY_MD_WR_RD_ACK_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
-----
begin
-----
-- A write to read only register wont have any effect on register.
-- The transaction is completed by generating WrAck only.
--------------------------------------------------------
-- IP2Bus_Error is generated under following conditions:
-- 1. If an full transmit register/FIFO is written into.
-- 2. If an empty receive register/FIFO is read from.
-- Due to software driver legacy, the register rule test is not applied to SPI.
--------------------------------------------------------
IP2Bus_Error_1 <= intr_ip2bus_error or
rst_ip2bus_error or
transmit_ip2bus_error or
receive_ip2bus_error;
REG_ERR_ACK_P:process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
IP2Bus_Error <= '0';
else
IP2Bus_Error <= IP2Bus_Error_1;
end if;
end if;
end process REG_ERR_ACK_P;
wr_ce_or_reduce_core_cmb <= Bus2IP_WrCE(SPISR) or -- read only register
Bus2IP_WrCE(SPIDRR) or -- read only register
(Bus2IP_WrCE(SPIDTR) and not_Tx_FIFO_FULL) or -- common to
-- spi_fifo_ifmodule_1 and
-- spi_receive_reg_1
-- (FROM TRANSMITTER) module
Bus2IP_WrCE(SPICR) or
Bus2IP_WrCE(SPISSR) or
Bus2IP_WrCE(SPITFOR)or -- locally generated
Bus2IP_WrCE(SPIRFOR)or -- locally generated
Bus2IP_WrCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_WrCE(17 to 23)); -- holes between reset end and start of SPICR register
--------------------------------------------------
WRITE_ACK_SPIDTR_REG_PROCESS: process(Bus2IP_Clk) is
---------------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
Bus2IP_WrCE_d1 <= '0';
Bus2IP_WrCE_d2 <= '0';
Bus2IP_WrCE_d3 <= '0';
else
Bus2IP_WrCE_d1 <= Bus2IP_WrCE(SPIDTR);
Bus2IP_WrCE_d2 <= Bus2IP_WrCE_d1;
Bus2IP_WrCE_d3 <= Bus2IP_WrCE_d2;
end if; end if;
end process WRITE_ACK_SPIDTR_REG_PROCESS;
Bus2IP_WrCE_pulse_1 <= Bus2IP_WrCE(SPIDTR) and not Bus2IP_WrCE_d1;
Bus2IP_WrCE_pulse_2 <= Bus2IP_WrCE_d1 and not Bus2IP_WrCE_d2;
Bus2IP_WrCE_pulse_3 <= Bus2IP_WrCE_d2 and not Bus2IP_WrCE_d3;
--end generate WR_ACK_OR_REDUCE_FIFO_1_GEN;
-----------------------------------------
-- WRITE_ACK_CORE_REG_PROCESS : The commong write ACK generation logic when FIFO is
-- ------------------------ not included in the design.
--------------------------------------------------
-- _____|-----|__________ wr_ce_or_reduce_fifo_no
-- ________|-----|_______ ip2Bus_WrAck_fifo_no_d1
-- ________|--|__________ ip2Bus_WrAck_fifo_no from common write ack register
-- this ack will be used in register files for
-- reference.
--------------------------------------------------
WRITE_ACK_CORE_REG_PROCESS: process(Bus2IP_Clk) is
---------------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_WrAck_core_reg_d1 <= '0';
ip2Bus_WrAck_core_reg <= '0';
ip2Bus_WrAck_core_reg_1 <= '0';
else
ip2Bus_WrAck_core_reg_d1 <= wr_ce_or_reduce_core_cmb;
ip2Bus_WrAck_core_reg <= wr_ce_or_reduce_core_cmb and
(not ip2Bus_WrAck_core_reg_d1);
ip2Bus_WrAck_core_reg_1 <= ip2Bus_WrAck_core_reg;
end if;
end if;
end process WRITE_ACK_CORE_REG_PROCESS;
-------------------------------------------------
-- internal logic uses this signal
wr_ce_reduce_ack_gen <= ip2Bus_WrAck_core_reg_1;
-------------------------------------------------
-- common WrAck to IPIF
IP2Bus_WrAck_1 <= intr_ip2bus_wrack or -- common
rst_ip2bus_wrack or -- common
ip2Bus_WrAck_intr_reg_hole or -- newly added to target the holes in register space
ip2Bus_WrAck_core_reg;-- or
--Tx_FIFO_wr_ack; -- newly added
REG_WR_ACK_P:process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
IP2Bus_WrAck <= '0';
else
IP2Bus_WrAck <= IP2Bus_WrAck_1;
end if;
end if;
end process REG_WR_ACK_P;
-------------------------------------------------
--end generate LEGACY_MD_WR_ACK_GEN;
-------------------------------------------------
--LEGACY_MD_RD_ACK_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
-----
--begin
-----
rd_ce_or_reduce_core_cmb <= Bus2IP_RdCE(SWRESET) or --common locally generated
Bus2IP_RdCE(SPIDTR) or --common locally generated
Bus2IP_RdCE(SPISR) or --common from status register
Bus2IP_RdCE(SPIDRR) or --common to
--spi_fifo_ifmodule_1
--and spi_receive_reg_1
--(FROM RECEIVER) module
Bus2IP_RdCE(SPICR) or --common spi_cntrl_reg_1
Bus2IP_RdCE(SPISSR) or --common spi_status_reg_1
Bus2IP_RdCE(SPITFOR) or --only for fifo_occu TX reg
Bus2IP_RdCE(SPIRFOR) or --only for fifo_occu RX reg
Bus2IP_RdCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_RdCE(17 to 23)); -- holes between reset end and start of SPICR register; --reg hole
-- READ_ACK_CORE_REG_PROCESS : The commong write ACK generation logic
--------------------------------------------------
-- _____|-----|__________ wr_ce_or_reduce_fifo_no
-- ________|-----|_______ ip2Bus_WrAck_fifo_no_d1
-- ________|--|__________ ip2Bus_WrAck_fifo_no from common write ack register
-- this ack will be used in register files for
-- reference.
--------------------------------------------------
READ_ACK_CORE_REG_PROCESS: process(Bus2IP_Clk) is
-------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_RdAck_core_reg_d1 <= '0';
ip2Bus_RdAck_core_reg <= '0';
ip2Bus_RdAck_core_reg_1 <= '0';
read_ack_delay_1 <= '0';
read_ack_delay_2 <= '0';
read_ack_delay_3 <= '0';
read_ack_delay_4 <= '0';
read_ack_delay_5 <= '0';
read_ack_delay_6 <= '0';
read_ack_delay_7 <= '0';
else
--ip2Bus_RdAck_core_reg_d1 <= rd_ce_or_reduce_core_cmb;
--ip2Bus_RdAck_core_reg <= rd_ce_or_reduce_core_cmb and
-- (not ip2Bus_RdAck_core_reg_d1);
read_ack_delay_1 <= rd_ce_or_reduce_core_cmb;
read_ack_delay_2 <= read_ack_delay_1;
read_ack_delay_3 <= read_ack_delay_2;
read_ack_delay_4 <= read_ack_delay_3;
read_ack_delay_5 <= read_ack_delay_4;
read_ack_delay_6 <= read_ack_delay_5;
read_ack_delay_7 <= read_ack_delay_6;
ip2Bus_RdAck_core_reg <= read_ack_delay_6 and (not read_ack_delay_7);
ip2Bus_RdAck_core_reg_1 <= ip2Bus_RdAck_core_reg;
end if;
end if;
end process READ_ACK_CORE_REG_PROCESS;
-------------------------------------------------
-- internal logic uses this signal
rd_ce_reduce_ack_gen <= ip2Bus_RdAck_core_reg;
-------------------------------------------------
-- common RdAck to IPIF
IP2Bus_RdAck_1 <= intr_ip2bus_rdack or -- common
ip2Bus_RdAck_intr_reg_hole or
ip2Bus_RdAck_core_reg;
REG_RD_ACK_P:process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
IP2Bus_RdAck <= '0';
else
IP2Bus_RdAck <= IP2Bus_RdAck_1;
end if;
end if;
end process REG_RD_ACK_P;
---------------------------------------------------
end generate LEGACY_MD_WR_RD_ACK_GEN;
-------------------------------------------------
ENHANCED_MD_WR_RD_ACK_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
-----
begin
-----
-- A write to read only register wont have any effect on register.
-- The transaction is completed by generating WrAck only.
--------------------------------------------------------
-- IP2Bus_Error is generated under following conditions:
-- 1. If an full transmit register/FIFO is written into.
-- 2. If an empty receive register/FIFO is read from.
-- Due to software driver legacy, the register rule test is not applied to SPI.
--------------------------------------------------------
IP2Bus_Error <= intr_ip2bus_error or
rst_ip2bus_error or
transmit_ip2bus_error or
receive_ip2bus_error;
wr_ce_or_reduce_core_cmb <= Bus2IP_WrCE(SPISR) or -- read only register
Bus2IP_WrCE(SPIDRR) or -- read only register
(Bus2IP_WrCE(SPIDTR) and not_Tx_FIFO_FULL) or -- common to
-- spi_fifo_ifmodule_1 and
-- spi_receive_reg_1
-- (FROM TRANSMITTER) module
Bus2IP_WrCE(SPICR) or
Bus2IP_WrCE(SPISSR) or
Bus2IP_WrCE(SPITFOR)or -- locally generated
Bus2IP_WrCE(SPIRFOR)or -- locally generated
Bus2IP_WrCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_WrCE(17 to 23)); -- holes between reset end and start of SPICR register; -- register hole
--------------------------------------------------
WRITE_ACK_SPIDTR_REG_PROCESS: process(Bus2IP_Clk) is
---------------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
Bus2IP_WrCE_d1 <= '0';
Bus2IP_WrCE_d2 <= '0';
Bus2IP_WrCE_d3 <= '0';
else
Bus2IP_WrCE_d1 <= Bus2IP_WrCE(SPIDTR);
Bus2IP_WrCE_d2 <= Bus2IP_WrCE_d1;
Bus2IP_WrCE_d3 <= Bus2IP_WrCE_d2;
end if; end if;
end process WRITE_ACK_SPIDTR_REG_PROCESS;
Bus2IP_WrCE_pulse_1 <= Bus2IP_WrCE(SPIDTR) and not Bus2IP_WrCE_d1;
Bus2IP_WrCE_pulse_2 <= Bus2IP_WrCE_d1 and not Bus2IP_WrCE_d2;
Bus2IP_WrCE_pulse_3 <= Bus2IP_WrCE_d2 and not Bus2IP_WrCE_d3;
-- WRITE_ACK_CORE_REG_PROCESS : The commong write ACK generation logic when FIFO is
-- ------------------------ not included in the design.
--------------------------------------------------
-- _____|-----|__________ wr_ce_or_reduce_fifo_no
-- ________|-----|_______ ip2Bus_WrAck_fifo_no_d1
-- ________|--|__________ ip2Bus_WrAck_fifo_no from common write ack register
-- this ack will be used in register files for
-- reference.
--------------------------------------------------
WRITE_ACK_CORE_REG_PROCESS: process(Bus2IP_Clk) is
---------------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_WrAck_core_reg_d1 <= '0';
ip2Bus_WrAck_core_reg <= '0';
ip2Bus_WrAck_core_reg_1 <= '0';
else
ip2Bus_WrAck_core_reg_d1 <= wr_ce_or_reduce_core_cmb;
ip2Bus_WrAck_core_reg <= wr_ce_or_reduce_core_cmb and
(not ip2Bus_WrAck_core_reg_d1);
ip2Bus_WrAck_core_reg_1 <= ip2Bus_WrAck_core_reg;
end if;
end if;
end process WRITE_ACK_CORE_REG_PROCESS;
-------------------------------------------------
-- internal logic uses this signal
wr_ce_reduce_ack_gen <= ip2Bus_WrAck_core_reg;--_1;
-------------------------------------------------
-- common WrAck to IPIF
-- in the enhanced mode for FIFO, the IP2bus_Wrack is provided by the enhanced mode statemachine only.
IP2Bus_WrAck <= intr_ip2bus_wrack or -- common
rst_ip2bus_wrack or -- common
ip2Bus_WrAck_intr_reg_hole or -- newly added to target the holes in register space
(ip2Bus_WrAck_core_reg and (not burst_tr));-- or
--(Tx_FIFO_wr_ack and burst_tr); -- newly added
-------------------------------------------------
--ENHANCED_MD_RD_ACK_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
-----
--begin
-----
FIFO_NO_RD_CE_GEN: if C_FIFO_EXIST = 0 generate
begin
rd_ce_or_reduce_core_cmb <= Bus2IP_RdCE(SWRESET) or --common locally generated
Bus2IP_RdCE(SPIDTR) or --common locally generated
Bus2IP_RdCE(SPISR) or --common from status register
Bus2IP_RdCE(SPIDRR) or --common to
--spi_fifo_ifmodule_1
--and spi_receive_reg_1
--(FROM RECEIVER) module
Bus2IP_RdCE(SPICR) or --common spi_cntrl_reg_1
Bus2IP_RdCE(SPISSR) or --common spi_status_reg_1
Bus2IP_RdCE(SPITFOR) or --only for fifo_occu TX reg
Bus2IP_RdCE(SPIRFOR) or --only for fifo_occu RX reg
Bus2IP_RdCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_RdCE(17 to 23)); -- holes between reset end and start of SPICR register; --reg hole
end generate FIFO_NO_RD_CE_GEN;
FIFO_YES_RD_CE_GEN: if C_FIFO_EXIST = 1 generate
begin
rd_ce_or_reduce_core_cmb <= Bus2IP_RdCE(SWRESET) or --common locally generated
Bus2IP_RdCE(SPIDTR) or --common locally generated
Bus2IP_RdCE(SPISR) or --common from status register
--Bus2IP_RdCE(SPIDRR) or --common to
--spi_fifo_ifmodule_1
--and spi_receive_reg_1
--(FROM RECEIVER) module
Bus2IP_RdCE(SPICR) or --common spi_cntrl_reg_1
Bus2IP_RdCE(SPISSR) or --common spi_status_reg_1
Bus2IP_RdCE(SPITFOR) or --only for fifo_occu TX reg
Bus2IP_RdCE(SPIRFOR) or --only for fifo_occu RX reg
Bus2IP_RdCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_RdCE(17 to 23)); -- holes between reset end and start of SPICR register; --reg hole
end generate FIFO_YES_RD_CE_GEN;
-- READ_ACK_CORE_REG_PROCESS : The commong write ACK generation logic
--------------------------------------------------
-- _____|-----|__________ wr_ce_or_reduce_fifo_no
-- ________|-----|_______ ip2Bus_WrAck_fifo_no_d1
-- ________|--|__________ ip2Bus_WrAck_fifo_no from common write ack register
-- this ack will be used in register files for
-- reference.
--------------------------------------------------
READ_ACK_CORE_REG_PROCESS: process(Bus2IP_Clk) is
-------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_RdAck_core_reg_d1 <= '0';
ip2Bus_RdAck_core_reg <= '0';
ip2Bus_RdAck_core_reg_1 <= '0';
read_ack_delay_1 <= '0';
read_ack_delay_2 <= '0';
read_ack_delay_3 <= '0';
read_ack_delay_4 <= '0';
read_ack_delay_5 <= '0';
read_ack_delay_6 <= '0';
read_ack_delay_7 <= '0';
else
--ip2Bus_RdAck_core_reg_d1 <= rd_ce_or_reduce_core_cmb;
--ip2Bus_RdAck_core_reg <= rd_ce_or_reduce_core_cmb and
-- (not ip2Bus_RdAck_core_reg_d1);
--ip2Bus_RdAck_core_reg_1 <= ip2Bus_RdAck_core_reg;
read_ack_delay_1 <= rd_ce_or_reduce_core_cmb;
read_ack_delay_2 <= read_ack_delay_1;
read_ack_delay_3 <= read_ack_delay_2;
read_ack_delay_4 <= read_ack_delay_3;
read_ack_delay_5 <= read_ack_delay_4;
read_ack_delay_6 <= read_ack_delay_5;
read_ack_delay_7 <= read_ack_delay_6;
ip2Bus_RdAck_core_reg <= read_ack_delay_6 and (not read_ack_delay_7);
ip2Bus_RdAck_core_reg_1 <= ip2Bus_RdAck_core_reg;
end if;
end if;
end process READ_ACK_CORE_REG_PROCESS;
-------------------------------------------------
-- internal logic uses this signal
rd_ce_reduce_ack_gen <= ip2Bus_RdAck_core_reg; --_1;
-------------------------------------------------
-- common RdAck to IPIF
IP2Bus_RdAck <= intr_ip2bus_rdack or -- common
ip2Bus_RdAck_intr_reg_hole or
ip2Bus_RdAck_core_reg or
(Rx_FIFO_rd_ack and rready);
-----------------------------------------------------
end generate ENHANCED_MD_WR_RD_ACK_GEN;
-------------------------------------------------
--=============================================================================
TX_FIFO_OCC_DATA_FIFO_16: if C_FIFO_DEPTH = 16 generate
-------------------------
begin
-----
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(0) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(0)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(1) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(1)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(2) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(2)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(3) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(3)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty); --(FIFO_Empty_tx);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(0) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(0)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(1) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(1)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(2) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(2)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(3) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(3)
and not (Rx_FIFO_Empty); --(FIFO_Empty_rx);
end generate TX_FIFO_OCC_DATA_FIFO_16;
--------------------------------------
TX_FIFO_OCC_DATA_FIFO_256: if C_FIFO_DEPTH = 256 generate
-------------------------
begin
-----
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(0) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(0)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(1) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(1)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(2) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(2)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(3) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(3)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(4) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(4)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(5) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(5)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(6) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(6)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(7) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(7)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);-- (FIFO_Empty_tx);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(0) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(0)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(1) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(1)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(2) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(2)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(3) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(3)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(4) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(4)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(5) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(5)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(6) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(6)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(7) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(7)
and not (Rx_FIFO_Empty); --(FIFO_Empty_rx);
end generate TX_FIFO_OCC_DATA_FIFO_256;
--*****************************************************************************
ip2Bus_Data_occupancy_int(0 to (C_S_AXI_DATA_WIDTH-C_OCCUPANCY_NUM_BITS-1))
<= (others => '0');
ip2Bus_Data_occupancy_int((C_S_AXI_DATA_WIDTH-C_OCCUPANCY_NUM_BITS)
to (C_S_AXI_DATA_WIDTH-1))
<= IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1 or
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1;
-------------------------------------------------------------------------------
-- SPECIAL_CASE_WHEN_SS_NOT_EQL_32 : The Special case is executed whenever
-- C_NUM_SS_BITS is less than 32
-------------------------------------------------------------------------------
SPECIAL_CASE_WHEN_SS_NOT_EQL_32: if(C_NUM_SS_BITS /= 32) generate
-----
begin
-----
ip2Bus_Data_SS_int(0 to (C_S_AXI_DATA_WIDTH-C_NUM_SS_BITS-1))
<= (others => '0');
end generate SPECIAL_CASE_WHEN_SS_NOT_EQL_32;
---------------------------------------------
ip2Bus_Data_SS_int((C_S_AXI_DATA_WIDTH-C_NUM_SS_BITS) to
(C_S_AXI_DATA_WIDTH-1)) <= IP2Bus_SPISSR_Data_int;
-------------------------------------------------------------------------------
ip2Bus_Data_Reg_int(0 to C_S_AXI_DATA_WIDTH-C_SPISR_REG_WIDTH-1) <= (others => '0');
ip2Bus_Data_Reg_int(C_S_AXI_DATA_WIDTH-C_SPISR_REG_WIDTH to C_S_AXI_DATA_WIDTH-1)
<= IP2Bus_SPISR_Data_int or -- SPISR - 11 bit
('0' & IP2Bus_SPICR_Data_int); -- SPICR - 10 bit
-------------------------------------------------------------------------------
-----------------------
Receive_Reg_width_is_32: if(C_NUM_TRANSFER_BITS = 32) generate
-----------------------
begin
-----
IP2Bus_Data_received_int <= IP2Bus_Receive_Reg_Data_int;
end generate Receive_Reg_width_is_32;
-----------------------------------------
---------------------------
Receive_Reg_width_is_not_32: if(C_NUM_TRANSFER_BITS /= 32) generate
---------------------------
begin
-----
IP2Bus_Data_received_int(0 to C_S_AXI_DATA_WIDTH-C_NUM_TRANSFER_BITS-1)
<= (others => '0');
IP2Bus_Data_received_int((C_S_AXI_DATA_WIDTH-C_NUM_TRANSFER_BITS) to
(C_S_AXI_DATA_WIDTH-1))
<= IP2Bus_Receive_Reg_Data_int;
end generate Receive_Reg_width_is_not_32;
-----------------------------------------
-------------------------------------------------------------------------------
LEGACY_MD_IP2BUS_DATA_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
-----
begin
-----
ip2Bus_Data_1 <= ip2Bus_Data_occupancy_int or -- occupancy reg data
ip2Bus_Data_SS_int or -- Slave select reg data
ip2Bus_Data_Reg_int or -- SPI CR & SR reg data
IP2Bus_Data_received_int or -- SPI received data
intr_ip2bus_data ;
REG_IP2BUS_DATA_P:process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_Data <= (others => '0');
else
ip2Bus_Data <= ip2Bus_Data_1;
end if;
end if;
end process REG_IP2BUS_DATA_P;
end generate LEGACY_MD_IP2BUS_DATA_GEN;
-------------------------------------------------------------------------------
ENHANCED_MD_IP2BUS_DATA_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
-----
begin
-----
ip2Bus_Data <= ip2Bus_Data_occupancy_int or -- occupancy reg data
ip2Bus_Data_SS_int or -- Slave select reg data
ip2Bus_Data_Reg_int or -- SPI CR & SR reg data
IP2Bus_Data_received_int or -- SPI received data
intr_ip2bus_data ;
end generate ENHANCED_MD_IP2BUS_DATA_GEN;
-------------------------------------------------------------------------------
RESET_SYNC_AXI_SPI_CLK_INST:entity axi_quad_spi_v3_2_8.reset_sync_module
port map(
EXT_SPI_CLK => EXT_SPI_CLK ,-- in std_logic;
--Bus2IP_Clk => Bus2IP_Clk ,-- in std_logic;
Soft_Reset_frm_axi => reset2ip_reset_int,-- in std_logic;
Rst_to_spi => Rst_to_spi_int -- out std_logic;
);
--------------------------------------
-- NO_FIFO_EXISTS : Signals initialisation and module
-- instantiation when C_FIFO_EXIST = 0
--------------------------------------
NO_FIFO_EXISTS: if(C_FIFO_EXIST = 0) generate
----------------------------------
signal spisel_pulse_frm_spi_clk : std_logic;
signal spisel_pulse_to_axi_clk : std_logic;
signal spiXfer_done_frm_spi_clk : std_logic;
signal spiXfer_done_to_axi_clk : std_logic;
signal modf_strobe_frm_spi_clk : std_logic;
-- signal modf_strobe_to_axi_clk : std_logic;
signal slave_MODF_strobe_frm_spi_clk : std_logic;
signal slave_MODF_strobe_to_axi_clk : std_logic;
signal receive_data_frm_spi_clk : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal receive_data_to_axi_clk : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_frm_axi_clk: std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_to_spi_clk : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_fifo_0 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal drr_Overrun_int_frm_spi_clk: std_logic;
signal drr_Overrun_int_to_axi_clk : std_logic;
-----
begin
-----
Rx_FIFO_rd_ack <= '0';
Tx_FIFO_Full <= '0';
--------------------------------------------------------------------------
-- I_RECEIVE_REG : INSTANTIATE RECEIVE REGISTER
--------------------------------------------------------------------------
QSPI_RX_TX_REG: entity axi_quad_spi_v3_2_8.qspi_receive_transmit_reg
generic map
(
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS
)
port map
(
Bus2IP_Clk => Bus2IP_Clk, -- in
Soft_Reset_op => reset2ip_reset_int, -- in
--SPI Receiver signals -- From AXI clock
Bus2IP_Receive_Reg_RdCE => Bus2IP_RdCE(SPIDRR), -- in
Receive_ip2bus_error => receive_ip2bus_error, -- out
IP2Bus_Receive_Reg_Data => IP2Bus_Receive_Reg_Data_int, -- out
--SPI module ports From SPI clock
SPIXfer_done => spiXfer_done_to_axi_clk,--spiXfer_done_int,-- in
SPI_Received_Data => receive_data_to_axi_clk,--receive_Data_int,-- in vec
-- receive & transmit reg signals
-- DRR_Overrun => drr_Overrun_int,-- drr_Overrun_int,-- out
SR_7_Rx_Empty => Rx_FIFO_Empty_i, -- out
-- From AXI clock
Bus2IP_Transmit_Reg_Data=> Bus2IP_Data, -- in vec
Bus2IP_Transmit_Reg_WrCE=> Bus2IP_WrCE(SPIDTR), -- in
Wr_ce_reduce_ack_gen => wr_ce_reduce_ack_gen, -- in
Rd_ce_reduce_ack_gen => rd_ce_reduce_ack_gen, -- in
--SPI Transmitter signals from AXI clock
Transmit_ip2bus_error => transmit_ip2bus_error, -- out
--SPI module ports
DTR_underrun => dtr_underrun_to_axi_clk,--dtr_underrun_int,-- in
SR_5_Tx_Empty => sr_5_Tx_Empty_int, -- out
tx_empty_signal_handshake_req => tx_empty_signal_handshake_req, -- out
tx_empty_signal_handshake_gnt => tx_empty_signal_handshake_gnt, -- in
DTR_Underrun_strobe => dtr_Underrun_strobe_int, -- out
Transmit_Reg_Data_Out => transmit_Data_fifo_0--transmit_Data_int -- out vec
);
spisel_d1_reg_frm_spi_clk <= spisel_d1_reg;
spisel_pulse_frm_spi_clk <= spisel_pulse_o_int;-- from SPI module
spiXfer_done_frm_spi_clk <= spiXfer_done_int ;-- from SPI module
modf_strobe_frm_spi_clk <= modf_strobe_int ;-- from SPI module
slave_MODF_strobe_frm_spi_clk <= slave_MODF_strobe_int;-- from SPI module
receive_data_frm_spi_clk <= Data_To_Rx_FIFO ; -- from SPI module
dtr_underrun_frm_spi_clk <= dtr_underrun_int; -- from SPI module
transmit_Data_frm_axi_clk <= transmit_Data_fifo_0; -- From AXI clock
Tx_FIFO_Empty_frm_axi_clk <= sr_5_Tx_Empty_int;
Tx_FIFO_Empty_SPISR_frm_spi_clk <= sr_5_Tx_Empty_int;
--Rx_FIFO_Empty_int <= Rx_FIFO_Empty;
Rx_FIFO_Empty_int <= Rx_FIFO_Empty_i;
drr_Overrun_int_frm_spi_clk <= drr_Overrun_int;
SR_3_modf_frm_axi_clk <= SR_3_modf_int;
CROSS_CLK_FIFO_0_INST:entity axi_quad_spi_v3_2_8.cross_clk_sync_fifo_0
generic map(
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS,
Async_Clk => Async_Clk ,
--C_AXI_SPI_CLK_EQ_DIFF => C_AXI_SPI_CLK_EQ_DIFF,
C_NUM_SS_BITS => C_NUM_SS_BITS
)
port map(
EXT_SPI_CLK => EXT_SPI_CLK,
Bus2IP_Clk => Bus2IP_Clk ,
Soft_Reset_op => reset2ip_reset_int,
Rst_from_axi_cdc_to_spi => Rst_to_spi_int, -- out std_logic;
----------------------------------------------------------
tx_empty_signal_handshake_req => tx_empty_signal_handshake_req,
tx_empty_signal_handshake_gnt => tx_empty_signal_handshake_gnt,
Tx_FIFO_Empty_cdc_from_axi => Tx_FIFO_Empty_frm_axi_clk,
Tx_FIFO_Empty_cdc_to_spi => Tx_FIFO_Empty,
----------------------------------------------------------
Tx_FIFO_Empty_SPISR_cdc_from_spi => Tx_FIFO_Empty_SPISR_frm_spi_clk,
Tx_FIFO_Empty_SPISR_cdc_to_axi => Tx_FIFO_Empty_SPISR_to_axi_clk,
----------------------------------------------------------
spisel_d1_reg_cdc_from_spi => spisel_d1_reg_frm_spi_clk , -- in
spisel_d1_reg_cdc_to_axi => spisel_d1_reg_to_axi_clk , -- out
----------------------------------------------------------
spisel_pulse_cdc_from_spi => spisel_pulse_frm_spi_clk , -- in
spisel_pulse_cdc_to_axi => spisel_pulse_to_axi_clk , -- out
----------------------------------------------------------
spiXfer_done_cdc_from_spi => spiXfer_done_frm_spi_clk , -- in
spiXfer_done_cdc_to_axi => spiXfer_done_to_axi_clk , -- out
----------------------------------------------------------
modf_strobe_cdc_from_spi => modf_strobe_frm_spi_clk, -- in
modf_strobe_cdc_to_axi => modf_strobe_to_axi_clk , -- out
----------------------------------------------------------
Slave_MODF_strobe_cdc_from_spi => slave_MODF_strobe_frm_spi_clk,-- in
Slave_MODF_strobe_cdc_to_axi => slave_MODF_strobe_to_axi_clk ,-- out
----------------------------------------------------------
receive_Data_cdc_from_spi => receive_Data_frm_spi_clk, -- in
receive_Data_cdc_to_axi => receive_data_to_axi_clk, -- out
----------------------------------------------------------
drr_Overrun_int_cdc_from_spi => drr_Overrun_int_frm_spi_clk, -- in
drr_Overrun_int_cdc_to_axi => drr_Overrun_int_to_axi_clk, -- out
----------------------------------------------------------
dtr_underrun_cdc_from_spi => dtr_underrun_frm_spi_clk, -- in
dtr_underrun_cdc_to_axi => dtr_underrun_to_axi_clk, -- out
----------------------------------------------------------
transmit_Data_cdc_from_axi => transmit_Data_frm_axi_clk, -- in
transmit_Data_cdc_to_spi => transmit_Data_to_spi_clk, -- out
----------------------------
SPICR_0_LOOP_cdc_from_axi => SPICR_0_LOOP_frm_axi_clk,-- in std_logic;
SPICR_0_LOOP_cdc_to_spi => SPICR_0_LOOP_to_spi_clk ,-- out
----------------------------
SPICR_1_SPE_cdc_from_axi => SPICR_1_SPE_frm_axi_clk ,-- in std_logic;
SPICR_1_SPE_cdc_to_spi => SPICR_1_SPE_to_spi_clk ,-- out
----------------------------
SPICR_2_MST_N_SLV_cdc_from_axi => SPICR_2_MST_N_SLV_frm_axi_clk,-- in std_logic;
SPICR_2_MST_N_SLV_cdc_to_spi => SPICR_2_MST_N_SLV_to_spi_clk, -- out
----------------------------
SPICR_3_CPOL_cdc_from_axi => SPICR_3_CPOL_frm_axi_clk,-- in std_logic;
SPICR_3_CPOL_cdc_to_spi => SPICR_3_CPOL_to_spi_clk ,-- out
----------------------------
SPICR_4_CPHA_cdc_from_axi => SPICR_4_CPHA_frm_axi_clk,-- in std_logic;
SPICR_4_CPHA_cdc_to_spi => SPICR_4_CPHA_to_spi_clk ,-- out
----------------------------
SPICR_5_TXFIFO_cdc_from_axi => SPICR_5_TXFIFO_frm_axi_clk,-- in std_logic;
SPICR_5_TXFIFO_cdc_to_spi => SPICR_5_TXFIFO_to_spi_clk, -- out
----------------------------
SPICR_6_RXFIFO_RST_cdc_from_axi=> SPICR_6_RXFIFO_RST_frm_axi_clk,-- in std_logic;
SPICR_6_RXFIFO_RST_cdc_to_spi => SPICR_6_RXFIFO_RST_to_spi_clk ,-- out
----------------------------
SPICR_7_SS_cdc_from_axi => SPICR_7_SS_frm_axi_clk ,-- in std_logic;
SPICR_7_SS_cdc_to_spi => SPICR_7_SS_to_spi_clk ,-- out
----------------------------
SPICR_8_TR_INHIBIT_cdc_from_axi=> SPICR_8_TR_INHIBIT_frm_axi_clk,-- in std_logic;
SPICR_8_TR_INHIBIT_cdc_to_spi => SPICR_8_TR_INHIBIT_to_spi_clk,-- out
----------------------------
SPICR_9_LSB_cdc_from_axi => SPICR_9_LSB_frm_axi_clk,-- in std_logic;
SPICR_9_LSB_cdc_to_spi => SPICR_9_LSB_to_spi_clk,-- out
----------------------------
SPICR_bits_7_8_cdc_from_axi => SPICR_bits_7_8_frm_axi_clk,-- in std_logic_vector
SPICR_bits_7_8_cdc_to_spi => SPICR_bits_7_8_to_spi_clk,-- out
----------------------------
SR_3_modf_cdc_from_axi => SR_3_modf_frm_axi_clk, -- in
SR_3_modf_cdc_to_spi => SR_3_modf_to_spi_clk , -- out
----------------------------
SPISSR_cdc_from_axi => SPISSR_frm_axi_clk, -- in
SPISSR_cdc_to_spi => register_Data_slvsel_int -- out
----------------------------
);
Data_From_TxFIFO <= transmit_Data_to_spi_clk;
rc_FIFO_Full_strobe_int <= '0';
rc_FIFO_occ_Reversed_int <= (others => '0');
rc_FIFO_Data_Out_int <= (others => '0');
data_Exists_RcFIFO_int <= '0';
tx_FIFO_Empty_strobe_int <= '0';
tx_FIFO_occ_Reversed_int <= (others => '0');
data_Exists_TxFIFO_int <= '0';
data_From_TxFIFO_int <= (others => '0');
tx_FIFO_less_half_int <= '0';
reset_TxFIFO_ptr_int <= '0';
reset_RcFIFO_ptr_int <= '0';
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1 <= (others => '0');
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1 <= (others => '0');
Tx_FIFO_Full_int <= not(sr_5_Tx_Empty_int); -- Tx_FIFO_Empty_to_axi_clk);
Rx_FIFO_Full_int <= not(Rx_FIFO_Empty_i);
Rx_FIFO_Full_Fifo <= not(Rx_FIFO_Empty_i);
Rx_FIFO_Full_Fifo_d1_synced <= not(Rx_FIFO_Empty_i);
--------------------------------------------------------------------------
bus2IP_Data_for_interrupt_core(0 to 14) <= Bus2IP_Data(0 to 14);
bus2IP_Data_for_interrupt_core(15 to 22) <= (others => '0');
-- below code manipulates the bus2ip_data going towards interrupt control
-- unit. In FIFO=0, case bit 23 and 25 of IPIER are not applicable.
-- Bu2IP Data to Interrupt Registers - IPISR and IPIER
-- Bus2IP_Data - 0 31
-- IPISR/IPIER - 0 22 23 31
-- <---NA---> <-used->
-- 23 24 25 26 27 28 29 30 31
-- DRR_Not Slave Tx_FIFO DRR_ DRR_ DTR_ DTR Slave MODF
-- _Empty Select_mode Half_Empty Over_Run Full Underrun Empty MODF
-- NA-fifo-0 NA -fifo-0
bus2IP_Data_for_interrupt_core(23) <= '0'; -- DRR_Not_Empty bit in IPIER/IPISR
bus2IP_Data_for_interrupt_core(24) <= Bus2IP_Data(24);
bus2IP_Data_for_interrupt_core(25) <= '0'; -- Tx FIFO Half Empty
bus2IP_Data_for_interrupt_core(26 to (C_S_AXI_DATA_WIDTH-1)) <=
Bus2IP_Data(26 to (C_S_AXI_DATA_WIDTH-1));
--------------------------------------------------------------------------
-- Interrupt Status Register(IPISR) Mapping
ip2Bus_IntrEvent_int(13) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(12) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(11) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(10) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(9) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(8) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(7) <= spisel_pulse_to_axi_clk; -- spisel_pulse_o_int;
ip2Bus_IntrEvent_int(6) <= '0'; --
ip2Bus_IntrEvent_int(5) <= drr_Overrun_int_to_axi_clk; -- drr_Overrun_int_to_axi_clk;
ip2Bus_IntrEvent_int(4) <= spiXfer_done_to_axi_clk; -- spiXfer_done_int;
ip2Bus_IntrEvent_int(3) <= dtr_Underrun_strobe_int;
ip2Bus_IntrEvent_int(2) <= spiXfer_done_to_axi_clk; -- spiXfer_done_int;
ip2Bus_IntrEvent_int(1) <= slave_MODF_strobe_to_axi_clk; -- slave_MODF_strobe_int;
ip2Bus_IntrEvent_int(0) <= modf_strobe_to_axi_clk; -- modf_strobe_int;
end generate NO_FIFO_EXISTS;
-------------------------------------------------------------------------------
-- FIFO_EXISTS : Signals initialisation and module
-- instantiation when C_FIFO_EXIST = 1
-------------------------------------------------------------------------------
FIFO_EXISTS: if(C_FIFO_EXIST = 1) generate
------------------------------
constant C_RD_COUNT_WIDTH_INT : integer := clog2(C_FIFO_DEPTH);
constant C_WR_COUNT_WIDTH_INT : integer := clog2(C_FIFO_DEPTH);
constant RX_FIFO_CNTR_WIDTH: integer := clog2(C_FIFO_DEPTH);
constant TX_FIFO_CNTR_WIDTH: integer := clog2(C_FIFO_DEPTH);
constant ZERO_RX_FIFO_CNT : std_logic_vector(RX_FIFO_CNTR_WIDTH-1 downto 0) := (others => '0');
constant ZERO_TX_FIFO_CNT : std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0) := (others => '0');
signal rx_fifo_count: std_logic_vector(RX_FIFO_CNTR_WIDTH-1 downto 0);
signal tx_fifo_count: std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0);
signal tx_fifo_count_d1: std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0);
signal tx_fifo_count_d2: std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0);
signal Tx_FIFO_Empty_1 : std_logic;
signal Tx_FIFO_Empty_intr : std_logic;
signal IP2Bus_RdAck_receive_enable : std_logic;
signal IP2Bus_WrAck_transmit_enable : std_logic;
constant ALL_0 : std_logic_vector(0 to TX_FIFO_CNTR_WIDTH-1)
:= (others => '1');
signal data_Exists_RcFIFO_int_d1: std_logic;
signal data_Exists_RcFIFO_pulse : std_logic;
--signal FIFO_Empty_rx : std_logic;
--signal SPISR_0_CMD_Error_frm_spi_clk : std_logic;
--signal SPISR_0_CMD_Error_to_axi_clk : std_logic;
--signal spisel_d1_reg_frm_spi_clk : std_logic;
--signal spisel_d1_reg_to_axi_clk : std_logic;
signal tx_occ_msb_111 : std_logic:= '0';
signal tx_occ_msb_11 : std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0);
signal spisel_pulse_frm_spi_clk : std_logic;
signal spisel_pulse_to_axi_clk : std_logic;
signal slave_MODF_strobe_frm_spi_clk : std_logic;
signal slave_MODF_strobe_to_axi_clk : std_logic;
signal Rx_FIFO_Empty_frm_axi_clk : std_logic;
signal Rx_FIFO_Empty_to_spi_clk : std_logic;
signal Tx_FIFO_Full_frm_axi_clk : std_logic;
signal Tx_FIFO_Full_to_spi_clk : std_logic;
signal spiXfer_done_frm_spi_clk : std_logic;
signal spiXfer_done_to_axi_clk : std_logic;
signal SR_3_modf_frm_axi_clk : std_logic;
signal spiXfer_done_to_axi_1 : std_logic;
signal spiXfer_done_to_axi_d1 : std_logic;
signal updown_cnt_en : std_logic;
signal drr_Overrun_int_to_axi_clk : std_logic;
signal drr_Overrun_int_frm_spi_clk: std_logic;
-----
begin
-----
SPISR_0_CMD_Error_frm_spi_clk <= SPISR_0_CMD_Error_int;
spisel_d1_reg_frm_spi_clk <= spisel_d1_reg;
spisel_pulse_frm_spi_clk <= spisel_pulse_o_int;-- from SPI module
slave_MODF_strobe_frm_spi_clk <= slave_MODF_strobe_int; -- from SPI module
modf_strobe_frm_spi_clk <= modf_strobe_int; -- spi module
--Rx_FIFO_Full_frm_axi_clk <= Rx_FIFO_Full; -- from Async Receive FIFO
----RX_FIFO_FULL Logic signals
Rx_FIFO_Full_frm_axi_clk <= Rx_FIFO_Full_Fifo; -- from Async Receive FIFO
Tx_FIFO_Empty_frm_spi_clk <= Tx_FIFO_Empty_intr; -- Tx_FIFO_Empty; -- from Async Transmit FIFO
spiXfer_done_frm_spi_clk <= spiXfer_done_int; -- from SPI module
dtr_underrun_frm_spi_clk <= dtr_underrun_int; -- from SPI module
Tx_FIFO_Empty_SPISR_frm_spi_clk <= Tx_FIFO_Empty;-- from TX FIFO for SPI Status register
drr_Overrun_int_frm_spi_clk <= drr_Overrun_int;
-- SPICR_6_RXFIFO_RST_frm_axi_clk<= SPICR_6_RXFIFO_RST_frm_axi_clk; -- from SPICR
reset_RcFIFO_ptr_frm_axi_clk <= reset_RcFIFO_ptr_int; -- from AXI clock
Rx_FIFO_Empty_frm_axi_clk <= Rx_FIFO_Empty; -- from Async Receive FIFO AXI side
Tx_FIFO_Full_frm_axi_clk <= Tx_FIFO_Full; -- from Async Transmit FIFO AXI side
SR_3_modf_frm_axi_clk <= SR_3_modf_int;
--CLK_CROSS_I:
CLK_CROSS_I:entity axi_quad_spi_v3_2_8.cross_clk_sync_fifo_1
generic map(
C_FAMILY => C_FAMILY ,
C_FIFO_DEPTH => C_FIFO_DEPTH ,
Async_Clk => Async_Clk ,
C_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS,
C_NUM_SS_BITS => C_NUM_SS_BITS
)
port map(
EXT_SPI_CLK => EXT_SPI_CLK , -- in std_logic;
Bus2IP_Clk => Bus2IP_Clk , -- in std_logic;
Soft_Reset_op => reset2ip_reset_int ,
--Soft_Reset_op => Soft_Reset_op , -- in std_logic;
Rst_cdc_to_spi => Rst_to_spi_int , -- out std_logic;
----------------------------
SPISR_0_CMD_Error_cdc_from_spi => SPISR_0_CMD_Error_frm_spi_clk ,
SPISR_0_CMD_Error_cdc_to_axi => SPISR_0_CMD_Error_to_axi_clk ,
----------------------------------------------------------
spisel_d1_reg_cdc_from_spi => spisel_d1_reg_frm_spi_clk , -- in
spisel_d1_reg_cdc_to_axi => spisel_d1_reg_to_axi_clk , -- out
----------------------------------------------------------
spisel_pulse_cdc_from_spi => spisel_pulse_frm_spi_clk , -- in
spisel_pulse_cdc_to_axi => spisel_pulse_to_axi_clk , -- out
----------------------------
Mst_N_Slv_mode_cdc_from_spi => Mst_N_Slv_mode_frm_spi_clk , -- in
Mst_N_Slv_mode_cdc_to_axi => Mst_N_Slv_mode_to_axi_clk , -- out
----------------------------
slave_MODF_strobe_cdc_from_spi => slave_MODF_strobe_frm_spi_clk, -- in
slave_MODF_strobe_cdc_to_axi => slave_MODF_strobe_to_axi_clk , -- out
----------------------------
modf_strobe_cdc_from_spi => modf_strobe_frm_spi_clk , -- in
modf_strobe_cdc_to_axi => modf_strobe_to_axi_clk , -- out
----------------------------
SPICR_6_RXFIFO_RST_cdc_from_axi=> SPICR_6_RXFIFO_RST_frm_axi_clk, -- in
SPICR_6_RXFIFO_RST_cdc_to_spi => SPICR_6_RXFIFO_RST_to_spi_clk , -- out
----------------------------
Rx_FIFO_Full_cdc_from_axi => Rx_FIFO_Full_frm_axi_clk, -- in
Rx_FIFO_Full_cdc_to_spi => Rx_FIFO_Full_to_spi_clk , -- out
----------------------------
reset_RcFIFO_ptr_cdc_from_axi => reset_RcFIFO_ptr_frm_axi_clk, -- in
reset_RcFIFO_ptr_cdc_to_spi => reset_RcFIFO_ptr_to_spi_clk , -- out
----------------------------
Rx_FIFO_Empty_cdc_from_axi => Rx_FIFO_Empty_frm_axi_clk , -- in
Rx_FIFO_Empty_cdc_to_spi => Rx_FIFO_Empty_to_spi_clk , -- out
----------------------------
Tx_FIFO_Empty_cdc_from_spi => Tx_FIFO_Empty_frm_spi_clk, -- in
Tx_FIFO_Empty_cdc_to_axi => Tx_FIFO_Empty_to_Axi_clk, -- out
----------------------------
Tx_FIFO_Empty_SPISR_cdc_from_spi => Tx_FIFO_Empty_SPISR_frm_spi_clk,
Tx_FIFO_Empty_SPISR_cdc_to_axi => Tx_FIFO_Empty_SPISR_to_axi_clk,
Tx_FIFO_Full_cdc_from_axi => Tx_FIFO_Full_frm_axi_clk,-- in
Tx_FIFO_Full_cdc_to_spi => Tx_FIFO_Full_to_spi_clk ,-- out
----------------------------
spiXfer_done_cdc_from_spi => spiXfer_done_frm_spi_clk, -- in
spiXfer_done_cdc_to_axi => spiXfer_done_to_axi_clk, -- out
----------------------------
dtr_underrun_cdc_from_spi => dtr_underrun_frm_spi_clk, -- in
dtr_underrun_cdc_to_axi => dtr_underrun_to_axi_clk , -- out
----------------------------
SPICR_0_LOOP_cdc_from_axi => SPICR_0_LOOP_frm_axi_clk,-- in std_logic;
SPICR_0_LOOP_cdc_to_spi => SPICR_0_LOOP_to_spi_clk ,-- out
----------------------------
SPICR_1_SPE_cdc_from_axi => SPICR_1_SPE_frm_axi_clk ,-- in std_logic;
SPICR_1_SPE_cdc_to_spi => SPICR_1_SPE_to_spi_clk ,-- out
----------------------------
SPICR_2_MST_N_SLV_cdc_from_axi => SPICR_2_MST_N_SLV_frm_axi_clk,-- in std_logic;
SPICR_2_MST_N_SLV_cdc_to_spi => SPICR_2_MST_N_SLV_to_spi_clk, -- out
----------------------------
SPICR_3_CPOL_cdc_from_axi => SPICR_3_CPOL_frm_axi_clk,-- in std_logic;
SPICR_3_CPOL_cdc_to_spi => SPICR_3_CPOL_to_spi_clk ,-- out
----------------------------
SPICR_4_CPHA_cdc_from_axi => SPICR_4_CPHA_frm_axi_clk,-- in std_logic;
SPICR_4_CPHA_cdc_to_spi => SPICR_4_CPHA_to_spi_clk ,-- out
----------------------------
SPICR_5_TXFIFO_cdc_from_axi => SPICR_5_TXFIFO_RST_frm_axi_clk,-- in std_logic;
SPICR_5_TXFIFO_cdc_to_spi => SPICR_5_TXFIFO_to_spi_clk, -- out
----------------------------
SPICR_7_SS_cdc_from_axi => SPICR_7_SS_frm_axi_clk ,-- in std_logic;
SPICR_7_SS_cdc_to_spi => SPICR_7_SS_to_spi_clk ,-- out
----------------------------
SPICR_8_TR_INHIBIT_cdc_from_axi=> SPICR_8_TR_INHIBIT_frm_axi_clk,-- in std_logic;
SPICR_8_TR_INHIBIT_cdc_to_spi => SPICR_8_TR_INHIBIT_to_spi_clk,-- out
----------------------------
SPICR_9_LSB_cdc_from_axi => SPICR_9_LSB_frm_axi_clk,-- in std_logic;
SPICR_9_LSB_cdc_to_spi => SPICR_9_LSB_to_spi_clk,-- out
----------------------------
SPICR_bits_7_8_cdc_from_axi => SPICR_bits_7_8_frm_axi_clk,-- in std_logic_vector
SPICR_bits_7_8_cdc_to_spi => SPICR_bits_7_8_to_spi_clk,-- out
----------------------------
SR_3_modf_cdc_from_axi => SR_3_modf_frm_axi_clk, -- in
SR_3_modf_cdc_to_spi => SR_3_modf_to_spi_clk , -- out
----------------------------
SPISSR_cdc_from_axi => SPISSR_frm_axi_clk, -- in
SPISSR_cdc_to_spi => register_Data_slvsel_int, -- out
----------------------------
spiXfer_done_cdc_to_axi_1 => spiXfer_done_to_axi_1,
----------------------------
drr_Overrun_int_cdc_from_spi => drr_Overrun_int_frm_spi_clk,
drr_Overrun_int_cdc_to_axi => drr_Overrun_int_to_axi_clk
----------------------------
);
-- Bu2IP Data to Interrupt Registers - IPISR and IPIER
-- Bus2IP_Data - 0 31
-- IPISR/IPIER - 0 17 18 31
-- <---NA---> <-used->
-- 18 19 20 21 22 23 24 25 26 27 28 29 30 31
-- CMD_ Loop_Bk MSB Slave_Mode CPOL_CPHA DRR_Not Slave Tx_FIFO DRR_ DRR_ DTR_ DTR Slave MODF
-- Error Error Error Error Error _Empty Select_mode Half_Empty Over_Run Full Underrun Empty MODF
-- In Slave
-- mode_only
-- <---------------------------------------> <------------------------------------------------------------->
-- In C_SPI_MODE 1 or 2 only Present in all conditions
-- IPISR Write
-- when FIFO = 1,all other the IPIER, IPISR interrupt bits are applicable based upon the SPI mode.
-- DRR_Not_Empty bit (bit 23) - available only in case of core is selected in
-- slave mode and control register mst_n_slv bit is '0'.
-- Slave_select_mode bit-available only in case of core is selected in slave mode
-- common assignment to SPI_MODE 1/2 and SPI_MODE = 0
bus2IP_Data_for_interrupt_core(0 to 17) <= Bus2IP_Data(0 to 17);
DUAL_MD_IPISR_GEN: if C_SPI_MODE = 1 or C_SPI_MODE = 2 generate
-----------------------
begin
-----
bus2IP_Data_for_interrupt_core(18 to 22) <= Bus2IP_Data(18 to 22);
end generate DUAL_MD_IPISR_GEN;
---------------------------------------------
STD_MD_IPISR_GEN: if C_SPI_MODE = 0 generate
-----------------------------------
begin
-----
bus2IP_Data_for_interrupt_core(18 to 22)<= (others => '0');
end generate STD_MD_IPISR_GEN;
------------------------------------------------
bus2IP_Data_for_interrupt_core(23) <= Bus2IP_Data(23) and -- exists only when FIFO = exists AND
((not spisel_d1_reg_to_axi_clk) --spisel_d1_reg)
or -- core is selected by asserting SPISEL by ext. master AND
(not SPICR_2_MST_N_SLV_frm_axi_clk) --Mst_N_Slv_mode) -- core is in slave mode
);
bus2IP_Data_for_interrupt_core(24 to (C_S_AXI_DATA_WIDTH-1)) <=
Bus2IP_Data(24 to (C_S_AXI_DATA_WIDTH-1));
--
----------------------------------------------------
-- _____|------------- data_Exists_RcFIFO_int
-- ________|---------- data_Exists_RcFIFO_int_d1
-- _____|--|__________ data_Exists_RcFIFO_pulse
----------------------------------------------------
DRR_NOT_EMPTY_PULSE_P: process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
data_Exists_RcFIFO_int_d1 <= '0';
else
data_Exists_RcFIFO_int_d1 <= not rx_fifo_empty_i; -- data_Exists_RcFIFO_int;
end if;
end if;
end process DRR_NOT_EMPTY_PULSE_P;
------------------------------------
data_Exists_RcFIFO_pulse <= not rx_fifo_empty_i and
(not data_Exists_RcFIFO_int_d1);
------------------------------------
---------------------------------------------------------------------------
DUAL_MD_INTR_GEN: if C_SPI_MODE = 1 or C_SPI_MODE = 2 generate
-----------------------
signal SPISR_4_CPOL_CPHA_Error_d1 : std_logic;
signal SPISR_3_Slave_Mode_Error_d1 : std_logic;
signal SPISR_2_MSB_Error_d1 : std_logic;
signal SPISR_1_LOOP_Back_Error_d1 : std_logic;
signal SPISR_0_CMD_Error_d1 : std_logic;
signal SPISR_4_CPOL_CPHA_Error_pulse : std_logic;
signal SPISR_3_Slave_Mode_Error_pulse: std_logic;
signal SPISR_2_MSB_Error_pulse : std_logic;
signal SPISR_1_LOOP_Back_Error_pulse : std_logic;
signal SPISR_0_CMD_Error_pulse : std_logic;
-----
begin
-----
INTR_UPPER_BITS_P: process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
SPISR_0_CMD_Error_d1 <= '0';
SPISR_1_LOOP_Back_Error_d1 <= '0';
SPISR_2_MSB_Error_d1 <= '0';
SPISR_3_Slave_Mode_Error_d1 <= '0';
SPISR_4_CPOL_CPHA_Error_d1 <= '0';
else
SPISR_0_CMD_Error_d1 <= SPISR_0_CMD_Error_to_axi_clk; -- SPISR_0_CMD_Error_int;
SPISR_1_LOOP_Back_Error_d1 <= SPISR_1_LOOP_Back_Error_int; -- from SPICR
SPISR_2_MSB_Error_d1 <= SPISR_2_MSB_Error_int; -- from SPICR
SPISR_3_Slave_Mode_Error_d1 <= SPISR_3_Slave_Mode_Error_int;-- from SPICR
SPISR_4_CPOL_CPHA_Error_d1 <= SPISR_4_CPOL_CPHA_Error_int; -- from SPICR
end if;
end if;
end process INTR_UPPER_BITS_P;
------------------------------------
SPISR_0_CMD_Error_pulse <= SPISR_0_CMD_Error_to_axi_clk -- SPISR_0_CMD_Error_int
and (not SPISR_0_CMD_Error_d1);
SPISR_1_LOOP_Back_Error_pulse <= SPISR_1_LOOP_Back_Error_int
and (not SPISR_1_LOOP_Back_Error_d1);
SPISR_2_MSB_Error_pulse <= SPISR_2_MSB_Error_int
and (not SPISR_2_MSB_Error_d1);
SPISR_3_Slave_Mode_Error_pulse <= SPISR_3_Slave_Mode_Error_int
and (not SPISR_3_Slave_Mode_Error_d1);
SPISR_4_CPOL_CPHA_Error_pulse <= SPISR_4_CPOL_CPHA_Error_int
and (not SPISR_4_CPOL_CPHA_Error_d1);
-- Interrupt Status Register(IPISR) Mapping
ip2Bus_IntrEvent_int(13) <= SPISR_0_CMD_Error_pulse;
ip2Bus_IntrEvent_int(12) <= SPISR_1_LOOP_Back_Error_pulse;
ip2Bus_IntrEvent_int(11) <= SPISR_2_MSB_Error_pulse;
ip2Bus_IntrEvent_int(10) <= SPISR_3_Slave_Mode_Error_pulse;
ip2Bus_IntrEvent_int(9) <= SPISR_4_CPOL_CPHA_Error_pulse ;
end generate DUAL_MD_INTR_GEN;
--------------------------------------------
STD_MD_INTR_GEN: if C_SPI_MODE = 0 generate
-----------------------
begin
-----
ip2Bus_IntrEvent_int(13) <= '0';
ip2Bus_IntrEvent_int(12) <= '0';
ip2Bus_IntrEvent_int(11) <= '0';
ip2Bus_IntrEvent_int(10) <= '0';
ip2Bus_IntrEvent_int(9) <= '0';
end generate STD_MD_INTR_GEN;
-----------------------------------------------
ip2Bus_IntrEvent_int(8) <= data_Exists_RcFIFO_pulse and
((not spisel_d1_reg_to_axi_clk) -- spisel_d1_reg)
or
(not SPICR_2_MST_N_SLV_frm_axi_clk) -- Mst_N_Slv_mode)
);
ip2Bus_IntrEvent_int(7) <= spisel_pulse_to_axi_clk;-- and not SPICR_2_MST_N_SLV_frm_axi_clk; -- spisel_pulse_o_int;-- spi_module
ip2Bus_IntrEvent_int(6) <= tx_FIFO_less_half_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(5) <= drr_Overrun_int_to_axi_clk; -- drr_Overrun_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(4) <= rc_FIFO_Full_strobe_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(3) <= dtr_Underrun_strobe_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(2) <= tx_FIFO_Empty_strobe_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(1) <= slave_MODF_strobe_to_axi_clk; --slave_MODF_strobe_int;-- spi_module
ip2Bus_IntrEvent_int(0) <= modf_strobe_to_axi_clk; -- modf_strobe_int; -- spi_module
--Combinatorial operations
reset_TxFIFO_ptr_int <= reset2ip_reset_int or SPICR_5_TXFIFO_RST_frm_axi_clk;
reset_TxFIFO_ptr_int_to_spi <= Rst_to_spi_int or SPICR_5_TXFIFO_to_spi_clk;
--reset_RcFIFO_ptr_int <= Rst_to_spi_int or SPICR_6_RXFIFO_RST_to_spi_clk; -- SPICR_6_RXFIFO_RST_int;
reset_RcFIFO_ptr_int <= reset2ip_reset_int or SPICR_6_RXFIFO_RST_frm_axi_clk;
sr_5_Tx_Empty_int <= not (data_Exists_TxFIFO_int);
Rc_FIFO_Empty_int <= Rx_FIFO_Empty;--not (data_Exists_RcFIFO_int);
-- AXI Clk domain -- __________________ SPI clk domain
--Dout --|AXI clk |-- Din
--Rd_en --| |-- Wr_en
--Rd_clk --| |-- Wr_clk
--| |--
--Rx_FIFO_Empty --| Rx FIFO |-- Rx_FIFO_Full
--Rx_FIFO_almost_Empty --| |-- Rx_FIFO_almost_Full
--Rx_FIFO_occ_Reversed --| |--
--Rx_FIFO_rd_ack --| |--
--| |--
--| |--
--| |--
--|__________________|--
RX_RD_EN_LEG_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
begin
-----
IP2Bus_RdAck_receive_enable <= (rd_ce_reduce_ack_gen and
Bus2IP_RdCE(SPIDRR)
)and
(not Rx_FIFO_Empty);
end generate RX_RD_EN_LEG_MD_GEN;
RX_RD_EN_ENHAN_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
begin
-----
IP2Bus_RdAck_receive_enable <= --(rd_ce_reduce_ack_gen and
(rready and
Bus2IP_RdCE(SPIDRR)
)and
(not Rx_FIFO_Empty);
end generate RX_RD_EN_ENHAN_MD_GEN;
-- Receive FIFO Logic
rx_fifo_reset <= Rst_to_spi_int or reset_RcFIFO_ptr_to_spi_clk;
RX_FIFO_II: entity lib_fifo_v1_0_5.async_fifo_fg --axi_quad_spi_v3_2_8_0.async_fifo_fg --lib_fifo_v1_0_5_4.async_fifo_fg
generic map(
-- for first word fall through FIFO below two parameters setting is must please dont change
C_PRELOAD_LATENCY => 0 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
C_PRELOAD_REGS => 1 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
-- variables
C_ALLOW_2N_DEPTH => 1 , -- : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY => C_FAMILY , -- : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH => C_NUM_TRANSFER_BITS, -- : integer := 16;
C_FIFO_DEPTH => C_FIFO_DEPTH , -- : integer := 15;
C_RD_COUNT_WIDTH => C_RD_COUNT_WIDTH_INT,-- : integer := 3 ;
C_WR_COUNT_WIDTH => C_WR_COUNT_WIDTH_INT,-- : integer := 3 ;
C_HAS_ALMOST_EMPTY => 1 , -- : integer := 1 ;
C_HAS_ALMOST_FULL => 1 , -- : integer := 1 ;
C_HAS_RD_ACK => 1 , -- : integer := 0 ;
C_HAS_RD_COUNT => 1 , -- : integer := 1 ;
C_HAS_WR_ACK => 1 , -- : integer := 0 ;
C_HAS_WR_COUNT => 1 , -- : integer := 1 ;
-- constants
C_HAS_RD_ERR => 0 , -- : integer := 0 ;
C_HAS_WR_ERR => 0 , -- : integer := 0 ;
C_RD_ACK_LOW => 0 , -- : integer := 0 ;
C_RD_ERR_LOW => 0 , -- : integer := 0 ;
C_WR_ACK_LOW => 0 , -- : integer := 0 ;
C_WR_ERR_LOW => 0 , -- : integer := 0
C_ENABLE_RLOCS => 0 , -- : integer := 0 ; -- not supported in FG
C_USE_BLOCKMEM => 0 -- : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
)
port map(
Din => Data_To_Rx_FIFO , -- : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en => spiXfer_done_int, --SPIXfer_done_Rx_Wr_en, -- , -- : in std_logic := '1';
Wr_clk => EXT_SPI_CLK , -- : in std_logic := '1';
Wr_ack => Rx_FIFO_wr_ack_open , -- : out std_logic;
------
Dout => Data_From_Rx_FIFO , -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Rd_en => IP2Bus_RdAck_receive_enable , -- : in std_logic := '0';
Rd_clk => Bus2IP_Clk , -- : in std_logic := '1';
Rd_ack => Rx_FIFO_rd_ack , -- : out std_logic;
------
Full => Rx_FIFO_Full_Fifo_org , -- : out std_logic;
Empty => Rx_FIFO_Empty , -- : out std_logic;
Almost_full => Rx_FIFO_almost_Full , -- : out std_logic;
Almost_empty => Rx_FIFO_almost_Empty , -- : out std_logic;
Rd_count => Rx_FIFO_occ_Reversed , -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
------
Ainit => rx_fifo_reset, -- reset_RcFIFO_ptr_to_spi_clk ,--reset_RcFIFO_ptr_int, -- reset_RcFIFO_ptr_to_spi_clk ,--Rx_FIFO_ptr_RST , -- : in std_logic := '1';
Wr_count => open , -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_err => open , -- : out std_logic;
Wr_err => open -- : out std_logic
);
RX_FIFO_EMPTY_SYNC_AXI_2_SPI_CDC : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1, -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => '0',
prmry_in => Rx_FIFO_Empty,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => '0' ,
scndry_out => Rx_FIFO_Empty_Synced_in_SPI_domain
);
Rx_FIFO_Full_Fifo <= Rx_FIFO_Full_Fifo_org and not Rx_FIFO_Empty_Synced_in_SPI_domain;
RX_FULL_DELAY_PROCESS: process(EXT_SPI_CLK) is
----------------------
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK='1') then
if (Rst_to_spi_int = '1') then
Rx_FIFO_Full_Fifo_d1 <= '0';
else
Rx_FIFO_Full_Fifo_d1 <= Rx_FIFO_Full_Fifo;
end if;
end if;
end process RX_FULL_DELAY_PROCESS;
RX_FULL_EDGE_PROCESS: process(Bus2IP_Clk) is
----------------------
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
Rx_FIFO_Full_Fifo_d1_flag <= '0';
else
Rx_FIFO_Full_Fifo_d1_flag <= Rx_FIFO_Full_Fifo_d1_synced;
end if;
end if;
end process RX_FULL_EDGE_PROCESS;
Rx_FIFO_Full_Fifo_pos_flag <= Rx_FIFO_Full_Fifo_d1_synced and (not Rx_FIFO_Full_Fifo_d1_flag);
--Rx_FIFO_Full_Fifo_neg_flag <= (not Rx_FIFO_Full_Fifo_d1_synced) and Rx_FIFO_Full_Fifo_d1_flag;
RX_FULL_GEN_PROCESS: process(Bus2IP_Clk) is
----------------------
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
Rx_FIFO_Full_Fifo_d1_sig <= '0';
elsif(IP2Bus_RdAck_receive_enable = '1' and Rx_FIFO_Full_Fifo_d1_synced = '1')then
Rx_FIFO_Full_Fifo_d1_sig <= '0';
elsif(Rx_FIFO_Full_Fifo_pos_flag = '1') then
Rx_FIFO_Full_Fifo_d1_sig <= '1';
end if;
end if;
end process RX_FULL_GEN_PROCESS;
----------------------------------
RX_FIFO_FULL_SYNCED_SPI_2_AXI_CDC : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1, -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => '0',
prmry_in => Rx_FIFO_Full_Fifo_d1,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => '0' ,
scndry_out => Rx_FIFO_Full_Fifo_d1_synced
);
RX_FIFO_FULL_CNTR_I : entity axi_quad_spi_v3_2_8.counter_f
generic map(
C_NUM_BITS => RX_FIFO_CNTR_WIDTH,
C_FAMILY => "nofamily"
)
port map(
Clk => Bus2IP_Clk, -- in
Rst => '0', -- in
Load_In => ALL_0, -- in
Count_Enable => updown_cnt_en_rx, -- in
----------------
Count_Load => reset_RcFIFO_ptr_int, -- in
----------------
Count_Down => IP2Bus_RdAck_receive_enable, -- in
Count_Out => rx_fifo_count, -- out std_logic_vector
Carry_Out => open -- out
);
--updown_cnt_en_rx <= IP2Bus_RdAck_receive_enable xor spiXfer_done_to_axi_1;
--fifo_full_f_int <= Rx_FIFO_Full_Fifo_d1_synced when
--updown_cnt_en_rx <= ((not spiXfer_done_to_axi_1) and IP2Bus_RdAck_receive_enable and Rx_FIFO_Full_int and (not Rx_FIFO_Full_Fifo_d1_synced)) or ((IP2Bus_RdAck_receive_enable xor spiXfer_done_to_axi_1) and (not Rx_FIFO_Full_Fifo_d1_synced) and (not Rx_FIFO_Full_int));
updown_cnt_en_rx <= ((not spiXfer_done_to_axi_1) and IP2Bus_RdAck_receive_enable and Rx_FIFO_Full_int and (not (Rx_FIFO_Full_Fifo_d1_sig or Rx_FIFO_Full_Fifo_pos_flag))) or ((IP2Bus_RdAck_receive_enable xor spiXfer_done_to_axi_1) and (not (Rx_FIFO_Full_Fifo_d1_sig or Rx_FIFO_Full_Fifo_pos_flag)) and (not Rx_FIFO_Full_int));
-- updown_cnt_en_rx <= (IP2Bus_RdAck_receive_enable and Rx_FIFO_Full_int)
-- or (spiXfer_done_to_axi_1 and (not Rx_FIFO_Full_int))
-- or ((IP2Bus_RdAck_receive_enable xor spiXfer_done_to_axi_1) and (not Rx_FIFO_Full_int));
RX_one_less_than_full <= and_reduce(rx_fifo_count(RX_FIFO_CNTR_WIDTH-1 downto RX_FIFO_CNTR_WIDTH-RX_FIFO_CNTR_WIDTH+1)) and
(not rx_fifo_count(0))and spiXfer_done_to_axi_1;
RX_FULL_EMP_MD_12_INTR_GEN: if C_SPI_MODE /= 0 generate
-----
--signal rx_fifo_empty_i : std_logic;
begin
-----
RX_FIFO_EMPTY_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
rx_fifo_empty_i <= '1';
elsif(reset_RcFIFO_ptr_int = '1')then
rx_fifo_empty_i <= '1';
elsif(spiXfer_done_to_axi_1 = '1')then
rx_fifo_empty_i <= '0';
end if;
end if;
end process RX_FIFO_EMPTY_P;
RX_FIFO_FULL_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Rx_FIFO_Full_int <= '0';
--elsif(reset_RcFIFO_ptr_int = '1') or (drr_Overrun_int_to_axi_clk = '1') then --(drr_Overrun_int = '1')then
elsif(reset_RcFIFO_ptr_int = '1') then --(drr_Overrun_int = '1')then
Rx_FIFO_Full_int <= '0';
elsif(Rx_FIFO_Full_int = '1' and IP2Bus_RdAck_receive_enable = '1') then -- IP2Bus_RdAck_receive_enable = '1')then
Rx_FIFO_Full_int <= '0';
elsif(RX_one_less_than_full = '1' and
spiXfer_done_to_axi_1 = '1' and
rx_fifo_empty_i = '0')then
Rx_FIFO_Full_int <= '1';
end if;
end if;
end process RX_FIFO_FULL_P;
end generate RX_FULL_EMP_MD_12_INTR_GEN;
------------------------------------
RX_FULL_EMP_MD_0_GEN: if C_SPI_MODE = 0 generate
--signal rx_fifo_empty_i : std_logic;
-----
begin
-----
RX_FIFO_EMPTY_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
rx_fifo_empty_i <= '1';
elsif(reset_RcFIFO_ptr_int = '1')then
rx_fifo_empty_i <= '1';
elsif(spiXfer_done_to_axi_1 = '1')then
rx_fifo_empty_i <= '0';
end if;
end if;
end process RX_FIFO_EMPTY_P;
-------------------------------------------
RX_FIFO_ABT_TO_FULL_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Rx_FIFO_Full_i <= '0';
--elsif(reset_RcFIFO_ptr_int = '1') or (drr_Overrun_int_to_axi_clk = '1') then -- (drr_Overrun_int = '1')then
elsif(reset_RcFIFO_ptr_int = '1') then -- (drr_Overrun_int = '1')then
Rx_FIFO_Full_i <= '0';
elsif(Rx_FIFO_Full_int = '1')then
Rx_FIFO_Full_i <= '0';
elsif(RX_one_less_than_full = '1')then
Rx_FIFO_Full_i <= '1';
end if;
end if;
end process RX_FIFO_ABT_TO_FULL_P;
-------------------------------------
RX_FIFO_FULL_P: process(Bus2IP_Clk)is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Rx_FIFO_Full_int <= '0';
--elsif(reset_RcFIFO_ptr_int = '1') or (drr_Overrun_int_to_axi_clk = '1') then -- (drr_Overrun_int = '1')then
elsif(reset_RcFIFO_ptr_int = '1') then -- (drr_Overrun_int = '1')then
Rx_FIFO_Full_int <= '0';
elsif(Rx_FIFO_Full_int = '1' and IP2Bus_RdAck_receive_enable = '1') then -- IP2Bus_RdAck_receive_enable = '1')then
Rx_FIFO_Full_int <= '0';
elsif(Rx_FIFO_Full_i = '1')then
Rx_FIFO_Full_int <= '1';
end if;
end if;
end process RX_FIFO_FULL_P;
---------------------------------
Rx_FIFO_Full <= Rx_FIFO_Full_int;
end generate RX_FULL_EMP_MD_0_GEN;
Rx_FIFO_Empty_int <= Rx_FIFO_Empty or Rx_FIFO_Empty_i;
-----------------------------------------------------------------------------
-- AXI Clk domain -- __________________ SPI clk domain
--Din --|AXI clk |-- Dout
--Wr_en --| |-- Rd_en
--Wr_clk --| |-- Rd_clk
--| |--
--Tx_FIFO_Full --| Tx FIFO |-- Tx_FIFO_Empty
--Tx_FIFO_almost_Full --| |-- Tx_FIFO_almost_Empty
--Tx_FIFO_occ_Reversed --| |-- Tx_FIFO_rd_ack
--Tx_FIFO_wr_ack --| |--
--| |--
--| |--
--| |--
--|__________________|--
TX_TR_EN_LEG_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
begin
-----
IP2Bus_WrAck_transmit_enable <= (wr_ce_reduce_ack_gen and
Bus2IP_WrCE(SPIDTR)
) and
(not Tx_FIFO_Full);-- after 100 ps;
end generate TX_TR_EN_LEG_MD_GEN;
TX_TR_EN_ENHAN_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
signal local_tr_en : std_logic;
begin
-----
--IP2Bus_WrAck_transmit_enable <= (wr_ce_reduce_ack_gen and
-- Bus2IP_WrCE(SPIDTR)
-- ) and
-- (not Tx_FIFO_Full)
-- when burst_tr = '0' else
-- (Bus2IP_WrCE(SPIDTR)
-- and
-- (not Tx_FIFO_Full));-- after 100 ps;
local_tr_en <= Bus2IP_WrCE(SPIDTR) and (not Tx_FIFO_Full);
--local_tr_en1 <= Bus2IP_WrCE_d1 and (not Tx_FIFO_Full);
TR_EN_P:process(wr_ce_reduce_ack_gen,
local_tr_en,
burst_tr,
WVALID)is
begin
if(burst_tr = '1') then
IP2Bus_WrAck_transmit_enable <= local_tr_en and WVALID; -- Bus2IP_WrCE_d1 and (not Tx_FIFO_Full); --local_tr_en;
else
IP2Bus_WrAck_transmit_enable <= local_tr_en and wr_ce_reduce_ack_gen;
end if;
end process TR_EN_P;
end generate TX_TR_EN_ENHAN_MD_GEN;
Data_To_TxFIFO <= Bus2IP_Data((C_S_AXI_DATA_WIDTH-C_NUM_TRANSFER_BITS) to(C_S_AXI_DATA_WIDTH-1));-- after 100 ps;
-- Transmit FIFO Logic
tx_fifo_reset <= reset2ip_reset_int or reset_TxFIFO_ptr_int;
TX_FIFO_II: entity lib_fifo_v1_0_5.async_fifo_fg -- entity axi_quad_spi_v3_2_8_0.async_fifo_fg -- lib_fifo_v1_0_5_4.async_fifo_fg
generic map
(
-- for first word fall through FIFO below two parameters setting is must please dont change
C_PRELOAD_LATENCY => 0 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
C_PRELOAD_REGS => 1 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
-- variables
C_ALLOW_2N_DEPTH => 1 , -- : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY => C_FAMILY , -- : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH => C_NUM_TRANSFER_BITS, -- : integer := 16;
C_FIFO_DEPTH => C_FIFO_DEPTH , -- : integer := 15;
C_RD_COUNT_WIDTH => C_RD_COUNT_WIDTH_INT,-- : integer := 3 ;
C_WR_COUNT_WIDTH => C_WR_COUNT_WIDTH_INT,-- : integer := 3 ;
C_HAS_ALMOST_EMPTY => 1 , -- : integer := 1 ;
C_HAS_ALMOST_FULL => 1 , -- : integer := 1 ;
C_HAS_RD_ACK => 1 , -- : integer := 0 ;
C_HAS_RD_COUNT => 1 , -- : integer := 1 ;
C_HAS_WR_ACK => 1 , -- : integer := 0 ;
C_HAS_WR_COUNT => 1 , -- : integer := 1 ;
-- constants
C_HAS_RD_ERR => 0 , -- : integer := 0 ;
C_HAS_WR_ERR => 0 , -- : integer := 0 ;
C_RD_ACK_LOW => 0 , -- : integer := 0 ;
C_RD_ERR_LOW => 0 , -- : integer := 0 ;
C_WR_ACK_LOW => 0 , -- : integer := 0 ;
C_WR_ERR_LOW => 0 , -- : integer := 0
C_ENABLE_RLOCS => 0 , -- : integer := 0 ; -- not supported in FG
C_USE_BLOCKMEM => 0 -- : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
)
port map
(
-- writing will be through AXI clock
Wr_clk => Bus2IP_Clk , -- : in std_logic := '1';
Din => Data_To_TxFIFO , -- : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en => IP2Bus_WrAck_transmit_enable, -- : in std_logic := '1';
Wr_ack => Tx_FIFO_wr_ack , -- : out std_logic;
------
-- reading will be through SPI clock
Rd_clk => EXT_SPI_CLK , -- : in std_logic := '1';
Dout => Data_From_TxFIFO , -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Rd_en => SPIXfer_done_rd_tx_en , -- : in std_logic := '0';
Rd_ack => Tx_FIFO_rd_ack_open , -- : out std_logic;
------
Full => Tx_FIFO_Full , -- : out std_logic;
Empty => Tx_FIFO_Empty , -- : out std_logic;
Almost_full => Tx_FIFO_almost_Full , -- : out std_logic;
Almost_empty => Tx_FIFO_almost_Empty , -- : out std_logic;
Rd_count => open , -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
------
Ainit => reset_TxFIFO_ptr_int ,--Tx_FIFO_ptr_RST , -- : in std_logic := '1';
Wr_count => Tx_FIFO_occ_Reversed , -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_err => open , -- : out std_logic;
Wr_err => open -- : out std_logic
);
--tx_occ_msb <= tx_fifo_count(TX_FIFO_CNTR_WIDTH-1); -- --Tx_FIFO_occ_Reversed(C_WR_COUNT_WIDTH_INT-1);
--tx_occ_msb_1 <= (tx_fifo_count(TX_FIFO_CNTR_WIDTH-1));-- and not(or_reduce(tx_fifo_count(TX_FIFO_CNTR_WIDTH-2 downto 0))) ;--
--and not Tx_FIFO_Empty_SPISR_to_axi_clk;-- and not Tx_FIFO_Full_int; -- --Tx_FIFO_occ_Reversed(C_WR_COUNT_WIDTH_INT-1);
tx_occ_msb_11 <= (tx_fifo_count);
FIFO_16_OCC_MSB_GEN: if C_FIFO_DEPTH = 16 generate
begin
tx_occ_msb_1 <= tx_occ_msb_11(3);
end generate FIFO_16_OCC_MSB_GEN;
FIFO_256_OCC_MSB_GEN: if C_FIFO_DEPTH = 256 generate
begin
tx_occ_msb_1 <= tx_occ_msb_11(7);
end generate FIFO_256_OCC_MSB_GEN;
TX_OCC_MSB_P: process (Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
tx_occ_msb_2 <= '0';
tx_occ_msb_3 <= '0';
tx_occ_msb_4 <= '0';
else
tx_occ_msb_2 <= tx_occ_msb_1;
tx_occ_msb_3 <= tx_occ_msb_2;
tx_occ_msb_4 <= tx_occ_msb_3;
end if;
end if;
end process TX_OCC_MSB_P;
tx_occ_msb <= tx_occ_msb_4 and not Tx_FIFO_Empty_SPISR_to_axi_clk;
data_Exists_TxFIFO_int <= not (Tx_FIFO_Empty);
-----------------------------------------------------------
TX_FIFO_EMPTY_CNTR_I : entity axi_quad_spi_v3_2_8.counter_f
generic map(
C_NUM_BITS => TX_FIFO_CNTR_WIDTH,
C_FAMILY => "nofamily"
)
port map(
Clk => Bus2IP_Clk, -- in
Rst => '0', -- in
Load_In => ALL_0, -- in
Count_Enable => updown_cnt_en, -- in
----------------
Count_Load => reset_TxFIFO_ptr_int, -- in
----------------
Count_Down => spiXfer_done_to_axi_1, -- in
Count_Out => tx_fifo_count, -- out std_logic_vector
Carry_Out => open -- out
);
updown_cnt_en <= IP2Bus_WrAck_transmit_enable xor spiXfer_done_to_axi_1;
----------------------------------------
TX_FULL_EMP_INTR_MD_12_GEN: if C_SPI_MODE /=0 generate
-----
begin
-----
Tx_FIFO_Empty_intr <= not (or_reduce(tx_fifo_count(TX_FIFO_CNTR_WIDTH-1 downto 0)))
-- and (tx_fifo_count(0))
and spiXfer_done_to_axi_1
and ( Tx_FIFO_Empty_SPISR_to_axi_clk); -- and ( Tx_FIFO_Empty);
Tx_FIFO_Full_int <= Tx_FIFO_Full;
end generate TX_FULL_EMP_INTR_MD_12_GEN;
----------------------------------------
----------------------------------------
TX_FULL_EMP_INTR_MD_0_GEN: if C_SPI_MODE =0 generate
-----
begin
-----
-- Tx_FIFO_one_less_to_Empty <= not(or_reduce(tx_fifo_count(TX_FIFO_CNTR_WIDTH-1 downto 0)))
-- --and (tx_fifo_count(0))
-- and spiXfer_done_to_axi_1;--tx_cntr_xfer_done_to_axi_1_clk; --
-- --------------------------------------------
-- TX_FIFO_ABT_TO_EMPTY_P:process(Bus2IP_Clk)is
-- begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(reset2ip_reset_int = RESET_ACTIVE)then
-- Tx_FIFO_Empty_i <= '0';
-- elsif(Tx_FIFO_Empty_int = '1')then
-- Tx_FIFO_Empty_i <= '0';
-- elsif(Tx_FIFO_one_less_to_Empty = '1') or then
-- Tx_FIFO_Empty_i <= '1';
-- end if;
-- end if;
-- end process TX_FIFO_ABT_TO_EMPTY_P;
-- --------------------------------------
-- TX_FIFO_EMPTY_P: process(Bus2IP_Clk)is
-- begin
-- -----
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(reset2ip_reset_int = RESET_ACTIVE)then
-- Tx_FIFO_Empty_int <= '0';
-- elsif(Tx_FIFO_Empty_int = '1' and spiXfer_done_to_axi_1 = '1')then
-- Tx_FIFO_Empty_int <= '0';
-- elsif(Tx_FIFO_Empty_i = '1')then
-- Tx_FIFO_Empty_int <= '1';
-- end if;
-- end if;
-- end process TX_FIFO_EMPTY_P;
--------------------------------
-- Tx_FIFO_Empty_intr <= Tx_FIFO_Empty_int and spiXfer_done_to_axi_1;
--------------------------------
TX_FIFO_CNTR_DELAY_P: process(Bus2IP_Clk)is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
tx_fifo_count_d1 <= (others => '0');
tx_fifo_count_d2 <= (others => '0');
spiXfer_done_to_axi_d1 <= '0';
else
tx_fifo_count_d1 <= tx_fifo_count;
tx_fifo_count_d2 <= tx_fifo_count_d1;
spiXfer_done_to_axi_d1 <= spiXfer_done_to_axi_1;
end if;
end if;
end process TX_FIFO_CNTR_DELAY_P;
Tx_FIFO_Empty_intr <= (not (or_reduce(tx_fifo_count_d2(TX_FIFO_CNTR_WIDTH-1 downto 0)))
-- and (tx_fifo_count(0))
and spiXfer_done_to_axi_d1
and ( Tx_FIFO_Empty_SPISR_to_axi_clk));
TX_one_less_than_full <= and_reduce(tx_fifo_count(TX_FIFO_CNTR_WIDTH-1 downto TX_FIFO_CNTR_WIDTH-TX_FIFO_CNTR_WIDTH+1)) and
(not tx_fifo_count(0))and IP2Bus_WrAck_transmit_enable;
-------------------------------------------
TX_FIFO_ABT_TO_FULL_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Tx_FIFO_Full_i <= '0';
elsif(reset_TxFIFO_ptr_int = '1')then
Tx_FIFO_Full_i <= '0';
elsif(Tx_FIFO_Full_int = '1')then
Tx_FIFO_Full_i <= '0';
elsif(TX_one_less_than_full = '1')then
Tx_FIFO_Full_i <= '1';
end if;
end if;
end process TX_FIFO_ABT_TO_FULL_P;
----------------------------------
TX_FIFO_FULL_P: process(Bus2IP_Clk)is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Tx_FIFO_Full_int <= '0';
elsif(reset_TxFIFO_ptr_int = '1')then
Tx_FIFO_Full_int <= '0';
elsif(Tx_FIFO_Full_int = '1' and spiXfer_done_to_axi_1 = '1')then
Tx_FIFO_Full_int <= '0';
elsif(Tx_FIFO_Full_i = '1') then -- and spiXfer_done_to_axi_1 = '1')then
Tx_FIFO_Full_int <= '1';
end if;
end if;
end process TX_FIFO_FULL_P;
---------------------------
end generate TX_FULL_EMP_INTR_MD_0_GEN;
----------------------------------------
-------------------------------------------------------------------------------
-- I_FIFO_IF_MODULE : INSTANTIATE FIFO INTERFACE MODULE
-------------------------------------------------------------------------------
Rx_FIFO_Full_Fifo_d1_synced_i <= Rx_FIFO_Full_Fifo_d1_synced and (not Rx_FIFO_Empty);
FIFO_IF_MODULE_I: entity axi_quad_spi_v3_2_8.qspi_fifo_ifmodule
generic map
(
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS
)
port map
(
Bus2IP_Clk => Bus2IP_Clk , -- in
Soft_Reset_op => reset2ip_reset_int, -- in
-- Slave attachment ports from AXI clock
Bus2IP_RcFIFO_RdCE => Bus2IP_RdCE(SPIDRR),-- axiclk -- in
Bus2IP_TxFIFO_WrCE => Bus2IP_WrCE(SPIDTR),-- axi clk -- in
Rd_ce_reduce_ack_gen => rd_ce_reduce_ack_gen,-- axi clk -- in
-- FIFO ports
Data_From_TxFIFO => Data_From_TxFIFO ,-- spi clk -- in vec
Data_From_Rc_FIFO => Data_From_Rx_FIFO ,-- axi clk -- in vec
Tx_FIFO_Data_WithZero => transmit_Data_int ,-- spi clk -- out vec
IP2Bus_RX_FIFO_Data => IP2Bus_Receive_Reg_Data_int, -- out vec
---------------------
--Rc_FIFO_Full => Rx_FIFO_Full_int, -- Rx_FIFO_Full_to_axi_clk, -- in
Rc_FIFO_Full => Rx_FIFO_Full_Fifo_d1_synced_i, -- Rx_FIFO_Full_to_axi_clk, -- in
Rc_FIFO_Full_strobe => rc_FIFO_Full_strobe_int, -- out
---------------------
Tx_FIFO_Empty => Tx_FIFO_Empty_intr , -- Tx_FIFO_Empty_to_Axi_clk, -- sr_5_Tx_Empty_int,-- spi clk -- in
Tx_FIFO_Empty_strobe => tx_FIFO_Empty_strobe_int, -- out
---------------------
Rc_FIFO_Empty => Rx_FIFO_Empty_int, -- 13-09-2012 rx_fifo_empty_i, -- Rx_FIFO_Empty , -- Rc_FIFO_Empty_int, -- in
Receive_ip2bus_error => receive_ip2bus_error, -- out
Tx_FIFO_Full => Tx_FIFO_Full_int, -- in
Transmit_ip2bus_error => transmit_ip2bus_error, -- out
---------------------
Tx_FIFO_Occpncy_MSB => tx_occ_msb, -- in
Tx_FIFO_less_half => tx_FIFO_less_half_int, -- out
---------------------
DTR_underrun => dtr_underrun_to_axi_clk,-- dtr_underrun_int,-- in
DTR_Underrun_strobe => dtr_Underrun_strobe_int, -- out
---------------------
SPIXfer_done => spiXfer_done_to_axi_1, -- spiXfer_done_int, -- in
rready => rready
-- DRR_Overrun_reg => drr_Overrun_int -- out
);
-------------------------------------------------------------------------------
-- TX_OCCUPANCY_I : INSTANTIATE TRANSMIT OCCUPANCY REGISTER
-------------------------------------------------------------------------------
TX_OCCUPANCY_I: entity axi_quad_spi_v3_2_8.qspi_occupancy_reg
generic map
(
C_OCCUPANCY_NUM_BITS => C_OCCUPANCY_NUM_BITS
)
port map
(
--Slave attachment ports
Bus2IP_OCC_REG_RdCE => Bus2IP_RdCE(SPITFOR), -- in
--FIFO port
IP2Reg_OCC_Data => tx_fifo_count, -- tx_FIFO_occ_Reversed, -- in vec
IP2Bus_OCC_REG_Data => IP2Bus_Tx_FIFO_OCC_Reg_Data_int -- out vec
);
-------------------------------------------------------------------------------
-- RX_OCCUPANCY_I : INSTANTIATE RECEIVE OCCUPANCY REGISTER
-------------------------------------------------------------------------------
RX_OCCUPANCY_I: entity axi_quad_spi_v3_2_8.qspi_occupancy_reg
generic map
(
C_OCCUPANCY_NUM_BITS => C_OCCUPANCY_NUM_BITS--,
)
port map
(
--Slave attachment ports
Bus2IP_OCC_REG_RdCE => Bus2IP_RdCE(SPIRFOR), -- in
--FIFO port
IP2Reg_OCC_Data => rx_fifo_count, --rx_FIFO_occ_Reversed, -- in vec
IP2Bus_OCC_REG_Data => IP2Bus_Rx_FIFO_OCC_Reg_Data_int -- out vec
);
end generate FIFO_EXISTS;
--------------------------------------------
-- LOGIC_FOR_MD_0_GEN: in stantiate the original SPI module when the core is configured in Standard SPI mode.
------------------------------
LOGIC_FOR_MD_0_GEN: if C_SPI_MODE = 0 generate
---------------------------
signal SCK_O_int : std_logic;
signal MISO_I_int: std_logic;
-----
begin
-----
-- un used IO2 and IO3 O/P ports are tied to 0 and T ports are tied to '1'
DATA_STARTUP_USED : if C_USE_STARTUP = 1 generate
-----
begin
-----
-- IO2_O <= do(2);
-- IO2_T <= dts(2);
-- IO3_O <= do(3);
-- IO3_T <= dts(3);
IO2_O <= '0';
IO2_T <= '1';
IO3_O <= '0';
IO3_T <= '1';
SPISR_0_CMD_Error_int <= '0'; -- no command error when C_SPI_MODE= 0
end generate DATA_STARTUP_USED;
-------------------------------------------------------
SCK_MISO_NO_STARTUP_USED: if C_USE_STARTUP = 0 generate
-----
begin
-----
IO2_O <= '0';
IO2_T <= '1';
IO3_O <= '0';
IO3_T <= '1';
SCK_O <= SCK_O_int; -- output from the core
MISO_I_int <= IO1_I; -- input to the core
end generate SCK_MISO_NO_STARTUP_USED;
-------------------------------------------------------
-------------------------------------------------------
SCK_MISO_STARTUP_USED: if C_USE_STARTUP = 1 generate
-----
begin
-----
QSPI_STARTUP_BLOCK_I: entity axi_quad_spi_v3_2_8.qspi_startup_block
---------------------
generic map
(
C_SUB_FAMILY => C_SUB_FAMILY , -- support for V6/V7/K7/A7 families only
-----------------
C_USE_STARTUP => C_USE_STARTUP,
-----------------
C_SHARED_STARTUP => C_SHARED_STARTUP,
-----------------
C_SPI_MODE => C_SPI_MODE
-----------------
)
port map
(
SCK_O => SCK_O_int, -- : in std_logic; -- input from the qspi_mode_0_module
IO1_I_startup => IO1_I, -- : in std_logic; -- input from the top level port list
IO1_Int => MISO_I_int,-- : out std_logic
Bus2IP_Clk => Bus2IP_Clk,
reset2ip_reset => reset2ip_reset_int,
CFGCLK => cfgclk, -- FGCLK , -- 1-bit output: Configuration main clock output
CFGMCLK => cfgmclk, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
EOS => eos, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => preq, -- REQ , -- 1-bit output: PROGRAM request to fabric output
DI => di_int, -- output
DO => do_int, -- 4-bit input
DTS => dts_int, -- 4-bit input
FCSBO => fcsbo_int, -- 1-bit input
FCSBTS => fcsbts_int,-- 1-bit input
CLK => clk, -- 1-bit input, SetReset
GSR => gsr, -- 1-bit input, SetReset
GTS => gts, -- 1-bit input
KEYCLEARB => keyclearb, --1-bit input
PACK => pack, --1-bit input
USRCCLKTS => usrcclkts, -- SRCCLKTS , -- 1-bit input
USRDONEO => usrdoneo, -- SRDONEO , -- 1-bit input
USRDONETS => usrdonets -- SRDONETS -- 1-bit input
);
--------------------
end generate SCK_MISO_STARTUP_USED;
-------------------------------------------------------
----------------------------------------------------------------------------
-- SPI_MODULE_I : INSTANTIATE SPI MODULE
----------------------------------------------------------------------------
SPI_MODULE_I: entity axi_quad_spi_v3_2_8.qspi_mode_0_module
-------------
generic map
(
C_SCK_RATIO => C_SCK_RATIO ,
C_USE_STARTUP => C_USE_STARTUP ,
C_SPICR_REG_WIDTH => C_SPICR_REG_WIDTH ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS ,
C_SUB_FAMILY => C_SUB_FAMILY ,
C_FIFO_EXIST => C_FIFO_EXIST
)
port map
(
Bus2IP_Clk => EXT_SPI_CLK, -- in
Soft_Reset_op => Rst_to_spi_int, -- in
------------------------
SPICR_0_LOOP => SPICR_0_LOOP_to_spi_clk,--_int,
SPICR_1_SPE => SPICR_1_SPE_to_spi_clk,--_int,
SPICR_2_MASTER_N_SLV => SPICR_2_MST_N_SLV_to_spi_clk,--_int,
SPICR_3_CPOL => SPICR_3_CPOL_to_spi_clk,--_int,
SPICR_4_CPHA => SPICR_4_CPHA_to_spi_clk,--_int,
SPICR_5_TXFIFO_RST => SPICR_5_TXFIFO_to_spi_clk, -- SPICR_5_TXFIFO_RST_to_spi_clk,--_int,
SPICR_6_RXFIFO_RST => SPICR_6_RXFIFO_RST_to_spi_clk,--_int,
SPICR_7_SS => SPICR_7_SS_to_spi_clk,--_int,
SPICR_8_TR_INHIBIT => SPICR_8_TR_INHIBIT_to_spi_clk,--_int,
SPICR_9_LSB => SPICR_9_LSB_to_spi_clk,--_int,
------------------------
Rx_FIFO_Empty_i_no_fifo => Rx_FIFO_Empty_i, -- in
SR_3_MODF => SR_3_modf_to_spi_clk, -- in
SR_5_Tx_Empty => Tx_FIFO_Empty, -- sr_5_Tx_Empty_int, -- in
Slave_MODF_strobe => slave_MODF_strobe_int, -- out
MODF_strobe => modf_strobe_int, -- out
Slave_Select_Reg => register_Data_slvsel_int, -- already updated -- in vec
Transmit_Data => Data_From_TxFIFO, -- transmit_Data_int, -- in vec
Receive_Data => Data_To_Rx_FIFO, -- receive_Data_int, -- out vec
SPIXfer_done => spiXfer_done_int, -- out
-- SPIXfer_done_Rx_Wr_en=> SPIXfer_done_Rx_Wr_en,
DTR_underrun => dtr_underrun_int, -- out
SPIXfer_done_rd_tx_en=> SPIXfer_done_rd_tx_en,
--SPI Ports
SCK_I => SCK_I, -- in
SCK_O_reg => SCK_O_int, -- out
SCK_T => SCK_T, -- out
MISO_I => str_IO1_I, --IO0_I, -- MOSI_I, -- in std_logic; -- MISO
MISO_O => str_IO1_O,--IO0_O, -- MOSI_O, -- out std_logic;
MISO_T => str_IO1_T, --IO0_T, -- MOSI_T, -- out std_logic;
MOSI_I => str_IO0_I,--MISO_I_int, -- IO1_I, -- MISO_I, -- in std_logic;
MOSI_O => str_IO0_O,--IO1_O, -- MISO_O, -- out std_logic; -- MOSI
MOSI_T => str_IO0_T,--IO1_T, -- MISO_T, -- out std_logic;
--MISO_I => MISO_I_int, -- IO1_I, -- MISO_I, -- in
--MISO_O => IO1_O, -- MISO_O, -- out
--MISO_T => IO1_T, -- MISO_T, -- out
--MOSI_I => IO0_I, -- MOSI_I, -- in
--MOSI_O => IO0_O, -- MOSI_O, -- out
--MOSI_T => IO0_T, -- MOSI_T, -- out
SPISEL => SPISEL, -- in
SS_I => SS_I_int, -- in
SS_O => SS_O_int, -- out
SS_T => SS_T_int, -- out
SPISEL_pulse_op => spisel_pulse_o_int , -- out std_logic;
SPISEL_d1_reg => spisel_d1_reg , -- out std_logic;
control_bit_7_8 => SPICR_bits_7_8_to_spi_clk, -- in vec
Mst_N_Slv_mode => Mst_N_Slv_mode ,
--Rx_FIFO_Full => Rx_FIFO_Full_to_spi_clk,
Rx_FIFO_Full => Rx_FIFO_Full_Fifo,
DRR_Overrun_reg => drr_Overrun_int, -- out
reset_RcFIFO_ptr_to_spi => reset_RcFIFO_ptr_to_spi_clk,
tx_cntr_xfer_done => tx_cntr_xfer_done
);
-------------
end generate LOGIC_FOR_MD_0_GEN;
----------------------------------------
-- LOGIC_FOR_MD_12_GEN: to generate the functionality for mode 1 and 2.
------------------------------
LOGIC_FOR_MD_12_GEN: if C_SPI_MODE /= 0 generate
---------------------------
signal SCK_O_int : std_logic;
signal MISO_I_int: std_logic;
signal Data_Dir_int : std_logic;
signal Data_Mode_1_int : std_logic;
signal Data_Mode_0_int : std_logic;
signal Data_Phase_int : std_logic;
signal Addr_Mode_1_int : std_logic;
signal Addr_Mode_0_int : std_logic;
signal Addr_Bit_int : std_logic;
signal Addr_Phase_int : std_logic;
signal CMD_Mode_1_int : std_logic;
signal CMD_Mode_0_int : std_logic;
signal CMD_Error_int : std_logic;
signal CMD_decoded_int : std_logic;
signal Dummy_Bits_int : std_logic_vector(3 downto 0);
-----
begin
-----
LOGIC_FOR_C_SPI_MODE_1_GEN: if C_SPI_MODE = 1 generate
-------
begin
-------
-- DATA_STARTUP_USED_MODE1 : if C_USE_STARTUP = 1 generate
-- -----
-- begin
-- -----
-- IO2_O <= do(2);
-- IO2_T <= dts(2);
-- IO3_O <= do(3);
-- IO3_T <= dts(3);
-- --IO2_I_int <= di(2);-- assign default value as this bit is not used in thid mode
-- IO2_I_int <= '0';-- assign default value as this bit is not used in thid mode
-- --IO3_I_int <= di(3);-- assign default value as this bit is not used in thid mode
-- IO3_I_int <= '0';-- assign default value as this bit is not used in thid mode
--end generate DATA_STARTUP_USED_MODE1;
--
--DATA_NOSTARTUP_USED_MODE1 : if C_USE_STARTUP = 0 generate
-- -----
-- begin
-- -----
IO2_O <= '0'; -- not used in the logic
IO3_O <= '0'; -- not used in the logic
IO2_T <= '1'; -- disable the tri-state buffers
IO3_T <= '1'; -- disable the tri-state buffers
IO2_I_int <= '0';-- assign default value as this bit is not used in thid mode
IO3_I_int <= '0';-- assign default value as this bit is not used in thid mode
--end generate DATA_NOSTARTUP_USED_MODE1;
end generate LOGIC_FOR_C_SPI_MODE_1_GEN;
---------------------------------------
LOGIC_FOR_C_SPI_MODE_2_GEN: if C_SPI_MODE = 2 generate
-------
begin
-------
DATA_STARTUP_USED_MODE2 : if (C_USE_STARTUP = 1 and C_UC_FAMILY = 1) generate
-----
begin
-----
di <= "00";
end generate DATA_STARTUP_USED_MODE2;
DATA_NOSTARTUP_USED_MODE2 : if (C_USE_STARTUP = 0 or (C_USE_STARTUP = 1 and C_UC_FAMILY = 0)) generate
-----
begin
-----
IO2_I_int <= IO2_I; -- assign this bit from the top level port
IO2_O <= IO2_O_int;
IO2_T <= IO2_T_int;
IO3_I_int <= IO3_I; -- assign this bit from the top level port
IO3_O <= IO3_O_int;
IO3_T <= IO3_T_int;
end generate DATA_NOSTARTUP_USED_MODE2;
end generate LOGIC_FOR_C_SPI_MODE_2_GEN;
---------------------------------------
SPISR_0_CMD_Error_int <= CMD_Error_int;
dtr_underrun_int <= '0'; -- SPI MODE 1 & 2 are master modes, so DTR under run wont be present
slave_MODF_strobe_int <= '0'; -- SPI MODE 1 & 2 are master modes, so the slave mode fault error wont appear
Mst_N_Slv_mode <= '1';
-------------------------------------------------------
-- SCK_O <= SCK_O_int; -- output from the core
-- MISO_I_int <= IO1_I; -- input to the core
-- *
-------------------------------------------------------
SCK_MISO_NO_STARTUP_USED: if C_USE_STARTUP = 0 generate
-----
begin
-----
SCK_O <= SCK_O_int; -- output from the core
MISO_I_int <= IO1_I; -- input to the core
end generate SCK_MISO_NO_STARTUP_USED;
-------------------------------------------------------
-------------------------------------------------------
SCK_MISO_STARTUP_USED: if C_USE_STARTUP = 1 generate
-----
begin
-----
QSPI_STARTUP_BLOCK_I: entity axi_quad_spi_v3_2_8.qspi_startup_block
---------------------
generic map
(
C_SUB_FAMILY => C_SUB_FAMILY , -- support for V6/V7/K7/A7 families only
-----------------
C_USE_STARTUP => C_USE_STARTUP,
-----------------
C_SHARED_STARTUP => C_SHARED_STARTUP,
-----------------
C_SPI_MODE => C_SPI_MODE
-----------------
)
port map
(
SCK_O => SCK_O_int, -- : in std_logic; -- input from the qspi_mode_0_module
IO1_I_startup => IO1_I, -- : in std_logic; -- input from the top level port list
IO1_Int => MISO_I_int,-- : out std_logic
Bus2IP_Clk => Bus2IP_Clk,
reset2ip_reset => reset2ip_reset_int,
CFGCLK => cfgclk, -- FGCLK , -- 1-bit output: Configuration main clock output
CFGMCLK => cfgmclk, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
EOS => eos, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => preq, -- REQ , -- 1-bit output: PROGRAM request to fabric output
DI => di_int, -- output
DO => do_int, -- 4-bit input
DTS => dts_int, -- 4-bit input
FCSBO => fcsbo_int, -- 1-bit input
FCSBTS => fcsbts_int,-- 1-bit input
CLK => clk, -- 1-bit input, SetReset
GSR => gsr, -- 1-bit input, SetReset
GTS => gts, -- 1-bit input
KEYCLEARB => keyclearb, --1-bit input
PACK => pack, --1-bit input
USRCCLKTS => usrcclkts, -- SRCCLKTS , -- 1-bit input
USRDONEO => usrdoneo, -- SRDONEO , -- 1-bit input
USRDONETS => usrdonets -- SRDONETS -- 1-bit input
);
--------------------
end generate SCK_MISO_STARTUP_USED;
-------------------------------------------------------
-- *
-- Add instance for Look up table logic
SPI_MODE_1_LUT_LOGIC_I: entity axi_quad_spi_v3_2_8.qspi_look_up_logic
-------------
generic map
(
C_FAMILY => C_FAMILY ,
C_SPI_MODE => C_SPI_MODE ,
C_SPI_MEMORY => C_SPI_MEMORY ,
C_SELECT_XPM => C_SELECT_XPM ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS
)
port map
(
EXT_SPI_CLK => EXT_SPI_CLK , -- : in std_logic;
Rst_to_spi => Rst_to_spi_int , -- : in std_logic;
TXFIFO_RST => reset_TxFIFO_ptr_int_to_spi, -- : in std_logic;
-------------------- --
DTR_FIFO_Data_Exists=> data_Exists_TxFIFO_int, -- : in std_logic;
Data_From_TxFIFO => Data_From_TxFIFO , -- : in std_logic_vector
-- (0 to (C_NUM_TRANSFER_BITS-1))
pr_state_idle => pr_state_idle_int , --
-------------------- --
Data_Dir => Data_Dir_int , -- : out std_logic;
Data_Mode_1 => Data_Mode_1_int , -- : out std_logic;
Data_Mode_0 => Data_Mode_0_int , -- : out std_logic;
Data_Phase => Data_Phase_int , -- : out std_logic;
-------------------- --
Quad_Phase => Quad_Phase_int ,
-------------------- --
Addr_Mode_1 => Addr_Mode_1_int , -- : out std_logic;
Addr_Mode_0 => Addr_Mode_0_int , -- : out std_logic;
Addr_Bit => Addr_Bit_int , -- : out std_logic;
Addr_Phase => Addr_Phase_int , -- : out std_logic;
-------------------- --
CMD_Mode_1 => CMD_Mode_1_int , -- : out std_logic;
CMD_Mode_0 => CMD_Mode_0_int , -- : out std_logic;
CMD_Error => CMD_Error_int , -- : out std_logic;
-------------------- -- -
CMD_decoded => CMD_decoded_int -- : out std_logic
);
---------
SPI_MODE_CONTROL_LOGIC_I: entity axi_quad_spi_v3_2_8.qspi_mode_control_logic
-------------
generic map
(
C_SCK_RATIO => C_SCK_RATIO ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS ,
C_SPI_MODE => C_SPI_MODE ,
C_USE_STARTUP => C_USE_STARTUP ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_SPI_MEMORY => C_SPI_MEMORY ,
C_SUB_FAMILY => C_SUB_FAMILY
)
port map
(
Bus2IP_Clk => EXT_SPI_CLK , -- Bus2IP_Clk , -- in std_logic;
Soft_Reset_op => Rst_to_spi_int , -- in std_logic;
-------------------- , --
DTR_FIFO_Data_Exists => data_Exists_TxFIFO_int , -- in std_logic;
Slave_Select_Reg => register_Data_slvsel_int , -- already updated -- in std_logic_vector(0 to (C_NUM_SS_BITS-1));
Transmit_Data => Data_From_TxFIFO,--transmit_Data_int , -- already updated -- in std_logic_vector(0 to (C_NUM_TRANSFER_BITS
Receive_Data => Data_To_Rx_FIFO , -- out std_logic_vector(0 to (C_NUM_TRANSFER_BITS
--Data_To_Rx_FIFO_1 => Data_To_Rx_FIFO_1,
SPIXfer_done => spiXfer_done_int , -- already updated -- out std_logic;
SPIXfer_done_Rx_Wr_en=> SPIXfer_done_Rx_Wr_en,
MODF_strobe => modf_strobe_int , -- already updated
SPIXfer_done_rd_tx_en=> SPIXfer_done_rd_tx_en,
--------------------- --
SR_3_MODF => SR_3_modf_to_spi_clk , -- in std_logic;
SR_5_Tx_Empty => Tx_FIFO_Empty , -- sr_5_Tx_Empty_int -- in std_logic;
--SR_6_Rx_Full => Rx_FIFO_Full , -- in
pr_state_idle => pr_state_idle_int , --
--------------------- -- from control register
SPICR_0_LOOP => SPICR_0_LOOP_to_spi_clk ,--SPICR_0_LOOP_int , -- in std_logic;
SPICR_1_SPE => SPICR_1_SPE_to_spi_clk ,--_int , -- in std_logic;
SPICR_2_MASTER_N_SLV => SPICR_2_MST_N_SLV_to_spi_clk,--_int , -- in std_logic;
SPICR_3_CPOL => SPICR_3_CPOL_to_spi_clk ,--_int , -- in std_logic;
SPICR_4_CPHA => SPICR_4_CPHA_to_spi_clk ,--_int , -- in std_logic;
SPICR_5_TXFIFO_RST => SPICR_5_TXFIFO_RST_to_spi_clk,--_int , -- in std_logic;
SPICR_6_RXFIFO_RST => SPICR_6_RXFIFO_RST_to_spi_clk,--_int , -- in std_logic;
SPICR_7_SS => SPICR_7_SS_to_spi_clk ,--_int , -- in std_logic;
SPICR_8_TR_INHIBIT => SPICR_8_TR_INHIBIT_to_spi_clk,--_int , -- in std_logic;
SPICR_9_LSB => SPICR_9_LSB_to_spi_clk ,--_int , -- in std_logic;
--------------------- --
--------------------- -- from look up table
Data_Dir => Data_Dir_int , -- in std_logic;
Data_Mode_1 => Data_Mode_1_int , -- in std_logic;
Data_Mode_0 => Data_Mode_0_int , -- in std_logic;
Data_Phase => Data_Phase_int ,
---------------------
--Dummy_Bits => Dummy_Bits_int , -- in std_logic_vector(3 downto 0);
Quad_Phase => Quad_Phase_int ,
--------------------- -- in std_logic;
Addr_Mode_1 => Addr_Mode_1_int , -- in std_logic;
Addr_Mode_0 => Addr_Mode_0_int , -- in std_logic;
Addr_Bit => Addr_Bit_int , -- in std_logic;
Addr_Phase => Addr_Phase_int , -- in std_logic;
---------------------
CMD_Mode_1 => CMD_Mode_1_int , -- in std_logic;
CMD_Mode_0 => CMD_Mode_0_int , -- in std_logic;
CMD_Error => CMD_Error_int , -- in std_logic;
--------------------- --
CMD_decoded => CMD_decoded_int , -- in std_logic;
--SPI Interface --
SCK_I => SCK_I, -- in std_logic;
SCK_O_reg => SCK_O_int, -- out std_logic;
SCK_T => SCK_T, -- out std_logic;
--
IO0_I => str_IO0_I, --IO0_I, -- MOSI_I, -- in std_logic; -- MISO
IO0_O => str_IO0_O,--IO0_O, -- MOSI_O, -- out std_logic;
IO0_T => str_IO0_T, --IO0_T, -- MOSI_T, -- out std_logic;
IO1_I => str_IO1_I,--MISO_I_int, -- IO1_I, -- MISO_I, -- in std_logic;
IO1_O => str_IO1_O,--IO1_O, -- MISO_O, -- out std_logic; -- MOSI
IO1_T => str_IO1_T,--IO1_T, -- MISO_T, -- out std_logic;
--
IO2_I => IO2_I_int, -- -- in std_logic;
IO2_O => IO2_O_int, -- -- out std_logic;
IO2_T => IO2_T_int, -- -- out std_logic;
--
IO3_I => IO3_I_int, -- -- in std_logic;
IO3_O => IO3_O_int, -- -- out std_logic;
IO3_T => IO3_T_int, -- -- out std_logic;
--
SPISEL => SPISEL, -- in std_logic;
--
SS_I => SS_I_int, -- in std_logic_vector(0 to (C_NUM_SS_BITS-1));
SS_O => SS_O_int, -- out std_logic_vector(0 to (C_NUM_SS_BITS-1));
SS_T => SS_T_int, -- out std_logic;
--
SPISEL_pulse_op => spisel_pulse_o_int , -- out std_logic;
SPISEL_d1_reg => spisel_d1_reg , -- out std_logic;
Control_bit_7_8 => SPICR_bits_7_8_to_spi_clk , -- in std_logic_vector(0 to 1) --(7 to 8)
Rx_FIFO_Full => Rx_FIFO_Full_Fifo,
DRR_Overrun_reg => drr_Overrun_int,
reset_RcFIFO_ptr_to_spi => reset_RcFIFO_ptr_to_spi_clk
);
-------------
end generate LOGIC_FOR_MD_12_GEN;
------------------------------------------
--------------------------------------------------------------------------------
CONTROL_REG_I: entity axi_quad_spi_v3_2_8.qspi_cntrl_reg
generic map
(
--------------------------
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
--------------------------
-- Number of bits in regis
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG,
--------------------------
C_SPICR_REG_WIDTH => C_SPICR_REG_WIDTH,
--------------------------
C_SPI_MODE => C_SPI_MODE
--------------------------
)
port map
( -- in
Bus2IP_Clk => Bus2IP_Clk, -- in
Soft_Reset_op => reset2ip_reset_int,
---------------------------
Wr_ce_reduce_ack_gen => Wr_ce_reduce_ack_gen, -- in
Bus2IP_SPICR_WrCE => Bus2IP_WrCE(SPICR), -- in
Bus2IP_SPICR_RdCE => Bus2IP_RdCE(SPICR), -- in
Bus2IP_SPICR_data => Bus2IP_Data, -- in vec
---------------------------
SPICR_0_LOOP => SPICR_0_LOOP_frm_axi_clk, -- out
SPICR_1_SPE => SPICR_1_SPE_frm_axi_clk, -- out
SPICR_2_MASTER_N_SLV => SPICR_2_MST_N_SLV_frm_axi_clk, -- out
SPICR_3_CPOL => SPICR_3_CPOL_frm_axi_clk, -- out
SPICR_4_CPHA => SPICR_4_CPHA_frm_axi_clk, -- out
SPICR_5_TXFIFO_RST => SPICR_5_TXFIFO_RST_frm_axi_clk, -- out
SPICR_6_RXFIFO_RST => SPICR_6_RXFIFO_RST_frm_axi_clk, -- out
SPICR_7_SS => SPICR_7_SS_frm_axi_clk, -- out
SPICR_8_TR_INHIBIT => SPICR_8_TR_INHIBIT_frm_axi_clk, -- out
SPICR_9_LSB => SPICR_9_LSB_frm_axi_clk, -- out
-- to Status Register
SPISR_1_LOOP_Back_Error => SPISR_1_LOOP_Back_Error_int, -- out
SPISR_2_MSB_Error => SPISR_2_MSB_Error_int, -- out
SPISR_3_Slave_Mode_Error => SPISR_3_Slave_Mode_Error_int, -- out
SPISR_4_CPOL_CPHA_Error => SPISR_4_CPOL_CPHA_Error_int, -- out
---------------------------
IP2Bus_SPICR_Data => IP2Bus_SPICR_Data_int, -- out vec
---------------------------
Control_bit_7_8 => SPICR_bits_7_8_frm_axi_clk -- out vec
---------------------------
);
-------------------------------------------------------------------------------
-- STATUS_REG_I : INSTANTIATE STATUS REGISTER
-------------------------------------------------------------------------------
STATUS_REG_MODE_0_GEN: if C_SPI_MODE = 0 generate
begin
STATUS_SLAVE_SEL_REG_I: entity axi_quad_spi_v3_2_8.qspi_status_slave_sel_reg
generic map(
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG ,
------------------------ ------------------------
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
------------------------ ------------------------
C_NUM_SS_BITS => C_NUM_SS_BITS ,
------------------------ ------------------------
C_SPISR_REG_WIDTH => C_SPISR_REG_WIDTH
)
port map(
Bus2IP_Clk => Bus2IP_Clk , -- in
Soft_Reset_op => reset2ip_reset_int , -- in
-- I/P from control regis
SPISR_0_Command_Error => '0' , -- SPISR_0_CMD_Error_int , -- in-- should come from look up table
SPISR_1_LOOP_Back_Error => SPISR_1_LOOP_Back_Error_int , -- in
SPISR_2_MSB_Error => SPISR_2_MSB_Error_int , -- in
SPISR_3_Slave_Mode_Error => SPISR_3_Slave_Mode_Error_int , -- in
SPISR_4_CPOL_CPHA_Error => SPISR_4_CPOL_CPHA_Error_int , -- in
-- I/P from other modules
SPISR_Ext_SPISEL_slave => spisel_d1_reg_to_axi_clk , -- in
SPISR_7_Tx_Full => Tx_FIFO_Full_int , -- in
SPISR_8_Tx_Empty => Tx_FIFO_Empty_SPISR_to_axi_clk, -- Tx_FIFO_Empty_to_Axi_clk , -- in
--SPISR_9_Rx_Full => Rx_FIFO_Full_int, -- Rx_FIFO_Full_to_axi_clk , -- in
SPISR_9_Rx_Full => Rx_FIFO_Full_Fifo_d1_synced, -- Rx_FIFO_Full_to_axi_clk , -- in
SPISR_10_Rx_Empty => Rx_FIFO_Empty_int , -- in
-- Slave attachment ports
ModeFault_Strobe => modf_strobe_to_axi_clk , -- in
Rd_ce_reduce_ack_gen => rd_ce_reduce_ack_gen , -- in
Bus2IP_SPISR_RdCE => Bus2IP_RdCE(SPISR) , -- in
IP2Bus_SPISR_Data => IP2Bus_SPISR_Data_int , -- out vec
SR_3_modf => SR_3_modf_int , -- out
-- Slave Select Register
Bus2IP_SPISSR_WrCE => Bus2IP_WrCE(SPISSR) , -- in
Wr_ce_reduce_ack_gen => Wr_ce_reduce_ack_gen , -- in
Bus2IP_SPISSR_RdCE => Bus2IP_RdCE(SPISSR) , -- in
Bus2IP_SPISSR_Data => Bus2IP_Data , -- in vec
IP2Bus_SPISSR_Data => IP2Bus_SPISSR_Data_int , -- out vec
SPISSR_Data_reg_op => SPISSR_frm_axi_clk -- out vec
);
end generate STATUS_REG_MODE_0_GEN;
STATUS_REG_MODE_12_GEN: if C_SPI_MODE /= 0 generate
begin
STATUS_SLAVE_SEL_REG_I: entity axi_quad_spi_v3_2_8.qspi_status_slave_sel_reg
generic map(
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG ,
------------------------ ------------------------
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
------------------------ ------------------------
C_NUM_SS_BITS => C_NUM_SS_BITS ,
------------------------ ------------------------
C_SPISR_REG_WIDTH => C_SPISR_REG_WIDTH
)
port map(
Bus2IP_Clk => Bus2IP_Clk , -- in
Soft_Reset_op => reset2ip_reset_int , -- in
-- I/P from control regis
SPISR_0_Command_Error => SPISR_0_CMD_Error_to_axi_clk , -- SPISR_0_CMD_Error_int , -- in-- should come from look up table
SPISR_1_LOOP_Back_Error => SPISR_1_LOOP_Back_Error_int , -- in
SPISR_2_MSB_Error => SPISR_2_MSB_Error_int , -- in
SPISR_3_Slave_Mode_Error => SPISR_3_Slave_Mode_Error_int , -- in
SPISR_4_CPOL_CPHA_Error => SPISR_4_CPOL_CPHA_Error_int , -- in
-- I/P from other modules
SPISR_Ext_SPISEL_slave => spisel_d1_reg_to_axi_clk , -- in
SPISR_7_Tx_Full => Tx_FIFO_Full_int , -- in
SPISR_8_Tx_Empty => Tx_FIFO_Empty_SPISR_to_axi_clk, -- Tx_FIFO_Empty_to_Axi_clk , -- in
--SPISR_9_Rx_Full => Rx_FIFO_Full_int, -- Rx_FIFO_Full_to_axi_clk , -- in
SPISR_9_Rx_Full => Rx_FIFO_Full_Fifo_d1_synced, -- Rx_FIFO_Full_to_axi_clk , -- in
SPISR_10_Rx_Empty => Rx_FIFO_Empty_int , -- in
-- Slave attachment ports
ModeFault_Strobe => modf_strobe_to_axi_clk , -- in
Rd_ce_reduce_ack_gen => rd_ce_reduce_ack_gen , -- in
Bus2IP_SPISR_RdCE => Bus2IP_RdCE(SPISR) , -- in
IP2Bus_SPISR_Data => IP2Bus_SPISR_Data_int , -- out vec
SR_3_modf => SR_3_modf_int , -- out
-- Slave Select Register
Bus2IP_SPISSR_WrCE => Bus2IP_WrCE(SPISSR) , -- in
Wr_ce_reduce_ack_gen => Wr_ce_reduce_ack_gen , -- in
Bus2IP_SPISSR_RdCE => Bus2IP_RdCE(SPISSR) , -- in
Bus2IP_SPISSR_Data => Bus2IP_Data , -- in vec
IP2Bus_SPISSR_Data => IP2Bus_SPISSR_Data_int , -- out vec
SPISSR_Data_reg_op => SPISSR_frm_axi_clk -- out vec
);
end generate STATUS_REG_MODE_12_GEN;
-------------------------------------------------------------------------------
-- SOFT_RESET_I : INSTANTIATE SOFT RESET
-------------------------------------------------------------------------------
SOFT_RESET_I: entity axi_quad_spi_v3_2_8.soft_reset
generic map
(
C_SIPIF_DWIDTH => C_S_AXI_DATA_WIDTH,
-- Width of triggered reset in Bus Clocks
C_RESET_WIDTH => 16
)
port map
(
-- Inputs From the PLBv46 Slave Single Bus
Bus2IP_Clk => Bus2IP_Clk, -- in
Bus2IP_Reset => Bus2IP_Reset, -- in
Bus2IP_WrCE => Bus2IP_WrCE(SWRESET), -- in
Bus2IP_Data => Bus2IP_Data, -- in
Bus2IP_BE => Bus2IP_BE, -- in
-- Final Device Reset Output
Reset2IP_Reset => reset2ip_reset_int, -- out
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck => rst_ip2bus_wrack, -- out
Reset2Bus_Error => rst_ip2bus_error, -- out
Reset2Bus_ToutSup => open -- out
);
-------------------------------------------------------------------------------
-- INTERRUPT_CONTROL_I : INSTANTIATE INTERRUPT CONTROLLER
-------------------------------------------------------------------------------
bus2ip_intr_rdce <= "0000000" &
Bus2IP_RdCE(7) &
Bus2IP_RdCE(8) &
'0' &
Bus2IP_RdCE(10)&
"00000";
bus2ip_intr_wrce <= "0000000" &
Bus2IP_WrCE(7) &
Bus2IP_WrCE(8) &
'0' &
Bus2IP_WrCE(10)&
"00000";
------------------------------------------------------------------------------
intr_controller_rd_ce_or_reduce <= or_reduce(Bus2IP_RdCE(0 to 6)) or
Bus2IP_RdCE(9) or
or_reduce(Bus2IP_RdCE(11 to 15));
------------------------------------------------------------------------------
I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_RdAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_RdAck_intr_reg_hole_d1 <= intr_controller_rd_ce_or_reduce;
ip2Bus_RdAck_intr_reg_hole <= intr_controller_rd_ce_or_reduce and
(not ip2Bus_RdAck_intr_reg_hole_d1);
end if;
end if;
end process I_READ_ACK_INTR_HOLES;
------------------------------------------------------------------------------
intr_controller_wr_ce_or_reduce <= or_reduce(Bus2IP_WrCE(0 to 6)) or
Bus2IP_WrCE(9) or
or_reduce(Bus2IP_WrCE(11 to 15));
------------------------------------------------------------------------------
I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_WrAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_WrAck_intr_reg_hole_d1 <= intr_controller_wr_ce_or_reduce;
ip2Bus_WrAck_intr_reg_hole <= intr_controller_wr_ce_or_reduce and
(not ip2Bus_WrAck_intr_reg_hole_d1);
end if;
end if;
end process I_WRITE_ACK_INTR_HOLES;
------------------------------------------------------------------------------
INTERRUPT_CONTROL_I: entity interrupt_control_v3_1_4.interrupt_control
generic map
(
C_NUM_CE => 16,
C_NUM_IPIF_IRPT_SRC => 1, -- Set to 1 to avoid null array
C_IP_INTR_MODE_ARRAY => C_IP_INTR_MODE_ARRAY,
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_PENCODER => false,
-- Specifies device ISC hierarchy
C_INCLUDE_DEV_ISC => false,
C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH
)
port map
(
Bus2IP_Clk => Bus2IP_Clk, -- in
Bus2IP_Reset => reset2ip_reset_int, -- in
Bus2IP_Data => bus2IP_Data_for_interrupt_core, -- in vec
Bus2IP_BE => Bus2IP_BE, -- in vec
Interrupt_RdCE => bus2ip_intr_rdce, -- in vec
Interrupt_WrCE => bus2ip_intr_wrce, -- in vec
IPIF_Reg_Interrupts => "00", -- Tie off the unused reg intrs
IPIF_Lvl_Interrupts => "0", -- Tie off the dummy lvl intr
IP2Bus_IntrEvent => ip2Bus_IntrEvent_int, -- in
Intr2Bus_DevIntr => IP2INTC_Irpt, -- out
Intr2Bus_DBus => intr_ip2bus_data, -- out vec
Intr2Bus_WrAck => intr_ip2bus_wrack, -- out
Intr2Bus_RdAck => intr_ip2bus_rdack, -- out
Intr2Bus_Error => intr_ip2bus_error, -- out
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
--------------------------------------------------------------------------------
end imp;
--------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- qspi_core_interface Module - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: qspi_core_interface.vhd
-- Version: v3.0
-- Description: Serial Peripheral Interface (SPI) Module for interfacing
-- with a 32-bit AXI bus.
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.vcomponents.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.async_fifo_fg;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
library lib_cdc_v1_0_2;
use lib_cdc_v1_0_2.cdc_sync;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.all;
use lib_pkg_v1_0_2.lib_pkg.log2;
-- use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
use lib_pkg_v1_0_2.lib_pkg.RESET_ACTIVE;
library interrupt_control_v3_1_4;
library axi_quad_spi_v3_2_8;
use axi_quad_spi_v3_2_8.all;
-------------------------------------------------------------------------------
entity qspi_core_interface is
generic(
C_FAMILY : string;
C_SUB_FAMILY : string;
C_SELECT_XPM : integer := 1;
C_UC_FAMILY : integer;
C_S_AXI_DATA_WIDTH : integer;
Async_Clk : integer;
----------------------
-- local parameters
C_NUM_CE_SIGNALS : integer;
----------------------
-- SPI parameters
--C_AXI4_CLK_PS : integer;
--C_EXT_SPI_CLK_PS : integer;
C_FIFO_DEPTH : integer;
C_SCK_RATIO : integer;
C_NUM_SS_BITS : integer;
C_NUM_TRANSFER_BITS : integer;
C_SPI_MODE : integer;
C_USE_STARTUP : integer;
C_SPI_MEMORY : integer;
C_SHARED_STARTUP : integer range 0 to 1 := 0;
C_TYPE_OF_AXI4_INTERFACE : integer;
----------------------
-- local constants
C_FIFO_EXIST : integer;
C_SPI_NUM_BITS_REG : integer;
C_OCCUPANCY_NUM_BITS : integer;
----------------------
-- local constants
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE;
----------------------
-- local constants
C_SPICR_REG_WIDTH : integer;
C_SPISR_REG_WIDTH : integer;
C_LSB_STUP : integer
);
port(
EXT_SPI_CLK : in std_logic;
------------------------------------------------
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
------------------------------------------------
Bus2IP_BE : in std_logic_vector(0 to ((C_S_AXI_DATA_WIDTH/8)-1));
Bus2IP_RdCE : in std_logic_vector(0 to (C_NUM_CE_SIGNALS-1));
Bus2IP_WrCE : in std_logic_vector(0 to (C_NUM_CE_SIGNALS-1));
Bus2IP_Data : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
------------------------------------------------
IP2Bus_Data : out std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
IP2Bus_WrAck : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_Error : out std_logic;
------------------------------------------------
burst_tr : in std_logic;
rready : in std_logic;
WVALID : in std_logic;
--SPI Ports
SCK_I : in std_logic;
SCK_O : out std_logic;
SCK_T : out std_logic;
------------------------------------------------
IO0_I : in std_logic;
IO0_O : out std_logic;
IO0_T : out std_logic;
------------------------------------------------
IO1_I : in std_logic;
IO1_O : out std_logic;
IO1_T : out std_logic;
------------------------------------------------
IO2_I : in std_logic;
IO2_O : out std_logic;
IO2_T : out std_logic;
------------------------------------------------
IO3_I : in std_logic;
IO3_O : out std_logic;
IO3_T : out std_logic;
------------------------------------------------
SPISEL : in std_logic;
------------------------------------------------
SS_I : in std_logic_vector((C_NUM_SS_BITS-1) downto C_LSB_STUP);
SS_O : out std_logic_vector((C_NUM_SS_BITS-1) downto C_LSB_STUP);
SS_T : out std_logic;
------------------------------------------------
IP2INTC_Irpt : out std_logic;
------------------------------------------------
------------------------
-- STARTUP INTERFACE
------------------------
cfgclk : out std_logic; -- FGCLK , -- 1-bit output: Configuration main clock output
cfgmclk : out std_logic; -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
eos : out std_logic; -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
preq : out std_logic; -- REQ , -- 1-bit output: PROGRAM request to fabric output
di : out std_logic_vector(1 downto 0); -- output
dts : in std_logic_vector(1 downto 0); -- input
do : in std_logic_vector(1 downto 0); -- input
-- fcsbo : in std_logic; -- input
-- fcsbts : in std_logic; -- input
clk : in std_logic; -- input
gsr : in std_logic; -- input
gts : in std_logic; -- input
keyclearb : in std_logic; -- input
pack : in std_logic; -- input
usrcclkts : in std_logic; -- input
usrdoneo : in std_logic; -- input
usrdonets : in std_logic -- input
);
end entity qspi_core_interface;
-------------------------------------------------------------------------------
------------
architecture imp of qspi_core_interface is
------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- function definition
----------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- constant definition
constant NEW_LOGIC : integer := 0;
-- These constants are indices into the "CE" arrays for the various registers.
constant INTR_LO : natural := 0;
constant INTR_HI : natural := 15;
constant SWRESET : natural := 16; -- at address C_BASEADDR + 40 h
constant SPICR : natural := 24; -- 17; -- at address C_BASEADDR + 60 h
constant SPISR : natural := 25; -- 18;
constant SPIDTR : natural := 26; -- 19;
constant SPIDRR : natural := 27; -- 20;
constant SPISSR : natural := 28; -- 21;
constant SPITFOR : natural := 29; -- 22;
constant SPIRFOR : natural := 30; -- 23; -- at address C_BASEADDR + 78 h
constant REG_HOLE : natural := 31; -- 24; -- at address C_BASEADDR + 7C h
--Startup Signals
signal str_IO0_I : std_logic;
signal str_IO0_O : std_logic;
signal str_IO0_T : std_logic;
signal str_IO1_I : std_logic;
signal str_IO1_O : std_logic;
signal str_IO1_T : std_logic;
signal di_int : std_logic_vector(3 downto 0); -- output
signal di_int_sync : std_logic_vector(3 downto 0); -- output
signal dts_int : std_logic_vector(3 downto 0); -- input
signal do_int : std_logic_vector(3 downto 0); -- input
--SPI MODULE SIGNALS
signal spiXfer_done_int : std_logic;
signal dtr_underrun_int : std_logic;
signal modf_strobe_int : std_logic;
signal slave_MODF_strobe_int : std_logic;
--OR REGISTER/FIFO SIGNALS
--TO/FROM REG/FIFO DATA
signal receive_Data_int : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_int : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
--Extra bit required for signal Register_Data_ctrl
signal register_Data_cntrl_int :std_logic_vector(0 to (C_SPI_NUM_BITS_REG+1));
signal register_Data_slvsel_int:std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal IP2Bus_SPICR_Data_int :std_logic_vector(0 to (C_SPICR_REG_WIDTH-1));
signal IP2Bus_SPISR_Data_int :std_logic_vector(0 to (C_SPISR_REG_WIDTH-1));
signal IP2Bus_Receive_Reg_Data_int :std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal IP2Bus_Data_received_int:
std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
signal IP2Bus_SPISSR_Data_int : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal IP2Bus_Tx_FIFO_OCC_Reg_Data_int:
std_logic_vector(0 to (C_OCCUPANCY_NUM_BITS-1));
signal IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1:
std_logic_vector((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1:
std_logic_vector((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal IP2Bus_Rx_FIFO_OCC_Reg_Data_int:
std_logic_vector(0 to (C_OCCUPANCY_NUM_BITS-1));
--STATUS REGISTER SIGNALS
signal sr_3_MODF_int : std_logic;
signal Tx_FIFO_Full_int : std_logic;
signal sr_5_Tx_Empty_int : std_logic;
signal tx_empty_signal_handshake_req : std_logic;
signal tx_empty_signal_handshake_gnt : std_logic;
signal sr_6_Rx_Full_int : std_logic;
signal Rc_FIFO_Empty_int : std_logic;
--RECEIVE AND TRANSMIT REGISTER SIGNALS
signal drr_Overrun_int : std_logic;
signal dtr_Underrun_strobe_int : std_logic;
--FIFO SIGNALS
signal rc_FIFO_Full_strobe_int : std_logic;
signal rc_FIFO_occ_Reversed_int :std_logic_vector
((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal rc_FIFO_occ_Reversed_int_2 :std_logic_vector
((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal rc_FIFO_Data_Out_int : std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1));
signal sr_6_Rx_Full_int_1 : std_logic;
signal FIFO_Empty_rx_1 : std_logic;
signal FIFO_Empty_rx : std_logic;
signal data_Exists_RcFIFO_int : std_logic;
signal tx_FIFO_Empty_strobe_int : std_logic;
signal tx_FIFO_occ_Reversed_int : std_logic_vector
((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal tx_FIFO_occ_Reversed_int_2 : std_logic_vector
((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal data_Exists_TxFIFO_int : std_logic;
signal data_Exists_TxFIFO_int_1 : std_logic;
signal data_From_TxFIFO_int : std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1));
signal tx_FIFO_less_half_int : std_logic;
signal Tx_FIFO_Full_int_1 : std_logic;
signal FIFO_Empty_tx : std_logic;
signal data_From_TxFIFO_int_1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal tx_occ_msb : std_logic;
signal tx_occ_msb_1 : std_logic:= '0';
signal tx_occ_msb_2 : std_logic;
signal tx_occ_msb_3 : std_logic;
signal tx_occ_msb_4 : std_logic;
signal reset_TxFIFO_ptr_int : std_logic;
signal reset_TxFIFO_ptr_int_to_spi : std_logic;
signal reset_RcFIFO_ptr_int : std_logic;
signal reset_RcFIFO_ptr_to_spi_clk : std_logic;
signal ip2Bus_Data_Reg_int : std_logic_vector
(0 to (C_S_AXI_DATA_WIDTH-1));
signal ip2Bus_Data_occupancy_int: std_logic_vector
(0 to (C_S_AXI_DATA_WIDTH-1));
signal ip2Bus_Data_SS_int : std_logic_vector
(0 to (C_S_AXI_DATA_WIDTH-1));
-- interface between signals on instance basis
signal bus2IP_Reset_int : std_logic;
signal bus2IP_Data_for_interrupt_core : std_logic_vector
(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2Bus_Error_int : std_logic;
signal ip2Bus_WrAck_int : std_logic;-- := '0';
signal ip2Bus_RdAck_int : std_logic;-- := '0';
signal ip2Bus_IntrEvent_int : std_logic_vector
(0 to (C_IP_INTR_MODE_ARRAY'length-1));
signal transmit_ip2bus_error : std_logic;
signal receive_ip2bus_error : std_logic;
-- SOFT RESET SIGNALS
signal reset2ip_reset_int : std_logic;
signal rst_ip2bus_wrack : std_logic;
signal rst_ip2bus_error : std_logic;
signal rst_ip2bus_rdack : std_logic;
-- INTERRUPT SIGNALS
signal intr_ip2bus_data : std_logic_vector
(0 to (C_S_AXI_DATA_WIDTH-1));
signal intr_ip2bus_rdack : std_logic;
signal intr_ip2bus_wrack : std_logic;
signal intr_ip2bus_error : std_logic;
signal ip2bus_error_RdWr : std_logic;
--
signal wr_ce_reduce_ack_gen: std_logic;
--
signal rd_ce_reduce_ack_gen : std_logic;
--
signal control_bit_7_8_int : std_logic_vector(0 to 1);
signal spisel_pulse_o_int : std_logic;
signal Interrupt_WrCE_sig : std_logic_vector(0 to 1);
signal IPIF_Lvl_Interrupts_sig : std_logic;
signal spisel_d1_reg : std_logic;
signal Mst_N_Slv_mode : std_logic;
-----
signal bus2ip_intr_rdce : std_logic_vector(INTR_LO to INTR_HI);
signal bus2ip_intr_wrce : std_logic_vector(INTR_LO to INTR_HI);
signal ip2Bus_RdAck_intr_reg_hole : std_logic;
signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic;
signal ip2Bus_WrAck_intr_reg_hole : std_logic;
signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic;
signal intr_controller_rd_ce_or_reduce : std_logic;
signal intr_controller_wr_ce_or_reduce : std_logic;
signal wr_ce_or_reduce_core_cmb : std_logic;
signal ip2Bus_WrAck_core_reg_d1 : std_logic;
signal ip2Bus_WrAck_core_reg : std_logic;
signal rd_ce_or_reduce_core_cmb : std_logic;
signal ip2Bus_RdAck_core_reg_d1 : std_logic;
signal ip2Bus_RdAck_core_reg : std_logic;
signal SPISR_0_CMD_Error_int : std_logic;
signal SPISR_1_LOOP_Back_Error_int : std_logic;
signal SPISR_2_MSB_Error_int : std_logic;
signal SPISR_3_Slave_Mode_Error_int : std_logic;
signal SPISR_4_CPOL_CPHA_Error_int : std_logic;
signal SPISR_Ext_SPISEL_slave_int : std_logic;
signal SPICR_5_TXFIFO_RST_int : std_logic;
-- signal SPICR_6_RXFIFO_RST_int : std_logic;
signal pr_state_idle_int : std_logic;
signal Quad_Phase_int : std_logic;
signal SPICR_0_LOOP_frm_axi :std_logic;
signal SPICR_0_LOOP_to_spi :std_logic;
signal SPICR_1_SPE_frm_axi :std_logic;
signal SPICR_1_SPE_to_spi :std_logic;
signal SPICR_2_MST_N_SLV_frm_axi :std_logic;
signal SPICR_2_MST_N_SLV_to_spi :std_logic;
signal SPICR_3_CPOL_frm_axi :std_logic;
signal SPICR_3_CPOL_to_spi :std_logic;
signal SPICR_4_CPHA_frm_axi :std_logic;
signal SPICR_4_CPHA_to_spi :std_logic;
signal SPICR_5_TXFIFO_frm_axi :std_logic;
signal SPICR_5_TXFIFO_to_spi :std_logic;
--signal SPICR_6_RXFIFO_RST_frm_axi:std_logic;
--signal SPICR_6_RXFIFO_RST_to_spi :std_logic;
signal SPICR_7_SS_frm_axi :std_logic;
signal SPICR_7_SS_to_spi :std_logic;
signal SPICR_8_TR_INHIBIT_frm_axi:std_logic;
signal SPICR_8_TR_INHIBIT_to_spi :std_logic;
signal SPICR_9_LSB_frm_axi :std_logic;
signal SPICR_9_LSB_to_spi :std_logic;
signal SPICR_bits_7_8_frm_spi :std_logic;
signal SPICR_bits_7_8_to_axi :std_logic;
signal Rx_FIFO_Empty : std_logic;
signal Rx_FIFO_Empty_Synced_in_SPI_domain : std_logic;
signal rx_fifo_full_to_spi_clk : std_logic;
signal tx_fifo_empty_to_axi_clk : std_logic;
signal tx_fifo_full : std_logic;
signal spisel_d1_reg_to_axi_clk : std_logic;
signal spicr_bits_7_8_frm_axi_clk : std_logic_vector(1 downto 0);
signal spicr_8_tr_inhibit_to_spi_clk : std_logic;
signal spicr_9_lsb_to_spi_clk : std_logic;
signal spicr_bits_7_8_to_spi_clk : std_logic_vector(0 to 1);
signal spicr_0_loop_frm_axi_clk : std_logic;
signal spicr_1_spe_frm_axi_clk : std_logic;
signal spicr_2_mst_n_slv_frm_axi_clk : std_logic;
signal spicr_3_cpol_frm_axi_clk : std_logic;
signal spicr_4_cpha_frm_axi_clk : std_logic;
signal spicr_5_txfifo_rst_frm_axi_clk : std_logic;
signal spicr_6_rxfifo_rst_frm_axi_clk : std_logic;
signal spicr_7_ss_frm_axi_clk : std_logic;
signal spicr_8_tr_inhibit_frm_axi_clk : std_logic;
signal spicr_9_lsb_frm_axi_clk : std_logic;
signal Tx_FIFO_wr_ack_1 : std_logic;
signal rst_to_spi_int : std_logic;
signal spicr_0_loop_to_spi_clk : std_logic;
signal spicr_1_spe_to_spi_clk : std_logic;
signal spicr_2_mas_n_slv_to_spi_clk : std_logic;
signal spicr_3_cpol_to_spi_clk : std_logic;
signal spicr_4_cpha_to_spi_clk : std_logic;
signal spicr_5_txfifo_rst_to_spi_clk : std_logic;
signal spicr_6_rxfifo_rst_to_spi_clk : std_logic;
signal spicr_7_ss_to_spi_clk : std_logic;
signal sr_3_modf_to_spi_clk : std_logic;
signal sr_3_modf_frm_axi_clk : std_logic;
signal data_from_txfifo : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal Bus2IP_WrCE_d1 : std_logic;
signal Bus2IP_WrCE_d2 : std_logic;
signal Bus2IP_WrCE_d3 : std_logic;
signal Bus2IP_WrCE_pulse_1 : std_logic;
signal Bus2IP_WrCE_pulse_2 : std_logic;
signal Bus2IP_WrCE_pulse_3 : std_logic;
signal data_to_txfifo : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal tx_fifo_wr_ack : std_logic;
-- signal ext_spi_clk : std_logic;
signal tx_fifo_rd_ack_open : std_logic;
signal tx_fifo_empty : std_logic;
signal tx_fifo_almost_full : std_logic;
signal tx_fifo_almost_empty : std_logic;
signal tx_fifo_occ_reversed : std_logic_vector((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal c_wr_count_width : std_logic;
signal rx_fifo_wr_ack_open : std_logic;
signal data_from_rx_fifo : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal rx_fifo_rd_ack : std_logic;
signal rx_fifo_full : std_logic;
signal rx_fifo_almost_full : std_logic;
signal rx_fifo_almost_empty : std_logic;
signal rx_fifo_occ_reversed : std_logic_vector((C_OCCUPANCY_NUM_BITS-1) downto 0);
signal SPISSR_frm_axi_clk : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal modf_strobe_frm_spi_clk : std_logic;
signal modf_strobe_to_axi_clk : std_logic;
signal dtr_underrun_frm_spi_clk : std_logic;
signal dtr_underrun_to_axi_clk : std_logic;
signal data_to_rx_fifo : std_logic_vector
(0 to (C_NUM_TRANSFER_BITS-1));
signal spisel_d1_reg_frm_spi_clk : std_logic;
signal Mst_N_Slv_mode_frm_spi_clk: std_logic;
signal Mst_N_Slv_mode_to_axi_clk : std_logic;
signal SPICR_2_MST_N_SLV_to_spi_clk : std_logic;
signal spicr_5_txfifo_frm_axi_clk : std_logic;
signal spicr_5_txfifo_to_spi_clk: std_logic;
signal reset_RcFIFO_ptr_frm_axi_clk : std_logic;
-- signal reset_RcFIFO_ptr_to_spi_clk : std_logic;
signal Data_To_Rx_FIFO_1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal SPIXfer_done_Rx_Wr_en, SPIXfer_done_rd_tx_en: std_logic;
signal Tx_FIFO_Empty_SPISR_frm_spi_clk : std_logic;
signal Tx_FIFO_Empty_SPISR_to_axi_clk : std_logic;
signal Tx_FIFO_Empty_frm_spi_clk : std_logic;
signal Rx_FIFO_Full_frm_axi_clk : std_logic;
signal Rx_FIFO_Full_int,Rx_FIFO_Full_i,RX_one_less_than_full, not_Tx_FIFO_FULL : std_logic;
signal updown_cnt_en_tx, updown_cnt_en_rx : std_logic;
signal TX_one_less_than_full : std_logic;
signal tx_cntr_xfer_done : std_logic;
signal Tx_FIFO_one_less_to_Empty, Tx_FIFO_Full_i: std_logic;
signal Tx_FIFO_Empty_i, Tx_FIFO_Empty_int : std_logic;
signal Tx_FIFO_Empty_frm_axi_clk : std_logic;
signal rx_fifo_empty_i : std_logic;
signal Rx_FIFO_Empty_int : std_logic;
signal IP2Bus_WrAck_1 : std_logic;
signal ip2Bus_WrAck_core_reg_1 : std_logic;
signal IP2Bus_RdAck_1 : std_logic;
signal ip2Bus_RdAck_core_reg_1 : std_logic;
signal IP2Bus_Error_1 : std_logic;
signal ip2Bus_Data_1 : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1)) ;
signal SPISR_0_CMD_Error_frm_spi_clk : std_logic;
signal SPISR_0_CMD_Error_to_axi_clk : std_logic;
signal rx_fifo_reset, tx_fifo_reset : std_logic;
signal reg_hole_wr_ack: std_logic;
signal reg_hole_rd_ack: std_logic;
signal read_ack_delay_1: std_logic;
signal read_ack_delay_2: std_logic;
signal read_ack_delay_3: std_logic;
signal read_ack_delay_4: std_logic;
signal read_ack_delay_5: std_logic;
signal read_ack_delay_6: std_logic;
signal read_ack_delay_7: std_logic;
signal read_ack_delay_8: std_logic;
signal write_ack_delay_1: std_logic;
signal write_ack_delay_2: std_logic;
signal write_ack_delay_3: std_logic;
signal write_ack_delay_4: std_logic;
signal write_ack_delay_5: std_logic;
signal write_ack_delay_6: std_logic;
signal write_ack_delay_7: std_logic;
signal write_ack_delay_8: std_logic;
signal error_ack_delay_1: std_logic;
signal error_ack_delay_2: std_logic;
signal error_ack_delay_3: std_logic;
signal error_ack_delay_4: std_logic;
signal error_ack_delay_5: std_logic;
signal error_ack_delay_6: std_logic;
signal error_ack_delay_7: std_logic;
signal error_ack_delay_8: std_logic;
signal IO2_O_int : std_logic;
signal IO2_T_int : std_logic;
signal IO3_O_int : std_logic;
signal IO3_T_int : std_logic;
signal IO2_I_int : std_logic;
signal IO3_I_int : std_logic;
signal fcsbo_int : std_logic;
signal SS_O_int : std_logic_vector((C_NUM_SS_BITS-1) downto 0);
signal SS_T_int : std_logic;
signal SS_I_int : std_logic_vector((C_NUM_SS_BITS-1) downto 0);
signal fcsbts_int : std_logic;
----RX_FIFO_FULL Logic signals
signal Rx_FIFO_Full_Fifo_org : std_logic;
signal Rx_FIFO_Full_Fifo : std_logic;
signal Rx_FIFO_Full_Fifo_d1 : std_logic;
signal Rx_FIFO_Full_Fifo_d1_synced : std_logic;
signal Rx_FIFO_Full_Fifo_d1_synced_i : std_logic;
signal Rx_FIFO_Full_Fifo_d1_flag : std_logic;
signal Rx_FIFO_Full_Fifo_pos_flag : std_logic;
signal Rx_FIFO_Full_Fifo_d1_sig : std_logic;
--------------------------------------------------------------------------------
begin
-----
DATA_STARTUP_EN : if (C_USE_STARTUP = 1 and C_UC_FAMILY = 1)
generate
-----
begin
-----
---
DI_INT_IO3_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => di_int_sync(3),
C => EXT_SPI_CLK,
D => di_int(3) --MOSI_I
);
DI_INT_IO2_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => di_int_sync(2),
C => EXT_SPI_CLK,
D => di_int(2) -- MISO_I
);
DI_INT_IO1_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => di_int_sync(1),
C => EXT_SPI_CLK,
D => di_int(1)
);
-----------------------
DI_INT_IO0_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => di_int_sync(0),
C => EXT_SPI_CLK,
D => di_int(0)
);
---
fcsbo_int <= SS_O_int(0);
fcsbts_int <= SS_T_int;
NUM_SS : if (C_NUM_SS_BITS = 1) generate
begin
SS_O <= (others => '0');
SS_T <= '0';
end generate NUM_SS;
NUM_SS_G1 : if (C_NUM_SS_BITS > 1) generate
begin
SS_I_int <= SS_I((C_NUM_SS_BITS-1) downto 1) & '1';
SS_O <= SS_O_int((C_NUM_SS_BITS-1) downto 1);
SS_T <= SS_T_int;
end generate NUM_SS_G1;
str_IO0_I <= di_int_sync(0);
do_int(0) <= str_IO0_O;
dts_int(0) <= str_IO0_T ;
str_IO1_I <= di_int_sync(1);
do_int(1) <= str_IO1_O;
dts_int(1) <= str_IO1_T;
DATA_OUT_NQUAD: if C_SPI_MODE = 0 or C_SPI_MODE = 1 generate
begin
di <= di_int_sync(3) & di_int_sync(2);
do_int(2) <= do(0);
do_int(3) <= do(1);
dts_int(2) <= dts(0);
dts_int(3) <= dts(1);
--do <= do_int(3) & do_int(1);
--dts <= dts_int(3) & dts_int(1);
end generate DATA_OUT_NQUAD;
DATA_OUT_QUAD: if C_SPI_MODE = 2 generate
begin
--di <= "00";--di_int_sync(3) & di_int_sync(2);
IO2_I_int <= di_int_sync(2);
do_int(2) <= IO2_O_int;--do(2);
do_int(3) <= IO3_O_int;--do(1);
--do <= do_int(3) & do_int(1);
IO3_I_int <= di_int_sync(3);
dts_int(2) <= IO2_T_int;--dts_int(3) & dts_int(1);
dts_int(3) <= IO3_T_int;--dts_int(3) & dts_int(1);
end generate DATA_OUT_QUAD;
end generate DATA_STARTUP_EN;
DATA_STARTUP_DIS : if (C_USE_STARTUP = 0 or (C_USE_STARTUP = 1 and C_UC_FAMILY = 0))
generate
-----
begin
-----
str_IO0_I <= IO0_I;
IO0_O <= str_IO0_O;
IO0_T <= str_IO0_T;
str_IO1_I <= IO1_I;
IO1_O <= str_IO1_O;
IO1_T <= str_IO1_T;
fcsbo_int <= '0';
fcsbts_int <= '0';
SS_O <= SS_O_int;
SS_T <= SS_T_int;
SS_I_int <= SS_I;
end generate DATA_STARTUP_DIS;
-----------------------------------
-- Combinatorial operations for SPI
-----------------------------------
---- A write to read only register wont have any effect on register.
---- The transaction is completed by generating WrAck only.
not_Tx_FIFO_FULL <= not Tx_FIFO_Full;
Interrupt_WrCE_sig <= "00";
IPIF_Lvl_Interrupts_sig <= '0';
LEGACY_MD_WR_RD_ACK_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
-----
begin
-----
-- A write to read only register wont have any effect on register.
-- The transaction is completed by generating WrAck only.
--------------------------------------------------------
-- IP2Bus_Error is generated under following conditions:
-- 1. If an full transmit register/FIFO is written into.
-- 2. If an empty receive register/FIFO is read from.
-- Due to software driver legacy, the register rule test is not applied to SPI.
--------------------------------------------------------
IP2Bus_Error_1 <= intr_ip2bus_error or
rst_ip2bus_error or
transmit_ip2bus_error or
receive_ip2bus_error;
REG_ERR_ACK_P:process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
IP2Bus_Error <= '0';
else
IP2Bus_Error <= IP2Bus_Error_1;
end if;
end if;
end process REG_ERR_ACK_P;
wr_ce_or_reduce_core_cmb <= Bus2IP_WrCE(SPISR) or -- read only register
Bus2IP_WrCE(SPIDRR) or -- read only register
(Bus2IP_WrCE(SPIDTR) and not_Tx_FIFO_FULL) or -- common to
-- spi_fifo_ifmodule_1 and
-- spi_receive_reg_1
-- (FROM TRANSMITTER) module
Bus2IP_WrCE(SPICR) or
Bus2IP_WrCE(SPISSR) or
Bus2IP_WrCE(SPITFOR)or -- locally generated
Bus2IP_WrCE(SPIRFOR)or -- locally generated
Bus2IP_WrCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_WrCE(17 to 23)); -- holes between reset end and start of SPICR register
--------------------------------------------------
WRITE_ACK_SPIDTR_REG_PROCESS: process(Bus2IP_Clk) is
---------------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
Bus2IP_WrCE_d1 <= '0';
Bus2IP_WrCE_d2 <= '0';
Bus2IP_WrCE_d3 <= '0';
else
Bus2IP_WrCE_d1 <= Bus2IP_WrCE(SPIDTR);
Bus2IP_WrCE_d2 <= Bus2IP_WrCE_d1;
Bus2IP_WrCE_d3 <= Bus2IP_WrCE_d2;
end if; end if;
end process WRITE_ACK_SPIDTR_REG_PROCESS;
Bus2IP_WrCE_pulse_1 <= Bus2IP_WrCE(SPIDTR) and not Bus2IP_WrCE_d1;
Bus2IP_WrCE_pulse_2 <= Bus2IP_WrCE_d1 and not Bus2IP_WrCE_d2;
Bus2IP_WrCE_pulse_3 <= Bus2IP_WrCE_d2 and not Bus2IP_WrCE_d3;
--end generate WR_ACK_OR_REDUCE_FIFO_1_GEN;
-----------------------------------------
-- WRITE_ACK_CORE_REG_PROCESS : The commong write ACK generation logic when FIFO is
-- ------------------------ not included in the design.
--------------------------------------------------
-- _____|-----|__________ wr_ce_or_reduce_fifo_no
-- ________|-----|_______ ip2Bus_WrAck_fifo_no_d1
-- ________|--|__________ ip2Bus_WrAck_fifo_no from common write ack register
-- this ack will be used in register files for
-- reference.
--------------------------------------------------
WRITE_ACK_CORE_REG_PROCESS: process(Bus2IP_Clk) is
---------------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_WrAck_core_reg_d1 <= '0';
ip2Bus_WrAck_core_reg <= '0';
ip2Bus_WrAck_core_reg_1 <= '0';
else
ip2Bus_WrAck_core_reg_d1 <= wr_ce_or_reduce_core_cmb;
ip2Bus_WrAck_core_reg <= wr_ce_or_reduce_core_cmb and
(not ip2Bus_WrAck_core_reg_d1);
ip2Bus_WrAck_core_reg_1 <= ip2Bus_WrAck_core_reg;
end if;
end if;
end process WRITE_ACK_CORE_REG_PROCESS;
-------------------------------------------------
-- internal logic uses this signal
wr_ce_reduce_ack_gen <= ip2Bus_WrAck_core_reg_1;
-------------------------------------------------
-- common WrAck to IPIF
IP2Bus_WrAck_1 <= intr_ip2bus_wrack or -- common
rst_ip2bus_wrack or -- common
ip2Bus_WrAck_intr_reg_hole or -- newly added to target the holes in register space
ip2Bus_WrAck_core_reg;-- or
--Tx_FIFO_wr_ack; -- newly added
REG_WR_ACK_P:process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
IP2Bus_WrAck <= '0';
else
IP2Bus_WrAck <= IP2Bus_WrAck_1;
end if;
end if;
end process REG_WR_ACK_P;
-------------------------------------------------
--end generate LEGACY_MD_WR_ACK_GEN;
-------------------------------------------------
--LEGACY_MD_RD_ACK_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
-----
--begin
-----
rd_ce_or_reduce_core_cmb <= Bus2IP_RdCE(SWRESET) or --common locally generated
Bus2IP_RdCE(SPIDTR) or --common locally generated
Bus2IP_RdCE(SPISR) or --common from status register
Bus2IP_RdCE(SPIDRR) or --common to
--spi_fifo_ifmodule_1
--and spi_receive_reg_1
--(FROM RECEIVER) module
Bus2IP_RdCE(SPICR) or --common spi_cntrl_reg_1
Bus2IP_RdCE(SPISSR) or --common spi_status_reg_1
Bus2IP_RdCE(SPITFOR) or --only for fifo_occu TX reg
Bus2IP_RdCE(SPIRFOR) or --only for fifo_occu RX reg
Bus2IP_RdCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_RdCE(17 to 23)); -- holes between reset end and start of SPICR register; --reg hole
-- READ_ACK_CORE_REG_PROCESS : The commong write ACK generation logic
--------------------------------------------------
-- _____|-----|__________ wr_ce_or_reduce_fifo_no
-- ________|-----|_______ ip2Bus_WrAck_fifo_no_d1
-- ________|--|__________ ip2Bus_WrAck_fifo_no from common write ack register
-- this ack will be used in register files for
-- reference.
--------------------------------------------------
READ_ACK_CORE_REG_PROCESS: process(Bus2IP_Clk) is
-------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_RdAck_core_reg_d1 <= '0';
ip2Bus_RdAck_core_reg <= '0';
ip2Bus_RdAck_core_reg_1 <= '0';
read_ack_delay_1 <= '0';
read_ack_delay_2 <= '0';
read_ack_delay_3 <= '0';
read_ack_delay_4 <= '0';
read_ack_delay_5 <= '0';
read_ack_delay_6 <= '0';
read_ack_delay_7 <= '0';
else
--ip2Bus_RdAck_core_reg_d1 <= rd_ce_or_reduce_core_cmb;
--ip2Bus_RdAck_core_reg <= rd_ce_or_reduce_core_cmb and
-- (not ip2Bus_RdAck_core_reg_d1);
read_ack_delay_1 <= rd_ce_or_reduce_core_cmb;
read_ack_delay_2 <= read_ack_delay_1;
read_ack_delay_3 <= read_ack_delay_2;
read_ack_delay_4 <= read_ack_delay_3;
read_ack_delay_5 <= read_ack_delay_4;
read_ack_delay_6 <= read_ack_delay_5;
read_ack_delay_7 <= read_ack_delay_6;
ip2Bus_RdAck_core_reg <= read_ack_delay_6 and (not read_ack_delay_7);
ip2Bus_RdAck_core_reg_1 <= ip2Bus_RdAck_core_reg;
end if;
end if;
end process READ_ACK_CORE_REG_PROCESS;
-------------------------------------------------
-- internal logic uses this signal
rd_ce_reduce_ack_gen <= ip2Bus_RdAck_core_reg;
-------------------------------------------------
-- common RdAck to IPIF
IP2Bus_RdAck_1 <= intr_ip2bus_rdack or -- common
ip2Bus_RdAck_intr_reg_hole or
ip2Bus_RdAck_core_reg;
REG_RD_ACK_P:process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
IP2Bus_RdAck <= '0';
else
IP2Bus_RdAck <= IP2Bus_RdAck_1;
end if;
end if;
end process REG_RD_ACK_P;
---------------------------------------------------
end generate LEGACY_MD_WR_RD_ACK_GEN;
-------------------------------------------------
ENHANCED_MD_WR_RD_ACK_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
-----
begin
-----
-- A write to read only register wont have any effect on register.
-- The transaction is completed by generating WrAck only.
--------------------------------------------------------
-- IP2Bus_Error is generated under following conditions:
-- 1. If an full transmit register/FIFO is written into.
-- 2. If an empty receive register/FIFO is read from.
-- Due to software driver legacy, the register rule test is not applied to SPI.
--------------------------------------------------------
IP2Bus_Error <= intr_ip2bus_error or
rst_ip2bus_error or
transmit_ip2bus_error or
receive_ip2bus_error;
wr_ce_or_reduce_core_cmb <= Bus2IP_WrCE(SPISR) or -- read only register
Bus2IP_WrCE(SPIDRR) or -- read only register
(Bus2IP_WrCE(SPIDTR) and not_Tx_FIFO_FULL) or -- common to
-- spi_fifo_ifmodule_1 and
-- spi_receive_reg_1
-- (FROM TRANSMITTER) module
Bus2IP_WrCE(SPICR) or
Bus2IP_WrCE(SPISSR) or
Bus2IP_WrCE(SPITFOR)or -- locally generated
Bus2IP_WrCE(SPIRFOR)or -- locally generated
Bus2IP_WrCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_WrCE(17 to 23)); -- holes between reset end and start of SPICR register; -- register hole
--------------------------------------------------
WRITE_ACK_SPIDTR_REG_PROCESS: process(Bus2IP_Clk) is
---------------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
Bus2IP_WrCE_d1 <= '0';
Bus2IP_WrCE_d2 <= '0';
Bus2IP_WrCE_d3 <= '0';
else
Bus2IP_WrCE_d1 <= Bus2IP_WrCE(SPIDTR);
Bus2IP_WrCE_d2 <= Bus2IP_WrCE_d1;
Bus2IP_WrCE_d3 <= Bus2IP_WrCE_d2;
end if; end if;
end process WRITE_ACK_SPIDTR_REG_PROCESS;
Bus2IP_WrCE_pulse_1 <= Bus2IP_WrCE(SPIDTR) and not Bus2IP_WrCE_d1;
Bus2IP_WrCE_pulse_2 <= Bus2IP_WrCE_d1 and not Bus2IP_WrCE_d2;
Bus2IP_WrCE_pulse_3 <= Bus2IP_WrCE_d2 and not Bus2IP_WrCE_d3;
-- WRITE_ACK_CORE_REG_PROCESS : The commong write ACK generation logic when FIFO is
-- ------------------------ not included in the design.
--------------------------------------------------
-- _____|-----|__________ wr_ce_or_reduce_fifo_no
-- ________|-----|_______ ip2Bus_WrAck_fifo_no_d1
-- ________|--|__________ ip2Bus_WrAck_fifo_no from common write ack register
-- this ack will be used in register files for
-- reference.
--------------------------------------------------
WRITE_ACK_CORE_REG_PROCESS: process(Bus2IP_Clk) is
---------------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_WrAck_core_reg_d1 <= '0';
ip2Bus_WrAck_core_reg <= '0';
ip2Bus_WrAck_core_reg_1 <= '0';
else
ip2Bus_WrAck_core_reg_d1 <= wr_ce_or_reduce_core_cmb;
ip2Bus_WrAck_core_reg <= wr_ce_or_reduce_core_cmb and
(not ip2Bus_WrAck_core_reg_d1);
ip2Bus_WrAck_core_reg_1 <= ip2Bus_WrAck_core_reg;
end if;
end if;
end process WRITE_ACK_CORE_REG_PROCESS;
-------------------------------------------------
-- internal logic uses this signal
wr_ce_reduce_ack_gen <= ip2Bus_WrAck_core_reg;--_1;
-------------------------------------------------
-- common WrAck to IPIF
-- in the enhanced mode for FIFO, the IP2bus_Wrack is provided by the enhanced mode statemachine only.
IP2Bus_WrAck <= intr_ip2bus_wrack or -- common
rst_ip2bus_wrack or -- common
ip2Bus_WrAck_intr_reg_hole or -- newly added to target the holes in register space
(ip2Bus_WrAck_core_reg and (not burst_tr));-- or
--(Tx_FIFO_wr_ack and burst_tr); -- newly added
-------------------------------------------------
--ENHANCED_MD_RD_ACK_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
-----
--begin
-----
FIFO_NO_RD_CE_GEN: if C_FIFO_EXIST = 0 generate
begin
rd_ce_or_reduce_core_cmb <= Bus2IP_RdCE(SWRESET) or --common locally generated
Bus2IP_RdCE(SPIDTR) or --common locally generated
Bus2IP_RdCE(SPISR) or --common from status register
Bus2IP_RdCE(SPIDRR) or --common to
--spi_fifo_ifmodule_1
--and spi_receive_reg_1
--(FROM RECEIVER) module
Bus2IP_RdCE(SPICR) or --common spi_cntrl_reg_1
Bus2IP_RdCE(SPISSR) or --common spi_status_reg_1
Bus2IP_RdCE(SPITFOR) or --only for fifo_occu TX reg
Bus2IP_RdCE(SPIRFOR) or --only for fifo_occu RX reg
Bus2IP_RdCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_RdCE(17 to 23)); -- holes between reset end and start of SPICR register; --reg hole
end generate FIFO_NO_RD_CE_GEN;
FIFO_YES_RD_CE_GEN: if C_FIFO_EXIST = 1 generate
begin
rd_ce_or_reduce_core_cmb <= Bus2IP_RdCE(SWRESET) or --common locally generated
Bus2IP_RdCE(SPIDTR) or --common locally generated
Bus2IP_RdCE(SPISR) or --common from status register
--Bus2IP_RdCE(SPIDRR) or --common to
--spi_fifo_ifmodule_1
--and spi_receive_reg_1
--(FROM RECEIVER) module
Bus2IP_RdCE(SPICR) or --common spi_cntrl_reg_1
Bus2IP_RdCE(SPISSR) or --common spi_status_reg_1
Bus2IP_RdCE(SPITFOR) or --only for fifo_occu TX reg
Bus2IP_RdCE(SPIRFOR) or --only for fifo_occu RX reg
Bus2IP_RdCE(REG_HOLE) or -- register hole
or_reduce(Bus2IP_RdCE(17 to 23)); -- holes between reset end and start of SPICR register; --reg hole
end generate FIFO_YES_RD_CE_GEN;
-- READ_ACK_CORE_REG_PROCESS : The commong write ACK generation logic
--------------------------------------------------
-- _____|-----|__________ wr_ce_or_reduce_fifo_no
-- ________|-----|_______ ip2Bus_WrAck_fifo_no_d1
-- ________|--|__________ ip2Bus_WrAck_fifo_no from common write ack register
-- this ack will be used in register files for
-- reference.
--------------------------------------------------
READ_ACK_CORE_REG_PROCESS: process(Bus2IP_Clk) is
-------------------
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_RdAck_core_reg_d1 <= '0';
ip2Bus_RdAck_core_reg <= '0';
ip2Bus_RdAck_core_reg_1 <= '0';
read_ack_delay_1 <= '0';
read_ack_delay_2 <= '0';
read_ack_delay_3 <= '0';
read_ack_delay_4 <= '0';
read_ack_delay_5 <= '0';
read_ack_delay_6 <= '0';
read_ack_delay_7 <= '0';
else
--ip2Bus_RdAck_core_reg_d1 <= rd_ce_or_reduce_core_cmb;
--ip2Bus_RdAck_core_reg <= rd_ce_or_reduce_core_cmb and
-- (not ip2Bus_RdAck_core_reg_d1);
--ip2Bus_RdAck_core_reg_1 <= ip2Bus_RdAck_core_reg;
read_ack_delay_1 <= rd_ce_or_reduce_core_cmb;
read_ack_delay_2 <= read_ack_delay_1;
read_ack_delay_3 <= read_ack_delay_2;
read_ack_delay_4 <= read_ack_delay_3;
read_ack_delay_5 <= read_ack_delay_4;
read_ack_delay_6 <= read_ack_delay_5;
read_ack_delay_7 <= read_ack_delay_6;
ip2Bus_RdAck_core_reg <= read_ack_delay_6 and (not read_ack_delay_7);
ip2Bus_RdAck_core_reg_1 <= ip2Bus_RdAck_core_reg;
end if;
end if;
end process READ_ACK_CORE_REG_PROCESS;
-------------------------------------------------
-- internal logic uses this signal
rd_ce_reduce_ack_gen <= ip2Bus_RdAck_core_reg; --_1;
-------------------------------------------------
-- common RdAck to IPIF
IP2Bus_RdAck <= intr_ip2bus_rdack or -- common
ip2Bus_RdAck_intr_reg_hole or
ip2Bus_RdAck_core_reg or
(Rx_FIFO_rd_ack and rready);
-----------------------------------------------------
end generate ENHANCED_MD_WR_RD_ACK_GEN;
-------------------------------------------------
--=============================================================================
TX_FIFO_OCC_DATA_FIFO_16: if C_FIFO_DEPTH = 16 generate
-------------------------
begin
-----
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(0) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(0)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(1) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(1)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(2) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(2)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(3) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(3)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty); --(FIFO_Empty_tx);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(0) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(0)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(1) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(1)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(2) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(2)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(3) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(3)
and not (Rx_FIFO_Empty); --(FIFO_Empty_rx);
end generate TX_FIFO_OCC_DATA_FIFO_16;
--------------------------------------
TX_FIFO_OCC_DATA_FIFO_256: if C_FIFO_DEPTH = 256 generate
-------------------------
begin
-----
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(0) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(0)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(1) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(1)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(2) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(2)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(3) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(3)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(4) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(4)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(5) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(5)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(6) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(6)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1(7) <= IP2Bus_Tx_FIFO_OCC_Reg_Data_int(7)
and not (Tx_FIFO_Empty_SPISR_to_axi_clk); -- (Tx_FIFO_Empty);-- (FIFO_Empty_tx);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(0) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(0)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(1) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(1)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(2) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(2)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(3) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(3)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(4) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(4)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(5) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(5)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(6) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(6)
and not (Rx_FIFO_Empty);
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1(7) <= IP2Bus_Rx_FIFO_OCC_Reg_Data_int(7)
and not (Rx_FIFO_Empty); --(FIFO_Empty_rx);
end generate TX_FIFO_OCC_DATA_FIFO_256;
--*****************************************************************************
ip2Bus_Data_occupancy_int(0 to (C_S_AXI_DATA_WIDTH-C_OCCUPANCY_NUM_BITS-1))
<= (others => '0');
ip2Bus_Data_occupancy_int((C_S_AXI_DATA_WIDTH-C_OCCUPANCY_NUM_BITS)
to (C_S_AXI_DATA_WIDTH-1))
<= IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1 or
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1;
-------------------------------------------------------------------------------
-- SPECIAL_CASE_WHEN_SS_NOT_EQL_32 : The Special case is executed whenever
-- C_NUM_SS_BITS is less than 32
-------------------------------------------------------------------------------
SPECIAL_CASE_WHEN_SS_NOT_EQL_32: if(C_NUM_SS_BITS /= 32) generate
-----
begin
-----
ip2Bus_Data_SS_int(0 to (C_S_AXI_DATA_WIDTH-C_NUM_SS_BITS-1))
<= (others => '0');
end generate SPECIAL_CASE_WHEN_SS_NOT_EQL_32;
---------------------------------------------
ip2Bus_Data_SS_int((C_S_AXI_DATA_WIDTH-C_NUM_SS_BITS) to
(C_S_AXI_DATA_WIDTH-1)) <= IP2Bus_SPISSR_Data_int;
-------------------------------------------------------------------------------
ip2Bus_Data_Reg_int(0 to C_S_AXI_DATA_WIDTH-C_SPISR_REG_WIDTH-1) <= (others => '0');
ip2Bus_Data_Reg_int(C_S_AXI_DATA_WIDTH-C_SPISR_REG_WIDTH to C_S_AXI_DATA_WIDTH-1)
<= IP2Bus_SPISR_Data_int or -- SPISR - 11 bit
('0' & IP2Bus_SPICR_Data_int); -- SPICR - 10 bit
-------------------------------------------------------------------------------
-----------------------
Receive_Reg_width_is_32: if(C_NUM_TRANSFER_BITS = 32) generate
-----------------------
begin
-----
IP2Bus_Data_received_int <= IP2Bus_Receive_Reg_Data_int;
end generate Receive_Reg_width_is_32;
-----------------------------------------
---------------------------
Receive_Reg_width_is_not_32: if(C_NUM_TRANSFER_BITS /= 32) generate
---------------------------
begin
-----
IP2Bus_Data_received_int(0 to C_S_AXI_DATA_WIDTH-C_NUM_TRANSFER_BITS-1)
<= (others => '0');
IP2Bus_Data_received_int((C_S_AXI_DATA_WIDTH-C_NUM_TRANSFER_BITS) to
(C_S_AXI_DATA_WIDTH-1))
<= IP2Bus_Receive_Reg_Data_int;
end generate Receive_Reg_width_is_not_32;
-----------------------------------------
-------------------------------------------------------------------------------
LEGACY_MD_IP2BUS_DATA_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
-----
begin
-----
ip2Bus_Data_1 <= ip2Bus_Data_occupancy_int or -- occupancy reg data
ip2Bus_Data_SS_int or -- Slave select reg data
ip2Bus_Data_Reg_int or -- SPI CR & SR reg data
IP2Bus_Data_received_int or -- SPI received data
intr_ip2bus_data ;
REG_IP2BUS_DATA_P:process(Bus2IP_Clk)is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_Data <= (others => '0');
else
ip2Bus_Data <= ip2Bus_Data_1;
end if;
end if;
end process REG_IP2BUS_DATA_P;
end generate LEGACY_MD_IP2BUS_DATA_GEN;
-------------------------------------------------------------------------------
ENHANCED_MD_IP2BUS_DATA_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
-----
begin
-----
ip2Bus_Data <= ip2Bus_Data_occupancy_int or -- occupancy reg data
ip2Bus_Data_SS_int or -- Slave select reg data
ip2Bus_Data_Reg_int or -- SPI CR & SR reg data
IP2Bus_Data_received_int or -- SPI received data
intr_ip2bus_data ;
end generate ENHANCED_MD_IP2BUS_DATA_GEN;
-------------------------------------------------------------------------------
RESET_SYNC_AXI_SPI_CLK_INST:entity axi_quad_spi_v3_2_8.reset_sync_module
port map(
EXT_SPI_CLK => EXT_SPI_CLK ,-- in std_logic;
--Bus2IP_Clk => Bus2IP_Clk ,-- in std_logic;
Soft_Reset_frm_axi => reset2ip_reset_int,-- in std_logic;
Rst_to_spi => Rst_to_spi_int -- out std_logic;
);
--------------------------------------
-- NO_FIFO_EXISTS : Signals initialisation and module
-- instantiation when C_FIFO_EXIST = 0
--------------------------------------
NO_FIFO_EXISTS: if(C_FIFO_EXIST = 0) generate
----------------------------------
signal spisel_pulse_frm_spi_clk : std_logic;
signal spisel_pulse_to_axi_clk : std_logic;
signal spiXfer_done_frm_spi_clk : std_logic;
signal spiXfer_done_to_axi_clk : std_logic;
signal modf_strobe_frm_spi_clk : std_logic;
-- signal modf_strobe_to_axi_clk : std_logic;
signal slave_MODF_strobe_frm_spi_clk : std_logic;
signal slave_MODF_strobe_to_axi_clk : std_logic;
signal receive_data_frm_spi_clk : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal receive_data_to_axi_clk : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_frm_axi_clk: std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_to_spi_clk : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_fifo_0 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal drr_Overrun_int_frm_spi_clk: std_logic;
signal drr_Overrun_int_to_axi_clk : std_logic;
-----
begin
-----
Rx_FIFO_rd_ack <= '0';
Tx_FIFO_Full <= '0';
--------------------------------------------------------------------------
-- I_RECEIVE_REG : INSTANTIATE RECEIVE REGISTER
--------------------------------------------------------------------------
QSPI_RX_TX_REG: entity axi_quad_spi_v3_2_8.qspi_receive_transmit_reg
generic map
(
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS
)
port map
(
Bus2IP_Clk => Bus2IP_Clk, -- in
Soft_Reset_op => reset2ip_reset_int, -- in
--SPI Receiver signals -- From AXI clock
Bus2IP_Receive_Reg_RdCE => Bus2IP_RdCE(SPIDRR), -- in
Receive_ip2bus_error => receive_ip2bus_error, -- out
IP2Bus_Receive_Reg_Data => IP2Bus_Receive_Reg_Data_int, -- out
--SPI module ports From SPI clock
SPIXfer_done => spiXfer_done_to_axi_clk,--spiXfer_done_int,-- in
SPI_Received_Data => receive_data_to_axi_clk,--receive_Data_int,-- in vec
-- receive & transmit reg signals
-- DRR_Overrun => drr_Overrun_int,-- drr_Overrun_int,-- out
SR_7_Rx_Empty => Rx_FIFO_Empty_i, -- out
-- From AXI clock
Bus2IP_Transmit_Reg_Data=> Bus2IP_Data, -- in vec
Bus2IP_Transmit_Reg_WrCE=> Bus2IP_WrCE(SPIDTR), -- in
Wr_ce_reduce_ack_gen => wr_ce_reduce_ack_gen, -- in
Rd_ce_reduce_ack_gen => rd_ce_reduce_ack_gen, -- in
--SPI Transmitter signals from AXI clock
Transmit_ip2bus_error => transmit_ip2bus_error, -- out
--SPI module ports
DTR_underrun => dtr_underrun_to_axi_clk,--dtr_underrun_int,-- in
SR_5_Tx_Empty => sr_5_Tx_Empty_int, -- out
tx_empty_signal_handshake_req => tx_empty_signal_handshake_req, -- out
tx_empty_signal_handshake_gnt => tx_empty_signal_handshake_gnt, -- in
DTR_Underrun_strobe => dtr_Underrun_strobe_int, -- out
Transmit_Reg_Data_Out => transmit_Data_fifo_0--transmit_Data_int -- out vec
);
spisel_d1_reg_frm_spi_clk <= spisel_d1_reg;
spisel_pulse_frm_spi_clk <= spisel_pulse_o_int;-- from SPI module
spiXfer_done_frm_spi_clk <= spiXfer_done_int ;-- from SPI module
modf_strobe_frm_spi_clk <= modf_strobe_int ;-- from SPI module
slave_MODF_strobe_frm_spi_clk <= slave_MODF_strobe_int;-- from SPI module
receive_data_frm_spi_clk <= Data_To_Rx_FIFO ; -- from SPI module
dtr_underrun_frm_spi_clk <= dtr_underrun_int; -- from SPI module
transmit_Data_frm_axi_clk <= transmit_Data_fifo_0; -- From AXI clock
Tx_FIFO_Empty_frm_axi_clk <= sr_5_Tx_Empty_int;
Tx_FIFO_Empty_SPISR_frm_spi_clk <= sr_5_Tx_Empty_int;
--Rx_FIFO_Empty_int <= Rx_FIFO_Empty;
Rx_FIFO_Empty_int <= Rx_FIFO_Empty_i;
drr_Overrun_int_frm_spi_clk <= drr_Overrun_int;
SR_3_modf_frm_axi_clk <= SR_3_modf_int;
CROSS_CLK_FIFO_0_INST:entity axi_quad_spi_v3_2_8.cross_clk_sync_fifo_0
generic map(
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS,
Async_Clk => Async_Clk ,
--C_AXI_SPI_CLK_EQ_DIFF => C_AXI_SPI_CLK_EQ_DIFF,
C_NUM_SS_BITS => C_NUM_SS_BITS
)
port map(
EXT_SPI_CLK => EXT_SPI_CLK,
Bus2IP_Clk => Bus2IP_Clk ,
Soft_Reset_op => reset2ip_reset_int,
Rst_from_axi_cdc_to_spi => Rst_to_spi_int, -- out std_logic;
----------------------------------------------------------
tx_empty_signal_handshake_req => tx_empty_signal_handshake_req,
tx_empty_signal_handshake_gnt => tx_empty_signal_handshake_gnt,
Tx_FIFO_Empty_cdc_from_axi => Tx_FIFO_Empty_frm_axi_clk,
Tx_FIFO_Empty_cdc_to_spi => Tx_FIFO_Empty,
----------------------------------------------------------
Tx_FIFO_Empty_SPISR_cdc_from_spi => Tx_FIFO_Empty_SPISR_frm_spi_clk,
Tx_FIFO_Empty_SPISR_cdc_to_axi => Tx_FIFO_Empty_SPISR_to_axi_clk,
----------------------------------------------------------
spisel_d1_reg_cdc_from_spi => spisel_d1_reg_frm_spi_clk , -- in
spisel_d1_reg_cdc_to_axi => spisel_d1_reg_to_axi_clk , -- out
----------------------------------------------------------
spisel_pulse_cdc_from_spi => spisel_pulse_frm_spi_clk , -- in
spisel_pulse_cdc_to_axi => spisel_pulse_to_axi_clk , -- out
----------------------------------------------------------
spiXfer_done_cdc_from_spi => spiXfer_done_frm_spi_clk , -- in
spiXfer_done_cdc_to_axi => spiXfer_done_to_axi_clk , -- out
----------------------------------------------------------
modf_strobe_cdc_from_spi => modf_strobe_frm_spi_clk, -- in
modf_strobe_cdc_to_axi => modf_strobe_to_axi_clk , -- out
----------------------------------------------------------
Slave_MODF_strobe_cdc_from_spi => slave_MODF_strobe_frm_spi_clk,-- in
Slave_MODF_strobe_cdc_to_axi => slave_MODF_strobe_to_axi_clk ,-- out
----------------------------------------------------------
receive_Data_cdc_from_spi => receive_Data_frm_spi_clk, -- in
receive_Data_cdc_to_axi => receive_data_to_axi_clk, -- out
----------------------------------------------------------
drr_Overrun_int_cdc_from_spi => drr_Overrun_int_frm_spi_clk, -- in
drr_Overrun_int_cdc_to_axi => drr_Overrun_int_to_axi_clk, -- out
----------------------------------------------------------
dtr_underrun_cdc_from_spi => dtr_underrun_frm_spi_clk, -- in
dtr_underrun_cdc_to_axi => dtr_underrun_to_axi_clk, -- out
----------------------------------------------------------
transmit_Data_cdc_from_axi => transmit_Data_frm_axi_clk, -- in
transmit_Data_cdc_to_spi => transmit_Data_to_spi_clk, -- out
----------------------------
SPICR_0_LOOP_cdc_from_axi => SPICR_0_LOOP_frm_axi_clk,-- in std_logic;
SPICR_0_LOOP_cdc_to_spi => SPICR_0_LOOP_to_spi_clk ,-- out
----------------------------
SPICR_1_SPE_cdc_from_axi => SPICR_1_SPE_frm_axi_clk ,-- in std_logic;
SPICR_1_SPE_cdc_to_spi => SPICR_1_SPE_to_spi_clk ,-- out
----------------------------
SPICR_2_MST_N_SLV_cdc_from_axi => SPICR_2_MST_N_SLV_frm_axi_clk,-- in std_logic;
SPICR_2_MST_N_SLV_cdc_to_spi => SPICR_2_MST_N_SLV_to_spi_clk, -- out
----------------------------
SPICR_3_CPOL_cdc_from_axi => SPICR_3_CPOL_frm_axi_clk,-- in std_logic;
SPICR_3_CPOL_cdc_to_spi => SPICR_3_CPOL_to_spi_clk ,-- out
----------------------------
SPICR_4_CPHA_cdc_from_axi => SPICR_4_CPHA_frm_axi_clk,-- in std_logic;
SPICR_4_CPHA_cdc_to_spi => SPICR_4_CPHA_to_spi_clk ,-- out
----------------------------
SPICR_5_TXFIFO_cdc_from_axi => SPICR_5_TXFIFO_frm_axi_clk,-- in std_logic;
SPICR_5_TXFIFO_cdc_to_spi => SPICR_5_TXFIFO_to_spi_clk, -- out
----------------------------
SPICR_6_RXFIFO_RST_cdc_from_axi=> SPICR_6_RXFIFO_RST_frm_axi_clk,-- in std_logic;
SPICR_6_RXFIFO_RST_cdc_to_spi => SPICR_6_RXFIFO_RST_to_spi_clk ,-- out
----------------------------
SPICR_7_SS_cdc_from_axi => SPICR_7_SS_frm_axi_clk ,-- in std_logic;
SPICR_7_SS_cdc_to_spi => SPICR_7_SS_to_spi_clk ,-- out
----------------------------
SPICR_8_TR_INHIBIT_cdc_from_axi=> SPICR_8_TR_INHIBIT_frm_axi_clk,-- in std_logic;
SPICR_8_TR_INHIBIT_cdc_to_spi => SPICR_8_TR_INHIBIT_to_spi_clk,-- out
----------------------------
SPICR_9_LSB_cdc_from_axi => SPICR_9_LSB_frm_axi_clk,-- in std_logic;
SPICR_9_LSB_cdc_to_spi => SPICR_9_LSB_to_spi_clk,-- out
----------------------------
SPICR_bits_7_8_cdc_from_axi => SPICR_bits_7_8_frm_axi_clk,-- in std_logic_vector
SPICR_bits_7_8_cdc_to_spi => SPICR_bits_7_8_to_spi_clk,-- out
----------------------------
SR_3_modf_cdc_from_axi => SR_3_modf_frm_axi_clk, -- in
SR_3_modf_cdc_to_spi => SR_3_modf_to_spi_clk , -- out
----------------------------
SPISSR_cdc_from_axi => SPISSR_frm_axi_clk, -- in
SPISSR_cdc_to_spi => register_Data_slvsel_int -- out
----------------------------
);
Data_From_TxFIFO <= transmit_Data_to_spi_clk;
rc_FIFO_Full_strobe_int <= '0';
rc_FIFO_occ_Reversed_int <= (others => '0');
rc_FIFO_Data_Out_int <= (others => '0');
data_Exists_RcFIFO_int <= '0';
tx_FIFO_Empty_strobe_int <= '0';
tx_FIFO_occ_Reversed_int <= (others => '0');
data_Exists_TxFIFO_int <= '0';
data_From_TxFIFO_int <= (others => '0');
tx_FIFO_less_half_int <= '0';
reset_TxFIFO_ptr_int <= '0';
reset_RcFIFO_ptr_int <= '0';
IP2Bus_Rx_FIFO_OCC_Reg_Data_int_1 <= (others => '0');
IP2Bus_Tx_FIFO_OCC_Reg_Data_int_1 <= (others => '0');
Tx_FIFO_Full_int <= not(sr_5_Tx_Empty_int); -- Tx_FIFO_Empty_to_axi_clk);
Rx_FIFO_Full_int <= not(Rx_FIFO_Empty_i);
Rx_FIFO_Full_Fifo <= not(Rx_FIFO_Empty_i);
Rx_FIFO_Full_Fifo_d1_synced <= not(Rx_FIFO_Empty_i);
--------------------------------------------------------------------------
bus2IP_Data_for_interrupt_core(0 to 14) <= Bus2IP_Data(0 to 14);
bus2IP_Data_for_interrupt_core(15 to 22) <= (others => '0');
-- below code manipulates the bus2ip_data going towards interrupt control
-- unit. In FIFO=0, case bit 23 and 25 of IPIER are not applicable.
-- Bu2IP Data to Interrupt Registers - IPISR and IPIER
-- Bus2IP_Data - 0 31
-- IPISR/IPIER - 0 22 23 31
-- <---NA---> <-used->
-- 23 24 25 26 27 28 29 30 31
-- DRR_Not Slave Tx_FIFO DRR_ DRR_ DTR_ DTR Slave MODF
-- _Empty Select_mode Half_Empty Over_Run Full Underrun Empty MODF
-- NA-fifo-0 NA -fifo-0
bus2IP_Data_for_interrupt_core(23) <= '0'; -- DRR_Not_Empty bit in IPIER/IPISR
bus2IP_Data_for_interrupt_core(24) <= Bus2IP_Data(24);
bus2IP_Data_for_interrupt_core(25) <= '0'; -- Tx FIFO Half Empty
bus2IP_Data_for_interrupt_core(26 to (C_S_AXI_DATA_WIDTH-1)) <=
Bus2IP_Data(26 to (C_S_AXI_DATA_WIDTH-1));
--------------------------------------------------------------------------
-- Interrupt Status Register(IPISR) Mapping
ip2Bus_IntrEvent_int(13) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(12) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(11) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(10) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(9) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(8) <= '0'; -- doesnt exist in the FIFO = 0 case
ip2Bus_IntrEvent_int(7) <= spisel_pulse_to_axi_clk; -- spisel_pulse_o_int;
ip2Bus_IntrEvent_int(6) <= '0'; --
ip2Bus_IntrEvent_int(5) <= drr_Overrun_int_to_axi_clk; -- drr_Overrun_int_to_axi_clk;
ip2Bus_IntrEvent_int(4) <= spiXfer_done_to_axi_clk; -- spiXfer_done_int;
ip2Bus_IntrEvent_int(3) <= dtr_Underrun_strobe_int;
ip2Bus_IntrEvent_int(2) <= spiXfer_done_to_axi_clk; -- spiXfer_done_int;
ip2Bus_IntrEvent_int(1) <= slave_MODF_strobe_to_axi_clk; -- slave_MODF_strobe_int;
ip2Bus_IntrEvent_int(0) <= modf_strobe_to_axi_clk; -- modf_strobe_int;
end generate NO_FIFO_EXISTS;
-------------------------------------------------------------------------------
-- FIFO_EXISTS : Signals initialisation and module
-- instantiation when C_FIFO_EXIST = 1
-------------------------------------------------------------------------------
FIFO_EXISTS: if(C_FIFO_EXIST = 1) generate
------------------------------
constant C_RD_COUNT_WIDTH_INT : integer := clog2(C_FIFO_DEPTH);
constant C_WR_COUNT_WIDTH_INT : integer := clog2(C_FIFO_DEPTH);
constant RX_FIFO_CNTR_WIDTH: integer := clog2(C_FIFO_DEPTH);
constant TX_FIFO_CNTR_WIDTH: integer := clog2(C_FIFO_DEPTH);
constant ZERO_RX_FIFO_CNT : std_logic_vector(RX_FIFO_CNTR_WIDTH-1 downto 0) := (others => '0');
constant ZERO_TX_FIFO_CNT : std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0) := (others => '0');
signal rx_fifo_count: std_logic_vector(RX_FIFO_CNTR_WIDTH-1 downto 0);
signal tx_fifo_count: std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0);
signal tx_fifo_count_d1: std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0);
signal tx_fifo_count_d2: std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0);
signal Tx_FIFO_Empty_1 : std_logic;
signal Tx_FIFO_Empty_intr : std_logic;
signal IP2Bus_RdAck_receive_enable : std_logic;
signal IP2Bus_WrAck_transmit_enable : std_logic;
constant ALL_0 : std_logic_vector(0 to TX_FIFO_CNTR_WIDTH-1)
:= (others => '1');
signal data_Exists_RcFIFO_int_d1: std_logic;
signal data_Exists_RcFIFO_pulse : std_logic;
--signal FIFO_Empty_rx : std_logic;
--signal SPISR_0_CMD_Error_frm_spi_clk : std_logic;
--signal SPISR_0_CMD_Error_to_axi_clk : std_logic;
--signal spisel_d1_reg_frm_spi_clk : std_logic;
--signal spisel_d1_reg_to_axi_clk : std_logic;
signal tx_occ_msb_111 : std_logic:= '0';
signal tx_occ_msb_11 : std_logic_vector(TX_FIFO_CNTR_WIDTH-1 downto 0);
signal spisel_pulse_frm_spi_clk : std_logic;
signal spisel_pulse_to_axi_clk : std_logic;
signal slave_MODF_strobe_frm_spi_clk : std_logic;
signal slave_MODF_strobe_to_axi_clk : std_logic;
signal Rx_FIFO_Empty_frm_axi_clk : std_logic;
signal Rx_FIFO_Empty_to_spi_clk : std_logic;
signal Tx_FIFO_Full_frm_axi_clk : std_logic;
signal Tx_FIFO_Full_to_spi_clk : std_logic;
signal spiXfer_done_frm_spi_clk : std_logic;
signal spiXfer_done_to_axi_clk : std_logic;
signal SR_3_modf_frm_axi_clk : std_logic;
signal spiXfer_done_to_axi_1 : std_logic;
signal spiXfer_done_to_axi_d1 : std_logic;
signal updown_cnt_en : std_logic;
signal drr_Overrun_int_to_axi_clk : std_logic;
signal drr_Overrun_int_frm_spi_clk: std_logic;
-----
begin
-----
SPISR_0_CMD_Error_frm_spi_clk <= SPISR_0_CMD_Error_int;
spisel_d1_reg_frm_spi_clk <= spisel_d1_reg;
spisel_pulse_frm_spi_clk <= spisel_pulse_o_int;-- from SPI module
slave_MODF_strobe_frm_spi_clk <= slave_MODF_strobe_int; -- from SPI module
modf_strobe_frm_spi_clk <= modf_strobe_int; -- spi module
--Rx_FIFO_Full_frm_axi_clk <= Rx_FIFO_Full; -- from Async Receive FIFO
----RX_FIFO_FULL Logic signals
Rx_FIFO_Full_frm_axi_clk <= Rx_FIFO_Full_Fifo; -- from Async Receive FIFO
Tx_FIFO_Empty_frm_spi_clk <= Tx_FIFO_Empty_intr; -- Tx_FIFO_Empty; -- from Async Transmit FIFO
spiXfer_done_frm_spi_clk <= spiXfer_done_int; -- from SPI module
dtr_underrun_frm_spi_clk <= dtr_underrun_int; -- from SPI module
Tx_FIFO_Empty_SPISR_frm_spi_clk <= Tx_FIFO_Empty;-- from TX FIFO for SPI Status register
drr_Overrun_int_frm_spi_clk <= drr_Overrun_int;
-- SPICR_6_RXFIFO_RST_frm_axi_clk<= SPICR_6_RXFIFO_RST_frm_axi_clk; -- from SPICR
reset_RcFIFO_ptr_frm_axi_clk <= reset_RcFIFO_ptr_int; -- from AXI clock
Rx_FIFO_Empty_frm_axi_clk <= Rx_FIFO_Empty; -- from Async Receive FIFO AXI side
Tx_FIFO_Full_frm_axi_clk <= Tx_FIFO_Full; -- from Async Transmit FIFO AXI side
SR_3_modf_frm_axi_clk <= SR_3_modf_int;
--CLK_CROSS_I:
CLK_CROSS_I:entity axi_quad_spi_v3_2_8.cross_clk_sync_fifo_1
generic map(
C_FAMILY => C_FAMILY ,
C_FIFO_DEPTH => C_FIFO_DEPTH ,
Async_Clk => Async_Clk ,
C_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS,
C_NUM_SS_BITS => C_NUM_SS_BITS
)
port map(
EXT_SPI_CLK => EXT_SPI_CLK , -- in std_logic;
Bus2IP_Clk => Bus2IP_Clk , -- in std_logic;
Soft_Reset_op => reset2ip_reset_int ,
--Soft_Reset_op => Soft_Reset_op , -- in std_logic;
Rst_cdc_to_spi => Rst_to_spi_int , -- out std_logic;
----------------------------
SPISR_0_CMD_Error_cdc_from_spi => SPISR_0_CMD_Error_frm_spi_clk ,
SPISR_0_CMD_Error_cdc_to_axi => SPISR_0_CMD_Error_to_axi_clk ,
----------------------------------------------------------
spisel_d1_reg_cdc_from_spi => spisel_d1_reg_frm_spi_clk , -- in
spisel_d1_reg_cdc_to_axi => spisel_d1_reg_to_axi_clk , -- out
----------------------------------------------------------
spisel_pulse_cdc_from_spi => spisel_pulse_frm_spi_clk , -- in
spisel_pulse_cdc_to_axi => spisel_pulse_to_axi_clk , -- out
----------------------------
Mst_N_Slv_mode_cdc_from_spi => Mst_N_Slv_mode_frm_spi_clk , -- in
Mst_N_Slv_mode_cdc_to_axi => Mst_N_Slv_mode_to_axi_clk , -- out
----------------------------
slave_MODF_strobe_cdc_from_spi => slave_MODF_strobe_frm_spi_clk, -- in
slave_MODF_strobe_cdc_to_axi => slave_MODF_strobe_to_axi_clk , -- out
----------------------------
modf_strobe_cdc_from_spi => modf_strobe_frm_spi_clk , -- in
modf_strobe_cdc_to_axi => modf_strobe_to_axi_clk , -- out
----------------------------
SPICR_6_RXFIFO_RST_cdc_from_axi=> SPICR_6_RXFIFO_RST_frm_axi_clk, -- in
SPICR_6_RXFIFO_RST_cdc_to_spi => SPICR_6_RXFIFO_RST_to_spi_clk , -- out
----------------------------
Rx_FIFO_Full_cdc_from_axi => Rx_FIFO_Full_frm_axi_clk, -- in
Rx_FIFO_Full_cdc_to_spi => Rx_FIFO_Full_to_spi_clk , -- out
----------------------------
reset_RcFIFO_ptr_cdc_from_axi => reset_RcFIFO_ptr_frm_axi_clk, -- in
reset_RcFIFO_ptr_cdc_to_spi => reset_RcFIFO_ptr_to_spi_clk , -- out
----------------------------
Rx_FIFO_Empty_cdc_from_axi => Rx_FIFO_Empty_frm_axi_clk , -- in
Rx_FIFO_Empty_cdc_to_spi => Rx_FIFO_Empty_to_spi_clk , -- out
----------------------------
Tx_FIFO_Empty_cdc_from_spi => Tx_FIFO_Empty_frm_spi_clk, -- in
Tx_FIFO_Empty_cdc_to_axi => Tx_FIFO_Empty_to_Axi_clk, -- out
----------------------------
Tx_FIFO_Empty_SPISR_cdc_from_spi => Tx_FIFO_Empty_SPISR_frm_spi_clk,
Tx_FIFO_Empty_SPISR_cdc_to_axi => Tx_FIFO_Empty_SPISR_to_axi_clk,
Tx_FIFO_Full_cdc_from_axi => Tx_FIFO_Full_frm_axi_clk,-- in
Tx_FIFO_Full_cdc_to_spi => Tx_FIFO_Full_to_spi_clk ,-- out
----------------------------
spiXfer_done_cdc_from_spi => spiXfer_done_frm_spi_clk, -- in
spiXfer_done_cdc_to_axi => spiXfer_done_to_axi_clk, -- out
----------------------------
dtr_underrun_cdc_from_spi => dtr_underrun_frm_spi_clk, -- in
dtr_underrun_cdc_to_axi => dtr_underrun_to_axi_clk , -- out
----------------------------
SPICR_0_LOOP_cdc_from_axi => SPICR_0_LOOP_frm_axi_clk,-- in std_logic;
SPICR_0_LOOP_cdc_to_spi => SPICR_0_LOOP_to_spi_clk ,-- out
----------------------------
SPICR_1_SPE_cdc_from_axi => SPICR_1_SPE_frm_axi_clk ,-- in std_logic;
SPICR_1_SPE_cdc_to_spi => SPICR_1_SPE_to_spi_clk ,-- out
----------------------------
SPICR_2_MST_N_SLV_cdc_from_axi => SPICR_2_MST_N_SLV_frm_axi_clk,-- in std_logic;
SPICR_2_MST_N_SLV_cdc_to_spi => SPICR_2_MST_N_SLV_to_spi_clk, -- out
----------------------------
SPICR_3_CPOL_cdc_from_axi => SPICR_3_CPOL_frm_axi_clk,-- in std_logic;
SPICR_3_CPOL_cdc_to_spi => SPICR_3_CPOL_to_spi_clk ,-- out
----------------------------
SPICR_4_CPHA_cdc_from_axi => SPICR_4_CPHA_frm_axi_clk,-- in std_logic;
SPICR_4_CPHA_cdc_to_spi => SPICR_4_CPHA_to_spi_clk ,-- out
----------------------------
SPICR_5_TXFIFO_cdc_from_axi => SPICR_5_TXFIFO_RST_frm_axi_clk,-- in std_logic;
SPICR_5_TXFIFO_cdc_to_spi => SPICR_5_TXFIFO_to_spi_clk, -- out
----------------------------
SPICR_7_SS_cdc_from_axi => SPICR_7_SS_frm_axi_clk ,-- in std_logic;
SPICR_7_SS_cdc_to_spi => SPICR_7_SS_to_spi_clk ,-- out
----------------------------
SPICR_8_TR_INHIBIT_cdc_from_axi=> SPICR_8_TR_INHIBIT_frm_axi_clk,-- in std_logic;
SPICR_8_TR_INHIBIT_cdc_to_spi => SPICR_8_TR_INHIBIT_to_spi_clk,-- out
----------------------------
SPICR_9_LSB_cdc_from_axi => SPICR_9_LSB_frm_axi_clk,-- in std_logic;
SPICR_9_LSB_cdc_to_spi => SPICR_9_LSB_to_spi_clk,-- out
----------------------------
SPICR_bits_7_8_cdc_from_axi => SPICR_bits_7_8_frm_axi_clk,-- in std_logic_vector
SPICR_bits_7_8_cdc_to_spi => SPICR_bits_7_8_to_spi_clk,-- out
----------------------------
SR_3_modf_cdc_from_axi => SR_3_modf_frm_axi_clk, -- in
SR_3_modf_cdc_to_spi => SR_3_modf_to_spi_clk , -- out
----------------------------
SPISSR_cdc_from_axi => SPISSR_frm_axi_clk, -- in
SPISSR_cdc_to_spi => register_Data_slvsel_int, -- out
----------------------------
spiXfer_done_cdc_to_axi_1 => spiXfer_done_to_axi_1,
----------------------------
drr_Overrun_int_cdc_from_spi => drr_Overrun_int_frm_spi_clk,
drr_Overrun_int_cdc_to_axi => drr_Overrun_int_to_axi_clk
----------------------------
);
-- Bu2IP Data to Interrupt Registers - IPISR and IPIER
-- Bus2IP_Data - 0 31
-- IPISR/IPIER - 0 17 18 31
-- <---NA---> <-used->
-- 18 19 20 21 22 23 24 25 26 27 28 29 30 31
-- CMD_ Loop_Bk MSB Slave_Mode CPOL_CPHA DRR_Not Slave Tx_FIFO DRR_ DRR_ DTR_ DTR Slave MODF
-- Error Error Error Error Error _Empty Select_mode Half_Empty Over_Run Full Underrun Empty MODF
-- In Slave
-- mode_only
-- <---------------------------------------> <------------------------------------------------------------->
-- In C_SPI_MODE 1 or 2 only Present in all conditions
-- IPISR Write
-- when FIFO = 1,all other the IPIER, IPISR interrupt bits are applicable based upon the SPI mode.
-- DRR_Not_Empty bit (bit 23) - available only in case of core is selected in
-- slave mode and control register mst_n_slv bit is '0'.
-- Slave_select_mode bit-available only in case of core is selected in slave mode
-- common assignment to SPI_MODE 1/2 and SPI_MODE = 0
bus2IP_Data_for_interrupt_core(0 to 17) <= Bus2IP_Data(0 to 17);
DUAL_MD_IPISR_GEN: if C_SPI_MODE = 1 or C_SPI_MODE = 2 generate
-----------------------
begin
-----
bus2IP_Data_for_interrupt_core(18 to 22) <= Bus2IP_Data(18 to 22);
end generate DUAL_MD_IPISR_GEN;
---------------------------------------------
STD_MD_IPISR_GEN: if C_SPI_MODE = 0 generate
-----------------------------------
begin
-----
bus2IP_Data_for_interrupt_core(18 to 22)<= (others => '0');
end generate STD_MD_IPISR_GEN;
------------------------------------------------
bus2IP_Data_for_interrupt_core(23) <= Bus2IP_Data(23) and -- exists only when FIFO = exists AND
((not spisel_d1_reg_to_axi_clk) --spisel_d1_reg)
or -- core is selected by asserting SPISEL by ext. master AND
(not SPICR_2_MST_N_SLV_frm_axi_clk) --Mst_N_Slv_mode) -- core is in slave mode
);
bus2IP_Data_for_interrupt_core(24 to (C_S_AXI_DATA_WIDTH-1)) <=
Bus2IP_Data(24 to (C_S_AXI_DATA_WIDTH-1));
--
----------------------------------------------------
-- _____|------------- data_Exists_RcFIFO_int
-- ________|---------- data_Exists_RcFIFO_int_d1
-- _____|--|__________ data_Exists_RcFIFO_pulse
----------------------------------------------------
DRR_NOT_EMPTY_PULSE_P: process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
data_Exists_RcFIFO_int_d1 <= '0';
else
data_Exists_RcFIFO_int_d1 <= not rx_fifo_empty_i; -- data_Exists_RcFIFO_int;
end if;
end if;
end process DRR_NOT_EMPTY_PULSE_P;
------------------------------------
data_Exists_RcFIFO_pulse <= not rx_fifo_empty_i and
(not data_Exists_RcFIFO_int_d1);
------------------------------------
---------------------------------------------------------------------------
DUAL_MD_INTR_GEN: if C_SPI_MODE = 1 or C_SPI_MODE = 2 generate
-----------------------
signal SPISR_4_CPOL_CPHA_Error_d1 : std_logic;
signal SPISR_3_Slave_Mode_Error_d1 : std_logic;
signal SPISR_2_MSB_Error_d1 : std_logic;
signal SPISR_1_LOOP_Back_Error_d1 : std_logic;
signal SPISR_0_CMD_Error_d1 : std_logic;
signal SPISR_4_CPOL_CPHA_Error_pulse : std_logic;
signal SPISR_3_Slave_Mode_Error_pulse: std_logic;
signal SPISR_2_MSB_Error_pulse : std_logic;
signal SPISR_1_LOOP_Back_Error_pulse : std_logic;
signal SPISR_0_CMD_Error_pulse : std_logic;
-----
begin
-----
INTR_UPPER_BITS_P: process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
SPISR_0_CMD_Error_d1 <= '0';
SPISR_1_LOOP_Back_Error_d1 <= '0';
SPISR_2_MSB_Error_d1 <= '0';
SPISR_3_Slave_Mode_Error_d1 <= '0';
SPISR_4_CPOL_CPHA_Error_d1 <= '0';
else
SPISR_0_CMD_Error_d1 <= SPISR_0_CMD_Error_to_axi_clk; -- SPISR_0_CMD_Error_int;
SPISR_1_LOOP_Back_Error_d1 <= SPISR_1_LOOP_Back_Error_int; -- from SPICR
SPISR_2_MSB_Error_d1 <= SPISR_2_MSB_Error_int; -- from SPICR
SPISR_3_Slave_Mode_Error_d1 <= SPISR_3_Slave_Mode_Error_int;-- from SPICR
SPISR_4_CPOL_CPHA_Error_d1 <= SPISR_4_CPOL_CPHA_Error_int; -- from SPICR
end if;
end if;
end process INTR_UPPER_BITS_P;
------------------------------------
SPISR_0_CMD_Error_pulse <= SPISR_0_CMD_Error_to_axi_clk -- SPISR_0_CMD_Error_int
and (not SPISR_0_CMD_Error_d1);
SPISR_1_LOOP_Back_Error_pulse <= SPISR_1_LOOP_Back_Error_int
and (not SPISR_1_LOOP_Back_Error_d1);
SPISR_2_MSB_Error_pulse <= SPISR_2_MSB_Error_int
and (not SPISR_2_MSB_Error_d1);
SPISR_3_Slave_Mode_Error_pulse <= SPISR_3_Slave_Mode_Error_int
and (not SPISR_3_Slave_Mode_Error_d1);
SPISR_4_CPOL_CPHA_Error_pulse <= SPISR_4_CPOL_CPHA_Error_int
and (not SPISR_4_CPOL_CPHA_Error_d1);
-- Interrupt Status Register(IPISR) Mapping
ip2Bus_IntrEvent_int(13) <= SPISR_0_CMD_Error_pulse;
ip2Bus_IntrEvent_int(12) <= SPISR_1_LOOP_Back_Error_pulse;
ip2Bus_IntrEvent_int(11) <= SPISR_2_MSB_Error_pulse;
ip2Bus_IntrEvent_int(10) <= SPISR_3_Slave_Mode_Error_pulse;
ip2Bus_IntrEvent_int(9) <= SPISR_4_CPOL_CPHA_Error_pulse ;
end generate DUAL_MD_INTR_GEN;
--------------------------------------------
STD_MD_INTR_GEN: if C_SPI_MODE = 0 generate
-----------------------
begin
-----
ip2Bus_IntrEvent_int(13) <= '0';
ip2Bus_IntrEvent_int(12) <= '0';
ip2Bus_IntrEvent_int(11) <= '0';
ip2Bus_IntrEvent_int(10) <= '0';
ip2Bus_IntrEvent_int(9) <= '0';
end generate STD_MD_INTR_GEN;
-----------------------------------------------
ip2Bus_IntrEvent_int(8) <= data_Exists_RcFIFO_pulse and
((not spisel_d1_reg_to_axi_clk) -- spisel_d1_reg)
or
(not SPICR_2_MST_N_SLV_frm_axi_clk) -- Mst_N_Slv_mode)
);
ip2Bus_IntrEvent_int(7) <= spisel_pulse_to_axi_clk;-- and not SPICR_2_MST_N_SLV_frm_axi_clk; -- spisel_pulse_o_int;-- spi_module
ip2Bus_IntrEvent_int(6) <= tx_FIFO_less_half_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(5) <= drr_Overrun_int_to_axi_clk; -- drr_Overrun_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(4) <= rc_FIFO_Full_strobe_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(3) <= dtr_Underrun_strobe_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(2) <= tx_FIFO_Empty_strobe_int; -- qspi_fifo_ifmodule
ip2Bus_IntrEvent_int(1) <= slave_MODF_strobe_to_axi_clk; --slave_MODF_strobe_int;-- spi_module
ip2Bus_IntrEvent_int(0) <= modf_strobe_to_axi_clk; -- modf_strobe_int; -- spi_module
--Combinatorial operations
reset_TxFIFO_ptr_int <= reset2ip_reset_int or SPICR_5_TXFIFO_RST_frm_axi_clk;
reset_TxFIFO_ptr_int_to_spi <= Rst_to_spi_int or SPICR_5_TXFIFO_to_spi_clk;
--reset_RcFIFO_ptr_int <= Rst_to_spi_int or SPICR_6_RXFIFO_RST_to_spi_clk; -- SPICR_6_RXFIFO_RST_int;
reset_RcFIFO_ptr_int <= reset2ip_reset_int or SPICR_6_RXFIFO_RST_frm_axi_clk;
sr_5_Tx_Empty_int <= not (data_Exists_TxFIFO_int);
Rc_FIFO_Empty_int <= Rx_FIFO_Empty;--not (data_Exists_RcFIFO_int);
-- AXI Clk domain -- __________________ SPI clk domain
--Dout --|AXI clk |-- Din
--Rd_en --| |-- Wr_en
--Rd_clk --| |-- Wr_clk
--| |--
--Rx_FIFO_Empty --| Rx FIFO |-- Rx_FIFO_Full
--Rx_FIFO_almost_Empty --| |-- Rx_FIFO_almost_Full
--Rx_FIFO_occ_Reversed --| |--
--Rx_FIFO_rd_ack --| |--
--| |--
--| |--
--| |--
--|__________________|--
RX_RD_EN_LEG_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
begin
-----
IP2Bus_RdAck_receive_enable <= (rd_ce_reduce_ack_gen and
Bus2IP_RdCE(SPIDRR)
)and
(not Rx_FIFO_Empty);
end generate RX_RD_EN_LEG_MD_GEN;
RX_RD_EN_ENHAN_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
begin
-----
IP2Bus_RdAck_receive_enable <= --(rd_ce_reduce_ack_gen and
(rready and
Bus2IP_RdCE(SPIDRR)
)and
(not Rx_FIFO_Empty);
end generate RX_RD_EN_ENHAN_MD_GEN;
-- Receive FIFO Logic
rx_fifo_reset <= Rst_to_spi_int or reset_RcFIFO_ptr_to_spi_clk;
RX_FIFO_II: entity lib_fifo_v1_0_5.async_fifo_fg --axi_quad_spi_v3_2_8_0.async_fifo_fg --lib_fifo_v1_0_5_4.async_fifo_fg
generic map(
-- for first word fall through FIFO below two parameters setting is must please dont change
C_PRELOAD_LATENCY => 0 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
C_PRELOAD_REGS => 1 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
-- variables
C_ALLOW_2N_DEPTH => 1 , -- : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY => C_FAMILY , -- : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH => C_NUM_TRANSFER_BITS, -- : integer := 16;
C_FIFO_DEPTH => C_FIFO_DEPTH , -- : integer := 15;
C_RD_COUNT_WIDTH => C_RD_COUNT_WIDTH_INT,-- : integer := 3 ;
C_WR_COUNT_WIDTH => C_WR_COUNT_WIDTH_INT,-- : integer := 3 ;
C_HAS_ALMOST_EMPTY => 1 , -- : integer := 1 ;
C_HAS_ALMOST_FULL => 1 , -- : integer := 1 ;
C_HAS_RD_ACK => 1 , -- : integer := 0 ;
C_HAS_RD_COUNT => 1 , -- : integer := 1 ;
C_HAS_WR_ACK => 1 , -- : integer := 0 ;
C_HAS_WR_COUNT => 1 , -- : integer := 1 ;
-- constants
C_HAS_RD_ERR => 0 , -- : integer := 0 ;
C_HAS_WR_ERR => 0 , -- : integer := 0 ;
C_RD_ACK_LOW => 0 , -- : integer := 0 ;
C_RD_ERR_LOW => 0 , -- : integer := 0 ;
C_WR_ACK_LOW => 0 , -- : integer := 0 ;
C_WR_ERR_LOW => 0 , -- : integer := 0
C_ENABLE_RLOCS => 0 , -- : integer := 0 ; -- not supported in FG
C_USE_BLOCKMEM => 0 -- : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
)
port map(
Din => Data_To_Rx_FIFO , -- : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en => spiXfer_done_int, --SPIXfer_done_Rx_Wr_en, -- , -- : in std_logic := '1';
Wr_clk => EXT_SPI_CLK , -- : in std_logic := '1';
Wr_ack => Rx_FIFO_wr_ack_open , -- : out std_logic;
------
Dout => Data_From_Rx_FIFO , -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Rd_en => IP2Bus_RdAck_receive_enable , -- : in std_logic := '0';
Rd_clk => Bus2IP_Clk , -- : in std_logic := '1';
Rd_ack => Rx_FIFO_rd_ack , -- : out std_logic;
------
Full => Rx_FIFO_Full_Fifo_org , -- : out std_logic;
Empty => Rx_FIFO_Empty , -- : out std_logic;
Almost_full => Rx_FIFO_almost_Full , -- : out std_logic;
Almost_empty => Rx_FIFO_almost_Empty , -- : out std_logic;
Rd_count => Rx_FIFO_occ_Reversed , -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
------
Ainit => rx_fifo_reset, -- reset_RcFIFO_ptr_to_spi_clk ,--reset_RcFIFO_ptr_int, -- reset_RcFIFO_ptr_to_spi_clk ,--Rx_FIFO_ptr_RST , -- : in std_logic := '1';
Wr_count => open , -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_err => open , -- : out std_logic;
Wr_err => open -- : out std_logic
);
RX_FIFO_EMPTY_SYNC_AXI_2_SPI_CDC : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1, -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => '0',
prmry_in => Rx_FIFO_Empty,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => '0' ,
scndry_out => Rx_FIFO_Empty_Synced_in_SPI_domain
);
Rx_FIFO_Full_Fifo <= Rx_FIFO_Full_Fifo_org and not Rx_FIFO_Empty_Synced_in_SPI_domain;
RX_FULL_DELAY_PROCESS: process(EXT_SPI_CLK) is
----------------------
begin
-----
if(EXT_SPI_CLK'event and EXT_SPI_CLK='1') then
if (Rst_to_spi_int = '1') then
Rx_FIFO_Full_Fifo_d1 <= '0';
else
Rx_FIFO_Full_Fifo_d1 <= Rx_FIFO_Full_Fifo;
end if;
end if;
end process RX_FULL_DELAY_PROCESS;
RX_FULL_EDGE_PROCESS: process(Bus2IP_Clk) is
----------------------
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
Rx_FIFO_Full_Fifo_d1_flag <= '0';
else
Rx_FIFO_Full_Fifo_d1_flag <= Rx_FIFO_Full_Fifo_d1_synced;
end if;
end if;
end process RX_FULL_EDGE_PROCESS;
Rx_FIFO_Full_Fifo_pos_flag <= Rx_FIFO_Full_Fifo_d1_synced and (not Rx_FIFO_Full_Fifo_d1_flag);
--Rx_FIFO_Full_Fifo_neg_flag <= (not Rx_FIFO_Full_Fifo_d1_synced) and Rx_FIFO_Full_Fifo_d1_flag;
RX_FULL_GEN_PROCESS: process(Bus2IP_Clk) is
----------------------
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
Rx_FIFO_Full_Fifo_d1_sig <= '0';
elsif(IP2Bus_RdAck_receive_enable = '1' and Rx_FIFO_Full_Fifo_d1_synced = '1')then
Rx_FIFO_Full_Fifo_d1_sig <= '0';
elsif(Rx_FIFO_Full_Fifo_pos_flag = '1') then
Rx_FIFO_Full_Fifo_d1_sig <= '1';
end if;
end if;
end process RX_FULL_GEN_PROCESS;
----------------------------------
RX_FIFO_FULL_SYNCED_SPI_2_AXI_CDC : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1, -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => '0',
prmry_in => Rx_FIFO_Full_Fifo_d1,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => '0' ,
scndry_out => Rx_FIFO_Full_Fifo_d1_synced
);
RX_FIFO_FULL_CNTR_I : entity axi_quad_spi_v3_2_8.counter_f
generic map(
C_NUM_BITS => RX_FIFO_CNTR_WIDTH,
C_FAMILY => "nofamily"
)
port map(
Clk => Bus2IP_Clk, -- in
Rst => '0', -- in
Load_In => ALL_0, -- in
Count_Enable => updown_cnt_en_rx, -- in
----------------
Count_Load => reset_RcFIFO_ptr_int, -- in
----------------
Count_Down => IP2Bus_RdAck_receive_enable, -- in
Count_Out => rx_fifo_count, -- out std_logic_vector
Carry_Out => open -- out
);
--updown_cnt_en_rx <= IP2Bus_RdAck_receive_enable xor spiXfer_done_to_axi_1;
--fifo_full_f_int <= Rx_FIFO_Full_Fifo_d1_synced when
--updown_cnt_en_rx <= ((not spiXfer_done_to_axi_1) and IP2Bus_RdAck_receive_enable and Rx_FIFO_Full_int and (not Rx_FIFO_Full_Fifo_d1_synced)) or ((IP2Bus_RdAck_receive_enable xor spiXfer_done_to_axi_1) and (not Rx_FIFO_Full_Fifo_d1_synced) and (not Rx_FIFO_Full_int));
updown_cnt_en_rx <= ((not spiXfer_done_to_axi_1) and IP2Bus_RdAck_receive_enable and Rx_FIFO_Full_int and (not (Rx_FIFO_Full_Fifo_d1_sig or Rx_FIFO_Full_Fifo_pos_flag))) or ((IP2Bus_RdAck_receive_enable xor spiXfer_done_to_axi_1) and (not (Rx_FIFO_Full_Fifo_d1_sig or Rx_FIFO_Full_Fifo_pos_flag)) and (not Rx_FIFO_Full_int));
-- updown_cnt_en_rx <= (IP2Bus_RdAck_receive_enable and Rx_FIFO_Full_int)
-- or (spiXfer_done_to_axi_1 and (not Rx_FIFO_Full_int))
-- or ((IP2Bus_RdAck_receive_enable xor spiXfer_done_to_axi_1) and (not Rx_FIFO_Full_int));
RX_one_less_than_full <= and_reduce(rx_fifo_count(RX_FIFO_CNTR_WIDTH-1 downto RX_FIFO_CNTR_WIDTH-RX_FIFO_CNTR_WIDTH+1)) and
(not rx_fifo_count(0))and spiXfer_done_to_axi_1;
RX_FULL_EMP_MD_12_INTR_GEN: if C_SPI_MODE /= 0 generate
-----
--signal rx_fifo_empty_i : std_logic;
begin
-----
RX_FIFO_EMPTY_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
rx_fifo_empty_i <= '1';
elsif(reset_RcFIFO_ptr_int = '1')then
rx_fifo_empty_i <= '1';
elsif(spiXfer_done_to_axi_1 = '1')then
rx_fifo_empty_i <= '0';
end if;
end if;
end process RX_FIFO_EMPTY_P;
RX_FIFO_FULL_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Rx_FIFO_Full_int <= '0';
--elsif(reset_RcFIFO_ptr_int = '1') or (drr_Overrun_int_to_axi_clk = '1') then --(drr_Overrun_int = '1')then
elsif(reset_RcFIFO_ptr_int = '1') then --(drr_Overrun_int = '1')then
Rx_FIFO_Full_int <= '0';
elsif(Rx_FIFO_Full_int = '1' and IP2Bus_RdAck_receive_enable = '1') then -- IP2Bus_RdAck_receive_enable = '1')then
Rx_FIFO_Full_int <= '0';
elsif(RX_one_less_than_full = '1' and
spiXfer_done_to_axi_1 = '1' and
rx_fifo_empty_i = '0')then
Rx_FIFO_Full_int <= '1';
end if;
end if;
end process RX_FIFO_FULL_P;
end generate RX_FULL_EMP_MD_12_INTR_GEN;
------------------------------------
RX_FULL_EMP_MD_0_GEN: if C_SPI_MODE = 0 generate
--signal rx_fifo_empty_i : std_logic;
-----
begin
-----
RX_FIFO_EMPTY_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
rx_fifo_empty_i <= '1';
elsif(reset_RcFIFO_ptr_int = '1')then
rx_fifo_empty_i <= '1';
elsif(spiXfer_done_to_axi_1 = '1')then
rx_fifo_empty_i <= '0';
end if;
end if;
end process RX_FIFO_EMPTY_P;
-------------------------------------------
RX_FIFO_ABT_TO_FULL_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Rx_FIFO_Full_i <= '0';
--elsif(reset_RcFIFO_ptr_int = '1') or (drr_Overrun_int_to_axi_clk = '1') then -- (drr_Overrun_int = '1')then
elsif(reset_RcFIFO_ptr_int = '1') then -- (drr_Overrun_int = '1')then
Rx_FIFO_Full_i <= '0';
elsif(Rx_FIFO_Full_int = '1')then
Rx_FIFO_Full_i <= '0';
elsif(RX_one_less_than_full = '1')then
Rx_FIFO_Full_i <= '1';
end if;
end if;
end process RX_FIFO_ABT_TO_FULL_P;
-------------------------------------
RX_FIFO_FULL_P: process(Bus2IP_Clk)is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Rx_FIFO_Full_int <= '0';
--elsif(reset_RcFIFO_ptr_int = '1') or (drr_Overrun_int_to_axi_clk = '1') then -- (drr_Overrun_int = '1')then
elsif(reset_RcFIFO_ptr_int = '1') then -- (drr_Overrun_int = '1')then
Rx_FIFO_Full_int <= '0';
elsif(Rx_FIFO_Full_int = '1' and IP2Bus_RdAck_receive_enable = '1') then -- IP2Bus_RdAck_receive_enable = '1')then
Rx_FIFO_Full_int <= '0';
elsif(Rx_FIFO_Full_i = '1')then
Rx_FIFO_Full_int <= '1';
end if;
end if;
end process RX_FIFO_FULL_P;
---------------------------------
Rx_FIFO_Full <= Rx_FIFO_Full_int;
end generate RX_FULL_EMP_MD_0_GEN;
Rx_FIFO_Empty_int <= Rx_FIFO_Empty or Rx_FIFO_Empty_i;
-----------------------------------------------------------------------------
-- AXI Clk domain -- __________________ SPI clk domain
--Din --|AXI clk |-- Dout
--Wr_en --| |-- Rd_en
--Wr_clk --| |-- Rd_clk
--| |--
--Tx_FIFO_Full --| Tx FIFO |-- Tx_FIFO_Empty
--Tx_FIFO_almost_Full --| |-- Tx_FIFO_almost_Empty
--Tx_FIFO_occ_Reversed --| |-- Tx_FIFO_rd_ack
--Tx_FIFO_wr_ack --| |--
--| |--
--| |--
--| |--
--|__________________|--
TX_TR_EN_LEG_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 0 generate
begin
-----
IP2Bus_WrAck_transmit_enable <= (wr_ce_reduce_ack_gen and
Bus2IP_WrCE(SPIDTR)
) and
(not Tx_FIFO_Full);-- after 100 ps;
end generate TX_TR_EN_LEG_MD_GEN;
TX_TR_EN_ENHAN_MD_GEN: if C_TYPE_OF_AXI4_INTERFACE = 1 generate
signal local_tr_en : std_logic;
begin
-----
--IP2Bus_WrAck_transmit_enable <= (wr_ce_reduce_ack_gen and
-- Bus2IP_WrCE(SPIDTR)
-- ) and
-- (not Tx_FIFO_Full)
-- when burst_tr = '0' else
-- (Bus2IP_WrCE(SPIDTR)
-- and
-- (not Tx_FIFO_Full));-- after 100 ps;
local_tr_en <= Bus2IP_WrCE(SPIDTR) and (not Tx_FIFO_Full);
--local_tr_en1 <= Bus2IP_WrCE_d1 and (not Tx_FIFO_Full);
TR_EN_P:process(wr_ce_reduce_ack_gen,
local_tr_en,
burst_tr,
WVALID)is
begin
if(burst_tr = '1') then
IP2Bus_WrAck_transmit_enable <= local_tr_en and WVALID; -- Bus2IP_WrCE_d1 and (not Tx_FIFO_Full); --local_tr_en;
else
IP2Bus_WrAck_transmit_enable <= local_tr_en and wr_ce_reduce_ack_gen;
end if;
end process TR_EN_P;
end generate TX_TR_EN_ENHAN_MD_GEN;
Data_To_TxFIFO <= Bus2IP_Data((C_S_AXI_DATA_WIDTH-C_NUM_TRANSFER_BITS) to(C_S_AXI_DATA_WIDTH-1));-- after 100 ps;
-- Transmit FIFO Logic
tx_fifo_reset <= reset2ip_reset_int or reset_TxFIFO_ptr_int;
TX_FIFO_II: entity lib_fifo_v1_0_5.async_fifo_fg -- entity axi_quad_spi_v3_2_8_0.async_fifo_fg -- lib_fifo_v1_0_5_4.async_fifo_fg
generic map
(
-- for first word fall through FIFO below two parameters setting is must please dont change
C_PRELOAD_LATENCY => 0 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
C_PRELOAD_REGS => 1 ,-- this is newly added and async_fifo_fg is referred from proc common v4_0
-- variables
C_ALLOW_2N_DEPTH => 1 , -- : Integer := 0; -- New paramter to leverage FIFO Gen 2**N depth
C_FAMILY => C_FAMILY , -- : String := "virtex5"; -- new for FIFO Gen
C_DATA_WIDTH => C_NUM_TRANSFER_BITS, -- : integer := 16;
C_FIFO_DEPTH => C_FIFO_DEPTH , -- : integer := 15;
C_RD_COUNT_WIDTH => C_RD_COUNT_WIDTH_INT,-- : integer := 3 ;
C_WR_COUNT_WIDTH => C_WR_COUNT_WIDTH_INT,-- : integer := 3 ;
C_HAS_ALMOST_EMPTY => 1 , -- : integer := 1 ;
C_HAS_ALMOST_FULL => 1 , -- : integer := 1 ;
C_HAS_RD_ACK => 1 , -- : integer := 0 ;
C_HAS_RD_COUNT => 1 , -- : integer := 1 ;
C_HAS_WR_ACK => 1 , -- : integer := 0 ;
C_HAS_WR_COUNT => 1 , -- : integer := 1 ;
-- constants
C_HAS_RD_ERR => 0 , -- : integer := 0 ;
C_HAS_WR_ERR => 0 , -- : integer := 0 ;
C_RD_ACK_LOW => 0 , -- : integer := 0 ;
C_RD_ERR_LOW => 0 , -- : integer := 0 ;
C_WR_ACK_LOW => 0 , -- : integer := 0 ;
C_WR_ERR_LOW => 0 , -- : integer := 0
C_ENABLE_RLOCS => 0 , -- : integer := 0 ; -- not supported in FG
C_USE_BLOCKMEM => 0 -- : integer := 1 ; -- 0 = distributed RAM, 1 = BRAM
)
port map
(
-- writing will be through AXI clock
Wr_clk => Bus2IP_Clk , -- : in std_logic := '1';
Din => Data_To_TxFIFO , -- : in std_logic_vector(C_DATA_WIDTH-1 downto 0) := (others => '0');
Wr_en => IP2Bus_WrAck_transmit_enable, -- : in std_logic := '1';
Wr_ack => Tx_FIFO_wr_ack , -- : out std_logic;
------
-- reading will be through SPI clock
Rd_clk => EXT_SPI_CLK , -- : in std_logic := '1';
Dout => Data_From_TxFIFO , -- : out std_logic_vector(C_DATA_WIDTH-1 downto 0);
Rd_en => SPIXfer_done_rd_tx_en , -- : in std_logic := '0';
Rd_ack => Tx_FIFO_rd_ack_open , -- : out std_logic;
------
Full => Tx_FIFO_Full , -- : out std_logic;
Empty => Tx_FIFO_Empty , -- : out std_logic;
Almost_full => Tx_FIFO_almost_Full , -- : out std_logic;
Almost_empty => Tx_FIFO_almost_Empty , -- : out std_logic;
Rd_count => open , -- : out std_logic_vector(C_RD_COUNT_WIDTH-1 downto 0);
------
Ainit => reset_TxFIFO_ptr_int ,--Tx_FIFO_ptr_RST , -- : in std_logic := '1';
Wr_count => Tx_FIFO_occ_Reversed , -- : out std_logic_vector(C_WR_COUNT_WIDTH-1 downto 0);
Rd_err => open , -- : out std_logic;
Wr_err => open -- : out std_logic
);
--tx_occ_msb <= tx_fifo_count(TX_FIFO_CNTR_WIDTH-1); -- --Tx_FIFO_occ_Reversed(C_WR_COUNT_WIDTH_INT-1);
--tx_occ_msb_1 <= (tx_fifo_count(TX_FIFO_CNTR_WIDTH-1));-- and not(or_reduce(tx_fifo_count(TX_FIFO_CNTR_WIDTH-2 downto 0))) ;--
--and not Tx_FIFO_Empty_SPISR_to_axi_clk;-- and not Tx_FIFO_Full_int; -- --Tx_FIFO_occ_Reversed(C_WR_COUNT_WIDTH_INT-1);
tx_occ_msb_11 <= (tx_fifo_count);
FIFO_16_OCC_MSB_GEN: if C_FIFO_DEPTH = 16 generate
begin
tx_occ_msb_1 <= tx_occ_msb_11(3);
end generate FIFO_16_OCC_MSB_GEN;
FIFO_256_OCC_MSB_GEN: if C_FIFO_DEPTH = 256 generate
begin
tx_occ_msb_1 <= tx_occ_msb_11(7);
end generate FIFO_256_OCC_MSB_GEN;
TX_OCC_MSB_P: process (Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
tx_occ_msb_2 <= '0';
tx_occ_msb_3 <= '0';
tx_occ_msb_4 <= '0';
else
tx_occ_msb_2 <= tx_occ_msb_1;
tx_occ_msb_3 <= tx_occ_msb_2;
tx_occ_msb_4 <= tx_occ_msb_3;
end if;
end if;
end process TX_OCC_MSB_P;
tx_occ_msb <= tx_occ_msb_4 and not Tx_FIFO_Empty_SPISR_to_axi_clk;
data_Exists_TxFIFO_int <= not (Tx_FIFO_Empty);
-----------------------------------------------------------
TX_FIFO_EMPTY_CNTR_I : entity axi_quad_spi_v3_2_8.counter_f
generic map(
C_NUM_BITS => TX_FIFO_CNTR_WIDTH,
C_FAMILY => "nofamily"
)
port map(
Clk => Bus2IP_Clk, -- in
Rst => '0', -- in
Load_In => ALL_0, -- in
Count_Enable => updown_cnt_en, -- in
----------------
Count_Load => reset_TxFIFO_ptr_int, -- in
----------------
Count_Down => spiXfer_done_to_axi_1, -- in
Count_Out => tx_fifo_count, -- out std_logic_vector
Carry_Out => open -- out
);
updown_cnt_en <= IP2Bus_WrAck_transmit_enable xor spiXfer_done_to_axi_1;
----------------------------------------
TX_FULL_EMP_INTR_MD_12_GEN: if C_SPI_MODE /=0 generate
-----
begin
-----
Tx_FIFO_Empty_intr <= not (or_reduce(tx_fifo_count(TX_FIFO_CNTR_WIDTH-1 downto 0)))
-- and (tx_fifo_count(0))
and spiXfer_done_to_axi_1
and ( Tx_FIFO_Empty_SPISR_to_axi_clk); -- and ( Tx_FIFO_Empty);
Tx_FIFO_Full_int <= Tx_FIFO_Full;
end generate TX_FULL_EMP_INTR_MD_12_GEN;
----------------------------------------
----------------------------------------
TX_FULL_EMP_INTR_MD_0_GEN: if C_SPI_MODE =0 generate
-----
begin
-----
-- Tx_FIFO_one_less_to_Empty <= not(or_reduce(tx_fifo_count(TX_FIFO_CNTR_WIDTH-1 downto 0)))
-- --and (tx_fifo_count(0))
-- and spiXfer_done_to_axi_1;--tx_cntr_xfer_done_to_axi_1_clk; --
-- --------------------------------------------
-- TX_FIFO_ABT_TO_EMPTY_P:process(Bus2IP_Clk)is
-- begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(reset2ip_reset_int = RESET_ACTIVE)then
-- Tx_FIFO_Empty_i <= '0';
-- elsif(Tx_FIFO_Empty_int = '1')then
-- Tx_FIFO_Empty_i <= '0';
-- elsif(Tx_FIFO_one_less_to_Empty = '1') or then
-- Tx_FIFO_Empty_i <= '1';
-- end if;
-- end if;
-- end process TX_FIFO_ABT_TO_EMPTY_P;
-- --------------------------------------
-- TX_FIFO_EMPTY_P: process(Bus2IP_Clk)is
-- begin
-- -----
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(reset2ip_reset_int = RESET_ACTIVE)then
-- Tx_FIFO_Empty_int <= '0';
-- elsif(Tx_FIFO_Empty_int = '1' and spiXfer_done_to_axi_1 = '1')then
-- Tx_FIFO_Empty_int <= '0';
-- elsif(Tx_FIFO_Empty_i = '1')then
-- Tx_FIFO_Empty_int <= '1';
-- end if;
-- end if;
-- end process TX_FIFO_EMPTY_P;
--------------------------------
-- Tx_FIFO_Empty_intr <= Tx_FIFO_Empty_int and spiXfer_done_to_axi_1;
--------------------------------
TX_FIFO_CNTR_DELAY_P: process(Bus2IP_Clk)is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
tx_fifo_count_d1 <= (others => '0');
tx_fifo_count_d2 <= (others => '0');
spiXfer_done_to_axi_d1 <= '0';
else
tx_fifo_count_d1 <= tx_fifo_count;
tx_fifo_count_d2 <= tx_fifo_count_d1;
spiXfer_done_to_axi_d1 <= spiXfer_done_to_axi_1;
end if;
end if;
end process TX_FIFO_CNTR_DELAY_P;
Tx_FIFO_Empty_intr <= (not (or_reduce(tx_fifo_count_d2(TX_FIFO_CNTR_WIDTH-1 downto 0)))
-- and (tx_fifo_count(0))
and spiXfer_done_to_axi_d1
and ( Tx_FIFO_Empty_SPISR_to_axi_clk));
TX_one_less_than_full <= and_reduce(tx_fifo_count(TX_FIFO_CNTR_WIDTH-1 downto TX_FIFO_CNTR_WIDTH-TX_FIFO_CNTR_WIDTH+1)) and
(not tx_fifo_count(0))and IP2Bus_WrAck_transmit_enable;
-------------------------------------------
TX_FIFO_ABT_TO_FULL_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Tx_FIFO_Full_i <= '0';
elsif(reset_TxFIFO_ptr_int = '1')then
Tx_FIFO_Full_i <= '0';
elsif(Tx_FIFO_Full_int = '1')then
Tx_FIFO_Full_i <= '0';
elsif(TX_one_less_than_full = '1')then
Tx_FIFO_Full_i <= '1';
end if;
end if;
end process TX_FIFO_ABT_TO_FULL_P;
----------------------------------
TX_FIFO_FULL_P: process(Bus2IP_Clk)is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(reset2ip_reset_int = RESET_ACTIVE)then
Tx_FIFO_Full_int <= '0';
elsif(reset_TxFIFO_ptr_int = '1')then
Tx_FIFO_Full_int <= '0';
elsif(Tx_FIFO_Full_int = '1' and spiXfer_done_to_axi_1 = '1')then
Tx_FIFO_Full_int <= '0';
elsif(Tx_FIFO_Full_i = '1') then -- and spiXfer_done_to_axi_1 = '1')then
Tx_FIFO_Full_int <= '1';
end if;
end if;
end process TX_FIFO_FULL_P;
---------------------------
end generate TX_FULL_EMP_INTR_MD_0_GEN;
----------------------------------------
-------------------------------------------------------------------------------
-- I_FIFO_IF_MODULE : INSTANTIATE FIFO INTERFACE MODULE
-------------------------------------------------------------------------------
Rx_FIFO_Full_Fifo_d1_synced_i <= Rx_FIFO_Full_Fifo_d1_synced and (not Rx_FIFO_Empty);
FIFO_IF_MODULE_I: entity axi_quad_spi_v3_2_8.qspi_fifo_ifmodule
generic map
(
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS
)
port map
(
Bus2IP_Clk => Bus2IP_Clk , -- in
Soft_Reset_op => reset2ip_reset_int, -- in
-- Slave attachment ports from AXI clock
Bus2IP_RcFIFO_RdCE => Bus2IP_RdCE(SPIDRR),-- axiclk -- in
Bus2IP_TxFIFO_WrCE => Bus2IP_WrCE(SPIDTR),-- axi clk -- in
Rd_ce_reduce_ack_gen => rd_ce_reduce_ack_gen,-- axi clk -- in
-- FIFO ports
Data_From_TxFIFO => Data_From_TxFIFO ,-- spi clk -- in vec
Data_From_Rc_FIFO => Data_From_Rx_FIFO ,-- axi clk -- in vec
Tx_FIFO_Data_WithZero => transmit_Data_int ,-- spi clk -- out vec
IP2Bus_RX_FIFO_Data => IP2Bus_Receive_Reg_Data_int, -- out vec
---------------------
--Rc_FIFO_Full => Rx_FIFO_Full_int, -- Rx_FIFO_Full_to_axi_clk, -- in
Rc_FIFO_Full => Rx_FIFO_Full_Fifo_d1_synced_i, -- Rx_FIFO_Full_to_axi_clk, -- in
Rc_FIFO_Full_strobe => rc_FIFO_Full_strobe_int, -- out
---------------------
Tx_FIFO_Empty => Tx_FIFO_Empty_intr , -- Tx_FIFO_Empty_to_Axi_clk, -- sr_5_Tx_Empty_int,-- spi clk -- in
Tx_FIFO_Empty_strobe => tx_FIFO_Empty_strobe_int, -- out
---------------------
Rc_FIFO_Empty => Rx_FIFO_Empty_int, -- 13-09-2012 rx_fifo_empty_i, -- Rx_FIFO_Empty , -- Rc_FIFO_Empty_int, -- in
Receive_ip2bus_error => receive_ip2bus_error, -- out
Tx_FIFO_Full => Tx_FIFO_Full_int, -- in
Transmit_ip2bus_error => transmit_ip2bus_error, -- out
---------------------
Tx_FIFO_Occpncy_MSB => tx_occ_msb, -- in
Tx_FIFO_less_half => tx_FIFO_less_half_int, -- out
---------------------
DTR_underrun => dtr_underrun_to_axi_clk,-- dtr_underrun_int,-- in
DTR_Underrun_strobe => dtr_Underrun_strobe_int, -- out
---------------------
SPIXfer_done => spiXfer_done_to_axi_1, -- spiXfer_done_int, -- in
rready => rready
-- DRR_Overrun_reg => drr_Overrun_int -- out
);
-------------------------------------------------------------------------------
-- TX_OCCUPANCY_I : INSTANTIATE TRANSMIT OCCUPANCY REGISTER
-------------------------------------------------------------------------------
TX_OCCUPANCY_I: entity axi_quad_spi_v3_2_8.qspi_occupancy_reg
generic map
(
C_OCCUPANCY_NUM_BITS => C_OCCUPANCY_NUM_BITS
)
port map
(
--Slave attachment ports
Bus2IP_OCC_REG_RdCE => Bus2IP_RdCE(SPITFOR), -- in
--FIFO port
IP2Reg_OCC_Data => tx_fifo_count, -- tx_FIFO_occ_Reversed, -- in vec
IP2Bus_OCC_REG_Data => IP2Bus_Tx_FIFO_OCC_Reg_Data_int -- out vec
);
-------------------------------------------------------------------------------
-- RX_OCCUPANCY_I : INSTANTIATE RECEIVE OCCUPANCY REGISTER
-------------------------------------------------------------------------------
RX_OCCUPANCY_I: entity axi_quad_spi_v3_2_8.qspi_occupancy_reg
generic map
(
C_OCCUPANCY_NUM_BITS => C_OCCUPANCY_NUM_BITS--,
)
port map
(
--Slave attachment ports
Bus2IP_OCC_REG_RdCE => Bus2IP_RdCE(SPIRFOR), -- in
--FIFO port
IP2Reg_OCC_Data => rx_fifo_count, --rx_FIFO_occ_Reversed, -- in vec
IP2Bus_OCC_REG_Data => IP2Bus_Rx_FIFO_OCC_Reg_Data_int -- out vec
);
end generate FIFO_EXISTS;
--------------------------------------------
-- LOGIC_FOR_MD_0_GEN: in stantiate the original SPI module when the core is configured in Standard SPI mode.
------------------------------
LOGIC_FOR_MD_0_GEN: if C_SPI_MODE = 0 generate
---------------------------
signal SCK_O_int : std_logic;
signal MISO_I_int: std_logic;
-----
begin
-----
-- un used IO2 and IO3 O/P ports are tied to 0 and T ports are tied to '1'
DATA_STARTUP_USED : if C_USE_STARTUP = 1 generate
-----
begin
-----
-- IO2_O <= do(2);
-- IO2_T <= dts(2);
-- IO3_O <= do(3);
-- IO3_T <= dts(3);
IO2_O <= '0';
IO2_T <= '1';
IO3_O <= '0';
IO3_T <= '1';
SPISR_0_CMD_Error_int <= '0'; -- no command error when C_SPI_MODE= 0
end generate DATA_STARTUP_USED;
-------------------------------------------------------
SCK_MISO_NO_STARTUP_USED: if C_USE_STARTUP = 0 generate
-----
begin
-----
IO2_O <= '0';
IO2_T <= '1';
IO3_O <= '0';
IO3_T <= '1';
SCK_O <= SCK_O_int; -- output from the core
MISO_I_int <= IO1_I; -- input to the core
end generate SCK_MISO_NO_STARTUP_USED;
-------------------------------------------------------
-------------------------------------------------------
SCK_MISO_STARTUP_USED: if C_USE_STARTUP = 1 generate
-----
begin
-----
QSPI_STARTUP_BLOCK_I: entity axi_quad_spi_v3_2_8.qspi_startup_block
---------------------
generic map
(
C_SUB_FAMILY => C_SUB_FAMILY , -- support for V6/V7/K7/A7 families only
-----------------
C_USE_STARTUP => C_USE_STARTUP,
-----------------
C_SHARED_STARTUP => C_SHARED_STARTUP,
-----------------
C_SPI_MODE => C_SPI_MODE
-----------------
)
port map
(
SCK_O => SCK_O_int, -- : in std_logic; -- input from the qspi_mode_0_module
IO1_I_startup => IO1_I, -- : in std_logic; -- input from the top level port list
IO1_Int => MISO_I_int,-- : out std_logic
Bus2IP_Clk => Bus2IP_Clk,
reset2ip_reset => reset2ip_reset_int,
CFGCLK => cfgclk, -- FGCLK , -- 1-bit output: Configuration main clock output
CFGMCLK => cfgmclk, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
EOS => eos, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => preq, -- REQ , -- 1-bit output: PROGRAM request to fabric output
DI => di_int, -- output
DO => do_int, -- 4-bit input
DTS => dts_int, -- 4-bit input
FCSBO => fcsbo_int, -- 1-bit input
FCSBTS => fcsbts_int,-- 1-bit input
CLK => clk, -- 1-bit input, SetReset
GSR => gsr, -- 1-bit input, SetReset
GTS => gts, -- 1-bit input
KEYCLEARB => keyclearb, --1-bit input
PACK => pack, --1-bit input
USRCCLKTS => usrcclkts, -- SRCCLKTS , -- 1-bit input
USRDONEO => usrdoneo, -- SRDONEO , -- 1-bit input
USRDONETS => usrdonets -- SRDONETS -- 1-bit input
);
--------------------
end generate SCK_MISO_STARTUP_USED;
-------------------------------------------------------
----------------------------------------------------------------------------
-- SPI_MODULE_I : INSTANTIATE SPI MODULE
----------------------------------------------------------------------------
SPI_MODULE_I: entity axi_quad_spi_v3_2_8.qspi_mode_0_module
-------------
generic map
(
C_SCK_RATIO => C_SCK_RATIO ,
C_USE_STARTUP => C_USE_STARTUP ,
C_SPICR_REG_WIDTH => C_SPICR_REG_WIDTH ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS ,
C_SUB_FAMILY => C_SUB_FAMILY ,
C_FIFO_EXIST => C_FIFO_EXIST
)
port map
(
Bus2IP_Clk => EXT_SPI_CLK, -- in
Soft_Reset_op => Rst_to_spi_int, -- in
------------------------
SPICR_0_LOOP => SPICR_0_LOOP_to_spi_clk,--_int,
SPICR_1_SPE => SPICR_1_SPE_to_spi_clk,--_int,
SPICR_2_MASTER_N_SLV => SPICR_2_MST_N_SLV_to_spi_clk,--_int,
SPICR_3_CPOL => SPICR_3_CPOL_to_spi_clk,--_int,
SPICR_4_CPHA => SPICR_4_CPHA_to_spi_clk,--_int,
SPICR_5_TXFIFO_RST => SPICR_5_TXFIFO_to_spi_clk, -- SPICR_5_TXFIFO_RST_to_spi_clk,--_int,
SPICR_6_RXFIFO_RST => SPICR_6_RXFIFO_RST_to_spi_clk,--_int,
SPICR_7_SS => SPICR_7_SS_to_spi_clk,--_int,
SPICR_8_TR_INHIBIT => SPICR_8_TR_INHIBIT_to_spi_clk,--_int,
SPICR_9_LSB => SPICR_9_LSB_to_spi_clk,--_int,
------------------------
Rx_FIFO_Empty_i_no_fifo => Rx_FIFO_Empty_i, -- in
SR_3_MODF => SR_3_modf_to_spi_clk, -- in
SR_5_Tx_Empty => Tx_FIFO_Empty, -- sr_5_Tx_Empty_int, -- in
Slave_MODF_strobe => slave_MODF_strobe_int, -- out
MODF_strobe => modf_strobe_int, -- out
Slave_Select_Reg => register_Data_slvsel_int, -- already updated -- in vec
Transmit_Data => Data_From_TxFIFO, -- transmit_Data_int, -- in vec
Receive_Data => Data_To_Rx_FIFO, -- receive_Data_int, -- out vec
SPIXfer_done => spiXfer_done_int, -- out
-- SPIXfer_done_Rx_Wr_en=> SPIXfer_done_Rx_Wr_en,
DTR_underrun => dtr_underrun_int, -- out
SPIXfer_done_rd_tx_en=> SPIXfer_done_rd_tx_en,
--SPI Ports
SCK_I => SCK_I, -- in
SCK_O_reg => SCK_O_int, -- out
SCK_T => SCK_T, -- out
MISO_I => str_IO1_I, --IO0_I, -- MOSI_I, -- in std_logic; -- MISO
MISO_O => str_IO1_O,--IO0_O, -- MOSI_O, -- out std_logic;
MISO_T => str_IO1_T, --IO0_T, -- MOSI_T, -- out std_logic;
MOSI_I => str_IO0_I,--MISO_I_int, -- IO1_I, -- MISO_I, -- in std_logic;
MOSI_O => str_IO0_O,--IO1_O, -- MISO_O, -- out std_logic; -- MOSI
MOSI_T => str_IO0_T,--IO1_T, -- MISO_T, -- out std_logic;
--MISO_I => MISO_I_int, -- IO1_I, -- MISO_I, -- in
--MISO_O => IO1_O, -- MISO_O, -- out
--MISO_T => IO1_T, -- MISO_T, -- out
--MOSI_I => IO0_I, -- MOSI_I, -- in
--MOSI_O => IO0_O, -- MOSI_O, -- out
--MOSI_T => IO0_T, -- MOSI_T, -- out
SPISEL => SPISEL, -- in
SS_I => SS_I_int, -- in
SS_O => SS_O_int, -- out
SS_T => SS_T_int, -- out
SPISEL_pulse_op => spisel_pulse_o_int , -- out std_logic;
SPISEL_d1_reg => spisel_d1_reg , -- out std_logic;
control_bit_7_8 => SPICR_bits_7_8_to_spi_clk, -- in vec
Mst_N_Slv_mode => Mst_N_Slv_mode ,
--Rx_FIFO_Full => Rx_FIFO_Full_to_spi_clk,
Rx_FIFO_Full => Rx_FIFO_Full_Fifo,
DRR_Overrun_reg => drr_Overrun_int, -- out
reset_RcFIFO_ptr_to_spi => reset_RcFIFO_ptr_to_spi_clk,
tx_cntr_xfer_done => tx_cntr_xfer_done
);
-------------
end generate LOGIC_FOR_MD_0_GEN;
----------------------------------------
-- LOGIC_FOR_MD_12_GEN: to generate the functionality for mode 1 and 2.
------------------------------
LOGIC_FOR_MD_12_GEN: if C_SPI_MODE /= 0 generate
---------------------------
signal SCK_O_int : std_logic;
signal MISO_I_int: std_logic;
signal Data_Dir_int : std_logic;
signal Data_Mode_1_int : std_logic;
signal Data_Mode_0_int : std_logic;
signal Data_Phase_int : std_logic;
signal Addr_Mode_1_int : std_logic;
signal Addr_Mode_0_int : std_logic;
signal Addr_Bit_int : std_logic;
signal Addr_Phase_int : std_logic;
signal CMD_Mode_1_int : std_logic;
signal CMD_Mode_0_int : std_logic;
signal CMD_Error_int : std_logic;
signal CMD_decoded_int : std_logic;
signal Dummy_Bits_int : std_logic_vector(3 downto 0);
-----
begin
-----
LOGIC_FOR_C_SPI_MODE_1_GEN: if C_SPI_MODE = 1 generate
-------
begin
-------
-- DATA_STARTUP_USED_MODE1 : if C_USE_STARTUP = 1 generate
-- -----
-- begin
-- -----
-- IO2_O <= do(2);
-- IO2_T <= dts(2);
-- IO3_O <= do(3);
-- IO3_T <= dts(3);
-- --IO2_I_int <= di(2);-- assign default value as this bit is not used in thid mode
-- IO2_I_int <= '0';-- assign default value as this bit is not used in thid mode
-- --IO3_I_int <= di(3);-- assign default value as this bit is not used in thid mode
-- IO3_I_int <= '0';-- assign default value as this bit is not used in thid mode
--end generate DATA_STARTUP_USED_MODE1;
--
--DATA_NOSTARTUP_USED_MODE1 : if C_USE_STARTUP = 0 generate
-- -----
-- begin
-- -----
IO2_O <= '0'; -- not used in the logic
IO3_O <= '0'; -- not used in the logic
IO2_T <= '1'; -- disable the tri-state buffers
IO3_T <= '1'; -- disable the tri-state buffers
IO2_I_int <= '0';-- assign default value as this bit is not used in thid mode
IO3_I_int <= '0';-- assign default value as this bit is not used in thid mode
--end generate DATA_NOSTARTUP_USED_MODE1;
end generate LOGIC_FOR_C_SPI_MODE_1_GEN;
---------------------------------------
LOGIC_FOR_C_SPI_MODE_2_GEN: if C_SPI_MODE = 2 generate
-------
begin
-------
DATA_STARTUP_USED_MODE2 : if (C_USE_STARTUP = 1 and C_UC_FAMILY = 1) generate
-----
begin
-----
di <= "00";
end generate DATA_STARTUP_USED_MODE2;
DATA_NOSTARTUP_USED_MODE2 : if (C_USE_STARTUP = 0 or (C_USE_STARTUP = 1 and C_UC_FAMILY = 0)) generate
-----
begin
-----
IO2_I_int <= IO2_I; -- assign this bit from the top level port
IO2_O <= IO2_O_int;
IO2_T <= IO2_T_int;
IO3_I_int <= IO3_I; -- assign this bit from the top level port
IO3_O <= IO3_O_int;
IO3_T <= IO3_T_int;
end generate DATA_NOSTARTUP_USED_MODE2;
end generate LOGIC_FOR_C_SPI_MODE_2_GEN;
---------------------------------------
SPISR_0_CMD_Error_int <= CMD_Error_int;
dtr_underrun_int <= '0'; -- SPI MODE 1 & 2 are master modes, so DTR under run wont be present
slave_MODF_strobe_int <= '0'; -- SPI MODE 1 & 2 are master modes, so the slave mode fault error wont appear
Mst_N_Slv_mode <= '1';
-------------------------------------------------------
-- SCK_O <= SCK_O_int; -- output from the core
-- MISO_I_int <= IO1_I; -- input to the core
-- *
-------------------------------------------------------
SCK_MISO_NO_STARTUP_USED: if C_USE_STARTUP = 0 generate
-----
begin
-----
SCK_O <= SCK_O_int; -- output from the core
MISO_I_int <= IO1_I; -- input to the core
end generate SCK_MISO_NO_STARTUP_USED;
-------------------------------------------------------
-------------------------------------------------------
SCK_MISO_STARTUP_USED: if C_USE_STARTUP = 1 generate
-----
begin
-----
QSPI_STARTUP_BLOCK_I: entity axi_quad_spi_v3_2_8.qspi_startup_block
---------------------
generic map
(
C_SUB_FAMILY => C_SUB_FAMILY , -- support for V6/V7/K7/A7 families only
-----------------
C_USE_STARTUP => C_USE_STARTUP,
-----------------
C_SHARED_STARTUP => C_SHARED_STARTUP,
-----------------
C_SPI_MODE => C_SPI_MODE
-----------------
)
port map
(
SCK_O => SCK_O_int, -- : in std_logic; -- input from the qspi_mode_0_module
IO1_I_startup => IO1_I, -- : in std_logic; -- input from the top level port list
IO1_Int => MISO_I_int,-- : out std_logic
Bus2IP_Clk => Bus2IP_Clk,
reset2ip_reset => reset2ip_reset_int,
CFGCLK => cfgclk, -- FGCLK , -- 1-bit output: Configuration main clock output
CFGMCLK => cfgmclk, -- FGMCLK , -- 1-bit output: Configuration internal oscillator clock output
EOS => eos, -- OS , -- 1-bit output: Active high output signal indicating the End Of Startup.
PREQ => preq, -- REQ , -- 1-bit output: PROGRAM request to fabric output
DI => di_int, -- output
DO => do_int, -- 4-bit input
DTS => dts_int, -- 4-bit input
FCSBO => fcsbo_int, -- 1-bit input
FCSBTS => fcsbts_int,-- 1-bit input
CLK => clk, -- 1-bit input, SetReset
GSR => gsr, -- 1-bit input, SetReset
GTS => gts, -- 1-bit input
KEYCLEARB => keyclearb, --1-bit input
PACK => pack, --1-bit input
USRCCLKTS => usrcclkts, -- SRCCLKTS , -- 1-bit input
USRDONEO => usrdoneo, -- SRDONEO , -- 1-bit input
USRDONETS => usrdonets -- SRDONETS -- 1-bit input
);
--------------------
end generate SCK_MISO_STARTUP_USED;
-------------------------------------------------------
-- *
-- Add instance for Look up table logic
SPI_MODE_1_LUT_LOGIC_I: entity axi_quad_spi_v3_2_8.qspi_look_up_logic
-------------
generic map
(
C_FAMILY => C_FAMILY ,
C_SPI_MODE => C_SPI_MODE ,
C_SPI_MEMORY => C_SPI_MEMORY ,
C_SELECT_XPM => C_SELECT_XPM ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS
)
port map
(
EXT_SPI_CLK => EXT_SPI_CLK , -- : in std_logic;
Rst_to_spi => Rst_to_spi_int , -- : in std_logic;
TXFIFO_RST => reset_TxFIFO_ptr_int_to_spi, -- : in std_logic;
-------------------- --
DTR_FIFO_Data_Exists=> data_Exists_TxFIFO_int, -- : in std_logic;
Data_From_TxFIFO => Data_From_TxFIFO , -- : in std_logic_vector
-- (0 to (C_NUM_TRANSFER_BITS-1))
pr_state_idle => pr_state_idle_int , --
-------------------- --
Data_Dir => Data_Dir_int , -- : out std_logic;
Data_Mode_1 => Data_Mode_1_int , -- : out std_logic;
Data_Mode_0 => Data_Mode_0_int , -- : out std_logic;
Data_Phase => Data_Phase_int , -- : out std_logic;
-------------------- --
Quad_Phase => Quad_Phase_int ,
-------------------- --
Addr_Mode_1 => Addr_Mode_1_int , -- : out std_logic;
Addr_Mode_0 => Addr_Mode_0_int , -- : out std_logic;
Addr_Bit => Addr_Bit_int , -- : out std_logic;
Addr_Phase => Addr_Phase_int , -- : out std_logic;
-------------------- --
CMD_Mode_1 => CMD_Mode_1_int , -- : out std_logic;
CMD_Mode_0 => CMD_Mode_0_int , -- : out std_logic;
CMD_Error => CMD_Error_int , -- : out std_logic;
-------------------- -- -
CMD_decoded => CMD_decoded_int -- : out std_logic
);
---------
SPI_MODE_CONTROL_LOGIC_I: entity axi_quad_spi_v3_2_8.qspi_mode_control_logic
-------------
generic map
(
C_SCK_RATIO => C_SCK_RATIO ,
C_NUM_TRANSFER_BITS => C_NUM_TRANSFER_BITS ,
C_SPI_MODE => C_SPI_MODE ,
C_USE_STARTUP => C_USE_STARTUP ,
C_NUM_SS_BITS => C_NUM_SS_BITS ,
C_SPI_MEMORY => C_SPI_MEMORY ,
C_SUB_FAMILY => C_SUB_FAMILY
)
port map
(
Bus2IP_Clk => EXT_SPI_CLK , -- Bus2IP_Clk , -- in std_logic;
Soft_Reset_op => Rst_to_spi_int , -- in std_logic;
-------------------- , --
DTR_FIFO_Data_Exists => data_Exists_TxFIFO_int , -- in std_logic;
Slave_Select_Reg => register_Data_slvsel_int , -- already updated -- in std_logic_vector(0 to (C_NUM_SS_BITS-1));
Transmit_Data => Data_From_TxFIFO,--transmit_Data_int , -- already updated -- in std_logic_vector(0 to (C_NUM_TRANSFER_BITS
Receive_Data => Data_To_Rx_FIFO , -- out std_logic_vector(0 to (C_NUM_TRANSFER_BITS
--Data_To_Rx_FIFO_1 => Data_To_Rx_FIFO_1,
SPIXfer_done => spiXfer_done_int , -- already updated -- out std_logic;
SPIXfer_done_Rx_Wr_en=> SPIXfer_done_Rx_Wr_en,
MODF_strobe => modf_strobe_int , -- already updated
SPIXfer_done_rd_tx_en=> SPIXfer_done_rd_tx_en,
--------------------- --
SR_3_MODF => SR_3_modf_to_spi_clk , -- in std_logic;
SR_5_Tx_Empty => Tx_FIFO_Empty , -- sr_5_Tx_Empty_int -- in std_logic;
--SR_6_Rx_Full => Rx_FIFO_Full , -- in
pr_state_idle => pr_state_idle_int , --
--------------------- -- from control register
SPICR_0_LOOP => SPICR_0_LOOP_to_spi_clk ,--SPICR_0_LOOP_int , -- in std_logic;
SPICR_1_SPE => SPICR_1_SPE_to_spi_clk ,--_int , -- in std_logic;
SPICR_2_MASTER_N_SLV => SPICR_2_MST_N_SLV_to_spi_clk,--_int , -- in std_logic;
SPICR_3_CPOL => SPICR_3_CPOL_to_spi_clk ,--_int , -- in std_logic;
SPICR_4_CPHA => SPICR_4_CPHA_to_spi_clk ,--_int , -- in std_logic;
SPICR_5_TXFIFO_RST => SPICR_5_TXFIFO_RST_to_spi_clk,--_int , -- in std_logic;
SPICR_6_RXFIFO_RST => SPICR_6_RXFIFO_RST_to_spi_clk,--_int , -- in std_logic;
SPICR_7_SS => SPICR_7_SS_to_spi_clk ,--_int , -- in std_logic;
SPICR_8_TR_INHIBIT => SPICR_8_TR_INHIBIT_to_spi_clk,--_int , -- in std_logic;
SPICR_9_LSB => SPICR_9_LSB_to_spi_clk ,--_int , -- in std_logic;
--------------------- --
--------------------- -- from look up table
Data_Dir => Data_Dir_int , -- in std_logic;
Data_Mode_1 => Data_Mode_1_int , -- in std_logic;
Data_Mode_0 => Data_Mode_0_int , -- in std_logic;
Data_Phase => Data_Phase_int ,
---------------------
--Dummy_Bits => Dummy_Bits_int , -- in std_logic_vector(3 downto 0);
Quad_Phase => Quad_Phase_int ,
--------------------- -- in std_logic;
Addr_Mode_1 => Addr_Mode_1_int , -- in std_logic;
Addr_Mode_0 => Addr_Mode_0_int , -- in std_logic;
Addr_Bit => Addr_Bit_int , -- in std_logic;
Addr_Phase => Addr_Phase_int , -- in std_logic;
---------------------
CMD_Mode_1 => CMD_Mode_1_int , -- in std_logic;
CMD_Mode_0 => CMD_Mode_0_int , -- in std_logic;
CMD_Error => CMD_Error_int , -- in std_logic;
--------------------- --
CMD_decoded => CMD_decoded_int , -- in std_logic;
--SPI Interface --
SCK_I => SCK_I, -- in std_logic;
SCK_O_reg => SCK_O_int, -- out std_logic;
SCK_T => SCK_T, -- out std_logic;
--
IO0_I => str_IO0_I, --IO0_I, -- MOSI_I, -- in std_logic; -- MISO
IO0_O => str_IO0_O,--IO0_O, -- MOSI_O, -- out std_logic;
IO0_T => str_IO0_T, --IO0_T, -- MOSI_T, -- out std_logic;
IO1_I => str_IO1_I,--MISO_I_int, -- IO1_I, -- MISO_I, -- in std_logic;
IO1_O => str_IO1_O,--IO1_O, -- MISO_O, -- out std_logic; -- MOSI
IO1_T => str_IO1_T,--IO1_T, -- MISO_T, -- out std_logic;
--
IO2_I => IO2_I_int, -- -- in std_logic;
IO2_O => IO2_O_int, -- -- out std_logic;
IO2_T => IO2_T_int, -- -- out std_logic;
--
IO3_I => IO3_I_int, -- -- in std_logic;
IO3_O => IO3_O_int, -- -- out std_logic;
IO3_T => IO3_T_int, -- -- out std_logic;
--
SPISEL => SPISEL, -- in std_logic;
--
SS_I => SS_I_int, -- in std_logic_vector(0 to (C_NUM_SS_BITS-1));
SS_O => SS_O_int, -- out std_logic_vector(0 to (C_NUM_SS_BITS-1));
SS_T => SS_T_int, -- out std_logic;
--
SPISEL_pulse_op => spisel_pulse_o_int , -- out std_logic;
SPISEL_d1_reg => spisel_d1_reg , -- out std_logic;
Control_bit_7_8 => SPICR_bits_7_8_to_spi_clk , -- in std_logic_vector(0 to 1) --(7 to 8)
Rx_FIFO_Full => Rx_FIFO_Full_Fifo,
DRR_Overrun_reg => drr_Overrun_int,
reset_RcFIFO_ptr_to_spi => reset_RcFIFO_ptr_to_spi_clk
);
-------------
end generate LOGIC_FOR_MD_12_GEN;
------------------------------------------
--------------------------------------------------------------------------------
CONTROL_REG_I: entity axi_quad_spi_v3_2_8.qspi_cntrl_reg
generic map
(
--------------------------
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
--------------------------
-- Number of bits in regis
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG,
--------------------------
C_SPICR_REG_WIDTH => C_SPICR_REG_WIDTH,
--------------------------
C_SPI_MODE => C_SPI_MODE
--------------------------
)
port map
( -- in
Bus2IP_Clk => Bus2IP_Clk, -- in
Soft_Reset_op => reset2ip_reset_int,
---------------------------
Wr_ce_reduce_ack_gen => Wr_ce_reduce_ack_gen, -- in
Bus2IP_SPICR_WrCE => Bus2IP_WrCE(SPICR), -- in
Bus2IP_SPICR_RdCE => Bus2IP_RdCE(SPICR), -- in
Bus2IP_SPICR_data => Bus2IP_Data, -- in vec
---------------------------
SPICR_0_LOOP => SPICR_0_LOOP_frm_axi_clk, -- out
SPICR_1_SPE => SPICR_1_SPE_frm_axi_clk, -- out
SPICR_2_MASTER_N_SLV => SPICR_2_MST_N_SLV_frm_axi_clk, -- out
SPICR_3_CPOL => SPICR_3_CPOL_frm_axi_clk, -- out
SPICR_4_CPHA => SPICR_4_CPHA_frm_axi_clk, -- out
SPICR_5_TXFIFO_RST => SPICR_5_TXFIFO_RST_frm_axi_clk, -- out
SPICR_6_RXFIFO_RST => SPICR_6_RXFIFO_RST_frm_axi_clk, -- out
SPICR_7_SS => SPICR_7_SS_frm_axi_clk, -- out
SPICR_8_TR_INHIBIT => SPICR_8_TR_INHIBIT_frm_axi_clk, -- out
SPICR_9_LSB => SPICR_9_LSB_frm_axi_clk, -- out
-- to Status Register
SPISR_1_LOOP_Back_Error => SPISR_1_LOOP_Back_Error_int, -- out
SPISR_2_MSB_Error => SPISR_2_MSB_Error_int, -- out
SPISR_3_Slave_Mode_Error => SPISR_3_Slave_Mode_Error_int, -- out
SPISR_4_CPOL_CPHA_Error => SPISR_4_CPOL_CPHA_Error_int, -- out
---------------------------
IP2Bus_SPICR_Data => IP2Bus_SPICR_Data_int, -- out vec
---------------------------
Control_bit_7_8 => SPICR_bits_7_8_frm_axi_clk -- out vec
---------------------------
);
-------------------------------------------------------------------------------
-- STATUS_REG_I : INSTANTIATE STATUS REGISTER
-------------------------------------------------------------------------------
STATUS_REG_MODE_0_GEN: if C_SPI_MODE = 0 generate
begin
STATUS_SLAVE_SEL_REG_I: entity axi_quad_spi_v3_2_8.qspi_status_slave_sel_reg
generic map(
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG ,
------------------------ ------------------------
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
------------------------ ------------------------
C_NUM_SS_BITS => C_NUM_SS_BITS ,
------------------------ ------------------------
C_SPISR_REG_WIDTH => C_SPISR_REG_WIDTH
)
port map(
Bus2IP_Clk => Bus2IP_Clk , -- in
Soft_Reset_op => reset2ip_reset_int , -- in
-- I/P from control regis
SPISR_0_Command_Error => '0' , -- SPISR_0_CMD_Error_int , -- in-- should come from look up table
SPISR_1_LOOP_Back_Error => SPISR_1_LOOP_Back_Error_int , -- in
SPISR_2_MSB_Error => SPISR_2_MSB_Error_int , -- in
SPISR_3_Slave_Mode_Error => SPISR_3_Slave_Mode_Error_int , -- in
SPISR_4_CPOL_CPHA_Error => SPISR_4_CPOL_CPHA_Error_int , -- in
-- I/P from other modules
SPISR_Ext_SPISEL_slave => spisel_d1_reg_to_axi_clk , -- in
SPISR_7_Tx_Full => Tx_FIFO_Full_int , -- in
SPISR_8_Tx_Empty => Tx_FIFO_Empty_SPISR_to_axi_clk, -- Tx_FIFO_Empty_to_Axi_clk , -- in
--SPISR_9_Rx_Full => Rx_FIFO_Full_int, -- Rx_FIFO_Full_to_axi_clk , -- in
SPISR_9_Rx_Full => Rx_FIFO_Full_Fifo_d1_synced, -- Rx_FIFO_Full_to_axi_clk , -- in
SPISR_10_Rx_Empty => Rx_FIFO_Empty_int , -- in
-- Slave attachment ports
ModeFault_Strobe => modf_strobe_to_axi_clk , -- in
Rd_ce_reduce_ack_gen => rd_ce_reduce_ack_gen , -- in
Bus2IP_SPISR_RdCE => Bus2IP_RdCE(SPISR) , -- in
IP2Bus_SPISR_Data => IP2Bus_SPISR_Data_int , -- out vec
SR_3_modf => SR_3_modf_int , -- out
-- Slave Select Register
Bus2IP_SPISSR_WrCE => Bus2IP_WrCE(SPISSR) , -- in
Wr_ce_reduce_ack_gen => Wr_ce_reduce_ack_gen , -- in
Bus2IP_SPISSR_RdCE => Bus2IP_RdCE(SPISSR) , -- in
Bus2IP_SPISSR_Data => Bus2IP_Data , -- in vec
IP2Bus_SPISSR_Data => IP2Bus_SPISSR_Data_int , -- out vec
SPISSR_Data_reg_op => SPISSR_frm_axi_clk -- out vec
);
end generate STATUS_REG_MODE_0_GEN;
STATUS_REG_MODE_12_GEN: if C_SPI_MODE /= 0 generate
begin
STATUS_SLAVE_SEL_REG_I: entity axi_quad_spi_v3_2_8.qspi_status_slave_sel_reg
generic map(
C_SPI_NUM_BITS_REG => C_SPI_NUM_BITS_REG ,
------------------------ ------------------------
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
------------------------ ------------------------
C_NUM_SS_BITS => C_NUM_SS_BITS ,
------------------------ ------------------------
C_SPISR_REG_WIDTH => C_SPISR_REG_WIDTH
)
port map(
Bus2IP_Clk => Bus2IP_Clk , -- in
Soft_Reset_op => reset2ip_reset_int , -- in
-- I/P from control regis
SPISR_0_Command_Error => SPISR_0_CMD_Error_to_axi_clk , -- SPISR_0_CMD_Error_int , -- in-- should come from look up table
SPISR_1_LOOP_Back_Error => SPISR_1_LOOP_Back_Error_int , -- in
SPISR_2_MSB_Error => SPISR_2_MSB_Error_int , -- in
SPISR_3_Slave_Mode_Error => SPISR_3_Slave_Mode_Error_int , -- in
SPISR_4_CPOL_CPHA_Error => SPISR_4_CPOL_CPHA_Error_int , -- in
-- I/P from other modules
SPISR_Ext_SPISEL_slave => spisel_d1_reg_to_axi_clk , -- in
SPISR_7_Tx_Full => Tx_FIFO_Full_int , -- in
SPISR_8_Tx_Empty => Tx_FIFO_Empty_SPISR_to_axi_clk, -- Tx_FIFO_Empty_to_Axi_clk , -- in
--SPISR_9_Rx_Full => Rx_FIFO_Full_int, -- Rx_FIFO_Full_to_axi_clk , -- in
SPISR_9_Rx_Full => Rx_FIFO_Full_Fifo_d1_synced, -- Rx_FIFO_Full_to_axi_clk , -- in
SPISR_10_Rx_Empty => Rx_FIFO_Empty_int , -- in
-- Slave attachment ports
ModeFault_Strobe => modf_strobe_to_axi_clk , -- in
Rd_ce_reduce_ack_gen => rd_ce_reduce_ack_gen , -- in
Bus2IP_SPISR_RdCE => Bus2IP_RdCE(SPISR) , -- in
IP2Bus_SPISR_Data => IP2Bus_SPISR_Data_int , -- out vec
SR_3_modf => SR_3_modf_int , -- out
-- Slave Select Register
Bus2IP_SPISSR_WrCE => Bus2IP_WrCE(SPISSR) , -- in
Wr_ce_reduce_ack_gen => Wr_ce_reduce_ack_gen , -- in
Bus2IP_SPISSR_RdCE => Bus2IP_RdCE(SPISSR) , -- in
Bus2IP_SPISSR_Data => Bus2IP_Data , -- in vec
IP2Bus_SPISSR_Data => IP2Bus_SPISSR_Data_int , -- out vec
SPISSR_Data_reg_op => SPISSR_frm_axi_clk -- out vec
);
end generate STATUS_REG_MODE_12_GEN;
-------------------------------------------------------------------------------
-- SOFT_RESET_I : INSTANTIATE SOFT RESET
-------------------------------------------------------------------------------
SOFT_RESET_I: entity axi_quad_spi_v3_2_8.soft_reset
generic map
(
C_SIPIF_DWIDTH => C_S_AXI_DATA_WIDTH,
-- Width of triggered reset in Bus Clocks
C_RESET_WIDTH => 16
)
port map
(
-- Inputs From the PLBv46 Slave Single Bus
Bus2IP_Clk => Bus2IP_Clk, -- in
Bus2IP_Reset => Bus2IP_Reset, -- in
Bus2IP_WrCE => Bus2IP_WrCE(SWRESET), -- in
Bus2IP_Data => Bus2IP_Data, -- in
Bus2IP_BE => Bus2IP_BE, -- in
-- Final Device Reset Output
Reset2IP_Reset => reset2ip_reset_int, -- out
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck => rst_ip2bus_wrack, -- out
Reset2Bus_Error => rst_ip2bus_error, -- out
Reset2Bus_ToutSup => open -- out
);
-------------------------------------------------------------------------------
-- INTERRUPT_CONTROL_I : INSTANTIATE INTERRUPT CONTROLLER
-------------------------------------------------------------------------------
bus2ip_intr_rdce <= "0000000" &
Bus2IP_RdCE(7) &
Bus2IP_RdCE(8) &
'0' &
Bus2IP_RdCE(10)&
"00000";
bus2ip_intr_wrce <= "0000000" &
Bus2IP_WrCE(7) &
Bus2IP_WrCE(8) &
'0' &
Bus2IP_WrCE(10)&
"00000";
------------------------------------------------------------------------------
intr_controller_rd_ce_or_reduce <= or_reduce(Bus2IP_RdCE(0 to 6)) or
Bus2IP_RdCE(9) or
or_reduce(Bus2IP_RdCE(11 to 15));
------------------------------------------------------------------------------
I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_RdAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_RdAck_intr_reg_hole_d1 <= intr_controller_rd_ce_or_reduce;
ip2Bus_RdAck_intr_reg_hole <= intr_controller_rd_ce_or_reduce and
(not ip2Bus_RdAck_intr_reg_hole_d1);
end if;
end if;
end process I_READ_ACK_INTR_HOLES;
------------------------------------------------------------------------------
intr_controller_wr_ce_or_reduce <= or_reduce(Bus2IP_WrCE(0 to 6)) or
Bus2IP_WrCE(9) or
or_reduce(Bus2IP_WrCE(11 to 15));
------------------------------------------------------------------------------
I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset_int = RESET_ACTIVE) then
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_WrAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_WrAck_intr_reg_hole_d1 <= intr_controller_wr_ce_or_reduce;
ip2Bus_WrAck_intr_reg_hole <= intr_controller_wr_ce_or_reduce and
(not ip2Bus_WrAck_intr_reg_hole_d1);
end if;
end if;
end process I_WRITE_ACK_INTR_HOLES;
------------------------------------------------------------------------------
INTERRUPT_CONTROL_I: entity interrupt_control_v3_1_4.interrupt_control
generic map
(
C_NUM_CE => 16,
C_NUM_IPIF_IRPT_SRC => 1, -- Set to 1 to avoid null array
C_IP_INTR_MODE_ARRAY => C_IP_INTR_MODE_ARRAY,
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_PENCODER => false,
-- Specifies device ISC hierarchy
C_INCLUDE_DEV_ISC => false,
C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH
)
port map
(
Bus2IP_Clk => Bus2IP_Clk, -- in
Bus2IP_Reset => reset2ip_reset_int, -- in
Bus2IP_Data => bus2IP_Data_for_interrupt_core, -- in vec
Bus2IP_BE => Bus2IP_BE, -- in vec
Interrupt_RdCE => bus2ip_intr_rdce, -- in vec
Interrupt_WrCE => bus2ip_intr_wrce, -- in vec
IPIF_Reg_Interrupts => "00", -- Tie off the unused reg intrs
IPIF_Lvl_Interrupts => "0", -- Tie off the dummy lvl intr
IP2Bus_IntrEvent => ip2Bus_IntrEvent_int, -- in
Intr2Bus_DevIntr => IP2INTC_Irpt, -- out
Intr2Bus_DBus => intr_ip2bus_data, -- out vec
Intr2Bus_WrAck => intr_ip2bus_wrack, -- out
Intr2Bus_RdAck => intr_ip2bus_rdack, -- out
Intr2Bus_Error => intr_ip2bus_error, -- out
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
--------------------------------------------------------------------------------
end imp;
--------------------------------------------------------------------------------
|
library IEEE;
use IEEE.std_logic_1164.all;
entity bcd_2_adder is
port (
Carry_in : in std_logic;
Carry_out : out std_logic;
Adig0: in STD_LOGIC_VECTOR (3 downto 0);
Adig1: in STD_LOGIC_VECTOR (3 downto 0);
Bdig0: in STD_LOGIC_VECTOR (3 downto 0);
Bdig1: in STD_LOGIC_VECTOR (3 downto 0);
Sdig0: out STD_LOGIC_VECTOR (3 downto 0);
Sdig1: out STD_LOGIC_VECTOR (3 downto 0)
);
end bcd_2_adder;
architecture bcd_2_adder_arch of bcd_2_adder is
COMPONENT bcd_1_adder port (
A: in STD_LOGIC_VECTOR (3 downto 0);
B: in STD_LOGIC_VECTOR (3 downto 0);
C_IN: in STD_LOGIC;
SUM: out STD_LOGIC_VECTOR (3 downto 0);
C_OUT: out STD_LOGIC
);
end component;
signal C_out1 : std_logic := '0';
BEGIN
u1: bcd_1_adder PORT MAP(Adig0, Bdig0, Carry_in, Sdig0, C_out1);
u2: bcd_1_adder PORT MAP(Adig1, Bdig1, C_out1, Sdig1, Carry_out);
end bcd_2_adder_arch;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity bcd_2_adder is
port (
Carry_in : in std_logic;
Carry_out : out std_logic;
Adig0: in STD_LOGIC_VECTOR (3 downto 0);
Adig1: in STD_LOGIC_VECTOR (3 downto 0);
Bdig0: in STD_LOGIC_VECTOR (3 downto 0);
Bdig1: in STD_LOGIC_VECTOR (3 downto 0);
Sdig0: out STD_LOGIC_VECTOR (3 downto 0);
Sdig1: out STD_LOGIC_VECTOR (3 downto 0)
);
end bcd_2_adder;
architecture bcd_2_adder_arch of bcd_2_adder is
COMPONENT bcd_1_adder port (
A: in STD_LOGIC_VECTOR (3 downto 0);
B: in STD_LOGIC_VECTOR (3 downto 0);
C_IN: in STD_LOGIC;
SUM: out STD_LOGIC_VECTOR (3 downto 0);
C_OUT: out STD_LOGIC
);
end component;
signal C_out1 : std_logic := '0';
BEGIN
u1: bcd_1_adder PORT MAP(Adig0, Bdig0, Carry_in, Sdig0, C_out1);
u2: bcd_1_adder PORT MAP(Adig1, Bdig1, C_out1, Sdig1, Carry_out);
end bcd_2_adder_arch;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/TWDLMULT_SDNF1_3_block.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLMULT_SDNF1_3_block
-- Source Path: ifft_16_bit/IFFT HDL Optimized/TWDLMULT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TWDLMULT_SDNF1_3_block IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
dout_5_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_5_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_7_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_7_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_2_vld : IN std_logic;
twdl_3_3_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_3_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_4_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_4_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_4_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_3_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_3_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_4_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_4_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_3_vld : OUT std_logic
);
END TWDLMULT_SDNF1_3_block;
ARCHITECTURE rtl OF TWDLMULT_SDNF1_3_block IS
-- Component Declarations
COMPONENT Complex3Multiply_block
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
din1_re_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
din1_im_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
din1_vld_dly3 : IN std_logic;
twdl_3_3_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_3_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
softReset : IN std_logic;
twdlXdin_3_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_3_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin1_vld : OUT std_logic
);
END COMPONENT;
COMPONENT Complex3Multiply_block1
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
din2_re_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
din2_im_dly3 : IN std_logic_vector(16 DOWNTO 0); -- sfix17
di2_vld_dly3 : IN std_logic;
twdl_3_4_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_4_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17_En15
softReset : IN std_logic;
twdlXdin_4_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_4_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin2_vld : OUT std_logic
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : Complex3Multiply_block
USE ENTITY work.Complex3Multiply_block(rtl);
FOR ALL : Complex3Multiply_block1
USE ENTITY work.Complex3Multiply_block1(rtl);
-- Signals
SIGNAL dout_5_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_re_dly1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_re_dly2 : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_5_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_im_dly1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_im_dly2 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_re_dly3 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_im_dly3 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din1_vld_dly1 : std_logic;
SIGNAL din1_vld_dly2 : std_logic;
SIGNAL din1_vld_dly3 : std_logic;
SIGNAL twdlXdin_3_re_tmp : std_logic_vector(16 DOWNTO 0); -- ufix17
SIGNAL twdlXdin_3_im_tmp : std_logic_vector(16 DOWNTO 0); -- ufix17
SIGNAL twdlXdin1_vld : std_logic;
SIGNAL dout_7_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_re_dly1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_re_dly2 : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_7_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_im_dly1 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_im_dly2 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_re_dly3 : signed(16 DOWNTO 0); -- sfix17
SIGNAL din2_im_dly3 : signed(16 DOWNTO 0); -- sfix17
SIGNAL di2_vld_dly1 : std_logic;
SIGNAL di2_vld_dly2 : std_logic;
SIGNAL di2_vld_dly3 : std_logic;
SIGNAL twdlXdin_4_re_tmp : std_logic_vector(16 DOWNTO 0); -- ufix17
SIGNAL twdlXdin_4_im_tmp : std_logic_vector(16 DOWNTO 0); -- ufix17
BEGIN
u_MUL3_1 : Complex3Multiply_block
PORT MAP( clk => clk,
reset => reset,
enb => enb,
din1_re_dly3 => std_logic_vector(din1_re_dly3), -- sfix17
din1_im_dly3 => std_logic_vector(din1_im_dly3), -- sfix17
din1_vld_dly3 => din1_vld_dly3,
twdl_3_3_re => twdl_3_3_re, -- sfix17_En15
twdl_3_3_im => twdl_3_3_im, -- sfix17_En15
softReset => softReset,
twdlXdin_3_re => twdlXdin_3_re_tmp, -- sfix17
twdlXdin_3_im => twdlXdin_3_im_tmp, -- sfix17
twdlXdin1_vld => twdlXdin1_vld
);
u_MUL3_2 : Complex3Multiply_block1
PORT MAP( clk => clk,
reset => reset,
enb => enb,
din2_re_dly3 => std_logic_vector(din2_re_dly3), -- sfix17
din2_im_dly3 => std_logic_vector(din2_im_dly3), -- sfix17
di2_vld_dly3 => di2_vld_dly3,
twdl_3_4_re => twdl_3_4_re, -- sfix17_En15
twdl_3_4_im => twdl_3_4_im, -- sfix17_En15
softReset => softReset,
twdlXdin_4_re => twdlXdin_4_re_tmp, -- sfix17
twdlXdin_4_im => twdlXdin_4_im_tmp, -- sfix17
twdlXdin2_vld => twdlXdin_3_vld
);
dout_5_re_signed <= signed(dout_5_re);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly1 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly1 <= dout_5_re_signed;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly2 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly2 <= din1_re_dly1;
END IF;
END IF;
END PROCESS intdelay_1_process;
dout_5_im_signed <= signed(dout_5_im);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly1 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly1 <= dout_5_im_signed;
END IF;
END IF;
END PROCESS intdelay_2_process;
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly2 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly2 <= din1_im_dly1;
END IF;
END IF;
END PROCESS intdelay_3_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly3 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_re_dly3 <= din1_re_dly2;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly3 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_im_dly3 <= din1_im_dly2;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_vld_dly1 <= dout_2_vld;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_vld_dly2 <= din1_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_7_process;
intdelay_8_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din1_vld_dly3 <= din1_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_8_process;
dout_7_re_signed <= signed(dout_7_re);
intdelay_9_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly1 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_re_dly1 <= dout_7_re_signed;
END IF;
END IF;
END PROCESS intdelay_9_process;
intdelay_10_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly2 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_re_dly2 <= din2_re_dly1;
END IF;
END IF;
END PROCESS intdelay_10_process;
dout_7_im_signed <= signed(dout_7_im);
intdelay_11_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly1 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_im_dly1 <= dout_7_im_signed;
END IF;
END IF;
END PROCESS intdelay_11_process;
intdelay_12_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly2 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_im_dly2 <= din2_im_dly1;
END IF;
END IF;
END PROCESS intdelay_12_process;
intdelay_13_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly3 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_re_dly3 <= din2_re_dly2;
END IF;
END IF;
END PROCESS intdelay_13_process;
intdelay_14_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly3 <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
din2_im_dly3 <= din2_im_dly2;
END IF;
END IF;
END PROCESS intdelay_14_process;
intdelay_15_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
di2_vld_dly1 <= dout_2_vld;
END IF;
END IF;
END PROCESS intdelay_15_process;
intdelay_16_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
di2_vld_dly2 <= di2_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_16_process;
intdelay_17_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
di2_vld_dly3 <= di2_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_17_process;
twdlXdin_3_re <= twdlXdin_3_re_tmp;
twdlXdin_3_im <= twdlXdin_3_im_tmp;
twdlXdin_4_re <= twdlXdin_4_re_tmp;
twdlXdin_4_im <= twdlXdin_4_im_tmp;
END rtl;
|
--------------------------------------------------------------------------
-- SOME VHDL DATA TYPES TO FACILITATE SYNTHESIS
-- Developed on Nov 1, 1991 by :
-- Indraneel Ghosh,
-- CADLAB,
-- Univ. of Calif. , Irvine.
--------------------------------------------------------------------------
use work.TYPES.all;
package SYNTHESIS_TYPES is
subtype clock is MVL7;
type Memory is array (integer range <>) of MVL7_vector(3 downto 0);
type Memory_12_bit is array (integer range <>) of MVL7_vector(11 downto 0);
end SYNTHESIS_TYPES; |
--------------------------------------------------------------------------
-- SOME VHDL DATA TYPES TO FACILITATE SYNTHESIS
-- Developed on Nov 1, 1991 by :
-- Indraneel Ghosh,
-- CADLAB,
-- Univ. of Calif. , Irvine.
--------------------------------------------------------------------------
use work.TYPES.all;
package SYNTHESIS_TYPES is
subtype clock is MVL7;
type Memory is array (integer range <>) of MVL7_vector(3 downto 0);
type Memory_12_bit is array (integer range <>) of MVL7_vector(11 downto 0);
end SYNTHESIS_TYPES; |
--------------------------------------------------------------------------
-- SOME VHDL DATA TYPES TO FACILITATE SYNTHESIS
-- Developed on Nov 1, 1991 by :
-- Indraneel Ghosh,
-- CADLAB,
-- Univ. of Calif. , Irvine.
--------------------------------------------------------------------------
use work.TYPES.all;
package SYNTHESIS_TYPES is
subtype clock is MVL7;
type Memory is array (integer range <>) of MVL7_vector(3 downto 0);
type Memory_12_bit is array (integer range <>) of MVL7_vector(11 downto 0);
end SYNTHESIS_TYPES; |
--------------------------------------------------------------------------
-- SOME VHDL DATA TYPES TO FACILITATE SYNTHESIS
-- Developed on Nov 1, 1991 by :
-- Indraneel Ghosh,
-- CADLAB,
-- Univ. of Calif. , Irvine.
--------------------------------------------------------------------------
use work.TYPES.all;
package SYNTHESIS_TYPES is
subtype clock is MVL7;
type Memory is array (integer range <>) of MVL7_vector(3 downto 0);
type Memory_12_bit is array (integer range <>) of MVL7_vector(11 downto 0);
end SYNTHESIS_TYPES; |
--------------------------------------------------------------------------
-- SOME VHDL DATA TYPES TO FACILITATE SYNTHESIS
-- Developed on Nov 1, 1991 by :
-- Indraneel Ghosh,
-- CADLAB,
-- Univ. of Calif. , Irvine.
--------------------------------------------------------------------------
use work.TYPES.all;
package SYNTHESIS_TYPES is
subtype clock is MVL7;
type Memory is array (integer range <>) of MVL7_vector(3 downto 0);
type Memory_12_bit is array (integer range <>) of MVL7_vector(11 downto 0);
end SYNTHESIS_TYPES; |
--------------------------------------------------------------------------
-- SOME VHDL DATA TYPES TO FACILITATE SYNTHESIS
-- Developed on Nov 1, 1991 by :
-- Indraneel Ghosh,
-- CADLAB,
-- Univ. of Calif. , Irvine.
--------------------------------------------------------------------------
use work.TYPES.all;
package SYNTHESIS_TYPES is
subtype clock is MVL7;
type Memory is array (integer range <>) of MVL7_vector(3 downto 0);
type Memory_12_bit is array (integer range <>) of MVL7_vector(11 downto 0);
end SYNTHESIS_TYPES; |
library accum;
use accum.OneHotAccum.all;
library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity mram_tb is
end mram_tb;
architecture TB_ARCHITECTURE of mram_tb is
-- Component declaration of the tested unit
component mram
port(
CLK : in STD_LOGIC;
RW : in STD_LOGIC;
ADDR : in mem_addr;
DIN : in operand;
DOUT : out operand );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal CLK : STD_LOGIC;
signal RW : STD_LOGIC;
signal ADDR : mem_addr;
signal DIN : operand;
-- Observed signals - signals mapped to the output ports of tested entity
signal DOUT : operand;
-- Add your code here ...
constant CLK_period: time := 10 ns;
begin
-- Unit Under Test port map
UUT : mram
port map (
CLK => CLK,
RW => RW,
ADDR => ADDR,
DIN => DIN,
DOUT => DOUT
);
CLK_Process: process
begin
CLK <= '0';
wait for CLK_Period/2;
CLK <= '1';
wait for CLK_Period/2;
end process;
main: process
begin
wait for 1 * CLK_PERIOD;
addr <= "00010";
din <= "0000000000000100";
wait for 1 * CLK_PERIOD;
addr <= "00001";
rw <= '1';
wait for 1 * CLK_PERIOD;
addr <= "00000";
din <= "0000000000010000";
rw <= '0';
wait for 1 * CLK_PERIOD;
wait for 100 * CLK_PERIOD;
wait;
end process;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_mram of mram_tb is
for TB_ARCHITECTURE
for UUT : mram
use entity work.mram(beh);
end for;
end for;
end TESTBENCH_FOR_mram;
|
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- This is an iterative implementation of the NOEKEON block
-- cipher relying on the direct mode of the cipher. This means that
-- key schedule is not performed.
entity noekeon is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end noekeon;
architecture Behavioral of noekeon is
component round_f is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic;
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component rc_gen is
port(clk : in std_logic;
rst : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
rc_out : out std_logic_vector(7 downto 0));
end component;
component output_trans is
port(clk : in std_logic;
enc : in std_logic; -- (enc, 0) / (dec, 1)
rc_in : in std_logic_vector(31 downto 0);
a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component theta is
port(a_0_in : in std_logic_vector(31 downto 0);
a_1_in : in std_logic_vector(31 downto 0);
a_2_in : in std_logic_vector(31 downto 0);
a_3_in : in std_logic_vector(31 downto 0);
k_0_in : in std_logic_vector(31 downto 0);
k_1_in : in std_logic_vector(31 downto 0);
k_2_in : in std_logic_vector(31 downto 0);
k_3_in : in std_logic_vector(31 downto 0);
a_0_out : out std_logic_vector(31 downto 0);
a_1_out : out std_logic_vector(31 downto 0);
a_2_out : out std_logic_vector(31 downto 0);
a_3_out : out std_logic_vector(31 downto 0));
end component;
component rc_shr is
port(clk : in std_logic;
rst : in std_logic;
rc_in : in std_logic_vector(407 downto 0);
rc_out : out std_logic_vector(7 downto 0));
end component;
signal rc_s : std_logic_vector(7 downto 0);
signal rc_ext_s : std_logic_vector(31 downto 0);
signal a_0_in_s : std_logic_vector(31 downto 0);
signal a_1_in_s : std_logic_vector(31 downto 0);
signal a_2_in_s : std_logic_vector(31 downto 0);
signal a_3_in_s : std_logic_vector(31 downto 0);
signal out_t_a_0_in_s : std_logic_vector(31 downto 0);
signal out_t_a_1_in_s : std_logic_vector(31 downto 0);
signal out_t_a_2_in_s : std_logic_vector(31 downto 0);
signal out_t_a_3_in_s : std_logic_vector(31 downto 0);
signal a_0_out_s : std_logic_vector(31 downto 0);
signal a_1_out_s : std_logic_vector(31 downto 0);
signal a_2_out_s : std_logic_vector(31 downto 0);
signal a_3_out_s : std_logic_vector(31 downto 0);
signal k_0_d_s : std_logic_vector(31 downto 0);
signal k_1_d_s : std_logic_vector(31 downto 0);
signal k_2_d_s : std_logic_vector(31 downto 0);
signal k_3_d_s : std_logic_vector(31 downto 0);
signal k_0_mux_s : std_logic_vector(31 downto 0);
signal k_1_mux_s : std_logic_vector(31 downto 0);
signal k_2_mux_s : std_logic_vector(31 downto 0);
signal k_3_mux_s : std_logic_vector(31 downto 0);
signal rc_in_s : std_logic_vector(407 downto 0);
begin
-- rc_in_s <= X"80 1b 36 6c d8 ab 4d 9a 2f 5e bc 63 c6 97 35 6a d4";
-- rc_in_s <= X"80801b1b36366c6cd8d8abab4d4d9a9a2f2f5e5ebcbc6363c6c6979735356a6ad4d4";
rc_in_s <= X"8080801b1b1b3636366c6c6cd8d8d8ababab4d4d4d9a9a9a2f2f2f5e5e5ebcbcbc636363c6c6c69797973535356a6a6ad4d4d4";
--00000000000000000000000000000000000000000000";
--RC_GEN_0 : rc_gen port map (clk, rst, enc, rc_s);
RC_SHR_0: rc_shr port map (clk, rst, rc_in_s, rc_s);
rc_ext_s <= X"000000" & rc_s;
ROUND_F_0 : round_f port map (clk,
rst,
enc,
rc_ext_s,
a_0_in_s,
a_1_in_s,
a_2_in_s,
a_3_in_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
a_0_out_s,
a_1_out_s,
a_2_out_s,
a_3_out_s);
pr_noe: process(clk, rst, enc)
begin
if rising_edge(clk) then
if rst = '1' then
a_0_in_s <= a_0_in;
a_1_in_s <= a_1_in;
a_2_in_s <= a_2_in;
a_3_in_s <= a_3_in;
else
a_0_in_s <= a_0_out_s;
a_1_in_s <= a_1_out_s;
a_2_in_s <= a_2_out_s;
a_3_in_s <= a_3_out_s;
end if;
end if;
end process;
-- Key decryption as k' = theta(0, k)
-- This is the key required for decryption
-- in NOEKEON
THETA_DECRYPT_0 : theta port map (
k_0_in,
k_1_in,
k_2_in,
k_3_in,
(others => '0'),
(others => '0'),
(others => '0'),
(others => '0'),
k_0_d_s,
k_1_d_s,
k_2_d_s,
k_3_d_s);
-- These multiplexers select the key that is used
-- in each mode i.e. during decryption the key generated
-- as k' = theta(0, k) (THETA_DECRYPT_0) is utilized.
k_0_mux_s <= k_0_in when enc = '0' else k_0_d_s;
k_1_mux_s <= k_1_in when enc = '0' else k_1_d_s;
k_2_mux_s <= k_2_in when enc = '0' else k_2_d_s;
k_3_mux_s <= k_3_in when enc = '0' else k_3_d_s;
out_trans_pr: process(clk, rst, a_0_out_s, a_1_out_s, a_2_out_s, a_3_out_s)
begin
if rising_edge(clk) then
out_t_a_0_in_s <= a_0_out_s;
out_t_a_1_in_s <= a_1_out_s;
out_t_a_2_in_s <= a_2_out_s;
out_t_a_3_in_s <= a_3_out_s;
end if;
end process;
-- This component performs the last operation
-- with theta.
OUT_TRANS_0 : output_trans port map (clk, enc, rc_ext_s,
out_t_a_0_in_s,
out_t_a_1_in_s,
out_t_a_2_in_s,
out_t_a_3_in_s,
k_0_mux_s,
k_1_mux_s,
k_2_mux_s,
k_3_mux_s,
a_0_out,
a_1_out,
a_2_out,
a_3_out);
end Behavioral;
|
--
-- Counter testbench
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
library FPGALIB;
use FPGALIB.Numeric.all;
use FPGALIB.Simul.all;
entity Counter_tb is
end entity Counter_tb;
architecture TestBench of Counter_tb is
constant DEPTH : positive:=5;
signal stop : boolean;
signal clk, rst : std_logic;
signal ena, last : std_logic;
signal count : std_logic_vector(clog2(DEPTH)-1 downto 0);
begin
clock_i : Clock
generic map(FREQUENCY => 2)
port map(clk_o => clk, rst_o => rst, stop_i => stop);
counter_i: counter
generic map (
DEPTH => DEPTH
)
port map (
clk_i => clk,
rst_i => rst,
ena_i => ena,
count_o => count,
last_o => last
);
test_p : process
begin
ena <= '0';
print("* Start of Test (DEPTH=5)");
wait until rising_edge(clk) and rst = '0';
assert count="000" report "Counter value is not 0" severity failure;
assert last='0' report "Wrong last value indication" severity failure;
print("Ena 1");
ena <= '1';
wait until rising_edge(clk);
print("Ena 2");
ena <= '1';
assert count="000" report "Counter value is not 0" severity failure;
assert last='0' report "Wrong last value indication" severity failure;
wait until rising_edge(clk);
assert count="001" report "Counter value is not 1" severity failure;
assert last='0' report "Wrong last value indication" severity failure;
ena <= '0';
wait until rising_edge(clk);
print("Ena 3");
ena <= '1';
wait until rising_edge(clk);
assert count="010" report "Counter value is not 2" severity failure;
assert last='0' report "Wrong last value indication" severity failure;
ena <= '0';
wait until rising_edge(clk);
print("Ena 4");
ena <= '1';
wait until rising_edge(clk);
assert count="011" report "Counter value is not 3" severity failure;
assert last='0' report "Wrong last value indication" severity failure;
print("Ena 5");
ena <= '1';
wait until rising_edge(clk);
assert count="100" report "Counter value is not 4" severity failure;
assert last='1' report "Wrong last value indication" severity failure;
print("Ena 6");
ena <= '1';
wait until rising_edge(clk);
assert count="000" report "Counter value is not 0" severity failure;
assert last='0' report "Wrong last value indication" severity failure;
ena <= '0';
wait until rising_edge(clk);
print("* End of Test");
stop <= TRUE;
wait;
end process test_p;
end architecture TestBench;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1787.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c09s06b00x00p04n05i01787ent_a is
generic (
g0 : Boolean ;
g1 : Bit ;
g2 : Character ;
g3 : SEVERITY_LEVEL ;
g4 : Integer ;
g5 : Real ;
g6 : TIME ;
g7 : Natural ;
g8 : Positive ;
g9 : String ;
gA : Bit_vector
);
port (
port0 : out Boolean ;
port1 : out Bit ;
port2 : out Character ;
port3 : out SEVERITY_LEVEL ;
port4 : out Integer ;
port5 : out Real ;
port6 : out TIME ;
port7 : out Natural ;
port8 : out Positive ;
port9 : out String ;
portA : out Bit_vector
);
end c09s06b00x00p04n05i01787ent_a;
architecture c09s06b00x00p04n05i01787arch_a of c09s06b00x00p04n05i01787ent_a is
begin
port0 <= g0 after 11 ns;
port1 <= g1 after 11 ns;
port2 <= g2 after 11 ns;
port3 <= g3 after 11 ns;
port4 <= g4 after 11 ns;
port5 <= g5 after 11 ns;
port6 <= g6 after 11 ns;
port7 <= g7 after 11 ns;
port8 <= g8 after 11 ns;
port9 <= g9 after 11 ns;
portA <= gA after 11 ns;
end c09s06b00x00p04n05i01787arch_a;
ENTITY c09s06b00x00p04n05i01787ent IS
END c09s06b00x00p04n05i01787ent;
ARCHITECTURE c09s06b00x00p04n05i01787arch OF c09s06b00x00p04n05i01787ent IS
component MultiType
generic (
g0 : Boolean ;
g1 : Bit ;
g2 : Character ;
g3 : SEVERITY_LEVEL ;
g4 : Integer ;
g5 : Real ;
g6 : TIME ;
g7 : Natural ;
g8 : Positive ;
g9 : String ;
gA : Bit_vector
);
port (
port0 : out Boolean ;
port1 : out Bit ;
port2 : out Character ;
port3 : out SEVERITY_LEVEL ;
port4 : out Integer ;
port5 : out Real ;
port6 : out TIME ;
port7 : out Natural ;
port8 : out Positive ;
port9 : out String ;
portA : out Bit_vector
);
end component;
for u1 : MultiType use entity work.c09s06b00x00p04n05i01787ent_a(c09s06b00x00p04n05i01787arch_a);
subtype reg32 is Bit_vector ( 31 downto 0 );
subtype string16 is String ( 1 to 16 );
signal signal0 : Boolean ;
signal signal1 : Bit ;
signal signal2 : Character ;
signal signal3 : SEVERITY_LEVEL ;
signal signal4 : Integer ;
signal signal5 : Real ;
signal signal6 : TIME ;
signal signal7 : Natural ;
signal signal8 : Positive ;
signal signal9 : String16 ;
signal signalA : Reg32 ;
BEGIN
u1 : MultiType
generic map (
True,
'0',
'@',
NOTE,
123456789,
987654321.5,
110 ns,
12312,
3423,
"16 characters OK",
B"0101_0010_1001_0101_0010_1010_0101_0100"
)
port map (
signal0 ,
signal1 ,
signal2 ,
signal3 ,
signal4 ,
signal5 ,
signal6 ,
signal7 ,
signal8 ,
signal9 ,
signalA
);
TESTING: PROCESS
BEGIN
wait on signal0,signal1,signal2,signal3,signal4,signal5,signal6,signal7,signal8;
assert NOT( signal0 = True and
signal1 = '0' and
signal2 = '@' and
signal3 = NOTE and
signal4 = 123456789 and
signal5 = 987654321.5 and
signal6 = 110 ns and
signal7 = 12312 and
signal8 = 3423 and
signal9 = "16 characters OK" and
signalA = B"01010010100101010010101001010100")
report "***PASSED TEST: c09s06b00x00p04n05i01787"
severity NOTE;
assert ( signal0 = True and
signal1 = '0' and
signal2 = '@' and
signal3 = NOTE and
signal4 = 123456789 and
signal5 = 987654321.5 and
signal6 = 110 ns and
signal7 = 12312 and
signal8 = 3423 and
signal9 = "16 characters OK" and
signalA = B"01010010100101010010101001010100")
report "***FAILED TEST: c09s06b00x00p04n05i01787 - The generic map aspect, if present, should associate a single actual with each local generic in the corresponding component declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s06b00x00p04n05i01787arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1787.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c09s06b00x00p04n05i01787ent_a is
generic (
g0 : Boolean ;
g1 : Bit ;
g2 : Character ;
g3 : SEVERITY_LEVEL ;
g4 : Integer ;
g5 : Real ;
g6 : TIME ;
g7 : Natural ;
g8 : Positive ;
g9 : String ;
gA : Bit_vector
);
port (
port0 : out Boolean ;
port1 : out Bit ;
port2 : out Character ;
port3 : out SEVERITY_LEVEL ;
port4 : out Integer ;
port5 : out Real ;
port6 : out TIME ;
port7 : out Natural ;
port8 : out Positive ;
port9 : out String ;
portA : out Bit_vector
);
end c09s06b00x00p04n05i01787ent_a;
architecture c09s06b00x00p04n05i01787arch_a of c09s06b00x00p04n05i01787ent_a is
begin
port0 <= g0 after 11 ns;
port1 <= g1 after 11 ns;
port2 <= g2 after 11 ns;
port3 <= g3 after 11 ns;
port4 <= g4 after 11 ns;
port5 <= g5 after 11 ns;
port6 <= g6 after 11 ns;
port7 <= g7 after 11 ns;
port8 <= g8 after 11 ns;
port9 <= g9 after 11 ns;
portA <= gA after 11 ns;
end c09s06b00x00p04n05i01787arch_a;
ENTITY c09s06b00x00p04n05i01787ent IS
END c09s06b00x00p04n05i01787ent;
ARCHITECTURE c09s06b00x00p04n05i01787arch OF c09s06b00x00p04n05i01787ent IS
component MultiType
generic (
g0 : Boolean ;
g1 : Bit ;
g2 : Character ;
g3 : SEVERITY_LEVEL ;
g4 : Integer ;
g5 : Real ;
g6 : TIME ;
g7 : Natural ;
g8 : Positive ;
g9 : String ;
gA : Bit_vector
);
port (
port0 : out Boolean ;
port1 : out Bit ;
port2 : out Character ;
port3 : out SEVERITY_LEVEL ;
port4 : out Integer ;
port5 : out Real ;
port6 : out TIME ;
port7 : out Natural ;
port8 : out Positive ;
port9 : out String ;
portA : out Bit_vector
);
end component;
for u1 : MultiType use entity work.c09s06b00x00p04n05i01787ent_a(c09s06b00x00p04n05i01787arch_a);
subtype reg32 is Bit_vector ( 31 downto 0 );
subtype string16 is String ( 1 to 16 );
signal signal0 : Boolean ;
signal signal1 : Bit ;
signal signal2 : Character ;
signal signal3 : SEVERITY_LEVEL ;
signal signal4 : Integer ;
signal signal5 : Real ;
signal signal6 : TIME ;
signal signal7 : Natural ;
signal signal8 : Positive ;
signal signal9 : String16 ;
signal signalA : Reg32 ;
BEGIN
u1 : MultiType
generic map (
True,
'0',
'@',
NOTE,
123456789,
987654321.5,
110 ns,
12312,
3423,
"16 characters OK",
B"0101_0010_1001_0101_0010_1010_0101_0100"
)
port map (
signal0 ,
signal1 ,
signal2 ,
signal3 ,
signal4 ,
signal5 ,
signal6 ,
signal7 ,
signal8 ,
signal9 ,
signalA
);
TESTING: PROCESS
BEGIN
wait on signal0,signal1,signal2,signal3,signal4,signal5,signal6,signal7,signal8;
assert NOT( signal0 = True and
signal1 = '0' and
signal2 = '@' and
signal3 = NOTE and
signal4 = 123456789 and
signal5 = 987654321.5 and
signal6 = 110 ns and
signal7 = 12312 and
signal8 = 3423 and
signal9 = "16 characters OK" and
signalA = B"01010010100101010010101001010100")
report "***PASSED TEST: c09s06b00x00p04n05i01787"
severity NOTE;
assert ( signal0 = True and
signal1 = '0' and
signal2 = '@' and
signal3 = NOTE and
signal4 = 123456789 and
signal5 = 987654321.5 and
signal6 = 110 ns and
signal7 = 12312 and
signal8 = 3423 and
signal9 = "16 characters OK" and
signalA = B"01010010100101010010101001010100")
report "***FAILED TEST: c09s06b00x00p04n05i01787 - The generic map aspect, if present, should associate a single actual with each local generic in the corresponding component declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s06b00x00p04n05i01787arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1787.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c09s06b00x00p04n05i01787ent_a is
generic (
g0 : Boolean ;
g1 : Bit ;
g2 : Character ;
g3 : SEVERITY_LEVEL ;
g4 : Integer ;
g5 : Real ;
g6 : TIME ;
g7 : Natural ;
g8 : Positive ;
g9 : String ;
gA : Bit_vector
);
port (
port0 : out Boolean ;
port1 : out Bit ;
port2 : out Character ;
port3 : out SEVERITY_LEVEL ;
port4 : out Integer ;
port5 : out Real ;
port6 : out TIME ;
port7 : out Natural ;
port8 : out Positive ;
port9 : out String ;
portA : out Bit_vector
);
end c09s06b00x00p04n05i01787ent_a;
architecture c09s06b00x00p04n05i01787arch_a of c09s06b00x00p04n05i01787ent_a is
begin
port0 <= g0 after 11 ns;
port1 <= g1 after 11 ns;
port2 <= g2 after 11 ns;
port3 <= g3 after 11 ns;
port4 <= g4 after 11 ns;
port5 <= g5 after 11 ns;
port6 <= g6 after 11 ns;
port7 <= g7 after 11 ns;
port8 <= g8 after 11 ns;
port9 <= g9 after 11 ns;
portA <= gA after 11 ns;
end c09s06b00x00p04n05i01787arch_a;
ENTITY c09s06b00x00p04n05i01787ent IS
END c09s06b00x00p04n05i01787ent;
ARCHITECTURE c09s06b00x00p04n05i01787arch OF c09s06b00x00p04n05i01787ent IS
component MultiType
generic (
g0 : Boolean ;
g1 : Bit ;
g2 : Character ;
g3 : SEVERITY_LEVEL ;
g4 : Integer ;
g5 : Real ;
g6 : TIME ;
g7 : Natural ;
g8 : Positive ;
g9 : String ;
gA : Bit_vector
);
port (
port0 : out Boolean ;
port1 : out Bit ;
port2 : out Character ;
port3 : out SEVERITY_LEVEL ;
port4 : out Integer ;
port5 : out Real ;
port6 : out TIME ;
port7 : out Natural ;
port8 : out Positive ;
port9 : out String ;
portA : out Bit_vector
);
end component;
for u1 : MultiType use entity work.c09s06b00x00p04n05i01787ent_a(c09s06b00x00p04n05i01787arch_a);
subtype reg32 is Bit_vector ( 31 downto 0 );
subtype string16 is String ( 1 to 16 );
signal signal0 : Boolean ;
signal signal1 : Bit ;
signal signal2 : Character ;
signal signal3 : SEVERITY_LEVEL ;
signal signal4 : Integer ;
signal signal5 : Real ;
signal signal6 : TIME ;
signal signal7 : Natural ;
signal signal8 : Positive ;
signal signal9 : String16 ;
signal signalA : Reg32 ;
BEGIN
u1 : MultiType
generic map (
True,
'0',
'@',
NOTE,
123456789,
987654321.5,
110 ns,
12312,
3423,
"16 characters OK",
B"0101_0010_1001_0101_0010_1010_0101_0100"
)
port map (
signal0 ,
signal1 ,
signal2 ,
signal3 ,
signal4 ,
signal5 ,
signal6 ,
signal7 ,
signal8 ,
signal9 ,
signalA
);
TESTING: PROCESS
BEGIN
wait on signal0,signal1,signal2,signal3,signal4,signal5,signal6,signal7,signal8;
assert NOT( signal0 = True and
signal1 = '0' and
signal2 = '@' and
signal3 = NOTE and
signal4 = 123456789 and
signal5 = 987654321.5 and
signal6 = 110 ns and
signal7 = 12312 and
signal8 = 3423 and
signal9 = "16 characters OK" and
signalA = B"01010010100101010010101001010100")
report "***PASSED TEST: c09s06b00x00p04n05i01787"
severity NOTE;
assert ( signal0 = True and
signal1 = '0' and
signal2 = '@' and
signal3 = NOTE and
signal4 = 123456789 and
signal5 = 987654321.5 and
signal6 = 110 ns and
signal7 = 12312 and
signal8 = 3423 and
signal9 = "16 characters OK" and
signalA = B"01010010100101010010101001010100")
report "***FAILED TEST: c09s06b00x00p04n05i01787 - The generic map aspect, if present, should associate a single actual with each local generic in the corresponding component declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s06b00x00p04n05i01787arch;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "ws2812"
-------------------------------------------------------------------------------
-- Author : [email protected]
-------------------------------------------------------------------------------
-- Created : 2014-12-13
-------------------------------------------------------------------------------
-- Copyright (c) 2014, Carl Treudler
-- All Rights Reserved.
--
-- The file is part for the Loa project and is released under the
-- 3-clause BSD license. See the file `LICENSE` for the full license
-- governing this code.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.ws2812_pkg.all;
use work.ws2812_cfg_pkg.all;
-------------------------------------------------------------------------------
entity ws2812_tb is
end ws2812_tb;
-------------------------------------------------------------------------------
architecture tb of ws2812_tb is
-- component ports
signal ws2812_in : ws2812_in_type;
signal ws2812_out : ws2812_out_type;
signal ws2812_chain_out : ws2812_chain_out_type;
-- clock
signal Clk : std_logic := '1';
signal reset : std_logic := '1';
begin -- tb
-- component instantiation
DUT : ws2812
port map (
ws2812_in => ws2812_in,
ws2812_out => ws2812_out,
ws2812_chain_out => ws2812_chain_out,
reset => reset,
clk => clk);
-- clock generation
Clk <= not Clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
wait until Clk = '1';
reset <='0';
wait until Clk = '1';
-- insert signal assignments here
ws2812_in.send_reset <= '0';
ws2812_in.we <= '0';
ws2812_in.d <= x"000000";
wait until Clk = '1';
ws2812_in.d <= x"aa0f55";
ws2812_in.we <= '1';
wait until Clk = '1';
ws2812_in.we <= '0';
wait for 40 us;
ws2812_in.send_reset <= '1';
wait until Clk = '1';
ws2812_in.send_reset <= '0';
wait for 80 us;
end process WaveGen_Proc;
end tb;
-------------------------------------------------------------------------------
configuration ws2812_tb_tb_cfg of ws2812_tb is
for tb
end for;
end ws2812_tb_tb_cfg;
-------------------------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MAC4 is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Z : out STD_LOGIC_VECTOR (7 downto 0));
end MAC4;
architecture MAC4_arch of MAC4 is
component HA
port(A,B: in STD_LOGIC; Sout, Cout: out STD_LOGIC);
end component;
component HAM
port(X,Y,B: in STD_LOGIC; Sout, Cout: out STD_LOGIC);
end component;
component FA
port(A,B,Cin: in STD_LOGIC; Sout, Cout: out STD_LOGIC);
end component;
component FAM
port(X,Y,B,Cin: in STD_LOGIC; Sout, Cout: out STD_LOGIC);
end component;
signal S0,S1,S2,S3,S4,C1,C2,C3,C4 : STD_LOGIC_VECTOR(3 downto 0);
begin
S0(0) <= A(0) AND B(0);
S0(1) <= A(1) AND B(0);
S0(2) <= A(2) AND B(0);
S0(3) <= A(3) AND B(0);
HAM10: HAM port map(A(0),B(1),S0(1),S1(0),C1(0));
HAM11: HAM port map(A(1),B(1),S0(2),S1(1),C1(1));
HAM12: HAM port map(A(2),B(1),S0(3),S1(2),C1(2));
HAM13: HAM port map(A(3),B(1),'0',S1(3),C1(3));
FAM20: FAM port map(A(0),B(2),S1(1),C1(0),S2(0),C2(0));
FAM21: FAM port map(A(1),B(2),S1(2),C1(1),S2(1),C2(1));
FAM22: FAM port map(A(2),B(2),S1(3),C1(2),S2(2),C2(2));
HAM23: HAM port map(A(3),B(2),C1(3),S2(3),C2(3));
FAM30: FAM port map(A(0),B(3),S2(1),C2(0),S3(0),C3(0));
FAM31: FAM port map(A(1),B(3),S2(2),C2(1),S3(1),C3(1));
FAM32: FAM port map(A(2),B(3),S2(3),C2(2),S3(2),C3(2));
HAM33: HAM port map(A(3),B(3),C2(3),S3(3),C3(3));
HA40: HA port map(S3(1),C3(0),S4(0),C4(0));
FA41: FA port map(S3(2),C3(1),C4(0),S4(1),C4(1));
FA42: FA port map(S3(3),C3(2),C4(1),S4(2),C4(2));
HA44: HA port map(C3(3),C4(2),S4(3),open);
Z(0)<=S0(0);
Z(1)<=S1(0);
Z(2)<=S2(0);
Z(3)<=S3(0);
Z(4)<=S4(0);
Z(5)<=S4(1);
Z(6)<=S4(2);
Z(7)<=S4(3);
end MAC4_arch;
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll8.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 10.1 Build 153 11/29/2010 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll8 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll8;
ARCHITECTURE SYN OF pll8 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
locked <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 2,
clk0_duty_cycle => 50,
clk0_multiply_by => 25,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 125000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll8",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire4,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "8.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll8.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "125000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Captures the pixels coming from the OV7670 camera and
-- Stores them in block RAM
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.NUMERIC_STD.ALL;
entity ov7670_capture is
port (
pclk : in std_logic;
vsync : in std_logic;
href : in std_logic;
d : in std_logic_vector ( 7 downto 0);
addr : out std_logic_vector (17 downto 0);
dout : out std_logic_vector (11 downto 0);
we : out std_logic
);
end ov7670_capture;
architecture behavioral of ov7670_capture is
signal d_latch : std_logic_vector(15 downto 0) := (others => '0');
signal address : std_logic_vector(18 downto 0) := (others => '0');
signal address_next : std_logic_vector(18 downto 0) := (others => '0');
signal wr_hold : std_logic_vector( 1 downto 0) := (others => '0');
begin
addr <= address(18 downto 1);
process(pclk)
begin
if rising_edge(pclk) then
-- This is a bit tricky href starts a pixel transfer that takes 3 cycles
-- Input | state after clock tick
-- href | wr_hold d_latch d we address address_next
-- cycle -1 x | xx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx x xxxx xxxx
-- cycle 0 1 | x1 xxxxxxxxRRRRRGGG xxxxxxxxxxxxxxxx x xxxx addr
-- cycle 1 0 | 10 RRRRRGGGGGGBBBBB xxxxxxxxRRRRRGGG x addr addr
-- cycle 2 x | 0x GGGBBBBBxxxxxxxx RRRRRGGGGGGBBBBB 1 addr addr+1
if vsync = '1' then
address <= (others => '0');
address_next <= (others => '0');
wr_hold <= (others => '0');
else
-- This should be a different order, but seems to be GRB!
dout <= d_latch(15 downto 12) & d_latch(10 downto 7) & d_latch(4 downto 1);
address <= address_next;
we <= wr_hold(1);
wr_hold <= wr_hold(0) & (href and not wr_hold(0));
d_latch <= d_latch( 7 downto 0) & d;
if wr_hold(1) = '1' then
address_next <= std_logic_vector(unsigned(address_next)+1);
end if;
end if;
end if;
end process;
end behavioral;
|
-------------------------------------------------------------------------------
-- TC_TYPES - package
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :tc_types.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Type definitions for Timer/Counter
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
--
-- tc_types.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
--Package Declaration
-------------------------------------------------------------------------------
package TC_Types is
subtype QUADLET_TYPE is std_logic_vector(0 to 31);
subtype ELEVEN_BIT_TYPE is std_logic_vector(21 to 31);
subtype TWELVE_BIT_TYPE is std_logic_vector(20 to 31);
subtype QUADLET_PLUS1_TYPE is std_logic_vector(0 to 32);
subtype BYTE_TYPE is std_logic_vector(0 to 7);
subtype ALU_OP_TYPE is std_logic_vector(0 to 1);
subtype ADDR_WORD_TYPE is std_logic_vector(0 to 31);
subtype BYTE_ENABLE_TYPE is std_logic_vector(0 to 3);
subtype DATA_WORD_TYPE is QUADLET_TYPE;
subtype INSTRUCTION_WORD_TYPE is QUADLET_TYPE;
-- Bus interface data types
subtype PLB_DWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_AWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_BEWIDTH_TYPE is std_logic_vector(0 to 3);
subtype BYTE_PLUS1_TYPE is std_logic_vector(0 to 8);
subtype NIBBLE_TYPE is std_logic_vector(0 to 3);
type TWO_QUADLET_TYPE is array (0 to 1) of QUADLET_TYPE;
constant CASC_POS : integer := 20;
constant ENALL_POS : integer := 21;
constant PWMA0_POS : integer := 22;
constant T0INT_POS : integer := 23;
constant ENT0_POS : integer := 24;
constant ENIT0_POS : integer := 25;
constant LOAD0_POS : integer := 26;
constant ARHT0_POS : integer := 27;
constant CAPT0_POS : integer := 28;
constant CMPT0_POS : integer := 29;
constant UDT0_POS : integer := 30;
constant MDT0_POS : integer := 31;
constant PWMB0_POS : integer := 22;
constant T1INT_POS : integer := 23;
constant ENT1_POS : integer := 24;
constant ENIT1_POS : integer := 25;
constant LOAD1_POS : integer := 26;
constant ARHT1_POS : integer := 27;
constant CAPT1_POS : integer := 28;
constant CMPT1_POS : integer := 29;
constant UDT1_POS : integer := 30;
constant MDT1_POS : integer := 31;
constant LS_ADDR : std_logic_vector(0 to 1) := "11";
constant NEXT_MSB_BIT : integer := -1;
constant NEXT_LSB_BIT : integer := 1;
-- The following four constants arer reversed from what's
-- in microblaze_isa_be_pkg.vhd
constant BYTE_ENABLE_BYTE_0 : natural := 0;
constant BYTE_ENABLE_BYTE_1 : natural := 1;
constant BYTE_ENABLE_BYTE_2 : natural := 2;
constant BYTE_ENABLE_BYTE_3 : natural := 3;
end package TC_TYPES;
|
-------------------------------------------------------------------------------
-- TC_TYPES - package
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :tc_types.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Type definitions for Timer/Counter
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
--
-- tc_types.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
--Package Declaration
-------------------------------------------------------------------------------
package TC_Types is
subtype QUADLET_TYPE is std_logic_vector(0 to 31);
subtype ELEVEN_BIT_TYPE is std_logic_vector(21 to 31);
subtype TWELVE_BIT_TYPE is std_logic_vector(20 to 31);
subtype QUADLET_PLUS1_TYPE is std_logic_vector(0 to 32);
subtype BYTE_TYPE is std_logic_vector(0 to 7);
subtype ALU_OP_TYPE is std_logic_vector(0 to 1);
subtype ADDR_WORD_TYPE is std_logic_vector(0 to 31);
subtype BYTE_ENABLE_TYPE is std_logic_vector(0 to 3);
subtype DATA_WORD_TYPE is QUADLET_TYPE;
subtype INSTRUCTION_WORD_TYPE is QUADLET_TYPE;
-- Bus interface data types
subtype PLB_DWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_AWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_BEWIDTH_TYPE is std_logic_vector(0 to 3);
subtype BYTE_PLUS1_TYPE is std_logic_vector(0 to 8);
subtype NIBBLE_TYPE is std_logic_vector(0 to 3);
type TWO_QUADLET_TYPE is array (0 to 1) of QUADLET_TYPE;
constant CASC_POS : integer := 20;
constant ENALL_POS : integer := 21;
constant PWMA0_POS : integer := 22;
constant T0INT_POS : integer := 23;
constant ENT0_POS : integer := 24;
constant ENIT0_POS : integer := 25;
constant LOAD0_POS : integer := 26;
constant ARHT0_POS : integer := 27;
constant CAPT0_POS : integer := 28;
constant CMPT0_POS : integer := 29;
constant UDT0_POS : integer := 30;
constant MDT0_POS : integer := 31;
constant PWMB0_POS : integer := 22;
constant T1INT_POS : integer := 23;
constant ENT1_POS : integer := 24;
constant ENIT1_POS : integer := 25;
constant LOAD1_POS : integer := 26;
constant ARHT1_POS : integer := 27;
constant CAPT1_POS : integer := 28;
constant CMPT1_POS : integer := 29;
constant UDT1_POS : integer := 30;
constant MDT1_POS : integer := 31;
constant LS_ADDR : std_logic_vector(0 to 1) := "11";
constant NEXT_MSB_BIT : integer := -1;
constant NEXT_LSB_BIT : integer := 1;
-- The following four constants arer reversed from what's
-- in microblaze_isa_be_pkg.vhd
constant BYTE_ENABLE_BYTE_0 : natural := 0;
constant BYTE_ENABLE_BYTE_1 : natural := 1;
constant BYTE_ENABLE_BYTE_2 : natural := 2;
constant BYTE_ENABLE_BYTE_3 : natural := 3;
end package TC_TYPES;
|
-------------------------------------------------------------------------------
-- TC_TYPES - package
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :tc_types.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Type definitions for Timer/Counter
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
--
-- tc_types.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
--Package Declaration
-------------------------------------------------------------------------------
package TC_Types is
subtype QUADLET_TYPE is std_logic_vector(0 to 31);
subtype ELEVEN_BIT_TYPE is std_logic_vector(21 to 31);
subtype TWELVE_BIT_TYPE is std_logic_vector(20 to 31);
subtype QUADLET_PLUS1_TYPE is std_logic_vector(0 to 32);
subtype BYTE_TYPE is std_logic_vector(0 to 7);
subtype ALU_OP_TYPE is std_logic_vector(0 to 1);
subtype ADDR_WORD_TYPE is std_logic_vector(0 to 31);
subtype BYTE_ENABLE_TYPE is std_logic_vector(0 to 3);
subtype DATA_WORD_TYPE is QUADLET_TYPE;
subtype INSTRUCTION_WORD_TYPE is QUADLET_TYPE;
-- Bus interface data types
subtype PLB_DWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_AWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_BEWIDTH_TYPE is std_logic_vector(0 to 3);
subtype BYTE_PLUS1_TYPE is std_logic_vector(0 to 8);
subtype NIBBLE_TYPE is std_logic_vector(0 to 3);
type TWO_QUADLET_TYPE is array (0 to 1) of QUADLET_TYPE;
constant CASC_POS : integer := 20;
constant ENALL_POS : integer := 21;
constant PWMA0_POS : integer := 22;
constant T0INT_POS : integer := 23;
constant ENT0_POS : integer := 24;
constant ENIT0_POS : integer := 25;
constant LOAD0_POS : integer := 26;
constant ARHT0_POS : integer := 27;
constant CAPT0_POS : integer := 28;
constant CMPT0_POS : integer := 29;
constant UDT0_POS : integer := 30;
constant MDT0_POS : integer := 31;
constant PWMB0_POS : integer := 22;
constant T1INT_POS : integer := 23;
constant ENT1_POS : integer := 24;
constant ENIT1_POS : integer := 25;
constant LOAD1_POS : integer := 26;
constant ARHT1_POS : integer := 27;
constant CAPT1_POS : integer := 28;
constant CMPT1_POS : integer := 29;
constant UDT1_POS : integer := 30;
constant MDT1_POS : integer := 31;
constant LS_ADDR : std_logic_vector(0 to 1) := "11";
constant NEXT_MSB_BIT : integer := -1;
constant NEXT_LSB_BIT : integer := 1;
-- The following four constants arer reversed from what's
-- in microblaze_isa_be_pkg.vhd
constant BYTE_ENABLE_BYTE_0 : natural := 0;
constant BYTE_ENABLE_BYTE_1 : natural := 1;
constant BYTE_ENABLE_BYTE_2 : natural := 2;
constant BYTE_ENABLE_BYTE_3 : natural := 3;
end package TC_TYPES;
|
-------------------------------------------------------------------------------
-- TC_TYPES - package
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :tc_types.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Type definitions for Timer/Counter
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
--
-- tc_types.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
--Package Declaration
-------------------------------------------------------------------------------
package TC_Types is
subtype QUADLET_TYPE is std_logic_vector(0 to 31);
subtype ELEVEN_BIT_TYPE is std_logic_vector(21 to 31);
subtype TWELVE_BIT_TYPE is std_logic_vector(20 to 31);
subtype QUADLET_PLUS1_TYPE is std_logic_vector(0 to 32);
subtype BYTE_TYPE is std_logic_vector(0 to 7);
subtype ALU_OP_TYPE is std_logic_vector(0 to 1);
subtype ADDR_WORD_TYPE is std_logic_vector(0 to 31);
subtype BYTE_ENABLE_TYPE is std_logic_vector(0 to 3);
subtype DATA_WORD_TYPE is QUADLET_TYPE;
subtype INSTRUCTION_WORD_TYPE is QUADLET_TYPE;
-- Bus interface data types
subtype PLB_DWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_AWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_BEWIDTH_TYPE is std_logic_vector(0 to 3);
subtype BYTE_PLUS1_TYPE is std_logic_vector(0 to 8);
subtype NIBBLE_TYPE is std_logic_vector(0 to 3);
type TWO_QUADLET_TYPE is array (0 to 1) of QUADLET_TYPE;
constant CASC_POS : integer := 20;
constant ENALL_POS : integer := 21;
constant PWMA0_POS : integer := 22;
constant T0INT_POS : integer := 23;
constant ENT0_POS : integer := 24;
constant ENIT0_POS : integer := 25;
constant LOAD0_POS : integer := 26;
constant ARHT0_POS : integer := 27;
constant CAPT0_POS : integer := 28;
constant CMPT0_POS : integer := 29;
constant UDT0_POS : integer := 30;
constant MDT0_POS : integer := 31;
constant PWMB0_POS : integer := 22;
constant T1INT_POS : integer := 23;
constant ENT1_POS : integer := 24;
constant ENIT1_POS : integer := 25;
constant LOAD1_POS : integer := 26;
constant ARHT1_POS : integer := 27;
constant CAPT1_POS : integer := 28;
constant CMPT1_POS : integer := 29;
constant UDT1_POS : integer := 30;
constant MDT1_POS : integer := 31;
constant LS_ADDR : std_logic_vector(0 to 1) := "11";
constant NEXT_MSB_BIT : integer := -1;
constant NEXT_LSB_BIT : integer := 1;
-- The following four constants arer reversed from what's
-- in microblaze_isa_be_pkg.vhd
constant BYTE_ENABLE_BYTE_0 : natural := 0;
constant BYTE_ENABLE_BYTE_1 : natural := 1;
constant BYTE_ENABLE_BYTE_2 : natural := 2;
constant BYTE_ENABLE_BYTE_3 : natural := 3;
end package TC_TYPES;
|
-------------------------------------------------------------------------------
-- TC_TYPES - package
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :tc_types.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Type definitions for Timer/Counter
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
--
-- tc_types.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
--Package Declaration
-------------------------------------------------------------------------------
package TC_Types is
subtype QUADLET_TYPE is std_logic_vector(0 to 31);
subtype ELEVEN_BIT_TYPE is std_logic_vector(21 to 31);
subtype TWELVE_BIT_TYPE is std_logic_vector(20 to 31);
subtype QUADLET_PLUS1_TYPE is std_logic_vector(0 to 32);
subtype BYTE_TYPE is std_logic_vector(0 to 7);
subtype ALU_OP_TYPE is std_logic_vector(0 to 1);
subtype ADDR_WORD_TYPE is std_logic_vector(0 to 31);
subtype BYTE_ENABLE_TYPE is std_logic_vector(0 to 3);
subtype DATA_WORD_TYPE is QUADLET_TYPE;
subtype INSTRUCTION_WORD_TYPE is QUADLET_TYPE;
-- Bus interface data types
subtype PLB_DWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_AWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_BEWIDTH_TYPE is std_logic_vector(0 to 3);
subtype BYTE_PLUS1_TYPE is std_logic_vector(0 to 8);
subtype NIBBLE_TYPE is std_logic_vector(0 to 3);
type TWO_QUADLET_TYPE is array (0 to 1) of QUADLET_TYPE;
constant CASC_POS : integer := 20;
constant ENALL_POS : integer := 21;
constant PWMA0_POS : integer := 22;
constant T0INT_POS : integer := 23;
constant ENT0_POS : integer := 24;
constant ENIT0_POS : integer := 25;
constant LOAD0_POS : integer := 26;
constant ARHT0_POS : integer := 27;
constant CAPT0_POS : integer := 28;
constant CMPT0_POS : integer := 29;
constant UDT0_POS : integer := 30;
constant MDT0_POS : integer := 31;
constant PWMB0_POS : integer := 22;
constant T1INT_POS : integer := 23;
constant ENT1_POS : integer := 24;
constant ENIT1_POS : integer := 25;
constant LOAD1_POS : integer := 26;
constant ARHT1_POS : integer := 27;
constant CAPT1_POS : integer := 28;
constant CMPT1_POS : integer := 29;
constant UDT1_POS : integer := 30;
constant MDT1_POS : integer := 31;
constant LS_ADDR : std_logic_vector(0 to 1) := "11";
constant NEXT_MSB_BIT : integer := -1;
constant NEXT_LSB_BIT : integer := 1;
-- The following four constants arer reversed from what's
-- in microblaze_isa_be_pkg.vhd
constant BYTE_ENABLE_BYTE_0 : natural := 0;
constant BYTE_ENABLE_BYTE_1 : natural := 1;
constant BYTE_ENABLE_BYTE_2 : natural := 2;
constant BYTE_ENABLE_BYTE_3 : natural := 3;
end package TC_TYPES;
|
-------------------------------------------------------------------------------
-- TC_TYPES - package
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :tc_types.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Type definitions for Timer/Counter
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
--
-- tc_types.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
--Package Declaration
-------------------------------------------------------------------------------
package TC_Types is
subtype QUADLET_TYPE is std_logic_vector(0 to 31);
subtype ELEVEN_BIT_TYPE is std_logic_vector(21 to 31);
subtype TWELVE_BIT_TYPE is std_logic_vector(20 to 31);
subtype QUADLET_PLUS1_TYPE is std_logic_vector(0 to 32);
subtype BYTE_TYPE is std_logic_vector(0 to 7);
subtype ALU_OP_TYPE is std_logic_vector(0 to 1);
subtype ADDR_WORD_TYPE is std_logic_vector(0 to 31);
subtype BYTE_ENABLE_TYPE is std_logic_vector(0 to 3);
subtype DATA_WORD_TYPE is QUADLET_TYPE;
subtype INSTRUCTION_WORD_TYPE is QUADLET_TYPE;
-- Bus interface data types
subtype PLB_DWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_AWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_BEWIDTH_TYPE is std_logic_vector(0 to 3);
subtype BYTE_PLUS1_TYPE is std_logic_vector(0 to 8);
subtype NIBBLE_TYPE is std_logic_vector(0 to 3);
type TWO_QUADLET_TYPE is array (0 to 1) of QUADLET_TYPE;
constant CASC_POS : integer := 20;
constant ENALL_POS : integer := 21;
constant PWMA0_POS : integer := 22;
constant T0INT_POS : integer := 23;
constant ENT0_POS : integer := 24;
constant ENIT0_POS : integer := 25;
constant LOAD0_POS : integer := 26;
constant ARHT0_POS : integer := 27;
constant CAPT0_POS : integer := 28;
constant CMPT0_POS : integer := 29;
constant UDT0_POS : integer := 30;
constant MDT0_POS : integer := 31;
constant PWMB0_POS : integer := 22;
constant T1INT_POS : integer := 23;
constant ENT1_POS : integer := 24;
constant ENIT1_POS : integer := 25;
constant LOAD1_POS : integer := 26;
constant ARHT1_POS : integer := 27;
constant CAPT1_POS : integer := 28;
constant CMPT1_POS : integer := 29;
constant UDT1_POS : integer := 30;
constant MDT1_POS : integer := 31;
constant LS_ADDR : std_logic_vector(0 to 1) := "11";
constant NEXT_MSB_BIT : integer := -1;
constant NEXT_LSB_BIT : integer := 1;
-- The following four constants arer reversed from what's
-- in microblaze_isa_be_pkg.vhd
constant BYTE_ENABLE_BYTE_0 : natural := 0;
constant BYTE_ENABLE_BYTE_1 : natural := 1;
constant BYTE_ENABLE_BYTE_2 : natural := 2;
constant BYTE_ENABLE_BYTE_3 : natural := 3;
end package TC_TYPES;
|
-------------------------------------------------------------------------------
-- TC_TYPES - package
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :tc_types.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Type definitions for Timer/Counter
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
--
-- tc_types.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
--Package Declaration
-------------------------------------------------------------------------------
package TC_Types is
subtype QUADLET_TYPE is std_logic_vector(0 to 31);
subtype ELEVEN_BIT_TYPE is std_logic_vector(21 to 31);
subtype TWELVE_BIT_TYPE is std_logic_vector(20 to 31);
subtype QUADLET_PLUS1_TYPE is std_logic_vector(0 to 32);
subtype BYTE_TYPE is std_logic_vector(0 to 7);
subtype ALU_OP_TYPE is std_logic_vector(0 to 1);
subtype ADDR_WORD_TYPE is std_logic_vector(0 to 31);
subtype BYTE_ENABLE_TYPE is std_logic_vector(0 to 3);
subtype DATA_WORD_TYPE is QUADLET_TYPE;
subtype INSTRUCTION_WORD_TYPE is QUADLET_TYPE;
-- Bus interface data types
subtype PLB_DWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_AWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_BEWIDTH_TYPE is std_logic_vector(0 to 3);
subtype BYTE_PLUS1_TYPE is std_logic_vector(0 to 8);
subtype NIBBLE_TYPE is std_logic_vector(0 to 3);
type TWO_QUADLET_TYPE is array (0 to 1) of QUADLET_TYPE;
constant CASC_POS : integer := 20;
constant ENALL_POS : integer := 21;
constant PWMA0_POS : integer := 22;
constant T0INT_POS : integer := 23;
constant ENT0_POS : integer := 24;
constant ENIT0_POS : integer := 25;
constant LOAD0_POS : integer := 26;
constant ARHT0_POS : integer := 27;
constant CAPT0_POS : integer := 28;
constant CMPT0_POS : integer := 29;
constant UDT0_POS : integer := 30;
constant MDT0_POS : integer := 31;
constant PWMB0_POS : integer := 22;
constant T1INT_POS : integer := 23;
constant ENT1_POS : integer := 24;
constant ENIT1_POS : integer := 25;
constant LOAD1_POS : integer := 26;
constant ARHT1_POS : integer := 27;
constant CAPT1_POS : integer := 28;
constant CMPT1_POS : integer := 29;
constant UDT1_POS : integer := 30;
constant MDT1_POS : integer := 31;
constant LS_ADDR : std_logic_vector(0 to 1) := "11";
constant NEXT_MSB_BIT : integer := -1;
constant NEXT_LSB_BIT : integer := 1;
-- The following four constants arer reversed from what's
-- in microblaze_isa_be_pkg.vhd
constant BYTE_ENABLE_BYTE_0 : natural := 0;
constant BYTE_ENABLE_BYTE_1 : natural := 1;
constant BYTE_ENABLE_BYTE_2 : natural := 2;
constant BYTE_ENABLE_BYTE_3 : natural := 3;
end package TC_TYPES;
|
-------------------------------------------------------------------------------
-- TC_TYPES - package
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :tc_types.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Type definitions for Timer/Counter
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
--
-- tc_types.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
--Package Declaration
-------------------------------------------------------------------------------
package TC_Types is
subtype QUADLET_TYPE is std_logic_vector(0 to 31);
subtype ELEVEN_BIT_TYPE is std_logic_vector(21 to 31);
subtype TWELVE_BIT_TYPE is std_logic_vector(20 to 31);
subtype QUADLET_PLUS1_TYPE is std_logic_vector(0 to 32);
subtype BYTE_TYPE is std_logic_vector(0 to 7);
subtype ALU_OP_TYPE is std_logic_vector(0 to 1);
subtype ADDR_WORD_TYPE is std_logic_vector(0 to 31);
subtype BYTE_ENABLE_TYPE is std_logic_vector(0 to 3);
subtype DATA_WORD_TYPE is QUADLET_TYPE;
subtype INSTRUCTION_WORD_TYPE is QUADLET_TYPE;
-- Bus interface data types
subtype PLB_DWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_AWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_BEWIDTH_TYPE is std_logic_vector(0 to 3);
subtype BYTE_PLUS1_TYPE is std_logic_vector(0 to 8);
subtype NIBBLE_TYPE is std_logic_vector(0 to 3);
type TWO_QUADLET_TYPE is array (0 to 1) of QUADLET_TYPE;
constant CASC_POS : integer := 20;
constant ENALL_POS : integer := 21;
constant PWMA0_POS : integer := 22;
constant T0INT_POS : integer := 23;
constant ENT0_POS : integer := 24;
constant ENIT0_POS : integer := 25;
constant LOAD0_POS : integer := 26;
constant ARHT0_POS : integer := 27;
constant CAPT0_POS : integer := 28;
constant CMPT0_POS : integer := 29;
constant UDT0_POS : integer := 30;
constant MDT0_POS : integer := 31;
constant PWMB0_POS : integer := 22;
constant T1INT_POS : integer := 23;
constant ENT1_POS : integer := 24;
constant ENIT1_POS : integer := 25;
constant LOAD1_POS : integer := 26;
constant ARHT1_POS : integer := 27;
constant CAPT1_POS : integer := 28;
constant CMPT1_POS : integer := 29;
constant UDT1_POS : integer := 30;
constant MDT1_POS : integer := 31;
constant LS_ADDR : std_logic_vector(0 to 1) := "11";
constant NEXT_MSB_BIT : integer := -1;
constant NEXT_LSB_BIT : integer := 1;
-- The following four constants arer reversed from what's
-- in microblaze_isa_be_pkg.vhd
constant BYTE_ENABLE_BYTE_0 : natural := 0;
constant BYTE_ENABLE_BYTE_1 : natural := 1;
constant BYTE_ENABLE_BYTE_2 : natural := 2;
constant BYTE_ENABLE_BYTE_3 : natural := 3;
end package TC_TYPES;
|
-------------------------------------------------------------------------------
-- TC_TYPES - package
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :tc_types.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Type definitions for Timer/Counter
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
--
-- tc_types.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
--Package Declaration
-------------------------------------------------------------------------------
package TC_Types is
subtype QUADLET_TYPE is std_logic_vector(0 to 31);
subtype ELEVEN_BIT_TYPE is std_logic_vector(21 to 31);
subtype TWELVE_BIT_TYPE is std_logic_vector(20 to 31);
subtype QUADLET_PLUS1_TYPE is std_logic_vector(0 to 32);
subtype BYTE_TYPE is std_logic_vector(0 to 7);
subtype ALU_OP_TYPE is std_logic_vector(0 to 1);
subtype ADDR_WORD_TYPE is std_logic_vector(0 to 31);
subtype BYTE_ENABLE_TYPE is std_logic_vector(0 to 3);
subtype DATA_WORD_TYPE is QUADLET_TYPE;
subtype INSTRUCTION_WORD_TYPE is QUADLET_TYPE;
-- Bus interface data types
subtype PLB_DWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_AWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_BEWIDTH_TYPE is std_logic_vector(0 to 3);
subtype BYTE_PLUS1_TYPE is std_logic_vector(0 to 8);
subtype NIBBLE_TYPE is std_logic_vector(0 to 3);
type TWO_QUADLET_TYPE is array (0 to 1) of QUADLET_TYPE;
constant CASC_POS : integer := 20;
constant ENALL_POS : integer := 21;
constant PWMA0_POS : integer := 22;
constant T0INT_POS : integer := 23;
constant ENT0_POS : integer := 24;
constant ENIT0_POS : integer := 25;
constant LOAD0_POS : integer := 26;
constant ARHT0_POS : integer := 27;
constant CAPT0_POS : integer := 28;
constant CMPT0_POS : integer := 29;
constant UDT0_POS : integer := 30;
constant MDT0_POS : integer := 31;
constant PWMB0_POS : integer := 22;
constant T1INT_POS : integer := 23;
constant ENT1_POS : integer := 24;
constant ENIT1_POS : integer := 25;
constant LOAD1_POS : integer := 26;
constant ARHT1_POS : integer := 27;
constant CAPT1_POS : integer := 28;
constant CMPT1_POS : integer := 29;
constant UDT1_POS : integer := 30;
constant MDT1_POS : integer := 31;
constant LS_ADDR : std_logic_vector(0 to 1) := "11";
constant NEXT_MSB_BIT : integer := -1;
constant NEXT_LSB_BIT : integer := 1;
-- The following four constants arer reversed from what's
-- in microblaze_isa_be_pkg.vhd
constant BYTE_ENABLE_BYTE_0 : natural := 0;
constant BYTE_ENABLE_BYTE_1 : natural := 1;
constant BYTE_ENABLE_BYTE_2 : natural := 2;
constant BYTE_ENABLE_BYTE_3 : natural := 3;
end package TC_TYPES;
|
-------------------------------------------------------------------------------
-- TC_TYPES - package
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :tc_types.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Type definitions for Timer/Counter
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
--
-- tc_types.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
--Package Declaration
-------------------------------------------------------------------------------
package TC_Types is
subtype QUADLET_TYPE is std_logic_vector(0 to 31);
subtype ELEVEN_BIT_TYPE is std_logic_vector(21 to 31);
subtype TWELVE_BIT_TYPE is std_logic_vector(20 to 31);
subtype QUADLET_PLUS1_TYPE is std_logic_vector(0 to 32);
subtype BYTE_TYPE is std_logic_vector(0 to 7);
subtype ALU_OP_TYPE is std_logic_vector(0 to 1);
subtype ADDR_WORD_TYPE is std_logic_vector(0 to 31);
subtype BYTE_ENABLE_TYPE is std_logic_vector(0 to 3);
subtype DATA_WORD_TYPE is QUADLET_TYPE;
subtype INSTRUCTION_WORD_TYPE is QUADLET_TYPE;
-- Bus interface data types
subtype PLB_DWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_AWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_BEWIDTH_TYPE is std_logic_vector(0 to 3);
subtype BYTE_PLUS1_TYPE is std_logic_vector(0 to 8);
subtype NIBBLE_TYPE is std_logic_vector(0 to 3);
type TWO_QUADLET_TYPE is array (0 to 1) of QUADLET_TYPE;
constant CASC_POS : integer := 20;
constant ENALL_POS : integer := 21;
constant PWMA0_POS : integer := 22;
constant T0INT_POS : integer := 23;
constant ENT0_POS : integer := 24;
constant ENIT0_POS : integer := 25;
constant LOAD0_POS : integer := 26;
constant ARHT0_POS : integer := 27;
constant CAPT0_POS : integer := 28;
constant CMPT0_POS : integer := 29;
constant UDT0_POS : integer := 30;
constant MDT0_POS : integer := 31;
constant PWMB0_POS : integer := 22;
constant T1INT_POS : integer := 23;
constant ENT1_POS : integer := 24;
constant ENIT1_POS : integer := 25;
constant LOAD1_POS : integer := 26;
constant ARHT1_POS : integer := 27;
constant CAPT1_POS : integer := 28;
constant CMPT1_POS : integer := 29;
constant UDT1_POS : integer := 30;
constant MDT1_POS : integer := 31;
constant LS_ADDR : std_logic_vector(0 to 1) := "11";
constant NEXT_MSB_BIT : integer := -1;
constant NEXT_LSB_BIT : integer := 1;
-- The following four constants arer reversed from what's
-- in microblaze_isa_be_pkg.vhd
constant BYTE_ENABLE_BYTE_0 : natural := 0;
constant BYTE_ENABLE_BYTE_1 : natural := 1;
constant BYTE_ENABLE_BYTE_2 : natural := 2;
constant BYTE_ENABLE_BYTE_3 : natural := 3;
end package TC_TYPES;
|
--! @file symbolizer_tb.vhd
--! @brief Symbolizer block testbench
--! @author Scott Teal ([email protected])
--! @date 2013-11-05
--! @copyright
--! Copyright 2013 Richard Scott Teal, Jr.
--!
--! Licensed under the Apache License, Version 2.0 (the "License"); you may not
--! use this file except in compliance with the License. You may obtain a copy
--! of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
--! WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
--! License for the specific language governing permissions and limitations
--! under the License.
--! Standard IEEE library
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
library boostdsp;
use boostdsp.fixed_pkg.all;
use boostdsp.util_pkg.all;
use boostdsp.basic_pkg;
entity symbolizer_tb is
end entity symbolizer_tb;
architecture rtl of symbolizer_tb is
constant clk_hp : time := 1 ns;
signal clk : std_logic := '1';
signal rst : std_logic := '1';
signal data_in : unsigned(7 downto 0) := (others => '0');
signal data_in_std : std_logic_vector(data_in'range) := (others => '0');
signal busy : std_logic;
signal data_valid : std_logic := '0';
signal fetch_symbol : std_logic := '0';
signal symbol_out : std_logic_vector(6 downto 0) := (others => '0');
begin
data_in_std <= std_logic_vector(data_in);
uut : basic_pkg.symbolizer
port map (
clk => clk,
rst => rst,
data_in => data_in_std,
busy => busy,
data_valid => data_valid,
fetch_symbol => fetch_symbol,
symbol_out => symbol_out
);
clk_proc : process
begin
wait for clk_hp;
clk <= not clk;
end process;
rst_proc : process
begin
wait for clk_hp*4;
rst <= '0';
end process;
fetch_symbols : process
begin
wait for clk_hp*4;
while(true) loop
wait for (clk_hp*2)*12;
fetch_symbol <= '1';
wait for (clk_hp*2);
fetch_symbol <= '0';
end loop;
end process;
send_data : process
begin
wait for clk_hp*4;
if busy = '0' then
data_in <= data_in + 1;
data_valid <= '1';
wait for clk_hp*2;
data_valid <= '0';
end if;
end process;
end rtl;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
-- Date : Fri Sep 22 17:40:25 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_processing_system7_0_1_stub.vhdl
-- Design : zqynq_lab_1_design_processing_system7_0_1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[1:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2017.2.1";
begin
end;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_fg_16_09.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity latch is
generic ( width : positive );
port ( enable : in bit;
d : in bit_vector(0 to width - 1);
q : out bit_vector(0 to width - 1) );
end entity latch;
--------------------------------------------------
architecture behavioral of latch is
begin
transfer_control : block ( enable = '1' ) is
begin
q <= guarded d;
end block transfer_control;
end architecture behavioral;
-- not in book
entity fg_16_09 is
end entity fg_16_09;
architecture test of fg_16_09 is
signal enable : bit := '0';
signal d, q : bit_vector(0 to 7);
begin
dut : entity work.latch(behavioral)
generic map ( width => 8 )
port map ( enable => enable, d => d, q => q );
stimulus : process is
begin
wait for 10 ns;
d <= X"11"; wait for 10 ns;
enable <= '1'; wait for 10 ns;
d <= X"AA"; wait for 10 ns;
enable <= '0'; wait for 10 ns;
d <= X"00"; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
-- end not in book
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_fg_16_09.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity latch is
generic ( width : positive );
port ( enable : in bit;
d : in bit_vector(0 to width - 1);
q : out bit_vector(0 to width - 1) );
end entity latch;
--------------------------------------------------
architecture behavioral of latch is
begin
transfer_control : block ( enable = '1' ) is
begin
q <= guarded d;
end block transfer_control;
end architecture behavioral;
-- not in book
entity fg_16_09 is
end entity fg_16_09;
architecture test of fg_16_09 is
signal enable : bit := '0';
signal d, q : bit_vector(0 to 7);
begin
dut : entity work.latch(behavioral)
generic map ( width => 8 )
port map ( enable => enable, d => d, q => q );
stimulus : process is
begin
wait for 10 ns;
d <= X"11"; wait for 10 ns;
enable <= '1'; wait for 10 ns;
d <= X"AA"; wait for 10 ns;
enable <= '0'; wait for 10 ns;
d <= X"00"; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
-- end not in book
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_fg_16_09.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity latch is
generic ( width : positive );
port ( enable : in bit;
d : in bit_vector(0 to width - 1);
q : out bit_vector(0 to width - 1) );
end entity latch;
--------------------------------------------------
architecture behavioral of latch is
begin
transfer_control : block ( enable = '1' ) is
begin
q <= guarded d;
end block transfer_control;
end architecture behavioral;
-- not in book
entity fg_16_09 is
end entity fg_16_09;
architecture test of fg_16_09 is
signal enable : bit := '0';
signal d, q : bit_vector(0 to 7);
begin
dut : entity work.latch(behavioral)
generic map ( width => 8 )
port map ( enable => enable, d => d, q => q );
stimulus : process is
begin
wait for 10 ns;
d <= X"11"; wait for 10 ns;
enable <= '1'; wait for 10 ns;
d <= X"AA"; wait for 10 ns;
enable <= '0'; wait for 10 ns;
d <= X"00"; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
-- end not in book
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : sim_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:58 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Spartan-6
-- Design Name : DDR/DDR2/DDR3/LPDDR
-- Purpose : This is the simulation testbench which is used to verify the
-- design. The basic clocks and resets to the interface are
-- generated here. This also connects the memory interface to the
-- memory model.
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity sim_tb_top is
end entity sim_tb_top;
architecture arch of sim_tb_top is
-- ========================================================================== --
-- Parameters --
-- ========================================================================== --
constant DEBUG_EN : integer :=0;
constant C3_HW_TESTING : string := "FALSE";
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C3_MEMCLK_PERIOD : integer := 3000;
constant C3_RST_ACT_LOW : integer := 0;
constant C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
constant C3_CLK_PERIOD_NS : real := 3000.0 / 1000.0;
constant C3_TCYC_SYS : real := C3_CLK_PERIOD_NS/2.0;
constant C3_TCYC_SYS_DIV2 : time := C3_TCYC_SYS * 1 ns;
constant C3_NUM_DQ_PINS : integer := 16;
constant C3_MEM_ADDR_WIDTH : integer := 14;
constant C3_MEM_BANKADDR_WIDTH : integer := 3;
constant C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
constant C3_P0_MASK_SIZE : integer := 4;
constant C3_P0_DATA_PORT_SIZE : integer := 32;
constant C3_P1_MASK_SIZE : integer := 4;
constant C3_P1_DATA_PORT_SIZE : integer := 32;
constant C3_CALIB_SOFT_IP : string := "TRUE";
constant C3_SIMULATION : string := "TRUE";
-- ========================================================================== --
-- Component Declarations
-- ========================================================================== --
component example_top is
generic
(
C3_P0_MASK_SIZE : integer;
C3_P0_DATA_PORT_SIZE : integer;
C3_P1_MASK_SIZE : integer;
C3_P1_DATA_PORT_SIZE : integer;
C3_MEMCLK_PERIOD : integer;
C3_RST_ACT_LOW : integer;
C3_INPUT_CLK_TYPE : string;
DEBUG_EN : integer;
C3_CALIB_SOFT_IP : string;
C3_SIMULATION : string;
C3_HW_TESTING : string;
C3_MEM_ADDR_ORDER : string;
C3_NUM_DQ_PINS : integer;
C3_MEM_ADDR_WIDTH : integer;
C3_MEM_BANKADDR_WIDTH : integer
);
port
(
calib_done : out std_logic;
error : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_reset_n : out std_logic
);
end component;
component ddr3_model_c3 is
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_tdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
ba : in std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0);
addr : in std_logic_vector((C3_MEM_ADDR_WIDTH - 1) downto 0);
dq : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0);
dqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
dqs_n : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
tdqs_n : out std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
odt : in std_logic;
rst_n : in std_logic
);
end component;
-- ========================================================================== --
-- Signal Declarations --
-- ========================================================================== --
-- Clocks
signal c3_sys_clk : std_logic := '0';
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
-- System Reset
signal c3_sys_rst : std_logic := '0';
signal c3_sys_rst_i : std_logic;
-- Design-Top Port Map
signal mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
signal mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
signal mcb3_dram_dqs : std_logic;
signal mcb3_dram_dqs_n : std_logic;
signal mcb3_dram_dm : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_odt : std_logic;
signal mcb3_dram_reset_n : std_logic;
signal calib_done : std_logic;
signal error : std_logic;
signal mcb3_dram_udqs : std_logic;
signal mcb3_dram_udqs_n : std_logic;
signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_dqs_n_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_udm :std_logic; -- for X16 parts
signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0);
signal mcb3_command : std_logic_vector(2 downto 0);
signal mcb3_enable1 : std_logic;
signal mcb3_enable2 : std_logic;
signal rzq3 : std_logic;
function vector (asi:std_logic) return std_logic_vector is
variable v : std_logic_vector(0 downto 0) ;
begin
v(0) := asi;
return(v);
end function vector;
begin
-- ========================================================================== --
-- Clocks Generation --
-- ========================================================================== --
process
begin
c3_sys_clk <= not c3_sys_clk;
wait for (C3_TCYC_SYS_DIV2);
end process;
c3_sys_clk_p <= c3_sys_clk;
c3_sys_clk_n <= not c3_sys_clk;
-- ========================================================================== --
-- Reset Generation --
-- ========================================================================== --
process
begin
c3_sys_rst <= '0';
wait for 200 ns;
c3_sys_rst <= '1';
wait;
end process;
c3_sys_rst_i <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst);
rzq_pulldown3 : PULLDOWN port map(O => rzq3);
-- ========================================================================== --
-- DESIGN TOP INSTANTIATION --
-- ========================================================================== --
design_top : example_top generic map
(
C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
DEBUG_EN => DEBUG_EN,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C3_HW_TESTING => C3_HW_TESTING,
C3_SIMULATION => C3_SIMULATION,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP
)
port map (
calib_done => calib_done,
error => error,
c3_sys_clk => c3_sys_clk,
c3_sys_rst_i => c3_sys_rst_i,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
mcb3_rzq => rzq3,
mcb3_dram_dqs => mcb3_dram_dqs
);
-- ========================================================================== --
-- Memory model instances --
-- ========================================================================== --
mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n);
process(mcb3_dram_ck)
begin
if (rising_edge(mcb3_dram_ck)) then
if (c3_sys_rst = '0') then
mcb3_enable1 <= '0';
mcb3_enable2 <= '0';
elsif (mcb3_command = "100") then
mcb3_enable2 <= '0';
elsif (mcb3_command = "101") then
mcb3_enable2 <= '1';
else
mcb3_enable2 <= mcb3_enable2;
end if;
mcb3_enable1 <= mcb3_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb3_dram_dqs_vector(1 downto 0) <= (mcb3_dram_udqs & mcb3_dram_dqs)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
mcb3_dram_dqs_n_vector(1 downto 0) <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb3_dram_dqs <= mcb3_dram_dqs_vector(0)
when ( mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs <= mcb3_dram_dqs_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dqs_n <= mcb3_dram_dqs_n_vector(0)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs_n <= mcb3_dram_dqs_n_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm);
u_mem_c3 : ddr3_model_c3 port map
(
ck => mcb3_dram_ck,
ck_n => mcb3_dram_ck_n,
cke => mcb3_dram_cke,
cs_n => '0',
ras_n => mcb3_dram_ras_n,
cas_n => mcb3_dram_cas_n,
we_n => mcb3_dram_we_n,
dm_tdqs => mcb3_dram_dm_vector,
ba => mcb3_dram_ba,
addr => mcb3_dram_a,
dq => mcb3_dram_dq,
dqs => mcb3_dram_dqs_vector,
dqs_n => mcb3_dram_dqs_n_vector,
tdqs_n => open,
odt => mcb3_dram_odt,
rst_n => mcb3_dram_reset_n
);
-----------------------------------------------------------------------------
-- Reporting the test case status
-----------------------------------------------------------------------------
Logging: process
begin
wait for 200 us;
if (calib_done = '1') then
if (error = '0') then
report ("****TEST PASSED****");
else
report ("****TEST FAILED: DATA ERROR****");
end if;
else
report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
end if;
end process;
end architecture;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : sim_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:58 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Spartan-6
-- Design Name : DDR/DDR2/DDR3/LPDDR
-- Purpose : This is the simulation testbench which is used to verify the
-- design. The basic clocks and resets to the interface are
-- generated here. This also connects the memory interface to the
-- memory model.
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity sim_tb_top is
end entity sim_tb_top;
architecture arch of sim_tb_top is
-- ========================================================================== --
-- Parameters --
-- ========================================================================== --
constant DEBUG_EN : integer :=0;
constant C3_HW_TESTING : string := "FALSE";
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C3_MEMCLK_PERIOD : integer := 3000;
constant C3_RST_ACT_LOW : integer := 0;
constant C3_INPUT_CLK_TYPE : string := "SINGLE_ENDED";
constant C3_CLK_PERIOD_NS : real := 3000.0 / 1000.0;
constant C3_TCYC_SYS : real := C3_CLK_PERIOD_NS/2.0;
constant C3_TCYC_SYS_DIV2 : time := C3_TCYC_SYS * 1 ns;
constant C3_NUM_DQ_PINS : integer := 16;
constant C3_MEM_ADDR_WIDTH : integer := 14;
constant C3_MEM_BANKADDR_WIDTH : integer := 3;
constant C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
constant C3_P0_MASK_SIZE : integer := 4;
constant C3_P0_DATA_PORT_SIZE : integer := 32;
constant C3_P1_MASK_SIZE : integer := 4;
constant C3_P1_DATA_PORT_SIZE : integer := 32;
constant C3_CALIB_SOFT_IP : string := "TRUE";
constant C3_SIMULATION : string := "TRUE";
-- ========================================================================== --
-- Component Declarations
-- ========================================================================== --
component example_top is
generic
(
C3_P0_MASK_SIZE : integer;
C3_P0_DATA_PORT_SIZE : integer;
C3_P1_MASK_SIZE : integer;
C3_P1_DATA_PORT_SIZE : integer;
C3_MEMCLK_PERIOD : integer;
C3_RST_ACT_LOW : integer;
C3_INPUT_CLK_TYPE : string;
DEBUG_EN : integer;
C3_CALIB_SOFT_IP : string;
C3_SIMULATION : string;
C3_HW_TESTING : string;
C3_MEM_ADDR_ORDER : string;
C3_NUM_DQ_PINS : integer;
C3_MEM_ADDR_WIDTH : integer;
C3_MEM_BANKADDR_WIDTH : integer
);
port
(
calib_done : out std_logic;
error : out std_logic;
mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
c3_sys_clk : in std_logic;
c3_sys_rst_i : in std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_reset_n : out std_logic
);
end component;
component ddr3_model_c3 is
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_tdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
ba : in std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0);
addr : in std_logic_vector((C3_MEM_ADDR_WIDTH - 1) downto 0);
dq : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0);
dqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
dqs_n : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
tdqs_n : out std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
odt : in std_logic;
rst_n : in std_logic
);
end component;
-- ========================================================================== --
-- Signal Declarations --
-- ========================================================================== --
-- Clocks
signal c3_sys_clk : std_logic := '0';
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
-- System Reset
signal c3_sys_rst : std_logic := '0';
signal c3_sys_rst_i : std_logic;
-- Design-Top Port Map
signal mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
signal mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
signal mcb3_dram_dqs : std_logic;
signal mcb3_dram_dqs_n : std_logic;
signal mcb3_dram_dm : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_odt : std_logic;
signal mcb3_dram_reset_n : std_logic;
signal calib_done : std_logic;
signal error : std_logic;
signal mcb3_dram_udqs : std_logic;
signal mcb3_dram_udqs_n : std_logic;
signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_dqs_n_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_udm :std_logic; -- for X16 parts
signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0);
signal mcb3_command : std_logic_vector(2 downto 0);
signal mcb3_enable1 : std_logic;
signal mcb3_enable2 : std_logic;
signal rzq3 : std_logic;
function vector (asi:std_logic) return std_logic_vector is
variable v : std_logic_vector(0 downto 0) ;
begin
v(0) := asi;
return(v);
end function vector;
begin
-- ========================================================================== --
-- Clocks Generation --
-- ========================================================================== --
process
begin
c3_sys_clk <= not c3_sys_clk;
wait for (C3_TCYC_SYS_DIV2);
end process;
c3_sys_clk_p <= c3_sys_clk;
c3_sys_clk_n <= not c3_sys_clk;
-- ========================================================================== --
-- Reset Generation --
-- ========================================================================== --
process
begin
c3_sys_rst <= '0';
wait for 200 ns;
c3_sys_rst <= '1';
wait;
end process;
c3_sys_rst_i <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst);
rzq_pulldown3 : PULLDOWN port map(O => rzq3);
-- ========================================================================== --
-- DESIGN TOP INSTANTIATION --
-- ========================================================================== --
design_top : example_top generic map
(
C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
DEBUG_EN => DEBUG_EN,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C3_HW_TESTING => C3_HW_TESTING,
C3_SIMULATION => C3_SIMULATION,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP
)
port map (
calib_done => calib_done,
error => error,
c3_sys_clk => c3_sys_clk,
c3_sys_rst_i => c3_sys_rst_i,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
mcb3_rzq => rzq3,
mcb3_dram_dqs => mcb3_dram_dqs
);
-- ========================================================================== --
-- Memory model instances --
-- ========================================================================== --
mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n);
process(mcb3_dram_ck)
begin
if (rising_edge(mcb3_dram_ck)) then
if (c3_sys_rst = '0') then
mcb3_enable1 <= '0';
mcb3_enable2 <= '0';
elsif (mcb3_command = "100") then
mcb3_enable2 <= '0';
elsif (mcb3_command = "101") then
mcb3_enable2 <= '1';
else
mcb3_enable2 <= mcb3_enable2;
end if;
mcb3_enable1 <= mcb3_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb3_dram_dqs_vector(1 downto 0) <= (mcb3_dram_udqs & mcb3_dram_dqs)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
mcb3_dram_dqs_n_vector(1 downto 0) <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb3_dram_dqs <= mcb3_dram_dqs_vector(0)
when ( mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs <= mcb3_dram_dqs_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dqs_n <= mcb3_dram_dqs_n_vector(0)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs_n <= mcb3_dram_dqs_n_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm);
u_mem_c3 : ddr3_model_c3 port map
(
ck => mcb3_dram_ck,
ck_n => mcb3_dram_ck_n,
cke => mcb3_dram_cke,
cs_n => '0',
ras_n => mcb3_dram_ras_n,
cas_n => mcb3_dram_cas_n,
we_n => mcb3_dram_we_n,
dm_tdqs => mcb3_dram_dm_vector,
ba => mcb3_dram_ba,
addr => mcb3_dram_a,
dq => mcb3_dram_dq,
dqs => mcb3_dram_dqs_vector,
dqs_n => mcb3_dram_dqs_n_vector,
tdqs_n => open,
odt => mcb3_dram_odt,
rst_n => mcb3_dram_reset_n
);
-----------------------------------------------------------------------------
-- Reporting the test case status
-----------------------------------------------------------------------------
Logging: process
begin
wait for 200 us;
if (calib_done = '1') then
if (error = '0') then
report ("****TEST PASSED****");
else
report ("****TEST FAILED: DATA ERROR****");
end if;
else
report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
end if;
end process;
end architecture;
|
entity foo is end;
architecture bar of foo is
constant A : std.standard.SEVERITY_LEVEL;
constant B : SEVERITY_LEVEL := NOTE;
constant C : SEVERITY_LEVEL := WARNING;
constant D : SEVERITY_LEVEL := ERROR;
constant E : SEVERITY_LEVEL := FAILURE;
begin end;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_split_controller:1.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_split_controller_0_0 IS
PORT (
rgb_0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clock : IN STD_LOGIC;
hsync : IN STD_LOGIC;
rgb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END system_vga_split_controller_0_0;
ARCHITECTURE system_vga_split_controller_0_0_arch OF system_vga_split_controller_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_split_controller_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_split_controller IS
GENERIC (
HALF_ROW : INTEGER
);
PORT (
rgb_0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clock : IN STD_LOGIC;
hsync : IN STD_LOGIC;
rgb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT vga_split_controller;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clock: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
BEGIN
U0 : vga_split_controller
GENERIC MAP (
HALF_ROW => 320
)
PORT MAP (
rgb_0 => rgb_0,
rgb_1 => rgb_1,
clock => clock,
hsync => hsync,
rgb => rgb
);
END system_vga_split_controller_0_0_arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Stefan Naco
--
-- Create Date: 04:18:26 04/11/2017
-- Design Name:
-- Module Name: TOPLEVEL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TOPLEVEL is
Port ( clk_i : in STD_LOGIC;
toggle : in STD_LOGIC;
anodes : out STD_LOGIC_VECTOR (3 downto 0);
disp : out STD_LOGIC_VECTOR (0 to 7);
leds_data : out STD_LOGIC_VECTOR (4 downto 0);
led_p: out STD_LOGIC;
ledC : out STD_LOGIC;
carry_optional : out STD_LOGIC;
reset : in STD_LOGIC;
opcode : in STD_LOGIC_VECTOR (2 downto 0);
data : in STD_LOGIC_VECTOR (4 downto 0);
clear : in STD_LOGIC);
end TOPLEVEL;
architecture PORTMAP of TOPLEVEL is
COMPONENT clk_controller IS
PORT ( clk : in STD_LOGIC;
toggle : in STD_LOGIC;
reset : in STD_LOGIC;
clk_o : out STD_LOGIC);
END COMPONENT;
COMPONENT display_controller IS
PORT ( seg7 : out STD_LOGIC_VECTOR (0 to 7);
clk : in STD_LOGIC;
opcode : in STD_LOGIC_VECTOR (2 downto 0);
reset : in STD_LOGIC;
anodes : out STD_LOGIC_VECTOR (3 downto 0));
END COMPONENT;
COMPONENT shiftregister_5bit IS
PORT ( sel : in STD_LOGIC_VECTOR (2 downto 0);
A : out STD_LOGIC_VECTOR (4 downto 0);
clk : in STD_LOGIC;
C : out STD_LOGIC;
reset : in STD_LOGIC;
I : in STD_LOGIC_VECTOR (4 downto 0));
END COMPONENT;
COMPONENT debounce IS
PORT ( clk : in STD_LOGIC;
button : in STD_LOGIC;
result : out STD_LOGIC);
END COMPONENT;
signal reg_bus : std_logic_vector (4 downto 0);
signal clk1,t_p : std_logic;
signal command : std_logic_vector (2 downto 0);
begin
segment7 : display_controller PORT MAP(
anodes => anodes,
seg7 => disp,
opcode => command,
clk => clk_i,
reset => reset
);
cp : clk_controller PORT MAP(
clk => clk_i,
toggle => t_p,
reset => reset,
clk_o => clk1
);
reg : shiftregister_5bit PORT MAP(
sel => command,
A => reg_bus,
clk => clk1,
reset => clear,
I => data,
C => carry_optional
);
debA :debounce PORT MAP (
clk => clk_i,
button => toggle,
result => t_p
);
leds_data <= reg_bus;
command <= opcode;
ledC <= clk1;
led_p <= t_p;
end PORTMAP ;
|
-- File: serial_rx.vhd
-- Generated by MyHDL 0.8
-- Date: Thu Aug 21 10:54:44 2014
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity serial_rx is
port (
sysclk: in std_logic;
reset_n: in std_logic;
half_baud_rate_tick_i: in std_logic;
baud_rate_tick_i: in std_logic;
recieve_i: in std_logic;
data_o: out unsigned(7 downto 0);
ready_o: out std_logic
);
end entity serial_rx;
-- Serial
-- This module implements a reciever serial interface
--
-- Ports:
-- -----
-- sysclk: sysclk input
-- reset_n: reset input
-- half_baud_rate_tick_i: half baud rate tick
-- baud_rate_tick_i: the baud rate
-- n_stop_bits_i: number of stop bits
-- recieve_i: rx
-- data_o: the data output in 1 byte
-- ready_o: indicates data_o is valid
-- -----
architecture MyHDL of serial_rx is
constant n_stop_bits_i: integer := 2;
constant END_OF_BYTE: integer := 7;
type t_enum_t_State_1 is (
ST_WAIT_START_BIT,
ST_GET_DATA_BITS,
ST_GET_STOP_BITS
);
signal data_reg: unsigned(7 downto 0);
signal count_8_bits_reg: unsigned(2 downto 0);
signal data: unsigned(7 downto 0);
signal count_8_bits: unsigned(2 downto 0);
signal ready: std_logic;
signal state: t_enum_t_State_1;
signal count_stop_bits_reg: unsigned(2 downto 0);
signal count_stop_bits: unsigned(2 downto 0);
signal state_reg: t_enum_t_State_1;
signal ready_reg: std_logic;
begin
data_o <= data_reg;
ready_o <= ready_reg;
SERIAL_RX_SEQUENTIAL_PROCESS: process (sysclk, reset_n) is
begin
if (reset_n = '0') then
count_8_bits_reg <= to_unsigned(0, 3);
count_stop_bits_reg <= to_unsigned(0, 3);
ready_reg <= '0';
state_reg <= ST_WAIT_START_BIT;
data_reg <= to_unsigned(0, 8);
elsif rising_edge(sysclk) then
state_reg <= state;
data_reg <= data;
ready_reg <= ready;
count_8_bits_reg <= count_8_bits;
count_stop_bits_reg <= count_stop_bits;
end if;
end process SERIAL_RX_SEQUENTIAL_PROCESS;
SERIAL_RX_COMBINATIONAL_PROCESS: process (count_8_bits_reg, recieve_i, data_reg, baud_rate_tick_i, count_stop_bits_reg, state_reg, ready_reg) is
begin
state <= state_reg;
data <= data_reg;
ready <= ready_reg;
count_8_bits <= count_8_bits_reg;
count_stop_bits <= count_stop_bits_reg;
case state_reg is
when ST_WAIT_START_BIT =>
ready <= '0';
if (baud_rate_tick_i = '1') then
if (recieve_i = '0') then
state <= ST_GET_DATA_BITS;
end if;
end if;
when ST_GET_DATA_BITS =>
if (baud_rate_tick_i = '1') then
data(to_integer(count_8_bits_reg)) <= recieve_i;
if (count_8_bits_reg = END_OF_BYTE) then
count_8_bits <= to_unsigned(0, 3);
state <= ST_GET_STOP_BITS;
else
count_8_bits <= (count_8_bits_reg + 1);
state <= ST_GET_DATA_BITS;
end if;
end if;
when ST_GET_STOP_BITS =>
if (baud_rate_tick_i = '1') then
if (signed(resize(count_stop_bits_reg, 4)) = (n_stop_bits_i - 1)) then
count_stop_bits <= to_unsigned(0, 3);
ready <= '1';
state <= ST_WAIT_START_BIT;
else
count_stop_bits <= (count_stop_bits_reg + 1);
end if;
end if;
when others =>
assert False report "End of Simulation" severity Failure;
end case;
end process SERIAL_RX_COMBINATIONAL_PROCESS;
end architecture MyHDL;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: lookuptable1_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY lookuptable1_tb IS
END ENTITY;
ARCHITECTURE lookuptable1_tb_ARCH OF lookuptable1_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
lookuptable1_synth_inst:ENTITY work.lookuptable1_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: BRAM_ROM_CELL
-- AUTHORS: Tomáš Bannert <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity BRAM_ROM_CELL is
Port (
CLK : in std_logic;
ROM_ADDR : in std_logic_vector(8 downto 0);
ROM_DOUT : out std_logic_vector(31 downto 0)
);
end BRAM_ROM_CELL;
architecture FULL of BRAM_ROM_CELL is
type rom_t is array (0 to 511) of std_logic_vector(0 to 31);
constant ROM : rom_t :=
(
"11111111111111111111111111111111",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"10000000000000000000000000000001",
"11111111111111111111111111111111",
-- Dalsi obrazek (rovna 1=modra) -- 0001
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"11100000000000000000000000000111",
"11100000000000000000000000000111",
"11100000000000000000000000000111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11100000000000000000000000000111",
"11100000000000000000000000000111",
"11100000000000000000000000000111",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
-- Dalsi obrazek (zahnuta 1=modra) 0010
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"11100000000000000000000000000000",
"11100000000000000000000000000000",
"11100000000000000000000000000000",
"11111111111111111111111110000000",
"11111111111111111111111110000000",
"11111111111111111111111110000000",
"11111111111111111111111110000000",
"11111111111111111111111110000000",
"11111111111111111111111110000000",
"11111111111111111111111110000000",
"00000000000000001111111110000000",
"00000000000000001111111110000000",
"00000000000000000011111110000000",
"00000000000000000011111110000000",
"11111111111111000011111110000000",
"11111111111111000011111110000000",
"11111111111111000011111110000000",
"11111111111111000011111110000000",
"11111111111111000011111110000000",
"11111111111111000011111110000000",
"11111111111111000011111110000000",
"11100001111111000011111110000000",
"11100001111111000011111110000000",
"11100001111111000011111110000000",
"00000001111111000011111110000000",
"00001111111111000011111111110000",
"00001111111111000011111111110000",
"00001111111111000011111111110000",
-- Dalsi obrazek (T 1=modra) - 0011
"00001111111111000011111111110000",
"00001111111111000011111111110000",
"00001111111111000011111111110000",
"00000001111111000011111110000000",
"11100001111111000011111110000111",
"11100001111111000011111110000111",
"11100001111111000011111110000111",
"11111111111111000011111111111111",
"11111111111111000011111111111111",
"11111111111111000011111111111111",
"11111111111111000011111111111111",
"11111111111111000011111111111111",
"11111111111111000011111111111111",
"11111111111111000011111111111111",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"11111111111111000011111111111111",
"11111111111111000011111111111111",
"11111111111111000011111111111111",
"11111111111111000011111111111111",
"11111111111111000011111111111111",
"11111111111111000011111111111111",
"11111111111111000011111111111111",
"11100001111111000011111110000111",
"11100001111111000011111110000111",
"11100001111111000011111110000111",
"00000001111111000011111110000000",
"00001111111111000011111111110000",
"00001111111111000011111111110000",
"00001111111111000011111111110000",
-- Dalsi obrazek (spodni cast bocni trubky 1=modra) - 0100
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111001110011100111001110011111",
"11111001110011100111001110011111",
"01111111111111111111111111111110",
"01111111111111111111111111111110",
"01111111111111111111111111111110",
"00111111111111111111111111111100",
"00111111111111111111111111111100",
"00011111111111111111111111111000",
"00001111111111111111111111110000",
"00000111111111111111111111100000",
"00000011111111111111111111000000",
"00000001111111111111111110000000",
"00000000011111111111111000000000",
"00000000000011111111000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
-- Dalsi obrazek (telo trubky 1=bila 8x) - 0101
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
"00100000000000000000000000000100",
-- Dalsi obrazek (vrchni cast bocni trubky 1=modra) - 0110
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
-- Dalsi obrazek (propojka bocni trubky s hernim polem 1=modra) - 0111
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"11100000000000000000000000000111",
"11100000000000000000000000000111",
"11100000000000000000000000000111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11100000000000000000000000000111",
"11100000000000000000000000000111",
"11100000000000000000000000000111",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
-- Dalsi obrazek (koncova trubka 1=modra) - 1000
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"11100000000000000000000000000111",
"11100000000000000000000000000111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111000011111111111111",
"11111111111100111100111111111111",
"11111111111001111110011111111111",
"11111111111010111101011111111111",
"11111111110111011011101111111111",
"11111111110111100111101111111111",
"11111111110111100111101111111111",
"11111111110111011011101111111111",
"11111111111010111101011111111111",
"11111111111001111110011111111111",
"11111111111100111100111111111111",
"11111111111111000011111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11100000000000000000000000000111",
"11100000000000000000000000000111",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
-- text1 (bila) - 1001
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00011110000111100001111110000111",
"00011110000111100001111110000111",
"00011001100110011001100000011000",
"00011001100110011001100000011000",
"00011110000111100001111000000110",
"00011110000111100001111000000110",
"00011000000110011001100000000001",
"00011000000110011001100000000001",
"00011000000110011001111110011110",
"00011000000110011001111110011110",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000001100001",
"00000000000000000000000001100001",
"00000000000000000000000110011001",
"00000000000000000000000110011001",
"00000000000000000000000110011001",
"00000000000000000000000110011001",
"00000000000000000000000110011001",
"00000000000000000000000110011001",
"00000000000000000000000001100001",
"00000000000000000000000001100001",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
-- Dalsi obrazek (tenka trubka ke startovni ohnuta 1=modra) - 1010
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000000111100000000000000",
"00000000000001111100000000000000",
"00000000000011111100000000000000",
"11111111111111111000000000000000",
"11111111111111111000000000000000",
"11111111111111110000000000000000",
"11111111111111000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
-- Dalsi obrazek (tenka trubka ke startovni rovna 1=modra) - 1011
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"11111111111111111111111111111111",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
-- Dalsi obrazek (cihla 1=cervena) - 1100
"01111111011111110111111101111111",
"01111111011111110111111101111111",
"01111111011111110111111101111111",
"00000000000000000000000000000000",
"11110111111101111111011111110111",
"11110111111101111111011111110111",
"11110111111101111111011111110111",
"00000000000000000000000000000000",
"01111111011111110111111101111111",
"01111111011111110111111101111111",
"01111111011111110111111101111111",
"00000000000000000000000000000000",
"11110111111101111111011111110111",
"11110111111101111111011111110111",
"11110111111101111111011111110111",
"00000000000000000000000000000000",
"01111111011111110111111101111111",
"01111111011111110111111101111111",
"01111111011111110111111101111111",
"00000000000000000000000000000000",
"11110111111101111111011111110111",
"11110111111101111111011111110111",
"11110111111101111111011111110111",
"00000000000000000000000000000000",
"01111111011111110111111101111111",
"01111111011111110111111101111111",
"01111111011111110111111101111111",
"00000000000000000000000000000000",
"11110111111101111111011111110111",
"11110111111101111111011111110111",
"11110111111101111111011111110111",
"00000000000000000000000000000000",
-- text2 (bila) - 1101
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000011000000000011000",
"00000000000000011000000000011000",
"10000111100000011000011110011000",
"10000111100000011000011110011000",
"00011000000000000001100000000000",
"00011000000000000001100000000000",
"00000110000000000000011000000000",
"00000110000000000000011000000000",
"10000001100000000000000110000000",
"10000001100000000000000110000000",
"00011110000000000001111000000000",
"00011110000000000001111000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"11100001100110011000011000011001",
"11100001100110011000011000011001",
"10011001100110011001100110011001",
"10011001100110011001100110011001",
"11100001100110011001100110011001",
"11100001100110011001100110011001",
"10011000011000011001100110011001",
"10011000011000011001100110011001",
"11100000011000011000011000000110",
"11100000011000011000011000000110",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
-- text3 (bila) - 1110
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00011111100001100000000001111001",
"00011111100001100000000001111001",
"00000110000110011000000110000000",
"00000110000110011000000110000000",
"00000110000110011000000001100000",
"00000110000110011000000001100000",
"00000110000110011000000000011000",
"00000110000110011000000000011000",
"00000110000001100000000111100000",
"00000110000001100000000111100000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000111100110000001100110000000",
"00000111100110000001100110000000",
"00011000000110000001100110000000",
"00011000000110000001100110000000",
"00000110000110000000011000000000",
"00000110000110000000011000000000",
"00000001100110000000011000000000",
"00000001100110000000011000000000",
"00011110000111111000011000011000",
"00011110000111111000011000011000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
-- text4 (bila) - 1111
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"11111000011000011110000111111000",
"11111000011000011110000111111000",
"01100001100110011001100001100000",
"01100001100110011001100001100000",
"01100001100110011110000001100000",
"01100001100110011110000001100000",
"01100001111110011001100001100000",
"01100001111110011001100001100000",
"01100001100110011001100001100000",
"01100001100110011001100001100000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00011000000000000000000000000000",
"00011000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
"00000000000000000000000000000000",
others => (others => '0')
);
begin
process (CLK)
begin
if (rising_edge(CLK)) then
ROM_DOUT <= ROM(to_integer(unsigned(ROM_ADDR)));
end if;
end process;
end FULL;
|
-------------------------------------------------------------------------------------
-- FILE NAME : data_check.vhd
-- AUTHOR : Luis
-- COMPANY :
-- UNITS : Entity -
-- Architecture - Behavioral
-- LANGUAGE : VHDL
-- DATE : AUG 21, 2014
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
--
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- LIBRARIES
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- IEEE
--use ieee.numeric_std.all;
-- non-IEEE
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
Library UNISIM;
use UNISIM.vcomponents.all;
-------------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------------
entity data_check is
port (
clk_in : in std_logic;
rst_in : in std_logic;
data_in : in std_logic_vector(63 downto 0);
valid_in : in std_logic;
check_en_in : in std_logic;
status_out : out std_logic_vector(7 downto 0)
);
end data_check;
-------------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------------
architecture Behavioral of data_check is
-------------------------------------------------------------------------------------
-- CONSTANTS
-------------------------------------------------------------------------------------
type state_machine is (HOLD_CMD, BYTE0_CMD, BYTE1_CMD, BYTE2_CMD);
type bus008 is array(natural range <>) of std_logic_vector(7 downto 0);
-------------------------------------------------------------------------------------
-- SIGNALS
-------------------------------------------------------------------------------------
signal recv_sm_reg : state_machine;
signal byte_in : bus008(7 downto 0);
signal byte_check : bus008(7 downto 0);
signal byte_error : std_logic_vector(7 downto 0);
signal run_test : std_logic;
signal valid_reg : std_logic;
signal data_reg : std_logic_vector(63 downto 0);
signal samples8bit : bus008(7 downto 0) := (others=>(others=>'0'));
signal base_cnt : std_logic_vector(7 downto 0);
signal generate_data : std_logic_vector(63 downto 0);
--***********************************************************************************
begin
--***********************************************************************************
run_test <= check_en_in;
status_out(7 downto 0) <= byte_error(7 downto 0);
-------------------------------------------------------------------------------------
-- Counter process
-------------------------------------------------------------------------------------
process(clk_in, rst_in)
begin
if rising_edge(clk_in) then
if rst_in = '1' then
for I in 0 to 7 loop
byte_in(I) <= (others=>'0');
byte_check(I) <= (others=>'0');
end loop;
valid_reg <= '0';
base_cnt <= (others=>'0');
data_reg <= (others=>'0');
byte_error <= (others=>'0');
else
base_cnt <= data_in(7 downto 0);
data_reg <= data_in;
valid_reg <= valid_in;
byte_in(0) <= data_reg(7 downto 0);
byte_in(1) <= data_reg(15 downto 8);
byte_in(2) <= data_reg(23 downto 16);
byte_in(3) <= data_reg(31 downto 24);
byte_in(4) <= data_reg(39 downto 32);
byte_in(5) <= data_reg(47 downto 40);
byte_in(6) <= data_reg(55 downto 48);
byte_in(7) <= data_reg(63 downto 56);
if run_test = '1' and valid_reg = '1' then
base_cnt <= base_cnt + 2;
byte_check(0) <= base_cnt + 0;
byte_check(1) <= base_cnt + 0;
byte_check(2) <= base_cnt + 0;
byte_check(3) <= base_cnt + 0;
byte_check(4) <= base_cnt + 1;
byte_check(5) <= base_cnt + 1;
byte_check(6) <= base_cnt + 1;
byte_check(7) <= base_cnt + 1;
else
byte_check(0) <= data_reg(7 downto 0);
byte_check(1) <= data_reg(15 downto 8);
byte_check(2) <= data_reg(23 downto 16);
byte_check(3) <= data_reg(31 downto 24);
byte_check(4) <= data_reg(39 downto 32);
byte_check(5) <= data_reg(47 downto 40);
byte_check(6) <= data_reg(55 downto 48);
byte_check(7) <= data_reg(63 downto 56);
end if;
for I in 0 to 7 loop
if byte_in(I) /= byte_check(I) and run_test = '1' and valid_reg = '1' then
byte_error(I) <= '1';
end if;
end loop;
end if;
end if;
end process;
--process(clk_in, rst_in)
--begin
-- if rising_edge(clk_in) then
-- if rst_in = '1' then
-- base_cnt <= (others =>'0');
-- else
-- base_cnt <= base_cnt + 2;
-- end if;
-- end if;
--end process;
--samples8bit(0) <= base_cnt + 0;
--samples8bit(1) <= base_cnt + 0;
--samples8bit(2) <= base_cnt + 0;
--samples8bit(3) <= base_cnt + 0;
--samples8bit(4) <= base_cnt + 1;
--samples8bit(5) <= base_cnt + 1;
--samples8bit(6) <= base_cnt + 1;
--samples8bit(7) <= base_cnt + 1;
-------------------------------------------------------------------------------------
-- Component Instance
-------------------------------------------------------------------------------------
--inst0_vp680_nnn_lx130t:
--entity work.vp680_nnn_lx130t
--generic map (
-- DEBUG => FALSE,
-- ADDRESS => "00010111111"
--)
--port map (
-- gpio_led_8 => ,
-- sys_clk_p_8 => ,
-- sys_clk_n_8 => ,
-- sys_reset_n_8 => ,
-- pci_exp_rxn_8 => ,
-- pci_exp_rxp_8 => ,
-- pci_exp_txn_8 => ,
-- pci_exp_txp_8 => ,
-- fp_cp_8 => ,
-- host_if_i2c_scl_8 =>
--);
-------------------------------------------------------------------------------------
-- Debug
-------------------------------------------------------------------------------------
--generate_debug:
--if (DEBUG_ENABLE = TRUE) generate
--begin
--
--end generate;
--generate_add_loop:
--for I in 0 to 7 generate
-- SUM(I) <= A(I) xor B(I) xor C(I);
-- C(I+1) <= (A(I) and B(I)) or (A(I) and C(I)) or (B(I) and C(I));
--end generate;
--***********************************************************************************
end architecture Behavioral;
--***********************************************************************************
|
--------------------------------------------------------------------------------
-- Title : Utilities package
-- Project :
--------------------------------------------------------------------------------
-- File : src_utils_pkg.vhd
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 02.06.2011
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- utilities to foster source code programming
--------------------------------------------------------------------------------
-- Hierarchy :
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package src_utils_pkg is
constant TYPE_IS_MEMORY : std_logic_vector(4 downto 0) := "00000";
constant TYPE_IS_IO : std_logic_vector(4 downto 0) := "00010";
constant TYPE_IS_CPL : std_logic_vector(4 downto 0) := "01010";
constant FMT_IS_READ : std_logic_vector(2 downto 0) := "000";
constant FMT_IS_WRITE : std_logic_vector(2 downto 0) := "010";
constant ZERO_02B : std_logic_vector(1 downto 0) := "00";
constant ZERO_03B : std_logic_vector(2 downto 0) := "000";
constant ZERO_04B : std_logic_vector(3 downto 0) := x"0";
constant ZERO_10B : std_logic_vector(9 downto 0) := "0000000000";
constant ZERO_11B : std_logic_vector(10 downto 0) := "00000000000";
constant ZERO_12B : std_logic_vector(11 downto 0) := x"000";
constant ZERO_20B : std_logic_vector(19 downto 0) := x"00000";
constant ONE_02B : std_logic_vector(1 downto 0) := "01";
constant ONE_03B : std_logic_vector(2 downto 0) := "001";
constant ONE_04B : std_logic_vector(3 downto 0) := x"1";
constant ONE_05B : std_logic_vector(4 downto 0) := "00001";
constant ONE_10B : std_logic_vector(9 downto 0) := "0000000001";
constant ONE_11B : std_logic_vector(10 downto 0) := "00000000001";
constant ONE_12B : std_logic_vector(11 downto 0) := x"001";
constant TWO_02B : std_logic_vector(1 downto 0) := "10";
constant TWO_03B : std_logic_vector(2 downto 0) := "010";
constant TWO_04B : std_logic_vector(3 downto 0) := x"2";
constant TWO_10B : std_logic_vector(9 downto 0) := "0000000010";
constant TWO_11B : std_logic_vector(10 downto 0) := "00000000010";
constant TWO_12B : std_logic_vector(11 downto 0) := x"002";
constant THREE_02B : std_logic_vector(1 downto 0) := "11";
constant THREE_03B : std_logic_vector(2 downto 0) := "011";
constant THREE_04B : std_logic_vector(3 downto 0) := x"3";
constant THREE_10B : std_logic_vector(9 downto 0) := "0000000011";
constant THREE_12B : std_logic_vector(11 downto 0) := x"003";
constant FOUR_03B : std_logic_vector(2 downto 0) := "100";
constant FOUR_04B : std_logic_vector(3 downto 0) := x"4";
constant FOUR_12B : std_logic_vector(11 downto 0) := x"004";
constant FOUR_32B : std_logic_vector(31 downto 0) := x"00000004";
constant FIVE_12B : std_logic_vector(11 downto 0) := x"005";
constant SIX_04B : std_logic_vector(3 downto 0) := x"6";
constant SIX_12B : std_logic_vector(11 downto 0) := x"006";
constant EIGHT_04B : std_logic_vector(3 downto 0) := x"8";
constant EIGHT_32B : std_logic_vector(31 downto 0) := x"00000008";
constant C_04B : std_logic_vector(3 downto 0) := x"C";
constant FULL_03B : std_logic_vector(2 downto 0) := "111";
constant FULL_10B : std_logic_vector(9 downto 0) := "1111111111";
constant X_400_11B : std_logic_vector(10 downto 0) := "10000000000";
end src_utils_pkg;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CU is
port (
clk, ExternalReset,
carry, zero, sign, parity, borrow, overflow -- status register
: in STD_LOGIC;
IRout : in STD_LOGIC_VECTOR(15 downto 0); -- IR
reg0 : in STD_LOGIC_VECTOR(15 downto 0); -- Register(0)
ALUout_on_Databus, -- Data Bus
IRload, -- IR
ResetPC, Im, PCplus1, EnablePC, -- Address Unit
W_EN, -- register file
we, re, -- memory
itype
: out STD_LOGIC;
-- ALU's bits
alu_operation : out std_logic_vector(3 downto 0);
databus : inout std_logic_vector(15 downto 0)
);
end entity;
architecture CU_ARCH of CU is
type state is (reset, fetch, baseExe, halt, PCInc, shiftRighting, shiftLefting);
signal currentState : state := reset;
signal nextState : state;
constant add : STD_LOGIC_VECTOR(3 downto 0) := "0000";
constant sub : STD_LOGIC_VECTOR(3 downto 0) := "0001";
constant andD : STD_LOGIC_VECTOR(3 downto 0) := "0010";
constant orD : STD_LOGIC_VECTOR(3 downto 0) := "0011";
constant xorD : STD_LOGIC_VECTOR(3 downto 0) := "0100";
constant notD : STD_LOGIC_VECTOR(3 downto 0) := "0101";
constant mul : STD_LOGIC_VECTOR(3 downto 0) := "0110";
constant jmp : STD_LOGIC_VECTOR(3 downto 0) := "0111";
constant addi : STD_LOGIC_VECTOR(3 downto 0) := "1000";
constant srlD : STD_LOGIC_VECTOR(3 downto 0) := "1001";
constant andi : STD_LOGIC_VECTOR(3 downto 0) := "1010";
constant ori : STD_LOGIC_VECTOR(3 downto 0) := "1011";
constant sllD : STD_LOGIC_VECTOR(3 downto 0) := "1100";
constant store : STD_LOGIC_VECTOR(3 downto 0) := "1101";
constant load : STD_LOGIC_VECTOR(3 downto 0) := "1110";
constant brnz : STD_LOGIC_VECTOR(3 downto 0) := "1111";
---------- ALU Operations ----------------------
constant ALU_and : std_logic_vector (3 downto 0) := "0000";
constant ALU_or : std_logic_vector (3 downto 0) := "0001";
constant ALU_xor : std_logic_vector (3 downto 0) := "0010";
constant ALU_sl : std_logic_vector (3 downto 0) := "0100";
constant ALU_sr : std_logic_vector (3 downto 0) := "0101";
constant ALU_add : std_logic_vector (3 downto 0) := "0110";
constant ALU_mul : std_logic_vector (3 downto 0) := "1001";
constant ALU_sub : std_logic_vector (3 downto 0) := "0111";
constant ALU_not : std_logic_vector (3 downto 0) := "1000";
constant ALU_input2 : std_logic_vector (3 downto 0) := "1010";
signal Immediate : std_logic_vector(7 downto 0);
signal shiftTempSig : std_logic_vector(15 downto 0);
begin
Immediate <= IRout(7 downto 0);
-- state changer
process (clk, ExternalReset)
begin
if ExternalReset = '1' then
currentState <= reset;
elsif clk'event and clk = '1' then
currentState <= nextState;
end if;
end process;
-- control signals base on state
process (currentState)
variable shiftCounter : integer;
begin
-- set defaults
ALUout_on_Databus <= '0';
IRload <= '0';
ResetPC <= '0';
EnablePC <= '0';
PCplus1 <= '0';
itype <= '0';
ALUout_on_Databus <= '0';
W_EN <= '0';
we <= '0';
re <= '0';
case currentState is
when halt =>
nextState <= halt;
when reset =>
ResetPC <= '1';
EnablePC <= '1';
nextState <= fetch;
when fetch =>
re <= '1';
IRload <= '1';
nextState <= baseExe;
when baseExe =>
case IRout(15 downto 12) is
when add =>
alu_operation <= ALU_add;
PCplus1 <= '1';
EnablePC <= '1';
ALUout_on_Databus <= '1';
W_EN <='1';
nextState <= fetch;
when addi =>
alu_operation <= ALU_add;
PCplus1 <= '1';
EnablePC <= '1';
itype <= '1';
ALUout_on_Databus <= '1';
W_EN <='1';
nextState <= fetch;
when sub =>
alu_operation <= ALU_sub;
PCplus1 <= '1';
EnablePC <= '1';
ALUout_on_Databus <= '1';
W_EN <='1';
nextState <= fetch;
when andD =>
alu_operation <= ALU_and;
PCplus1 <= '1';
EnablePC <= '1';
ALUout_on_Databus <= '1';
W_EN <='1';
nextState <= fetch;
when andi =>
alu_operation <= ALU_and;
PCplus1 <= '1';
EnablePC <= '1';
itype <= '1';
ALUout_on_Databus <= '1';
W_EN <='1';
nextState <= fetch;
when orD =>
alu_operation <= ALU_or;
PCplus1 <= '1';
EnablePC <= '1';
ALUout_on_Databus <= '1';
W_EN <='1';
nextState <= fetch;
when ori =>
alu_operation <= ALU_or;
PCplus1 <= '1';
EnablePC <= '1';
itype <= '1';
ALUout_on_Databus <= '1';
W_EN <='1';
nextState <= fetch;
when xorD =>
alu_operation <= ALU_xor;
PCplus1 <= '1';
EnablePC <= '1';
ALUout_on_Databus <= '1';
W_EN <='1';
nextState <= fetch;
when notD =>
alu_operation <= ALU_not;
PCplus1 <= '1';
EnablePC <= '1';
ALUout_on_Databus <= '1';
W_EN <='1';
nextState <= fetch;
when mul =>
alu_operation <= ALU_mul;
PCplus1 <= '1';
EnablePC <= '1';
ALUout_on_Databus <= '1';
W_EN <='1';
nextState <= fetch;
when jmp =>
nextState <= fetch;
Im <= '1';
EnablePC <= '1';
when brnz =>
alu_operation <= ALU_sub;
if (reg0 = "0000000000000000") then -- if reg(0) is 0
nextState <= fetch;
Im <= '1';
EnablePC <= '1';
else
nextState <= fetch;
EnablePC <= '1';
PCplus1 <= '1';
end if;
when store =>
Im <= '1';
we <= '1';
alu_operation <= ALU_input2;
ALUout_on_Databus <= '1';
nextState <= PCInc;
when load =>
Im <='1';
re <= '1';
W_EN <='1';
nextState <= PCInc;
when srlD =>
shiftCounter := to_integer(unsigned(Immediate));
alu_operation <= ALU_input2;
ALUout_on_Databus <= '1';
W_EN <='1';
shiftTempSig <= databus;
nextState <= shiftRighting;
when sllD =>
shiftCounter := to_integer(unsigned(Immediate));
alu_operation <= ALU_input2;
ALUout_on_Databus <= '1';
W_EN <='1';
shiftTempSig <= databus;
nextState <= shiftLefting;
when others =>
assert false report "X is out";
end case;
when PCInc =>
PCplus1 <= '1';
EnablePC <= '1';
nextState <= fetch;
when shiftRighting =>
case to_integer(unsigned(Immediate)) is
when 0 =>
ALUout_on_Databus <= '1';
W_EN <='1';
PCplus1 <= '1';
EnablePC <= '1';
nextState <= fetch;
when OTHERS =>
nextState <= shiftRighting;
end case;
shiftCounter := shiftCounter - 1;
when shiftLefting =>
case to_integer(unsigned(Immediate)) is
when 0 =>
ALUout_on_Databus <= '1';
W_EN <='1';
PCplus1 <= '1';
EnablePC <= '1';
nextState <= fetch;
when OTHERS =>
shiftTempSig <= shiftTempSig(14 downto 0) & '0';
nextState <= shiftLefting;
end case;
shiftCounter := shiftCounter - 1;
-- when comparator =>
when OTHERS =>
nextState <= reset;
end case;
end process;
end architecture;
|
-- Based on xwb_fabric_source.vhd from Tomasz Wlostowski
--
-- Modified by Lucas Russo <[email protected]> for multiple width support
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.genram_pkg.all;
use work.wb_stream_generic_pkg.all;
entity wb_stream_source_gen is
generic (
--g_wbs_adr_width : natural := c_wbs_adr4_width;
g_wbs_interface_width : t_wbs_interface_width := LARGE1
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Streaming Interface I/O.
-- Only the used interface should be connected. The others can be left unconnected
-- 16-bit interface
src_adr16_o : out t_wbs_adr4;
src_dat16_o : out t_wbs_dat16;
src_sel16_o : out t_wbs_sel16;
-- 32-bit interface
src_adr32_o : out t_wbs_adr4;
src_dat32_o : out t_wbs_dat32;
src_sel32_o : out t_wbs_sel32;
-- 64-bit interface
src_adr64_o : out t_wbs_adr4;
src_dat64_o : out t_wbs_dat64;
src_sel64_o : out t_wbs_sel64;
-- 128-bit interface
src_adr128_o : out t_wbs_adr4;
src_dat128_o : out t_wbs_dat128;
src_sel128_o : out t_wbs_sel128;
-- Common Wishbone Streaming lines
src_cyc_o : out std_logic;
src_stb_o : out std_logic;
src_we_o : out std_logic;
src_ack_i : in std_logic := '0';
src_stall_i : in std_logic := '0';
src_err_i : in std_logic := '0';
src_rty_i : in std_logic := '0';
-- Decoded & buffered logic
-- Only the used interface must be connected. The others can be left unconnected
-- 16-bit interface
adr16_i : in std_logic_vector(c_wbs_adr4_width-1 downto 0) := cc_dummy_wbs_adr4;
dat16_i : in std_logic_vector(c_wbs_dat16_width-1 downto 0) := cc_dummy_wbs_dat16;
sel16_i : in std_logic_vector(c_wbs_sel16_width-1 downto 0) := cc_dummy_wbs_sel16;
-- 32-bit interface
adr32_i : in std_logic_vector(c_wbs_adr4_width-1 downto 0) := cc_dummy_wbs_adr4;
dat32_i : in std_logic_vector(c_wbs_dat32_width-1 downto 0) := cc_dummy_wbs_dat32;
sel32_i : in std_logic_vector(c_wbs_sel32_width-1 downto 0) := cc_dummy_wbs_sel32;
-- 64-bit interface
adr64_i : in std_logic_vector(c_wbs_adr4_width-1 downto 0) := cc_dummy_wbs_adr4;
dat64_i : in std_logic_vector(c_wbs_dat64_width-1 downto 0) := cc_dummy_wbs_dat64;
sel64_i : in std_logic_vector(c_wbs_sel64_width-1 downto 0) := cc_dummy_wbs_sel64;
-- 128-bit interface
adr128_i : in std_logic_vector(c_wbs_adr4_width-1 downto 0) := cc_dummy_wbs_adr4;
dat128_i : in std_logic_vector(c_wbs_dat128_width-1 downto 0) := cc_dummy_wbs_dat128;
sel128_i : in std_logic_vector(c_wbs_sel128_width-1 downto 0) := cc_dummy_wbs_sel128;
-- Common lines
dvalid_i : in std_logic := '0';
sof_i : in std_logic := '0';
eof_i : in std_logic := '0';
error_i : in std_logic := '0';
dreq_o : out std_logic
);
end wb_stream_source_gen;
architecture rtl of wb_stream_source_gen is
-- Convert enum to natural
constant c_wbs_dat_width : natural := f_conv_wbs_interface_width(g_wbs_interface_width);
constant c_wbs_sel_width : natural := c_wbs_dat_width/8;
-- Fixed 4-bit address as we do not exceptct it to address real peripheral
-- just to inform some other conditions
constant c_wbs_adr_width : natural := c_wbs_adr4_width;
-- FIFO ranges and control bits location
constant c_dat_lsb : natural := 0;
constant c_dat_msb : natural := c_dat_lsb + c_wbs_dat_width - 1;
constant c_adr_lsb : natural := c_dat_msb + 1;
constant c_adr_msb : natural := c_adr_lsb + c_wbs_adr_width - 1;
constant c_valid_bit : natural := c_adr_msb + 1;
constant c_sel_lsb : natural := c_valid_bit + 1;
constant c_sel_msb : natural := c_sel_lsb + c_wbs_sel_width - 1;
constant c_eof_bit : natural := c_sel_msb + 1;
constant c_sof_bit : natural := c_eof_bit + 1;
constant c_logic_width : integer := c_sof_bit - c_valid_bit + 1;
constant c_fifo_width : integer := c_sof_bit - c_dat_lsb + 1;
constant c_fifo_depth : integer := 32;
-- Signals
signal q_valid, full, we, rd, rd_d0 : std_logic;
signal fin, fout : std_logic_vector(c_fifo_width-1 downto 0);
signal pre_dvalid, pre_sof : std_logic;
signal pre_eof : std_logic;
signal pre_dat : std_logic_vector(c_wbs_dat_width-1 downto 0);
signal pre_adr : std_logic_vector(c_wbs_adr_width-1 downto 0);
signal pre_sel : std_logic_vector(c_wbs_sel_width-1 downto 0);
signal post_dvalid, post_sof : std_logic;
signal post_eof : std_logic;
signal post_sel : std_logic_vector(c_wbs_sel_width-1 downto 0);
signal post_dat : std_logic_vector(c_wbs_dat_width-1 downto 0);
signal post_adr : std_logic_vector(c_wbs_adr_width-1 downto 0);
signal err_status : t_wbs_status_reg;
signal cyc_int : std_logic;
function f_gen_zeros(size : natural)
return std_logic_vector is
variable zeros : std_logic_vector(size-1 downto 0) := (others => '0');
begin
return zeros;
end f_gen_zeros;
begin -- rtl
err_status.error <= '1';
dreq_o <= not full;
rd <= not src_stall_i;
we <= sof_i or eof_i or error_i or dvalid_i;
pre_dvalid <= dvalid_i or error_i;
pre_eof <= error_i or eof_i;
-----------------------------
-- Wishbone Streaming Interface selection
-----------------------------
gen_16_bit_interface_in : if g_wbs_interface_width = NARROW2 generate
pre_dat <= dat16_i when (error_i = '0') else f_gen_zeros(pre_dat'length-c_wbs_status_width) &
f_marshall_wbs_status(err_status);
pre_adr <= adr16_i when (error_i = '0') else std_logic_vector(resize(c_WBS_STATUS, pre_adr'length));
pre_sel <= sel16_i;
end generate;
gen_32_bit_interface_in : if g_wbs_interface_width = NARROW1 generate
pre_dat <= dat32_i when (error_i = '0') else f_gen_zeros(pre_dat'length-c_wbs_status_width) &
f_marshall_wbs_status(err_status);
pre_adr <= adr32_i when (error_i = '0') else std_logic_vector(resize(c_WBS_STATUS, pre_adr'length));
pre_sel <= sel32_i;
end generate;
gen_64_bit_interface_in : if g_wbs_interface_width = LARGE1 generate
pre_dat <= dat64_i when (error_i = '0') else f_gen_zeros(pre_dat'length-c_wbs_status_width) &
f_marshall_wbs_status(err_status);
pre_adr <= adr64_i when (error_i = '0') else std_logic_vector(resize(c_WBS_STATUS, pre_adr'length));
pre_sel <= sel64_i;
end generate;
gen_128_bit_interface_in : if g_wbs_interface_width = LARGE2 generate
pre_dat <= dat128_i when (error_i = '0') else f_gen_zeros(pre_dat'length-c_wbs_status_width) &
f_marshall_wbs_status(err_status);
pre_adr <= adr128_i when (error_i = '0') else std_logic_vector(resize(c_WBS_STATUS, pre_adr'length));
pre_sel <= sel128_i;
end generate;
fin <= sof_i & pre_eof & pre_sel & pre_dvalid & pre_adr & pre_dat;
cmp_fifo : generic_shiftreg_fifo
generic map (
g_data_width => c_fifo_width,
g_size => c_fifo_depth
)
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
d_i => fin,
we_i => we,
q_o => fout,
rd_i => rd,
almost_full_o => full,
q_valid_o => q_valid
);
post_sof <= fout(c_sof_bit);
post_eof <= fout(c_eof_bit);
post_dvalid <= fout(c_valid_bit);
post_sel <= fout(c_sel_msb downto c_sel_lsb);
post_dat <= fout(c_dat_msb downto c_dat_lsb);
post_adr <= fout(c_adr_msb downto c_adr_lsb);
p_gen_cyc : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
cyc_int <= '0';
else
if(src_stall_i = '0' and q_valid = '1') then
-- SOF and SOF signals must be one clock cycle long
-- and must be asserted at the same clock edge as the valid
-- signal!
if(post_sof = '1') then --or post_eof = '1')then
cyc_int <= '1';
elsif(post_eof = '1') then
cyc_int <= '0';
end if;
end if;
end if;
end if;
end process;
src_cyc_o <= cyc_int or post_sof;
src_we_o <= '1';
src_stb_o <= post_dvalid and q_valid;
-----------------------------
-- Wishbone Streaming Interface selection
-----------------------------
gen_16_bit_interface_out : if g_wbs_interface_width = NARROW2 generate
src_sel16_o <= post_sel;
src_dat16_o <= post_dat;
src_adr16_o <= post_adr;
end generate;
gen_32_bit_interface_out : if g_wbs_interface_width = NARROW1 generate
src_sel32_o <= post_sel;
src_dat32_o <= post_dat;
src_adr32_o <= post_adr;
end generate;
gen_64_bit_interface_out : if g_wbs_interface_width = LARGE1 generate
src_sel64_o <= post_sel;
src_dat64_o <= post_dat;
src_adr64_o <= post_adr;
end generate;
gen_128_bit_interface_out : if g_wbs_interface_width = LARGE2 generate
src_sel128_o <= post_sel;
src_dat128_o <= post_dat;
src_adr128_o <= post_adr;
end generate;
end rtl;
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:15:04 12/17/2013
-- Design Name:
-- Module Name: logi_virtual_sw - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity logi_virtual_sw is
generic(
wb_size : natural := 16 -- Data port size for wishbone
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
sw : out std_logic_vector(15 downto 0)
);
end logi_virtual_sw;
architecture Behavioral of logi_virtual_sw is
signal reg_out_d : std_logic_vector(15 downto 0) ;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
reg_out_d <= (others => '0');
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
reg_out_d <= wbs_writedata;
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
sw <= reg_out_d ;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
end Behavioral;
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:15:04 12/17/2013
-- Design Name:
-- Module Name: logi_virtual_sw - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity logi_virtual_sw is
generic(
wb_size : natural := 16 -- Data port size for wishbone
);
port
(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
-- out signals
sw : out std_logic_vector(15 downto 0)
);
end logi_virtual_sw;
architecture Behavioral of logi_virtual_sw is
signal reg_out_d : std_logic_vector(15 downto 0) ;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
reg_out_d <= (others => '0');
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
reg_out_d <= wbs_writedata;
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
sw <= reg_out_d ;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
end Behavioral;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0;
USE axi_bram_ctrl_v4_0.axi_bram_ctrl;
ENTITY axi_bram_ctrl_16b IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END axi_bram_ctrl_16b;
ARCHITECTURE axi_bram_ctrl_16b_arch OF axi_bram_ctrl_16b IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF axi_bram_ctrl_16b_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 16384,
C_BRAM_ADDR_WIDTH => 14,
C_S_AXI_ADDR_WIDTH => 16,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 1,
C_S_AXI_PROTOCOL => "AXI4LITE",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 1,
C_FAMILY => "zynq",
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => '0',
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => '0',
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => s_axi_araddr,
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => '0',
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END axi_bram_ctrl_16b_arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity SimCore is
port(
rs232rx : in std_logic;
rst : in std_logic;
clk : in std_logic;
rs232tx : out std_logic;
led : out std_logic_vector(7 downto 0);
CLKMULOUT : out std_logic;
CLK2XOUT : out std_logic
);
end SimCore;
architecture Behavioral of SimCore is
component thermometersLogic
port(
rsTxBusy : IN std_logic;
rst : IN std_logic;
clk50Mhz : IN std_logic;
clk3kHz : IN std_logic;
rsDataOut : OUT std_logic_vector(7 downto 0);
rsTxStart : OUT std_logic;
led : OUT std_logic_vector(7 downto 0)
);
end component;
component heatersLogic
port(
rsDataIn : in std_logic_vector(7 downto 0);
rsRdy : in std_logic;
rst : in std_logic;
clk50Mhz : in std_logic;
readyOut : out std_logic
);
end component;
component RS232
port(
rs232_rxd : in std_logic;
txdi : in std_logic_vector(7 downto 0);
txstart : in std_logic;
reset : in std_logic;
clk_50Mhz : in std_logic;
clk_sys : in std_logic;
rs232_txd : out std_logic;
rxdo : out std_logic_vector(7 downto 0);
rxrdy : out std_logic;
txbusy : out std_logic
);
end component;
component FeqDiv
generic( width : integer );
port(
clkIn : IN std_logic;
clkOut : OUT std_logic
);
end component;
COMPONENT ClockGenerator
PORT(
clk100Mhz : IN std_logic;
reset : IN std_logic;
clk50Mhz : OUT std_logic
);
END COMPONENT;
COMPONENT HeaterClockGenerator
PORT(
CLKIN_IN : IN std_logic;
RST_IN : IN std_logic;
CLKFX_OUT : OUT std_logic;
CLKIN_IBUFG_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic;
CLK2X_OUT : OUT std_logic
);
END COMPONENT;
signal clk50Mhz : std_logic;
signal clk3kHz : std_logic;
signal rsDataOut : std_logic_vector(7 downto 0);
signal rsDataIn : std_logic_vector(7 downto 0);
signal rsTxStart : std_logic;
signal rsTxBusy : std_logic;
signal rsRxRdy : std_logic;
signal heatersLogicReady : std_logic;
signal clkfx : std_logic;
attribute keep : string;
attribute keep of heatersLogicReady: signal is "True";
attribute keep_hierarchy : string;
attribute keep_hierarchy of thermometersLogic: component is "TRUE";
attribute keep_hierarchy of heatersLogic: component is "TRUE";
attribute keep_hierarchy of FeqDiv: component is "TRUE";
attribute keep_hierarchy of RS232: component is "TRUE";
begin
InstFeqDiv: FeqDiv generic map( width => 14 )
port map(
clkIn => clk50MHz,
clkOut => clk3kHz
);
InstThermometersLogic: thermometersLogic
port map(
rsTxBusy => rsTxBusy,
rst => rst,
clk50Mhz => clk50Mhz,
clk3kHz => clk3kHz,
rsDataOut => rsDataOut,
rsTxStart => rsTxStart,
led => led
);
InstHeatersLogic: heatersLogic PORT MAP(
rsDataIn => rsDataIn,
rsRdy => rsRxRdy,
rst => rst,
clk50Mhz => clk50Mhz,
readyOut => heatersLogicReady
);
InstRS232: RS232 port map(
rs232_rxd => rs232rx,
txdi => rsDataOut,
txstart => rsTxStart,
reset => rst,
clk_50Mhz => clk50Mhz,
clk_sys => clk50Mhz,
rs232_txd => rs232tx,
rxdo => rsDataIn,
rxrdy => rsRxRdy,
txbusy => rsTxBusy
);
Inst_ClockGenerator: ClockGenerator PORT MAP(
clk100Mhz => clk,
reset => rst,
clk50Mhz => clk50Mhz
);
Inst_SystemClockGenerator: HeaterClockGenerator PORT MAP(
CLKIN_IN => clk,
RST_IN => rst,
CLKFX_OUT => clkfx,
CLKIN_IBUFG_OUT => open,
CLK0_OUT => open,
CLK2x_OUT => open
);
CLKMULOUT <= clkfx;
Inst_SystemClockGenerator2: HeaterClockGenerator PORT MAP(
CLKIN_IN => clkfx,
RST_IN => rst,
CLKFX_OUT => open,
CLKIN_IBUFG_OUT => open,
CLK0_OUT => open,
CLK2X_OUT => CLK2XOUT
);
end Behavioral; |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY alu_control IS
PORT (
funct : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
ALUop : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
operation : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END alu_control;
ARCHITECTURE Behavioral OF alu_control IS
BEGIN
-- notes from class
operation(3) <= '0';
operation(2) <= ALUop(0) or (ALUop(1) and funct(1));
operation(1) <= not ALUop(1) or not funct(2);
operation(0) <= (funct(3) or funct(0)) and ALUop(1);
END Behavioral; |
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Tue May 5 20:44:19 2015 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
CLK_48_in : in std_logic;
CLK_100M_in : in std_logic;
Audio_Left_in : in std_logic_vector(23 downto 0);
Audio_Right_in : in std_logic_vector(23 downto 0);
Mux2_FilterORMux1_Left_out : out std_logic_vector(23 downto 0);
Mux2_FilterORMux1_Right_out : out std_logic_vector(23 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg2 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg3 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg4 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg5 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg6 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg7 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg8 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg9 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg10 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg11 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg12 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg13 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg14 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg15 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg16 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg17 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg18 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg19 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg20 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg21 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg22 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg23 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg24 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg25 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg26 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg27 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg28 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg29 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg30 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg31 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(31 downto 0);
signal slv_reg_read_sel : std_logic_vector(31 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal slv_reg28_internal : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg29_internal : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg30_internal : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg31_internal : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
component superip_internal is
port(
-- Outputs
Mux2_FilterORMux1_Left_out : out std_logic_vector(23 downto 0);
Mux2_FilterORMux1_Right_out : out std_logic_vector(23 downto 0);
slv_reg28 : out STD_LOGIC_VECTOR(31 downto 0);
slv_reg29 : out STD_LOGIC_VECTOR(31 downto 0);
slv_reg30 : out STD_LOGIC_VECTOR(31 downto 0);
slv_reg31 : out STD_LOGIC_VECTOR(31 downto 0);
-- Inputs
CLK_48_in : in std_logic;
CLK_100M_in : in std_logic;
Audio_Left_in : in std_logic_vector(23 downto 0);
Audio_Right_in : in std_logic_vector(23 downto 0);
-- REGISTERS
slv_reg0 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg1 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg2 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg3 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg4 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg5 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg6 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg7 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg8 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg9 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg10 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg11 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg12 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg13 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg14 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg15 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg16 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg17 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg18 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg19 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg20 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg21 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg22 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg23 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg24 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg25 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg26 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg27 : in STD_LOGIC_VECTOR(31 downto 0)
);
end component;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(31 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(31 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13) or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7) or Bus2IP_RdCE(8) or Bus2IP_RdCE(9) or Bus2IP_RdCE(10) or Bus2IP_RdCE(11) or Bus2IP_RdCE(12) or Bus2IP_RdCE(13) or Bus2IP_RdCE(14) or Bus2IP_RdCE(15) or Bus2IP_RdCE(16) or Bus2IP_RdCE(17) or Bus2IP_RdCE(18) or Bus2IP_RdCE(19) or Bus2IP_RdCE(20) or Bus2IP_RdCE(21) or Bus2IP_RdCE(22) or Bus2IP_RdCE(23) or Bus2IP_RdCE(24) or Bus2IP_RdCE(25) or Bus2IP_RdCE(26) or Bus2IP_RdCE(27) or Bus2IP_RdCE(28) or Bus2IP_RdCE(29) or Bus2IP_RdCE(30) or Bus2IP_RdCE(31);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
slv_reg16 <= (others => '0');
slv_reg17 <= (others => '0');
slv_reg18 <= (others => '0');
slv_reg19 <= (others => '0');
slv_reg20 <= (others => '0');
slv_reg21 <= (others => '0');
slv_reg22 <= (others => '0');
slv_reg23 <= (others => '0');
slv_reg24 <= (others => '0');
slv_reg25 <= (others => '0');
slv_reg26 <= (others => '0');
slv_reg27 <= (others => '0');
slv_reg28 <= (others => '0');
slv_reg29 <= (others => '0');
slv_reg30 <= (others => '0');
slv_reg31 <= (others => '0');
else
case slv_reg_write_sel is
when "10000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00100000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00010000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00001000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg4(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000100000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg5(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000010000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg6(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000001000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg7(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000100000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg8(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000010000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg9(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000001000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg10(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000100000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg11(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000010000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg12(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000001000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg13(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000100000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg14(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000010000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg15(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000001000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg16(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000100000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg17(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg18(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg19(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg20(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg21(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg22(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg23(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg24(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg25(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg26(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg27(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
-- when "00000000000000000000000000001000" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg28(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when "00000000000000000000000000000100" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg29(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when "00000000000000000000000000000010" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg30(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when "00000000000000000000000000000001" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg31(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
when others => null;
end case;
slv_reg28 <= slv_reg28_internal;
slv_reg29 <= slv_reg29_internal;
slv_reg30 <= slv_reg30_internal;
slv_reg31 <= slv_reg31_internal;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, slv_reg24, slv_reg25, slv_reg26, slv_reg27, slv_reg28, slv_reg29, slv_reg30, slv_reg31 ) is
begin
case slv_reg_read_sel is
when "10000000000000000000000000000000" => slv_ip2bus_data <= slv_reg0;
when "01000000000000000000000000000000" => slv_ip2bus_data <= slv_reg1;
when "00100000000000000000000000000000" => slv_ip2bus_data <= slv_reg2;
when "00010000000000000000000000000000" => slv_ip2bus_data <= slv_reg3;
when "00001000000000000000000000000000" => slv_ip2bus_data <= slv_reg4;
when "00000100000000000000000000000000" => slv_ip2bus_data <= slv_reg5;
when "00000010000000000000000000000000" => slv_ip2bus_data <= slv_reg6;
when "00000001000000000000000000000000" => slv_ip2bus_data <= slv_reg7;
when "00000000100000000000000000000000" => slv_ip2bus_data <= slv_reg8;
when "00000000010000000000000000000000" => slv_ip2bus_data <= slv_reg9;
when "00000000001000000000000000000000" => slv_ip2bus_data <= slv_reg10;
when "00000000000100000000000000000000" => slv_ip2bus_data <= slv_reg11;
when "00000000000010000000000000000000" => slv_ip2bus_data <= slv_reg12;
when "00000000000001000000000000000000" => slv_ip2bus_data <= slv_reg13;
when "00000000000000100000000000000000" => slv_ip2bus_data <= slv_reg14;
when "00000000000000010000000000000000" => slv_ip2bus_data <= slv_reg15;
when "00000000000000001000000000000000" => slv_ip2bus_data <= slv_reg16;
when "00000000000000000100000000000000" => slv_ip2bus_data <= slv_reg17;
when "00000000000000000010000000000000" => slv_ip2bus_data <= slv_reg18;
when "00000000000000000001000000000000" => slv_ip2bus_data <= slv_reg19;
when "00000000000000000000100000000000" => slv_ip2bus_data <= slv_reg20;
when "00000000000000000000010000000000" => slv_ip2bus_data <= slv_reg21;
when "00000000000000000000001000000000" => slv_ip2bus_data <= slv_reg22;
when "00000000000000000000000100000000" => slv_ip2bus_data <= slv_reg23;
when "00000000000000000000000010000000" => slv_ip2bus_data <= slv_reg24;
when "00000000000000000000000001000000" => slv_ip2bus_data <= slv_reg25;
when "00000000000000000000000000100000" => slv_ip2bus_data <= slv_reg26;
when "00000000000000000000000000010000" => slv_ip2bus_data <= slv_reg27;
when "00000000000000000000000000001000" => slv_ip2bus_data <= slv_reg28;
when "00000000000000000000000000000100" => slv_ip2bus_data <= slv_reg29;
when "00000000000000000000000000000010" => slv_ip2bus_data <= slv_reg30;
when "00000000000000000000000000000001" => slv_ip2bus_data <= slv_reg31;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
SIP : superip_internal port map (
Mux2_FilterORMux1_Left_out => Mux2_FilterORMux1_Left_out,
Mux2_FilterORMux1_Right_out => Mux2_FilterORMux1_Right_out,
slv_reg28 => slv_reg28_internal ,
slv_reg29 => slv_reg29_internal ,
slv_reg30 => slv_reg30_internal ,
slv_reg31 => slv_reg31_internal ,
CLK_48_in => CLK_48_in ,
CLK_100M_in => CLK_100M_in ,
Audio_Left_in => Audio_Left_in ,
Audio_Right_in => Audio_Right_in ,
slv_reg0 => slv_reg0 ,
slv_reg1 => slv_reg1 ,
slv_reg2 => slv_reg2 ,
slv_reg3 => slv_reg3 ,
slv_reg4 => slv_reg4 ,
slv_reg5 => slv_reg5 ,
slv_reg6 => slv_reg6 ,
slv_reg7 => slv_reg7 ,
slv_reg8 => slv_reg8 ,
slv_reg9 => slv_reg9 ,
slv_reg10 => slv_reg10 ,
slv_reg11 => slv_reg11 ,
slv_reg12 => slv_reg12 ,
slv_reg13 => slv_reg13 ,
slv_reg14 => slv_reg14 ,
slv_reg15 => slv_reg15 ,
slv_reg16 => slv_reg16 ,
slv_reg17 => slv_reg17 ,
slv_reg18 => slv_reg18 ,
slv_reg19 => slv_reg19 ,
slv_reg20 => slv_reg20 ,
slv_reg21 => slv_reg21 ,
slv_reg22 => slv_reg22 ,
slv_reg23 => slv_reg23 ,
slv_reg24 => slv_reg24 ,
slv_reg25 => slv_reg25 ,
slv_reg26 => slv_reg26 ,
slv_reg27 => slv_reg27
);
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc255.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p07n01i00255ent IS
END c03s01b02x00p07n01i00255ent;
ARCHITECTURE c03s01b02x00p07n01i00255arch OF c03s01b02x00p07n01i00255ent IS
subtype T1 is integer range 1 to 10;
subtype T2 is integer range 1 to 100;
BEGIN
TESTING: PROCESS
variable V1 : T1;
variable V2 : T1 := 4;
variable V3 : T1 := 9;
BEGIN
V1 := V2 * V3; -- failure_here
assert FALSE
report "***FAILED TEST: c03s01b02x00p07n01i00255 - Result of mathematical operation is not of integer type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p07n01i00255arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc255.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p07n01i00255ent IS
END c03s01b02x00p07n01i00255ent;
ARCHITECTURE c03s01b02x00p07n01i00255arch OF c03s01b02x00p07n01i00255ent IS
subtype T1 is integer range 1 to 10;
subtype T2 is integer range 1 to 100;
BEGIN
TESTING: PROCESS
variable V1 : T1;
variable V2 : T1 := 4;
variable V3 : T1 := 9;
BEGIN
V1 := V2 * V3; -- failure_here
assert FALSE
report "***FAILED TEST: c03s01b02x00p07n01i00255 - Result of mathematical operation is not of integer type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p07n01i00255arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc255.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p07n01i00255ent IS
END c03s01b02x00p07n01i00255ent;
ARCHITECTURE c03s01b02x00p07n01i00255arch OF c03s01b02x00p07n01i00255ent IS
subtype T1 is integer range 1 to 10;
subtype T2 is integer range 1 to 100;
BEGIN
TESTING: PROCESS
variable V1 : T1;
variable V2 : T1 := 4;
variable V3 : T1 := 9;
BEGIN
V1 := V2 * V3; -- failure_here
assert FALSE
report "***FAILED TEST: c03s01b02x00p07n01i00255 - Result of mathematical operation is not of integer type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p07n01i00255arch;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sa : out std_logic_vector(14 downto 0);
sd : inout std_logic_vector(63 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (7 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART2 tx data
rxd2 : in std_logic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(7 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
emddis : out std_logic;
epwrdwn : out std_logic;
ereset : out std_logic;
esleep : out std_logic;
epause : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
can_txd : out std_logic;
can_rxd : in std_logic;
can_stb : out std_logic;
spw_clk : in std_logic;
spw_rxd : in std_logic_vector(0 to 2);
spw_rxdn : in std_logic_vector(0 to 2);
spw_rxs : in std_logic_vector(0 to 2);
spw_rxsn : in std_logic_vector(0 to 2);
spw_txd : out std_logic_vector(0 to 2);
spw_txdn : out std_logic_vector(0 to 2);
spw_txs : out std_logic_vector(0 to 2);
spw_txsn : out std_logic_vector(0 to 2)
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbmsp : integer := NCPU+CFG_AHB_UART+
CFG_GRETH+CFG_AHB_JTAG;
constant maxahbm : integer := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2, sdo3 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl, spw_lclk : std_logic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal can_lrx, can_ltx : std_logic;
signal lclk, pci_lclk : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal tck, tms, tdi, tdo : std_logic;
signal spwi : grspw_in_type_vector(0 to 2);
signal spwo : grspw_out_type_vector(0 to 2);
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
constant BOARD_FREQ : integer := 20000; -- Board frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV;
constant IOAEN : integer := CFG_SDCTRL + CFG_CAN;
constant CFG_SDEN : integer := CFG_SDCTRL + CFG_MCTRL_SDEN ;
constant CFG_INVCLK : integer := CFG_SDCTRL_INVCLK + CFG_MCTRL_INVCLK;
constant sysfreq : integer := (CFG_CLKMUL/CFG_CLKDIV)*20000;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= '0';
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_SDEN,
CFG_CLK_NOFB, 0, 0, 0)
port map (lclk, pci_lclk, clkm, open, open, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sdclk, sdclkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
src : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS,
romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#,
prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)
port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo3);
apbo(0) <= apb_none;
end generate;
sdc : if CFG_SDCTRL = 1 generate
sdc : sdctrl generic map (hindex => 3, haddr => 16#600#, hmask => 16#F00#,
ioaddr => 1, fast => 0, pwron => 0, invclk => CFG_SDCTRL_INVCLK,
sdbits => 32 + 32*CFG_SDCTRL_SD64)
port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo2);
sa_pad : outpadv generic map (width => 15, tech => padtech)
port map (sa, sdo2.address);
sd_pad : iopadv generic map (width => 32, tech => padtech)
port map (sd(31 downto 0), sdo2.data, sdo2.bdrive, sdi.data(31 downto 0));
sd2 : if CFG_SDCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (width => 32)
port map (sd(63 downto 32), sdo2.data, sdo2.bdrive, sdi.data(63 downto 32));
end generate;
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo2.sdcke);
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo2.sdwen);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo2.sdcsn);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo2.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo2.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo2.dqm);
end generate;
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 2, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS, sdbits => 32 + 32*CFG_MCTRL_SD64)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sd2 : if CFG_MCTRL_SEPBUS = 1 generate
sa_pad : outpadv generic map (width => 15) port map (sa, memo.sa);
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
sd2 : if CFG_MCTRL_SD64 = 1 generate
sd_pad2 : iopadv generic map (tech => padtech, width => 8)
port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));
end generate;
end generate;
end generate;
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>8, tech => padtech)
port map (sddqm, sdo.dqm);
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
end generate;
nosd0 : if (CFG_MCTRL_SDEN = 0) and (CFG_SDCTRL = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
mgpads : if (CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1) generate -- prom/sram pads
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 8, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(8));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(8) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 8)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
pio_pads : for i in 0 to 7 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
-- pp : if CFG_PCI /= 0 generate
-- pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
-- pciarb0 : pciarb generic map (pindex => 10, paddr => 10,
-- apb_en => CFG_PCI_ARBAPB)
-- port map ( clk => pciclk, rst_n => pcii.rst,
-- req_n => pci_arb_req_n, frame_n => pcii.frame,
-- gnt_n => pci_arb_gnt_n, pclk => clkm,
-- prst_n => rstn, apbi => apbi, apbo => apbo(10)
-- );
-- pgnt_pad : outpadv generic map (tech => padtech, width => 4)
-- port map (pci_arb_gnt, pci_arb_gnt_n);
-- preq_pad : inpadv generic map (tech => padtech, width => 4)
-- port map (pci_arb_req, pci_arb_req_n);
-- end generate;
--
-- pcipads0 : pcipads generic map (padtech => padtech) -- PCI pads
-- port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
-- pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
-- pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
--
-- end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 7, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
emdis_pad : outpad generic map (tech => padtech)
port map (emddis, vcc(0));
eepwrdwn_pad : outpad generic map (tech => padtech)
port map (epwrdwn, gnd(0));
esleep_pad : outpad generic map (tech => padtech)
port map (esleep, gnd(0));
epause_pad : outpad generic map (tech => padtech)
port map (epause, gnd(0));
ereset_pad : outpad generic map (tech => padtech)
port map (ereset, gnd(0));
end generate;
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_oc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FFF#, irq => CFG_CANIRQ, memtech => memtech)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
end generate;
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
can_stb <= '0'; -- no standby
can_loopback : if CFG_CANLOOP = 1 generate
can_lrx <= can_ltx;
end generate;
can_pads : if CFG_CANLOOP = 0 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd, can_ltx);
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd, can_lrx);
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
spw_clk_pad : clkpad generic map (tech => padtech) port map (spw_clk, spw_lclk);
spw_rxtxclk <= spw_lclk;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT,
rxclkbuftype => 1)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0';
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => memtech,
hindex => maxahbmsp+i, pindex => 12+i, paddr => 12+i, pirq => 10+i,
sysfreq => sysfreq, nsync => 1, rmap => CFG_SPW_RMAP,
rmapcrc => CFG_SPW_RMAPCRC, rmapbufs => CFG_SPW_RMAPBUF,
fifosize1 => CFG_SPW_AHBFIFO, fifosize2 => CFG_SPW_RXFIFO,
rxclkbuftype => 1, ports => 1, dmachan => CFG_SPW_DMACHAN,
spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT, output_type => CFG_SPW_OUTPUT,
rxtx_sameclk => CFG_SPW_RTSAME)
port map(resetn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi, ahbmo(maxahbmsp+i),
apbi, apbo(12+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(sysfreq/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxd(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x25v)
port map (spw_rxs(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txd(i), spw_txdn(i), spwo(i).d(0), gnd(0));
spw_txs_pad : outpad_ds generic map (padtech, lvds, x25v)
port map (spw_txs(i), spw_txsn(i), spwo(i).s(0), gnd(0));
end generate;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in maxahbm to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_PCI-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 12+(CFG_SPW_NUM*CFG_SPW_EN) to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-- nah0 : for i in 9 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 MP Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity main is
Port( LEDS : out STD_LOGIC_VECTOR (3 downto 0);
D_AN : out STD_LOGIC_VECTOR (3 downto 0);
D_C : out STD_LOGIC_VECTOR (7 downto 0);
BTN0 : in STD_LOGIC;
BTN1 : in STD_LOGIC;
SW0 : in STD_LOGIC;
SW1 : in STD_LOGIC;
MCLK : in STD_LOGIC;
USB_D : inout STD_LOGIC_VECTOR (7 downto 0);
USB_WAIT : out STD_LOGIC;
USB_WRITE : in STD_LOGIC;
USB_ASTB : in STD_LOGIC;
USB_DSTB : in STD_LOGIC;
-- clockport
CP_CS : in STD_LOGIC;
CP_A : in STD_LOGIC_VECTOR (3 downto 0);
CP_D : inout STD_LOGIC_VECTOR (7 downto 0);
CP_IORD : in STD_LOGIC;
CP_IOWR : in STD_LOGIC);
end main;
architecture Behavioral of main is
component clk_gen
Port( clk : in STD_LOGIC;
clkmod : out STD_LOGIC;
divval : in integer
);
end component;
component eppmodule
Port ( astb : in STD_LOGIC;
dstb : in STD_LOGIC;
wr : in STD_LOGIC;
wt : out STD_LOGIC;
databus :inout STD_LOGIC_VECTOR (7 downto 0);
ssegReg :out STD_LOGIC_VECTOR (7 downto 0);
ledReg : out STD_LOGIC_VECTOR (3 downto 0);
btnReg : in STD_LOGIC_VECTOR (7 downto 0);
commDataOutReg : out STD_LOGIC_VECTOR (7 downto 0);
commDataInReg: in STD_LOGIC_VECTOR(7 downto 0));
end component;
component sseg
Port ( clock : in STD_LOGIC;
segA : in STD_LOGIC_VECTOR (7 downto 0);
segB : in STD_LOGIC_VECTOR (7 downto 0);
segC : in STD_LOGIC_VECTOR (7 downto 0);
segD : in STD_LOGIC_VECTOR (7 downto 0);
segout :out STD_LOGIC_VECTOR (7 downto 0);
segan : out STD_LOGIC_VECTOR (3 downto 0));
end component;
component hextoseg
Port ( hex : in STD_LOGIC_VECTOR (3 downto 0);
seg : out STD_LOGIC_VECTOR (7 downto 0));
end component;
component clockport
Port( -- clockport signals
data : inout STD_LOGIC_VECTOR (7 downto 0);
addressIn : in STD_LOGIC_VECTOR (3 downto 0);
iord : in STD_LOGIC;
iowr : in STD_LOGIC;
cs : in STD_LOGIC;
--addressOut : out STD_LOGIC_VECTOR (3 downto 0);
btnReg : in STD_LOGIC_VECTOR (7 downto 0);
ledReg : out STD_LOGIC_VECTOR (3 downto 0);
testOut : out STD_LOGIC_VECTOR (7 downto 0);
commDataOutReg : out STD_LOGIC_VECTOR (7 downto 0);
commDataInReg: in STD_LOGIC_VECTOR(7 downto 0));
end component;
signal sA, sB, sC, sD : STD_LOGIC_VECTOR (7 downto 0);
signal sHex : STD_LOGIC_VECTOR (7 downto 0);
signal sHexLo : STD_LOGIC_VECTOR (3 downto 0);
signal sHexHi : STD_LOGIC_VECTOR (3 downto 0);
signal sHex2 : STD_LOGIC_VECTOR (7 downto 0);
signal sHex2Lo : STD_LOGIC_VECTOR (3 downto 0);
signal sHex2Hi : STD_LOGIC_VECTOR (3 downto 0);
signal slowclk : STD_LOGIC;
signal pushableReg : STD_LOGIC_VECTOR(7 downto 0);
signal ledReg : STD_LOGIC_VECTOR(3 downto 0);
signal commDataAtoU : STD_LOGIC_VECTOR (7 downto 0);
signal commDataUtoA : STD_LOGIC_VECTOR (7 downto 0);
-- only for debugging
--signal cpAddress : STD_LOGIC_VECTOR (3 downto 0);
begin
-- CLK_DIV16_inst1 : CLK_DIV16
-- port map (
-- CLKDV => fullclk1,
-- CLKIN => CLK
-- );
clk_gen_inst1 : clk_gen
port map (
clk => MCLK,
clkmod => slowclk,
divval => 500 -- 8MHz / 500 = circa 16kHz
);
deppusb : eppmodule
port map (
astb => USB_ASTB,
dstb => USB_DSTB,
wr => USB_WRITE,
wt => USB_WAIT,
dataBus => USB_D,
ssegReg => sHex,
-- ledReg => ledReg,
btnReg => pushableReg,
commDataInReg => commDataAtoU,
commDataOutReg => commDataUtoA
);
sseg1 : sseg
port map (
clock => slowclk,
segA => sA,
segB => sB,
segC => sC,
segD => sD,
segout => D_C,
segan => D_AN
);
hextoseglo : hextoseg
port map (
hex => sHexLo,
seg => sA
);
hextoseghi : hextoseg
port map (
hex => sHexHi,
seg => sB
);
hextoseglo2 : hextoseg
port map (
hex => sHex2Lo,
seg => sC
);
hextoseghi2 : hextoseg
port map (
hex => sHex2Hi,
seg => sD
);
amigacp : clockport
port map (
data => CP_D,
addressIn => CP_A,
iord => CP_IORD,
iowr => CP_IOWR,
cs => CP_CS,
btnReg => pushableReg,
ledReg => ledReg,
testOut => sHex2,
commDataInReg => commDataUtoA,
commDataOutReg => commDataAtoU
);
LEDS <= NOT ledReg;
--LEDS <= NOT cpAddress;
sHexLo <= sHex(0) & sHex(1) & sHex(2) & sHex(3);
sHexHi <= sHex(4) & sHex(5) & sHex(6) & sHex(7);
sHex2Lo <= sHex2(0) & sHex2(1) & sHex2(2) & sHex2(3);
sHex2Hi <= sHex2(4) & sHex2(5) & sHex2(6) & sHex2(7);
pushableReg(0) <= NOT BTN0;
pushableReg(1) <= NOT BTN1;
pushableReg(2) <= NOT SW0;
pushableReg(3) <= NOT SW1;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3095.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p08n01i03095ent IS
END c05s01b00x00p08n01i03095ent;
ARCHITECTURE c05s01b00x00p08n01i03095arch OF c05s01b00x00p08n01i03095ent IS
attribute A1 : INTEGER;
signal S1 : BOOLEAN;
attribute A2 of S1 : signal is 9; -- Failure_here
-- ERROR : no preceding user-defined attribute declaration for A2
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s01b00x00p08n01i03095 - User defined attribute has to be predefined."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p08n01i03095arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3095.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p08n01i03095ent IS
END c05s01b00x00p08n01i03095ent;
ARCHITECTURE c05s01b00x00p08n01i03095arch OF c05s01b00x00p08n01i03095ent IS
attribute A1 : INTEGER;
signal S1 : BOOLEAN;
attribute A2 of S1 : signal is 9; -- Failure_here
-- ERROR : no preceding user-defined attribute declaration for A2
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s01b00x00p08n01i03095 - User defined attribute has to be predefined."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p08n01i03095arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3095.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p08n01i03095ent IS
END c05s01b00x00p08n01i03095ent;
ARCHITECTURE c05s01b00x00p08n01i03095arch OF c05s01b00x00p08n01i03095ent IS
attribute A1 : INTEGER;
signal S1 : BOOLEAN;
attribute A2 of S1 : signal is 9; -- Failure_here
-- ERROR : no preceding user-defined attribute declaration for A2
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c05s01b00x00p08n01i03095 - User defined attribute has to be predefined."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p08n01i03095arch;
|
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: WTR_CTRL
-- AUTHORS: Ondřej Dujíček <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_unsigned.ALL;
entity WTR_CTRL is
Port (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
ADR : out STD_LOGIC_VECTOR(7 downto 0) :=(others=>'0');
CELL_IN : in STD_LOGIC_VECTOR(31 downto 0);
CELL_OUT : out STD_LOGIC_VECTOR(31 downto 0) :=(others=>'0');
WE_OUT : out STD_LOGIC := '0';
RE_OUT : out STD_LOGIC := '0';
WIN_BIT : out STD_LOGIC := '0';
KNLG_next : in STD_LOGIC;
START : in STD_LOGIC;
FAIL_OUT : out STD_LOGIC
);
end WTR_CTRL;
architecture Behavioral of WTR_CTRL is
-- casovac
signal rst_clk : STD_LOGIC;
signal start2 : STD_LOGIC;
-- I/O data
signal s_cell_in : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
signal s_cell_in_next : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
signal s_cell_out : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
signal s_cell_out_next : STD_LOGIC_VECTOR(31 downto 0) := (others=>'0');
-- data o trubkach
signal typ_tr : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0'); -- typ trubky
signal rot_tr : STD_LOGIC_VECTOR(1 downto 0) := (others=>'0'); -- natoèení trubky
signal r,l,up,down : STD_LOGIC := '0';
signal bit_check : STD_LOGIC_VECTOR(1 downto 0) := "00";
signal bit_check_next : STD_LOGIC_VECTOR(1 downto 0) := "00";
signal cesta_vody : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0');
signal cesta_vody_next : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0');
-- adresy
signal adr_x_next : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0');
signal adr_y_next : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0');
signal adr_x : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0');
signal adr_y : STD_LOGIC_VECTOR(3 downto 0) := (others=>'0');
signal s_adr : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0');
signal now_addr : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); -- adresa aktualni bunky, pouziva se ke cteni a zapisu
signal now_addr_next : STD_LOGIC_VECTOR(7 downto 0) := (others=>'0'); -- adresa aktualni bunky, pouziva se ke cteni a zapisu
signal adr_xn_1_next : STD_LOGIC_VECTOR(3 downto 0); --pøedchozí adresy
signal adr_yn_1_next : STD_LOGIC_VECTOR(3 downto 0); --pøedchozí adresy
signal adr_xn_1 : STD_LOGIC_VECTOR(3 downto 0); --pøedchozí adresy
signal adr_yn_1 : STD_LOGIC_VECTOR(3 downto 0); --pøedchozí adresy
signal adr_xn_2_next : STD_LOGIC_VECTOR(3 downto 0); --pøedchozí adresy
signal adr_yn_2_next : STD_LOGIC_VECTOR(3 downto 0); --pøedchozí adresy
signal adr_xn_2 : STD_LOGIC_VECTOR(3 downto 0); --pøedchozí adresy
signal adr_yn_2 : STD_LOGIC_VECTOR(3 downto 0); --pøedchozí adresy
-- win, lose signaly
signal fail_bit_next : STD_LOGIC := '0';
signal WIN_BIT_next : STD_LOGIC := '0';
-- ostatni signaly
signal tmp1 : STD_LOGIC_VECTOR(4 downto 0) := (others=>'0'); --- counter na trubky
signal tmp1_next : STD_LOGIC_VECTOR(4 downto 0) := (others=>'0'); --- counter na trubky
signal knlg : STD_LOGIC;
type state_type0 is (m1,m2,m3,m4,m5,m6,m0,m7,m8,m9,m10,m11,m12,m13,m16,m17,m18,m19); -- mody prace s bunkou
signal next_state, present_state : state_type0 := m0; -- vnitrni signaly typu state
-- konstanty
constant clock_defi : STD_LOGIC_VECTOR(25 downto 0) := "00001101111111011110000100"; -- cim vetsi tim pomalejsi
begin
-- zapojeni podkomponenty
-- casovani 10 - 14 to je 5 bit 00001 voda ma tect 00011 voda tece a je v prvnim policku casovac na 0.2s az 0.5s
wtr_clk_unit : entity work.WTR_CLK
generic map (
Flip_flops => 26 -- odpovída nastavenemu clock defi
)
port map (
CLK => CLK,
RST => rst_clk,
CLOCK_DEFI => clock_defi, -- nastavuje hodnotu casovace
ENABLE_OUT => start2
);
-- rozdeleni ulozenych dat
up <= s_cell_in(6);
r <= s_cell_in(7);
down <= s_cell_in(8);
l <= s_cell_in(9);
typ_tr <= s_cell_in(3 downto 0);
rot_tr <= s_cell_in(5 downto 4);
s_adr <= std_logic_vector(unsigned(adr_y) & unsigned(adr_x));
ADR <= now_addr;
CELL_OUT <= s_cell_out_next;
WIN_BIT <= win_bit_next;
FAIL_OUT <= fail_bit_next;
-----------------------------------------------------------------------------------------------------
-- STAVOVY AUTOMAT - THE DUJDA SYSTEM
-----------------------------------------------------------------------------------------------------
process (CLK)
begin
if (rising_edge(CLK)) then
if (RST = '1') then -- synchronni reset
present_state <= m0;
now_addr <= (others=>'0');
s_cell_out <= (others=>'0');
s_cell_in <= (others=>'0');
tmp1 <= (others=>'0');
bit_check <= (others=>'0');
adr_xn_1 <= (others=>'0');
adr_yn_1 <= (others=>'0');
adr_xn_2 <= (others=>'0');
adr_yn_2 <= (others=>'0');
adr_x <= (others=>'0');
adr_y <= (others=>'0');
knlg <= '0';
cesta_vody <= (others=>'0');
else
present_state <= next_state;
now_addr <= now_addr_next;
s_cell_out <= s_cell_out_next;
s_cell_in <= s_cell_in_next;
tmp1 <= tmp1_next;
bit_check <= bit_check_next;
adr_xn_1 <= adr_xn_1_next;
adr_yn_1 <= adr_yn_1_next;
adr_xn_2 <= adr_xn_2_next;
adr_yn_2 <= adr_yn_2_next;
adr_x <= adr_x_next;
adr_y <= adr_y_next;
knlg <= knlg_next;
cesta_vody <= cesta_vody_next;
end if;
end if;
end process;
process(present_state,up,l,r,down,start,adr_x,adr_y,typ_tr,rot_tr, adr_xn_1, adr_yn_1, bit_check,
KNLG_next, knlg, s_adr, start2, tmp1, s_cell_in, s_cell_out, now_addr, CELL_IN, cesta_vody, adr_xn_2, adr_yn_2)
begin
bit_check_next <= bit_check;
adr_xn_1_next <= adr_xn_1;
adr_yn_1_next <= adr_yn_1;
adr_xn_2_next <= adr_xn_2;
adr_yn_2_next <= adr_yn_2;
adr_x_next <= adr_x;
adr_y_next <= adr_y;
now_addr_next <= now_addr;
s_cell_out_next <= s_cell_out;
s_cell_in_next <= s_cell_in;
tmp1_next <= tmp1;
rst_clk <= '0';
cesta_vody_next <= cesta_vody;
case present_state is
-- startovni stav
when m0=>
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
adr_x_next <= (others=>'0');
adr_y_next <= (others=>'0');
now_addr_next <= (others=>'0'); -- nastaveni adresy startovniho policka
if (start = '1') then
next_state<= m1;
else
next_state<= m0;
end if;
------------------------------------------------------------
-- cteni dat o aktualni bunce
when m1 =>
fail_bit_next <= '0';
win_bit_next <= '0';
WE_OUT <= '0';
if (knlg = '1') then
RE_OUT <= '0';
s_cell_in_next <= CELL_IN;
next_state <= m17;
else
RE_OUT <= '1';
next_state <= m1;
end if;
------------------------------------------------------------
-- kontrola zdali jsme na startovnim policku
when m17 =>
RE_OUT <= '0';
WE_OUT <= '0';
fail_bit_next <= '0';
win_bit_next <= '0';
s_cell_out_next <= s_cell_in;
if (s_adr = "00000000") then
next_state <= m8;
else
next_state <= m16;
end if;
------------------------------------------------------------
-- kontrola jestli je spravne zapojena prvni trubka
when m8 =>
RE_OUT <= '0';
WE_OUT <= '0';
fail_bit_next <= '0';
win_bit_next <= '0';
if (l='1') then -- kontrola pripojení první trubky
next_state<= m2;
else
next_state<= m3;
end if;
------------------------------------------------------------
-- kontrola pripojeni druhe trubky
when m16=>
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
case bit_check is
when "00" =>
if (l='1') then
next_state <= m2;
else
next_state <= m3;
end if;
when "01" =>
if (r='1') then
next_state <= m2;
else
next_state <= m3;
end if;
when "10" =>
if (down='1') then
next_state <= m2;
else
next_state <= m3;
end if;
when "11" =>
if (up='1') then
next_state <= m2;
else
next_state <= m3;
end if;
when others =>
next_state <= m3;
end case;
------------------------------------------------------------
-- zjisteni typu trubky
when m2=>
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
case typ_tr is
when "0000" =>
next_state <= m3; -- prazdne pole
when "0010" =>
next_state <= m4; -- trubka L-ko
when "0001" =>
next_state <= m5; -- rovna trubka
when "0011" =>
next_state <= m6; -- krizova trubka
when others =>
next_state <= m3; -- zed nebo jine
end case;
------------------------------------------------------------
-- trubka L, zjistovani natoceni
when m4 =>
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
case rot_tr is
when "10" => -- L = z hora do prava
if (adr_yn_1<adr_y) then
next_state<= m10; -- doprava
cesta_vody_next <= "1011"; -- zhora doprava
else
next_state<= m12; -- nahoru
cesta_vody_next <= "0111"; -- zprava nahoru
end if;
when "11" => -- P z prava dolu
if (adr_yn_1>adr_y) then
next_state<= m10; -- doprava
cesta_vody_next <= "1001"; -- zdola doprava
else
next_state<= m13; -- dolu
cesta_vody_next <= "1000"; -- zprava dolu
end if;
when "00" => -- 7 z dola do leva + osetreny prvni stav
if (adr_yn_1>adr_y) then
next_state<= m11; -- doleva
cesta_vody_next <= "1010"; -- zdola doleva
else
next_state<= m13; -- dolu
cesta_vody_next <= "0110"; -- zleva dolu
end if;
when "01" => -- d z leva nahoru
if (adr_yn_1<adr_y) then
next_state<= m11; -- doleva
cesta_vody_next <= "1100"; -- zhora doleva
else
next_state<= m12; -- nahoru
cesta_vody_next <= "0101"; -- zleva nahoru
end if;
when others => -- kdyby se neco posralo
next_state <= m3;
end case;
------------------------------------------------------------
-- rovna trubka, zjistovani natoceni
when m5 =>
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
case rot_tr is
when "00" =>
if (adr_xn_1>adr_x) then
next_state<= m11; -- doleva
cesta_vody_next <= "0010";
else
next_state<= m10; -- doprava
cesta_vody_next <= "0001";
end if;
when "01" =>
if (adr_yn_1<adr_y) then
next_state<= m13; -- dolu
cesta_vody_next <= "0100";
else
next_state<= m12; -- nahoru
cesta_vody_next <= "0011";
end if;
when others =>
next_state <= m3;
end case;
------------------------------------------------------------
-- krizova trubka, zjistovani natoceni
when m6 =>
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
if (adr_xn_1<adr_x) then
next_state<= m10; -- tece doprava
cesta_vody_next <= "0001";
elsif (adr_xn_1>adr_x) then
next_state<= m11; -- tece doleva
cesta_vody_next <= "0010";
elsif (adr_yn_1<adr_y) then
next_state<= m13; -- tece dolu
cesta_vody_next <= "0100";
elsif (adr_yn_1>adr_y) then
next_state<= m12; -- tece nahoru
cesta_vody_next <= "0011";
elsif (s_adr="00000000") then
next_state<=m10; -- tece doprava
cesta_vody_next <= "0001";
else
next_state<=m3;
end if;
------------------------------------------------------------
-- voda potece doprava
when m10 => --- ptam se do prava
adr_x_next<= std_logic_vector(unsigned(adr_x) + 1);
bit_check_next<="00";
adr_xn_1_next <= adr_x;
adr_yn_1_next <= adr_y;
adr_xn_2_next <= adr_xn_1;
adr_yn_2_next <= adr_yn_1;
next_state<= m18;
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
rst_clk<='1';
------------------------------------------------------------
-- voda potece doleva
when m11 => --- ptam se do leva
adr_x_next<= std_logic_vector(unsigned(adr_x) - 1);
bit_check_next<="01";
adr_xn_1_next <= adr_x;
adr_yn_1_next <= adr_y;
adr_xn_2_next <= adr_xn_1;
adr_yn_2_next <= adr_yn_1;
next_state<= m18;
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
rst_clk<='1';
------------------------------------------------------------
-- voda potece nahoru
when m12 => --- ptam se nahoru
adr_y_next<= std_logic_vector(unsigned(adr_y) - 1);
bit_check_next<="10";
adr_xn_1_next <= adr_x;
adr_yn_1_next <= adr_y;
adr_xn_2_next <= adr_xn_1;
adr_yn_2_next <= adr_yn_1;
next_state<= m18;
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
rst_clk<='1';
------------------------------------------------------------
-- voda potece dolu
when m13 => --- ptam se dolu
adr_y_next<= std_logic_vector(unsigned(adr_y) + 1);
bit_check_next<="11";
adr_xn_1_next <= adr_x;
adr_yn_1_next <= adr_y;
adr_xn_2_next <= adr_xn_1;
adr_yn_2_next <= adr_yn_1;
next_state<= m18;
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
rst_clk<='1';
------------------------------------------------------------
-- kontrola jestli voda prosla celou trubkou
when m18=>
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
if (start2='1') then
if (tmp1="11111") then
--tmp1_next <= "00000";
next_state <= m7;
--now_addr_next <= s_adr; -- nastaveni adresy noveho policka
else
tmp1_next<=std_logic_vector(unsigned(tmp1)+1);
next_state<=m19;
end if;
else
next_state <= m18;
end if;
------------------------------------------------------------
-- zapis vody, zapne casovani a pricte vodu
when m19=>
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '1';
WE_OUT <= '1';
if ((cesta_vody = "0011") OR (cesta_vody = "0100")) then
s_cell_out_next(15 downto 10) <= s_cell_in(15 downto 10);
s_cell_out_next(21 downto 16) <= tmp1 & '1';
s_cell_out_next(25 downto 22) <= s_cell_in(25 downto 22);
s_cell_out_next(29 downto 26) <= cesta_vody;
else
s_cell_out_next(15 downto 10) <= tmp1 & '1';
s_cell_out_next(21 downto 16) <= s_cell_in(21 downto 16);
s_cell_out_next(25 downto 22) <= cesta_vody;
s_cell_out_next(29 downto 26) <= s_cell_in(29 downto 26);
end if;
if (KNLG_next = '1') then
next_state <= m18;
else
next_state <= m19;
end if;
------------------------------------------------------------
-- kontrola jestli trubka neni zapojena do cile nebo do zdi
when m7 =>
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
tmp1_next <= "00000";
now_addr_next <= s_adr; -- nastaveni adresy noveho policka
if ((adr_yn_1="0000")and (up='1') and (typ_tr/="0011")) then
next_state<=m3;
elsif((adr_yn_1="1100")and (down='1')and (typ_tr/="0011")) then
next_state<=m3;
elsif((adr_xn_1="1101")and (r='1') and (adr_yn_1/="1100")and (typ_tr/="0011")) then
next_state<=m3;
elsif((adr_xn_1="1101")and (r='1') and (adr_yn_1="1100") and (typ_tr/="0011")) then -- win
next_state<=m9;
elsif((adr_xn_1="0000")and (l='1')and(adr_yn_1/="0000") and (typ_tr/="0011")) then
next_state<=m3;
-- krizova --- fix
elsif (typ_tr="0011") then
if (adr_xn_2<adr_xn_1) then
if ((adr_xn_1="1101") and (adr_yn_1/="1100")) then
next_state <= m3;
elsif ((adr_xn_1="1101") and (adr_yn_1="1100")) then
next_state <= m9;
else
next_state<=m1;
end if;
elsif ((adr_xn_2>adr_xn_1) and (adr_xn_1="0000")) then
next_state<= m3;
elsif ((adr_yn_2<adr_yn_1) and (adr_yn_1="1100")) then
next_state<= m3;
elsif ((adr_yn_2>adr_yn_1) and (adr_yn_1="0000")) then
next_state<= m3;
else
next_state<=m1;
end if;
else
next_state<=m1;
end if;
------------------------------------------------------------
-- Prohra
when m3 =>
fail_bit_next <= '1';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
next_state<=m3;
------------------------------------------------------------
-- Vyhra
when m9 =>
fail_bit_next <= '0';
win_bit_next <= '1';
RE_OUT <= '0';
WE_OUT <= '0';
next_state <= m9;
------------------------------------------------------------
-- ostatni stavy
when others =>
fail_bit_next <= '0';
win_bit_next <= '0';
RE_OUT <= '0';
WE_OUT <= '0';
next_state <= m0;
end case;
end process;
end Behavioral;
|
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
---------------------------------------------------
---------------------------------------------------
-- $0 : 0
-- $1 : 1
-- $2 : 2
-- $3 : 3
-- $4 : 4
-- $5 : 5
-- $29: contains fixed bottom of stack for $31 values
--
-- add $2, $0, $0
-- add $3, $1, $1 ---
-- jal subroutine ---
-- add $3, $2, $3 ---store final ans. in $3
-- nop
-- nop
-- nop
-- jump exit
-- subroutine:
-- add $2, $1, $2
-- add $3, $1, $3
-- jr $31
-- nop
-- nop
-- nop
-- nop
-- exit:
-- lots of nop
--- EXPECTED RESULT
--- PHYSICAL REG FILE CONTENTS CHANGE AS FOLLOWS :
-- 32 => 0(d)
-- 33 => 2(d)
-- 34 => 12(d)
-- 35 => 1(d)
-- 36 => 3(d)
-- 37 => 4(d)
---------------------------------------------------
---------------------------------------------------
signal mem : mem_type :=
( X"00621820_0C000008_00211820_00001020", -- Loc 0C, 08, 04, 00 sw_addi_add_add
X"08000010_00000020_00000020_00000020", -- Loc 1C, 18, 14, 10 jump_nop_add_jal
X"00000020_03E00008_00611820_00221020", -- Loc 2C, 28, 24, 20 addi_lw_add_add
X"00000020_00000020_00000020_00000020", -- Loc 3C, 38, 34, 30 nop_nop_nop_jr
X"00000020_00000020_00000020_00000020", -- Loc 4C, 48, 44, 40 nop_nop_nop_nop
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping ump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for s package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
|
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
---------------------------------------------------
---------------------------------------------------
-- $0 : 0
-- $1 : 1
-- $2 : 2
-- $3 : 3
-- $4 : 4
-- $5 : 5
-- $29: contains fixed bottom of stack for $31 values
--
-- add $2, $0, $0
-- add $3, $1, $1 ---
-- jal subroutine ---
-- add $3, $2, $3 ---store final ans. in $3
-- nop
-- nop
-- nop
-- jump exit
-- subroutine:
-- add $2, $1, $2
-- add $3, $1, $3
-- jr $31
-- nop
-- nop
-- nop
-- nop
-- exit:
-- lots of nop
--- EXPECTED RESULT
--- PHYSICAL REG FILE CONTENTS CHANGE AS FOLLOWS :
-- 32 => 0(d)
-- 33 => 2(d)
-- 34 => 12(d)
-- 35 => 1(d)
-- 36 => 3(d)
-- 37 => 4(d)
---------------------------------------------------
---------------------------------------------------
signal mem : mem_type :=
( X"00621820_0C000008_00211820_00001020", -- Loc 0C, 08, 04, 00 sw_addi_add_add
X"08000010_00000020_00000020_00000020", -- Loc 1C, 18, 14, 10 jump_nop_add_jal
X"00000020_03E00008_00611820_00221020", -- Loc 2C, 28, 24, 20 addi_lw_add_add
X"00000020_00000020_00000020_00000020", -- Loc 3C, 38, 34, 30 nop_nop_nop_jr
X"00000020_00000020_00000020_00000020", -- Loc 4C, 48, 44, 40 nop_nop_nop_nop
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping ump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for s package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
|
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
---------------------------------------------------
---------------------------------------------------
-- $0 : 0
-- $1 : 1
-- $2 : 2
-- $3 : 3
-- $4 : 4
-- $5 : 5
-- $29: contains fixed bottom of stack for $31 values
--
-- add $2, $0, $0
-- add $3, $1, $1 ---
-- jal subroutine ---
-- add $3, $2, $3 ---store final ans. in $3
-- nop
-- nop
-- nop
-- jump exit
-- subroutine:
-- add $2, $1, $2
-- add $3, $1, $3
-- jr $31
-- nop
-- nop
-- nop
-- nop
-- exit:
-- lots of nop
--- EXPECTED RESULT
--- PHYSICAL REG FILE CONTENTS CHANGE AS FOLLOWS :
-- 32 => 0(d)
-- 33 => 2(d)
-- 34 => 12(d)
-- 35 => 1(d)
-- 36 => 3(d)
-- 37 => 4(d)
---------------------------------------------------
---------------------------------------------------
signal mem : mem_type :=
( X"00621820_0C000008_00211820_00001020", -- Loc 0C, 08, 04, 00 sw_addi_add_add
X"08000010_00000020_00000020_00000020", -- Loc 1C, 18, 14, 10 jump_nop_add_jal
X"00000020_03E00008_00611820_00221020", -- Loc 2C, 28, 24, 20 addi_lw_add_add
X"00000020_00000020_00000020_00000020", -- Loc 3C, 38, 34, 30 nop_nop_nop_jr
X"00000020_00000020_00000020_00000020", -- Loc 4C, 48, 44, 40 nop_nop_nop_nop
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping ump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
-- the last 16 instructions are looping jump instructions
-- of the type: loop: j loop
-- This is to make sure that neither instruction fetching
-- nor instruction execution proceeds beyond the end of this memory.
-- Loc 3C0 -- 080000F0 => J 240
-- Loc 3C4 -- 080000F1 => J 241
-- Loc 3C8 -- 080000F2 => J 242
-- Loc 3CC -- 080000F3 => J 243
--
-- Loc 3D0 -- 080000F4 => J 244
-- Loc 3D4 -- 080000F5 => J 245
-- Loc 3D8 -- 080000F6 => J 246
-- Loc 3DC -- 080000F7 => J 247
--
-- Loc 3E0 -- 080000F8 => J 248
-- Loc 3E4 -- 080000F9 => J 249
-- Loc 3E8 -- 080000FA => J 250
-- Loc 3EC -- 080000FB => J 251
--
-- Loc 3F0 -- 080000FC => J 252
-- Loc 3F4 -- 080000FD => J 253
-- Loc 3F8 -- 080000FE => J 254
-- Loc 3FC -- 080000FF => J 255
end package instr_stream_pkg;
-- -- No need for s package body here
-- package body instr_stream_pkg is
--
-- end package body instr_stream_pkg;
|
---------------------------------------------------------------------------
-- Company : Vim Inc
-- Author(s) : Fabien Marteau
--
-- Creation Date : 23/04/2008
-- File : atmega_pkg.vhd
--
-- Abstract : Simulate atmega128 read and write
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
package atmega_emi_pkg is
procedure atmega_write(
Address : in std_logic_vector( 15 downto 0);
value : in std_logic_vector( 7 downto 0);
signal clk : in std_logic ;
signal Address_H : out std_logic_vector( 6 downto 0);
signal DA : inout std_logic_vector( 7 downto 0);
signal ALE : out std_logic ;
signal RD : out std_logic ;
signal WR : out std_logic ;
signal DIR_buffer : in std_logic ;
wait_states : natural
);
procedure atmega_read(
Address : in std_logic_vector( 15 downto 0);
signal value : out std_logic_vector( 7 downto 0);
signal clk : in std_logic ;
signal Address_H : out std_logic_vector( 6 downto 0);
signal DA : inout std_logic_vector( 7 downto 0);
signal ALE : out std_logic ;
signal RD : out std_logic ;
signal WR : out std_logic ;
signal DIR_buffer : in std_logic ;
wait_states : natural
);
end package atmega_emi_pkg;
package body atmega_emi_pkg is
CONSTANT TCLCL : time :=62 ns; -- 16 MHz
--Write value
procedure atmega_write(
Address : in std_logic_vector( 15 downto 0);
value : in std_logic_vector( 7 downto 0);
signal clk : in std_logic ;
signal Address_H : out std_logic_vector( 6 downto 0);
signal DA : inout std_logic_vector( 7 downto 0);
signal ALE : out std_logic ;
signal RD : out std_logic ;
signal WR : out std_logic ;
signal DIR_buffer : in std_logic ;
wait_states : natural
) is
begin
WR <= '1';
RD <= '1';
wait until falling_edge(clk);
ALE <= '1';
wait until rising_edge(clk);
Address_H <= Address(14 downto 8);
DA <= Address(7 downto 0);
wait until falling_edge(clk);
ALE <= '0';
wait for 5 ns;
DA <= (others => 'Z');
wait until rising_edge(clk);
DA <= value;
-- 0.5TCLCL - 20 ns
wait for 0.5*TCLCL - 20 ns;
WR <= '0';
wait until falling_edge(clk);
wait until rising_edge(clk);
if wait_states >= 0 then
for n in 1 to wait_states loop
wait until rising_edge(clk);
end loop;
end if;
WR <= '1';
wait until falling_edge(clk);
DA <= (others => 'Z');
Address_H <= (others => 'Z');
end procedure atmega_write;
--Read value
procedure atmega_read(
Address : in std_logic_vector( 15 downto 0);
signal value : out std_logic_vector( 7 downto 0);
signal clk : in std_logic ;
signal Address_H : out std_logic_vector( 6 downto 0);
signal DA : inout std_logic_vector( 7 downto 0);
signal ALE : out std_logic ;
signal RD : out std_logic ;
signal WR : out std_logic ;
signal DIR_buffer : in std_logic ;
wait_states : natural
) is
begin
RD <= '1';
WR <= '1';
wait until falling_edge(clk);
ALE <= '1';
wait until rising_edge(clk);
Address_H <= Address(14 downto 8);
DA <= Address(7 downto 0);
wait until falling_edge(clk);
ALE <= '0';
wait for 5 ns;
DA <= (others => 'Z');
wait until rising_edge(clk);
wait for 0.5*TCLCL - 20 ns;
RD <= '0';
wait until rising_edge(clk); -- 0 wait states
if wait_states >= 0 then
for n in 1 to wait_states loop
wait until rising_edge(clk);
end loop;
end if;
assert DIR_buffer = '1' report "buffer direction error" severity error;
value <= DA;
RD <= '1';
wait until falling_edge(clk);
DA <= (others => 'Z');
Address_H <= (others => 'Z');
end procedure atmega_read;
end package body atmega_emi_pkg;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Jun 05 17:25:05 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_sync_reset_0_0/system_vga_sync_reset_0_0_stub.vhdl
-- Design : system_vga_sync_reset_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_vga_sync_reset_0_0 is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end system_vga_sync_reset_0_0;
architecture stub of system_vga_sync_reset_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rst,active,hsync,vsync,xaddr[9:0],yaddr[9:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "vga_sync_reset,Vivado 2016.4";
begin
end;
|
---------------------------------------------------------------------------------------------
-- Author: Martin Kumm
-- Contact: [email protected]
-- License: LGPL
-- Date: 04.04.2013
--
-- Description:
-- Testbench for testing a single ternary adder component
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all; -- for uniform, trunc functions
entity tb_ternary_adder is
generic(
input_word_size : integer := 15;
subtract_y : boolean := false;
subtract_z : boolean := true;
use_output_ff : boolean := false
);
end tb_ternary_adder;
architecture tb_ternary_adder_arch of tb_ternary_adder is
signal clk, rst : std_logic := '0';
signal x,y,z : std_logic_vector(input_word_size-1 downto 0) := (others => '0');
signal sum : std_logic_vector(input_word_size+1 downto 0) := (others => '0');
signal sum_ref,sum_dut: integer := 0;
begin
dut: entity work.ternary_adder
generic map (
input_word_size => input_word_size,
subtract_y => subtract_y,
subtract_z => subtract_z,
use_output_ff => use_output_ff
)
port map (
clk_i => clk,
rst_i => rst,
x_i => x,
y_i => y,
z_i => z,
sum_o => sum
);
clk <= not clk after 5 ns; -- 100 MHz
rst <= '1', '0' after 5 ns;
process
variable seed1,seed2: positive;
variable rand : real;
variable x_int,y_int,z_int : integer;
begin
uniform(seed1, seed2, rand);
x_int := integer(trunc(rand*real(2**(input_word_size-2)-1)));
uniform(seed1, seed2, rand);
y_int := integer(trunc(rand*real(2**(input_word_size-2)-1)));
uniform(seed1, seed2, rand);
z_int := integer(trunc(rand*real(2**(input_word_size-2)-1)));
x <= std_logic_vector(to_signed(x_int, x'length)); -- rescale, quantize and convert
y <= std_logic_vector(to_signed(y_int, y'length)); -- rescale, quantize and convert
z <= std_logic_vector(to_signed(z_int, z'length)); -- rescale, quantize and convert
wait until clk'event and clk='1';
end process;
process(clk,rst,x,y,z)
variable y_sgn,z_sgn,sum_ref_unsync : integer;
begin
if subtract_y = true then
y_sgn := -1*to_integer(signed(y));
else
y_sgn := to_integer(signed(y));
end if;
if subtract_z = true then
z_sgn := -1*to_integer(signed(z));
else
z_sgn := to_integer(signed(z));
end if;
sum_ref_unsync := to_integer(signed(x)) + y_sgn + z_sgn;
if use_output_ff = false then
sum_ref <= sum_ref_unsync;
else
if clk'event and clk='1' then
sum_ref <= sum_ref_unsync;
end if;
end if;
end process;
process(clk,rst,sum_ref)
begin
end process;
sum_dut <= to_integer(signed(sum));
process
begin
wait for 50 ns;
loop
wait until clk'event and clk='0';
assert (sum_dut = sum_ref) report "Test failure" severity failure;
wait until clk'event and clk='1';
end loop;
end process;
end architecture; |
library verilog;
use verilog.vl_types.all;
entity SSD1306_VHDLImplementation is
port(
CD : out vl_logic;
CLKI : in vl_logic;
RSTI : in vl_logic;
CLKO : out vl_logic;
DO : out vl_logic;
CS : out vl_logic;
RSTO : out vl_logic
);
end SSD1306_VHDLImplementation;
|
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|
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n8Pv2BjGHEEcdjSzkxifqw==
`protect end_protected
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: pulse_regen_v6_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity pulse_regen_v6_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end pulse_regen_v6_top;
architecture xilinx of pulse_regen_v6_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component pulse_regen_v6 is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
VALID : OUT std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(1-1 DOWNTO 0);
DOUT : OUT std_logic_vector(1-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : pulse_regen_v6 PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
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