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--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_credit_counter_logic_pseudo_checkers is
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out : in std_logic_vector(1 downto 0);
valid_N, valid_E, valid_W, valid_S, valid_L: in std_logic; -- ?? Not sure yet ! grant or valid !
credit_counter_N_in, credit_counter_E_in, credit_counter_W_in, credit_counter_S_in, credit_counter_L_in : in std_logic_vector(1 downto 0);
-- Checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change,
err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change,
err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change,
err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change,
err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change,
err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : out std_logic
);
end allocator_credit_counter_logic_pseudo_checkers;
architecture behavior of allocator_credit_counter_logic_pseudo_checkers is
begin
-- The combionational part
----------------------------------------------------------------
-- Checkers for the process handling the credit counters
-- North credit counter
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '1' and valid_N = '1' and credit_counter_N_in /= credit_counter_N_out) then
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '1';
else
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '0';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '1' and valid_N = '1' and credit_counter_N_out < 3 and credit_counter_N_in /= credit_counter_N_out + 1) then
err_credit_in_N_credit_counter_N_out_increment <= '1';
else
err_credit_in_N_credit_counter_N_out_increment <= '0';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '1' and valid_N = '0' and credit_counter_N_out = 3 and credit_counter_N_in /= credit_counter_N_out) then
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change <= '1';
else
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change <= '0';
end if;
end process;
process (valid_N, credit_in_N, credit_counter_N_in, credit_counter_N_out)
begin
if (valid_N = '1' and credit_in_N = '0' and credit_counter_N_out > 0 and credit_counter_N_in /= credit_counter_N_out - 1) then
err_grant_N_credit_counter_N_out_decrement <= '1';
else
err_grant_N_credit_counter_N_out_decrement <= '0';
end if;
end process;
process (valid_N, credit_in_N, credit_counter_N_in, credit_counter_N_out)
begin
if (valid_N = '1' and credit_in_N = '0' and credit_counter_N_out = 0 and credit_counter_N_in /= credit_counter_N_out) then
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change <= '1';
else
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change <= '0';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '0' and valid_N = '0' and credit_counter_N_in /= credit_counter_N_out) then
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '1';
else
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '0';
end if;
end process;
-- East credit counter
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '1' and valid_E = '1' and credit_counter_E_in /= credit_counter_E_out) then
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '1';
else
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '0';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '1' and valid_E = '0' and credit_counter_E_out < 3 and credit_counter_E_in /= credit_counter_E_out + 1) then
err_credit_in_E_credit_counter_E_out_increment <= '1';
else
err_credit_in_E_credit_counter_E_out_increment <= '0';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '1' and valid_E = '0' and credit_counter_E_out = 3 and credit_counter_E_in /= credit_counter_E_out) then
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change <= '1';
else
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change <= '0';
end if;
end process;
process (valid_E, credit_in_E, credit_counter_E_in, credit_counter_E_out)
begin
if (valid_E = '1' and credit_in_E = '0' and credit_counter_E_out > 0 and credit_counter_E_in /= credit_counter_E_out - 1) then
err_grant_E_credit_counter_E_out_decrement <= '1';
else
err_grant_E_credit_counter_E_out_decrement <= '0';
end if;
end process;
process (valid_E, credit_in_E, credit_counter_E_in, credit_counter_E_out)
begin
if (valid_E = '1' and credit_in_E = '0' and credit_counter_E_out = 0 and credit_counter_E_in /= credit_counter_E_out) then
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change <= '1';
else
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change <= '0';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '0' and valid_E = '0' and credit_counter_E_in /= credit_counter_E_out) then
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '1';
else
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '0';
end if;
end process;
-- West credit counter
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if (credit_in_W = '1' and valid_W = '1' and credit_counter_W_in /= credit_counter_W_out) then
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '1';
else
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '0';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if (credit_in_W = '1' and valid_W = '0' and credit_counter_W_out < 3 and credit_counter_W_in /= credit_counter_W_out + 1) then
err_credit_in_W_credit_counter_W_out_increment <= '1';
else
err_credit_in_W_credit_counter_W_out_increment <= '0';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if ( (credit_in_W = '1' and valid_W = '0' and credit_counter_W_out = 3) and credit_counter_W_in /= credit_counter_W_out) then
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change <= '1';
else
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change <= '0';
end if;
end process;
process (valid_W, credit_in_W, credit_counter_W_in, credit_counter_W_out)
begin
if (valid_W = '1' and credit_in_W = '0' and credit_counter_W_out > 0 and credit_counter_W_in /= credit_counter_W_out - 1) then
err_grant_W_credit_counter_W_out_decrement <= '1';
else
err_grant_W_credit_counter_W_out_decrement <= '0';
end if;
end process;
process (valid_W, credit_in_W, credit_counter_W_in, credit_counter_W_out)
begin
if ( valid_W = '1' and credit_in_W = '0' and credit_counter_W_out = 0 and credit_counter_W_in /= credit_counter_W_out) then
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change <= '1';
else
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change <= '0';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if (credit_in_W = '0' and valid_W = '0' and credit_counter_W_in /= credit_counter_W_out) then
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '1';
else
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '0';
end if;
end process;
-- South credit counter
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if (credit_in_S = '1' and valid_S = '1' and credit_counter_S_in /= credit_counter_S_out) then
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '1';
else
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '0';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if (credit_in_S = '1' and valid_S = '0' and credit_counter_S_out < 3 and credit_counter_S_in /= credit_counter_S_out + 1) then
err_credit_in_S_credit_counter_S_out_increment <= '1';
else
err_credit_in_S_credit_counter_S_out_increment <= '0';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if ( credit_in_S = '1' and valid_S = '0' and credit_counter_S_out = 3 and credit_counter_S_in /= credit_counter_S_out) then
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change <= '1';
else
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change <= '0';
end if;
end process;
process (valid_S, credit_in_S, credit_counter_S_in, credit_counter_S_out)
begin
if (valid_S = '1' and credit_in_S = '0' and credit_counter_S_out > 0 and credit_counter_S_in /= credit_counter_S_out - 1) then
err_grant_S_credit_counter_S_out_decrement <= '1';
else
err_grant_S_credit_counter_S_out_decrement <= '0';
end if;
end process;
process (valid_S, credit_in_S, credit_counter_S_in, credit_counter_S_out)
begin
if (valid_S = '1' and credit_in_S = '0' and credit_counter_S_out = 0 and credit_counter_S_in /= credit_counter_S_out) then
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change <= '1';
else
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change <= '0';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if (credit_in_S = '0' and valid_S = '0' and credit_counter_S_in /= credit_counter_S_out) then
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '1';
else
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '0';
end if;
end process;
-- Local credit counter
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '1' and valid_L = '1' and credit_counter_L_in /= credit_counter_L_out) then
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '1';
else
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '0';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '1' and valid_L = '0' and credit_counter_L_out < 3 and credit_counter_L_in /= credit_counter_L_out + 1) then
err_credit_in_L_credit_counter_L_out_increment <= '1';
else
err_credit_in_L_credit_counter_L_out_increment <= '0';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '1' and valid_L = '0' and credit_counter_L_out = 3 and credit_counter_L_in /= credit_counter_L_out) then
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change <= '1';
else
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change <= '0';
end if;
end process;
process (valid_L, credit_in_L, credit_counter_L_in, credit_counter_L_out)
begin
if (valid_L = '1' and credit_in_L = '0' and credit_counter_L_out > 0 and credit_counter_L_in /= credit_counter_L_out - 1) then
err_grant_L_credit_counter_L_out_decrement <= '1';
else
err_grant_L_credit_counter_L_out_decrement <= '0';
end if;
end process;
process (valid_L, credit_in_L, credit_counter_L_in, credit_counter_L_out)
begin
if (valid_L = '1' and credit_in_L = '0' and credit_counter_L_out = 0 and credit_counter_L_in /= credit_counter_L_out) then
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change <= '1';
else
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change <= '0';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '0' and valid_L = '0' and credit_counter_L_in /= credit_counter_L_out) then
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '1';
else
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '0';
end if;
end process;
END;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_credit_counter_logic_pseudo_checkers is
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out : in std_logic_vector(1 downto 0);
valid_N, valid_E, valid_W, valid_S, valid_L: in std_logic; -- ?? Not sure yet ! grant or valid !
credit_counter_N_in, credit_counter_E_in, credit_counter_W_in, credit_counter_S_in, credit_counter_L_in : in std_logic_vector(1 downto 0);
-- Checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change,
err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change,
err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change,
err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change,
err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change,
err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : out std_logic
);
end allocator_credit_counter_logic_pseudo_checkers;
architecture behavior of allocator_credit_counter_logic_pseudo_checkers is
begin
-- The combionational part
----------------------------------------------------------------
-- Checkers for the process handling the credit counters
-- North credit counter
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '1' and valid_N = '1' and credit_counter_N_in /= credit_counter_N_out) then
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '1';
else
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '0';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '1' and valid_N = '1' and credit_counter_N_out < 3 and credit_counter_N_in /= credit_counter_N_out + 1) then
err_credit_in_N_credit_counter_N_out_increment <= '1';
else
err_credit_in_N_credit_counter_N_out_increment <= '0';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '1' and valid_N = '0' and credit_counter_N_out = 3 and credit_counter_N_in /= credit_counter_N_out) then
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change <= '1';
else
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change <= '0';
end if;
end process;
process (valid_N, credit_in_N, credit_counter_N_in, credit_counter_N_out)
begin
if (valid_N = '1' and credit_in_N = '0' and credit_counter_N_out > 0 and credit_counter_N_in /= credit_counter_N_out - 1) then
err_grant_N_credit_counter_N_out_decrement <= '1';
else
err_grant_N_credit_counter_N_out_decrement <= '0';
end if;
end process;
process (valid_N, credit_in_N, credit_counter_N_in, credit_counter_N_out)
begin
if (valid_N = '1' and credit_in_N = '0' and credit_counter_N_out = 0 and credit_counter_N_in /= credit_counter_N_out) then
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change <= '1';
else
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change <= '0';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '0' and valid_N = '0' and credit_counter_N_in /= credit_counter_N_out) then
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '1';
else
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '0';
end if;
end process;
-- East credit counter
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '1' and valid_E = '1' and credit_counter_E_in /= credit_counter_E_out) then
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '1';
else
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '0';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '1' and valid_E = '0' and credit_counter_E_out < 3 and credit_counter_E_in /= credit_counter_E_out + 1) then
err_credit_in_E_credit_counter_E_out_increment <= '1';
else
err_credit_in_E_credit_counter_E_out_increment <= '0';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '1' and valid_E = '0' and credit_counter_E_out = 3 and credit_counter_E_in /= credit_counter_E_out) then
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change <= '1';
else
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change <= '0';
end if;
end process;
process (valid_E, credit_in_E, credit_counter_E_in, credit_counter_E_out)
begin
if (valid_E = '1' and credit_in_E = '0' and credit_counter_E_out > 0 and credit_counter_E_in /= credit_counter_E_out - 1) then
err_grant_E_credit_counter_E_out_decrement <= '1';
else
err_grant_E_credit_counter_E_out_decrement <= '0';
end if;
end process;
process (valid_E, credit_in_E, credit_counter_E_in, credit_counter_E_out)
begin
if (valid_E = '1' and credit_in_E = '0' and credit_counter_E_out = 0 and credit_counter_E_in /= credit_counter_E_out) then
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change <= '1';
else
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change <= '0';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '0' and valid_E = '0' and credit_counter_E_in /= credit_counter_E_out) then
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '1';
else
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '0';
end if;
end process;
-- West credit counter
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if (credit_in_W = '1' and valid_W = '1' and credit_counter_W_in /= credit_counter_W_out) then
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '1';
else
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '0';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if (credit_in_W = '1' and valid_W = '0' and credit_counter_W_out < 3 and credit_counter_W_in /= credit_counter_W_out + 1) then
err_credit_in_W_credit_counter_W_out_increment <= '1';
else
err_credit_in_W_credit_counter_W_out_increment <= '0';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if ( (credit_in_W = '1' and valid_W = '0' and credit_counter_W_out = 3) and credit_counter_W_in /= credit_counter_W_out) then
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change <= '1';
else
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change <= '0';
end if;
end process;
process (valid_W, credit_in_W, credit_counter_W_in, credit_counter_W_out)
begin
if (valid_W = '1' and credit_in_W = '0' and credit_counter_W_out > 0 and credit_counter_W_in /= credit_counter_W_out - 1) then
err_grant_W_credit_counter_W_out_decrement <= '1';
else
err_grant_W_credit_counter_W_out_decrement <= '0';
end if;
end process;
process (valid_W, credit_in_W, credit_counter_W_in, credit_counter_W_out)
begin
if ( valid_W = '1' and credit_in_W = '0' and credit_counter_W_out = 0 and credit_counter_W_in /= credit_counter_W_out) then
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change <= '1';
else
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change <= '0';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if (credit_in_W = '0' and valid_W = '0' and credit_counter_W_in /= credit_counter_W_out) then
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '1';
else
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '0';
end if;
end process;
-- South credit counter
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if (credit_in_S = '1' and valid_S = '1' and credit_counter_S_in /= credit_counter_S_out) then
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '1';
else
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '0';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if (credit_in_S = '1' and valid_S = '0' and credit_counter_S_out < 3 and credit_counter_S_in /= credit_counter_S_out + 1) then
err_credit_in_S_credit_counter_S_out_increment <= '1';
else
err_credit_in_S_credit_counter_S_out_increment <= '0';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if ( credit_in_S = '1' and valid_S = '0' and credit_counter_S_out = 3 and credit_counter_S_in /= credit_counter_S_out) then
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change <= '1';
else
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change <= '0';
end if;
end process;
process (valid_S, credit_in_S, credit_counter_S_in, credit_counter_S_out)
begin
if (valid_S = '1' and credit_in_S = '0' and credit_counter_S_out > 0 and credit_counter_S_in /= credit_counter_S_out - 1) then
err_grant_S_credit_counter_S_out_decrement <= '1';
else
err_grant_S_credit_counter_S_out_decrement <= '0';
end if;
end process;
process (valid_S, credit_in_S, credit_counter_S_in, credit_counter_S_out)
begin
if (valid_S = '1' and credit_in_S = '0' and credit_counter_S_out = 0 and credit_counter_S_in /= credit_counter_S_out) then
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change <= '1';
else
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change <= '0';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if (credit_in_S = '0' and valid_S = '0' and credit_counter_S_in /= credit_counter_S_out) then
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '1';
else
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '0';
end if;
end process;
-- Local credit counter
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '1' and valid_L = '1' and credit_counter_L_in /= credit_counter_L_out) then
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '1';
else
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '0';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '1' and valid_L = '0' and credit_counter_L_out < 3 and credit_counter_L_in /= credit_counter_L_out + 1) then
err_credit_in_L_credit_counter_L_out_increment <= '1';
else
err_credit_in_L_credit_counter_L_out_increment <= '0';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '1' and valid_L = '0' and credit_counter_L_out = 3 and credit_counter_L_in /= credit_counter_L_out) then
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change <= '1';
else
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change <= '0';
end if;
end process;
process (valid_L, credit_in_L, credit_counter_L_in, credit_counter_L_out)
begin
if (valid_L = '1' and credit_in_L = '0' and credit_counter_L_out > 0 and credit_counter_L_in /= credit_counter_L_out - 1) then
err_grant_L_credit_counter_L_out_decrement <= '1';
else
err_grant_L_credit_counter_L_out_decrement <= '0';
end if;
end process;
process (valid_L, credit_in_L, credit_counter_L_in, credit_counter_L_out)
begin
if (valid_L = '1' and credit_in_L = '0' and credit_counter_L_out = 0 and credit_counter_L_in /= credit_counter_L_out) then
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change <= '1';
else
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change <= '0';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '0' and valid_L = '0' and credit_counter_L_in /= credit_counter_L_out) then
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '1';
else
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '0';
end if;
end process;
END;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_credit_counter_logic_pseudo_checkers is
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out : in std_logic_vector(1 downto 0);
valid_N, valid_E, valid_W, valid_S, valid_L: in std_logic; -- ?? Not sure yet ! grant or valid !
credit_counter_N_in, credit_counter_E_in, credit_counter_W_in, credit_counter_S_in, credit_counter_L_in : in std_logic_vector(1 downto 0);
-- Checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change,
err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change,
err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change,
err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change,
err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change,
err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : out std_logic
);
end allocator_credit_counter_logic_pseudo_checkers;
architecture behavior of allocator_credit_counter_logic_pseudo_checkers is
begin
-- The combionational part
----------------------------------------------------------------
-- Checkers for the process handling the credit counters
-- North credit counter
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '1' and valid_N = '1' and credit_counter_N_in /= credit_counter_N_out) then
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '1';
else
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '0';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '1' and valid_N = '1' and credit_counter_N_out < 3 and credit_counter_N_in /= credit_counter_N_out + 1) then
err_credit_in_N_credit_counter_N_out_increment <= '1';
else
err_credit_in_N_credit_counter_N_out_increment <= '0';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '1' and valid_N = '0' and credit_counter_N_out = 3 and credit_counter_N_in /= credit_counter_N_out) then
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change <= '1';
else
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change <= '0';
end if;
end process;
process (valid_N, credit_in_N, credit_counter_N_in, credit_counter_N_out)
begin
if (valid_N = '1' and credit_in_N = '0' and credit_counter_N_out > 0 and credit_counter_N_in /= credit_counter_N_out - 1) then
err_grant_N_credit_counter_N_out_decrement <= '1';
else
err_grant_N_credit_counter_N_out_decrement <= '0';
end if;
end process;
process (valid_N, credit_in_N, credit_counter_N_in, credit_counter_N_out)
begin
if (valid_N = '1' and credit_in_N = '0' and credit_counter_N_out = 0 and credit_counter_N_in /= credit_counter_N_out) then
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change <= '1';
else
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change <= '0';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '0' and valid_N = '0' and credit_counter_N_in /= credit_counter_N_out) then
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '1';
else
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '0';
end if;
end process;
-- East credit counter
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '1' and valid_E = '1' and credit_counter_E_in /= credit_counter_E_out) then
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '1';
else
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '0';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '1' and valid_E = '0' and credit_counter_E_out < 3 and credit_counter_E_in /= credit_counter_E_out + 1) then
err_credit_in_E_credit_counter_E_out_increment <= '1';
else
err_credit_in_E_credit_counter_E_out_increment <= '0';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '1' and valid_E = '0' and credit_counter_E_out = 3 and credit_counter_E_in /= credit_counter_E_out) then
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change <= '1';
else
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change <= '0';
end if;
end process;
process (valid_E, credit_in_E, credit_counter_E_in, credit_counter_E_out)
begin
if (valid_E = '1' and credit_in_E = '0' and credit_counter_E_out > 0 and credit_counter_E_in /= credit_counter_E_out - 1) then
err_grant_E_credit_counter_E_out_decrement <= '1';
else
err_grant_E_credit_counter_E_out_decrement <= '0';
end if;
end process;
process (valid_E, credit_in_E, credit_counter_E_in, credit_counter_E_out)
begin
if (valid_E = '1' and credit_in_E = '0' and credit_counter_E_out = 0 and credit_counter_E_in /= credit_counter_E_out) then
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change <= '1';
else
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change <= '0';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '0' and valid_E = '0' and credit_counter_E_in /= credit_counter_E_out) then
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '1';
else
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '0';
end if;
end process;
-- West credit counter
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if (credit_in_W = '1' and valid_W = '1' and credit_counter_W_in /= credit_counter_W_out) then
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '1';
else
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '0';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if (credit_in_W = '1' and valid_W = '0' and credit_counter_W_out < 3 and credit_counter_W_in /= credit_counter_W_out + 1) then
err_credit_in_W_credit_counter_W_out_increment <= '1';
else
err_credit_in_W_credit_counter_W_out_increment <= '0';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if ( (credit_in_W = '1' and valid_W = '0' and credit_counter_W_out = 3) and credit_counter_W_in /= credit_counter_W_out) then
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change <= '1';
else
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change <= '0';
end if;
end process;
process (valid_W, credit_in_W, credit_counter_W_in, credit_counter_W_out)
begin
if (valid_W = '1' and credit_in_W = '0' and credit_counter_W_out > 0 and credit_counter_W_in /= credit_counter_W_out - 1) then
err_grant_W_credit_counter_W_out_decrement <= '1';
else
err_grant_W_credit_counter_W_out_decrement <= '0';
end if;
end process;
process (valid_W, credit_in_W, credit_counter_W_in, credit_counter_W_out)
begin
if ( valid_W = '1' and credit_in_W = '0' and credit_counter_W_out = 0 and credit_counter_W_in /= credit_counter_W_out) then
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change <= '1';
else
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change <= '0';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if (credit_in_W = '0' and valid_W = '0' and credit_counter_W_in /= credit_counter_W_out) then
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '1';
else
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '0';
end if;
end process;
-- South credit counter
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if (credit_in_S = '1' and valid_S = '1' and credit_counter_S_in /= credit_counter_S_out) then
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '1';
else
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '0';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if (credit_in_S = '1' and valid_S = '0' and credit_counter_S_out < 3 and credit_counter_S_in /= credit_counter_S_out + 1) then
err_credit_in_S_credit_counter_S_out_increment <= '1';
else
err_credit_in_S_credit_counter_S_out_increment <= '0';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if ( credit_in_S = '1' and valid_S = '0' and credit_counter_S_out = 3 and credit_counter_S_in /= credit_counter_S_out) then
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change <= '1';
else
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change <= '0';
end if;
end process;
process (valid_S, credit_in_S, credit_counter_S_in, credit_counter_S_out)
begin
if (valid_S = '1' and credit_in_S = '0' and credit_counter_S_out > 0 and credit_counter_S_in /= credit_counter_S_out - 1) then
err_grant_S_credit_counter_S_out_decrement <= '1';
else
err_grant_S_credit_counter_S_out_decrement <= '0';
end if;
end process;
process (valid_S, credit_in_S, credit_counter_S_in, credit_counter_S_out)
begin
if (valid_S = '1' and credit_in_S = '0' and credit_counter_S_out = 0 and credit_counter_S_in /= credit_counter_S_out) then
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change <= '1';
else
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change <= '0';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if (credit_in_S = '0' and valid_S = '0' and credit_counter_S_in /= credit_counter_S_out) then
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '1';
else
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '0';
end if;
end process;
-- Local credit counter
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '1' and valid_L = '1' and credit_counter_L_in /= credit_counter_L_out) then
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '1';
else
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '0';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '1' and valid_L = '0' and credit_counter_L_out < 3 and credit_counter_L_in /= credit_counter_L_out + 1) then
err_credit_in_L_credit_counter_L_out_increment <= '1';
else
err_credit_in_L_credit_counter_L_out_increment <= '0';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '1' and valid_L = '0' and credit_counter_L_out = 3 and credit_counter_L_in /= credit_counter_L_out) then
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change <= '1';
else
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change <= '0';
end if;
end process;
process (valid_L, credit_in_L, credit_counter_L_in, credit_counter_L_out)
begin
if (valid_L = '1' and credit_in_L = '0' and credit_counter_L_out > 0 and credit_counter_L_in /= credit_counter_L_out - 1) then
err_grant_L_credit_counter_L_out_decrement <= '1';
else
err_grant_L_credit_counter_L_out_decrement <= '0';
end if;
end process;
process (valid_L, credit_in_L, credit_counter_L_in, credit_counter_L_out)
begin
if (valid_L = '1' and credit_in_L = '0' and credit_counter_L_out = 0 and credit_counter_L_in /= credit_counter_L_out) then
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change <= '1';
else
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change <= '0';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '0' and valid_L = '0' and credit_counter_L_in /= credit_counter_L_out) then
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '1';
else
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '0';
end if;
end process;
END;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_credit_counter_logic_pseudo_checkers is
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out : in std_logic_vector(1 downto 0);
valid_N, valid_E, valid_W, valid_S, valid_L: in std_logic; -- ?? Not sure yet ! grant or valid !
credit_counter_N_in, credit_counter_E_in, credit_counter_W_in, credit_counter_S_in, credit_counter_L_in : in std_logic_vector(1 downto 0);
-- Checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change,
err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change,
err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change,
err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change,
err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change,
err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : out std_logic
);
end allocator_credit_counter_logic_pseudo_checkers;
architecture behavior of allocator_credit_counter_logic_pseudo_checkers is
begin
-- The combionational part
----------------------------------------------------------------
-- Checkers for the process handling the credit counters
-- North credit counter
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '1' and valid_N = '1' and credit_counter_N_in /= credit_counter_N_out) then
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '1';
else
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '0';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '1' and valid_N = '1' and credit_counter_N_out < 3 and credit_counter_N_in /= credit_counter_N_out + 1) then
err_credit_in_N_credit_counter_N_out_increment <= '1';
else
err_credit_in_N_credit_counter_N_out_increment <= '0';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '1' and valid_N = '0' and credit_counter_N_out = 3 and credit_counter_N_in /= credit_counter_N_out) then
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change <= '1';
else
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change <= '0';
end if;
end process;
process (valid_N, credit_in_N, credit_counter_N_in, credit_counter_N_out)
begin
if (valid_N = '1' and credit_in_N = '0' and credit_counter_N_out > 0 and credit_counter_N_in /= credit_counter_N_out - 1) then
err_grant_N_credit_counter_N_out_decrement <= '1';
else
err_grant_N_credit_counter_N_out_decrement <= '0';
end if;
end process;
process (valid_N, credit_in_N, credit_counter_N_in, credit_counter_N_out)
begin
if (valid_N = '1' and credit_in_N = '0' and credit_counter_N_out = 0 and credit_counter_N_in /= credit_counter_N_out) then
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change <= '1';
else
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change <= '0';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '0' and valid_N = '0' and credit_counter_N_in /= credit_counter_N_out) then
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '1';
else
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '0';
end if;
end process;
-- East credit counter
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '1' and valid_E = '1' and credit_counter_E_in /= credit_counter_E_out) then
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '1';
else
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '0';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '1' and valid_E = '0' and credit_counter_E_out < 3 and credit_counter_E_in /= credit_counter_E_out + 1) then
err_credit_in_E_credit_counter_E_out_increment <= '1';
else
err_credit_in_E_credit_counter_E_out_increment <= '0';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '1' and valid_E = '0' and credit_counter_E_out = 3 and credit_counter_E_in /= credit_counter_E_out) then
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change <= '1';
else
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change <= '0';
end if;
end process;
process (valid_E, credit_in_E, credit_counter_E_in, credit_counter_E_out)
begin
if (valid_E = '1' and credit_in_E = '0' and credit_counter_E_out > 0 and credit_counter_E_in /= credit_counter_E_out - 1) then
err_grant_E_credit_counter_E_out_decrement <= '1';
else
err_grant_E_credit_counter_E_out_decrement <= '0';
end if;
end process;
process (valid_E, credit_in_E, credit_counter_E_in, credit_counter_E_out)
begin
if (valid_E = '1' and credit_in_E = '0' and credit_counter_E_out = 0 and credit_counter_E_in /= credit_counter_E_out) then
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change <= '1';
else
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change <= '0';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '0' and valid_E = '0' and credit_counter_E_in /= credit_counter_E_out) then
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '1';
else
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '0';
end if;
end process;
-- West credit counter
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if (credit_in_W = '1' and valid_W = '1' and credit_counter_W_in /= credit_counter_W_out) then
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '1';
else
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '0';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if (credit_in_W = '1' and valid_W = '0' and credit_counter_W_out < 3 and credit_counter_W_in /= credit_counter_W_out + 1) then
err_credit_in_W_credit_counter_W_out_increment <= '1';
else
err_credit_in_W_credit_counter_W_out_increment <= '0';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if ( (credit_in_W = '1' and valid_W = '0' and credit_counter_W_out = 3) and credit_counter_W_in /= credit_counter_W_out) then
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change <= '1';
else
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change <= '0';
end if;
end process;
process (valid_W, credit_in_W, credit_counter_W_in, credit_counter_W_out)
begin
if (valid_W = '1' and credit_in_W = '0' and credit_counter_W_out > 0 and credit_counter_W_in /= credit_counter_W_out - 1) then
err_grant_W_credit_counter_W_out_decrement <= '1';
else
err_grant_W_credit_counter_W_out_decrement <= '0';
end if;
end process;
process (valid_W, credit_in_W, credit_counter_W_in, credit_counter_W_out)
begin
if ( valid_W = '1' and credit_in_W = '0' and credit_counter_W_out = 0 and credit_counter_W_in /= credit_counter_W_out) then
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change <= '1';
else
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change <= '0';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if (credit_in_W = '0' and valid_W = '0' and credit_counter_W_in /= credit_counter_W_out) then
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '1';
else
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '0';
end if;
end process;
-- South credit counter
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if (credit_in_S = '1' and valid_S = '1' and credit_counter_S_in /= credit_counter_S_out) then
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '1';
else
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '0';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if (credit_in_S = '1' and valid_S = '0' and credit_counter_S_out < 3 and credit_counter_S_in /= credit_counter_S_out + 1) then
err_credit_in_S_credit_counter_S_out_increment <= '1';
else
err_credit_in_S_credit_counter_S_out_increment <= '0';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if ( credit_in_S = '1' and valid_S = '0' and credit_counter_S_out = 3 and credit_counter_S_in /= credit_counter_S_out) then
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change <= '1';
else
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change <= '0';
end if;
end process;
process (valid_S, credit_in_S, credit_counter_S_in, credit_counter_S_out)
begin
if (valid_S = '1' and credit_in_S = '0' and credit_counter_S_out > 0 and credit_counter_S_in /= credit_counter_S_out - 1) then
err_grant_S_credit_counter_S_out_decrement <= '1';
else
err_grant_S_credit_counter_S_out_decrement <= '0';
end if;
end process;
process (valid_S, credit_in_S, credit_counter_S_in, credit_counter_S_out)
begin
if (valid_S = '1' and credit_in_S = '0' and credit_counter_S_out = 0 and credit_counter_S_in /= credit_counter_S_out) then
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change <= '1';
else
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change <= '0';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if (credit_in_S = '0' and valid_S = '0' and credit_counter_S_in /= credit_counter_S_out) then
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '1';
else
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '0';
end if;
end process;
-- Local credit counter
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '1' and valid_L = '1' and credit_counter_L_in /= credit_counter_L_out) then
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '1';
else
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '0';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '1' and valid_L = '0' and credit_counter_L_out < 3 and credit_counter_L_in /= credit_counter_L_out + 1) then
err_credit_in_L_credit_counter_L_out_increment <= '1';
else
err_credit_in_L_credit_counter_L_out_increment <= '0';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '1' and valid_L = '0' and credit_counter_L_out = 3 and credit_counter_L_in /= credit_counter_L_out) then
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change <= '1';
else
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change <= '0';
end if;
end process;
process (valid_L, credit_in_L, credit_counter_L_in, credit_counter_L_out)
begin
if (valid_L = '1' and credit_in_L = '0' and credit_counter_L_out > 0 and credit_counter_L_in /= credit_counter_L_out - 1) then
err_grant_L_credit_counter_L_out_decrement <= '1';
else
err_grant_L_credit_counter_L_out_decrement <= '0';
end if;
end process;
process (valid_L, credit_in_L, credit_counter_L_in, credit_counter_L_out)
begin
if (valid_L = '1' and credit_in_L = '0' and credit_counter_L_out = 0 and credit_counter_L_in /= credit_counter_L_out) then
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change <= '1';
else
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change <= '0';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '0' and valid_L = '0' and credit_counter_L_in /= credit_counter_L_out) then
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '1';
else
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '0';
end if;
end process;
END;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allocator_credit_counter_logic_pseudo_checkers is
port (
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
credit_counter_N_out, credit_counter_E_out, credit_counter_W_out, credit_counter_S_out, credit_counter_L_out : in std_logic_vector(1 downto 0);
valid_N, valid_E, valid_W, valid_S, valid_L: in std_logic; -- ?? Not sure yet ! grant or valid !
credit_counter_N_in, credit_counter_E_in, credit_counter_W_in, credit_counter_S_in, credit_counter_L_in : in std_logic_vector(1 downto 0);
-- Checker outputs
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_N_credit_counter_N_out_increment,
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change,
err_grant_N_credit_counter_N_out_decrement,
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change,
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal,
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_E_credit_counter_E_out_increment,
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change,
err_grant_E_credit_counter_E_out_decrement,
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change,
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal,
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_W_credit_counter_W_out_increment,
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change,
err_grant_W_credit_counter_W_out_decrement,
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change,
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal,
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_S_credit_counter_S_out_increment,
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change,
err_grant_S_credit_counter_S_out_decrement,
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change,
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal,
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal,
err_credit_in_L_credit_counter_L_out_increment,
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change,
err_grant_L_credit_counter_L_out_decrement,
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change,
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal : out std_logic
);
end allocator_credit_counter_logic_pseudo_checkers;
architecture behavior of allocator_credit_counter_logic_pseudo_checkers is
begin
-- The combionational part
----------------------------------------------------------------
-- Checkers for the process handling the credit counters
-- North credit counter
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '1' and valid_N = '1' and credit_counter_N_in /= credit_counter_N_out) then
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '1';
else
err_credit_in_N_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '0';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '1' and valid_N = '1' and credit_counter_N_out < 3 and credit_counter_N_in /= credit_counter_N_out + 1) then
err_credit_in_N_credit_counter_N_out_increment <= '1';
else
err_credit_in_N_credit_counter_N_out_increment <= '0';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '1' and valid_N = '0' and credit_counter_N_out = 3 and credit_counter_N_in /= credit_counter_N_out) then
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change <= '1';
else
err_not_credit_in_N_credit_counter_N_out_max_credit_counter_N_in_not_change <= '0';
end if;
end process;
process (valid_N, credit_in_N, credit_counter_N_in, credit_counter_N_out)
begin
if (valid_N = '1' and credit_in_N = '0' and credit_counter_N_out > 0 and credit_counter_N_in /= credit_counter_N_out - 1) then
err_grant_N_credit_counter_N_out_decrement <= '1';
else
err_grant_N_credit_counter_N_out_decrement <= '0';
end if;
end process;
process (valid_N, credit_in_N, credit_counter_N_in, credit_counter_N_out)
begin
if (valid_N = '1' and credit_in_N = '0' and credit_counter_N_out = 0 and credit_counter_N_in /= credit_counter_N_out) then
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change <= '1';
else
err_not_grant_N_or_credit_counter_N_out_zero_credit_counter_N_in_not_change <= '0';
end if;
end process;
process (credit_in_N, valid_N, credit_counter_N_in, credit_counter_N_out)
begin
if (credit_in_N = '0' and valid_N = '0' and credit_counter_N_in /= credit_counter_N_out) then
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '1';
else
err_not_credit_in_N_not_grant_N_credit_counter_N_in_credit_counter_N_out_equal <= '0';
end if;
end process;
-- East credit counter
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '1' and valid_E = '1' and credit_counter_E_in /= credit_counter_E_out) then
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '1';
else
err_credit_in_E_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '0';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '1' and valid_E = '0' and credit_counter_E_out < 3 and credit_counter_E_in /= credit_counter_E_out + 1) then
err_credit_in_E_credit_counter_E_out_increment <= '1';
else
err_credit_in_E_credit_counter_E_out_increment <= '0';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '1' and valid_E = '0' and credit_counter_E_out = 3 and credit_counter_E_in /= credit_counter_E_out) then
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change <= '1';
else
err_not_credit_in_E_credit_counter_E_out_max_credit_counter_E_in_not_change <= '0';
end if;
end process;
process (valid_E, credit_in_E, credit_counter_E_in, credit_counter_E_out)
begin
if (valid_E = '1' and credit_in_E = '0' and credit_counter_E_out > 0 and credit_counter_E_in /= credit_counter_E_out - 1) then
err_grant_E_credit_counter_E_out_decrement <= '1';
else
err_grant_E_credit_counter_E_out_decrement <= '0';
end if;
end process;
process (valid_E, credit_in_E, credit_counter_E_in, credit_counter_E_out)
begin
if (valid_E = '1' and credit_in_E = '0' and credit_counter_E_out = 0 and credit_counter_E_in /= credit_counter_E_out) then
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change <= '1';
else
err_not_grant_E_or_credit_counter_E_out_zero_credit_counter_E_in_not_change <= '0';
end if;
end process;
process (credit_in_E, valid_E, credit_counter_E_in, credit_counter_E_out)
begin
if (credit_in_E = '0' and valid_E = '0' and credit_counter_E_in /= credit_counter_E_out) then
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '1';
else
err_not_credit_in_E_not_grant_E_credit_counter_E_in_credit_counter_E_out_equal <= '0';
end if;
end process;
-- West credit counter
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if (credit_in_W = '1' and valid_W = '1' and credit_counter_W_in /= credit_counter_W_out) then
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '1';
else
err_credit_in_W_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '0';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if (credit_in_W = '1' and valid_W = '0' and credit_counter_W_out < 3 and credit_counter_W_in /= credit_counter_W_out + 1) then
err_credit_in_W_credit_counter_W_out_increment <= '1';
else
err_credit_in_W_credit_counter_W_out_increment <= '0';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if ( (credit_in_W = '1' and valid_W = '0' and credit_counter_W_out = 3) and credit_counter_W_in /= credit_counter_W_out) then
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change <= '1';
else
err_not_credit_in_W_credit_counter_W_out_max_credit_counter_W_in_not_change <= '0';
end if;
end process;
process (valid_W, credit_in_W, credit_counter_W_in, credit_counter_W_out)
begin
if (valid_W = '1' and credit_in_W = '0' and credit_counter_W_out > 0 and credit_counter_W_in /= credit_counter_W_out - 1) then
err_grant_W_credit_counter_W_out_decrement <= '1';
else
err_grant_W_credit_counter_W_out_decrement <= '0';
end if;
end process;
process (valid_W, credit_in_W, credit_counter_W_in, credit_counter_W_out)
begin
if ( valid_W = '1' and credit_in_W = '0' and credit_counter_W_out = 0 and credit_counter_W_in /= credit_counter_W_out) then
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change <= '1';
else
err_not_grant_W_or_credit_counter_W_out_zero_credit_counter_W_in_not_change <= '0';
end if;
end process;
process (credit_in_W, valid_W, credit_counter_W_in, credit_counter_W_out)
begin
if (credit_in_W = '0' and valid_W = '0' and credit_counter_W_in /= credit_counter_W_out) then
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '1';
else
err_not_credit_in_W_not_grant_W_credit_counter_W_in_credit_counter_W_out_equal <= '0';
end if;
end process;
-- South credit counter
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if (credit_in_S = '1' and valid_S = '1' and credit_counter_S_in /= credit_counter_S_out) then
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '1';
else
err_credit_in_S_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '0';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if (credit_in_S = '1' and valid_S = '0' and credit_counter_S_out < 3 and credit_counter_S_in /= credit_counter_S_out + 1) then
err_credit_in_S_credit_counter_S_out_increment <= '1';
else
err_credit_in_S_credit_counter_S_out_increment <= '0';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if ( credit_in_S = '1' and valid_S = '0' and credit_counter_S_out = 3 and credit_counter_S_in /= credit_counter_S_out) then
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change <= '1';
else
err_not_credit_in_S_credit_counter_S_out_max_credit_counter_S_in_not_change <= '0';
end if;
end process;
process (valid_S, credit_in_S, credit_counter_S_in, credit_counter_S_out)
begin
if (valid_S = '1' and credit_in_S = '0' and credit_counter_S_out > 0 and credit_counter_S_in /= credit_counter_S_out - 1) then
err_grant_S_credit_counter_S_out_decrement <= '1';
else
err_grant_S_credit_counter_S_out_decrement <= '0';
end if;
end process;
process (valid_S, credit_in_S, credit_counter_S_in, credit_counter_S_out)
begin
if (valid_S = '1' and credit_in_S = '0' and credit_counter_S_out = 0 and credit_counter_S_in /= credit_counter_S_out) then
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change <= '1';
else
err_not_grant_S_or_credit_counter_S_out_zero_credit_counter_S_in_not_change <= '0';
end if;
end process;
process (credit_in_S, valid_S, credit_counter_S_in, credit_counter_S_out)
begin
if (credit_in_S = '0' and valid_S = '0' and credit_counter_S_in /= credit_counter_S_out) then
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '1';
else
err_not_credit_in_S_not_grant_S_credit_counter_S_in_credit_counter_S_out_equal <= '0';
end if;
end process;
-- Local credit counter
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '1' and valid_L = '1' and credit_counter_L_in /= credit_counter_L_out) then
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '1';
else
err_credit_in_L_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '0';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '1' and valid_L = '0' and credit_counter_L_out < 3 and credit_counter_L_in /= credit_counter_L_out + 1) then
err_credit_in_L_credit_counter_L_out_increment <= '1';
else
err_credit_in_L_credit_counter_L_out_increment <= '0';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '1' and valid_L = '0' and credit_counter_L_out = 3 and credit_counter_L_in /= credit_counter_L_out) then
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change <= '1';
else
err_not_credit_in_L_credit_counter_L_out_max_credit_counter_L_in_not_change <= '0';
end if;
end process;
process (valid_L, credit_in_L, credit_counter_L_in, credit_counter_L_out)
begin
if (valid_L = '1' and credit_in_L = '0' and credit_counter_L_out > 0 and credit_counter_L_in /= credit_counter_L_out - 1) then
err_grant_L_credit_counter_L_out_decrement <= '1';
else
err_grant_L_credit_counter_L_out_decrement <= '0';
end if;
end process;
process (valid_L, credit_in_L, credit_counter_L_in, credit_counter_L_out)
begin
if (valid_L = '1' and credit_in_L = '0' and credit_counter_L_out = 0 and credit_counter_L_in /= credit_counter_L_out) then
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change <= '1';
else
err_not_grant_L_or_credit_counter_L_out_zero_credit_counter_L_in_not_change <= '0';
end if;
end process;
process (credit_in_L, valid_L, credit_counter_L_in, credit_counter_L_out)
begin
if (credit_in_L = '0' and valid_L = '0' and credit_counter_L_in /= credit_counter_L_out) then
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '1';
else
err_not_credit_in_L_not_grant_L_credit_counter_L_in_credit_counter_L_out_equal <= '0';
end if;
end process;
END;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
--
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
-- http://www.mesanet.com
--
-- This program is is licensed under a disjunctive dual license giving you
-- the choice of one of the two following sets of free software/open source
-- licensing terms:
--
-- * GNU General Public License (GPL), version 2.0 or later
-- * 3-clause BSD License
--
--
-- The GNU GPL License:
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
--
--
-- The 3-clause BSD License:
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- * Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- * Neither the name of Mesa Electronics nor the names of its
-- contributors may be used to endorse or promote products
-- derived from this software without specific prior written
-- permission.
--
--
-- Disclaimer:
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Created from usbram.obj
-- On 6/ 5/2008
entity usbram is
port (
addra: in std_logic_vector(10 downto 0);
addrb: in std_logic_vector(10 downto 0);
clk: in std_logic;
dina: in std_logic_vector(7 downto 0);
douta: out std_logic_vector(7 downto 0);
doutb: out std_logic_vector(7 downto 0);
wea: in std_logic);
end usbram;
architecture syn of usbram is
type ram_type is array (0 to 2047) of std_logic_vector(7 downto 0);
signal RAM : ram_type :=
(
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
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x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00", x"00",
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signal daddra: std_logic_vector(10 downto 0);
signal daddrb: std_logic_vector(10 downto 0);
begin
ausbram: process (clk)
begin
if (clk'event and clk = '1') then
if (wea = '1') then
RAM(conv_integer(addra)) <= dina;
end if;
daddra <= addra;
daddrb <= addrb;
end if; -- clk
end process;
douta <= RAM(conv_integer(daddra));
doutb <= RAM(conv_integer(daddrb));
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmutlbcam
-- File: mmutlbcam.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU TLB logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmutlbcam is
generic (
tlb_type : integer range 0 to 3 := 1;
mmupgsz : integer range 0 to 5 := 0
);
port (
rst : in std_logic;
clk : in std_logic;
tlbcami : in mmutlbcam_in_type;
tlbcamo : out mmutlbcam_out_type
);
end mmutlbcam;
architecture rtl of mmutlbcam is
constant M_TLB_FASTWRITE : integer range 0 to 3 := conv_integer(conv_std_logic_vector(tlb_type,2) and conv_std_logic_vector(2,2)); -- fast writebuffer
type tlbcam_rtype is record
btag : tlbcam_reg;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant ASYNC_RESET : boolean := GRLIB_CONFIG_ARRAY(grlib_async_reset_enable) = 1;
constant RRES : tlbcam_rtype := (btag => tlbcam_reg_none);
signal r,c : tlbcam_rtype;
begin
p0: process (rst, r, tlbcami)
variable v : tlbcam_rtype;
variable hm, hf : std_logic;
variable h_i1, h_i2, h_i3, h_c : std_logic;
variable h_l2, h_l3 : std_logic;
variable h_su_cnt : std_logic;
variable blvl : std_logic_vector(1 downto 0);
variable bet : std_logic_vector(1 downto 0);
variable bsu : std_logic;
variable blvl_decode : std_logic_vector(3 downto 0);
variable bet_decode : std_logic_vector(3 downto 0);
variable ref, modified : std_logic;
variable tlbcamo_pteout : std_logic_vector(31 downto 0);
variable tlbcamo_LVL : std_logic_vector(1 downto 0);
variable tlbcamo_NEEDSYNC : std_logic;
variable tlbcamo_WBNEEDSYNC : std_logic;
variable vaddr_r : std_logic_vector(31 downto 12);
variable vaddr_i : std_logic_vector(31 downto 12);
variable pagesize : integer range 0 to 3;
begin
v := r;
--#init
h_i1 := '0'; h_i2 := '0'; h_i3 := '0'; h_c := '0';
hm := '0'; pagesize := 0;
hf := r.btag.VALID;
blvl := r.btag.LVL;
bet := r.btag.ET;
bsu := r.btag.SU;
bet_decode := decode(bet);
blvl_decode := decode(blvl);
ref := r.btag.R;
modified := r.btag.M;
tlbcamo_pteout := (others => '0');
tlbcamo_lvl := (others => '0');
vaddr_r := r.btag.I1 & r.btag.I2 & r.btag.I3;
vaddr_i := tlbcami.tagin.I1 & tlbcami.tagin.I2 & tlbcami.tagin.I3;
-- prepare tag comparision
pagesize := MMU_getpagesize(mmupgsz,tlbcami.mmctrl);
case pagesize is
when 1 =>
-- 8k tag comparision [ 7 6 6 ]
if (vaddr_r(P8K_VA_I1_U downto P8K_VA_I1_D) = vaddr_i(P8K_VA_I1_U downto P8K_VA_I1_D)) then h_i1 := '1'; else h_i1 := '0'; end if;
if (vaddr_r(P8K_VA_I2_U downto P8K_VA_I2_D) = vaddr_i(P8K_VA_I2_U downto P8K_VA_I2_D)) then h_i2 := '1'; else h_i2 := '0'; end if;
if (vaddr_r(P8K_VA_I3_U downto P8K_VA_I3_D) = vaddr_i(P8K_VA_I3_U downto P8K_VA_I3_D)) then h_i3 := '1'; else h_i3 := '0'; end if;
if (r.btag.CTX = tlbcami.tagin.CTX) then h_c := '1'; else h_c := '0'; end if;
when 2 =>
-- 16k tag comparision [ 6 6 6 ]
if (vaddr_r(P16K_VA_I1_U downto P16K_VA_I1_D) = vaddr_i(P16K_VA_I1_U downto P16K_VA_I1_D)) then h_i1 := '1'; else h_i1 := '0'; end if;
if (vaddr_r(P16K_VA_I2_U downto P16K_VA_I2_D) = vaddr_i(P16K_VA_I2_U downto P16K_VA_I2_D)) then h_i2 := '1'; else h_i2 := '0'; end if;
if (vaddr_r(P16K_VA_I3_U downto P16K_VA_I3_D) = vaddr_i(P16K_VA_I3_U downto P16K_VA_I3_D)) then h_i3 := '1'; else h_i3 := '0'; end if;
if (r.btag.CTX = tlbcami.tagin.CTX) then h_c := '1'; else h_c := '0'; end if;
when 3 =>
-- 32k tag comparision [ 4 7 6 ]
if (vaddr_r(P32K_VA_I1_U downto P32K_VA_I1_D) = vaddr_i(P32K_VA_I1_U downto P32K_VA_I1_D)) then h_i1 := '1'; else h_i1 := '0'; end if;
if (vaddr_r(P32K_VA_I2_U downto P32K_VA_I2_D) = vaddr_i(P32K_VA_I2_U downto P32K_VA_I2_D)) then h_i2 := '1'; else h_i2 := '0'; end if;
if (vaddr_r(P32K_VA_I3_U downto P32K_VA_I3_D) = vaddr_i(P32K_VA_I3_U downto P32K_VA_I3_D)) then h_i3 := '1'; else h_i3 := '0'; end if;
if (r.btag.CTX = tlbcami.tagin.CTX) then h_c := '1'; else h_c := '0'; end if;
when others => -- standard 4k tag comparision [ 8 6 6 ]
if (r.btag.I1 = tlbcami.tagin.I1) then h_i1 := '1'; else h_i1 := '0'; end if;
if (r.btag.I2 = tlbcami.tagin.I2) then h_i2 := '1'; else h_i2 := '0'; end if;
if (r.btag.I3 = tlbcami.tagin.I3) then h_i3 := '1'; else h_i3 := '0'; end if;
if (r.btag.CTX = tlbcami.tagin.CTX) then h_c := '1'; else h_c := '0'; end if;
end case;
-- #level 2 hit (segment)
h_l2 := h_i1 and h_i2 ;
-- #level 3 hit (page)
h_l3 := h_i1 and h_i2 and h_i3;
-- # context + su
h_su_cnt := h_c or bsu;
--# translation (match) op
case blvl is
when LVL_PAGE => hm := h_l3 and h_c and r.btag.VALID;
when LVL_SEGMENT => hm := h_l2 and h_c and r.btag.VALID;
when LVL_REGION => hm := h_i1 and h_c and r.btag.VALID;
when LVL_CTX => hm := h_c and r.btag.VALID;
when others => hm := 'X';
end case;
--# translation: update ref/mod bit
tlbcamo_NEEDSYNC := '0';
if (tlbcami.trans_op and hm ) = '1' then
v.btag.R := '1';
v.btag.M := r.btag.M or tlbcami.tagin.M;
tlbcamo_NEEDSYNC := (not r.btag.R) or (tlbcami.tagin.M and (not r.btag.M)); -- cam: ref/modified changed, write back synchronously
end if;
tlbcamo_WBNEEDSYNC := '0';
if ( hm ) = '1' then
tlbcamo_WBNEEDSYNC := (not r.btag.R) or (tlbcami.tagin.M and (not r.btag.M)); -- cam: ref/modified changed, write back synchronously
end if;
--# flush operation
-- tlbcam only stores PTEs, tlb does not store PTDs
case tlbcami.tagin.TYP is
when FPTY_PAGE => -- page
hf := hf and h_su_cnt and h_l3 and (blvl_decode(0)); -- only level 3 (page)
when FPTY_SEGMENT => -- segment
hf := hf and h_su_cnt and h_l2 and (blvl_decode(0) or blvl_decode(1)); -- only level 2+3 (segment,page)
when FPTY_REGION => -- region
hf := hf and h_su_cnt and h_i1 and (not blvl_decode(3)); -- only level 1+2+3 (region,segment,page)
when FPTY_CTX => -- context
hf := hf and (h_c and (not bsu));
when FPTY_N => -- entire
when others =>
hf := '0';
end case;
--# flush: invalidate on flush hit
--if (tlbcami.flush_op and hf ) = '1' then
if (tlbcami.flush_op ) = '1' then
v.btag.VALID := '0';
end if;
--# write op
if ( tlbcami.write_op = '1' ) then
v.btag := tlbcami.tagwrite;
end if;
--# reset
if ((not ASYNC_RESET) and (not RESET_ALL) and (rst = '0')) or (tlbcami.mmuen = '0') then
v.btag.VALID := RRES.btag.VALID;
end if;
tlbcamo_pteout(PTE_PPN_U downto PTE_PPN_D) := r.btag.PPN;
tlbcamo_pteout(PTE_C) := r.btag.C;
tlbcamo_pteout(PTE_M) := r.btag.M;
tlbcamo_pteout(PTE_R) := r.btag.R;
tlbcamo_pteout(PTE_ACC_U downto PTE_ACC_D) := r.btag.ACC;
tlbcamo_pteout(PT_ET_U downto PT_ET_D) := r.btag.ET;
tlbcamo_LVL(1 downto 0) := r.btag.LVL;
--# drive signals
tlbcamo.pteout <= tlbcamo_pteout;
tlbcamo.LVL <= tlbcamo_LVL;
--tlbcamo.hit <= (tlbcami.trans_op and hm) or (tlbcami.flush_op and hf);
tlbcamo.hit <= (hm) or (tlbcami.flush_op and hf);
tlbcamo.ctx <= r.btag.CTX; -- for diagnostic only
tlbcamo.valid <= r.btag.VALID; -- for diagnostic only
tlbcamo.vaddr <= r.btag.I1 & r.btag.I2 & r.btag.I3 & "000000000000"; -- for diagnostic only
tlbcamo.NEEDSYNC <= tlbcamo_NEEDSYNC;
tlbcamo.WBNEEDSYNC <= tlbcamo_WBNEEDSYNC;
c <= v;
end process p0;
syncrregs : if not ASYNC_RESET generate
p1: process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r <= RRES;
end if;
end if;
end process p1;
end generate;
asyncrregs : if ASYNC_RESET generate
p1: process (clk, rst)
begin
if rst = '0' then
r <= RRES;
elsif rising_edge(clk) then
r <= c;
end if;
end process p1;
end generate;
end rtl;
|
entity sklopI is port (
a,b: in std_logic;
f, test: out std_logic);
end sklopI;
architecture pon of sklopI is
signal pomocni: std_logic;
begin
pomocni <= a and b after 3 s;
f <= pomocni after 100 ms;
test <= pomocni after 2 s;
end pon;
|
-----------------------------------------------------------------------------
--
-- AVR opcode package
--
-- This package defines opcode constants for the complete AVR instruction
-- set. Not all variants of the AVR implement all instructions.
--
-- Revision History
-- 4/27/98 Glen George initial revision
-- 4/14/00 Glen George updated comments
-- 4/22/02 Glen George added new instructions
-- 4/22/02 Glen George updated comments
-- 5/16/02 Glen George fixed LPM instruction constant
--
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package ALUCommands is
-- ALU Blocks for ALUBlockSel
constant ALUAddBlock : std_logic_vector(1 downto 0) := "00";
constant ALUFBlock : std_logic_vector(1 downto 0) := "01";
constant ALUShiftBlock : std_logic_vector(1 downto 0) := "10";
constant ALUMulBlock : std_logic_vector(1 downto 0) := "11";
-- ALU Block Instructions for BlockInstructionSel
--F Block
constant FBlockZERO : std_logic_vector(3 downto 0) := "0000";
constant FBlockNOR : std_logic_vector(3 downto 0) := "0001";
constant FBlockNOTA : std_logic_vector(3 downto 0) := "0011";
constant FBlockNOTB : std_logic_vector(3 downto 0) := "0101";
constant FBlockXOR : std_logic_vector(3 downto 0) := "0110";
constant FBlockNAND : std_logic_vector(3 downto 0) := "0111";
constant FBlockAND : std_logic_vector(3 downto 0) := "1000";
constant FBlockXNOR : std_logic_vector(3 downto 0) := "1001";
constant FBlockOR : std_logic_vector(3 downto 0) := "1110";
constant FBlockONE : std_logic_vector(3 downto 0) := "1111";
--Shift Block
--bit 2 - shift 1 vs shift 4
--bit 1:0 - high bit source: 00 => 0, 01 => A0, 10 => An
constant ShiftBlockArith : std_logic_vector(3 downto 0) := "0010";
constant ShiftBlockLog : std_logic_vector(3 downto 0) := "0000";
constant ShiftBlockRot : std_logic_vector(3 downto 0) := "0001";
constant ShiftBlockSwap : std_logic_vector(3 downto 0) := "0100";
--Add Block
constant AddBlockAdd : std_logic_vector(3 downto 0) := "0000";
constant AddBlockSub : std_logic_vector(3 downto 0) := "0010";
constant AddBlockAddCarry : std_logic_vector(3 downto 0) := "0001";
constant AddBlockSubCarry : std_logic_vector(3 downto 0) := "0011";
constant AddBlockNeg : std_logic_vector(3 downto 0) := "0100";
--Multiply Block
constant MulBlockLowByte : std_logic_vector(3 downto 0) := "0000";
constant MulBlockHighByte : std_logic_vector(3 downto 0) := "0001";
-- ALU Flags
constant flag_C : integer := 0;
constant flag_Z : integer := 1;
constant flag_N : integer := 2;
constant flag_V : integer := 3;
constant flag_S : integer := 4;
constant flag_H : integer := 5;
constant flag_T : integer := 6;
constant flag_I : integer := 7;
-- ALU Flag Masks ITHSVNZC
constant flag_mask_ZCNVSH : std_logic_vector(7 downto 0) := "00111111";
constant flag_mask_ZCNVS : std_logic_vector(7 downto 0) := "00011111";
constant flag_mask_ZNVS : std_logic_vector(7 downto 0) := "00011110";
constant flag_mask_T : std_logic_vector(7 downto 0) := "01000000";
constant flag_mask_ZC : std_logic_vector(7 downto 0) := "00000011";
constant flag_mask_KEEPALL: std_logic_vector(7 downto 0) := "00000000";
-- ALU Operand 2 Select (ALUOp2Sel) Values
constant RegOp2 : std_logic := '0'; --Operand 2 is from registers
constant ImmedOp2 : std_logic := '1'; --Operand 2 is immediate
constant StatusBitClear : std_logic := '0';
constant StatusBitSet : std_logic := '1';
end package; |
-------- Clock Divisor -----------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.processor_functions.all;
----------------------------------------------------------------------------------
ENTITY clock_divisor IS
PORT (clk, nrst : IN STD_LOGIC; -- clock de entrada, que é o de 25MHz da placa
clk_out : BUFFER STD_LOGIC); -- clock de saída, configurável pelo "clk_frequency" de "processor_functions"
END ENTITY clock_divisor;
----------------------------------------------------------------------------------
ARCHITECTURE rtl OF clock_divisor IS
BEGIN
PROCESS (clk, nrst)
VARIABLE count : INTEGER RANGE 0 TO clk_frequency;
BEGIN
IF (nrst = '0') THEN
count := 0;
clk_out <= '0';
ELSIF rising_edge(clk) THEN
count := count + 1;
IF (count = clk_frequency) THEN
clk_out <= NOT clk_out;
count := 0;
END IF;
END IF;
END PROCESS;
END rtl; |
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity RAM_16_8 is
port( clk : in std_logic;
writeEnable : in std_logic;
address : in std_logic_vector(3 downto 0);
writeData : in std_logic_vector(7 downto 0);
readData : out std_logic_vector(7 downto 0));
end Ram_16_8;
architecture Behavioral of Ram_16_8 is
subtype memory is std_logic_vector(7 downto 0);
type Ram1 is array (15 downto 0) of memory;
signal ram : Ram1;
begin
process(clk)
begin
if(rising_edge(clk)) then
if(writeEnable='1') then
Ram(to_integer(unsigned(address))) <= writeData;
end if;
end if;
end process;
readData <= Ram(to_integer(unsigned(address)));
end Behavioral; |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_118 is
port (
result : out std_logic_vector(15 downto 0);
in_a : in std_logic_vector(15 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end add_118;
architecture augh of add_118 is
signal carry_inA : std_logic_vector(17 downto 0);
signal carry_inB : std_logic_vector(17 downto 0);
signal carry_res : std_logic_vector(17 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(16 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_118 is
port (
result : out std_logic_vector(15 downto 0);
in_a : in std_logic_vector(15 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end add_118;
architecture augh of add_118 is
signal carry_inA : std_logic_vector(17 downto 0);
signal carry_inB : std_logic_vector(17 downto 0);
signal carry_res : std_logic_vector(17 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(16 downto 1);
end architecture;
|
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
-- Violation below
entity FIFO is
GENERIC(
g_size : integer := 10;
g_width : integer := 256;
g_depth : integer := 32
);
end entity FIFO;
|
-------------------------------------------------------------------------------
-- File : bmp_source.vhd
-- Author : mr-kenhoff
-------------------------------------------------------------------------------
-- Description:
-- Outputs a bitmap image as a data stream
-- Target: Simulator
-- Dependencies: bmp_pkg.vhd
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.bmp_pkg.all;
entity bmp_source is
generic (
FILENAME : string;
ITERATIONS : natural;
BACKPRESSURE_EN : boolean := false
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
val_o : out std_logic := '0';
dat_o : out std_logic_vector(23 downto 0) := (others => '0');
rdy_i : in std_logic;
eol_o : out std_logic := '0';
eof_o : out std_logic := '0'
);
end entity;
architecture behavioural of bmp_source is
begin
source_process : process( clk_i )
variable source_bmp : bmp_ptr;
variable source_pix : bmp_pix;
variable is_bmp_loaded : boolean := false;
variable iteration : natural := 0;
variable x : natural := 0;
variable y : natural := 0;
begin
if is_bmp_loaded = false then
source_bmp := new bmp;
bmp_open(source_bmp, FILENAME);
is_bmp_loaded := true;
end if;
if rising_edge( clk_i ) then
eol_o <= '0';
eof_o <= '0';
val_o <= '0';
if rst_i = '1' then
iteration := 0;
x := 0;
y := 0;
else
if (BACKPRESSURE_EN and rdy_i = '1') or not BACKPRESSURE_EN then
if iteration < ITERATIONS then
bmp_get_pix( source_bmp, x, y, source_pix );
dat_o(23 downto 16) <= source_pix.r;
dat_o(15 downto 8) <= source_pix.g;
dat_o(7 downto 0) <= source_pix.b;
val_o <= '1';
if x = source_bmp.meta.width-1 then -- EOL
eol_o <= '1';
x := 0;
if y = source_bmp.meta.height-1 then -- EOF
eof_o <= '1';
y := 0;
iteration := iteration + 1;
else -- Not EOF
y := y + 1;
end if;
else -- Not EOL
x := x + 1;
end if;
end if; -- if iteration < ITERATIONS
end if;
end if;
end if;
end process;
end architecture;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/TWDLROM_3_11.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLROM_3_11
-- Source Path: ifft_16_bit/IFFT HDL Optimized/TWDLROM_3_11
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.ifft_16_bit_pkg.ALL;
ENTITY TWDLROM_3_11 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_11_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_11_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_11_vld : OUT std_logic
);
END TWDLROM_3_11;
ARCHITECTURE rtl OF TWDLROM_3_11 IS
-- Constants
CONSTANT Twiddle_re_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#08000#, 17), to_signed(16#07642#, 17)); -- sfix17 [2]
CONSTANT Twiddle_im_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#00000#, 17), to_signed(-16#030FC#, 17)); -- sfix17 [2]
-- Signals
SIGNAL Radix22TwdlMapping_cnt : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1 : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2 : std_logic;
SIGNAL Radix22TwdlMapping_cnt_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1_next : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw_next : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap_next : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2_next : std_logic;
SIGNAL twdlAddr : std_logic; -- ufix1
SIGNAL twdlAddrVld : std_logic;
SIGNAL twdlOctant : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45 : std_logic;
SIGNAL Twiddle_re_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL Twiddle_im_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdlOctantReg : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45Reg : std_logic;
SIGNAL twdl_3_11_re_tmp : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_11_im_tmp : signed(16 DOWNTO 0); -- sfix17_En15
BEGIN
-- Radix22TwdlMapping
Radix22TwdlMapping_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22TwdlMapping_octantReg1 <= to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdlAddr_raw <= to_unsigned(16#0#, 4);
Radix22TwdlMapping_twdlAddrMap <= '0';
Radix22TwdlMapping_twdl45Reg <= '0';
Radix22TwdlMapping_dvldReg1 <= '0';
Radix22TwdlMapping_dvldReg2 <= '0';
Radix22TwdlMapping_cnt <= to_unsigned(16#2#, 2);
Radix22TwdlMapping_phase <= to_unsigned(16#2#, 2);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22TwdlMapping_cnt <= Radix22TwdlMapping_cnt_next;
Radix22TwdlMapping_phase <= Radix22TwdlMapping_phase_next;
Radix22TwdlMapping_octantReg1 <= Radix22TwdlMapping_octantReg1_next;
Radix22TwdlMapping_twdlAddr_raw <= Radix22TwdlMapping_twdlAddr_raw_next;
Radix22TwdlMapping_twdlAddrMap <= Radix22TwdlMapping_twdlAddrMap_next;
Radix22TwdlMapping_twdl45Reg <= Radix22TwdlMapping_twdl45Reg_next;
Radix22TwdlMapping_dvldReg1 <= Radix22TwdlMapping_dvldReg1_next;
Radix22TwdlMapping_dvldReg2 <= Radix22TwdlMapping_dvldReg2_next;
END IF;
END IF;
END PROCESS Radix22TwdlMapping_process;
Radix22TwdlMapping_output : PROCESS (Radix22TwdlMapping_cnt, Radix22TwdlMapping_phase,
Radix22TwdlMapping_octantReg1, Radix22TwdlMapping_twdlAddr_raw,
Radix22TwdlMapping_twdlAddrMap, Radix22TwdlMapping_twdl45Reg,
Radix22TwdlMapping_dvldReg1, Radix22TwdlMapping_dvldReg2, dout_2_vld)
VARIABLE octant : unsigned(2 DOWNTO 0);
VARIABLE cnt_cast : unsigned(3 DOWNTO 0);
VARIABLE sub_cast : signed(9 DOWNTO 0);
VARIABLE sub_temp : signed(9 DOWNTO 0);
VARIABLE sub_cast_0 : signed(5 DOWNTO 0);
VARIABLE sub_temp_0 : signed(5 DOWNTO 0);
VARIABLE sub_cast_1 : signed(5 DOWNTO 0);
VARIABLE sub_temp_1 : signed(5 DOWNTO 0);
VARIABLE sub_cast_2 : signed(9 DOWNTO 0);
VARIABLE sub_temp_2 : signed(9 DOWNTO 0);
VARIABLE sub_cast_3 : signed(9 DOWNTO 0);
VARIABLE sub_temp_3 : signed(9 DOWNTO 0);
BEGIN
Radix22TwdlMapping_twdlAddr_raw_next <= Radix22TwdlMapping_twdlAddr_raw;
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddrMap;
Radix22TwdlMapping_twdl45Reg_next <= Radix22TwdlMapping_twdl45Reg;
Radix22TwdlMapping_dvldReg2_next <= Radix22TwdlMapping_dvldReg1;
Radix22TwdlMapping_dvldReg1_next <= dout_2_vld;
CASE Radix22TwdlMapping_twdlAddr_raw IS
WHEN "0010" =>
octant := to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "0100" =>
octant := to_unsigned(16#1#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "0110" =>
octant := to_unsigned(16#2#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "1000" =>
octant := to_unsigned(16#3#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "1010" =>
octant := to_unsigned(16#4#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN OTHERS =>
octant := Radix22TwdlMapping_twdlAddr_raw(3 DOWNTO 1);
Radix22TwdlMapping_twdl45Reg_next <= '0';
END CASE;
Radix22TwdlMapping_octantReg1_next <= octant;
CASE octant IS
WHEN "000" =>
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddr_raw(0);
WHEN "001" =>
sub_cast_0 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_0 := to_signed(16#04#, 6) - sub_cast_0;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_0(0);
WHEN "010" =>
sub_cast_1 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_1 := sub_cast_1 - to_signed(16#04#, 6);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_1(0);
WHEN "011" =>
sub_cast_2 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_2 := to_signed(16#010#, 10) - sub_cast_2;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_2(1);
WHEN "100" =>
sub_cast_3 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_3 := sub_cast_3 - to_signed(16#010#, 10);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_3(1);
WHEN OTHERS =>
sub_cast := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp := to_signed(16#018#, 10) - sub_cast;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp(1);
END CASE;
IF Radix22TwdlMapping_phase = to_unsigned(16#0#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= to_unsigned(16#0#, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#1#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4) sll 1;
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#2#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4);
ELSE
cnt_cast := resize(Radix22TwdlMapping_cnt, 4);
Radix22TwdlMapping_twdlAddr_raw_next <= (cnt_cast sll 1) + cnt_cast;
END IF;
Radix22TwdlMapping_phase_next <= to_unsigned(16#2#, 2);
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt + to_unsigned(16#000000010#, 2);
twdlAddr <= Radix22TwdlMapping_twdlAddrMap;
twdlAddrVld <= Radix22TwdlMapping_dvldReg2;
twdlOctant <= Radix22TwdlMapping_octantReg1;
twdl45 <= Radix22TwdlMapping_twdl45Reg;
END PROCESS Radix22TwdlMapping_output;
-- Twiddle ROM1
Twiddle_re_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_re <= Twiddle_re_table_data(to_integer(Twiddle_re_cast));
TWIDDLEROM_RE_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_re <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_re <= twiddleS_re;
END IF;
END IF;
END PROCESS TWIDDLEROM_RE_process;
-- Twiddle ROM2
Twiddle_im_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_im <= Twiddle_im_table_data(to_integer(Twiddle_im_cast));
TWIDDLEROM_IM_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_im <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_im <= twiddleS_im;
END IF;
END IF;
END PROCESS TWIDDLEROM_IM_process;
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdlOctantReg <= to_unsigned(16#0#, 3);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdlOctantReg <= twdlOctant;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl45Reg <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl45Reg <= twdl45;
END IF;
END IF;
END PROCESS intdelay_1_process;
-- Radix22TwdlOctCorr
Radix22TwdlOctCorr_output : PROCESS (twiddleReg_re, twiddleReg_im, twdlOctantReg, twdl45Reg)
VARIABLE twdlIn_re : signed(16 DOWNTO 0);
VARIABLE twdlIn_im : signed(16 DOWNTO 0);
VARIABLE cast : signed(17 DOWNTO 0);
VARIABLE cast_0 : signed(17 DOWNTO 0);
VARIABLE cast_1 : signed(17 DOWNTO 0);
VARIABLE cast_2 : signed(17 DOWNTO 0);
VARIABLE cast_3 : signed(17 DOWNTO 0);
VARIABLE cast_4 : signed(17 DOWNTO 0);
VARIABLE cast_5 : signed(17 DOWNTO 0);
VARIABLE cast_6 : signed(17 DOWNTO 0);
VARIABLE cast_7 : signed(17 DOWNTO 0);
VARIABLE cast_8 : signed(17 DOWNTO 0);
VARIABLE cast_9 : signed(17 DOWNTO 0);
VARIABLE cast_10 : signed(17 DOWNTO 0);
BEGIN
twdlIn_re := twiddleReg_re;
twdlIn_im := twiddleReg_im;
IF twdl45Reg = '1' THEN
CASE twdlOctantReg IS
WHEN "000" =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "010" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "100" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(16#05A82#, 17);
WHEN OTHERS =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
END CASE;
ELSE
CASE twdlOctantReg IS
WHEN "000" =>
NULL;
WHEN "001" =>
cast := resize(twiddleReg_im, 18);
cast_0 := - (cast);
twdlIn_re := cast_0(16 DOWNTO 0);
cast_5 := resize(twiddleReg_re, 18);
cast_6 := - (cast_5);
twdlIn_im := cast_6(16 DOWNTO 0);
WHEN "010" =>
twdlIn_re := twiddleReg_im;
cast_7 := resize(twiddleReg_re, 18);
cast_8 := - (cast_7);
twdlIn_im := cast_8(16 DOWNTO 0);
WHEN "011" =>
cast_1 := resize(twiddleReg_re, 18);
cast_2 := - (cast_1);
twdlIn_re := cast_2(16 DOWNTO 0);
twdlIn_im := twiddleReg_im;
WHEN "100" =>
cast_3 := resize(twiddleReg_re, 18);
cast_4 := - (cast_3);
twdlIn_re := cast_4(16 DOWNTO 0);
cast_9 := resize(twiddleReg_im, 18);
cast_10 := - (cast_9);
twdlIn_im := cast_10(16 DOWNTO 0);
WHEN OTHERS =>
twdlIn_re := twiddleReg_im;
twdlIn_im := twiddleReg_re;
END CASE;
END IF;
twdl_3_11_re_tmp <= twdlIn_re;
twdl_3_11_im_tmp <= twdlIn_im;
END PROCESS Radix22TwdlOctCorr_output;
twdl_3_11_re <= std_logic_vector(twdl_3_11_re_tmp);
twdl_3_11_im <= std_logic_vector(twdl_3_11_im_tmp);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_3_11_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl_3_11_vld <= twdlAddrVld;
END IF;
END IF;
END PROCESS intdelay_2_process;
END rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VHDL_lib.all;
entity clk_div is
generic(
div:integer := 8
);
port(
input: in std_logic;
output: out std_logic;
state: out std_logic_vector(log2(div/2)-1 downto 0)
);
end clk_div;
architecture Behavioral of clk_div is
signal timer: std_logic_vector(log2(div/2)-1 downto 0) := (others=>'0');
signal out_clk: std_logic := '0';
begin
output <= out_clk;
state <= timer;
clk_div_signal:process(input)
begin
if(input'event and input = '1')then
timer <= timer + 1;
if(timer = div/2-1)then
timer <= (others=>'0');
out_clk <= not out_clk;
end if;
end if;
end process;
end Behavioral;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:rgb565_to_rgb888:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rgb565_to_rgb888_0_0 IS
PORT (
clk : IN STD_LOGIC;
rgb_565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_888 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_rgb565_to_rgb888_0_0;
ARCHITECTURE system_rgb565_to_rgb888_0_0_arch OF system_rgb565_to_rgb888_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rgb565_to_rgb888_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb565_to_rgb888 IS
PORT (
clk : IN STD_LOGIC;
rgb_565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_888 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT rgb565_to_rgb888;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_rgb565_to_rgb888_0_0_arch: ARCHITECTURE IS "rgb565_to_rgb888,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_rgb565_to_rgb888_0_0_arch : ARCHITECTURE IS "system_rgb565_to_rgb888_0_0,rgb565_to_rgb888,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_rgb565_to_rgb888_0_0_arch: ARCHITECTURE IS "system_rgb565_to_rgb888_0_0,rgb565_to_rgb888,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=rgb565_to_rgb888,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : rgb565_to_rgb888
PORT MAP (
clk => clk,
rgb_565 => rgb_565,
rgb_888 => rgb_888
);
END system_rgb565_to_rgb888_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:rgb565_to_rgb888:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rgb565_to_rgb888_0_0 IS
PORT (
clk : IN STD_LOGIC;
rgb_565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_888 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_rgb565_to_rgb888_0_0;
ARCHITECTURE system_rgb565_to_rgb888_0_0_arch OF system_rgb565_to_rgb888_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rgb565_to_rgb888_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb565_to_rgb888 IS
PORT (
clk : IN STD_LOGIC;
rgb_565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_888 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT rgb565_to_rgb888;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_rgb565_to_rgb888_0_0_arch: ARCHITECTURE IS "rgb565_to_rgb888,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_rgb565_to_rgb888_0_0_arch : ARCHITECTURE IS "system_rgb565_to_rgb888_0_0,rgb565_to_rgb888,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_rgb565_to_rgb888_0_0_arch: ARCHITECTURE IS "system_rgb565_to_rgb888_0_0,rgb565_to_rgb888,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=rgb565_to_rgb888,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : rgb565_to_rgb888
PORT MAP (
clk => clk,
rgb_565 => rgb_565,
rgb_888 => rgb_888
);
END system_rgb565_to_rgb888_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:rgb565_to_rgb888:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rgb565_to_rgb888_0_0 IS
PORT (
clk : IN STD_LOGIC;
rgb_565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_888 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_rgb565_to_rgb888_0_0;
ARCHITECTURE system_rgb565_to_rgb888_0_0_arch OF system_rgb565_to_rgb888_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rgb565_to_rgb888_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb565_to_rgb888 IS
PORT (
clk : IN STD_LOGIC;
rgb_565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_888 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT rgb565_to_rgb888;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_rgb565_to_rgb888_0_0_arch: ARCHITECTURE IS "rgb565_to_rgb888,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_rgb565_to_rgb888_0_0_arch : ARCHITECTURE IS "system_rgb565_to_rgb888_0_0,rgb565_to_rgb888,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_rgb565_to_rgb888_0_0_arch: ARCHITECTURE IS "system_rgb565_to_rgb888_0_0,rgb565_to_rgb888,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=rgb565_to_rgb888,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : rgb565_to_rgb888
PORT MAP (
clk => clk,
rgb_565 => rgb_565,
rgb_888 => rgb_888
);
END system_rgb565_to_rgb888_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:rgb565_to_rgb888:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rgb565_to_rgb888_0_0 IS
PORT (
clk : IN STD_LOGIC;
rgb_565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_888 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_rgb565_to_rgb888_0_0;
ARCHITECTURE system_rgb565_to_rgb888_0_0_arch OF system_rgb565_to_rgb888_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rgb565_to_rgb888_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb565_to_rgb888 IS
PORT (
clk : IN STD_LOGIC;
rgb_565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_888 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT rgb565_to_rgb888;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_rgb565_to_rgb888_0_0_arch: ARCHITECTURE IS "rgb565_to_rgb888,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_rgb565_to_rgb888_0_0_arch : ARCHITECTURE IS "system_rgb565_to_rgb888_0_0,rgb565_to_rgb888,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_rgb565_to_rgb888_0_0_arch: ARCHITECTURE IS "system_rgb565_to_rgb888_0_0,rgb565_to_rgb888,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=rgb565_to_rgb888,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : rgb565_to_rgb888
PORT MAP (
clk => clk,
rgb_565 => rgb_565,
rgb_888 => rgb_888
);
END system_rgb565_to_rgb888_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:rgb565_to_rgb888:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rgb565_to_rgb888_0_0 IS
PORT (
clk : IN STD_LOGIC;
rgb_565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_888 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_rgb565_to_rgb888_0_0;
ARCHITECTURE system_rgb565_to_rgb888_0_0_arch OF system_rgb565_to_rgb888_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rgb565_to_rgb888_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb565_to_rgb888 IS
PORT (
clk : IN STD_LOGIC;
rgb_565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_888 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT rgb565_to_rgb888;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_rgb565_to_rgb888_0_0_arch: ARCHITECTURE IS "rgb565_to_rgb888,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_rgb565_to_rgb888_0_0_arch : ARCHITECTURE IS "system_rgb565_to_rgb888_0_0,rgb565_to_rgb888,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_rgb565_to_rgb888_0_0_arch: ARCHITECTURE IS "system_rgb565_to_rgb888_0_0,rgb565_to_rgb888,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=rgb565_to_rgb888,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : rgb565_to_rgb888
PORT MAP (
clk => clk,
rgb_565 => rgb_565,
rgb_888 => rgb_888
);
END system_rgb565_to_rgb888_0_0_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2728.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s05b00x00p01n01i02728ent IS
END c13s05b00x00p01n01i02728ent;
ARCHITECTURE c13s05b00x00p01n01i02728arch OF c13s05b00x00p01n01i02728ent IS
BEGIN
TESTING: PROCESS
variable k : character;
BEGIN
k := '';
assert FALSE
report "***FAILED TEST: c13s05b00x00p01n01i02728 - A character literal may not be empty."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s05b00x00p01n01i02728arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2728.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s05b00x00p01n01i02728ent IS
END c13s05b00x00p01n01i02728ent;
ARCHITECTURE c13s05b00x00p01n01i02728arch OF c13s05b00x00p01n01i02728ent IS
BEGIN
TESTING: PROCESS
variable k : character;
BEGIN
k := '';
assert FALSE
report "***FAILED TEST: c13s05b00x00p01n01i02728 - A character literal may not be empty."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s05b00x00p01n01i02728arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2728.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s05b00x00p01n01i02728ent IS
END c13s05b00x00p01n01i02728ent;
ARCHITECTURE c13s05b00x00p01n01i02728arch OF c13s05b00x00p01n01i02728ent IS
BEGIN
TESTING: PROCESS
variable k : character;
BEGIN
k := '';
assert FALSE
report "***FAILED TEST: c13s05b00x00p01n01i02728 - A character literal may not be empty."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s05b00x00p01n01i02728arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Rob Mushrall
-- Timothy Doucette Jr
-- Christopher Parks
--
-- Create Date: 15:43:26 03/25/2016
-- Design Name:
-- Module Name: ProjLab01 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
entity ProjLab01 is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
--instruction : in STD_LOGIC_VECTOR (15 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (15 downto 0);
DST_ADR : out STD_LOGIC_VECTOR (15 downto 0);
STORE_DATA : out STD_LOGIC_VECTOR (15 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0));
end ProjLab01;
architecture Structural of ProjLab01 is
signal OP1, OP2, OP3, OP4 : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal RA1, RA2, RA3 : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal RA4 : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '1');
signal RB1, RB2, RB3, RB4 : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal PC0, PC1, PC2, PC3, PC4 : STD_LOGIC_VECTOR (4 downto 0) := (OTHERS => '0');
signal IMM1, IMM2, IMM3 : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal GLOBAL_EN : STD_LOGIC := '1'; -- Determines whether things are enabled (allowed to operate)
signal IMM_SEL : STD_LOGIC := '0'; -- Determines selection between immediate data and RB
signal PC_EN, PC_INC : STD_LOGIC := '1'; -- Program counter enable
signal PC_RST : STD_LOGIC := '0';
signal INST_EN : STD_LOGIC := '1'; -- Enables instruction memory
signal RD_EN, WR_EN : STD_LOGIC := '0'; -- Enables the register bank to read, write
signal OPR1, OPR2, OPRB :STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0'); -- From reg bank to RA and RB data registers
signal OPIN : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal RAIN : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal RBIN : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal IMMIN : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal IMSEL : STD_LOGIC := '0';
signal OP1_SEL, OP2_SEL : STD_LOGIC_VECTOR (1 downto 0):= (OTHERS => '0'); -- Selector for data contention
signal ALU_RESULT : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0'); -- Latched Result of ALU
signal ALU_VAL : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0'); -- Result direct from ALU
signal ALU_OUT_FLAGS : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0'); -- flags output from ALU
signal ALU_FLAGS : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0'); -- latched flags from ALU
signal RA_IN, RB_IN : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0'); -- Values to go to DC Muxes
signal RA_OUT, RB_OUT : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0'); -- Values from DC muxes to ALU
signal ALU_DC1, ALU_DC2: STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0'); -- Data contention ALU values
signal RA_DC1, RA_DC2: STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '1'); -- Data contention RA values
signal RB_DC1, RB_DC2: STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '1'); -- Data contention RB values
signal DATARD_EN, DATAWR_EN: STD_LOGIC := '0'; -- Enable reading or writing to/from Data Memory
----------------------------------------
-- Project lab 2 --
----------------------------------------
signal SHADOW_DAT : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0'); --Shadow Register output signal
signal EX_ADDR : STD_LOGIC_VECTOR (13 downto 0) := (OTHERS => '0'); --Shadow_Reg + IMM output
signal EX_ADDR_OUT : STD_LOGIC_VECTOR (13 downto 0) := (OTHERS => '0'); --Shadow_Reg + IMM output
signal EX_DATA : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal ALU_EX_MUX : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal EX_WR : STD_LOGIC := '0';
signal EX_RD : STD_LOGIC := '0';
begin
ALU_OUT <= ALU_RESULT;
CCR <= ALU_FLAGS;
-------- Debugging I/O --------
---------------------------------
--ALU_OUT <= "000" & RA4 & RB4 & PC4; --ALU_RESULT;
--STORE_DATA <= "000" & IMSEL & OP4 & IMM3;
--OPIN <= instruction(15 downto 12);
--RAIN <= instruction(11 downto 8);
--RBIN <= instruction(7 downto 4);
--IMMIN <= instruction (7 downto 0);
-------- ALU --------
-----------------------
ALU_UNIT : entity work.ALU_Toplevel
port map(RA => RA_OUT,
RB => RB_OUT,
OP => OP3,
CLK => CLK,
ALU_OUT => ALU_VAL,
SREG => ALU_OUT_FLAGS,
LDST_DAT => STORE_DATA,
LDST_ADR => DST_ADR);
-------- Fetch --------
-------------------------
Fetch_UNIT : entity work.Instruction_Memory_TL
port map( CLK => CLK,
RST => RST,
RA => RAIN,
RB => RBIN,
OP => OPIN,
IMM => IMMIN);
-------- Control Units --------
---------------------------------
-- DISPTCH : entity work.Dispatch port map(CLK => CLK, -- (in)
-- OPC => OP2, -- (in)
-- RA => RA2, -- (in)
-- RB => RB2, -- (in)
-- RA4 => RA4, -- (in)
-- IMM_SEL => IMM_SEL, -- (out)
-- DC1 => DC2_1, -- (out)
-- DC2 => DC2_2); -- Dispatch control unit (out)
-- FETCH : entity work.Fetch_CTL port map(CLK => CLK, -- (in)
-- EN => GLOBAL_EN, -- (in)
-- RST => PC_RST, -- (out)
-- INC => PC_INC, -- (out)
-- PC_EN => PC_EN, -- (out)
-- INST_EN => INST_EN); -- Fetch control unit (out)
REGCTL : entity work.REG_CTL port map(CLK => CLK, -- (in)
OPC => OP1, -- (in)
OPC4 => OP4, -- (in)
RD_EN => RD_EN, -- (out)
WR_EN => WR_EN); -- Register control unit (out)
DCCTL : entity work.DC_CTL port map(CLK => CLK, -- (in)
RA => RA3, -- (in)
RB => RB3,
RA0 => RA4,
-- RB0 => RB4,
RA1 => RA_DC1,
RA2 => RA_DC2,
-- RB1 => RB_DC1,
-- RB2 => RB_DC2,
OPC => OP3, -- (in)
OP1_SEL => OP1_SEL, -- (out)
OP2_SEL => OP2_SEL); -- Data contention (out)
DATA_CTL : entity work.DATA_CTL
port map(CLK => CLK,
EN => GLOBAL_EN,
OP => OP3,
RD_EN => DATARD_EN,
WR_EN => DATAWR_EN);
IMSELECT : entity work.IMSEL
port map(OP => OP2,
SEL_IM => IMSEL);
-------- Pipeline Registers --------
--------------------------------------
----> Stage One <----
OP1_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => OPIN,
Dout => OP1);
RA1_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => RAIN,
Dout => RA1);
RB1_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => RBIN,
Dout => RB1);
IMM1_Reg: entity work.PipelineRegisters
generic map( dataWidth => 8)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => IMMIN,
Dout => IMM1);
PC1_Reg: entity work.PipelineRegisters
generic map( dataWidth => 5)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => PC0,
Dout => PC1);
----> Stage Two <----
OP2_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => OP1,
Dout => OP2);
RA2ADR_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => RA1,
Dout => RA2);
RB2ADR_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => RB1,
Dout => RB2);
OPR0_Reg: entity work.PipelineRegisters
generic map( dataWidth => 8)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => IMM1,
Dout => IMM2);
-- OPR1_Reg: entity work.PipelineRegisters
-- generic map( dataWidth => 16)
-- port map( Clk => CLK,
-- Ena => GLOBAL_EN,
-- Rst => RST,
-- Din => F2OPR1,
-- Dout => S3OPR1);
-- OPR2_Reg: entity work.PipelineRegisters
-- generic map( dataWidth => 16)
-- port map( Clk => CLK,
-- Ena => GLOBAL_EN,
-- Rst => RST,
-- Din => F2OPR2,
-- Dout => S3OPR2);
PC2_Reg: entity work.PipelineRegisters
generic map( dataWidth => 5)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => PC1,
Dout => PC2);
----> Stage Three <----
RA3ADR_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => RA2,
Dout => RA3);
RB3ADR_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => RB2,
Dout => RB3);
PC3_Reg: entity work.PipelineRegisters
generic map( dataWidth => 5)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => PC2,
Dout => PC3);
OP3_Reg: entity work.PipelineRegisters
generic map( datawidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => OP2,
Dout => OP3);
RA_DATA: entity work.PipelineRegisters
generic map( datawidth => 16)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => OPR1,
Dout => RA_IN);
RB_DATA: entity work.PipelineRegisters
generic map( datawidth => 16)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => OPRB,
Dout => RB_IN);
----> Stage Four <----
RA4ADR_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => RA3,
Dout => RA4);
RB4ADR_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => RB3,
Dout => RB4);
PC4_Reg: entity work.PipelineRegisters
generic map( dataWidth => 5)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => PC3,
Dout => PC4);
ALU_OUT_Reg: entity work.PipelineRegisters
generic map( dataWidth => 16)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => ALU_EX_MUX,
Dout => ALU_RESULT);
ALU_FLAGS_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => ALU_OUT_FLAGS,
Dout => ALU_FLAGS);
OP4_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => OP3,
Dout => OP4);
---->EXTERNAL_MEMORY_MUX<------
-------------------------------
with OP3 select
ALU_EX_MUX <= EX_DATA when "1011",
ALU_RESULT when others;
----> DC Stage 1 <----
ALU_OUT1_Reg: entity work.PipelineRegisters
generic map( dataWidth => 16)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => ALU_RESULT,
Dout => ALU_DC1);
RA_DC1_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => RA4,
Dout => RA_DC1);
RB_DC1_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => RB4,
Dout => RB_DC1);
----> DC Stage 2 <----
ALU_OUT2_Reg: entity work.PipelineRegisters
generic map( dataWidth => 16)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => ALU_DC1,
Dout => ALU_DC2);
RA_DC2_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => RA_DC1,
Dout => RA_DC2);
RB_DC2_Reg: entity work.PipelineRegisters
generic map( dataWidth => 4)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => RB_DC1,
Dout => RB_DC2);
-------- Immediate Select Mux --------
----------------------------------------
with IMSEL select OPRB <=
x"00" & IMM2 when '1',
OPR2 when OTHERS;
-------- Memory Entities --------
-----------------------------------
ProgCounter: entity work.programCounter
generic map(PCWIDTH => 5)
port map( CLK => CLK,
EN => PC_EN,
RST => RST,
INSADR => PC0);
RegisterBank_Unit: entity work.RegisterBank
port map( RAddr => RA1,
RBddr => RB1,
RWddr => RA4,
DATAIN => ALU_RESULT,
clk => CLK,
R => RD_EN,
W => WR_EN,
RAout => OPR1,
RBout => OPR2);
------------------------------------------
-- Project lab 2 --
------------------------------------------
Shadow_Reg: entity work.Shadow_Reg
port map( RAddr => RB1(3 downto 2),
--RBddr => RB1(1 downto 0),
--RWddr => ,
--DATAIN => RB1,
CLK => CLK,
RST => RST,
R => RD_EN,
W => WR_EN,
RAout => SHADOW_DAT);--Goes to "Shadow_Reg + IMM" MUX
-- RBout => SHADOW_DAT(1 downto 0));--Goes to "Shadow_Reg + IMM" MUX
Shadow_IMM_Add: entity work.Shadow_IMM_Add
port map( SHADOW => SHADOW_DAT,
IMM => IMM2(3 downto 0),
EX_ADDR => EX_ADDR);
EX_MEM_REG: entity work.PipelineRegisters
generic map( dataWidth => 14)
port map( Clk => CLK,
Ena => GLOBAL_EN,
Rst => RST,
Din => EX_ADDR,
Dout => EX_ADDR_OUT);
EXTERNAL_MEM: entity work.EXTERNAL_MEMORY
port map( CLKA => CLK,
ADDRA => EX_ADDR_OUT,
DINA => RA_OUT,
WEA(0) => EX_WR,
DOUTA => EX_DATA);
EX_MEM_CTL: entity work.EX_MEM_CTL
port map( CLK => CLK,
EN => GLOBAL_EN,
OP => OP3,
RD_EN => EX_RD,
WR_EN => EX_WR);
-------- Data Contention Handler --------
-------------------------------------------
with OP1_SEL select RA_OUT <=
ALU_RESULT when "01",
ALU_DC1 when "10",
ALU_DC2 when "11",
RA_IN when OTHERS;
with OP2_SEL select RB_OUT <=
ALU_RESUlt when "01",
ALU_DC1 when "10",
ALU_DC2 when "11",
RB_IN when OTHERS;
end Structural;
|
-- NEED RESULT: ARCH00615: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00615.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00615.P2: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00615.P3: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00615.P4: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00615.P5: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00615.P6: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00615.P7: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00615.P8: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00615.P9: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00615: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00615: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00615: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00615: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P9: Transport transactions completed entirely passed
-- NEED RESULT: P8: Transport transactions completed entirely passed
-- NEED RESULT: P7: Transport transactions completed entirely passed
-- NEED RESULT: P6: Transport transactions completed entirely passed
-- NEED RESULT: P5: Transport transactions completed entirely passed
-- NEED RESULT: P4: Transport transactions completed entirely passed
-- NEED RESULT: P3: Transport transactions completed entirely passed
-- NEED RESULT: P2: Transport transactions completed entirely passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00615
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.3 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00615(ARCH00615)
-- ENT00615_Test_Bench(ARCH00615_Test_Bench)
--
-- REVISION HISTORY:
--
-- 24-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00615 is
end ENT00615 ;
--
--
architecture ARCH00615 of ENT00615 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_boolean_vector_savt : chk_time_type := 0 ns ;
signal s_st_severity_level_vector_savt : chk_time_type := 0 ns ;
signal s_st_string_savt : chk_time_type := 0 ns ;
signal s_st_enum1_vector_savt : chk_time_type := 0 ns ;
signal s_st_integer_vector_savt : chk_time_type := 0 ns ;
signal s_st_time_vector_savt : chk_time_type := 0 ns ;
signal s_st_real_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec1_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_boolean_vector_cnt : chk_cnt_type := 0 ;
signal s_st_severity_level_vector_cnt : chk_cnt_type := 0 ;
signal s_st_string_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_integer_vector_cnt : chk_cnt_type := 0 ;
signal s_st_time_vector_cnt : chk_cnt_type := 0 ;
signal s_st_real_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_boolean_vector_select : select_type := 1 ;
signal st_severity_level_vector_select : select_type := 1 ;
signal st_string_select : select_type := 1 ;
signal st_enum1_vector_select : select_type := 1 ;
signal st_integer_vector_select : select_type := 1 ;
signal st_time_vector_select : select_type := 1 ;
signal st_real_vector_select : select_type := 1 ;
signal st_rec1_vector_select : select_type := 1 ;
signal st_arr2_vector_select : select_type := 1 ;
--
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
--
procedure P1
(signal s_st_boolean_vector : in st_boolean_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_boolean_vector_cnt is
when 0
=> null ;
-- s_st_boolean_vector(lowb to highb-1) <= transport
-- c_st_boolean_vector_2(lowb to highb-1) after 10 ns,
-- c_st_boolean_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_2(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_1(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_boolean_vector(lowb to highb-1) <= transport
-- c_st_boolean_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_boolean_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_boolean_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_boolean_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_2(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_boolean_vector(lowb to highb-1) <= transport
-- c_st_boolean_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_1(lowb to highb-1) and
(s_st_boolean_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_boolean_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_boolean_vector_cnt + 1 ;
--
end ;
--
procedure P2
(signal s_st_severity_level_vector : in st_severity_level_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_severity_level_vector_cnt is
when 0
=> null ;
-- s_st_severity_level_vector(lowb to highb-1) <= transport
-- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns,
-- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_2(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_1(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615.P2" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_severity_level_vector(lowb to highb-1) <= transport
-- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_severity_level_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_severity_level_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_2(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_severity_level_vector(lowb to highb-1) <= transport
-- c_st_severity_level_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_1(lowb to highb-1) and
(s_st_severity_level_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_severity_level_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_severity_level_vector_cnt + 1 ;
--
end ;
--
procedure P3
(signal s_st_string : in st_string ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_string_cnt is
when 0
=> null ;
-- s_st_string(highb-1 to highb-1) <= transport
-- c_st_string_2(highb-1 to highb-1) after 10 ns,
-- c_st_string_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_string(highb-1 to highb-1) =
c_st_string_2(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_string(highb-1 to highb-1) =
c_st_string_1(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615.P3" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_string(highb-1 to highb-1) <= transport
-- c_st_string_2(highb-1 to highb-1) after 10 ns ,
-- c_st_string_1(highb-1 to highb-1) after 20 ns ,
-- c_st_string_2(highb-1 to highb-1) after 30 ns ,
-- c_st_string_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_string(highb-1 to highb-1) =
c_st_string_2(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_string(highb-1 to highb-1) <= transport
-- c_st_string_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_string(highb-1 to highb-1) =
c_st_string_1(highb-1 to highb-1) and
(s_st_string_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_string_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_string_cnt + 1 ;
--
end ;
--
procedure P4
(signal s_st_enum1_vector : in st_enum1_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_enum1_vector_cnt is
when 0
=> null ;
-- s_st_enum1_vector(highb-1 to highb-1) <= transport
-- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_2(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_1(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615.P4" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_enum1_vector(highb-1 to highb-1) <= transport
-- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_2(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_enum1_vector(highb-1 to highb-1) <= transport
-- c_st_enum1_vector_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_1(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_enum1_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_enum1_vector_cnt + 1 ;
--
end ;
--
procedure P5
(signal s_st_integer_vector : in st_integer_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_integer_vector_cnt is
when 0
=> null ;
-- s_st_integer_vector(lowb to highb-1) <= transport
-- c_st_integer_vector_2(lowb to highb-1) after 10 ns,
-- c_st_integer_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_2(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_1(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615.P5" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_integer_vector(lowb to highb-1) <= transport
-- c_st_integer_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_integer_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_integer_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_integer_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_2(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_integer_vector(lowb to highb-1) <= transport
-- c_st_integer_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_1(lowb to highb-1) and
(s_st_integer_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_integer_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_integer_vector_cnt + 1 ;
--
end ;
--
procedure P6
(signal s_st_time_vector : in st_time_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_time_vector_cnt is
when 0
=> null ;
-- s_st_time_vector(lowb to highb-1) <= transport
-- c_st_time_vector_2(lowb to highb-1) after 10 ns,
-- c_st_time_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_2(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_1(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615.P6" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_time_vector(lowb to highb-1) <= transport
-- c_st_time_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_time_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_time_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_time_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_2(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_time_vector(lowb to highb-1) <= transport
-- c_st_time_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_1(lowb to highb-1) and
(s_st_time_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_time_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_time_vector_cnt + 1 ;
--
end ;
--
procedure P7
(signal s_st_real_vector : in st_real_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_real_vector_cnt is
when 0
=> null ;
-- s_st_real_vector(highb-1 to highb-1) <= transport
-- c_st_real_vector_2(highb-1 to highb-1) after 10 ns,
-- c_st_real_vector_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_2(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_1(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615.P7" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_real_vector(highb-1 to highb-1) <= transport
-- c_st_real_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_real_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_real_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_real_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_2(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_real_vector(highb-1 to highb-1) <= transport
-- c_st_real_vector_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_1(highb-1 to highb-1) and
(s_st_real_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_real_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_real_vector_cnt + 1 ;
--
end ;
--
procedure P8
(signal s_st_rec1_vector : in st_rec1_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_rec1_vector_cnt is
when 0
=> null ;
-- s_st_rec1_vector(highb-1 to highb-1) <= transport
-- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_2(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_1(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615.P8" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_rec1_vector(highb-1 to highb-1) <= transport
-- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_2(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_rec1_vector(highb-1 to highb-1) <= transport
-- c_st_rec1_vector_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_1(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_rec1_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_rec1_vector_cnt + 1 ;
--
end ;
--
procedure P9
(signal s_st_arr2_vector : in st_arr2_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_arr2_vector_cnt is
when 0
=> null ;
-- s_st_arr2_vector(lowb to highb-1) <= transport
-- c_st_arr2_vector_2(lowb to highb-1) after 10 ns,
-- c_st_arr2_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_2(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_1(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615.P9" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_arr2_vector(lowb to highb-1) <= transport
-- c_st_arr2_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_arr2_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_arr2_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_arr2_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_2(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_arr2_vector(lowb to highb-1) <= transport
-- c_st_arr2_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_1(lowb to highb-1) and
(s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00615" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00615" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_arr2_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_arr2_vector_cnt + 1 ;
--
end ;
--
begin
CHG1 :
P1(
s_st_boolean_vector ,
st_boolean_vector_select ,
s_st_boolean_vector_savt ,
chk_st_boolean_vector ,
s_st_boolean_vector_cnt ) ;
--
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_boolean_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_boolean_vector_select select
s_st_boolean_vector(lowb to highb-1) <= transport
c_st_boolean_vector_2(lowb to highb-1) after 10 ns,
c_st_boolean_vector_1(lowb to highb-1) after 20 ns
when 1,
--
c_st_boolean_vector_2(lowb to highb-1) after 10 ns ,
c_st_boolean_vector_1(lowb to highb-1) after 20 ns ,
c_st_boolean_vector_2(lowb to highb-1) after 30 ns ,
c_st_boolean_vector_1(lowb to highb-1) after 40 ns
when 2,
--
c_st_boolean_vector_1(lowb to highb-1) after 5 ns when 3 ;
--
CHG2 :
P2(
s_st_severity_level_vector ,
st_severity_level_vector_select ,
s_st_severity_level_vector_savt ,
chk_st_severity_level_vector ,
s_st_severity_level_vector_cnt ) ;
--
PGEN_CHKP_2 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions completed entirely",
chk_st_severity_level_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with st_severity_level_vector_select select
s_st_severity_level_vector(lowb to highb-1) <= transport
c_st_severity_level_vector_2(lowb to highb-1) after 10 ns,
c_st_severity_level_vector_1(lowb to highb-1) after 20 ns
when 1,
--
c_st_severity_level_vector_2(lowb to highb-1) after 10 ns ,
c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ,
c_st_severity_level_vector_2(lowb to highb-1) after 30 ns ,
c_st_severity_level_vector_1(lowb to highb-1) after 40 ns
when 2,
--
c_st_severity_level_vector_1(lowb to highb-1) after 5 ns when 3 ;
--
CHG3 :
P3(
s_st_string ,
st_string_select ,
s_st_string_savt ,
chk_st_string ,
s_st_string_cnt ) ;
--
PGEN_CHKP_3 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions completed entirely",
chk_st_string = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
with st_string_select select
s_st_string(highb-1 to highb-1) <= transport
c_st_string_2(highb-1 to highb-1) after 10 ns,
c_st_string_1(highb-1 to highb-1) after 20 ns
when 1,
--
c_st_string_2(highb-1 to highb-1) after 10 ns ,
c_st_string_1(highb-1 to highb-1) after 20 ns ,
c_st_string_2(highb-1 to highb-1) after 30 ns ,
c_st_string_1(highb-1 to highb-1) after 40 ns
when 2,
--
c_st_string_1(highb-1 to highb-1) after 5 ns when 3 ;
--
CHG4 :
P4(
s_st_enum1_vector ,
st_enum1_vector_select ,
s_st_enum1_vector_savt ,
chk_st_enum1_vector ,
s_st_enum1_vector_cnt ) ;
--
PGEN_CHKP_4 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Transport transactions completed entirely",
chk_st_enum1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
with st_enum1_vector_select select
s_st_enum1_vector(highb-1 to highb-1) <= transport
c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns,
c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns
when 1,
--
c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns
when 2,
--
c_st_enum1_vector_1(highb-1 to highb-1) after 5 ns when 3 ;
--
CHG5 :
P5(
s_st_integer_vector ,
st_integer_vector_select ,
s_st_integer_vector_savt ,
chk_st_integer_vector ,
s_st_integer_vector_cnt ) ;
--
PGEN_CHKP_5 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Transport transactions completed entirely",
chk_st_integer_vector = 4 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
with st_integer_vector_select select
s_st_integer_vector(lowb to highb-1) <= transport
c_st_integer_vector_2(lowb to highb-1) after 10 ns,
c_st_integer_vector_1(lowb to highb-1) after 20 ns
when 1,
--
c_st_integer_vector_2(lowb to highb-1) after 10 ns ,
c_st_integer_vector_1(lowb to highb-1) after 20 ns ,
c_st_integer_vector_2(lowb to highb-1) after 30 ns ,
c_st_integer_vector_1(lowb to highb-1) after 40 ns
when 2,
--
c_st_integer_vector_1(lowb to highb-1) after 5 ns when 3 ;
--
CHG6 :
P6(
s_st_time_vector ,
st_time_vector_select ,
s_st_time_vector_savt ,
chk_st_time_vector ,
s_st_time_vector_cnt ) ;
--
PGEN_CHKP_6 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Transport transactions completed entirely",
chk_st_time_vector = 4 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
with st_time_vector_select select
s_st_time_vector(lowb to highb-1) <= transport
c_st_time_vector_2(lowb to highb-1) after 10 ns,
c_st_time_vector_1(lowb to highb-1) after 20 ns
when 1,
--
c_st_time_vector_2(lowb to highb-1) after 10 ns ,
c_st_time_vector_1(lowb to highb-1) after 20 ns ,
c_st_time_vector_2(lowb to highb-1) after 30 ns ,
c_st_time_vector_1(lowb to highb-1) after 40 ns
when 2,
--
c_st_time_vector_1(lowb to highb-1) after 5 ns when 3 ;
--
CHG7 :
P7(
s_st_real_vector ,
st_real_vector_select ,
s_st_real_vector_savt ,
chk_st_real_vector ,
s_st_real_vector_cnt ) ;
--
PGEN_CHKP_7 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Transport transactions completed entirely",
chk_st_real_vector = 4 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
with st_real_vector_select select
s_st_real_vector(highb-1 to highb-1) <= transport
c_st_real_vector_2(highb-1 to highb-1) after 10 ns,
c_st_real_vector_1(highb-1 to highb-1) after 20 ns
when 1,
--
c_st_real_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_real_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_real_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_real_vector_1(highb-1 to highb-1) after 40 ns
when 2,
--
c_st_real_vector_1(highb-1 to highb-1) after 5 ns when 3 ;
--
CHG8 :
P8(
s_st_rec1_vector ,
st_rec1_vector_select ,
s_st_rec1_vector_savt ,
chk_st_rec1_vector ,
s_st_rec1_vector_cnt ) ;
--
PGEN_CHKP_8 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Transport transactions completed entirely",
chk_st_rec1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
with st_rec1_vector_select select
s_st_rec1_vector(highb-1 to highb-1) <= transport
c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns,
c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns
when 1,
--
c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns
when 2,
--
c_st_rec1_vector_1(highb-1 to highb-1) after 5 ns when 3 ;
--
CHG9 :
P9(
s_st_arr2_vector ,
st_arr2_vector_select ,
s_st_arr2_vector_savt ,
chk_st_arr2_vector ,
s_st_arr2_vector_cnt ) ;
--
PGEN_CHKP_9 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Transport transactions completed entirely",
chk_st_arr2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
with st_arr2_vector_select select
s_st_arr2_vector(lowb to highb-1) <= transport
c_st_arr2_vector_2(lowb to highb-1) after 10 ns,
c_st_arr2_vector_1(lowb to highb-1) after 20 ns
when 1,
--
c_st_arr2_vector_2(lowb to highb-1) after 10 ns ,
c_st_arr2_vector_1(lowb to highb-1) after 20 ns ,
c_st_arr2_vector_2(lowb to highb-1) after 30 ns ,
c_st_arr2_vector_1(lowb to highb-1) after 40 ns
when 2,
--
c_st_arr2_vector_1(lowb to highb-1) after 5 ns when 3 ;
--
end ARCH00615 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00615_Test_Bench is
end ENT00615_Test_Bench ;
--
--
architecture ARCH00615_Test_Bench of ENT00615_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00615 ( ARCH00615 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00615_Test_Bench ;
|
-- NEED RESULT: ARCH00408.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00408.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00408.P3: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00408: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00408: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00408: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00408: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00408: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00408: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00408: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00408: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00408: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00408: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00408: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00408: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P3: Inertial transactions completed entirely passed
-- NEED RESULT: P2: Inertial transactions completed entirely passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00408
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00408(ARCH00408)
-- ENT00408_Test_Bench(ARCH00408_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00408 is
port (
s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
--
end ENT00408 ;
--
--
architecture ARCH00408 of ENT00408 is
subtype chk_time_type is Time ;
signal s_st_rec1_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec2_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec3_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec2_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec3_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_rec1_vector_select : select_type := 1 ;
signal st_rec2_vector_select : select_type := 1 ;
signal st_rec3_vector_select : select_type := 1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_rec1_vector_cnt is
when 0
=> null ;
-- s_st_rec1_vector(lowb).f2 <=
-- c_st_rec1_vector_2(lowb).f2 after 10 ns,
-- c_st_rec1_vector_1(lowb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(lowb).f2 and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(lowb).f2 and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00408.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_vector_select <= transport 2 ;
-- s_st_rec1_vector(lowb).f2 <=
-- c_st_rec1_vector_2(lowb).f2 after 10 ns ,
-- c_st_rec1_vector_1(lowb).f2 after 20 ns ,
-- c_st_rec1_vector_2(lowb).f2 after 30 ns ,
-- c_st_rec1_vector_1(lowb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(lowb).f2 and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec1_vector_select <= transport 3 ;
-- s_st_rec1_vector(lowb).f2 <=
-- c_st_rec1_vector_1(lowb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(lowb).f2 and
(s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00408" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 4 ;
-- s_st_rec1_vector(lowb).f2 <=
-- c_st_rec1_vector_1(lowb).f2 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(lowb).f2 and
(s_st_rec1_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00408" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 5 ;
-- s_st_rec1_vector(lowb).f2 <=
-- c_st_rec1_vector_2(lowb).f2 after 10 ns ,
-- c_st_rec1_vector_1(lowb).f2 after 20 ns ,
-- c_st_rec1_vector_2(lowb).f2 after 30 ns ,
-- c_st_rec1_vector_1(lowb).f2 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(lowb).f2 and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00408" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec1_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec1_vector(lowb).f2 <=
-- c_st_rec1_vector_1(lowb).f2 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(lowb).f2 and
(s_st_rec1_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(lowb).f2 and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00408" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00408" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec1_vector_savt <= transport Std.Standard.Now ;
chk_st_rec1_vector <= transport s_st_rec1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ;
wait until (not s_st_rec1_vector(lowb).f2'Quiet) and
(s_st_rec1_vector_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_rec1_vector(lowb).f2 <=
c_st_rec1_vector_2(lowb).f2 after 10 ns,
c_st_rec1_vector_1(lowb).f2 after 20 ns
when st_rec1_vector_select = 1 else
--
c_st_rec1_vector_2(lowb).f2 after 10 ns ,
c_st_rec1_vector_1(lowb).f2 after 20 ns ,
c_st_rec1_vector_2(lowb).f2 after 30 ns ,
c_st_rec1_vector_1(lowb).f2 after 40 ns
when st_rec1_vector_select = 2 else
--
c_st_rec1_vector_1(lowb).f2 after 5 ns
when st_rec1_vector_select = 3 else
--
c_st_rec1_vector_1(lowb).f2 after 100 ns
when st_rec1_vector_select = 4 else
--
c_st_rec1_vector_2(lowb).f2 after 10 ns ,
c_st_rec1_vector_1(lowb).f2 after 20 ns ,
c_st_rec1_vector_2(lowb).f2 after 30 ns ,
c_st_rec1_vector_1(lowb).f2 after 40 ns
when st_rec1_vector_select = 5 else
--
-- Last transaction above is marked
c_st_rec1_vector_1(lowb).f2 after 40 ns ;
--
CHG2 :
process
variable correct : boolean ;
begin
case s_st_rec2_vector_cnt is
when 0
=> null ;
-- s_st_rec2_vector(lowb).f2 <=
-- c_st_rec2_vector_2(lowb).f2 after 10 ns,
-- c_st_rec2_vector_1(lowb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(lowb).f2 and
(s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(lowb).f2 and
(s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00408.P2" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec2_vector_select <= transport 2 ;
-- s_st_rec2_vector(lowb).f2 <=
-- c_st_rec2_vector_2(lowb).f2 after 10 ns ,
-- c_st_rec2_vector_1(lowb).f2 after 20 ns ,
-- c_st_rec2_vector_2(lowb).f2 after 30 ns ,
-- c_st_rec2_vector_1(lowb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(lowb).f2 and
(s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec2_vector_select <= transport 3 ;
-- s_st_rec2_vector(lowb).f2 <=
-- c_st_rec2_vector_1(lowb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(lowb).f2 and
(s_st_rec2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00408" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_vector_select <= transport 4 ;
-- s_st_rec2_vector(lowb).f2 <=
-- c_st_rec2_vector_1(lowb).f2 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(lowb).f2 and
(s_st_rec2_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00408" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec2_vector_select <= transport 5 ;
-- s_st_rec2_vector(lowb).f2 <=
-- c_st_rec2_vector_2(lowb).f2 after 10 ns ,
-- c_st_rec2_vector_1(lowb).f2 after 20 ns ,
-- c_st_rec2_vector_2(lowb).f2 after 30 ns ,
-- c_st_rec2_vector_1(lowb).f2 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(lowb).f2 and
(s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00408" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec2_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec2_vector(lowb).f2 <=
-- c_st_rec2_vector_1(lowb).f2 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(lowb).f2 and
(s_st_rec2_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(lowb).f2 and
(s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00408" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00408" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec2_vector_savt <= transport Std.Standard.Now ;
chk_st_rec2_vector <= transport s_st_rec2_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec2_vector_cnt <= transport s_st_rec2_vector_cnt + 1 ;
wait until (not s_st_rec2_vector(lowb).f2'Quiet) and
(s_st_rec2_vector_savt /= Std.Standard.Now) ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions completed entirely",
chk_st_rec2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
s_st_rec2_vector(lowb).f2 <=
c_st_rec2_vector_2(lowb).f2 after 10 ns,
c_st_rec2_vector_1(lowb).f2 after 20 ns
when st_rec2_vector_select = 1 else
--
c_st_rec2_vector_2(lowb).f2 after 10 ns ,
c_st_rec2_vector_1(lowb).f2 after 20 ns ,
c_st_rec2_vector_2(lowb).f2 after 30 ns ,
c_st_rec2_vector_1(lowb).f2 after 40 ns
when st_rec2_vector_select = 2 else
--
c_st_rec2_vector_1(lowb).f2 after 5 ns
when st_rec2_vector_select = 3 else
--
c_st_rec2_vector_1(lowb).f2 after 100 ns
when st_rec2_vector_select = 4 else
--
c_st_rec2_vector_2(lowb).f2 after 10 ns ,
c_st_rec2_vector_1(lowb).f2 after 20 ns ,
c_st_rec2_vector_2(lowb).f2 after 30 ns ,
c_st_rec2_vector_1(lowb).f2 after 40 ns
when st_rec2_vector_select = 5 else
--
-- Last transaction above is marked
c_st_rec2_vector_1(lowb).f2 after 40 ns ;
--
CHG3 :
process
variable correct : boolean ;
begin
case s_st_rec3_vector_cnt is
when 0
=> null ;
-- s_st_rec3_vector(highb).f3 <=
-- c_st_rec3_vector_2(highb).f3 after 10 ns,
-- c_st_rec3_vector_1(highb).f3 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_2(highb).f3 and
(s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_1(highb).f3 and
(s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00408.P3" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_vector_select <= transport 2 ;
-- s_st_rec3_vector(highb).f3 <=
-- c_st_rec3_vector_2(highb).f3 after 10 ns ,
-- c_st_rec3_vector_1(highb).f3 after 20 ns ,
-- c_st_rec3_vector_2(highb).f3 after 30 ns ,
-- c_st_rec3_vector_1(highb).f3 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_2(highb).f3 and
(s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec3_vector_select <= transport 3 ;
-- s_st_rec3_vector(highb).f3 <=
-- c_st_rec3_vector_1(highb).f3 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_1(highb).f3 and
(s_st_rec3_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00408" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_vector_select <= transport 4 ;
-- s_st_rec3_vector(highb).f3 <=
-- c_st_rec3_vector_1(highb).f3 after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_1(highb).f3 and
(s_st_rec3_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00408" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_rec3_vector_select <= transport 5 ;
-- s_st_rec3_vector(highb).f3 <=
-- c_st_rec3_vector_2(highb).f3 after 10 ns ,
-- c_st_rec3_vector_1(highb).f3 after 20 ns ,
-- c_st_rec3_vector_2(highb).f3 after 30 ns ,
-- c_st_rec3_vector_1(highb).f3 after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_2(highb).f3 and
(s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00408" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_rec3_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_rec3_vector(highb).f3 <=
-- c_st_rec3_vector_1(highb).f3 after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_1(highb).f3 and
(s_st_rec3_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_1(highb).f3 and
(s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00408" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00408" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_rec3_vector_savt <= transport Std.Standard.Now ;
chk_st_rec3_vector <= transport s_st_rec3_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_vector_cnt <= transport s_st_rec3_vector_cnt + 1 ;
wait until (not s_st_rec3_vector(highb).f3'Quiet) and
(s_st_rec3_vector_savt /= Std.Standard.Now) ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions completed entirely",
chk_st_rec3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
s_st_rec3_vector(highb).f3 <=
c_st_rec3_vector_2(highb).f3 after 10 ns,
c_st_rec3_vector_1(highb).f3 after 20 ns
when st_rec3_vector_select = 1 else
--
c_st_rec3_vector_2(highb).f3 after 10 ns ,
c_st_rec3_vector_1(highb).f3 after 20 ns ,
c_st_rec3_vector_2(highb).f3 after 30 ns ,
c_st_rec3_vector_1(highb).f3 after 40 ns
when st_rec3_vector_select = 2 else
--
c_st_rec3_vector_1(highb).f3 after 5 ns
when st_rec3_vector_select = 3 else
--
c_st_rec3_vector_1(highb).f3 after 100 ns
when st_rec3_vector_select = 4 else
--
c_st_rec3_vector_2(highb).f3 after 10 ns ,
c_st_rec3_vector_1(highb).f3 after 20 ns ,
c_st_rec3_vector_2(highb).f3 after 30 ns ,
c_st_rec3_vector_1(highb).f3 after 40 ns
when st_rec3_vector_select = 5 else
--
-- Last transaction above is marked
c_st_rec3_vector_1(highb).f3 after 40 ns ;
--
end ARCH00408 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00408_Test_Bench is
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
--
end ENT00408_Test_Bench ;
--
--
architecture ARCH00408_Test_Bench of ENT00408_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00408 ( ARCH00408 ) ;
begin
CIS1 : UUT
port map (
s_st_rec1_vector
, s_st_rec2_vector
, s_st_rec3_vector
)
;
end block L1 ;
end ARCH00408_Test_Bench ;
|
-- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: tetrisIO.vhd
-- // Date: 12/9/2004
-- // Description: Main Tetris Program
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TetrisIO is
port ( NESData : in std_logic;
mclk : in std_logic;
NESClock : out std_logic;
NESLatch: out std_logic;
RGB : out std_logic_vector(2 downto 0);
VSync : out std_logic;
HSync : out std_logic;
LDG : out std_logic;
LED : out std_logic;
LD : out std_logic_vector(1 to 8);
bn : in std_logic;
BTN4 : in std_logic;
SW : in std_logic_vector(7 downto 0);
A : out std_logic_vector(1 to 4);
AtoG : out std_logic_vector(6 downto 0));
end TetrisIO;
architecture Behavioral of TetrisIO is
signal clr : std_logic;
signal tClk190hz, tClk25mhz, tClk48khz : std_logic;
signal Buttons : std_logic_vector(7 downto 0);
signal tGPUBlockAddr : std_logic_vector(4 downto 0); --Holds static blocks
signal tGPUBlockData : std_logic_vector(15 downto 0);
signal tDiag : std_logic;
-- // intermediate signals connecting into the x position register
signal t_xpos_in : std_logic_vector(3 downto 0) := "0000";
signal t_xpos_out : std_logic_vector(3 downto 0) := "0000";
signal t_xpos_load : std_logic := '0';
-- // intermediate signals connecting into the y position register
signal t_ypos_in : std_logic_vector(4 downto 0) := "00000";
signal t_ypos_out : std_logic_vector(4 downto 0) := "00000";
signal t_ypos_load : std_logic := '0';
-- // intermediate signals connecting into the block shape register
signal t_block_in : std_logic_vector(15 downto 0) := X"0000";
signal t_block_out : std_logic_vector(15 downto 0) := X"0000";
signal t_block_load : std_logic := '0';
Signal tT : std_logic_vector(15 downto 0);
signal tDigLoad : std_logic;
Signal tAddr : std_logic_vector(15 downto 0);
Signal tM : std_logic_vector(15 downto 0);
Signal tLinesDestroyed : std_logic_vector(2 downto 0);
signal tClearLines : std_logic := '0';
Signal tClr : std_logic := '0';
signal clrflag : std_logic := '0';
-- // '1' denotes "PAUSED" status
signal t_paused : std_logic := '0';
-- // Intermediate signals for tetris_control
Signal t_row_no : std_logic_vector(4 downto 0);
Signal t_row_val : std_logic_vector(15 downto 0);
Signal t_row_val2 : std_logic_vector(15 downto 0);
Signal t_row_load : std_logic;
signal tRandom : std_logic_vector(2 downto 0) := "000";
component tetris_control is
port(
clk: in STD_LOGIC;
clr: in STD_LOGIC;
i_buttons: in STD_LOGIC_VECTOR(7 downto 0); -- controller buttons vector
i_block_code: in STD_LOGIC_VECTOR(2 downto 0); -- 0..8, chooses next block
o_load_xpos: out STD_LOGIC; -- '1' when xreg should be loaded with xpos
o_xpos_val: out STD_LOGIC_VECTOR(3 downto 0); -- 0..9 < 16
o_load_ypos: out STD_LOGIC; -- '1' when yreg should be loaded with ypos
o_ypos_val: out STD_LOGIC_VECTOR(4 downto 0); -- 0..19 < 32
o_load_block: out STD_LOGIC; -- '1' when blockreg should be loaded with shape
o_block_val: out STD_LOGIC_VECTOR(15 downto 0); -- 4x4 block, '1' = SOLID
o_paused: out STD_LOGIC; -- '1' when the game is paused
-- // for fetching rows into and out of tetris_control / ramtable
i_row_val: in STD_LOGIC_VECTOR(15 downto 0);
o_row_fetch: out STD_LOGIC; -- '1' when i_row_val should be loaded for i_row_no
o_row_load: out STD_LOGIC; -- '1' when o_row_val should br put for o_row_no
o_row_no: out STD_LOGIC_VECTOR(4 downto 0); -- 0..19 < 32
o_row_val: out STD_LOGIC_VECTOR(15 downto 0);
o_Lines_Destroyed : out std_logic_vector(2 downto 0);
i_clear_Lines : in std_logic
);
end component;
component reg is
generic(width: positive);
port
(
d: in STD_LOGIC_VECTOR (width-1 downto 0);
load: in STD_LOGIC;
clr: in STD_LOGIC;
clk: in STD_LOGIC;
q: out STD_LOGIC_VECTOR (width-1 downto 0)
);
end component;
component dpram32x16 IS
port
(
A: IN std_logic_VECTOR(4 downto 0);
CLK: IN std_logic;
D: IN std_logic_VECTOR(15 downto 0);
WE: IN std_logic;
DPRA: IN std_logic_VECTOR(4 downto 0);
DPO: OUT std_logic_VECTOR(15 downto 0);
SPO: OUT std_logic_VECTOR(15 downto 0)
);
end component;
component NES is
Port ( DataI : in std_logic;
clkO : out std_logic;
clkI : in std_logic; --50 mhz
waitCLKI : std_logic; --97.6 Khz
clr : in std_logic;
latchO : out std_logic;
Buttons : out std_logic_vector(7 downto 0));
end component;
component ClockDiv is
Port ( iMclk : in std_logic;
oClk190Hz : out std_logic;
oClk48Khz : out std_logic;
oClk25Mhz : out std_logic);
end component;
component GPU is
port(
iClk25MHZ : in std_logic;
iPaused : in std_logic;
iScore : std_logic_vector(15 downto 0);
oBlockAddr : out std_logic_vector(4 downto 0); --Holds static blocks
iBlockData : in std_logic_vector(15 downto 0); --Holds each row
iBlockY : in std_logic_vector(4 downto 0); --top edge of moving block
iBlockX : in std_logic_vector(3 downto 0); --left edge of moving block
iBlockReg : in std_logic_vector(15 downto 0); --encoded dynamic block memory
iClr : in std_logic;
iDiag : in std_logic;
oRGB : out std_logic_vector(2 downto 0);
oVSync : out std_logic;
oHSync : out std_logic);
end component;
component whypcore is
port (
p : out STD_LOGIC_VECTOR(15 downto 0);
destro : in STD_LOGIC_VECTOR(2 downto 0);
m : in STD_LOGIC_VECTOR(15 downto 0);
SW : in std_logic_vector(7 downto 0);
BTN4 : in std_logic;
clk : in STD_LOGIC;
clr : in STD_LOGIC;
digload : out STD_LOGIC;
ldload: out STD_LOGIC;
t : out STD_LOGIC_VECTOR(15 downto 0);
o_Clear_Lines : out std_logic
);
end component;
component Promscore is
port (
addr : in STD_LOGIC_VECTOR (15 downto 0);
M : out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
component dig7seg is
Port ( T: in std_logic_vector(15 downto 0);
digload: in std_logic;
clr : in std_logic;
clk : in std_logic; --25 Mhz
cclk : in std_logic; --190 Hz
AtoG : out std_logic_vector(6 downto 0);
A : out std_logic_vector(1 to 4));
end component;
component IBUFG
port (
I : in STD_LOGIC;
O : out std_logic
);
end component;
component random is
Port ( iClk : in std_logic;
iClr : in std_logic;
iM : in std_logic_vector(15 downto 0);
iP : in std_logic_vector(15 downto 0);
oRandom : out std_logic_vector(2 downto 0);
iT : in std_logic_vector(15 downto 0);
iX : in std_logic_vector(3 downto 0);
iY : in std_logic_vector(4 downto 0));
end component;
begin
RND00 : random port map(
iClk => tclk25Mhz,
iClr => clr,
iP => tAddr,
iM => tM,
oRandom => tRandom,
iX => t_xpos_in,
iY => t_ypos_in,
iT => tT);
GPU00 : GPU port map(
iClk25Mhz => tclk25Mhz,
iPaused => t_paused,
iScore => X"0000",
oBlockAddr => tGPUBlockAddr,
iBlockData => tGPUBlockData,
iBlockX => t_xpos_out,
iBlockY => t_ypos_out,
iBlockReg => t_block_out,
iClr => clr,
iDiag => tDiag,
oRGB => RGB,
oVSync => VSync,
oHSync => HSync);
CLK00 : ClockDiv port map(iMclk => mclk, oClk190Hz => tClk190hz, oClk48khz => tClk48khz, oClk25mhz => tClk25mhz);
NES00 : NES port map(DataI => NESData, clkO => NESClock, clkI => tclk25Mhz, WaitclkI => tClk48Khz, clr => clr, latchO => NESLatch, buttons => Buttons);
DEB00 : IBUFG port map(I => BN, O => tClr);
RegXPos : Reg generic map(width => 4) port map(clk => tclk25Mhz, clr => clr, d => t_xpos_in, q => t_xpos_out, load => t_xpos_load);
RegYPos : Reg generic map(width => 16) port map(clk => tclk25Mhz, clr => clr, d => t_block_in, q => t_block_out, load => t_block_load);
RegBlk: Reg generic map(width => 5) port map(clk => tclk25Mhz, clr => clr, d => t_ypos_in, q => t_ypos_out, load => t_ypos_load);
BlockRAM : dpram32x16 port map(A => t_row_no, clk => tclk25Mhz, d => t_row_val, we => t_row_load, DPRA=> tGPUBlockAddr, SPO => t_row_val2, DPO => tGPUBlockData);
tc_00: tetris_control port map(
clk => tclk25Mhz,
clr => clr,
i_buttons => Buttons,
i_block_code => tRandom,
o_load_xpos => t_xpos_load,
o_xpos_val => t_xpos_in,
o_load_ypos => t_ypos_load,
o_ypos_val => t_ypos_in,
o_load_block => t_block_load,
o_block_val => t_block_in,
o_paused => t_paused,
i_row_val => t_row_val2,
--o_row_fetch
o_row_load => t_row_load,
o_row_no => t_row_no,
o_row_val => t_row_val,
o_Lines_Destroyed => tLinesDestroyed,
i_clear_Lines => tClearLines);
d7s00: dig7seg port map(
T => tT,
digload => tDigLoad,
clr => clr,
clk => tclk25Mhz,
cclk => tclk190hz,
AtoG => AtoG,
A => A);
PRM00: Promscore port map(
addr => tAddr,
M => tM);
WPC00 : whypcore port map(
p => tAddr,
M => tM,
digload => tDigLoad,
T => tT,
clk => tclk25Mhz,
clr => clr,
Destro => tLinesDestroyed,
BTN4 => BTN4,
SW => SW,
o_Clear_Lines => tClearLines);
Reset : process(tClk190hz, tClr, clr, Buttons)
begin
if tClk190hz'event and tClk190hz = '1' then
if (((Buttons(7) and Buttons(6) and Buttons(5) and Buttons(4)) or tClr) and (not clrflag)) = '1' then
clr <= '1';
clrflag <= '1';
else
clr <= '0';
clrflag <= '0';
end if;
end if;
end process;
tDiag <= SW(7);
LD <= Buttons;
LED <= clr;
LDG <= '1';
end Behavioral; |
---------------------------------------------------------------------
-- TITLE: DDR SDRAM Interface
-- AUTHORS: Steve Rhoads ([email protected])
-- DATE CREATED: 7/26/07
-- FILENAME: ddr_ctrl.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Double Data Rate Sychronous Dynamic Random Access Memory Interface
--
-- For: 64 MB = MT46V32M16, 512Mb, 32Mb x 16 (default)
-- ROW = address(25 downto 13)
-- BANK = address(12 downto 11)
-- COL = address(10 downto 2)
--
-- Changes are needed for 32 MB = MT46V16M16, 256Mb, 16Mb x 16
-- ROW = address(24 downto 12) -- 25 ignored
-- BANK = address(11 downto 10)
-- COL = address(9 downto 2) --also change ddr_init.c
--
-- Changes are needed for 128 MB = MT46V64M16, 1Gb, 64Mb x 16
-- ROW = address(26 downto 14)
-- BANK = address(13 downto 12)
-- COL = address(11 downto 2) --also change ddr_init.c
--
-- Requires CAS latency=2; burst size=2.
-- Requires clk changes on rising_edge(clk_2x).
-- Requires active, address, byte_we, data_w stable throughout transfer.
-- DLL mode requires 77MHz. Non-DLL mode runs at 25 MHz.
--
-- cycle_cnt 777777770000111122223333444455556666777777777777
-- clk_2x --__--__--__--__--__--__--__--__--__--__--__--__
-- clk ____----____----____----____----____----____----
-- SD_CLK ----____----____----____----____----____----____
-- cmd ____write+++WRITE+++____________________________
-- SD_DQ ~~~~~~~~~~~~~~uuuullllUUUULLLL~~~~~~~~~~~~~~~~~~
--
-- cycle_cnt 777777770000111122223333444455556666777777777777
-- clk_2x --__--__--__--__--__--__--__--__--__--__--__--__
-- clk ____----____----____----____----____----____----
-- SD_CLK ----____----____----____----____----____----____
-- cmd ____read++++________________________read++++____
-- SD_DQ ~~~~~~~~~~~~~~~~~~~~~~~~uuuullll~~~~~~~~~~~~~~~~
-- SD_DQnDLL ~~~~~~~~~~~~~~~~~~~~~~~~~~uuuullll~~~~~~~~~~~~~~
-- pause ____------------------------________------------
--
-- Must run DdrInit() to initialize DDR chip.
-- Read Micron DDR SDRAM MT46V32M16 data sheet for more details.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.mlite_pack.all;
entity ddr_ctrl is
port(
clk : in std_logic;
clk_2x : in std_logic;
reset_in : in std_logic;
address : in std_logic_vector(25 downto 2);
byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
no_start : in std_logic;
no_stop : in std_logic;
pause : out std_logic;
SD_CK_P : out std_logic; --clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic); --low_data_strobe
end; --entity ddr
architecture logic of ddr_ctrl is
--Commands for bits RAS & CAS & WE
subtype command_type is std_logic_vector(2 downto 0);
constant COMMAND_LMR : command_type := "000";
constant COMMAND_AUTO_REFRESH : command_type := "001";
constant COMMAND_PRECHARGE : command_type := "010";
constant COMMAND_ACTIVE : command_type := "011";
constant COMMAND_WRITE : command_type := "100";
constant COMMAND_READ : command_type := "101";
constant COMMAND_TERMINATE : command_type := "110";
constant COMMAND_NOP : command_type := "111";
subtype ddr_state_type is std_logic_vector(3 downto 0);
constant STATE_POWER_ON : ddr_state_type := "0000";
constant STATE_IDLE : ddr_state_type := "0001";
constant STATE_ROW_ACTIVATE : ddr_state_type := "0010";
constant STATE_ROW_ACTIVE : ddr_state_type := "0011";
constant STATE_READ : ddr_state_type := "0100";
constant STATE_READ2 : ddr_state_type := "0101";
constant STATE_READ3 : ddr_state_type := "0110";
constant STATE_PRECHARGE : ddr_state_type := "0111";
constant STATE_PRECHARGE2 : ddr_state_type := "1000";
signal state_prev : ddr_state_type;
signal refresh_cnt : std_logic_vector(7 downto 0);
signal data_write2 : std_logic_vector(47 downto 0); --write pipeline
signal byte_we_reg2 : std_logic_vector(5 downto 0); --write pipeline
signal write_active : std_logic;
signal write_prev : std_logic;
signal cycle_count : std_logic_vector(2 downto 0); --half clocks since op
signal cycle_count2 : std_logic_vector(2 downto 0); --delayed by quarter clock
signal cke_reg : std_logic;
signal clk_p : std_logic;
signal bank_open : std_logic_vector(3 downto 0);
signal data_read : std_logic_vector(31 downto 0);
begin
ddr_proc: process(clk, clk_p, clk_2x, reset_in,
address, byte_we, data_w, active, no_start, no_stop,
SD_DQ, SD_UDQS, SD_LDQS,
state_prev, refresh_cnt,
byte_we_reg2, data_write2,
cycle_count, cycle_count2, write_prev,
write_active, cke_reg, bank_open,
data_read)
type address_array_type is array(3 downto 0) of std_logic_vector(12 downto 0);
variable address_row : address_array_type;
variable command : std_logic_vector(2 downto 0); --RAS & CAS & WE
variable bank_index : integer;
variable state_current : ddr_state_type;
begin
command := COMMAND_NOP;
bank_index := conv_integer(address(12 downto 11));
state_current := state_prev;
--DDR state machine to determine state_current and command
case state_prev is
when STATE_POWER_ON =>
if active = '1' then
if byte_we /= "0000" then
command := address(6 downto 4); --LMR="000"
else
state_current := STATE_IDLE; --read transistions to STATE_IDLE
end if;
end if;
when STATE_IDLE =>
if refresh_cnt(7) = '1' then
state_current := STATE_PRECHARGE;
command := COMMAND_AUTO_REFRESH;
elsif active = '1' and no_start = '0' then
state_current := STATE_ROW_ACTIVATE;
command := COMMAND_ACTIVE;
end if;
when STATE_ROW_ACTIVATE =>
state_current := STATE_ROW_ACTIVE;
when STATE_ROW_ACTIVE =>
if refresh_cnt(7) = '1' then
if write_prev = '0' then
state_current := STATE_PRECHARGE;
command := COMMAND_PRECHARGE;
end if;
elsif active = '1' and no_start = '0' then
if bank_open(bank_index) = '0' then
state_current := STATE_ROW_ACTIVATE;
command := COMMAND_ACTIVE;
elsif address(25 downto 13) /= address_row(bank_index) then
if write_prev = '0' then
state_current := STATE_PRECHARGE;
command := COMMAND_PRECHARGE;
end if;
else
if byte_we /= "0000" then
command := COMMAND_WRITE;
elsif write_prev = '0' then
state_current := STATE_READ;
command := COMMAND_READ;
end if;
end if;
end if;
when STATE_READ =>
state_current := STATE_READ2;
when STATE_READ2 =>
state_current := STATE_READ3;
when STATE_READ3 =>
if no_stop = '0' then
state_current := STATE_ROW_ACTIVE;
end if;
when STATE_PRECHARGE =>
state_current := STATE_PRECHARGE2;
when STATE_PRECHARGE2 =>
state_current := STATE_IDLE;
when others =>
state_current := STATE_IDLE;
end case; --state_prev
--rising_edge(clk) domain registers
if reset_in = '1' then
state_prev <= STATE_POWER_ON;
cke_reg <= '0';
refresh_cnt <= ZERO(7 downto 0);
write_prev <= '0';
write_active <= '0';
bank_open <= "0000";
elsif rising_edge(clk) then
if active = '1' then
cke_reg <= '1';
end if;
if command = COMMAND_WRITE then
write_prev <= '1';
elsif cycle_count2(2 downto 1) = "11" then
write_prev <= '0';
end if;
if command = COMMAND_WRITE then
write_active <= '1';
elsif cycle_count2 = "100" then
write_active <= '0';
end if;
if command = COMMAND_ACTIVE then
bank_open(bank_index) <= '1';
address_row(bank_index) := address(25 downto 13);
end if;
if command = COMMAND_PRECHARGE then
bank_open <= "0000";
end if;
if command = COMMAND_AUTO_REFRESH then
refresh_cnt <= ZERO(7 downto 0);
else
refresh_cnt <= refresh_cnt + 1;
end if;
state_prev <= state_current;
end if; --rising_edge(clk)
--rising_edge(clk_2x) domain registers
if reset_in = '1' then
cycle_count <= "000";
elsif rising_edge(clk_2x) then
--Cycle_count
if (command = COMMAND_READ or command = COMMAND_WRITE) and clk = '1' then
cycle_count <= "000";
elsif cycle_count /= "111" then
cycle_count <= cycle_count + 1;
end if;
clk_p <= clk; --earlier version of not clk
--Read data (DLL disabled)
if cycle_count = "100" then
data_read(31 downto 16) <= SD_DQ; --data
elsif cycle_count = "101" then
data_read(15 downto 0) <= SD_DQ;
end if;
end if;
--falling_edge(clk_2x) domain registers
if reset_in = '1' then
cycle_count2 <= "000";
data_write2 <= ZERO(15 downto 0) & ZERO;
byte_we_reg2 <= "000000";
elsif falling_edge(clk_2x) then
cycle_count2 <= cycle_count;
--Write pipeline
if clk = '0' then
data_write2 <= data_write2(31 downto 16) & data_w;
byte_we_reg2 <= byte_we_reg2(3 downto 2) & byte_we;
else
data_write2(47 downto 16) <= data_write2(31 downto 0);
byte_we_reg2(5 downto 2) <= byte_we_reg2(3 downto 0);
end if;
--Read data (DLL enabled)
--if cycle_count = "100" then
-- data_read(31 downto 16) <= SD_DQ; --data
--elsif cycle_count = "101" then
-- data_read(15 downto 0) <= SD_DQ;
--end if;
end if;
data_r <= data_read;
--Write data
if write_active = '1' then
SD_UDQS <= clk_p; --upper_data_strobe
SD_LDQS <= clk_p; --low_data_strobe
SD_DQ <= data_write2(47 downto 32); --data
SD_UDM <= not byte_we_reg2(5); --upper_byte_enable
SD_LDM <= not byte_we_reg2(4); --low_byte_enable
else
SD_UDQS <= 'Z'; --upper_data_strobe
SD_LDQS <= 'Z'; --low_data_strobe
SD_DQ <= "ZZZZZZZZZZZZZZZZ"; --data
SD_UDM <= 'Z';
SD_LDM <= 'Z';
end if;
--DDR control signals
SD_CK_P <= clk_p; --clock_positive
SD_CK_N <= not clk_p; --clock_negative
SD_CKE <= cke_reg; --clock_enable
SD_BA <= address(12 downto 11); --bank_address
if command = COMMAND_ACTIVE or state_current = STATE_POWER_ON then
SD_A <= address(25 downto 13); --address row
elsif command = COMMAND_READ or command = COMMAND_WRITE then
SD_A <= "000" & address(10 downto 2) & "0"; --address col
else
SD_A <= "0010000000000"; --PERCHARGE all banks
end if;
SD_CS <= not cke_reg; --chip_select
SD_RAS <= command(2); --row_address_strobe
SD_CAS <= command(1); --column_address_strobe
SD_WE <= command(0); --write_enable
if active = '1' and state_current /= STATE_POWER_ON and
command /= COMMAND_WRITE and state_prev /= STATE_READ3 then
pause <= '1';
else
pause <= '0';
end if;
end process; --ddr_proc
end; --architecture logic
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity top_level is
port(
CLOCK_50 : in std_logic;
KEY : in std_logic_vector (3 downto 0);
LEDG : out std_logic_vector(7 downto 0) := X"00";
SRAM_ADDR : out std_logic_vector(17 downto 0);
SRAM_DQ : inout std_logic_vector(15 downto 0);
SRAM_WE_N : out std_logic;
SRAM_OE_N : out std_logic;
SRAM_UB_N : out std_logic;
SRAM_LB_N : out std_logic;
SRAM_CE_N : out std_logic;
ROW_SEL : in std_logic_vector(4 downto 0);
COL_SEL : out std_logic_vector(3 downto 0);
LCD_DATA : out std_logic_vector(7 downto 0);
LCD_EN : out std_logic;
LCD_RS : out std_logic;
LCD_ON : out std_logic;
HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7 : out std_logic_vector(7 downto 0)
);
end top_level;
architecture Behavioral of top_level is
component system_controller is
port (
clk_50 : in std_logic;
reset_key : in std_logic;
op_prog_mode : out std_logic;
sram_addr : out std_logic_vector (17 downto 0);
sram_dq : inout std_logic_vector (15 downto 0);
sram_we_n : out std_logic;
sram_oe_n : out std_logic;
sram_ub_n : out std_logic;
sram_lb_n : out std_logic;
sram_ce_n : out std_logic;
row_sel : in std_logic_vector (4 downto 0);
col_sel : out std_logic_vector(3 downto 0);
lcd_data_out : out std_logic_vector(7 downto 0);
lcd_enable_out : out std_logic;
lcd_select_out : out std_logic;
hex0, hex1, hex2, hex3, hex4, hex5 : out std_logic_vector (7 downto 0)
);
end component;
begin
LCD_ON <= '1';
HEX6 <= X"FF";
HEX7 <= X"FF";
Inst_system_controller: system_controller
port map (
clk_50 => CLOCK_50,
reset_key => KEY(0),
op_prog_mode => LEDG(0),
sram_addr => SRAM_ADDR,
sram_dq => SRAM_DQ,
sram_we_n => SRAM_WE_N,
sram_oe_n => SRAM_OE_N,
sram_ub_n => SRAM_UB_N,
sram_lb_n => SRAM_LB_N,
sram_ce_n => SRAM_CE_N,
row_sel => ROW_SEL,
col_sel => COL_SEL,
lcd_data_out => LCD_DATA,
lcd_enable_out => LCD_EN,
lcd_select_out => LCD_RS,
hex0 => HEX0,
hex1 => HEX1,
hex2 => HEX2,
hex3 => HEX3,
hex4 => HEX4,
hex5 => HEX5
);
end Behavioral; |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in1,
S => net6
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in2,
S => net6
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net7,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net7,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net3,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias3,
S => net8
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net8,
G => net5,
S => gnd
);
subnet0_subnet5_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net9,
G => net5,
S => gnd
);
subnet0_subnet5_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net9
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net10
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net10,
G => vbias4,
S => gnd
);
end simple;
|
-- $Id: ibdlib.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: ibdlib
-- Description: Definitions for ibus devices
--
-- Dependencies: -
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.2 now numeric_std clean
-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM;
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-07-12 233 1.0.5 add RESET, CE_USEC to _dl11, CE_USEC to _minisys
-- 2009-06-07 224 1.0.4 add iist_mreq and iist_sreq;
-- 2009-06-01 221 1.0.3 add RESET to kw11l; add iist;
-- 2009-05-30 220 1.0.2 add most additional device def's
-- 2009-05-24 219 1.0.1 add CE_MSEC to _rk11; add _maxisys
-- 2008-08-22 161 1.0 Initial version (extracted from pdp11.vhd)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
package ibdlib is
type iist_line_type is record -- iist line
dcf : slbit; -- disconnect flag
req : slbit; -- request
stf : slbit; -- sanity timer flag
imask : slv4; -- interrupt mask
bmask : slv4; -- boot mask
par : slbit; -- parity (odd)
frm : slbit; -- frame error flag
end record iist_line_type;
constant iist_line_init : iist_line_type := ('1','0','0',"0000","0000",'0','0');
type iist_bus_type is array (3 downto 0) of iist_line_type;
constant iist_bus_init : iist_bus_type := (others=>iist_line_init);
type iist_mreq_type is record -- iist->cpu requests
lock : slbit; -- lock-up CPU
boot : slbit; -- boot-up CPU
end record iist_mreq_type;
constant iist_mreq_init : iist_mreq_type := ('0','0');
type iist_sres_type is record -- cpu->iist responses
ack_lock : slbit; -- release lock
ack_boot : slbit; -- boot started
end record iist_sres_type;
constant iist_sres_init : iist_sres_type := ('0','0');
-- ise 13.1 xst can bug check if generic defaults in a package are defined via
-- 'slv(to_unsigned())'. The conv_ construct prior to numeric_std was ok.
-- As workaround the ibus default addresses are defined here as constant.
constant ibaddr_dz11 : slv16 := slv(to_unsigned(8#160100#,16));
constant ibaddr_dl11 : slv16 := slv(to_unsigned(8#177560#,16));
component ibd_iist is -- ibus dev(loc): IIST
-- fixed address: 177500
generic (
SID : slv2 := "00"); -- self id
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit; -- interrupt acknowledge
IIST_BUS : in iist_bus_type; -- iist bus (input from all iist's)
IIST_OUT : out iist_line_type; -- iist output
IIST_MREQ : out iist_mreq_type; -- iist->cpu requests
IIST_SRES : in iist_sres_type -- cpu->iist responses
);
end component;
component ibd_kw11p is -- ibus dev(loc): KW11-P (line clock)
-- fixed address: 172540
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end component;
component ibd_kw11l is -- ibus dev(loc): KW11-L (line clock)
-- fixed address: 177546
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end component;
component ibdr_rl11 is -- ibus dev(rem): RL11
-- fixed address: 174400
port (
CLK : in slbit; -- clock
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end component;
component ibdr_rk11 is -- ibus dev(rem): RK11
-- fixed address: 177400
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- msec pulse
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end component;
component ibdr_tm11 is -- ibus dev(rem): TM11
-- fixed address: 172520
port (
CLK : in slbit; -- clock
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end component;
component ibdr_dz11 is -- ibus dev(rem): DZ11
generic (
IB_ADDR : slv16 := ibaddr_dz11);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_RX : out slbit; -- interrupt request, receiver
EI_REQ_TX : out slbit; -- interrupt request, transmitter
EI_ACK_RX : in slbit; -- interrupt acknowledge, receiver
EI_ACK_TX : in slbit -- interrupt acknowledge, transmitter
);
end component;
component ibdr_dl11 is -- ibus dev(rem): DL11-A/B
generic (
IB_ADDR : slv16 := ibaddr_dl11);
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_RX : out slbit; -- interrupt request, receiver
EI_REQ_TX : out slbit; -- interrupt request, transmitter
EI_ACK_RX : in slbit; -- interrupt acknowledge, receiver
EI_ACK_TX : in slbit -- interrupt acknowledge, transmitter
);
end component;
component ibdr_pc11 is -- ibus dev(rem): PC11
-- fixed address: 177550
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_PTR : out slbit; -- interrupt request, reader
EI_REQ_PTP : out slbit; -- interrupt request, punch
EI_ACK_PTR : in slbit; -- interrupt acknowledge, reader
EI_ACK_PTP : in slbit -- interrupt acknowledge, punch
);
end component;
component ibdr_lp11 is -- ibus dev(rem): LP11
-- fixed address: 177514
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end component;
component ibdr_sdreg is -- ibus dev(rem): Switch/Display regs
-- fixed address: 177570
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
DISPREG : out slv16 -- display register
);
end component;
component ibdr_minisys is -- ibus(rem) minimal sys:SDR+KW+DL+RK
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slv16_1; -- remote attention vector
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
EI_PRI : out slv3; -- interrupt priority (to cpu)
EI_VECT : out slv9_2; -- interrupt vector (to cpu)
DISPREG : out slv16 -- display register
);
end component;
component ibdr_maxisys is -- ibus(rem) full system
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slv16_1; -- remote attention vector
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
EI_PRI : out slv3; -- interrupt priority (to cpu)
EI_VECT : out slv9_2; -- interrupt vector (to cpu)
DISPREG : out slv16 -- display register
);
end component;
end package ibdlib;
|
-- $Id: ibdlib.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: ibdlib
-- Description: Definitions for ibus devices
--
-- Dependencies: -
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.1.2 now numeric_std clean
-- 2010-10-23 335 1.1.1 rename RRI_LAM->RB_LAM;
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-07-12 233 1.0.5 add RESET, CE_USEC to _dl11, CE_USEC to _minisys
-- 2009-06-07 224 1.0.4 add iist_mreq and iist_sreq;
-- 2009-06-01 221 1.0.3 add RESET to kw11l; add iist;
-- 2009-05-30 220 1.0.2 add most additional device def's
-- 2009-05-24 219 1.0.1 add CE_MSEC to _rk11; add _maxisys
-- 2008-08-22 161 1.0 Initial version (extracted from pdp11.vhd)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
package ibdlib is
type iist_line_type is record -- iist line
dcf : slbit; -- disconnect flag
req : slbit; -- request
stf : slbit; -- sanity timer flag
imask : slv4; -- interrupt mask
bmask : slv4; -- boot mask
par : slbit; -- parity (odd)
frm : slbit; -- frame error flag
end record iist_line_type;
constant iist_line_init : iist_line_type := ('1','0','0',"0000","0000",'0','0');
type iist_bus_type is array (3 downto 0) of iist_line_type;
constant iist_bus_init : iist_bus_type := (others=>iist_line_init);
type iist_mreq_type is record -- iist->cpu requests
lock : slbit; -- lock-up CPU
boot : slbit; -- boot-up CPU
end record iist_mreq_type;
constant iist_mreq_init : iist_mreq_type := ('0','0');
type iist_sres_type is record -- cpu->iist responses
ack_lock : slbit; -- release lock
ack_boot : slbit; -- boot started
end record iist_sres_type;
constant iist_sres_init : iist_sres_type := ('0','0');
-- ise 13.1 xst can bug check if generic defaults in a package are defined via
-- 'slv(to_unsigned())'. The conv_ construct prior to numeric_std was ok.
-- As workaround the ibus default addresses are defined here as constant.
constant ibaddr_dz11 : slv16 := slv(to_unsigned(8#160100#,16));
constant ibaddr_dl11 : slv16 := slv(to_unsigned(8#177560#,16));
component ibd_iist is -- ibus dev(loc): IIST
-- fixed address: 177500
generic (
SID : slv2 := "00"); -- self id
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit; -- interrupt acknowledge
IIST_BUS : in iist_bus_type; -- iist bus (input from all iist's)
IIST_OUT : out iist_line_type; -- iist output
IIST_MREQ : out iist_mreq_type; -- iist->cpu requests
IIST_SRES : in iist_sres_type -- cpu->iist responses
);
end component;
component ibd_kw11p is -- ibus dev(loc): KW11-P (line clock)
-- fixed address: 172540
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end component;
component ibd_kw11l is -- ibus dev(loc): KW11-L (line clock)
-- fixed address: 177546
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end component;
component ibdr_rl11 is -- ibus dev(rem): RL11
-- fixed address: 174400
port (
CLK : in slbit; -- clock
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end component;
component ibdr_rk11 is -- ibus dev(rem): RK11
-- fixed address: 177400
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- msec pulse
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end component;
component ibdr_tm11 is -- ibus dev(rem): TM11
-- fixed address: 172520
port (
CLK : in slbit; -- clock
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end component;
component ibdr_dz11 is -- ibus dev(rem): DZ11
generic (
IB_ADDR : slv16 := ibaddr_dz11);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_RX : out slbit; -- interrupt request, receiver
EI_REQ_TX : out slbit; -- interrupt request, transmitter
EI_ACK_RX : in slbit; -- interrupt acknowledge, receiver
EI_ACK_TX : in slbit -- interrupt acknowledge, transmitter
);
end component;
component ibdr_dl11 is -- ibus dev(rem): DL11-A/B
generic (
IB_ADDR : slv16 := ibaddr_dl11);
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_RX : out slbit; -- interrupt request, receiver
EI_REQ_TX : out slbit; -- interrupt request, transmitter
EI_ACK_RX : in slbit; -- interrupt acknowledge, receiver
EI_ACK_TX : in slbit -- interrupt acknowledge, transmitter
);
end component;
component ibdr_pc11 is -- ibus dev(rem): PC11
-- fixed address: 177550
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_PTR : out slbit; -- interrupt request, reader
EI_REQ_PTP : out slbit; -- interrupt request, punch
EI_ACK_PTR : in slbit; -- interrupt acknowledge, reader
EI_ACK_PTP : in slbit -- interrupt acknowledge, punch
);
end component;
component ibdr_lp11 is -- ibus dev(rem): LP11
-- fixed address: 177514
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ : out slbit; -- interrupt request
EI_ACK : in slbit -- interrupt acknowledge
);
end component;
component ibdr_sdreg is -- ibus dev(rem): Switch/Display regs
-- fixed address: 177570
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
DISPREG : out slv16 -- display register
);
end component;
component ibdr_minisys is -- ibus(rem) minimal sys:SDR+KW+DL+RK
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slv16_1; -- remote attention vector
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
EI_PRI : out slv3; -- interrupt priority (to cpu)
EI_VECT : out slv9_2; -- interrupt vector (to cpu)
DISPREG : out slv16 -- display register
);
end component;
component ibdr_maxisys is -- ibus(rem) full system
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
CE_MSEC : in slbit; -- msec pulse
RESET : in slbit; -- reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slv16_1; -- remote attention vector
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_ACKM : in slbit; -- interrupt acknowledge (from master)
EI_PRI : out slv3; -- interrupt priority (to cpu)
EI_VECT : out slv9_2; -- interrupt vector (to cpu)
DISPREG : out slv16 -- display register
);
end component;
end package ibdlib;
|
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity CountEventsDown is
Port (
entrada_clk : in STD_LOGIC;
reset : in STD_LOGIC;
salida : out STD_LOGIC
);
end CountEventsDown;
architecture Behavioral of CountEventsDown is
constant cantidad: positive:=1000;
signal temporal: STD_LOGIC;
signal counter: positive:=cantidad;
begin process(entrada_clk)
begin
if reset='1' then
counter <= cantidad;
elsif rising_edge(entrada_clk) then
counter <= counter-1;
end if;
if counter=0 then
temporal<='1';
counter <= cantidad;
else
temporal<='0';
end if;
end process;
salida<=temporal;
end Behavioral;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:53:20 11/25/2016
-- Design Name:
-- Module Name: Z:/Documents/COP/COPproject/project/maintester.vhd
-- Project Name: project
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: main
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY maintester IS
END maintester;
ARCHITECTURE behavior OF maintester IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT main
PORT(
CLK0 : IN std_logic;
CLK1 : IN std_logic;
RAM1DATA : INOUT std_logic_vector(15 downto 0);
RAM2DATA : INOUT std_logic_vector(15 downto 0);
RAM1EN : OUT std_logic;
RAM1OE : OUT std_logic;
RAM1WE : OUT std_logic;
RAM2EN : OUT std_logic;
RAM2OE : OUT std_logic;
RAM2WE : OUT std_logic;
RAM1ADDR : OUT std_logic_vector(17 downto 0);
RAM2ADDR : OUT std_logic_vector(17 downto 0);
RESET : IN std_logic;
rdn : OUT std_logic;
wrn : OUT std_logic;
data_ready : IN std_logic;
tbre : IN std_logic;
tsre : IN std_logic
);
END COMPONENT;
--Inputs
signal CLK0 : std_logic := '0';
signal CLK1 : std_logic := '0';
signal RESET : std_logic := '1';
signal data_ready : std_logic := '0';
signal tbre : std_logic := '0';
signal tsre : std_logic := '0';
--BiDirs
signal RAM1DATA : std_logic_vector(15 downto 0);
signal RAM2DATA : std_logic_vector(15 downto 0);
--Outputs
signal RAM1EN : std_logic;
signal RAM1OE : std_logic;
signal RAM1WE : std_logic;
signal RAM2EN : std_logic;
signal RAM2OE : std_logic;
signal RAM2WE : std_logic;
signal RAM1ADDR : std_logic_vector(17 downto 0);
signal RAM2ADDR : std_logic_vector(17 downto 0);
signal rdn : std_logic;
signal wrn : std_logic;
-- Clock period definitions
constant CLK0_period : time := 1 sec;
constant CLK1_period : time := 1 sec;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: main PORT MAP (
CLK0 => CLK0,
CLK1 => CLK1,
RAM1DATA => RAM1DATA,
RAM2DATA => RAM2DATA,
RAM1EN => RAM1EN,
RAM1OE => RAM1OE,
RAM1WE => RAM1WE,
RAM2EN => RAM2EN,
RAM2OE => RAM2OE,
RAM2WE => RAM2WE,
RAM1ADDR => RAM1ADDR,
RAM2ADDR => RAM2ADDR,
RESET => RESET,
rdn => rdn,
wrn => wrn,
data_ready => data_ready,
tbre => tbre,
tsre => tsre
);
-- Clock process definitions
CLK0_process :process
begin
CLK0 <= '0';
wait for CLK0_period/2;
CLK0 <= '1';
wait for CLK0_period/2;
end process;
CLK1 <= '1';
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK0_period*10;
-- insert stimulus here
wait;
end process;
END;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2314.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p01n01i02314ent IS
END c07s02b07x00p01n01i02314ent;
ARCHITECTURE c07s02b07x00p01n01i02314arch OF c07s02b07x00p01n01i02314ent IS
BEGIN
TESTING: PROCESS
variable SEVERV : SEVERITY_LEVEL := NOTE;
BEGIN
SEVERV := ABS SEVERV;
assert FALSE
report "***FAILED TEST: c07s02b07x00p01n01i02314 - Unary operator abs is predefined for any numeric type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p01n01i02314arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2314.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p01n01i02314ent IS
END c07s02b07x00p01n01i02314ent;
ARCHITECTURE c07s02b07x00p01n01i02314arch OF c07s02b07x00p01n01i02314ent IS
BEGIN
TESTING: PROCESS
variable SEVERV : SEVERITY_LEVEL := NOTE;
BEGIN
SEVERV := ABS SEVERV;
assert FALSE
report "***FAILED TEST: c07s02b07x00p01n01i02314 - Unary operator abs is predefined for any numeric type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p01n01i02314arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2314.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p01n01i02314ent IS
END c07s02b07x00p01n01i02314ent;
ARCHITECTURE c07s02b07x00p01n01i02314arch OF c07s02b07x00p01n01i02314ent IS
BEGIN
TESTING: PROCESS
variable SEVERV : SEVERITY_LEVEL := NOTE;
BEGIN
SEVERV := ABS SEVERV;
assert FALSE
report "***FAILED TEST: c07s02b07x00p01n01i02314 - Unary operator abs is predefined for any numeric type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p01n01i02314arch;
|
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: gpio_core.vhd
-- Version: v1.01a
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
--
-------------------------------------------------------------------------------
--
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 09/15/09
-- ^^^^^^^^^^^^^^
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
-- Definition of Generics : --
-------------------------------------------------------------------------------
-- C_DW -- Data width of PLB BUS.
-- C_AW -- Address width of PLB BUS.
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_GPIO2_WIDTH -- GPIO2 Data Bus width.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-- C_FAMILY -- XILINX FPGA family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports --
-------------------------------------------------------------------------------
-- Clk -- Input clock
-- Rst -- Reset
-- ABus_Reg -- Bus to IP address
-- BE_Reg -- Bus to IP byte enables
-- DBus_Reg -- Bus to IP data bus
-- RNW_Reg -- Bus to IP read write control
-- GPIO_DBus -- IP to Bus data bus
-- GPIO_xferAck -- GPIO transfer acknowledge
-- GPIO_intr -- GPIO channel 1 interrupt to IPIC
-- GPIO2_intr -- GPIO channel 2 interrupt to IPIC
-- GPIO_Select -- GPIO select
--
-- GPIO_IO_I -- Channel 1 General purpose I/O in port
-- GPIO_IO_O -- Channel 1 General purpose I/O out port
-- GPIO_IO_T -- Channel 1 General purpose I/O TRI-STATE control port
-- GPIO2_IO_I -- Channel 2 General purpose I/O in port
-- GPIO2_IO_O -- Channel 2 General purpose I/O out port
-- GPIO2_IO_T -- Channel 2 General purpose I/O TRI-STATE control port
-------------------------------------------------------------------------------
entity GPIO_Core is
generic
(
C_DW : integer := 32;
C_AW : integer := 32;
C_GPIO_WIDTH : integer := 32;
C_GPIO2_WIDTH : integer := 32;
C_MAX_GPIO_WIDTH : integer := 32;
C_INTERRUPT_PRESENT : integer := 0;
C_DOUT_DEFAULT : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_IS_DUAL : integer := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_FAMILY : string := "virtex7"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
ABus_Reg : in std_logic_vector(0 to C_AW-1);
BE_Reg : in std_logic_vector(0 to C_DW/8-1);
DBus_Reg : in std_logic_vector(0 to C_MAX_GPIO_WIDTH-1);
RNW_Reg : in std_logic;
GPIO_DBus : out std_logic_vector(0 to C_DW-1);
GPIO_xferAck : out std_logic;
GPIO_intr : out std_logic;
GPIO2_intr : out std_logic;
GPIO_Select : in std_logic;
GPIO_IO_I : in std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_O : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_T : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO2_IO_I : in std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_O : out std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T : out std_logic_vector(0 to C_GPIO2_WIDTH-1)
);
end entity GPIO_Core;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of GPIO_Core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
----------------------------------------------------------------------
-- Function for Reduction OR
----------------------------------------------------------------------
function or_reduce(l : std_logic_vector) return std_logic is
variable v : std_logic := '0';
begin
for i in l'range loop
v := v or l(i);
end loop;
return v;
end;
---------------------------------------------------------------------
-- End of Function
-------------------------------------------------------------------
signal gpio_Data_Select : std_logic_vector(0 to C_IS_DUAL);
signal gpio_OE_Select : std_logic_vector(0 to C_IS_DUAL);
signal Read_Reg_Rst : STD_LOGIC;
signal Read_Reg_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal Read_Reg_CE : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_Data_Out : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_DOUT_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal gpio_Data_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_OE : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_TRI_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal GPIO_DBus_i : std_logic_vector(0 to C_DW-1);
signal gpio_data_in_xor : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_data_in_xor_reg : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal or_ints : std_logic_vector(0 to 0);
signal or_ints2 : std_logic_vector(0 to 0);
signal iGPIO_xferAck : STD_LOGIC;
signal gpio_xferAck_Reg : STD_LOGIC;
signal dout_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal tri_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal reset_zeros : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal dout2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal tri2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal reset2_zeros : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio_reg_en : std_logic;
begin -- architecture IMP
reset_zeros <= (others => '0');
reset2_zeros <= (others => '0');
TIE_DEFAULTS_GENERATE : if C_DW >= C_GPIO_WIDTH generate
SELECT_BITS_GENERATE : for i in 0 to C_GPIO_WIDTH-1 generate
dout_default_i(i) <= C_DOUT_DEFAULT(i-C_GPIO_WIDTH+C_DW);
tri_default_i(i) <= C_TRI_DEFAULT(i-C_GPIO_WIDTH+C_DW);
end generate SELECT_BITS_GENERATE;
end generate TIE_DEFAULTS_GENERATE;
TIE_DEFAULTS_2_GENERATE : if C_DW >= C_GPIO2_WIDTH generate
SELECT_BITS_2_GENERATE : for i in 0 to C_GPIO2_WIDTH-1 generate
dout2_default_i(i) <= C_DOUT_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
tri2_default_i(i) <= C_TRI_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
end generate SELECT_BITS_2_GENERATE;
end generate TIE_DEFAULTS_2_GENERATE;
Read_Reg_Rst <= iGPIO_xferAck or gpio_xferAck_Reg or (not GPIO_Select) or
(GPIO_Select and not RNW_Reg);
gpio_reg_en <= GPIO_Select when (ABus_Reg(0) = '0') else '0';
-----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
-----------------------------------------------------------------------------
XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
iGPIO_xferAck <= '0';
else
iGPIO_xferAck <= GPIO_Select and not gpio_xferAck_Reg;
if iGPIO_xferAck = '1' then
iGPIO_xferAck <= '0';
end if;
end if;
end if;
end process XFER_ACK_PROCESS;
-----------------------------------------------------------------------------
-- DELAYED_XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Single Reg stage to make Transfer Ack period one clock pulse wide
-----------------------------------------------------------------------------
DELAYED_XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_xferAck_Reg <= '0';
else
gpio_xferAck_Reg <= iGPIO_xferAck;
end if;
end if;
end process DELAYED_XFER_ACK_PROCESS;
GPIO_xferAck <= iGPIO_xferAck;
-----------------------------------------------------------------------------
-- Drive GPIO interrupts to '0' when interrupt not present
-----------------------------------------------------------------------------
DONT_GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
gpio_intr <= '0';
gpio2_intr <= '0';
end generate DONT_GEN_INTERRUPT;
----------------------------------------------------------------------------
-- When only one channel is used, the additional logic for the second
-- channel ports is not present
-----------------------------------------------------------------------------
Not_Dual : if (C_IS_DUAL = 0) generate
GPIO2_IO_O <= C_DOUT_DEFAULT(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T <= C_TRI_DEFAULT_2(0 to C_GPIO2_WIDTH-1);
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
----------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
-----------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
-----------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I based on
-- the channel select signals
-----------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i;
-----------------------------------------------------------------------------
-- REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for single channel configuration
-----------------------------------------------------------------------------
--REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
begin
gpio_Data_Select(0) <= '0';
gpio_OE_Select(0) <= '0';
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
if (ABus_Reg(5) = '0') then
case ABus_Reg(6) is -- bit A29
when '0' => gpio_Data_Select(0) <= '1';
when '1' => gpio_OE_Select(0) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end if;
end process REG_SELECT_PROCESS;
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS
---------------------------------------------------------------------------
-- Selects GPIO_TRI control or GPIO_DATA Register to be read
---------------------------------------------------------------------------
READ_MUX_PROCESS : process (gpio_Data_In, gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
end if;
end process READ_MUX_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
----------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
----------------------------------------------------------------------------
-- When the C_INTERRUPT_PRESENT=1, the interrupt is driven based on whether
-- there is a change in the data coming in at the GPIO_IO_I port or GPIO_In
-- port
----------------------------------------------------------------------------
GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change on any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XOR_INTR : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
GPIO_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
GPIO_intr <= or_ints(0);
end if;
end if;
end process REGISTER_XOR_INTR;
gpio2_intr <= '0'; -- Channel 2 interrupt is driven low
end generate GEN_INTERRUPT;
end generate Not_Dual;
---)(------------------------------------------------------------------------
-- When both the channels are used, the additional logic for the second
-- channel ports
-----------------------------------------------------------------------------
Dual : if (C_IS_DUAL = 1) generate
signal gpio2_Data_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor_reg : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_Data_Out : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_DOUT_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal gpio2_OE : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_TRI_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal Read_Reg2_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal Read_Reg2_CE : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal GPIO2_DBus_i : std_logic_vector(0 to C_DW-1);
begin
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
begin
--------------------------------------------------------------------------
-- GPIO_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL1 DATA BUS
--------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate
--------------------------------------------------------------------------
-- GPIO2_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL2 DATA BUS
--------------------------------------------------------------------------
GPIO2_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0';
else
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i);
end if;
end if;
end process;
end generate READ_REG2_GEN;
TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate
GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0');
end generate TIE_DBUS2_GENERATE;
---------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
---------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I and
-- GPIO2_DBUS_I based on which channel is selected
---------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i when (((gpio_Data_Select(0) = '1') or
(gpio_OE_Select(0) = '1')) and (RNW_Reg = '1'))
else GPIO2_DBus_i;
-----------------------------------------------------------------------------
-- DUAL_REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for Dual channel configuration
-----------------------------------------------------------------------------
--DUAL_REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
DUAL_REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
variable ABus_reg_select : std_logic_vector(0 to 1);
begin
ABus_reg_select := ABus_Reg(5 to 6);
gpio_Data_Select <= (others => '0');
gpio_OE_Select <= (others => '0');
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
-- case ABus_Reg(28 to 29) is -- bit A28,A29 for dual
case ABus_reg_select is -- bit A28,A29 for dual
when "00" => gpio_Data_Select(0) <= '1';
when "01" => gpio_OE_Select(0) <= '1';
when "10" => gpio_Data_Select(1) <= '1';
when "11" => gpio_OE_Select(1) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end process DUAL_REG_SELECT_PROCESS;
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
INPUT_DOUBLE_REGS4 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
INPUT_DOUBLE_REGS5 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO2_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO2_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio2_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO2_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 2 data from Bidirectional GPIO2 port
-- to GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio2_io_i_d1 <= GPIO2_IO_I;
-- gpio2_io_i_d2 <= gpio2_io_i_d1;
gpio2_Data_In <= gpio2_io_i_d2;
end if;
end process GPIO2_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS_0_0
---------------------------------------------------------------------------
-- Selects among Channel 1 GPIO_DATA ,GPIO_TRI and Channel 2 GPIO2_DATA
-- GPIO2_TRI REGISTERS for reading
---------------------------------------------------------------------------
READ_MUX_PROCESS_0_0 : process (gpio2_Data_In, gpio2_OE, gpio_Data_In,
gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
Read_Reg2_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
elsif gpio_Data_Select(1) = '1' then
Read_Reg2_In <= gpio2_Data_In;
elsif gpio_OE_Select(1) = '1' then
Read_Reg2_In <= gpio2_OE;
end if;
end process READ_MUX_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
---------------------------------------------------------------------------
-- GPIO2_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_Data_Out <= dout2_default_i;
elsif gpio_Data_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_Data_Out(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO2_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO2_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO2_OE_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_OE <= tri2_default_i;
elsif gpio_OE_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO2_OE_PROCESS_0_0;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
GPIO2_IO_O <= gpio2_Data_Out;
GPIO2_IO_T <= gpio2_OE;
---------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
---------------------------------------------------------------------------
gen_interrupt_dual : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
gpio2_data_in_xor <= gpio2_Data_In xor gpio2_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
or_ints2(0) <= or_reduce(gpio2_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XORs_INTRs : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
gpio2_data_in_xor_reg <= reset2_zeros;
GPIO_intr <= '0';
GPIO2_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
gpio2_data_in_xor_reg <= gpio2_data_in_xor;
GPIO_intr <= or_ints(0);
GPIO2_intr <= or_ints2(0);
end if;
end if;
end process REGISTER_XORs_INTRs;
end generate gen_interrupt_dual;
end generate Dual;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: gpio_core.vhd
-- Version: v1.01a
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
--
-------------------------------------------------------------------------------
--
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 09/15/09
-- ^^^^^^^^^^^^^^
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
-- Definition of Generics : --
-------------------------------------------------------------------------------
-- C_DW -- Data width of PLB BUS.
-- C_AW -- Address width of PLB BUS.
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_GPIO2_WIDTH -- GPIO2 Data Bus width.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-- C_FAMILY -- XILINX FPGA family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports --
-------------------------------------------------------------------------------
-- Clk -- Input clock
-- Rst -- Reset
-- ABus_Reg -- Bus to IP address
-- BE_Reg -- Bus to IP byte enables
-- DBus_Reg -- Bus to IP data bus
-- RNW_Reg -- Bus to IP read write control
-- GPIO_DBus -- IP to Bus data bus
-- GPIO_xferAck -- GPIO transfer acknowledge
-- GPIO_intr -- GPIO channel 1 interrupt to IPIC
-- GPIO2_intr -- GPIO channel 2 interrupt to IPIC
-- GPIO_Select -- GPIO select
--
-- GPIO_IO_I -- Channel 1 General purpose I/O in port
-- GPIO_IO_O -- Channel 1 General purpose I/O out port
-- GPIO_IO_T -- Channel 1 General purpose I/O TRI-STATE control port
-- GPIO2_IO_I -- Channel 2 General purpose I/O in port
-- GPIO2_IO_O -- Channel 2 General purpose I/O out port
-- GPIO2_IO_T -- Channel 2 General purpose I/O TRI-STATE control port
-------------------------------------------------------------------------------
entity GPIO_Core is
generic
(
C_DW : integer := 32;
C_AW : integer := 32;
C_GPIO_WIDTH : integer := 32;
C_GPIO2_WIDTH : integer := 32;
C_MAX_GPIO_WIDTH : integer := 32;
C_INTERRUPT_PRESENT : integer := 0;
C_DOUT_DEFAULT : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_IS_DUAL : integer := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_FAMILY : string := "virtex7"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
ABus_Reg : in std_logic_vector(0 to C_AW-1);
BE_Reg : in std_logic_vector(0 to C_DW/8-1);
DBus_Reg : in std_logic_vector(0 to C_MAX_GPIO_WIDTH-1);
RNW_Reg : in std_logic;
GPIO_DBus : out std_logic_vector(0 to C_DW-1);
GPIO_xferAck : out std_logic;
GPIO_intr : out std_logic;
GPIO2_intr : out std_logic;
GPIO_Select : in std_logic;
GPIO_IO_I : in std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_O : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_T : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO2_IO_I : in std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_O : out std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T : out std_logic_vector(0 to C_GPIO2_WIDTH-1)
);
end entity GPIO_Core;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of GPIO_Core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
----------------------------------------------------------------------
-- Function for Reduction OR
----------------------------------------------------------------------
function or_reduce(l : std_logic_vector) return std_logic is
variable v : std_logic := '0';
begin
for i in l'range loop
v := v or l(i);
end loop;
return v;
end;
---------------------------------------------------------------------
-- End of Function
-------------------------------------------------------------------
signal gpio_Data_Select : std_logic_vector(0 to C_IS_DUAL);
signal gpio_OE_Select : std_logic_vector(0 to C_IS_DUAL);
signal Read_Reg_Rst : STD_LOGIC;
signal Read_Reg_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal Read_Reg_CE : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_Data_Out : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_DOUT_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal gpio_Data_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_OE : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_TRI_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal GPIO_DBus_i : std_logic_vector(0 to C_DW-1);
signal gpio_data_in_xor : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_data_in_xor_reg : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal or_ints : std_logic_vector(0 to 0);
signal or_ints2 : std_logic_vector(0 to 0);
signal iGPIO_xferAck : STD_LOGIC;
signal gpio_xferAck_Reg : STD_LOGIC;
signal dout_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal tri_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal reset_zeros : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal dout2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal tri2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal reset2_zeros : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio_reg_en : std_logic;
begin -- architecture IMP
reset_zeros <= (others => '0');
reset2_zeros <= (others => '0');
TIE_DEFAULTS_GENERATE : if C_DW >= C_GPIO_WIDTH generate
SELECT_BITS_GENERATE : for i in 0 to C_GPIO_WIDTH-1 generate
dout_default_i(i) <= C_DOUT_DEFAULT(i-C_GPIO_WIDTH+C_DW);
tri_default_i(i) <= C_TRI_DEFAULT(i-C_GPIO_WIDTH+C_DW);
end generate SELECT_BITS_GENERATE;
end generate TIE_DEFAULTS_GENERATE;
TIE_DEFAULTS_2_GENERATE : if C_DW >= C_GPIO2_WIDTH generate
SELECT_BITS_2_GENERATE : for i in 0 to C_GPIO2_WIDTH-1 generate
dout2_default_i(i) <= C_DOUT_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
tri2_default_i(i) <= C_TRI_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
end generate SELECT_BITS_2_GENERATE;
end generate TIE_DEFAULTS_2_GENERATE;
Read_Reg_Rst <= iGPIO_xferAck or gpio_xferAck_Reg or (not GPIO_Select) or
(GPIO_Select and not RNW_Reg);
gpio_reg_en <= GPIO_Select when (ABus_Reg(0) = '0') else '0';
-----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
-----------------------------------------------------------------------------
XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
iGPIO_xferAck <= '0';
else
iGPIO_xferAck <= GPIO_Select and not gpio_xferAck_Reg;
if iGPIO_xferAck = '1' then
iGPIO_xferAck <= '0';
end if;
end if;
end if;
end process XFER_ACK_PROCESS;
-----------------------------------------------------------------------------
-- DELAYED_XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Single Reg stage to make Transfer Ack period one clock pulse wide
-----------------------------------------------------------------------------
DELAYED_XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_xferAck_Reg <= '0';
else
gpio_xferAck_Reg <= iGPIO_xferAck;
end if;
end if;
end process DELAYED_XFER_ACK_PROCESS;
GPIO_xferAck <= iGPIO_xferAck;
-----------------------------------------------------------------------------
-- Drive GPIO interrupts to '0' when interrupt not present
-----------------------------------------------------------------------------
DONT_GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
gpio_intr <= '0';
gpio2_intr <= '0';
end generate DONT_GEN_INTERRUPT;
----------------------------------------------------------------------------
-- When only one channel is used, the additional logic for the second
-- channel ports is not present
-----------------------------------------------------------------------------
Not_Dual : if (C_IS_DUAL = 0) generate
GPIO2_IO_O <= C_DOUT_DEFAULT(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T <= C_TRI_DEFAULT_2(0 to C_GPIO2_WIDTH-1);
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
----------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
-----------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
-----------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I based on
-- the channel select signals
-----------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i;
-----------------------------------------------------------------------------
-- REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for single channel configuration
-----------------------------------------------------------------------------
--REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
begin
gpio_Data_Select(0) <= '0';
gpio_OE_Select(0) <= '0';
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
if (ABus_Reg(5) = '0') then
case ABus_Reg(6) is -- bit A29
when '0' => gpio_Data_Select(0) <= '1';
when '1' => gpio_OE_Select(0) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end if;
end process REG_SELECT_PROCESS;
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS
---------------------------------------------------------------------------
-- Selects GPIO_TRI control or GPIO_DATA Register to be read
---------------------------------------------------------------------------
READ_MUX_PROCESS : process (gpio_Data_In, gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
end if;
end process READ_MUX_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
----------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
----------------------------------------------------------------------------
-- When the C_INTERRUPT_PRESENT=1, the interrupt is driven based on whether
-- there is a change in the data coming in at the GPIO_IO_I port or GPIO_In
-- port
----------------------------------------------------------------------------
GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change on any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XOR_INTR : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
GPIO_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
GPIO_intr <= or_ints(0);
end if;
end if;
end process REGISTER_XOR_INTR;
gpio2_intr <= '0'; -- Channel 2 interrupt is driven low
end generate GEN_INTERRUPT;
end generate Not_Dual;
---)(------------------------------------------------------------------------
-- When both the channels are used, the additional logic for the second
-- channel ports
-----------------------------------------------------------------------------
Dual : if (C_IS_DUAL = 1) generate
signal gpio2_Data_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor_reg : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_Data_Out : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_DOUT_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal gpio2_OE : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_TRI_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal Read_Reg2_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal Read_Reg2_CE : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal GPIO2_DBus_i : std_logic_vector(0 to C_DW-1);
begin
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
begin
--------------------------------------------------------------------------
-- GPIO_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL1 DATA BUS
--------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate
--------------------------------------------------------------------------
-- GPIO2_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL2 DATA BUS
--------------------------------------------------------------------------
GPIO2_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0';
else
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i);
end if;
end if;
end process;
end generate READ_REG2_GEN;
TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate
GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0');
end generate TIE_DBUS2_GENERATE;
---------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
---------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I and
-- GPIO2_DBUS_I based on which channel is selected
---------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i when (((gpio_Data_Select(0) = '1') or
(gpio_OE_Select(0) = '1')) and (RNW_Reg = '1'))
else GPIO2_DBus_i;
-----------------------------------------------------------------------------
-- DUAL_REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for Dual channel configuration
-----------------------------------------------------------------------------
--DUAL_REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
DUAL_REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
variable ABus_reg_select : std_logic_vector(0 to 1);
begin
ABus_reg_select := ABus_Reg(5 to 6);
gpio_Data_Select <= (others => '0');
gpio_OE_Select <= (others => '0');
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
-- case ABus_Reg(28 to 29) is -- bit A28,A29 for dual
case ABus_reg_select is -- bit A28,A29 for dual
when "00" => gpio_Data_Select(0) <= '1';
when "01" => gpio_OE_Select(0) <= '1';
when "10" => gpio_Data_Select(1) <= '1';
when "11" => gpio_OE_Select(1) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end process DUAL_REG_SELECT_PROCESS;
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
INPUT_DOUBLE_REGS4 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
INPUT_DOUBLE_REGS5 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO2_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO2_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio2_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO2_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 2 data from Bidirectional GPIO2 port
-- to GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio2_io_i_d1 <= GPIO2_IO_I;
-- gpio2_io_i_d2 <= gpio2_io_i_d1;
gpio2_Data_In <= gpio2_io_i_d2;
end if;
end process GPIO2_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS_0_0
---------------------------------------------------------------------------
-- Selects among Channel 1 GPIO_DATA ,GPIO_TRI and Channel 2 GPIO2_DATA
-- GPIO2_TRI REGISTERS for reading
---------------------------------------------------------------------------
READ_MUX_PROCESS_0_0 : process (gpio2_Data_In, gpio2_OE, gpio_Data_In,
gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
Read_Reg2_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
elsif gpio_Data_Select(1) = '1' then
Read_Reg2_In <= gpio2_Data_In;
elsif gpio_OE_Select(1) = '1' then
Read_Reg2_In <= gpio2_OE;
end if;
end process READ_MUX_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
---------------------------------------------------------------------------
-- GPIO2_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_Data_Out <= dout2_default_i;
elsif gpio_Data_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_Data_Out(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO2_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO2_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO2_OE_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_OE <= tri2_default_i;
elsif gpio_OE_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO2_OE_PROCESS_0_0;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
GPIO2_IO_O <= gpio2_Data_Out;
GPIO2_IO_T <= gpio2_OE;
---------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
---------------------------------------------------------------------------
gen_interrupt_dual : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
gpio2_data_in_xor <= gpio2_Data_In xor gpio2_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
or_ints2(0) <= or_reduce(gpio2_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XORs_INTRs : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
gpio2_data_in_xor_reg <= reset2_zeros;
GPIO_intr <= '0';
GPIO2_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
gpio2_data_in_xor_reg <= gpio2_data_in_xor;
GPIO_intr <= or_ints(0);
GPIO2_intr <= or_ints2(0);
end if;
end if;
end process REGISTER_XORs_INTRs;
end generate gen_interrupt_dual;
end generate Dual;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: gpio_core.vhd
-- Version: v1.01a
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
--
-------------------------------------------------------------------------------
--
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 09/15/09
-- ^^^^^^^^^^^^^^
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
-- Definition of Generics : --
-------------------------------------------------------------------------------
-- C_DW -- Data width of PLB BUS.
-- C_AW -- Address width of PLB BUS.
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_GPIO2_WIDTH -- GPIO2 Data Bus width.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-- C_FAMILY -- XILINX FPGA family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports --
-------------------------------------------------------------------------------
-- Clk -- Input clock
-- Rst -- Reset
-- ABus_Reg -- Bus to IP address
-- BE_Reg -- Bus to IP byte enables
-- DBus_Reg -- Bus to IP data bus
-- RNW_Reg -- Bus to IP read write control
-- GPIO_DBus -- IP to Bus data bus
-- GPIO_xferAck -- GPIO transfer acknowledge
-- GPIO_intr -- GPIO channel 1 interrupt to IPIC
-- GPIO2_intr -- GPIO channel 2 interrupt to IPIC
-- GPIO_Select -- GPIO select
--
-- GPIO_IO_I -- Channel 1 General purpose I/O in port
-- GPIO_IO_O -- Channel 1 General purpose I/O out port
-- GPIO_IO_T -- Channel 1 General purpose I/O TRI-STATE control port
-- GPIO2_IO_I -- Channel 2 General purpose I/O in port
-- GPIO2_IO_O -- Channel 2 General purpose I/O out port
-- GPIO2_IO_T -- Channel 2 General purpose I/O TRI-STATE control port
-------------------------------------------------------------------------------
entity GPIO_Core is
generic
(
C_DW : integer := 32;
C_AW : integer := 32;
C_GPIO_WIDTH : integer := 32;
C_GPIO2_WIDTH : integer := 32;
C_MAX_GPIO_WIDTH : integer := 32;
C_INTERRUPT_PRESENT : integer := 0;
C_DOUT_DEFAULT : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_IS_DUAL : integer := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_FAMILY : string := "virtex7"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
ABus_Reg : in std_logic_vector(0 to C_AW-1);
BE_Reg : in std_logic_vector(0 to C_DW/8-1);
DBus_Reg : in std_logic_vector(0 to C_MAX_GPIO_WIDTH-1);
RNW_Reg : in std_logic;
GPIO_DBus : out std_logic_vector(0 to C_DW-1);
GPIO_xferAck : out std_logic;
GPIO_intr : out std_logic;
GPIO2_intr : out std_logic;
GPIO_Select : in std_logic;
GPIO_IO_I : in std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_O : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_T : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO2_IO_I : in std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_O : out std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T : out std_logic_vector(0 to C_GPIO2_WIDTH-1)
);
end entity GPIO_Core;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of GPIO_Core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
----------------------------------------------------------------------
-- Function for Reduction OR
----------------------------------------------------------------------
function or_reduce(l : std_logic_vector) return std_logic is
variable v : std_logic := '0';
begin
for i in l'range loop
v := v or l(i);
end loop;
return v;
end;
---------------------------------------------------------------------
-- End of Function
-------------------------------------------------------------------
signal gpio_Data_Select : std_logic_vector(0 to C_IS_DUAL);
signal gpio_OE_Select : std_logic_vector(0 to C_IS_DUAL);
signal Read_Reg_Rst : STD_LOGIC;
signal Read_Reg_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal Read_Reg_CE : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_Data_Out : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_DOUT_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal gpio_Data_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_OE : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_TRI_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal GPIO_DBus_i : std_logic_vector(0 to C_DW-1);
signal gpio_data_in_xor : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_data_in_xor_reg : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal or_ints : std_logic_vector(0 to 0);
signal or_ints2 : std_logic_vector(0 to 0);
signal iGPIO_xferAck : STD_LOGIC;
signal gpio_xferAck_Reg : STD_LOGIC;
signal dout_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal tri_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal reset_zeros : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal dout2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal tri2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal reset2_zeros : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio_reg_en : std_logic;
begin -- architecture IMP
reset_zeros <= (others => '0');
reset2_zeros <= (others => '0');
TIE_DEFAULTS_GENERATE : if C_DW >= C_GPIO_WIDTH generate
SELECT_BITS_GENERATE : for i in 0 to C_GPIO_WIDTH-1 generate
dout_default_i(i) <= C_DOUT_DEFAULT(i-C_GPIO_WIDTH+C_DW);
tri_default_i(i) <= C_TRI_DEFAULT(i-C_GPIO_WIDTH+C_DW);
end generate SELECT_BITS_GENERATE;
end generate TIE_DEFAULTS_GENERATE;
TIE_DEFAULTS_2_GENERATE : if C_DW >= C_GPIO2_WIDTH generate
SELECT_BITS_2_GENERATE : for i in 0 to C_GPIO2_WIDTH-1 generate
dout2_default_i(i) <= C_DOUT_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
tri2_default_i(i) <= C_TRI_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
end generate SELECT_BITS_2_GENERATE;
end generate TIE_DEFAULTS_2_GENERATE;
Read_Reg_Rst <= iGPIO_xferAck or gpio_xferAck_Reg or (not GPIO_Select) or
(GPIO_Select and not RNW_Reg);
gpio_reg_en <= GPIO_Select when (ABus_Reg(0) = '0') else '0';
-----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
-----------------------------------------------------------------------------
XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
iGPIO_xferAck <= '0';
else
iGPIO_xferAck <= GPIO_Select and not gpio_xferAck_Reg;
if iGPIO_xferAck = '1' then
iGPIO_xferAck <= '0';
end if;
end if;
end if;
end process XFER_ACK_PROCESS;
-----------------------------------------------------------------------------
-- DELAYED_XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Single Reg stage to make Transfer Ack period one clock pulse wide
-----------------------------------------------------------------------------
DELAYED_XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_xferAck_Reg <= '0';
else
gpio_xferAck_Reg <= iGPIO_xferAck;
end if;
end if;
end process DELAYED_XFER_ACK_PROCESS;
GPIO_xferAck <= iGPIO_xferAck;
-----------------------------------------------------------------------------
-- Drive GPIO interrupts to '0' when interrupt not present
-----------------------------------------------------------------------------
DONT_GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
gpio_intr <= '0';
gpio2_intr <= '0';
end generate DONT_GEN_INTERRUPT;
----------------------------------------------------------------------------
-- When only one channel is used, the additional logic for the second
-- channel ports is not present
-----------------------------------------------------------------------------
Not_Dual : if (C_IS_DUAL = 0) generate
GPIO2_IO_O <= C_DOUT_DEFAULT(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T <= C_TRI_DEFAULT_2(0 to C_GPIO2_WIDTH-1);
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
----------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
-----------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
-----------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I based on
-- the channel select signals
-----------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i;
-----------------------------------------------------------------------------
-- REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for single channel configuration
-----------------------------------------------------------------------------
--REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
begin
gpio_Data_Select(0) <= '0';
gpio_OE_Select(0) <= '0';
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
if (ABus_Reg(5) = '0') then
case ABus_Reg(6) is -- bit A29
when '0' => gpio_Data_Select(0) <= '1';
when '1' => gpio_OE_Select(0) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end if;
end process REG_SELECT_PROCESS;
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS
---------------------------------------------------------------------------
-- Selects GPIO_TRI control or GPIO_DATA Register to be read
---------------------------------------------------------------------------
READ_MUX_PROCESS : process (gpio_Data_In, gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
end if;
end process READ_MUX_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
----------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
----------------------------------------------------------------------------
-- When the C_INTERRUPT_PRESENT=1, the interrupt is driven based on whether
-- there is a change in the data coming in at the GPIO_IO_I port or GPIO_In
-- port
----------------------------------------------------------------------------
GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change on any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XOR_INTR : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
GPIO_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
GPIO_intr <= or_ints(0);
end if;
end if;
end process REGISTER_XOR_INTR;
gpio2_intr <= '0'; -- Channel 2 interrupt is driven low
end generate GEN_INTERRUPT;
end generate Not_Dual;
---)(------------------------------------------------------------------------
-- When both the channels are used, the additional logic for the second
-- channel ports
-----------------------------------------------------------------------------
Dual : if (C_IS_DUAL = 1) generate
signal gpio2_Data_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor_reg : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_Data_Out : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_DOUT_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal gpio2_OE : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_TRI_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal Read_Reg2_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal Read_Reg2_CE : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal GPIO2_DBus_i : std_logic_vector(0 to C_DW-1);
begin
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
begin
--------------------------------------------------------------------------
-- GPIO_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL1 DATA BUS
--------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate
--------------------------------------------------------------------------
-- GPIO2_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL2 DATA BUS
--------------------------------------------------------------------------
GPIO2_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0';
else
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i);
end if;
end if;
end process;
end generate READ_REG2_GEN;
TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate
GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0');
end generate TIE_DBUS2_GENERATE;
---------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
---------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I and
-- GPIO2_DBUS_I based on which channel is selected
---------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i when (((gpio_Data_Select(0) = '1') or
(gpio_OE_Select(0) = '1')) and (RNW_Reg = '1'))
else GPIO2_DBus_i;
-----------------------------------------------------------------------------
-- DUAL_REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for Dual channel configuration
-----------------------------------------------------------------------------
--DUAL_REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
DUAL_REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
variable ABus_reg_select : std_logic_vector(0 to 1);
begin
ABus_reg_select := ABus_Reg(5 to 6);
gpio_Data_Select <= (others => '0');
gpio_OE_Select <= (others => '0');
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
-- case ABus_Reg(28 to 29) is -- bit A28,A29 for dual
case ABus_reg_select is -- bit A28,A29 for dual
when "00" => gpio_Data_Select(0) <= '1';
when "01" => gpio_OE_Select(0) <= '1';
when "10" => gpio_Data_Select(1) <= '1';
when "11" => gpio_OE_Select(1) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end process DUAL_REG_SELECT_PROCESS;
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
INPUT_DOUBLE_REGS4 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
INPUT_DOUBLE_REGS5 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO2_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO2_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio2_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO2_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 2 data from Bidirectional GPIO2 port
-- to GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio2_io_i_d1 <= GPIO2_IO_I;
-- gpio2_io_i_d2 <= gpio2_io_i_d1;
gpio2_Data_In <= gpio2_io_i_d2;
end if;
end process GPIO2_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS_0_0
---------------------------------------------------------------------------
-- Selects among Channel 1 GPIO_DATA ,GPIO_TRI and Channel 2 GPIO2_DATA
-- GPIO2_TRI REGISTERS for reading
---------------------------------------------------------------------------
READ_MUX_PROCESS_0_0 : process (gpio2_Data_In, gpio2_OE, gpio_Data_In,
gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
Read_Reg2_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
elsif gpio_Data_Select(1) = '1' then
Read_Reg2_In <= gpio2_Data_In;
elsif gpio_OE_Select(1) = '1' then
Read_Reg2_In <= gpio2_OE;
end if;
end process READ_MUX_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
---------------------------------------------------------------------------
-- GPIO2_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_Data_Out <= dout2_default_i;
elsif gpio_Data_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_Data_Out(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO2_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO2_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO2_OE_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_OE <= tri2_default_i;
elsif gpio_OE_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO2_OE_PROCESS_0_0;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
GPIO2_IO_O <= gpio2_Data_Out;
GPIO2_IO_T <= gpio2_OE;
---------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
---------------------------------------------------------------------------
gen_interrupt_dual : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
gpio2_data_in_xor <= gpio2_Data_In xor gpio2_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
or_ints2(0) <= or_reduce(gpio2_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XORs_INTRs : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
gpio2_data_in_xor_reg <= reset2_zeros;
GPIO_intr <= '0';
GPIO2_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
gpio2_data_in_xor_reg <= gpio2_data_in_xor;
GPIO_intr <= or_ints(0);
GPIO2_intr <= or_ints2(0);
end if;
end if;
end process REGISTER_XORs_INTRs;
end generate gen_interrupt_dual;
end generate Dual;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: gpio_core.vhd
-- Version: v1.01a
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
--
-------------------------------------------------------------------------------
--
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 09/15/09
-- ^^^^^^^^^^^^^^
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
-- Definition of Generics : --
-------------------------------------------------------------------------------
-- C_DW -- Data width of PLB BUS.
-- C_AW -- Address width of PLB BUS.
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_GPIO2_WIDTH -- GPIO2 Data Bus width.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-- C_FAMILY -- XILINX FPGA family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports --
-------------------------------------------------------------------------------
-- Clk -- Input clock
-- Rst -- Reset
-- ABus_Reg -- Bus to IP address
-- BE_Reg -- Bus to IP byte enables
-- DBus_Reg -- Bus to IP data bus
-- RNW_Reg -- Bus to IP read write control
-- GPIO_DBus -- IP to Bus data bus
-- GPIO_xferAck -- GPIO transfer acknowledge
-- GPIO_intr -- GPIO channel 1 interrupt to IPIC
-- GPIO2_intr -- GPIO channel 2 interrupt to IPIC
-- GPIO_Select -- GPIO select
--
-- GPIO_IO_I -- Channel 1 General purpose I/O in port
-- GPIO_IO_O -- Channel 1 General purpose I/O out port
-- GPIO_IO_T -- Channel 1 General purpose I/O TRI-STATE control port
-- GPIO2_IO_I -- Channel 2 General purpose I/O in port
-- GPIO2_IO_O -- Channel 2 General purpose I/O out port
-- GPIO2_IO_T -- Channel 2 General purpose I/O TRI-STATE control port
-------------------------------------------------------------------------------
entity GPIO_Core is
generic
(
C_DW : integer := 32;
C_AW : integer := 32;
C_GPIO_WIDTH : integer := 32;
C_GPIO2_WIDTH : integer := 32;
C_MAX_GPIO_WIDTH : integer := 32;
C_INTERRUPT_PRESENT : integer := 0;
C_DOUT_DEFAULT : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_IS_DUAL : integer := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_FAMILY : string := "virtex7"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
ABus_Reg : in std_logic_vector(0 to C_AW-1);
BE_Reg : in std_logic_vector(0 to C_DW/8-1);
DBus_Reg : in std_logic_vector(0 to C_MAX_GPIO_WIDTH-1);
RNW_Reg : in std_logic;
GPIO_DBus : out std_logic_vector(0 to C_DW-1);
GPIO_xferAck : out std_logic;
GPIO_intr : out std_logic;
GPIO2_intr : out std_logic;
GPIO_Select : in std_logic;
GPIO_IO_I : in std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_O : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_T : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO2_IO_I : in std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_O : out std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T : out std_logic_vector(0 to C_GPIO2_WIDTH-1)
);
end entity GPIO_Core;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of GPIO_Core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
----------------------------------------------------------------------
-- Function for Reduction OR
----------------------------------------------------------------------
function or_reduce(l : std_logic_vector) return std_logic is
variable v : std_logic := '0';
begin
for i in l'range loop
v := v or l(i);
end loop;
return v;
end;
---------------------------------------------------------------------
-- End of Function
-------------------------------------------------------------------
signal gpio_Data_Select : std_logic_vector(0 to C_IS_DUAL);
signal gpio_OE_Select : std_logic_vector(0 to C_IS_DUAL);
signal Read_Reg_Rst : STD_LOGIC;
signal Read_Reg_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal Read_Reg_CE : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_Data_Out : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_DOUT_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal gpio_Data_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_OE : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_TRI_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal GPIO_DBus_i : std_logic_vector(0 to C_DW-1);
signal gpio_data_in_xor : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_data_in_xor_reg : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal or_ints : std_logic_vector(0 to 0);
signal or_ints2 : std_logic_vector(0 to 0);
signal iGPIO_xferAck : STD_LOGIC;
signal gpio_xferAck_Reg : STD_LOGIC;
signal dout_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal tri_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal reset_zeros : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal dout2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal tri2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal reset2_zeros : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio_reg_en : std_logic;
begin -- architecture IMP
reset_zeros <= (others => '0');
reset2_zeros <= (others => '0');
TIE_DEFAULTS_GENERATE : if C_DW >= C_GPIO_WIDTH generate
SELECT_BITS_GENERATE : for i in 0 to C_GPIO_WIDTH-1 generate
dout_default_i(i) <= C_DOUT_DEFAULT(i-C_GPIO_WIDTH+C_DW);
tri_default_i(i) <= C_TRI_DEFAULT(i-C_GPIO_WIDTH+C_DW);
end generate SELECT_BITS_GENERATE;
end generate TIE_DEFAULTS_GENERATE;
TIE_DEFAULTS_2_GENERATE : if C_DW >= C_GPIO2_WIDTH generate
SELECT_BITS_2_GENERATE : for i in 0 to C_GPIO2_WIDTH-1 generate
dout2_default_i(i) <= C_DOUT_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
tri2_default_i(i) <= C_TRI_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
end generate SELECT_BITS_2_GENERATE;
end generate TIE_DEFAULTS_2_GENERATE;
Read_Reg_Rst <= iGPIO_xferAck or gpio_xferAck_Reg or (not GPIO_Select) or
(GPIO_Select and not RNW_Reg);
gpio_reg_en <= GPIO_Select when (ABus_Reg(0) = '0') else '0';
-----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
-----------------------------------------------------------------------------
XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
iGPIO_xferAck <= '0';
else
iGPIO_xferAck <= GPIO_Select and not gpio_xferAck_Reg;
if iGPIO_xferAck = '1' then
iGPIO_xferAck <= '0';
end if;
end if;
end if;
end process XFER_ACK_PROCESS;
-----------------------------------------------------------------------------
-- DELAYED_XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Single Reg stage to make Transfer Ack period one clock pulse wide
-----------------------------------------------------------------------------
DELAYED_XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_xferAck_Reg <= '0';
else
gpio_xferAck_Reg <= iGPIO_xferAck;
end if;
end if;
end process DELAYED_XFER_ACK_PROCESS;
GPIO_xferAck <= iGPIO_xferAck;
-----------------------------------------------------------------------------
-- Drive GPIO interrupts to '0' when interrupt not present
-----------------------------------------------------------------------------
DONT_GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
gpio_intr <= '0';
gpio2_intr <= '0';
end generate DONT_GEN_INTERRUPT;
----------------------------------------------------------------------------
-- When only one channel is used, the additional logic for the second
-- channel ports is not present
-----------------------------------------------------------------------------
Not_Dual : if (C_IS_DUAL = 0) generate
GPIO2_IO_O <= C_DOUT_DEFAULT(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T <= C_TRI_DEFAULT_2(0 to C_GPIO2_WIDTH-1);
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
----------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
-----------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
-----------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I based on
-- the channel select signals
-----------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i;
-----------------------------------------------------------------------------
-- REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for single channel configuration
-----------------------------------------------------------------------------
--REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
begin
gpio_Data_Select(0) <= '0';
gpio_OE_Select(0) <= '0';
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
if (ABus_Reg(5) = '0') then
case ABus_Reg(6) is -- bit A29
when '0' => gpio_Data_Select(0) <= '1';
when '1' => gpio_OE_Select(0) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end if;
end process REG_SELECT_PROCESS;
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS
---------------------------------------------------------------------------
-- Selects GPIO_TRI control or GPIO_DATA Register to be read
---------------------------------------------------------------------------
READ_MUX_PROCESS : process (gpio_Data_In, gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
end if;
end process READ_MUX_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
----------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
----------------------------------------------------------------------------
-- When the C_INTERRUPT_PRESENT=1, the interrupt is driven based on whether
-- there is a change in the data coming in at the GPIO_IO_I port or GPIO_In
-- port
----------------------------------------------------------------------------
GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change on any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XOR_INTR : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
GPIO_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
GPIO_intr <= or_ints(0);
end if;
end if;
end process REGISTER_XOR_INTR;
gpio2_intr <= '0'; -- Channel 2 interrupt is driven low
end generate GEN_INTERRUPT;
end generate Not_Dual;
---)(------------------------------------------------------------------------
-- When both the channels are used, the additional logic for the second
-- channel ports
-----------------------------------------------------------------------------
Dual : if (C_IS_DUAL = 1) generate
signal gpio2_Data_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor_reg : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_Data_Out : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_DOUT_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal gpio2_OE : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_TRI_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal Read_Reg2_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal Read_Reg2_CE : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal GPIO2_DBus_i : std_logic_vector(0 to C_DW-1);
begin
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
begin
--------------------------------------------------------------------------
-- GPIO_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL1 DATA BUS
--------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate
--------------------------------------------------------------------------
-- GPIO2_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL2 DATA BUS
--------------------------------------------------------------------------
GPIO2_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0';
else
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i);
end if;
end if;
end process;
end generate READ_REG2_GEN;
TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate
GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0');
end generate TIE_DBUS2_GENERATE;
---------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
---------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I and
-- GPIO2_DBUS_I based on which channel is selected
---------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i when (((gpio_Data_Select(0) = '1') or
(gpio_OE_Select(0) = '1')) and (RNW_Reg = '1'))
else GPIO2_DBus_i;
-----------------------------------------------------------------------------
-- DUAL_REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for Dual channel configuration
-----------------------------------------------------------------------------
--DUAL_REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
DUAL_REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
variable ABus_reg_select : std_logic_vector(0 to 1);
begin
ABus_reg_select := ABus_Reg(5 to 6);
gpio_Data_Select <= (others => '0');
gpio_OE_Select <= (others => '0');
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
-- case ABus_Reg(28 to 29) is -- bit A28,A29 for dual
case ABus_reg_select is -- bit A28,A29 for dual
when "00" => gpio_Data_Select(0) <= '1';
when "01" => gpio_OE_Select(0) <= '1';
when "10" => gpio_Data_Select(1) <= '1';
when "11" => gpio_OE_Select(1) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end process DUAL_REG_SELECT_PROCESS;
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
INPUT_DOUBLE_REGS4 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
INPUT_DOUBLE_REGS5 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO2_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO2_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio2_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO2_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 2 data from Bidirectional GPIO2 port
-- to GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio2_io_i_d1 <= GPIO2_IO_I;
-- gpio2_io_i_d2 <= gpio2_io_i_d1;
gpio2_Data_In <= gpio2_io_i_d2;
end if;
end process GPIO2_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS_0_0
---------------------------------------------------------------------------
-- Selects among Channel 1 GPIO_DATA ,GPIO_TRI and Channel 2 GPIO2_DATA
-- GPIO2_TRI REGISTERS for reading
---------------------------------------------------------------------------
READ_MUX_PROCESS_0_0 : process (gpio2_Data_In, gpio2_OE, gpio_Data_In,
gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
Read_Reg2_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
elsif gpio_Data_Select(1) = '1' then
Read_Reg2_In <= gpio2_Data_In;
elsif gpio_OE_Select(1) = '1' then
Read_Reg2_In <= gpio2_OE;
end if;
end process READ_MUX_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
---------------------------------------------------------------------------
-- GPIO2_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_Data_Out <= dout2_default_i;
elsif gpio_Data_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_Data_Out(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO2_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO2_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO2_OE_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_OE <= tri2_default_i;
elsif gpio_OE_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO2_OE_PROCESS_0_0;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
GPIO2_IO_O <= gpio2_Data_Out;
GPIO2_IO_T <= gpio2_OE;
---------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
---------------------------------------------------------------------------
gen_interrupt_dual : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
gpio2_data_in_xor <= gpio2_Data_In xor gpio2_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
or_ints2(0) <= or_reduce(gpio2_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XORs_INTRs : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
gpio2_data_in_xor_reg <= reset2_zeros;
GPIO_intr <= '0';
GPIO2_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
gpio2_data_in_xor_reg <= gpio2_data_in_xor;
GPIO_intr <= or_ints(0);
GPIO2_intr <= or_ints2(0);
end if;
end if;
end process REGISTER_XORs_INTRs;
end generate gen_interrupt_dual;
end generate Dual;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: gpio_core.vhd
-- Version: v1.01a
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
--
-------------------------------------------------------------------------------
--
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 09/15/09
-- ^^^^^^^^^^^^^^
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
-- Definition of Generics : --
-------------------------------------------------------------------------------
-- C_DW -- Data width of PLB BUS.
-- C_AW -- Address width of PLB BUS.
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_GPIO2_WIDTH -- GPIO2 Data Bus width.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-- C_FAMILY -- XILINX FPGA family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports --
-------------------------------------------------------------------------------
-- Clk -- Input clock
-- Rst -- Reset
-- ABus_Reg -- Bus to IP address
-- BE_Reg -- Bus to IP byte enables
-- DBus_Reg -- Bus to IP data bus
-- RNW_Reg -- Bus to IP read write control
-- GPIO_DBus -- IP to Bus data bus
-- GPIO_xferAck -- GPIO transfer acknowledge
-- GPIO_intr -- GPIO channel 1 interrupt to IPIC
-- GPIO2_intr -- GPIO channel 2 interrupt to IPIC
-- GPIO_Select -- GPIO select
--
-- GPIO_IO_I -- Channel 1 General purpose I/O in port
-- GPIO_IO_O -- Channel 1 General purpose I/O out port
-- GPIO_IO_T -- Channel 1 General purpose I/O TRI-STATE control port
-- GPIO2_IO_I -- Channel 2 General purpose I/O in port
-- GPIO2_IO_O -- Channel 2 General purpose I/O out port
-- GPIO2_IO_T -- Channel 2 General purpose I/O TRI-STATE control port
-------------------------------------------------------------------------------
entity GPIO_Core is
generic
(
C_DW : integer := 32;
C_AW : integer := 32;
C_GPIO_WIDTH : integer := 32;
C_GPIO2_WIDTH : integer := 32;
C_MAX_GPIO_WIDTH : integer := 32;
C_INTERRUPT_PRESENT : integer := 0;
C_DOUT_DEFAULT : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_IS_DUAL : integer := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_FAMILY : string := "virtex7"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
ABus_Reg : in std_logic_vector(0 to C_AW-1);
BE_Reg : in std_logic_vector(0 to C_DW/8-1);
DBus_Reg : in std_logic_vector(0 to C_MAX_GPIO_WIDTH-1);
RNW_Reg : in std_logic;
GPIO_DBus : out std_logic_vector(0 to C_DW-1);
GPIO_xferAck : out std_logic;
GPIO_intr : out std_logic;
GPIO2_intr : out std_logic;
GPIO_Select : in std_logic;
GPIO_IO_I : in std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_O : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_T : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO2_IO_I : in std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_O : out std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T : out std_logic_vector(0 to C_GPIO2_WIDTH-1)
);
end entity GPIO_Core;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of GPIO_Core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
----------------------------------------------------------------------
-- Function for Reduction OR
----------------------------------------------------------------------
function or_reduce(l : std_logic_vector) return std_logic is
variable v : std_logic := '0';
begin
for i in l'range loop
v := v or l(i);
end loop;
return v;
end;
---------------------------------------------------------------------
-- End of Function
-------------------------------------------------------------------
signal gpio_Data_Select : std_logic_vector(0 to C_IS_DUAL);
signal gpio_OE_Select : std_logic_vector(0 to C_IS_DUAL);
signal Read_Reg_Rst : STD_LOGIC;
signal Read_Reg_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal Read_Reg_CE : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_Data_Out : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_DOUT_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal gpio_Data_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_OE : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_TRI_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal GPIO_DBus_i : std_logic_vector(0 to C_DW-1);
signal gpio_data_in_xor : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_data_in_xor_reg : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal or_ints : std_logic_vector(0 to 0);
signal or_ints2 : std_logic_vector(0 to 0);
signal iGPIO_xferAck : STD_LOGIC;
signal gpio_xferAck_Reg : STD_LOGIC;
signal dout_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal tri_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal reset_zeros : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal dout2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal tri2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal reset2_zeros : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio_reg_en : std_logic;
begin -- architecture IMP
reset_zeros <= (others => '0');
reset2_zeros <= (others => '0');
TIE_DEFAULTS_GENERATE : if C_DW >= C_GPIO_WIDTH generate
SELECT_BITS_GENERATE : for i in 0 to C_GPIO_WIDTH-1 generate
dout_default_i(i) <= C_DOUT_DEFAULT(i-C_GPIO_WIDTH+C_DW);
tri_default_i(i) <= C_TRI_DEFAULT(i-C_GPIO_WIDTH+C_DW);
end generate SELECT_BITS_GENERATE;
end generate TIE_DEFAULTS_GENERATE;
TIE_DEFAULTS_2_GENERATE : if C_DW >= C_GPIO2_WIDTH generate
SELECT_BITS_2_GENERATE : for i in 0 to C_GPIO2_WIDTH-1 generate
dout2_default_i(i) <= C_DOUT_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
tri2_default_i(i) <= C_TRI_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
end generate SELECT_BITS_2_GENERATE;
end generate TIE_DEFAULTS_2_GENERATE;
Read_Reg_Rst <= iGPIO_xferAck or gpio_xferAck_Reg or (not GPIO_Select) or
(GPIO_Select and not RNW_Reg);
gpio_reg_en <= GPIO_Select when (ABus_Reg(0) = '0') else '0';
-----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
-----------------------------------------------------------------------------
XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
iGPIO_xferAck <= '0';
else
iGPIO_xferAck <= GPIO_Select and not gpio_xferAck_Reg;
if iGPIO_xferAck = '1' then
iGPIO_xferAck <= '0';
end if;
end if;
end if;
end process XFER_ACK_PROCESS;
-----------------------------------------------------------------------------
-- DELAYED_XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Single Reg stage to make Transfer Ack period one clock pulse wide
-----------------------------------------------------------------------------
DELAYED_XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_xferAck_Reg <= '0';
else
gpio_xferAck_Reg <= iGPIO_xferAck;
end if;
end if;
end process DELAYED_XFER_ACK_PROCESS;
GPIO_xferAck <= iGPIO_xferAck;
-----------------------------------------------------------------------------
-- Drive GPIO interrupts to '0' when interrupt not present
-----------------------------------------------------------------------------
DONT_GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
gpio_intr <= '0';
gpio2_intr <= '0';
end generate DONT_GEN_INTERRUPT;
----------------------------------------------------------------------------
-- When only one channel is used, the additional logic for the second
-- channel ports is not present
-----------------------------------------------------------------------------
Not_Dual : if (C_IS_DUAL = 0) generate
GPIO2_IO_O <= C_DOUT_DEFAULT(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T <= C_TRI_DEFAULT_2(0 to C_GPIO2_WIDTH-1);
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
----------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
-----------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
-----------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I based on
-- the channel select signals
-----------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i;
-----------------------------------------------------------------------------
-- REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for single channel configuration
-----------------------------------------------------------------------------
--REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
begin
gpio_Data_Select(0) <= '0';
gpio_OE_Select(0) <= '0';
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
if (ABus_Reg(5) = '0') then
case ABus_Reg(6) is -- bit A29
when '0' => gpio_Data_Select(0) <= '1';
when '1' => gpio_OE_Select(0) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end if;
end process REG_SELECT_PROCESS;
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS
---------------------------------------------------------------------------
-- Selects GPIO_TRI control or GPIO_DATA Register to be read
---------------------------------------------------------------------------
READ_MUX_PROCESS : process (gpio_Data_In, gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
end if;
end process READ_MUX_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
----------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
----------------------------------------------------------------------------
-- When the C_INTERRUPT_PRESENT=1, the interrupt is driven based on whether
-- there is a change in the data coming in at the GPIO_IO_I port or GPIO_In
-- port
----------------------------------------------------------------------------
GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change on any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XOR_INTR : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
GPIO_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
GPIO_intr <= or_ints(0);
end if;
end if;
end process REGISTER_XOR_INTR;
gpio2_intr <= '0'; -- Channel 2 interrupt is driven low
end generate GEN_INTERRUPT;
end generate Not_Dual;
---)(------------------------------------------------------------------------
-- When both the channels are used, the additional logic for the second
-- channel ports
-----------------------------------------------------------------------------
Dual : if (C_IS_DUAL = 1) generate
signal gpio2_Data_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor_reg : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_Data_Out : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_DOUT_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal gpio2_OE : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_TRI_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal Read_Reg2_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal Read_Reg2_CE : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal GPIO2_DBus_i : std_logic_vector(0 to C_DW-1);
begin
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
begin
--------------------------------------------------------------------------
-- GPIO_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL1 DATA BUS
--------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate
--------------------------------------------------------------------------
-- GPIO2_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL2 DATA BUS
--------------------------------------------------------------------------
GPIO2_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0';
else
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i);
end if;
end if;
end process;
end generate READ_REG2_GEN;
TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate
GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0');
end generate TIE_DBUS2_GENERATE;
---------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
---------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I and
-- GPIO2_DBUS_I based on which channel is selected
---------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i when (((gpio_Data_Select(0) = '1') or
(gpio_OE_Select(0) = '1')) and (RNW_Reg = '1'))
else GPIO2_DBus_i;
-----------------------------------------------------------------------------
-- DUAL_REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for Dual channel configuration
-----------------------------------------------------------------------------
--DUAL_REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
DUAL_REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
variable ABus_reg_select : std_logic_vector(0 to 1);
begin
ABus_reg_select := ABus_Reg(5 to 6);
gpio_Data_Select <= (others => '0');
gpio_OE_Select <= (others => '0');
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
-- case ABus_Reg(28 to 29) is -- bit A28,A29 for dual
case ABus_reg_select is -- bit A28,A29 for dual
when "00" => gpio_Data_Select(0) <= '1';
when "01" => gpio_OE_Select(0) <= '1';
when "10" => gpio_Data_Select(1) <= '1';
when "11" => gpio_OE_Select(1) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end process DUAL_REG_SELECT_PROCESS;
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
INPUT_DOUBLE_REGS4 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
INPUT_DOUBLE_REGS5 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO2_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO2_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio2_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO2_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 2 data from Bidirectional GPIO2 port
-- to GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio2_io_i_d1 <= GPIO2_IO_I;
-- gpio2_io_i_d2 <= gpio2_io_i_d1;
gpio2_Data_In <= gpio2_io_i_d2;
end if;
end process GPIO2_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS_0_0
---------------------------------------------------------------------------
-- Selects among Channel 1 GPIO_DATA ,GPIO_TRI and Channel 2 GPIO2_DATA
-- GPIO2_TRI REGISTERS for reading
---------------------------------------------------------------------------
READ_MUX_PROCESS_0_0 : process (gpio2_Data_In, gpio2_OE, gpio_Data_In,
gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
Read_Reg2_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
elsif gpio_Data_Select(1) = '1' then
Read_Reg2_In <= gpio2_Data_In;
elsif gpio_OE_Select(1) = '1' then
Read_Reg2_In <= gpio2_OE;
end if;
end process READ_MUX_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
---------------------------------------------------------------------------
-- GPIO2_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_Data_Out <= dout2_default_i;
elsif gpio_Data_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_Data_Out(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO2_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO2_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO2_OE_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_OE <= tri2_default_i;
elsif gpio_OE_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO2_OE_PROCESS_0_0;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
GPIO2_IO_O <= gpio2_Data_Out;
GPIO2_IO_T <= gpio2_OE;
---------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
---------------------------------------------------------------------------
gen_interrupt_dual : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
gpio2_data_in_xor <= gpio2_Data_In xor gpio2_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
or_ints2(0) <= or_reduce(gpio2_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XORs_INTRs : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
gpio2_data_in_xor_reg <= reset2_zeros;
GPIO_intr <= '0';
GPIO2_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
gpio2_data_in_xor_reg <= gpio2_data_in_xor;
GPIO_intr <= or_ints(0);
GPIO2_intr <= or_ints2(0);
end if;
end if;
end process REGISTER_XORs_INTRs;
end generate gen_interrupt_dual;
end generate Dual;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: gpio_core.vhd
-- Version: v1.01a
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
--
-------------------------------------------------------------------------------
--
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 09/15/09
-- ^^^^^^^^^^^^^^
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
-- Definition of Generics : --
-------------------------------------------------------------------------------
-- C_DW -- Data width of PLB BUS.
-- C_AW -- Address width of PLB BUS.
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_GPIO2_WIDTH -- GPIO2 Data Bus width.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-- C_FAMILY -- XILINX FPGA family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports --
-------------------------------------------------------------------------------
-- Clk -- Input clock
-- Rst -- Reset
-- ABus_Reg -- Bus to IP address
-- BE_Reg -- Bus to IP byte enables
-- DBus_Reg -- Bus to IP data bus
-- RNW_Reg -- Bus to IP read write control
-- GPIO_DBus -- IP to Bus data bus
-- GPIO_xferAck -- GPIO transfer acknowledge
-- GPIO_intr -- GPIO channel 1 interrupt to IPIC
-- GPIO2_intr -- GPIO channel 2 interrupt to IPIC
-- GPIO_Select -- GPIO select
--
-- GPIO_IO_I -- Channel 1 General purpose I/O in port
-- GPIO_IO_O -- Channel 1 General purpose I/O out port
-- GPIO_IO_T -- Channel 1 General purpose I/O TRI-STATE control port
-- GPIO2_IO_I -- Channel 2 General purpose I/O in port
-- GPIO2_IO_O -- Channel 2 General purpose I/O out port
-- GPIO2_IO_T -- Channel 2 General purpose I/O TRI-STATE control port
-------------------------------------------------------------------------------
entity GPIO_Core is
generic
(
C_DW : integer := 32;
C_AW : integer := 32;
C_GPIO_WIDTH : integer := 32;
C_GPIO2_WIDTH : integer := 32;
C_MAX_GPIO_WIDTH : integer := 32;
C_INTERRUPT_PRESENT : integer := 0;
C_DOUT_DEFAULT : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_IS_DUAL : integer := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_FAMILY : string := "virtex7"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
ABus_Reg : in std_logic_vector(0 to C_AW-1);
BE_Reg : in std_logic_vector(0 to C_DW/8-1);
DBus_Reg : in std_logic_vector(0 to C_MAX_GPIO_WIDTH-1);
RNW_Reg : in std_logic;
GPIO_DBus : out std_logic_vector(0 to C_DW-1);
GPIO_xferAck : out std_logic;
GPIO_intr : out std_logic;
GPIO2_intr : out std_logic;
GPIO_Select : in std_logic;
GPIO_IO_I : in std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_O : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_T : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO2_IO_I : in std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_O : out std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T : out std_logic_vector(0 to C_GPIO2_WIDTH-1)
);
end entity GPIO_Core;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of GPIO_Core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
----------------------------------------------------------------------
-- Function for Reduction OR
----------------------------------------------------------------------
function or_reduce(l : std_logic_vector) return std_logic is
variable v : std_logic := '0';
begin
for i in l'range loop
v := v or l(i);
end loop;
return v;
end;
---------------------------------------------------------------------
-- End of Function
-------------------------------------------------------------------
signal gpio_Data_Select : std_logic_vector(0 to C_IS_DUAL);
signal gpio_OE_Select : std_logic_vector(0 to C_IS_DUAL);
signal Read_Reg_Rst : STD_LOGIC;
signal Read_Reg_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal Read_Reg_CE : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_Data_Out : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_DOUT_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal gpio_Data_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_OE : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_TRI_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal GPIO_DBus_i : std_logic_vector(0 to C_DW-1);
signal gpio_data_in_xor : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_data_in_xor_reg : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal or_ints : std_logic_vector(0 to 0);
signal or_ints2 : std_logic_vector(0 to 0);
signal iGPIO_xferAck : STD_LOGIC;
signal gpio_xferAck_Reg : STD_LOGIC;
signal dout_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal tri_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal reset_zeros : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal dout2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal tri2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal reset2_zeros : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio_reg_en : std_logic;
begin -- architecture IMP
reset_zeros <= (others => '0');
reset2_zeros <= (others => '0');
TIE_DEFAULTS_GENERATE : if C_DW >= C_GPIO_WIDTH generate
SELECT_BITS_GENERATE : for i in 0 to C_GPIO_WIDTH-1 generate
dout_default_i(i) <= C_DOUT_DEFAULT(i-C_GPIO_WIDTH+C_DW);
tri_default_i(i) <= C_TRI_DEFAULT(i-C_GPIO_WIDTH+C_DW);
end generate SELECT_BITS_GENERATE;
end generate TIE_DEFAULTS_GENERATE;
TIE_DEFAULTS_2_GENERATE : if C_DW >= C_GPIO2_WIDTH generate
SELECT_BITS_2_GENERATE : for i in 0 to C_GPIO2_WIDTH-1 generate
dout2_default_i(i) <= C_DOUT_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
tri2_default_i(i) <= C_TRI_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
end generate SELECT_BITS_2_GENERATE;
end generate TIE_DEFAULTS_2_GENERATE;
Read_Reg_Rst <= iGPIO_xferAck or gpio_xferAck_Reg or (not GPIO_Select) or
(GPIO_Select and not RNW_Reg);
gpio_reg_en <= GPIO_Select when (ABus_Reg(0) = '0') else '0';
-----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
-----------------------------------------------------------------------------
XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
iGPIO_xferAck <= '0';
else
iGPIO_xferAck <= GPIO_Select and not gpio_xferAck_Reg;
if iGPIO_xferAck = '1' then
iGPIO_xferAck <= '0';
end if;
end if;
end if;
end process XFER_ACK_PROCESS;
-----------------------------------------------------------------------------
-- DELAYED_XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Single Reg stage to make Transfer Ack period one clock pulse wide
-----------------------------------------------------------------------------
DELAYED_XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_xferAck_Reg <= '0';
else
gpio_xferAck_Reg <= iGPIO_xferAck;
end if;
end if;
end process DELAYED_XFER_ACK_PROCESS;
GPIO_xferAck <= iGPIO_xferAck;
-----------------------------------------------------------------------------
-- Drive GPIO interrupts to '0' when interrupt not present
-----------------------------------------------------------------------------
DONT_GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
gpio_intr <= '0';
gpio2_intr <= '0';
end generate DONT_GEN_INTERRUPT;
----------------------------------------------------------------------------
-- When only one channel is used, the additional logic for the second
-- channel ports is not present
-----------------------------------------------------------------------------
Not_Dual : if (C_IS_DUAL = 0) generate
GPIO2_IO_O <= C_DOUT_DEFAULT(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T <= C_TRI_DEFAULT_2(0 to C_GPIO2_WIDTH-1);
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
----------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
-----------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
-----------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I based on
-- the channel select signals
-----------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i;
-----------------------------------------------------------------------------
-- REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for single channel configuration
-----------------------------------------------------------------------------
--REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
begin
gpio_Data_Select(0) <= '0';
gpio_OE_Select(0) <= '0';
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
if (ABus_Reg(5) = '0') then
case ABus_Reg(6) is -- bit A29
when '0' => gpio_Data_Select(0) <= '1';
when '1' => gpio_OE_Select(0) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end if;
end process REG_SELECT_PROCESS;
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS
---------------------------------------------------------------------------
-- Selects GPIO_TRI control or GPIO_DATA Register to be read
---------------------------------------------------------------------------
READ_MUX_PROCESS : process (gpio_Data_In, gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
end if;
end process READ_MUX_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
----------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
----------------------------------------------------------------------------
-- When the C_INTERRUPT_PRESENT=1, the interrupt is driven based on whether
-- there is a change in the data coming in at the GPIO_IO_I port or GPIO_In
-- port
----------------------------------------------------------------------------
GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change on any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XOR_INTR : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
GPIO_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
GPIO_intr <= or_ints(0);
end if;
end if;
end process REGISTER_XOR_INTR;
gpio2_intr <= '0'; -- Channel 2 interrupt is driven low
end generate GEN_INTERRUPT;
end generate Not_Dual;
---)(------------------------------------------------------------------------
-- When both the channels are used, the additional logic for the second
-- channel ports
-----------------------------------------------------------------------------
Dual : if (C_IS_DUAL = 1) generate
signal gpio2_Data_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor_reg : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_Data_Out : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_DOUT_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal gpio2_OE : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_TRI_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal Read_Reg2_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal Read_Reg2_CE : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal GPIO2_DBus_i : std_logic_vector(0 to C_DW-1);
begin
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
begin
--------------------------------------------------------------------------
-- GPIO_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL1 DATA BUS
--------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate
--------------------------------------------------------------------------
-- GPIO2_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL2 DATA BUS
--------------------------------------------------------------------------
GPIO2_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0';
else
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i);
end if;
end if;
end process;
end generate READ_REG2_GEN;
TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate
GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0');
end generate TIE_DBUS2_GENERATE;
---------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
---------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I and
-- GPIO2_DBUS_I based on which channel is selected
---------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i when (((gpio_Data_Select(0) = '1') or
(gpio_OE_Select(0) = '1')) and (RNW_Reg = '1'))
else GPIO2_DBus_i;
-----------------------------------------------------------------------------
-- DUAL_REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for Dual channel configuration
-----------------------------------------------------------------------------
--DUAL_REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
DUAL_REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
variable ABus_reg_select : std_logic_vector(0 to 1);
begin
ABus_reg_select := ABus_Reg(5 to 6);
gpio_Data_Select <= (others => '0');
gpio_OE_Select <= (others => '0');
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
-- case ABus_Reg(28 to 29) is -- bit A28,A29 for dual
case ABus_reg_select is -- bit A28,A29 for dual
when "00" => gpio_Data_Select(0) <= '1';
when "01" => gpio_OE_Select(0) <= '1';
when "10" => gpio_Data_Select(1) <= '1';
when "11" => gpio_OE_Select(1) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end process DUAL_REG_SELECT_PROCESS;
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
INPUT_DOUBLE_REGS4 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
INPUT_DOUBLE_REGS5 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO2_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO2_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio2_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO2_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 2 data from Bidirectional GPIO2 port
-- to GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio2_io_i_d1 <= GPIO2_IO_I;
-- gpio2_io_i_d2 <= gpio2_io_i_d1;
gpio2_Data_In <= gpio2_io_i_d2;
end if;
end process GPIO2_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS_0_0
---------------------------------------------------------------------------
-- Selects among Channel 1 GPIO_DATA ,GPIO_TRI and Channel 2 GPIO2_DATA
-- GPIO2_TRI REGISTERS for reading
---------------------------------------------------------------------------
READ_MUX_PROCESS_0_0 : process (gpio2_Data_In, gpio2_OE, gpio_Data_In,
gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
Read_Reg2_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
elsif gpio_Data_Select(1) = '1' then
Read_Reg2_In <= gpio2_Data_In;
elsif gpio_OE_Select(1) = '1' then
Read_Reg2_In <= gpio2_OE;
end if;
end process READ_MUX_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
---------------------------------------------------------------------------
-- GPIO2_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_Data_Out <= dout2_default_i;
elsif gpio_Data_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_Data_Out(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO2_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO2_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO2_OE_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_OE <= tri2_default_i;
elsif gpio_OE_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO2_OE_PROCESS_0_0;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
GPIO2_IO_O <= gpio2_Data_Out;
GPIO2_IO_T <= gpio2_OE;
---------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
---------------------------------------------------------------------------
gen_interrupt_dual : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
gpio2_data_in_xor <= gpio2_Data_In xor gpio2_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
or_ints2(0) <= or_reduce(gpio2_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XORs_INTRs : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
gpio2_data_in_xor_reg <= reset2_zeros;
GPIO_intr <= '0';
GPIO2_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
gpio2_data_in_xor_reg <= gpio2_data_in_xor;
GPIO_intr <= or_ints(0);
GPIO2_intr <= or_ints2(0);
end if;
end if;
end process REGISTER_XORs_INTRs;
end generate gen_interrupt_dual;
end generate Dual;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: gpio_core.vhd
-- Version: v1.01a
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
--
-------------------------------------------------------------------------------
--
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 09/15/09
-- ^^^^^^^^^^^^^^
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
-- Definition of Generics : --
-------------------------------------------------------------------------------
-- C_DW -- Data width of PLB BUS.
-- C_AW -- Address width of PLB BUS.
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_GPIO2_WIDTH -- GPIO2 Data Bus width.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-- C_FAMILY -- XILINX FPGA family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports --
-------------------------------------------------------------------------------
-- Clk -- Input clock
-- Rst -- Reset
-- ABus_Reg -- Bus to IP address
-- BE_Reg -- Bus to IP byte enables
-- DBus_Reg -- Bus to IP data bus
-- RNW_Reg -- Bus to IP read write control
-- GPIO_DBus -- IP to Bus data bus
-- GPIO_xferAck -- GPIO transfer acknowledge
-- GPIO_intr -- GPIO channel 1 interrupt to IPIC
-- GPIO2_intr -- GPIO channel 2 interrupt to IPIC
-- GPIO_Select -- GPIO select
--
-- GPIO_IO_I -- Channel 1 General purpose I/O in port
-- GPIO_IO_O -- Channel 1 General purpose I/O out port
-- GPIO_IO_T -- Channel 1 General purpose I/O TRI-STATE control port
-- GPIO2_IO_I -- Channel 2 General purpose I/O in port
-- GPIO2_IO_O -- Channel 2 General purpose I/O out port
-- GPIO2_IO_T -- Channel 2 General purpose I/O TRI-STATE control port
-------------------------------------------------------------------------------
entity GPIO_Core is
generic
(
C_DW : integer := 32;
C_AW : integer := 32;
C_GPIO_WIDTH : integer := 32;
C_GPIO2_WIDTH : integer := 32;
C_MAX_GPIO_WIDTH : integer := 32;
C_INTERRUPT_PRESENT : integer := 0;
C_DOUT_DEFAULT : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_IS_DUAL : integer := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_FAMILY : string := "virtex7"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
ABus_Reg : in std_logic_vector(0 to C_AW-1);
BE_Reg : in std_logic_vector(0 to C_DW/8-1);
DBus_Reg : in std_logic_vector(0 to C_MAX_GPIO_WIDTH-1);
RNW_Reg : in std_logic;
GPIO_DBus : out std_logic_vector(0 to C_DW-1);
GPIO_xferAck : out std_logic;
GPIO_intr : out std_logic;
GPIO2_intr : out std_logic;
GPIO_Select : in std_logic;
GPIO_IO_I : in std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_O : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_T : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO2_IO_I : in std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_O : out std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T : out std_logic_vector(0 to C_GPIO2_WIDTH-1)
);
end entity GPIO_Core;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of GPIO_Core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
----------------------------------------------------------------------
-- Function for Reduction OR
----------------------------------------------------------------------
function or_reduce(l : std_logic_vector) return std_logic is
variable v : std_logic := '0';
begin
for i in l'range loop
v := v or l(i);
end loop;
return v;
end;
---------------------------------------------------------------------
-- End of Function
-------------------------------------------------------------------
signal gpio_Data_Select : std_logic_vector(0 to C_IS_DUAL);
signal gpio_OE_Select : std_logic_vector(0 to C_IS_DUAL);
signal Read_Reg_Rst : STD_LOGIC;
signal Read_Reg_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal Read_Reg_CE : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_Data_Out : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_DOUT_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal gpio_Data_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_OE : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_TRI_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal GPIO_DBus_i : std_logic_vector(0 to C_DW-1);
signal gpio_data_in_xor : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_data_in_xor_reg : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal or_ints : std_logic_vector(0 to 0);
signal or_ints2 : std_logic_vector(0 to 0);
signal iGPIO_xferAck : STD_LOGIC;
signal gpio_xferAck_Reg : STD_LOGIC;
signal dout_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal tri_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal reset_zeros : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal dout2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal tri2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal reset2_zeros : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio_reg_en : std_logic;
begin -- architecture IMP
reset_zeros <= (others => '0');
reset2_zeros <= (others => '0');
TIE_DEFAULTS_GENERATE : if C_DW >= C_GPIO_WIDTH generate
SELECT_BITS_GENERATE : for i in 0 to C_GPIO_WIDTH-1 generate
dout_default_i(i) <= C_DOUT_DEFAULT(i-C_GPIO_WIDTH+C_DW);
tri_default_i(i) <= C_TRI_DEFAULT(i-C_GPIO_WIDTH+C_DW);
end generate SELECT_BITS_GENERATE;
end generate TIE_DEFAULTS_GENERATE;
TIE_DEFAULTS_2_GENERATE : if C_DW >= C_GPIO2_WIDTH generate
SELECT_BITS_2_GENERATE : for i in 0 to C_GPIO2_WIDTH-1 generate
dout2_default_i(i) <= C_DOUT_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
tri2_default_i(i) <= C_TRI_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
end generate SELECT_BITS_2_GENERATE;
end generate TIE_DEFAULTS_2_GENERATE;
Read_Reg_Rst <= iGPIO_xferAck or gpio_xferAck_Reg or (not GPIO_Select) or
(GPIO_Select and not RNW_Reg);
gpio_reg_en <= GPIO_Select when (ABus_Reg(0) = '0') else '0';
-----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
-----------------------------------------------------------------------------
XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
iGPIO_xferAck <= '0';
else
iGPIO_xferAck <= GPIO_Select and not gpio_xferAck_Reg;
if iGPIO_xferAck = '1' then
iGPIO_xferAck <= '0';
end if;
end if;
end if;
end process XFER_ACK_PROCESS;
-----------------------------------------------------------------------------
-- DELAYED_XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Single Reg stage to make Transfer Ack period one clock pulse wide
-----------------------------------------------------------------------------
DELAYED_XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_xferAck_Reg <= '0';
else
gpio_xferAck_Reg <= iGPIO_xferAck;
end if;
end if;
end process DELAYED_XFER_ACK_PROCESS;
GPIO_xferAck <= iGPIO_xferAck;
-----------------------------------------------------------------------------
-- Drive GPIO interrupts to '0' when interrupt not present
-----------------------------------------------------------------------------
DONT_GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
gpio_intr <= '0';
gpio2_intr <= '0';
end generate DONT_GEN_INTERRUPT;
----------------------------------------------------------------------------
-- When only one channel is used, the additional logic for the second
-- channel ports is not present
-----------------------------------------------------------------------------
Not_Dual : if (C_IS_DUAL = 0) generate
GPIO2_IO_O <= C_DOUT_DEFAULT(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T <= C_TRI_DEFAULT_2(0 to C_GPIO2_WIDTH-1);
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
----------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
-----------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
-----------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I based on
-- the channel select signals
-----------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i;
-----------------------------------------------------------------------------
-- REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for single channel configuration
-----------------------------------------------------------------------------
--REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
begin
gpio_Data_Select(0) <= '0';
gpio_OE_Select(0) <= '0';
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
if (ABus_Reg(5) = '0') then
case ABus_Reg(6) is -- bit A29
when '0' => gpio_Data_Select(0) <= '1';
when '1' => gpio_OE_Select(0) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end if;
end process REG_SELECT_PROCESS;
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS
---------------------------------------------------------------------------
-- Selects GPIO_TRI control or GPIO_DATA Register to be read
---------------------------------------------------------------------------
READ_MUX_PROCESS : process (gpio_Data_In, gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
end if;
end process READ_MUX_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
----------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
----------------------------------------------------------------------------
-- When the C_INTERRUPT_PRESENT=1, the interrupt is driven based on whether
-- there is a change in the data coming in at the GPIO_IO_I port or GPIO_In
-- port
----------------------------------------------------------------------------
GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change on any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XOR_INTR : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
GPIO_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
GPIO_intr <= or_ints(0);
end if;
end if;
end process REGISTER_XOR_INTR;
gpio2_intr <= '0'; -- Channel 2 interrupt is driven low
end generate GEN_INTERRUPT;
end generate Not_Dual;
---)(------------------------------------------------------------------------
-- When both the channels are used, the additional logic for the second
-- channel ports
-----------------------------------------------------------------------------
Dual : if (C_IS_DUAL = 1) generate
signal gpio2_Data_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor_reg : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_Data_Out : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_DOUT_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal gpio2_OE : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_TRI_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal Read_Reg2_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal Read_Reg2_CE : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal GPIO2_DBus_i : std_logic_vector(0 to C_DW-1);
begin
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
begin
--------------------------------------------------------------------------
-- GPIO_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL1 DATA BUS
--------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate
--------------------------------------------------------------------------
-- GPIO2_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL2 DATA BUS
--------------------------------------------------------------------------
GPIO2_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0';
else
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i);
end if;
end if;
end process;
end generate READ_REG2_GEN;
TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate
GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0');
end generate TIE_DBUS2_GENERATE;
---------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
---------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I and
-- GPIO2_DBUS_I based on which channel is selected
---------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i when (((gpio_Data_Select(0) = '1') or
(gpio_OE_Select(0) = '1')) and (RNW_Reg = '1'))
else GPIO2_DBus_i;
-----------------------------------------------------------------------------
-- DUAL_REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for Dual channel configuration
-----------------------------------------------------------------------------
--DUAL_REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
DUAL_REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
variable ABus_reg_select : std_logic_vector(0 to 1);
begin
ABus_reg_select := ABus_Reg(5 to 6);
gpio_Data_Select <= (others => '0');
gpio_OE_Select <= (others => '0');
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
-- case ABus_Reg(28 to 29) is -- bit A28,A29 for dual
case ABus_reg_select is -- bit A28,A29 for dual
when "00" => gpio_Data_Select(0) <= '1';
when "01" => gpio_OE_Select(0) <= '1';
when "10" => gpio_Data_Select(1) <= '1';
when "11" => gpio_OE_Select(1) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end process DUAL_REG_SELECT_PROCESS;
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
INPUT_DOUBLE_REGS4 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
INPUT_DOUBLE_REGS5 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO2_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO2_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio2_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO2_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 2 data from Bidirectional GPIO2 port
-- to GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio2_io_i_d1 <= GPIO2_IO_I;
-- gpio2_io_i_d2 <= gpio2_io_i_d1;
gpio2_Data_In <= gpio2_io_i_d2;
end if;
end process GPIO2_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS_0_0
---------------------------------------------------------------------------
-- Selects among Channel 1 GPIO_DATA ,GPIO_TRI and Channel 2 GPIO2_DATA
-- GPIO2_TRI REGISTERS for reading
---------------------------------------------------------------------------
READ_MUX_PROCESS_0_0 : process (gpio2_Data_In, gpio2_OE, gpio_Data_In,
gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
Read_Reg2_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
elsif gpio_Data_Select(1) = '1' then
Read_Reg2_In <= gpio2_Data_In;
elsif gpio_OE_Select(1) = '1' then
Read_Reg2_In <= gpio2_OE;
end if;
end process READ_MUX_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
---------------------------------------------------------------------------
-- GPIO2_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_Data_Out <= dout2_default_i;
elsif gpio_Data_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_Data_Out(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO2_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO2_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO2_OE_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_OE <= tri2_default_i;
elsif gpio_OE_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO2_OE_PROCESS_0_0;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
GPIO2_IO_O <= gpio2_Data_Out;
GPIO2_IO_T <= gpio2_OE;
---------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
---------------------------------------------------------------------------
gen_interrupt_dual : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
gpio2_data_in_xor <= gpio2_Data_In xor gpio2_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
or_ints2(0) <= or_reduce(gpio2_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XORs_INTRs : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
gpio2_data_in_xor_reg <= reset2_zeros;
GPIO_intr <= '0';
GPIO2_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
gpio2_data_in_xor_reg <= gpio2_data_in_xor;
GPIO_intr <= or_ints(0);
GPIO2_intr <= or_ints2(0);
end if;
end if;
end process REGISTER_XORs_INTRs;
end generate gen_interrupt_dual;
end generate Dual;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- gpio_core - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: gpio_core.vhd
-- Version: v1.01a
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
--
-------------------------------------------------------------------------------
--
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 09/15/09
-- ^^^^^^^^^^^^^^
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
-- Definition of Generics : --
-------------------------------------------------------------------------------
-- C_DW -- Data width of PLB BUS.
-- C_AW -- Address width of PLB BUS.
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_GPIO2_WIDTH -- GPIO2 Data Bus width.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-- C_FAMILY -- XILINX FPGA family
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports --
-------------------------------------------------------------------------------
-- Clk -- Input clock
-- Rst -- Reset
-- ABus_Reg -- Bus to IP address
-- BE_Reg -- Bus to IP byte enables
-- DBus_Reg -- Bus to IP data bus
-- RNW_Reg -- Bus to IP read write control
-- GPIO_DBus -- IP to Bus data bus
-- GPIO_xferAck -- GPIO transfer acknowledge
-- GPIO_intr -- GPIO channel 1 interrupt to IPIC
-- GPIO2_intr -- GPIO channel 2 interrupt to IPIC
-- GPIO_Select -- GPIO select
--
-- GPIO_IO_I -- Channel 1 General purpose I/O in port
-- GPIO_IO_O -- Channel 1 General purpose I/O out port
-- GPIO_IO_T -- Channel 1 General purpose I/O TRI-STATE control port
-- GPIO2_IO_I -- Channel 2 General purpose I/O in port
-- GPIO2_IO_O -- Channel 2 General purpose I/O out port
-- GPIO2_IO_T -- Channel 2 General purpose I/O TRI-STATE control port
-------------------------------------------------------------------------------
entity GPIO_Core is
generic
(
C_DW : integer := 32;
C_AW : integer := 32;
C_GPIO_WIDTH : integer := 32;
C_GPIO2_WIDTH : integer := 32;
C_MAX_GPIO_WIDTH : integer := 32;
C_INTERRUPT_PRESENT : integer := 0;
C_DOUT_DEFAULT : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_IS_DUAL : integer := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (0 to 31) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (0 to 31) := X"FFFF_FFFF";
C_FAMILY : string := "virtex7"
);
port
(
Clk : in std_logic;
Rst : in std_logic;
ABus_Reg : in std_logic_vector(0 to C_AW-1);
BE_Reg : in std_logic_vector(0 to C_DW/8-1);
DBus_Reg : in std_logic_vector(0 to C_MAX_GPIO_WIDTH-1);
RNW_Reg : in std_logic;
GPIO_DBus : out std_logic_vector(0 to C_DW-1);
GPIO_xferAck : out std_logic;
GPIO_intr : out std_logic;
GPIO2_intr : out std_logic;
GPIO_Select : in std_logic;
GPIO_IO_I : in std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_O : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO_IO_T : out std_logic_vector(0 to C_GPIO_WIDTH-1);
GPIO2_IO_I : in std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_O : out std_logic_vector(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T : out std_logic_vector(0 to C_GPIO2_WIDTH-1)
);
end entity GPIO_Core;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of GPIO_Core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes";
----------------------------------------------------------------------
-- Function for Reduction OR
----------------------------------------------------------------------
function or_reduce(l : std_logic_vector) return std_logic is
variable v : std_logic := '0';
begin
for i in l'range loop
v := v or l(i);
end loop;
return v;
end;
---------------------------------------------------------------------
-- End of Function
-------------------------------------------------------------------
signal gpio_Data_Select : std_logic_vector(0 to C_IS_DUAL);
signal gpio_OE_Select : std_logic_vector(0 to C_IS_DUAL);
signal Read_Reg_Rst : STD_LOGIC;
signal Read_Reg_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal Read_Reg_CE : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_Data_Out : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_DOUT_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal gpio_Data_In : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_in_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_io_i_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_OE : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_TRI_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1);
signal GPIO_DBus_i : std_logic_vector(0 to C_DW-1);
signal gpio_data_in_xor : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal gpio_data_in_xor_reg : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal or_ints : std_logic_vector(0 to 0);
signal or_ints2 : std_logic_vector(0 to 0);
signal iGPIO_xferAck : STD_LOGIC;
signal gpio_xferAck_Reg : STD_LOGIC;
signal dout_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal tri_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal reset_zeros : std_logic_vector(0 to C_GPIO_WIDTH-1);
signal dout2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal tri2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal reset2_zeros : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio_reg_en : std_logic;
begin -- architecture IMP
reset_zeros <= (others => '0');
reset2_zeros <= (others => '0');
TIE_DEFAULTS_GENERATE : if C_DW >= C_GPIO_WIDTH generate
SELECT_BITS_GENERATE : for i in 0 to C_GPIO_WIDTH-1 generate
dout_default_i(i) <= C_DOUT_DEFAULT(i-C_GPIO_WIDTH+C_DW);
tri_default_i(i) <= C_TRI_DEFAULT(i-C_GPIO_WIDTH+C_DW);
end generate SELECT_BITS_GENERATE;
end generate TIE_DEFAULTS_GENERATE;
TIE_DEFAULTS_2_GENERATE : if C_DW >= C_GPIO2_WIDTH generate
SELECT_BITS_2_GENERATE : for i in 0 to C_GPIO2_WIDTH-1 generate
dout2_default_i(i) <= C_DOUT_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
tri2_default_i(i) <= C_TRI_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW);
end generate SELECT_BITS_2_GENERATE;
end generate TIE_DEFAULTS_2_GENERATE;
Read_Reg_Rst <= iGPIO_xferAck or gpio_xferAck_Reg or (not GPIO_Select) or
(GPIO_Select and not RNW_Reg);
gpio_reg_en <= GPIO_Select when (ABus_Reg(0) = '0') else '0';
-----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
-----------------------------------------------------------------------------
XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
iGPIO_xferAck <= '0';
else
iGPIO_xferAck <= GPIO_Select and not gpio_xferAck_Reg;
if iGPIO_xferAck = '1' then
iGPIO_xferAck <= '0';
end if;
end if;
end if;
end process XFER_ACK_PROCESS;
-----------------------------------------------------------------------------
-- DELAYED_XFER_ACK_PROCESS
-----------------------------------------------------------------------------
-- Single Reg stage to make Transfer Ack period one clock pulse wide
-----------------------------------------------------------------------------
DELAYED_XFER_ACK_PROCESS : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_xferAck_Reg <= '0';
else
gpio_xferAck_Reg <= iGPIO_xferAck;
end if;
end if;
end process DELAYED_XFER_ACK_PROCESS;
GPIO_xferAck <= iGPIO_xferAck;
-----------------------------------------------------------------------------
-- Drive GPIO interrupts to '0' when interrupt not present
-----------------------------------------------------------------------------
DONT_GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
gpio_intr <= '0';
gpio2_intr <= '0';
end generate DONT_GEN_INTERRUPT;
----------------------------------------------------------------------------
-- When only one channel is used, the additional logic for the second
-- channel ports is not present
-----------------------------------------------------------------------------
Not_Dual : if (C_IS_DUAL = 0) generate
GPIO2_IO_O <= C_DOUT_DEFAULT(0 to C_GPIO2_WIDTH-1);
GPIO2_IO_T <= C_TRI_DEFAULT_2(0 to C_GPIO2_WIDTH-1);
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
----------------------------------------------------------------------------
-- XFER_ACK_PROCESS
----------------------------------------------------------------------------
-- Generation of Transfer Ack signal for one clock pulse
----------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
-----------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
-----------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I based on
-- the channel select signals
-----------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i;
-----------------------------------------------------------------------------
-- REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for single channel configuration
-----------------------------------------------------------------------------
--REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
begin
gpio_Data_Select(0) <= '0';
gpio_OE_Select(0) <= '0';
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
if (ABus_Reg(5) = '0') then
case ABus_Reg(6) is -- bit A29
when '0' => gpio_Data_Select(0) <= '1';
when '1' => gpio_OE_Select(0) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end if;
end process REG_SELECT_PROCESS;
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS
---------------------------------------------------------------------------
-- Selects GPIO_TRI control or GPIO_DATA Register to be read
---------------------------------------------------------------------------
READ_MUX_PROCESS : process (gpio_Data_In, gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
end if;
end process READ_MUX_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
----------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
----------------------------------------------------------------------------
-- When the C_INTERRUPT_PRESENT=1, the interrupt is driven based on whether
-- there is a change in the data coming in at the GPIO_IO_I port or GPIO_In
-- port
----------------------------------------------------------------------------
GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change on any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XOR_INTR : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
GPIO_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
GPIO_intr <= or_ints(0);
end if;
end if;
end process REGISTER_XOR_INTR;
gpio2_intr <= '0'; -- Channel 2 interrupt is driven low
end generate GEN_INTERRUPT;
end generate Not_Dual;
---)(------------------------------------------------------------------------
-- When both the channels are used, the additional logic for the second
-- channel ports
-----------------------------------------------------------------------------
Dual : if (C_IS_DUAL = 1) generate
signal gpio2_Data_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_in_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_io_i_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_data_in_xor_reg : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal gpio2_Data_Out : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_DOUT_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal gpio2_OE : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_TRI_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1);
signal Read_Reg2_In : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal Read_Reg2_CE : std_logic_vector(0 to C_GPIO2_WIDTH-1);
signal GPIO2_DBus_i : std_logic_vector(0 to C_DW-1);
begin
READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate
begin
--------------------------------------------------------------------------
-- GPIO_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL1 DATA BUS
--------------------------------------------------------------------------
GPIO_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0';
else
GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i);
end if;
end if;
end process;
end generate READ_REG_GEN;
TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate
GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0');
end generate TIE_DBUS_GENERATE;
READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate
--------------------------------------------------------------------------
-- GPIO2_DBUS_I_PROCESS
--------------------------------------------------------------------------
-- This process generates the GPIO CHANNEL2 DATA BUS
--------------------------------------------------------------------------
GPIO2_DBUS_I_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Read_Reg_Rst = '1' then
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0';
else
GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i);
end if;
end if;
end process;
end generate READ_REG2_GEN;
TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate
GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0');
end generate TIE_DBUS2_GENERATE;
---------------------------------------------------------------------------
-- GPIO_DBUS_PROCESS
---------------------------------------------------------------------------
-- This process generates the GPIO DATA BUS from the GPIO_DBUS_I and
-- GPIO2_DBUS_I based on which channel is selected
---------------------------------------------------------------------------
GPIO_DBus <= GPIO_DBus_i when (((gpio_Data_Select(0) = '1') or
(gpio_OE_Select(0) = '1')) and (RNW_Reg = '1'))
else GPIO2_DBus_i;
-----------------------------------------------------------------------------
-- DUAL_REG_SELECT_PROCESS
-----------------------------------------------------------------------------
-- GPIO REGISTER selection decoder for Dual channel configuration
-----------------------------------------------------------------------------
--DUAL_REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is
DUAL_REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is
variable ABus_reg_select : std_logic_vector(0 to 1);
begin
ABus_reg_select := ABus_Reg(5 to 6);
gpio_Data_Select <= (others => '0');
gpio_OE_Select <= (others => '0');
--if GPIO_Select = '1' then
if gpio_reg_en = '1' then
-- case ABus_Reg(28 to 29) is -- bit A28,A29 for dual
case ABus_reg_select is -- bit A28,A29 for dual
when "00" => gpio_Data_Select(0) <= '1';
when "01" => gpio_OE_Select(0) <= '1';
when "10" => gpio_Data_Select(1) <= '1';
when "11" => gpio_OE_Select(1) <= '1';
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end process DUAL_REG_SELECT_PROCESS;
---------------------------------------------------------------------------
-- GPIO_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 1 data from Bidirectional GPIO port
-- to GPIO_DATA REGISTER
---------------------------------------------------------------------------
INPUT_DOUBLE_REGS4 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio_io_i_d2
);
GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio_io_i_d1 <= GPIO_IO_I;
-- gpio_io_i_d2 <= gpio_io_i_d1;
gpio_Data_In <= gpio_io_i_d2;
end if;
end process GPIO_INDATA_BIRDIR_PROCESS;
INPUT_DOUBLE_REGS5 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_GPIO2_WIDTH,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => GPIO2_IO_I,
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => gpio2_io_i_d2
);
---------------------------------------------------------------------------
-- GPIO2_INDATA_BIRDIR_PROCESS
---------------------------------------------------------------------------
-- Reading of channel 2 data from Bidirectional GPIO2 port
-- to GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_INDATA_BIRDIR_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
-- gpio2_io_i_d1 <= GPIO2_IO_I;
-- gpio2_io_i_d2 <= gpio2_io_i_d1;
gpio2_Data_In <= gpio2_io_i_d2;
end if;
end process GPIO2_INDATA_BIRDIR_PROCESS;
---------------------------------------------------------------------------
-- READ_MUX_PROCESS_0_0
---------------------------------------------------------------------------
-- Selects among Channel 1 GPIO_DATA ,GPIO_TRI and Channel 2 GPIO2_DATA
-- GPIO2_TRI REGISTERS for reading
---------------------------------------------------------------------------
READ_MUX_PROCESS_0_0 : process (gpio2_Data_In, gpio2_OE, gpio_Data_In,
gpio_Data_Select, gpio_OE,
gpio_OE_Select) is
begin
Read_Reg_In <= (others => '0');
Read_Reg2_In <= (others => '0');
if gpio_Data_Select(0) = '1' then
Read_Reg_In <= gpio_Data_In;
elsif gpio_OE_Select(0) = '1' then
Read_Reg_In <= gpio_OE;
elsif gpio_Data_Select(1) = '1' then
Read_Reg2_In <= gpio2_Data_In;
elsif gpio_OE_Select(1) = '1' then
Read_Reg2_In <= gpio2_OE;
end if;
end process READ_MUX_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_DATA REGISTER
---------------------------------------------------------------------------
GPIO_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_Data_Out <= dout_default_i;
elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_Data_Out(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 1 GPIO_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO_OE_PROCESS : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio_OE <= tri_default_i;
elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO_WIDTH-1 loop
gpio_OE(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO_OE_PROCESS;
---------------------------------------------------------------------------
-- GPIO2_OUTDATA_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_DATA REGISTER
---------------------------------------------------------------------------
GPIO2_OUTDATA_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_Data_Out <= dout2_default_i;
elsif gpio_Data_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_Data_Out(i) <= DBus_Reg(i);
-- end if;
end loop;
end if;
end if;
end process GPIO2_OUTDATA_PROCESS_0_0;
---------------------------------------------------------------------------
-- GPIO2_OE_PROCESS_0_0
---------------------------------------------------------------------------
-- Writing to Channel 2 GPIO2_TRI Control REGISTER
---------------------------------------------------------------------------
GPIO2_OE_PROCESS_0_0 : process(Clk) is
begin
if Clk = '1' and Clk'EVENT then
if (Rst = '1') then
gpio2_OE <= tri2_default_i;
elsif gpio_OE_Select(1) = '1' and RNW_Reg = '0' then
for i in 0 to C_GPIO2_WIDTH-1 loop
gpio2_OE(i) <= DBus_Reg(i);
end loop;
end if;
end if;
end process GPIO2_OE_PROCESS_0_0;
GPIO_IO_O <= gpio_Data_Out;
GPIO_IO_T <= gpio_OE;
GPIO2_IO_O <= gpio2_Data_Out;
GPIO2_IO_T <= gpio2_OE;
---------------------------------------------------------------------------
-- INTERRUPT IS PRESENT
---------------------------------------------------------------------------
gen_interrupt_dual : if (C_INTERRUPT_PRESENT = 1) generate
gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2;
gpio2_data_in_xor <= gpio2_Data_In xor gpio2_io_i_d2;
-------------------------------------------------------------------------
-- An interrupt conditon exists if there is a change any bit.
-------------------------------------------------------------------------
or_ints(0) <= or_reduce(gpio_data_in_xor_reg);
or_ints2(0) <= or_reduce(gpio2_data_in_xor_reg);
-------------------------------------------------------------------------
-- Registering Interrupt condition
-------------------------------------------------------------------------
REGISTER_XORs_INTRs : process (Clk) is
begin
if (Clk'EVENT and Clk = '1') then
if (Rst = '1') then
gpio_data_in_xor_reg <= reset_zeros;
gpio2_data_in_xor_reg <= reset2_zeros;
GPIO_intr <= '0';
GPIO2_intr <= '0';
else
gpio_data_in_xor_reg <= gpio_data_in_xor;
gpio2_data_in_xor_reg <= gpio2_data_in_xor;
GPIO_intr <= or_ints(0);
GPIO2_intr <= or_ints2(0);
end if;
end if;
end process REGISTER_XORs_INTRs;
end generate gen_interrupt_dual;
end generate Dual;
end architecture IMP;
|
entity tb_top is
end tb_top;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_top is
signal clk : std_logic;
signal addr : std_logic_vector (1 downto 0);
signal data : std_logic_vector (2 downto 0);
begin
dut: entity work.top
port map (clk, addr, data);
process
procedure pulse is
begin
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
end pulse;
begin
clk <= '0';
addr <= "00";
pulse;
assert data = "001" severity failure;
addr <= "10";
pulse;
assert data = "100" severity failure;
wait;
end process;
end behav;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_reg_module.vhd
-- Description: This entity is AXI DMA Register Module Top Level
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_reg_module is
generic(
C_INCLUDE_MM2S : integer range 0 to 1 := 1 ;
C_INCLUDE_S2MM : integer range 0 to 1 := 1 ;
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
C_AXI_LITE_IS_ASYNC : integer range 0 to 1 := 0 ;
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 32 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 32 := 32 ;
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_MICRO_DMA : integer range 0 to 1 := 0 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
);
port (
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
m_axi_sg_hrdresetn : in std_logic ; --
--
s_axi_lite_aclk : in std_logic ; --
axi_lite_reset_n : in std_logic ; --
--
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
--
-- MM2S Signals --
mm2s_stop : in std_logic ; --
mm2s_halted_clr : in std_logic ; --
mm2s_halted_set : in std_logic ; --
mm2s_idle_set : in std_logic ; --
mm2s_idle_clr : in std_logic ; --
mm2s_dma_interr_set : in std_logic ; --
mm2s_dma_slverr_set : in std_logic ; --
mm2s_dma_decerr_set : in std_logic ; --
mm2s_ioc_irq_set : in std_logic ; --
mm2s_dly_irq_set : in std_logic ; --
mm2s_irqdelay_status : in std_logic_vector(7 downto 0) ; --
mm2s_irqthresh_status : in std_logic_vector(7 downto 0) ; --
mm2s_ftch_interr_set : in std_logic ; --
mm2s_ftch_slverr_set : in std_logic ; --
mm2s_ftch_decerr_set : in std_logic ; --
mm2s_updt_interr_set : in std_logic ; --
mm2s_updt_slverr_set : in std_logic ; --
mm2s_updt_decerr_set : in std_logic ; --
mm2s_new_curdesc_wren : in std_logic ; --
mm2s_new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_dlyirq_dsble : out std_logic ; -- CR605888 --
mm2s_irqthresh_rstdsbl : out std_logic ; -- CR572013 --
mm2s_irqthresh_wren : out std_logic ; --
mm2s_irqdelay_wren : out std_logic ; --
mm2s_tailpntr_updated : out std_logic ; --
mm2s_dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
mm2s_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_sa : out std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
mm2s_length_wren : out std_logic ; --
--
-- S2MM Signals --
tdest_in : in std_logic_vector (6 downto 0) ;
same_tdest_in : in std_logic;
sg_ctl : out std_logic_vector (7 downto 0) ;
s2mm_sof : in std_logic ;
s2mm_eof : in std_logic ;
s2mm_stop : in std_logic ; --
s2mm_halted_clr : in std_logic ; --
s2mm_halted_set : in std_logic ; --
s2mm_idle_set : in std_logic ; --
s2mm_idle_clr : in std_logic ; --
s2mm_dma_interr_set : in std_logic ; --
s2mm_dma_slverr_set : in std_logic ; --
s2mm_dma_decerr_set : in std_logic ; --
s2mm_ioc_irq_set : in std_logic ; --
s2mm_dly_irq_set : in std_logic ; --
s2mm_irqdelay_status : in std_logic_vector(7 downto 0) ; --
s2mm_irqthresh_status : in std_logic_vector(7 downto 0) ; --
s2mm_ftch_interr_set : in std_logic ; --
s2mm_ftch_slverr_set : in std_logic ; --
s2mm_ftch_decerr_set : in std_logic ; --
s2mm_updt_interr_set : in std_logic ; --
s2mm_updt_slverr_set : in std_logic ; --
s2mm_updt_decerr_set : in std_logic ; --
s2mm_new_curdesc_wren : in std_logic ; --
s2mm_new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_tvalid : in std_logic;
s2mm_dlyirq_dsble : out std_logic ; -- CR605888 --
s2mm_irqthresh_rstdsbl : out std_logic ; -- CR572013 --
s2mm_irqthresh_wren : out std_logic ; --
s2mm_irqdelay_wren : out std_logic ; --
s2mm_tailpntr_updated : out std_logic ; --
s2mm_tvalid_latch : out std_logic ;
s2mm_tvalid_latch_del : out std_logic ;
s2mm_dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s2mm_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_taildesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_da : out std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_length_wren : out std_logic ; --
s2mm_bytes_rcvd : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_bytes_rcvd_wren : in std_logic ; --
--
soft_reset : out std_logic ; --
soft_reset_clr : in std_logic ; --
--
-- Fetch/Update error addresses --
ftch_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_introut : out std_logic ; --
s2mm_introut : out std_logic --
);
end axi_dma_reg_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_reg_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant LENGTH_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH - C_SG_LENGTH_WIDTH;
constant LENGTH_PAD : std_logic_vector(LENGTH_PAD_WIDTH-1 downto 0) := (others => '0');
constant ZERO_BYTES : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
constant NUM_REG_PER_S2MM_INT : integer := NUM_REG_PER_CHANNEL + (NUM_REG_PER_S2MM*C_ENABLE_MULTI_CHANNEL);
-- Specifies to axi_dma_register which block belongs to S2MM channel
-- so simple dma s2mm_da register offset can be correctly assigned
-- CR603034
--constant NOT_S2MM_CHANNEL : integer := 0;
--constant IS_S2MM_CHANNEL : integer := 1;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal axi2ip_wrce : std_logic_vector(23+(120*C_ENABLE_MULTI_CHANNEL) - 1 downto 0) := (others => '0');
signal axi2ip_wrdata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_rdce : std_logic_vector(23+(120*C_ENABLE_MULTI_CHANNEL) - 1 downto 0) := (others => '0');
signal axi2ip_rdaddr : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ip2axi_rddata : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmacr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_dmasr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_curdesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_taildesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_sa_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_length_i : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_error_in : std_logic := '0';
signal mm2s_error_out : std_logic := '0';
signal s2mm_curdesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_curdesc_int2 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int2 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_taildesc_int3 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal s2mm_dmacr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_dmasr_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc1_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc1_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc1_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc1_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc2_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc2_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc2_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc2_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc3_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc3_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc3_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc3_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc4_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc4_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc4_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc4_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc5_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc5_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc5_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc5_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc6_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc6_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc6_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc6_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc7_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc7_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc7_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc7_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc8_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc8_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc8_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc8_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc9_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc9_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc9_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc9_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc10_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc10_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc10_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc10_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc11_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc11_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc11_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc11_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc12_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc12_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc12_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc12_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc13_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc13_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc13_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc13_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc14_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc14_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc14_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc14_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc15_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc15_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc15_lsb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc15_msb_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_lsb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_curdesc_msb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_lsb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_taildesc_msb_muxed : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_da_i : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_length_i : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_error_in : std_logic := '0';
signal s2mm_error_out : std_logic := '0';
signal read_addr : std_logic_vector(9 downto 0) := (others => '0');
signal mm2s_introut_i_cdc_from : std_logic := '0';
signal mm2s_introut_d1_cdc_tig : std_logic := '0';
signal mm2s_introut_to : std_logic := '0';
signal s2mm_introut_i_cdc_from : std_logic := '0';
signal s2mm_introut_d1_cdc_tig : std_logic := '0';
signal s2mm_introut_to : std_logic := '0';
signal mm2s_sgctl : std_logic_vector (7 downto 0);
signal s2mm_sgctl : std_logic_vector (7 downto 0);
signal or_sgctl : std_logic_vector (7 downto 0);
signal open_window, wren : std_logic;
signal s2mm_tailpntr_updated_int : std_logic;
signal s2mm_tailpntr_updated_int1 : std_logic;
signal s2mm_tailpntr_updated_int2 : std_logic;
signal s2mm_tailpntr_updated_int3 : std_logic;
signal tvalid_int : std_logic;
signal tvalid_int1 : std_logic;
signal tvalid_int2 : std_logic;
signal new_tdest : std_logic;
signal tvalid_latch : std_logic;
signal tdest_changed : std_logic;
signal tdest_fix : std_logic_vector (4 downto 0);
signal same_tdest_int1 : std_logic;
signal same_tdest_int2 : std_logic;
signal same_tdest_int3 : std_logic;
signal same_tdest_arrived : std_logic;
--ATTRIBUTE async_reg OF mm2s_introut_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_introut_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_introut_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_introut_to : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
or_sgctl <= mm2s_sgctl or s2mm_sgctl;
sg_ctl <= mm2s_sgctl or s2mm_sgctl;
mm2s_dmacr <= mm2s_dmacr_i; -- MM2S DMA Control Register
mm2s_dmasr <= mm2s_dmasr_i; -- MM2S DMA Status Register
mm2s_sa <= mm2s_sa_i; -- MM2S Source Address (Simple Only)
mm2s_length <= mm2s_length_i; -- MM2S Length (Simple Only)
s2mm_dmacr <= s2mm_dmacr_i; -- S2MM DMA Control Register
s2mm_dmasr <= s2mm_dmasr_i; -- S2MM DMA Status Register
s2mm_da <= s2mm_da_i; -- S2MM Destination Address (Simple Only)
s2mm_length <= s2mm_length_i; -- S2MM Length (Simple Only)
-- Soft reset set in mm2s DMACR or s2MM DMACR
soft_reset <= mm2s_dmacr_i(DMACR_RESET_BIT)
or s2mm_dmacr_i(DMACR_RESET_BIT);
-- CR572013 - added to match legacy SDMA operation
mm2s_irqthresh_rstdsbl <= not mm2s_dmacr_i(DMACR_DLY_IRQEN_BIT);
s2mm_irqthresh_rstdsbl <= not s2mm_dmacr_i(DMACR_DLY_IRQEN_BIT);
--GEN_S2MM_TDEST : if (C_NUM_S2MM_CHANNELS > 1) generate
GEN_S2MM_TDEST : if (C_ENABLE_MULTI_CHANNEL = 1 and C_INCLUDE_S2MM = 1) generate
begin
PROC_WREN : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
s2mm_taildesc_int3 <= (others => '0');
s2mm_tailpntr_updated_int <= '0';
s2mm_tailpntr_updated_int2 <= '0';
s2mm_tailpntr_updated <= '0';
else -- (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- s2mm_tailpntr_updated_int <= new_tdest or same_tdest_arrived;
-- s2mm_tailpntr_updated_int2 <= s2mm_tailpntr_updated_int;
-- s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int2;
-- Commenting this code as it is causing SG to start early
s2mm_tailpntr_updated_int <= new_tdest or s2mm_tailpntr_updated_int1 or same_tdest_arrived;
s2mm_tailpntr_updated_int2 <= s2mm_tailpntr_updated_int;
s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int2;
end if;
end if;
end process PROC_WREN;
-- this is always '1' as MCH needs to have all desc reg programmed before hand
--s2mm_tailpntr_updated_int3_i <= s2mm_tailpntr_updated_int2_i and (not s2mm_tailpntr_updated_int_i); -- and tvalid_latch;
tdest_fix <= "11111";
new_tdest <= tvalid_int1 xor tvalid_int2;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
tvalid_int <= '0';
tvalid_int1 <= '0';
tvalid_int2 <= '0';
tvalid_latch <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
tvalid_int <= tdest_in (6); --s2mm_tvalid;
tvalid_int1 <= tvalid_int;
tvalid_int2 <= tvalid_int1;
s2mm_tvalid_latch_del <= tvalid_latch;
if (new_tdest = '1') then
tvalid_latch <= '0';
else
tvalid_latch <= '1';
end if;
end if;
end if;
end process;
-- will trigger tailptrupdtd and it will then get SG out of pause
same_tdest_arrived <= same_tdest_int2 xor same_tdest_int3;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
same_tdest_int1 <= '0';
same_tdest_int2 <= '0';
same_tdest_int3 <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
same_tdest_int1 <= same_tdest_in;
same_tdest_int2 <= same_tdest_int1;
same_tdest_int3 <= same_tdest_int2;
end if;
end if;
end process;
-- process (m_axi_sg_aclk)
-- begin
-- if (m_axi_sg_aresetn = '0') then
-- tvalid_int <= '0';
-- tvalid_int1 <= '0';
-- tvalid_latch <= '0';
-- tdest_in_int <= (others => '0');
-- elsif (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- tvalid_int <= s2mm_tvalid;
-- tvalid_int1 <= tvalid_int;
-- tdest_in_int <= tdest_in;
-- -- if (tvalid_int1 = '1' and (tdest_in_int /= tdest_in)) then
-- if (tvalid_int1 = '1' and tdest_in_int = "00000" and (tdest_in_int = tdest_in)) then
-- tvalid_latch <= '1';
-- elsif (tvalid_int1 = '1' and (tdest_in_int /= tdest_in)) then
-- tvalid_latch <= '0';
-- elsif (tvalid_int1 = '1' and (tdest_in_int = tdest_in)) then
-- tvalid_latch <= '1';
-- end if;
-- end if;
-- end process;
s2mm_tvalid_latch <= tvalid_latch;
PROC_TDEST_IN : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
s2mm_curdesc_int2 <= (others => '0');
s2mm_taildesc_int2 <= (others => '0');
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
s2mm_curdesc_int2 <= s2mm_curdesc_int;
s2mm_taildesc_int2 <= s2mm_taildesc_int;
end if;
end if;
end process PROC_TDEST_IN;
s2mm_curdesc <= s2mm_curdesc_int2;
s2mm_taildesc <= s2mm_taildesc_int2;
end generate GEN_S2MM_TDEST;
GEN_S2MM_NO_TDEST : if (C_ENABLE_MULTI_CHANNEL = 0) generate
--GEN_S2MM_NO_TDEST : if (C_NUM_S2MM_CHANNELS = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
begin
s2mm_tailpntr_updated <= s2mm_tailpntr_updated_int1;
s2mm_curdesc <= s2mm_curdesc_int;
s2mm_taildesc <= s2mm_taildesc_int;
s2mm_tvalid_latch <= '1';
s2mm_tvalid_latch_del <= '1';
end generate GEN_S2MM_NO_TDEST;
-- For 32 bit address map only lsb registers out
GEN_DESC_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
mm2s_curdesc <= mm2s_curdesc_lsb_i;
mm2s_taildesc <= mm2s_taildesc_lsb_i;
s2mm_curdesc_int <= s2mm_curdesc_lsb_muxed;
s2mm_taildesc_int <= s2mm_taildesc_lsb_muxed;
end generate GEN_DESC_ADDR_EQL32;
-- For 64 bit address map lsb and msb registers out
GEN_DESC_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
mm2s_curdesc <= mm2s_curdesc_msb_i & mm2s_curdesc_lsb_i;
mm2s_taildesc <= mm2s_taildesc_msb_i & mm2s_taildesc_lsb_i;
s2mm_curdesc_int <= s2mm_curdesc_msb_muxed & s2mm_curdesc_lsb_muxed;
s2mm_taildesc_int <= s2mm_taildesc_msb_muxed & s2mm_taildesc_lsb_muxed;
end generate GEN_DESC_ADDR_EQL64;
-------------------------------------------------------------------------------
-- Generate AXI Lite Inteface
-------------------------------------------------------------------------------
GEN_AXI_LITE_IF : if C_INCLUDE_MM2S = 1 or C_INCLUDE_S2MM = 1 generate
begin
AXI_LITE_IF_I : entity axi_dma_v7_1.axi_dma_lite_if
generic map(
C_NUM_CE => 23+(120*C_ENABLE_MULTI_CHANNEL) ,
C_AXI_LITE_IS_ASYNC => C_AXI_LITE_IS_ASYNC ,
C_S_AXI_LITE_ADDR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH
)
port map(
ip2axi_aclk => m_axi_sg_aclk ,
ip2axi_aresetn => m_axi_sg_hrdresetn ,
s_axi_lite_aclk => s_axi_lite_aclk ,
s_axi_lite_aresetn => axi_lite_reset_n ,
-- AXI Lite Write Address Channel
s_axi_lite_awvalid => s_axi_lite_awvalid ,
s_axi_lite_awready => s_axi_lite_awready ,
s_axi_lite_awaddr => s_axi_lite_awaddr ,
-- AXI Lite Write Data Channel
s_axi_lite_wvalid => s_axi_lite_wvalid ,
s_axi_lite_wready => s_axi_lite_wready ,
s_axi_lite_wdata => s_axi_lite_wdata ,
-- AXI Lite Write Response Channel
s_axi_lite_bresp => s_axi_lite_bresp ,
s_axi_lite_bvalid => s_axi_lite_bvalid ,
s_axi_lite_bready => s_axi_lite_bready ,
-- AXI Lite Read Address Channel
s_axi_lite_arvalid => s_axi_lite_arvalid ,
s_axi_lite_arready => s_axi_lite_arready ,
s_axi_lite_araddr => s_axi_lite_araddr ,
s_axi_lite_rvalid => s_axi_lite_rvalid ,
s_axi_lite_rready => s_axi_lite_rready ,
s_axi_lite_rdata => s_axi_lite_rdata ,
s_axi_lite_rresp => s_axi_lite_rresp ,
-- User IP Interface
axi2ip_wrce => axi2ip_wrce ,
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_rdce => open ,
axi2ip_rdaddr => axi2ip_rdaddr ,
ip2axi_rddata => ip2axi_rddata
);
end generate GEN_AXI_LITE_IF;
-------------------------------------------------------------------------------
-- No channels therefore do not generate an AXI Lite interface
-------------------------------------------------------------------------------
GEN_NO_AXI_LITE_IF : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 0 generate
begin
s_axi_lite_awready <= '0';
s_axi_lite_wready <= '0';
s_axi_lite_bresp <= (others => '0');
s_axi_lite_bvalid <= '0';
s_axi_lite_arready <= '0';
s_axi_lite_rvalid <= '0';
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rresp <= (others => '0');
end generate GEN_NO_AXI_LITE_IF;
-------------------------------------------------------------------------------
-- Generate MM2S Registers if included
-------------------------------------------------------------------------------
GEN_MM2S_REGISTERS : if C_INCLUDE_MM2S = 1 generate
begin
I_MM2S_DMA_REGISTER : entity axi_dma_v7_1.axi_dma_register
generic map (
C_NUM_REGISTERS => NUM_REG_PER_CHANNEL ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
-- C_NUM_S2MM_CHANNELS => 1 --C_S2MM_NUM_CHANNELS
--C_CHANNEL_IS_S2MM => NOT_S2MM_CHANNEL CR603034
)
port map(
-- Secondary Clock / Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- CPU Write Control (via AXI Lite)
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_wrce => axi2ip_wrce
(RESERVED_2C_INDEX
downto MM2S_DMACR_INDEX),
--(MM2S_LENGTH_INDEX
-- DMASR Register bit control/status
stop_dma => mm2s_stop ,
halted_clr => mm2s_halted_clr ,
halted_set => mm2s_halted_set ,
idle_set => mm2s_idle_set ,
idle_clr => mm2s_idle_clr ,
ioc_irq_set => mm2s_ioc_irq_set ,
dly_irq_set => mm2s_dly_irq_set ,
irqdelay_status => mm2s_irqdelay_status ,
irqthresh_status => mm2s_irqthresh_status ,
-- SG Error Control
ftch_interr_set => mm2s_ftch_interr_set ,
ftch_slverr_set => mm2s_ftch_slverr_set ,
ftch_decerr_set => mm2s_ftch_decerr_set ,
ftch_error_addr => ftch_error_addr ,
updt_interr_set => mm2s_updt_interr_set ,
updt_slverr_set => mm2s_updt_slverr_set ,
updt_decerr_set => mm2s_updt_decerr_set ,
updt_error_addr => updt_error_addr ,
dma_interr_set => mm2s_dma_interr_set ,
dma_slverr_set => mm2s_dma_slverr_set ,
dma_decerr_set => mm2s_dma_decerr_set ,
irqthresh_wren => mm2s_irqthresh_wren ,
irqdelay_wren => mm2s_irqdelay_wren ,
dlyirq_dsble => mm2s_dlyirq_dsble , -- CR605888
error_in => s2mm_error_out ,
error_out => mm2s_error_out ,
introut => mm2s_introut_i_cdc_from ,
soft_reset_in => s2mm_dmacr_i(DMACR_RESET_BIT),
soft_reset_clr => soft_reset_clr ,
-- CURDESC Update
update_curdesc => mm2s_new_curdesc_wren ,
new_curdesc => mm2s_new_curdesc ,
-- TAILDESC Update
tailpntr_updated => mm2s_tailpntr_updated ,
-- Channel Registers
sg_ctl => mm2s_sgctl ,
dmacr => mm2s_dmacr_i ,
dmasr => mm2s_dmasr_i ,
curdesc_lsb => mm2s_curdesc_lsb_i ,
curdesc_msb => mm2s_curdesc_msb_i ,
taildesc_lsb => mm2s_taildesc_lsb_i ,
taildesc_msb => mm2s_taildesc_msb_i ,
-- curdesc1_lsb => open ,
-- curdesc1_msb => open ,
-- taildesc1_lsb => open ,
-- taildesc1_msb => open ,
-- curdesc2_lsb => open ,
-- curdesc2_msb => open ,
-- taildesc2_lsb => open ,
-- taildesc2_msb => open ,
--
-- curdesc3_lsb => open ,
-- curdesc3_msb => open ,
-- taildesc3_lsb => open ,
-- taildesc3_msb => open ,
--
-- curdesc4_lsb => open ,
-- curdesc4_msb => open ,
-- taildesc4_lsb => open ,
-- taildesc4_msb => open ,
--
-- curdesc5_lsb => open ,
-- curdesc5_msb => open ,
-- taildesc5_lsb => open ,
-- taildesc5_msb => open ,
--
-- curdesc6_lsb => open ,
-- curdesc6_msb => open ,
-- taildesc6_lsb => open ,
-- taildesc6_msb => open ,
--
-- curdesc7_lsb => open ,
-- curdesc7_msb => open ,
-- taildesc7_lsb => open ,
-- taildesc7_msb => open ,
--
-- curdesc8_lsb => open ,
-- curdesc8_msb => open ,
-- taildesc8_lsb => open ,
-- taildesc8_msb => open ,
--
-- curdesc9_lsb => open ,
-- curdesc9_msb => open ,
-- taildesc9_lsb => open ,
-- taildesc9_msb => open ,
--
-- curdesc10_lsb => open ,
-- curdesc10_msb => open ,
-- taildesc10_lsb => open ,
-- taildesc10_msb => open ,
--
-- curdesc11_lsb => open ,
-- curdesc11_msb => open ,
-- taildesc11_lsb => open ,
-- taildesc11_msb => open ,
--
-- curdesc12_lsb => open ,
-- curdesc12_msb => open ,
-- taildesc12_lsb => open ,
-- taildesc12_msb => open ,
--
-- curdesc13_lsb => open ,
-- curdesc13_msb => open ,
-- taildesc13_lsb => open ,
-- taildesc13_msb => open ,
--
-- curdesc14_lsb => open ,
-- curdesc14_msb => open ,
-- taildesc14_lsb => open ,
-- taildesc14_msb => open ,
--
--
-- curdesc15_lsb => open ,
-- curdesc15_msb => open ,
-- taildesc15_lsb => open ,
-- taildesc15_msb => open ,
--
-- tdest_in => "00000" ,
buffer_address => mm2s_sa_i ,
buffer_length => mm2s_length_i ,
buffer_length_wren => mm2s_length_wren ,
bytes_received => ZERO_BYTES , -- Not used on transmit
bytes_received_wren => '0' -- Not used on transmit
);
-- If async clocks then cross interrupt out to AXI Lite clock domain
GEN_INTROUT_ASYNC : if C_AXI_LITE_IS_ASYNC = 1 generate
begin
PROC_REG_INTR2LITE : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_introut_i_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => mm2s_introut_to,
scndry_vect_out => open
);
-- PROC_REG_INTR2LITE : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- -- if(axi_lite_reset_n = '0')then
-- -- mm2s_introut_d1_cdc_tig <= '0';
-- -- mm2s_introut_to <= '0';
-- -- else
-- mm2s_introut_d1_cdc_tig <= mm2s_introut_i_cdc_from;
-- mm2s_introut_to <= mm2s_introut_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process PROC_REG_INTR2LITE;
mm2s_introut <= mm2s_introut_to;
end generate GEN_INTROUT_ASYNC;
-- If sync then simply pass out
GEN_INTROUT_SYNC : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
mm2s_introut <= mm2s_introut_i_cdc_from;
end generate GEN_INTROUT_SYNC;
end generate GEN_MM2S_REGISTERS;
-------------------------------------------------------------------------------
-- Tie MM2S Register outputs to zero if excluded
-------------------------------------------------------------------------------
GEN_NO_MM2S_REGISTERS : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_dmacr_i <= (others => '0');
mm2s_dmasr_i <= (others => '0');
mm2s_curdesc_lsb_i <= (others => '0');
mm2s_curdesc_msb_i <= (others => '0');
mm2s_taildesc_lsb_i <= (others => '0');
mm2s_taildesc_msb_i <= (others => '0');
mm2s_tailpntr_updated <= '0';
mm2s_sa_i <= (others => '0');
mm2s_length_i <= (others => '0');
mm2s_length_wren <= '0';
mm2s_irqthresh_wren <= '0';
mm2s_irqdelay_wren <= '0';
mm2s_tailpntr_updated <= '0';
mm2s_introut <= '0';
mm2s_sgctl <= (others => '0');
mm2s_dlyirq_dsble <= '0';
end generate GEN_NO_MM2S_REGISTERS;
-------------------------------------------------------------------------------
-- Generate S2MM Registers if included
-------------------------------------------------------------------------------
GEN_S2MM_REGISTERS : if C_INCLUDE_S2MM = 1 generate
begin
I_S2MM_DMA_REGISTER : entity axi_dma_v7_1.axi_dma_register_s2mm
generic map (
C_NUM_REGISTERS => NUM_REG_PER_S2MM_INT, --NUM_REG_TOTAL, --NUM_REG_PER_CHANNEL ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_S_AXI_LITE_DATA_WIDTH => C_S_AXI_LITE_DATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
--C_CHANNEL_IS_S2MM => IS_S2MM_CHANNEL CR603034
)
port map(
-- Secondary Clock / Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- CPU Write Control (via AXI Lite)
axi2ip_wrdata => axi2ip_wrdata ,
axi2ip_wrce => axi2ip_wrce
((23+(120*C_ENABLE_MULTI_CHANNEL)-1)
downto RESERVED_2C_INDEX) ,
-- downto S2MM_DMACR_INDEX),
--S2MM_LENGTH_INDEX
-- DMASR Register bit control/status
stop_dma => s2mm_stop ,
halted_clr => s2mm_halted_clr ,
halted_set => s2mm_halted_set ,
idle_set => s2mm_idle_set ,
idle_clr => s2mm_idle_clr ,
ioc_irq_set => s2mm_ioc_irq_set ,
dly_irq_set => s2mm_dly_irq_set ,
irqdelay_status => s2mm_irqdelay_status ,
irqthresh_status => s2mm_irqthresh_status ,
-- SG Error Control
dma_interr_set => s2mm_dma_interr_set ,
dma_slverr_set => s2mm_dma_slverr_set ,
dma_decerr_set => s2mm_dma_decerr_set ,
ftch_interr_set => s2mm_ftch_interr_set ,
ftch_slverr_set => s2mm_ftch_slverr_set ,
ftch_decerr_set => s2mm_ftch_decerr_set ,
ftch_error_addr => ftch_error_addr ,
updt_interr_set => s2mm_updt_interr_set ,
updt_slverr_set => s2mm_updt_slverr_set ,
updt_decerr_set => s2mm_updt_decerr_set ,
updt_error_addr => updt_error_addr ,
irqthresh_wren => s2mm_irqthresh_wren ,
irqdelay_wren => s2mm_irqdelay_wren ,
dlyirq_dsble => s2mm_dlyirq_dsble , -- CR605888
error_in => mm2s_error_out ,
error_out => s2mm_error_out ,
introut => s2mm_introut_i_cdc_from ,
soft_reset_in => mm2s_dmacr_i(DMACR_RESET_BIT),
soft_reset_clr => soft_reset_clr ,
-- CURDESC Update
update_curdesc => s2mm_new_curdesc_wren ,
new_curdesc => s2mm_new_curdesc ,
-- TAILDESC Update
tailpntr_updated => s2mm_tailpntr_updated_int1 ,
-- Channel Registers
sg_ctl => s2mm_sgctl ,
dmacr => s2mm_dmacr_i ,
dmasr => s2mm_dmasr_i ,
curdesc_lsb => s2mm_curdesc_lsb_i ,
curdesc_msb => s2mm_curdesc_msb_i ,
taildesc_lsb => s2mm_taildesc_lsb_i ,
taildesc_msb => s2mm_taildesc_msb_i ,
curdesc1_lsb => s2mm_curdesc1_lsb_i ,
curdesc1_msb => s2mm_curdesc1_msb_i ,
taildesc1_lsb => s2mm_taildesc1_lsb_i ,
taildesc1_msb => s2mm_taildesc1_msb_i ,
curdesc2_lsb => s2mm_curdesc2_lsb_i ,
curdesc2_msb => s2mm_curdesc2_msb_i ,
taildesc2_lsb => s2mm_taildesc2_lsb_i ,
taildesc2_msb => s2mm_taildesc2_msb_i ,
curdesc3_lsb => s2mm_curdesc3_lsb_i ,
curdesc3_msb => s2mm_curdesc3_msb_i ,
taildesc3_lsb => s2mm_taildesc3_lsb_i ,
taildesc3_msb => s2mm_taildesc3_msb_i ,
curdesc4_lsb => s2mm_curdesc4_lsb_i ,
curdesc4_msb => s2mm_curdesc4_msb_i ,
taildesc4_lsb => s2mm_taildesc4_lsb_i ,
taildesc4_msb => s2mm_taildesc4_msb_i ,
curdesc5_lsb => s2mm_curdesc5_lsb_i ,
curdesc5_msb => s2mm_curdesc5_msb_i ,
taildesc5_lsb => s2mm_taildesc5_lsb_i ,
taildesc5_msb => s2mm_taildesc5_msb_i ,
curdesc6_lsb => s2mm_curdesc6_lsb_i ,
curdesc6_msb => s2mm_curdesc6_msb_i ,
taildesc6_lsb => s2mm_taildesc6_lsb_i ,
taildesc6_msb => s2mm_taildesc6_msb_i ,
curdesc7_lsb => s2mm_curdesc7_lsb_i ,
curdesc7_msb => s2mm_curdesc7_msb_i ,
taildesc7_lsb => s2mm_taildesc7_lsb_i ,
taildesc7_msb => s2mm_taildesc7_msb_i ,
curdesc8_lsb => s2mm_curdesc8_lsb_i ,
curdesc8_msb => s2mm_curdesc8_msb_i ,
taildesc8_lsb => s2mm_taildesc8_lsb_i ,
taildesc8_msb => s2mm_taildesc8_msb_i ,
curdesc9_lsb => s2mm_curdesc9_lsb_i ,
curdesc9_msb => s2mm_curdesc9_msb_i ,
taildesc9_lsb => s2mm_taildesc9_lsb_i ,
taildesc9_msb => s2mm_taildesc9_msb_i ,
curdesc10_lsb => s2mm_curdesc10_lsb_i ,
curdesc10_msb => s2mm_curdesc10_msb_i ,
taildesc10_lsb => s2mm_taildesc10_lsb_i ,
taildesc10_msb => s2mm_taildesc10_msb_i ,
curdesc11_lsb => s2mm_curdesc11_lsb_i ,
curdesc11_msb => s2mm_curdesc11_msb_i ,
taildesc11_lsb => s2mm_taildesc11_lsb_i ,
taildesc11_msb => s2mm_taildesc11_msb_i ,
curdesc12_lsb => s2mm_curdesc12_lsb_i ,
curdesc12_msb => s2mm_curdesc12_msb_i ,
taildesc12_lsb => s2mm_taildesc12_lsb_i ,
taildesc12_msb => s2mm_taildesc12_msb_i ,
curdesc13_lsb => s2mm_curdesc13_lsb_i ,
curdesc13_msb => s2mm_curdesc13_msb_i ,
taildesc13_lsb => s2mm_taildesc13_lsb_i ,
taildesc13_msb => s2mm_taildesc13_msb_i ,
curdesc14_lsb => s2mm_curdesc14_lsb_i ,
curdesc14_msb => s2mm_curdesc14_msb_i ,
taildesc14_lsb => s2mm_taildesc14_lsb_i ,
taildesc14_msb => s2mm_taildesc14_msb_i ,
curdesc15_lsb => s2mm_curdesc15_lsb_i ,
curdesc15_msb => s2mm_curdesc15_msb_i ,
taildesc15_lsb => s2mm_taildesc15_lsb_i ,
taildesc15_msb => s2mm_taildesc15_msb_i ,
tdest_in => tdest_in (5 downto 0) ,
buffer_address => s2mm_da_i ,
buffer_length => s2mm_length_i ,
buffer_length_wren => s2mm_length_wren ,
bytes_received => s2mm_bytes_rcvd ,
bytes_received_wren => s2mm_bytes_rcvd_wren
);
GEN_DESC_MUX_SINGLE_CH : if C_NUM_S2MM_CHANNELS = 1 generate
begin
s2mm_curdesc_lsb_muxed <= s2mm_curdesc_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc_msb_i;
end generate GEN_DESC_MUX_SINGLE_CH;
GEN_DESC_MUX : if C_NUM_S2MM_CHANNELS > 1 generate
begin
PROC_DESC_SEL : process (tdest_in, s2mm_curdesc_lsb_i,s2mm_curdesc_msb_i, s2mm_taildesc_lsb_i, s2mm_taildesc_msb_i,
s2mm_curdesc1_lsb_i,s2mm_curdesc1_msb_i, s2mm_taildesc1_lsb_i, s2mm_taildesc1_msb_i,
s2mm_curdesc2_lsb_i,s2mm_curdesc2_msb_i, s2mm_taildesc2_lsb_i, s2mm_taildesc2_msb_i,
s2mm_curdesc3_lsb_i,s2mm_curdesc3_msb_i, s2mm_taildesc3_lsb_i, s2mm_taildesc3_msb_i,
s2mm_curdesc4_lsb_i,s2mm_curdesc4_msb_i, s2mm_taildesc4_lsb_i, s2mm_taildesc4_msb_i,
s2mm_curdesc5_lsb_i,s2mm_curdesc5_msb_i, s2mm_taildesc5_lsb_i, s2mm_taildesc5_msb_i,
s2mm_curdesc6_lsb_i,s2mm_curdesc6_msb_i, s2mm_taildesc6_lsb_i, s2mm_taildesc6_msb_i,
s2mm_curdesc7_lsb_i,s2mm_curdesc7_msb_i, s2mm_taildesc7_lsb_i, s2mm_taildesc7_msb_i,
s2mm_curdesc8_lsb_i,s2mm_curdesc8_msb_i, s2mm_taildesc8_lsb_i, s2mm_taildesc8_msb_i,
s2mm_curdesc9_lsb_i,s2mm_curdesc9_msb_i, s2mm_taildesc9_lsb_i, s2mm_taildesc9_msb_i,
s2mm_curdesc10_lsb_i,s2mm_curdesc10_msb_i, s2mm_taildesc10_lsb_i, s2mm_taildesc10_msb_i,
s2mm_curdesc11_lsb_i,s2mm_curdesc11_msb_i, s2mm_taildesc11_lsb_i, s2mm_taildesc11_msb_i,
s2mm_curdesc12_lsb_i,s2mm_curdesc12_msb_i, s2mm_taildesc12_lsb_i, s2mm_taildesc12_msb_i,
s2mm_curdesc13_lsb_i,s2mm_curdesc13_msb_i, s2mm_taildesc13_lsb_i, s2mm_taildesc13_msb_i,
s2mm_curdesc14_lsb_i,s2mm_curdesc14_msb_i, s2mm_taildesc14_lsb_i, s2mm_taildesc14_msb_i,
s2mm_curdesc15_lsb_i,s2mm_curdesc15_msb_i, s2mm_taildesc15_lsb_i, s2mm_taildesc15_msb_i
)
begin
case tdest_in (3 downto 0) is
when "0000" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc_msb_i;
when "0001" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc1_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc1_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc1_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc1_msb_i;
when "0010" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc2_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc2_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc2_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc2_msb_i;
when "0011" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc3_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc3_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc3_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc3_msb_i;
when "0100" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc4_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc4_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc4_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc4_msb_i;
when "0101" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc5_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc5_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc5_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc5_msb_i;
when "0110" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc6_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc6_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc6_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc6_msb_i;
when "0111" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc7_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc7_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc7_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc7_msb_i;
when "1000" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc8_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc8_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc8_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc8_msb_i;
when "1001" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc9_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc9_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc9_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc9_msb_i;
when "1010" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc10_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc10_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc10_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc10_msb_i;
when "1011" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc11_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc11_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc11_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc11_msb_i;
when "1100" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc12_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc12_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc12_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc12_msb_i;
when "1101" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc13_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc13_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc13_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc13_msb_i;
when "1110" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc14_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc14_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc14_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc14_msb_i;
when "1111" =>
s2mm_curdesc_lsb_muxed <= s2mm_curdesc15_lsb_i;
s2mm_curdesc_msb_muxed <= s2mm_curdesc15_msb_i;
s2mm_taildesc_lsb_muxed <= s2mm_taildesc15_lsb_i;
s2mm_taildesc_msb_muxed <= s2mm_taildesc15_msb_i;
when others =>
s2mm_curdesc_lsb_muxed <= (others => '0');
s2mm_curdesc_msb_muxed <= (others => '0');
s2mm_taildesc_lsb_muxed <= (others => '0');
s2mm_taildesc_msb_muxed <= (others => '0');
end case;
end process PROC_DESC_SEL;
end generate GEN_DESC_MUX;
-- If async clocks then cross interrupt out to AXI Lite clock domain
GEN_INTROUT_ASYNC : if C_AXI_LITE_IS_ASYNC = 1 generate
begin
-- Cross interrupt out to AXI Lite clock domain
PROC_REG_INTR2LITE : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_introut_i_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => s2mm_introut_to,
scndry_vect_out => open
);
-- PROC_REG_INTR2LITE : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(axi_lite_reset_n = '0')then
-- s2mm_introut_d1_cdc_tig <= '0';
-- s2mm_introut_to <= '0';
-- else
-- s2mm_introut_d1_cdc_tig <= s2mm_introut_i_cdc_from;
-- s2mm_introut_to <= s2mm_introut_d1_cdc_tig;
-- end if;
-- end if;
-- end process PROC_REG_INTR2LITE;
s2mm_introut <= s2mm_introut_to;
end generate GEN_INTROUT_ASYNC;
-- If sync then simply pass out
GEN_INTROUT_SYNC : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
s2mm_introut <= s2mm_introut_i_cdc_from;
end generate GEN_INTROUT_SYNC;
end generate GEN_S2MM_REGISTERS;
-------------------------------------------------------------------------------
-- Tie S2MM Register outputs to zero if excluded
-------------------------------------------------------------------------------
GEN_NO_S2MM_REGISTERS : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_dmacr_i <= (others => '0');
s2mm_dmasr_i <= (others => '0');
s2mm_curdesc_lsb_i <= (others => '0');
s2mm_curdesc_msb_i <= (others => '0');
s2mm_taildesc_lsb_i <= (others => '0');
s2mm_taildesc_msb_i <= (others => '0');
s2mm_da_i <= (others => '0');
s2mm_length_i <= (others => '0');
s2mm_length_wren <= '0';
s2mm_tailpntr_updated <= '0';
s2mm_introut <= '0';
s2mm_irqthresh_wren <= '0';
s2mm_irqdelay_wren <= '0';
s2mm_tailpntr_updated <= '0';
s2mm_dlyirq_dsble <= '0';
s2mm_tailpntr_updated_int1 <= '0';
s2mm_sgctl <= (others => '0');
end generate GEN_NO_S2MM_REGISTERS;
-------------------------------------------------------------------------------
-- AXI LITE READ MUX
-------------------------------------------------------------------------------
read_addr <= axi2ip_rdaddr(9 downto 0);
-- Generate read mux for Scatter Gather Mode
GEN_READ_MUX_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
mm2s_dmacr_i ,
mm2s_dmasr_i ,
mm2s_curdesc_lsb_i ,
mm2s_curdesc_msb_i ,
mm2s_taildesc_lsb_i ,
mm2s_taildesc_msb_i ,
s2mm_dmacr_i ,
s2mm_dmasr_i ,
s2mm_curdesc_lsb_i ,
s2mm_curdesc_msb_i ,
s2mm_taildesc_lsb_i ,
s2mm_taildesc_msb_i ,
s2mm_curdesc1_lsb_i ,
s2mm_curdesc1_msb_i ,
s2mm_taildesc1_lsb_i ,
s2mm_taildesc1_msb_i ,
s2mm_curdesc2_lsb_i ,
s2mm_curdesc2_msb_i ,
s2mm_taildesc2_lsb_i ,
s2mm_taildesc2_msb_i ,
s2mm_curdesc3_lsb_i ,
s2mm_curdesc3_msb_i ,
s2mm_taildesc3_lsb_i ,
s2mm_taildesc3_msb_i ,
s2mm_curdesc4_lsb_i ,
s2mm_curdesc4_msb_i ,
s2mm_taildesc4_lsb_i ,
s2mm_taildesc4_msb_i ,
s2mm_curdesc5_lsb_i ,
s2mm_curdesc5_msb_i ,
s2mm_taildesc5_lsb_i ,
s2mm_taildesc5_msb_i ,
s2mm_curdesc6_lsb_i ,
s2mm_curdesc6_msb_i ,
s2mm_taildesc6_lsb_i ,
s2mm_taildesc6_msb_i ,
s2mm_curdesc7_lsb_i ,
s2mm_curdesc7_msb_i ,
s2mm_taildesc7_lsb_i ,
s2mm_taildesc7_msb_i ,
s2mm_curdesc8_lsb_i ,
s2mm_curdesc8_msb_i ,
s2mm_taildesc8_lsb_i ,
s2mm_taildesc8_msb_i ,
s2mm_curdesc9_lsb_i ,
s2mm_curdesc9_msb_i ,
s2mm_taildesc9_lsb_i ,
s2mm_taildesc9_msb_i ,
s2mm_curdesc10_lsb_i ,
s2mm_curdesc10_msb_i ,
s2mm_taildesc10_lsb_i ,
s2mm_taildesc10_msb_i ,
s2mm_curdesc11_lsb_i ,
s2mm_curdesc11_msb_i ,
s2mm_taildesc11_lsb_i ,
s2mm_taildesc11_msb_i ,
s2mm_curdesc12_lsb_i ,
s2mm_curdesc12_msb_i ,
s2mm_taildesc12_lsb_i ,
s2mm_taildesc12_msb_i ,
s2mm_curdesc13_lsb_i ,
s2mm_curdesc13_msb_i ,
s2mm_taildesc13_lsb_i ,
s2mm_taildesc13_msb_i ,
s2mm_curdesc14_lsb_i ,
s2mm_curdesc14_msb_i ,
s2mm_taildesc14_lsb_i ,
s2mm_taildesc14_msb_i ,
s2mm_curdesc15_lsb_i ,
s2mm_curdesc15_msb_i ,
s2mm_taildesc15_lsb_i ,
s2mm_taildesc15_msb_i ,
or_sgctl
)
begin
case read_addr is
when MM2S_DMACR_OFFSET =>
ip2axi_rddata <= mm2s_dmacr_i;
when MM2S_DMASR_OFFSET =>
ip2axi_rddata <= mm2s_dmasr_i;
when MM2S_CURDESC_LSB_OFFSET =>
ip2axi_rddata <= mm2s_curdesc_lsb_i;
when MM2S_CURDESC_MSB_OFFSET =>
ip2axi_rddata <= mm2s_curdesc_msb_i;
when MM2S_TAILDESC_LSB_OFFSET =>
ip2axi_rddata <= mm2s_taildesc_lsb_i;
when MM2S_TAILDESC_MSB_OFFSET =>
ip2axi_rddata <= mm2s_taildesc_msb_i;
when SGCTL_OFFSET =>
ip2axi_rddata <= x"00000" & or_sgctl (7 downto 4) & "0000" & or_sgctl (3 downto 0);
when S2MM_DMACR_OFFSET =>
ip2axi_rddata <= s2mm_dmacr_i;
when S2MM_DMASR_OFFSET =>
ip2axi_rddata <= s2mm_dmasr_i;
when S2MM_CURDESC_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc_lsb_i;
when S2MM_CURDESC_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc_msb_i;
when S2MM_TAILDESC_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc_lsb_i;
when S2MM_TAILDESC_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc_msb_i;
when S2MM_CURDESC1_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc1_lsb_i;
when S2MM_CURDESC1_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc1_msb_i;
when S2MM_TAILDESC1_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc1_lsb_i;
when S2MM_TAILDESC1_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc1_msb_i;
when S2MM_CURDESC2_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc2_lsb_i;
when S2MM_CURDESC2_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc2_msb_i;
when S2MM_TAILDESC2_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc2_lsb_i;
when S2MM_TAILDESC2_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc2_msb_i;
when S2MM_CURDESC3_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc3_lsb_i;
when S2MM_CURDESC3_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc3_msb_i;
when S2MM_TAILDESC3_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc3_lsb_i;
when S2MM_TAILDESC3_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc3_msb_i;
when S2MM_CURDESC4_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc4_lsb_i;
when S2MM_CURDESC4_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc4_msb_i;
when S2MM_TAILDESC4_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc4_lsb_i;
when S2MM_TAILDESC4_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc4_msb_i;
when S2MM_CURDESC5_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc5_lsb_i;
when S2MM_CURDESC5_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc5_msb_i;
when S2MM_TAILDESC5_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc5_lsb_i;
when S2MM_TAILDESC5_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc5_msb_i;
when S2MM_CURDESC6_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc6_lsb_i;
when S2MM_CURDESC6_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc6_msb_i;
when S2MM_TAILDESC6_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc6_lsb_i;
when S2MM_TAILDESC6_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc6_msb_i;
when S2MM_CURDESC7_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc7_lsb_i;
when S2MM_CURDESC7_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc7_msb_i;
when S2MM_TAILDESC7_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc7_lsb_i;
when S2MM_TAILDESC7_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc7_msb_i;
when S2MM_CURDESC8_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc8_lsb_i;
when S2MM_CURDESC8_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc8_msb_i;
when S2MM_TAILDESC8_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc8_lsb_i;
when S2MM_TAILDESC8_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc8_msb_i;
when S2MM_CURDESC9_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc9_lsb_i;
when S2MM_CURDESC9_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc9_msb_i;
when S2MM_TAILDESC9_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc9_lsb_i;
when S2MM_TAILDESC9_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc9_msb_i;
when S2MM_CURDESC10_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc10_lsb_i;
when S2MM_CURDESC10_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc10_msb_i;
when S2MM_TAILDESC10_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc10_lsb_i;
when S2MM_TAILDESC10_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc10_msb_i;
when S2MM_CURDESC11_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc11_lsb_i;
when S2MM_CURDESC11_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc11_msb_i;
when S2MM_TAILDESC11_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc11_lsb_i;
when S2MM_TAILDESC11_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc11_msb_i;
when S2MM_CURDESC12_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc12_lsb_i;
when S2MM_CURDESC12_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc12_msb_i;
when S2MM_TAILDESC12_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc12_lsb_i;
when S2MM_TAILDESC12_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc12_msb_i;
when S2MM_CURDESC13_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc13_lsb_i;
when S2MM_CURDESC13_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc13_msb_i;
when S2MM_TAILDESC13_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc13_lsb_i;
when S2MM_TAILDESC13_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc13_msb_i;
when S2MM_CURDESC14_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc14_lsb_i;
when S2MM_CURDESC14_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc14_msb_i;
when S2MM_TAILDESC14_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc14_lsb_i;
when S2MM_TAILDESC14_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc14_msb_i;
when S2MM_CURDESC15_LSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc15_lsb_i;
when S2MM_CURDESC15_MSB_OFFSET =>
ip2axi_rddata <= s2mm_curdesc15_msb_i;
when S2MM_TAILDESC15_LSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc15_lsb_i;
when S2MM_TAILDESC15_MSB_OFFSET =>
ip2axi_rddata <= s2mm_taildesc15_msb_i;
-- coverage off
when others =>
ip2axi_rddata <= (others => '0');
-- coverage on
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_FOR_SG;
-- Generate read mux for Simple DMA Mode
GEN_READ_MUX_FOR_SMPL_DMA : if C_INCLUDE_SG = 0 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
mm2s_dmacr_i ,
mm2s_dmasr_i ,
mm2s_sa_i ,
mm2s_length_i ,
s2mm_dmacr_i ,
s2mm_dmasr_i ,
s2mm_da_i ,
s2mm_length_i
)
begin
case read_addr is
when MM2S_DMACR_OFFSET =>
ip2axi_rddata <= mm2s_dmacr_i;
when MM2S_DMASR_OFFSET =>
ip2axi_rddata <= mm2s_dmasr_i;
when MM2S_SA_OFFSET =>
ip2axi_rddata <= mm2s_sa_i;
when MM2S_LENGTH_OFFSET =>
ip2axi_rddata <= LENGTH_PAD & mm2s_length_i;
when S2MM_DMACR_OFFSET =>
ip2axi_rddata <= s2mm_dmacr_i;
when S2MM_DMASR_OFFSET =>
ip2axi_rddata <= s2mm_dmasr_i;
when S2MM_DA_OFFSET =>
ip2axi_rddata <= s2mm_da_i;
when S2MM_LENGTH_OFFSET =>
ip2axi_rddata <= LENGTH_PAD & s2mm_length_i;
when others =>
ip2axi_rddata <= (others => '0');
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_FOR_SMPL_DMA;
end implementation;
|
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity add16 is
port (X,Y : in std_logic_vector(15 downto 0);
Z : out std_logic_vector(15 downto 0));
end add16;
architecture Logic of add16 is
signal C : std_logic_vector(4 downto 0);
begin
C(0)<='0';
adx : for i in 0 to 3 generate
ADD_COMP : add4 port map(X((i*4)+3 downto i*4),Y((i*4)+3 downto i*4),C(i),Z((i*4)+3 downto i*4),C(i+1));
end generate adx;
end Logic; |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity add16 is
port (X,Y : in std_logic_vector(15 downto 0);
Z : out std_logic_vector(15 downto 0));
end add16;
architecture Logic of add16 is
signal C : std_logic_vector(4 downto 0);
begin
C(0)<='0';
adx : for i in 0 to 3 generate
ADD_COMP : add4 port map(X((i*4)+3 downto i*4),Y((i*4)+3 downto i*4),C(i),Z((i*4)+3 downto i*4),C(i+1));
end generate adx;
end Logic; |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity add16 is
port (X,Y : in std_logic_vector(15 downto 0);
Z : out std_logic_vector(15 downto 0));
end add16;
architecture Logic of add16 is
signal C : std_logic_vector(4 downto 0);
begin
C(0)<='0';
adx : for i in 0 to 3 generate
ADD_COMP : add4 port map(X((i*4)+3 downto i*4),Y((i*4)+3 downto i*4),C(i),Z((i*4)+3 downto i*4),C(i+1));
end generate adx;
end Logic; |
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity add16 is
port (X,Y : in std_logic_vector(15 downto 0);
Z : out std_logic_vector(15 downto 0));
end add16;
architecture Logic of add16 is
signal C : std_logic_vector(4 downto 0);
begin
C(0)<='0';
adx : for i in 0 to 3 generate
ADD_COMP : add4 port map(X((i*4)+3 downto i*4),Y((i*4)+3 downto i*4),C(i),Z((i*4)+3 downto i*4),C(i+1));
end generate adx;
end Logic; |
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: Elmer Homero
--
-- Create Date: 10:59:30 08/26/2015
-- Design Name:
-- Module Name: Dec_Binary_7Seg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Binary to 7-segment decoder using behavioral
-- description
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Dec_Binary_7Seg is
Port ( D : in STD_LOGIC;
C : in STD_LOGIC;
B : in STD_LOGIC;
A : in STD_LOGIC;
Seg : out STD_LOGIC_VECTOR (7 downto 0);
Disp : out STD_LOGIC_VECTOR (3 downto 0));
end Dec_Binary_7Seg;
architecture Behavioral of Dec_Binary_7Seg is
-- Embedded signals declaration
signal Ent: STD_LOGIC_VECTOR (3 downto 0);
begin
-- Behavioral Concurrent implementation using When / Else
--.gfedcba
-- Seg <= "11000000" when (D='0' and C='0' and B='0' and A='0') else -- 0
-- "11111001" when (D='0' and C='0' and B='0' and A='1') else -- 1
-- "10100100" when (D='0' and C='0' and B='1' and A='0') else -- 2
-- "10110000" when (D='0' and C='0' and B='1' and A='1') else -- 3
-- "10011001" when (D='0' and C='1' and B='0' and A='0') else -- 4
-- "10010010" when (D='0' and C='1' and B='0' and A='1') else -- 5
-- "10000010" when (D='0' and C='1' and B='1' and A='0') else -- 6
-- "11111000" when (D='0' and C='1' and B='1' and A='1') else -- 7
-- "10000000" when (D='1' and C='0' and B='0' and A='0') else -- 8
-- "10010000" when (D='1' and C='0' and B='0' and A='1') else -- 9
-- "10001000" when (D='1' and C='0' and B='1' and A='0') else -- A
-- "10000011" when (D='1' and C='0' and B='1' and A='1') else -- b
-- "11000110" when (D='1' and C='1' and B='0' and A='0') else -- C
-- "10100001" when (D='1' and C='1' and B='0' and A='1') else -- d
-- "10000110" when (D='1' and C='1' and B='1' and A='0') else -- E
-- "10001110"; -- F
-- Behavioral Concurrent implementation using When / Else
-- using embedded signals
-- Group input signals into a vector using aggregate
-- Ent <= D & C & B & A;
-- --.gfedcba
-- Seg <= "11000000" when (Ent = "0000") else -- 0
-- "11111001" when (Ent = "0001") else -- 1
-- "10100100" when (Ent = "0010") else -- 2
-- "10110000" when (Ent = "0011") else -- 3
-- "10011001" when (Ent = "0100") else -- 4
-- "10010010" when (Ent = "0101") else -- 5
-- "10000010" when (Ent = "0110") else -- 6
-- "11111000" when (Ent = "0111") else -- 7
-- "10000000" when (Ent = "1000") else -- 8
-- "10010000" when (Ent = "1001") else -- 9
-- "10001000" when (Ent = "1010") else -- A
-- "10000011" when (Ent = "1011") else -- b
-- "11000110" when (Ent = "1100") else -- C
-- "10100001" when (Ent = "1101") else -- d
-- "10000110" when (Ent = "1110") else -- E
-- "10001110"; -- F
-- Behavioral Concurrent implementation using Select / When
-- using embedded signals
-- Group input signals into a vector using aggregate
-- Ent <= D & C & B & A;
--
-- with Ent select
-- Seg <= "11000000" when "0000",
-- "11111001" when "0001",
-- "10100100" when "0010",
-- "10110000" when "0011",
-- "10011001" when "0100",
-- "10010010" when "0101",
-- "10000010" when "0110",
-- "11111000" when "0111",
-- "10000000" when "1000",
-- "10010000" when "1001",
-- "10001000" when "1010",
-- "10000011" when "1011",
-- "11000110" when "1100",
-- "10100001" when "1101",
-- "10000110" when "1110",
-- "10001110" when others;
--
-- -- Select Display
-- Disp <= "1110";
-- Behavioral Concurrent implementation using Select / When
-- using embedded signals
-- Group input signals into a vector using aggregate
-- Ent <= D & C & B & A;
--
-- with Ent select
-- --.gfedcba
-- Seg <= "11000000" when x"0",
-- "11111001" when x"1",
-- "10100100" when x"2",
-- "10110000" when x"3",
-- "10011001" when x"4",
-- "10010010" when x"5",
-- "10000010" when x"6",
-- "11111000" when x"7",
-- "10000000" when x"8",
-- "10010000" when x"9",
-- "10001000" when x"A",
-- "10000011" when x"B",
-- "11000110" when x"C",
-- "10100001" when x"D",
-- "10000110" when x"E",
-- "10001110" when others;
-- Select Display
-- Disp <= "1110";
-- Behavioral Sequential implementation using
-- if / else / elsif and using embedded signals
-- Group input signals into a vector using aggregate
Ent <= D & C & B & A;
decoder: process(Ent)
begin --.gfedcba
if Ent = x"0" then Seg <= "11000000";
elsif Ent = x"1" then Seg <= "11111001";
elsif Ent = x"2" then Seg <= "10100100";
elsif Ent = x"3" then Seg <= "10110000";
elsif Ent = x"4" then Seg <= "10011001";
elsif Ent = x"5" then Seg <= "10010010";
elsif Ent = x"6" then Seg <= "10000010";
elsif Ent = x"7" then Seg <= "11111000";
elsif Ent = x"8" then Seg <= "10000000";
elsif Ent = x"9" then Seg <= "10010000";
elsif Ent = x"A" then Seg <= "10001000";
elsif Ent = x"B" then Seg <= "10000011";
elsif Ent = x"C" then Seg <= "11000110";
elsif Ent = x"D" then Seg <= "10100001";
elsif Ent = x"E" then Seg <= "10000110";
else Seg <= "10001110";
end if;
end process decoder;
-- Select Display
Disp <= "1110";
--
-- Behavioral Sequential implementation using
-- the Case statement and using embedded signals
-- Group input signals into a vector using aggregate
-- Ent <= D & C & B & A;
--
-- decodercase: process(Ent)
-- begin
-- case (Ent) is
-- when "0000" => Seg <= "11000000";
-- when "0001" => Seg <= "11111001";
-- when "0010" => Seg <= "10100100";
-- when "0011" => Seg <= "10110000";
-- when "0100" => Seg <= "10011001";
-- when "0101" =>
-- <statement>;
-- when "0110" =>
-- <statement>;
-- when "0111" =>
-- <statement>;
-- when "1000" =>
-- <statement>;
-- when "1001" =>
-- <statement>;
-- when "1010" =>
-- <statement>;
-- when "1011" =>
-- <statement>;
-- when "1100" =>
-- <statement>;
-- when "1101" =>
-- <statement>;
-- when "1110" =>
-- <statement>;
-- when others => Seg <= "10001110";
-- end case;
-- end process decodercase;
-- Select Display--
-- Disp <= "1110";
end Behavioral;
|
--------------------------------------------------------------------------------
-- MIPS I CPU - Functions --
--------------------------------------------------------------------------------
-- Copyright (C)2011 Mathias Hörtnagl <[email protected]> --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mips1.all;
use work.tcpu.all;
package fcpu is
-----------------------------------------------------------------------------
-- ALU --
-----------------------------------------------------------------------------
function addsub (l,r : std_logic_vector; op : alu_op_t)
return std_logic_vector;
function fslt (l,r : std_logic_vector) return std_logic_vector;
function fsltu (l,r : std_logic_vector) return std_logic_vector;
function fsll (l,s : std_logic_vector) return std_logic_vector;
function fsrl (l,s : std_logic_vector) return std_logic_vector;
function fsra (l,s : std_logic_vector) return std_logic_vector;
-----------------------------------------------------------------------------
-- Extend --
-----------------------------------------------------------------------------
function zext (a : std_logic_vector; l : integer) return std_logic_vector;
function sext (a : std_logic_vector; l : integer) return std_logic_vector;
-----------------------------------------------------------------------------
-- Decode --
-----------------------------------------------------------------------------
function link (v_i : de_t) return de_t;
function load (v_i : de_t) return de_t;
function store (v_i : de_t) return de_t;
function simm (v_i : de_t) return de_t;
function zimm (v_i : de_t) return de_t;
-----------------------------------------------------------------------------
-- Clear Pipeline --
-----------------------------------------------------------------------------
function clear (v_i : fe_t) return fe_t;
function clear (v_i : de_t) return de_t;
function clear (v_i : ex_t) return ex_t;
function clear (v_i : me_t) return me_t;
-----------------------------------------------------------------------------
-- Co-Processor 0 --
-----------------------------------------------------------------------------
function clear (v_i : cp0_t) return cp0_t;
function push_ie(v_i : cp0_t) return cp0_t;
function pop_ie(v_i : cp0_t) return cp0_t;
--function set_sr(v_i : cp0_t; v_j : comb_cp0_t) return cp0_t;
function get_sr(v_i : cp0_t) return std_logic_vector;
end fcpu;
package body fcpu is
-----------------------------------------------------------------------------
-- Adder/Subtractor (signed) --
-----------------------------------------------------------------------------
-- Compound Adder/Subtractor (saves LUTs).
function addsub (l,r : std_logic_vector; op : alu_op_t)
return std_logic_vector is
begin
case op is
when ADD | ADDU => return std_logic_vector(signed(l) + signed(r));
when others => return std_logic_vector(signed(l) - signed(r));
end case;
end addsub;
-----------------------------------------------------------------------------
-- Set Less Than Functions --
-----------------------------------------------------------------------------
function fslt (l,r : std_logic_vector) return std_logic_vector is
variable o : std_logic_vector(l'length-1 downto 0) := (others => '0');
begin
if signed(l) < signed(r) then o(0) := '1'; end if;
return o;
end fslt;
function fsltu (l,r : std_logic_vector) return std_logic_vector is
variable o : std_logic_vector(l'length-1 downto 0) := (others => '0');
begin
if unsigned(l) < unsigned(r) then o(0) := '1'; end if;
return o;
end fsltu;
-----------------------------------------------------------------------------
-- Shift (Left, Right Logic, Right Arithmetic) --
-----------------------------------------------------------------------------
function fsll (l,s : std_logic_vector) return std_logic_vector is
variable sh : natural range 0 to l'length-1;
begin
sh := to_integer(unsigned(s));
return std_logic_vector(shift_left(unsigned(l), sh));
end fsll;
function fsrl (l,s : std_logic_vector) return std_logic_vector is
variable sh : natural range 0 to l'length-1;
begin
sh := to_integer(unsigned(s));
return std_logic_vector(shift_right(unsigned(l), sh));
end fsrl;
function fsra (l,s : std_logic_vector) return std_logic_vector is
variable sh : natural range 0 to l'length-1;
begin
sh := to_integer(unsigned(s));
return std_logic_vector(shift_right(signed(l), sh));
end fsra;
-----------------------------------------------------------------------------
-- Extend --
-----------------------------------------------------------------------------
-- Zero extend vector.
function zext (a : std_logic_vector; l : integer) return std_logic_vector is
begin
return std_logic_vector(resize(unsigned(a), l));
end zext;
-- Sign extend vector.
function sext (a : std_logic_vector; l : integer) return std_logic_vector is
begin
return std_logic_vector(resize(signed(a), l));
end sext;
-----------------------------------------------------------------------------
-- Decode --
-----------------------------------------------------------------------------
-- JAL, JRAL, BGEZAL, BLTZAL operations.
function link (v_i : de_t) return de_t is
variable v : de_t := v_i;
begin
v.ec.alu.op := ADDU;
v.ec.alu.src.a := ADD_4;
v.ec.alu.src.b := PC;
v.wc.we := '1';
return v;
end link;
-- Memory load operation setter.
function load (v_i : de_t) return de_t is
variable v : de_t := v_i;
begin
v.ec.wbr := RT;
v.ec.alu.op := ADDU;
v.ec.alu.src.b := SIGN;
v.mc.src := MEM;
v.wc.we := '1';
return v;
end load;
-- Memory store operation setter.
function store (v_i : de_t) return de_t is
variable v : de_t := v_i;
begin
v.ec.alu.op := ADDU;
v.ec.alu.src.b := SIGN;
v.mc.mem.we := '1';
return v;
end store;
-- Sign immediate operation setter.
function simm (v_i : de_t) return de_t is
variable v : de_t := v_i;
begin
v.ec.wbr := RT;
v.ec.alu.src.b := SIGN;
v.wc.we := '1';
return v;
end simm;
-- Zero immediate operation setter.
function zimm (v_i : de_t) return de_t is
variable v : de_t := v_i;
begin
v.ec.wbr := RT;
v.ec.alu.src.b := ZERO;
v.wc.we := '1';
return v;
end zimm;
-----------------------------------------------------------------------------
-- Clear Pipeline --
-----------------------------------------------------------------------------
function clear (v_i : fe_t) return fe_t is
variable v : fe_t := v_i;
begin
v.pc := (others => '0');
return v;
end clear;
function clear (v_i : de_t) return de_t is
variable v : de_t := v_i;
begin
v.cc.mtsr := false;
v.cc.rfe := false;
v.ec.jmp.op := NOP;
v.mc.mem.we := '0';
v.mc.mem.byt := NONE;
v.wc.we := '0';
return v;
end clear;
function clear (v_i : ex_t) return ex_t is
variable v : ex_t := v_i;
begin
v.f.jmp := '0';
v.mc.mem.we := '0';
v.mc.mem.byt := NONE;
v.wc.we := '0';
return v;
end clear;
function clear (v_i : me_t) return me_t is
variable v : me_t := v_i;
begin
v.wc.we := '0';
return v;
end clear;
-----------------------------------------------------------------------------
-- Co-Processor 0 --
-----------------------------------------------------------------------------
-- Clear CP0 status register.
function clear (v_i : cp0_t) return cp0_t is
variable v : cp0_t := v_i;
begin
v.sr.im := x"00";
v.sr.iec := '0';
v.sr.iep := '0';
v.sr.ieo := '0';
return v;
end clear;
-- Push interrupt enable stack.
function push_ie(v_i : cp0_t) return cp0_t is
variable v : cp0_t := v_i;
begin
v.sr.ieo := v_i.sr.iep;
v.sr.iep := v_i.sr.iec;
v.sr.iec := '0';
return v;
end push_ie;
-- Pop interrupt enable stack.
function pop_ie(v_i : cp0_t) return cp0_t is
variable v : cp0_t := v_i;
begin
v.sr.iec := v_i.sr.iep;
v.sr.iep := v_i.sr.ieo;
return v;
end pop_ie;
-- Get status register.
function get_sr(v_i : cp0_t) return std_logic_vector is
variable v : std_logic_vector(31 downto 0) := (others => '0');
begin
v(15 downto 8) := v_i.sr.im;
v(0) := v_i.sr.iec;
v(2) := v_i.sr.iep;
v(4) := v_i.sr.ieo;
return v;
end get_sr;
end fcpu; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library WORK;
use WORK.CONSTANTS.ALL;
use WORK.FUNCTIONS.ALL;
entity Zoom is
Port ( bleft : in STD_LOGIC;
bright : in STD_LOGIC;
bup : in STD_LOGIC;
bdwn : in STD_LOGIC;
bctr : in STD_LOGIC;
clock : in STD_LOGIC;
reset : in STD_LOGIC;
ce_param : in std_logic;
x_start : out STD_LOGIC_VECTOR(XY_RANGE-1 downto 0);
y_start : out STD_LOGIC_VECTOR(XY_RANGE-1 downto 0);
step : out STD_LOGIC_VECTOR(XY_RANGE-1 downto 0));
end Zoom;
architecture Behavioral of Zoom is
signal s_xstart, s_ystart, s_step : signed(XY_RANGE-1 downto 0);
begin
process(clock, ce_param, reset, bup, bdwn, bleft, bright, bctr)
begin
if reset = '1' then
s_xstart <= x"E0000000";
s_ystart <= x"F0000000";
s_step <= x"00111111"; --Mandelbrot -2 1 x -1 1 sur 640x480
elsif ((rising_edge(clock)) and (ce_param='1')) then -- TODO : Centrer le zoom
if bctr = '1' then
if bup = '1' then
s_xstart <= s_xstart + (mult(s_step srl 2,x"28000000",FIXED) sll 8);
s_ystart <= s_ystart + (mult(s_step srl 2,x"1E000000",FIXED) sll 8);
s_step <= s_step srl 1; --Zoom x2> réduction du step
elsif bdwn = '1' then
s_xstart <= s_xstart + not (mult(s_step srl 1,x"28000000",FIXED) sll 8) + 1;
s_ystart <= s_ystart + not (mult(s_step srl 1,x"1E000000",FIXED) sll 8) +1;
s_step <= s_step sll 1; --Dezoom x0.5> augmentation du step
end if;
elsif bup = '1' then
s_ystart <= s_ystart + (s_step sll 7);
elsif bdwn = '1' then
s_ystart <= s_ystart - (s_step sll 7);
end if;
if bleft = '1' then
s_xstart <= s_xstart + (s_step sll 7);
elsif bright = '1' then
s_xstart <= s_xstart - (s_step sll 7);
end if;
end if;
end process;
x_start <= STD_LOGIC_VECTOR(s_xstart);
y_start <= STD_LOGIC_VECTOR(s_ystart);
step <= STD_LOGIC_VECTOR(s_step);
end Behavioral;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:34:06 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_mid/bg_mid_sim_netlist.vhdl
-- Design : bg_mid
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid_bindec is
port (
ena_array : out STD_LOGIC_VECTOR ( 4 downto 0 );
addra : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_mid_bindec : entity is "bindec";
end bg_mid_bindec;
architecture STRUCTURE of bg_mid_bindec is
begin
ENOUT: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => addra(2),
I1 => addra(0),
I2 => addra(1),
O => ena_array(0)
);
\ENOUT__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addra(2),
I1 => addra(0),
I2 => addra(1),
O => ena_array(1)
);
\ENOUT__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addra(0),
I1 => addra(1),
I2 => addra(2),
O => ena_array(2)
);
\ENOUT__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => addra(1),
I1 => addra(0),
I2 => addra(2),
O => ena_array(3)
);
\ENOUT__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => addra(0),
I1 => addra(2),
I2 => addra(1),
O => ena_array(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid_blk_mem_gen_mux is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
DOADO : in STD_LOGIC_VECTOR ( 7 downto 0 );
addra : in STD_LOGIC_VECTOR ( 2 downto 0 );
clka : in STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\ : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_mid_blk_mem_gen_mux : entity is "blk_mem_gen_mux";
end bg_mid_blk_mem_gen_mux;
architecture STRUCTURE of bg_mid_blk_mem_gen_mux is
signal \douta[10]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[10]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[11]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[11]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[4]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[5]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[6]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[7]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[8]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[8]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \douta[9]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \douta[9]_INST_0_i_2_n_0\ : STD_LOGIC;
signal sel_pipe : STD_LOGIC_VECTOR ( 2 downto 0 );
signal sel_pipe_d1 : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
\douta[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FF0400"
)
port map (
I0 => sel_pipe_d1(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(0),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_0\(0),
O => douta(0)
);
\douta[10]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[10]_INST_0_i_1_n_0\,
I1 => \douta[10]_INST_0_i_2_n_0\,
O => douta(10),
S => sel_pipe_d1(2)
);
\douta[10]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(6),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(6),
O => \douta[10]_INST_0_i_1_n_0\
);
\douta[10]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(0),
I1 => DOADO(6),
I2 => sel_pipe_d1(1),
O => \douta[10]_INST_0_i_2_n_0\
);
\douta[11]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[11]_INST_0_i_1_n_0\,
I1 => \douta[11]_INST_0_i_2_n_0\,
O => douta(11),
S => sel_pipe_d1(2)
);
\douta[11]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(7),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(7),
O => \douta[11]_INST_0_i_1_n_0\
);
\douta[11]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(0),
I1 => DOADO(7),
I2 => sel_pipe_d1(1),
O => \douta[11]_INST_0_i_2_n_0\
);
\douta[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FF0400"
)
port map (
I0 => sel_pipe_d1(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(1),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_1\(0),
O => douta(1)
);
\douta[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FF0400"
)
port map (
I0 => sel_pipe_d1(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(2),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_2\(0),
O => douta(2)
);
\douta[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"04FF0400"
)
port map (
I0 => sel_pipe_d1(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(3),
I2 => sel_pipe_d1(1),
I3 => sel_pipe_d1(2),
I4 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_3\(0),
O => douta(3)
);
\douta[4]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[4]_INST_0_i_1_n_0\,
I1 => \douta[4]_INST_0_i_2_n_0\,
O => douta(4),
S => sel_pipe_d1(2)
);
\douta[4]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(0),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(0),
O => \douta[4]_INST_0_i_1_n_0\
);
\douta[4]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(0),
I1 => DOADO(0),
I2 => sel_pipe_d1(1),
O => \douta[4]_INST_0_i_2_n_0\
);
\douta[5]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[5]_INST_0_i_1_n_0\,
I1 => \douta[5]_INST_0_i_2_n_0\,
O => douta(5),
S => sel_pipe_d1(2)
);
\douta[5]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(1),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(1),
O => \douta[5]_INST_0_i_1_n_0\
);
\douta[5]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(0),
I1 => DOADO(1),
I2 => sel_pipe_d1(1),
O => \douta[5]_INST_0_i_2_n_0\
);
\douta[6]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[6]_INST_0_i_1_n_0\,
I1 => \douta[6]_INST_0_i_2_n_0\,
O => douta(6),
S => sel_pipe_d1(2)
);
\douta[6]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(2),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(2),
O => \douta[6]_INST_0_i_1_n_0\
);
\douta[6]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(0),
I1 => DOADO(2),
I2 => sel_pipe_d1(1),
O => \douta[6]_INST_0_i_2_n_0\
);
\douta[7]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[7]_INST_0_i_1_n_0\,
I1 => \douta[7]_INST_0_i_2_n_0\,
O => douta(7),
S => sel_pipe_d1(2)
);
\douta[7]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(3),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(3),
O => \douta[7]_INST_0_i_1_n_0\
);
\douta[7]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(0),
I1 => DOADO(3),
I2 => sel_pipe_d1(1),
O => \douta[7]_INST_0_i_2_n_0\
);
\douta[8]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[8]_INST_0_i_1_n_0\,
I1 => \douta[8]_INST_0_i_2_n_0\,
O => douta(8),
S => sel_pipe_d1(2)
);
\douta[8]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(4),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(4),
O => \douta[8]_INST_0_i_1_n_0\
);
\douta[8]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(0),
I1 => DOADO(4),
I2 => sel_pipe_d1(1),
O => \douta[8]_INST_0_i_2_n_0\
);
\douta[9]_INST_0\: unisim.vcomponents.MUXF7
port map (
I0 => \douta[9]_INST_0_i_1_n_0\,
I1 => \douta[9]_INST_0_i_2_n_0\,
O => douta(9),
S => sel_pipe_d1(2)
);
\douta[9]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5),
I1 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5),
I2 => sel_pipe_d1(1),
I3 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(5),
I4 => sel_pipe_d1(0),
I5 => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(5),
O => \douta[9]_INST_0_i_1_n_0\
);
\douta[9]_INST_0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => sel_pipe_d1(0),
I1 => DOADO(5),
I2 => sel_pipe_d1(1),
O => \douta[9]_INST_0_i_2_n_0\
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(0),
Q => sel_pipe_d1(0),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(1),
Q => sel_pipe_d1(1),
R => '0'
);
\no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => sel_pipe(2),
Q => sel_pipe_d1(2),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(0),
Q => sel_pipe(0),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(1),
Q => sel_pipe(1),
R => '0'
);
\no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => '1',
D => addra(2),
Q => sel_pipe(2),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid_blk_mem_gen_prim_wrapper_init is
port (
\douta[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
\addra[14]\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_mid_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end bg_mid_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of bg_mid_blk_mem_gen_prim_wrapper_init is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFCFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_01 => X"FFFFFFFB7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_02 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF43FFFFFFF",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF73FFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFF43FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"EFFEFFE63EFFEFFEFFEFFEFFFFFFFFFFFDFFDFFDFFDFFDFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7FF7FF7FF7FF7FF7FF7FF7FFFFFFFFFF",
INIT_08 => X"FEFFEFFEFFEFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA7FFFFFFF",
INIT_09 => X"BFFBFFBFFBFFBFFBFFFFFFFF7FF7FF7FF7FF7FF27F7FF7FFFFFFFFFFEFFEFFEF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFF97FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFA7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFDFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF96FFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFB7FFFFFFFFFFFFFFBFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFDFFFFFB7FFFFFFFFFFFFFFDFFFFFFF7FFFFFFFFFFFFFFFF",
INIT_10 => X"FFFFFFFA7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_11 => X"FFEFFFFFFFFFFFFFFFFF7FBFFFFFFFFFFFFFFFBFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_12 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB7FFFFFFF",
INIT_13 => X"FFFFFFDFFFFFFFFFFFFFFFFFFFDFFFFFFFFFFFF97FFBFEFFFFFFFFFFFFFFFFFF",
INIT_14 => X"FFFFFFFFFFFFFFFFFFFFFFF97FF7FFFFFFFFFFFFF7FFFFFFFFFFFFFFFFFFFFFF",
INIT_15 => X"FFFFFF737EFFF7FFFFFFFFFFFF7FFFFFFFFFFFFFFFFFFFFF7FFFFFFFFFFFFFFF",
INIT_16 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFBFFFFDF",
INIT_17 => X"FFFFF7FFFFFFFFFFFFFFFFFFFFFDFFFFF7FFFFFFFFFFFFFFFFFFFFEA7FFFFFFF",
INIT_18 => X"FFFBFFFFFF7FFFFFFDFFFBFDBFFFFFFBFF7FFFFB7FFFFFFFFFFFFFFFFFFFFFF7",
INIT_19 => X"FFFFFEFFFFFFFFFFFFFFFFFB7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFEF7F",
INIT_1A => X"FFFFFFF97FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFDBFFFFFFFFFFFFFFFFFFFF",
INIT_1B => X"FFFFFFFFFFFFFFF7FBFFFDFFFFFFF7FFFFFFFFFDFFBFFFFFFFFFFFFFFFFFFFFF",
INIT_1C => X"FF7FBF7FFFFF7FFFFFFFFFFBFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA7FFFFFFF",
INIT_1D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF97FFFFFFFFFFFFFFFFFEDBD7F",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFA7FFFFFFFFFFFFFFFFFFFFFF7FDFFFFFFFFFFFFFF",
INIT_1F => X"FFFFFFFB7FFFFFFFFFFFEEFFFFFFDFFFFBFFDFFF7FFFFFFFFFFFFFFFFFFFFFFF",
INIT_20 => X"FFFEFF7FFFFEEFFFFFFFFFFFFBFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_21 => X"FEFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA7FFFFFFF",
INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB7FFFFFFFFFFFFFFFFFFBFFFD",
INIT_23 => X"FFFFFFFFBFFFFFFFFFFFFFFA7FFFFFFFFFFFFFBFFF5F8FDBFFFFFFDFFFFFBFFF",
INIT_24 => X"FFFFFFF97FDFFFFFFFFEFFFFFDFEFFFFFFFFBDFFFFFFFFBFFFFFFFFFFFFFFFFF",
INIT_25 => X"FFBFEBFFFFFFBFEFFBF7FFDFFFFDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_26 => X"FEFF7FFDFBEEFFFFFFFFFFFBFFFFFFFFFFFFFFFBFFFF9FFFFFFFFFFB7FFFF7FF",
INIT_27 => X"BBFFFFFF5FF7FFFFFFFFFFFFFFFFFFFFFFFFFDFA7FFFFEFFFFDFDF7FFFF6FFFE",
INIT_28 => X"FFFFFFEFFFFFFFFFFFFFFEFA6FF7DFFFFFFFFD7BBEEFFFFFFFFEFFFFFEFFFFFF",
INIT_29 => X"FFFFFFFB5FEFFFDF7FFFFFFFEFFF5BDFFFFFDFFFFFFFFFFFFFFFFFFFFFFEFFFF",
INIT_2A => X"FDFFFFFEFB7FFFFDFFFE7FFFFFFFFF7FBEFFFFFFF7FFFDFFFFFFFFFFFFFFFEFF",
INIT_2B => X"FFFFFFFFEFFFB7FFFFFBFFFD7DEFFFFFFFFFFFFFFFFFFFDFFFFBFFD97FFFFEFF",
INIT_2C => X"FFFFFFFFFEFFEFFFFFFFFFFFFFFFF7FEFFBFDFFA3FFFFFFFFF3F7FFFFEFFFF7F",
INIT_2D => X"FFFFFFFFFFFBADFFEFDFFF7B7FFFFFFDFFFFFFFFFFFFFFFFFFFD3FFFE3FFFFFF",
INIT_2E => X"FFFF7FFA7FBB767BFFBFFFFFFFEEFFEFFDBFFFFFFFFDFFFFFFFFFFFFDFFFFFFD",
INIT_2F => X"BB7FFFFFFFF74FFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEBDDCCFED",
INIT_30 => X"FEFFFFBFFFFFFFFFFFFFFFFFFFFFFFFFFBFFFFAF77772BF63BFFFDDB7FD16AAD",
INIT_31 => X"FFFFFFFFFFFFFFFEFFBFD2AEBF72F15AFCEED7EA7DE8DFC8B5B76FFFFEFDFFDF",
INIT_32 => X"FFDFADBBFFFF5758AFBF74495DBFD6F3D98FFD6FFFFFABFBFFFFFFFFFFFFFFFF",
INIT_33 => X"DCE6FFF27B42F9AFEB69632F3FFDFFEFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_34 => X"7CEF6EA4DFFF5FFFFFFFFFFFFFFFFFFFFFFFFBFFFFFFFEFFFFFADBF56D3CFC7B",
INIT_35 => X"7FFFFFFFFFFDBFFFFFFFFFFFFFFFFFFFFFF7AD6FFEFFFE7FE7BF697969FA4FF1",
INIT_36 => X"FFFFFFFFFFFFFFFFFFD91DFB43FD6C69AAFD9FD35DE4F3AEA13F9B4F88BBFDFF",
INIT_37 => X"F6FDFFFEBCECB2FAEAFEBEF33DD4F49EF953DD4F6D6FFFFFFFFFFFFFFFFFDFFF",
INIT_38 => X"9963EB3A12236E9B4AFB2236684FFFFFFDFFFFFFFBFFFDFFFFFFFFFFFFFFFFFF",
INIT_39 => X"B7EAEFBD55BBFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFDAF466DB3ECDE4EF7",
INIT_3A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7CECFBBEE1B7D6DD776DD6EFB4EFBDCB5",
INIT_3B => X"FFEFFFBFFFBF7B7FBA66DD59F19AB2765FF6F70128DCD396FC648DCDA7133FFF",
INIT_3C => X"7E5D965F7FFA25A6197CAEB90EEF9E97A6AEEEF9F7A6C2FBFDFFFFFFFFFFFFFF",
INIT_3D => X"AFA95F635D77303C3BB5D773B85CD1FFF7FFFFFFFFFFEFFFFFFFEFBBDBFA7FAE",
INIT_3E => X"54D2319F77BB4F3FFFFFFFFFFFFFFDFFFFEC979E64D7479133B3C9DDDB45E1CE",
INIT_3F => X"FFFFFFFFFFFFF7FFFFEFFC63AB6D9BDBEB7FADBACEF6FBA57876544A6319F7F3",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(13 downto 0) => addra(13 downto 0),
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 1) => B"000000000000000",
DIADI(0) => dina(0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => \douta[0]\(0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => \addra[14]\,
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
\douta[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 4 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"5055500505505545404455350500450054605055750555065070030075033055",
INIT_01 => X"0550755570304057505550745555407900554044553505004500542505045434",
INIT_02 => X"4507553053055075070745564540775405550477050733505300064356657072",
INIT_03 => X"5FF9575756550555565755555305505555055553705545505740035000705504",
INIT_04 => X"605555559775597F95F57F5F77B759777D79FF977F7F5777FB77FF95F5F95757",
INIT_05 => X"0055057035500555035705555073550555507007000707455005737075050750",
INIT_06 => X"0540320545557053705005070577007900550357055550735505055555055035",
INIT_07 => X"7037555353505555050005447073475555350534505550705405055745000555",
INIT_08 => X"7977550503575550575453320234000746504505507037755430545050055437",
INIT_09 => X"53020555579F5F977957F777F797DFF57777977F9797F9B77779777F597F7F7F",
INIT_0A => X"4505305070453403753040050057405440505535775573453570003050750565",
INIT_0B => X"9053555300500007005570523503306904537530400500574054300054403703",
INIT_0C => X"5550555050755600545553444455500750455555055005370005505507577555",
INIT_0D => X"7755754777070755577005055535555305055575557505543350670575553444",
INIT_0E => X"0070030735557559D7F775F779F399955F59BDF757F7F99BF77F7F77BF579797",
INIT_0F => X"5534555355050505405053545755455050452050300705000007055705003705",
INIT_10 => X"5000500075555550544505555370507805354050535457554550005425505475",
INIT_11 => X"7755075735002550370555554575457074556055770775507500555055030075",
INIT_12 => X"5504557550457547550455534050555055540700575755672523570300505554",
INIT_13 => X"55275033500535555579595FF5797FF777795775F77F79F77F95F77F57B7D7D7",
INIT_14 => X"0500730355350030505500003005055903005557057055055704555003555070",
INIT_15 => X"5500547547055340355700005005008900505055000030050559035300070555",
INIT_16 => X"3056553075500073350530006435660554405570705070755790535004755505",
INIT_17 => X"5775755055667050567503504750507556506755505055575053053350540006",
INIT_18 => X"055005030500300005353572597537F79F57FF95B77F95F7F577FF79977F5F5F",
INIT_19 => X"5307500555305043050050570505550504035352505053523573353003007550",
INIT_1A => X"0457507503003375035500455430709807730500505705055505545550703050",
INIT_1B => X"7540737063507555070540505574500570057705704055000720500005705707",
INIT_1C => X"7405554505007055047046300075057505075065767755750575555050550555",
INIT_1D => X"53004030505005355050050335755557557755F5979577399F959775BF959597",
INIT_1E => X"7570550300000550757077005300300355000555300705370435030545320303",
INIT_1F => X"0535350353450400735000505070007903307570770053003003053507350707",
INIT_20 => X"0343044070505050555505550405507507503050057750030535073030740303",
INIT_21 => X"0555070550453003053507303074030305353503534504007350005305353503",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(13 downto 2) => addra(11 downto 0),
ADDRARDADDR(1 downto 0) => B"00",
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 4) => B"000000000000",
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 4) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 4),
DOADO(3 downto 0) => \douta[3]\(3 downto 0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
\douta[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
\addra[14]\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"B5DB5DB5C95D6EF67D27EDDC4FA4FA4FB6BB6BB6B92B92B9BBDBBDBB49F49F49",
INIT_01 => X"FEDF9AFB3FDBFDBF59F59F59F7DF7DF75F35F35FB7FB7FB7F6EF6EF67D27D27D",
INIT_02 => X"7D57D57DC79C79C78E78E78EFAAFAAFACD7CD7CDFEDFEDFECFACFACFBEFAD7CD",
INIT_03 => X"6FF6FF6F76F76F769E39E39EABEABEABEABEABEA3CE3E39EABEB3C74157D57D5",
INIT_04 => X"FDBFDBFDBDDBDDBDDBDDBDDBDFFDDBFDBDDBFB7737BB7BB7BB7BB7BBFBFFBFFB",
INIT_05 => X"67D67D6756356356B76B76B42B3EB3EBACFACFAC6AC6AC6AD6ED6ED67D67D67D",
INIT_06 => X"A76A76A638778778E5CE5CE54E54E54ED4ED4ED4EF0EF0EFBB5BB5BB59F59F59",
INIT_07 => X"EF7EF7EFFEBFEBFEAFEAFEAFFAFFAFFA3B53B53BC3BC3BC32E72E72E72A72A72",
INIT_08 => X"D67D67D6FF6FF6FFFABFABFABFEBFEBF7BF7BF7BF5FF5FF57F57F57A57FD7FD7",
INIT_09 => X"9F59F59FDBFDBFDBEFBEFBEF3EB3EB3EB3EB3EB27B7FB7FB7DF7DF7D67D67D67",
INIT_0A => X"75C75C75D71D71D79D79D79A6B9EB9EB8EB8EB8E3AE3AE3AF3AF3AF33D73D73D",
INIT_0B => X"9D79D79A6BDEBDEBCEBCEBCE3EE3EE3EF3AF3AF3BD7BD7BDEBCEBCEB5CF5CF5C",
INIT_0C => X"FFF7F5FB9EB7CFE4AFD7E927BE2D4C4AEBCEBCEB5EF5EF5E75E75E75F71F71F7",
INIT_0D => X"54FBB6EFC7F761CDFF3EFFBDFFDBFF0FD8FCCD9DFAE9DFC77F5657F865DB2BDD",
INIT_0E => X"F9ED77F3FFD766BFBEAE47EF9EF69A3E9B6FFF727E7DD253FFC76DD2BFAEFDA9",
INIT_0F => X"E6DB6B78F6F3B9AFFFFDEBEA7EFD8F9A6EFDFF7DFDDF7DE48E7D67FB48A4CF4F",
INIT_10 => X"AFD743F27D6FEFE7775C69F3BFEEFABF696B7A2FA881A4DEDFB7FFEBDF7FDFF7",
INIT_11 => X"FFEEFFF0F67BE31EFD651CBFF57ED6D5F6F4CB2D7EE3F5F7DBDE3BD2EAF9CDDE",
INIT_12 => X"1C6F5DD7E8FF3D5F3F1774FDCEBF8F4D677E6B71FF55FFFFC57FCF9A73F577CD",
INIT_13 => X"F55DB2FEE35D63F791D2FEFFDFDEF7F7FFFBFFFA7ED1DF37FFF9FF84CEF5FFFD",
INIT_14 => X"AAD9B6FBFFF7B4E3EE31E7F077F7FFCF7F2EFE7F51DAF535F6F3AFEFADFB8BF0",
INIT_15 => X"5FFEBD326ABD361BDB8DCEBC06732D1D9FB3FBF7A9FF21F66EEF3BEBDDFF67FE",
INIT_16 => X"F508FC3A09E1D6FAFE667297F7FFAD3A87D9DCF7B57ADCEEFFFA7D5FFBEF664F",
INIT_17 => X"89D4E74FFBECC10AFF2FFFEDB7BCAFFD735D37FFFEE5FDB79FFB67E87CBEA9DF",
INIT_18 => X"FF9A7FEFED7F67FF5DFDE371BFBFD6D9FF2FFFF2217FF853FE530005357AFEB7",
INIT_19 => X"FBDEAEE070A4BA07DFF1DD42257FB40517E9118293DC3FE5C59883FFCE5CC1EF",
INIT_1A => X"F4A6FAB236FFD54035F5DAD73877778E8EEBD8FFFC903EECFFFAFFFDBD697FFF",
INIT_1B => X"0F9781D280FAA177319C7DDAFF97475FFFFF6DF1FF07FFFFFFBBFD1E3F4AC87D",
INIT_1C => X"AC4ABA69E4D519FF9FFFEFDBD39FFFFFFE9FF8FF37DF4C7FDFFDEFE2697FEA59",
INIT_1D => X"1FFF6FF7FDFFFFFFFFFFFFFF0ED3A05EFFDBE9A8183FE236E7FFF1E3C2E8343E",
INIT_1E => X"FEDDDEEC01836377FFDEBF500C9C166CA2DFDBE0177CF4217C2AFD96D8E2CBFA",
INIT_1F => X"976BE81A3AFE89FF67DFEEF05FC7DBFF13F7DB47041005DF1FFFBFFFDFDDFFFF",
INIT_20 => X"E59EFC760EF8E6D85C9FA0E45AC9C6FA5DFF3FFFBF7BFFF07E67AB778CDF1DE6",
INIT_21 => X"B2F1CF8889BEEC6F24FFC7FB8DAFFFE650399EA530E2E5FE19A86B620C3B2FFF",
INIT_22 => X"087F65BD777F7FF4FE9A7D84E7FF8F77332ECFDA42FED7561FFF79DF9F5BF78C",
INIT_23 => X"EDA4D1B1B39FEF3B5F3B7D3213FE9FD3E6F75FAF7F5F089AADA7BA074FF6B87F",
INIT_24 => X"FD76DFC83D5FFF3B9BDE684E7DBCF5D497609CE91DFFB81F8188759FFC7E04F7",
INIT_25 => X"FF3FABA7F7F386A57B55698F1BBD7BEF70EE97FFFF7578485E751DDDE7E4F856",
INIT_26 => X"CEA875617AA2E6DFFDFD5FFBFBDFD7F1C8EC3679A9FE9F58FFE7F56A19FEF5E6",
INIT_27 => X"2BFEFFEF5FE77E9C973ECBFC4F7F7FA7BE7BFD786F7F7AFBC95DC811FBD6AD18",
INIT_28 => X"29976BEEDFAF5FCC1FFAECFA6FF5D5B4FEE69C3B1EACE17ABF76EDE47E39FAC0",
INIT_29 => X"223F7F4A4FCB5BD77F924B454184118F89C70AFF28F7DF55C57FFF8FFFF6FF6A",
INIT_2A => X"395527AE3853FD9197AA6A939130D26A3EBCDFFFF7FFED7DB6DE7FF9F9FFAAFF",
INIT_2B => X"F68DB15D2EB6A0FF77FB93FD09EE9AFBDD4BFFF27EFF098FFDFB9FD27FD6B27F",
INIT_2C => X"EEEACBBFCAAEEE7F6FBFFFEF9D37A1E8F9BFD1E23FF0070D511755FFCAE7EA3F",
INIT_2D => X"FEFFDFBD5BE7BD7B4F431C724ED35FDC759031FFFFFBB919BF2D2EDD62A7826F",
INIT_2E => X"2CE97FD864420149AF9CB3A7FFAE74AC3D93C78FDEF15BF56EE1D145DE9BE73D",
INIT_2F => X"0037FC7EFFF74A15054399F62F98CA3F52C1413F97DE8D47577FC7FC49922394",
INIT_30 => X"B8979E4FF95F05EFCCB5DDBBCBF5EF6EFBEFB6470F680C6B3870800232DB5A25",
INIT_31 => X"5542EFFDB73DEF96B5B4E04040BF1230CA2D03024CA46C55ADA055F9DCFD259C",
INIT_32 => X"FBDB6DA28E404901046DF00208304000045484449BFF22DB6B67F577DF4FABF5",
INIT_33 => X"34D0E8125200892C2000D9082FFDB15FABAEED3DF19B114F9E27FFD7F7EF7DEF",
INIT_34 => X"448400008FD64D3AED972FAB3F67BEAFCA976BEF5D3DAEBEFAF6420622208A89",
INIT_35 => X"7E35BCFFF219BFBFB17FF2B7BFD8FA36B7D02C8EA14C0D513380003008000844",
INIT_36 => X"2DDFFBEB57EFFCFDEFDD0012206208E08A2C1C423000B198008A920B0A33BC93",
INIT_37 => X"C6CC00420A008AD2020C8E0211102018111111022109D57F03547DF71FFB06DF",
INIT_38 => X"1902A11A1010489A104901041003C5BF148B9FD5F94DA93583A9F7FDFDFBBBDE",
INIT_39 => X"2162A40440B001AA2B3E7BEFD6C7B7CF4ADEEDF8D8FABFD9B9226820073444AA",
INIT_3A => X"2795BE5DEDE74CDFEEFFDBC7E7F1FC8646482A461001010622C548920A404405",
INIT_3B => X"5FE7EFB1915A1245900009005192886E44724002204400022000044000031DD1",
INIT_3C => X"66481158000005A4281802001241960B20872419C1B0CAF52CB796DF5DF67DFF",
INIT_3D => X"420045425906202C0B1190620890011EFF5F62FFEFAD2F5F65E6E09D5D5384A0",
INIT_3E => X"40C0301400A05E0D4FFF7D77F7A5C9FA72C51216280349113296889489202001",
INIT_3F => X"F7FF0BBCFF5F82FFBDC0B4422B7A0050C0682021808601001810100023014303",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(13 downto 0) => addra(13 downto 0),
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 1) => B"000000000000000",
DIADI(0) => dina(0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => \douta[1]\(0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => \addra[14]\,
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized2\ is
port (
\douta[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
\addra[14]\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized2\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized2\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized2\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"B5DB5DB549556EB679276DD44F24F24FB6BB6BB6A92A92A9BADBADBA49E49E49",
INIT_01 => X"FFFFFFFB7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB6EB6EB679279279",
INIT_02 => X"5D55D55DD79D79D78F38F38FBABBABBAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_03 => X"7FF7FF7FF7FF7FF7CE3CE3CEAEEAEEAEEAAEAAEABCEAE3CEAEEB9C7415DD5DD5",
INIT_04 => X"FDFFDFFDFFDFFDFFDFFDFFDFFFFFDFFDFFDFFBF73FFBFFBFFBFFBFFBFFFFFFFF",
INIT_05 => X"4BD4BD4BD6BD6BD63F23F23433BB3BB3A97A97A97AD7AD7A47E47E4776776776",
INIT_06 => X"E76E76E63C77C77CE5CE5CE5CE5CE5CEDCEDCEDCEF8EF8EFF91F91F99DD9DD9D",
INIT_07 => X"DF7DF7DFFFBFFBFFAFBAFBAFBAFBAFBA3B73B73BE3BE3BE32E72E72E72E72E72",
INIT_08 => X"DC7DC7DCEFCEFCEFEEBEEBEEBEEBEEBEFBEFBEFBFDFFDFFD7DD7DD7A57DD7DD7",
INIT_09 => X"1F71F71FF3BF3BF3AF3AF3AF3AF3AF3AE3EE3EE27E77E77E75E75E75E75E75E7",
INIT_0A => X"EDDEDDED5ED5ED5ED7ED7ED27F3FF3FFBDBBDBBDABDABDABDAFDAFDA7FE7FE7F",
INIT_0B => X"9939939A2BDABDAB4AB4AB4A36E36E3673273273B57B57B5BF6BF6BFF9FF9FF9",
INIT_0C => X"FFFBFDBB0FFDCEB6FFF7FBBF3EBF6DDAC9CC9CC95ED5ED5E55A55A55B71B71B7",
INIT_0D => X"5EDD7FEFC3FFF3AFFBA7DFBDF7EBEF0FD8EED1BDEEEBEFCFEF56FFF8677BABDF",
INIT_0E => X"CDED77FBDFDB5EFFBFB767FB1FFE9A3E9BEFEE325EFFF75AAF6729D2FF26BDF9",
INIT_0F => X"EF7B6F7ABEF79DEFDFEFEB9A76FF9FDEAEFCE73DFD7F6DE5CE5DEFC4B775EFDF",
INIT_10 => X"6BD9937A7DEAE96FF7D7FFE7B7F7FBBFF9FFFA105701B5FF5FBEAEEE9FD7FFF9",
INIT_11 => X"7EE9FF1AEE2F765CCD650E000A82DF95F7E4D93D76EBF5F7F9DE92F6C9F9DDD6",
INIT_12 => X"3E6F4CC017003DFFBF5776F5CEBFCF3DB7FF7BEBFF57FF7FD57FEFB23B5577F9",
INIT_13 => X"D5EFFBBCFB656AF791F0F65EFF9BEFB3FEFB7BFA7DD28B1F29FFFFFC5FF4FBDF",
INIT_14 => X"9B7DB3FFDEDFFF76F767F77016F29BCF79FFFFFFF3DAB1B7F7DB9A0052240FFA",
INIT_15 => X"4FBEFC322EC735EAE2F7FFFFFF736D5DBFB02101170121FF0AE5BBCF7F7D624F",
INIT_16 => X"FAF7FFFFFDA5F6FAF464066808000DFA7BDA6DF6FDDA9BFBFEDA6D4FBBFFDBDF",
INIT_17 => X"89F0C4B04400013FFFFFF7FFB7B4FFFEF7593FFEF77FF6FFBEF7FEA877FFCFEF",
INIT_18 => X"FFFA9FEDEF6FFFFFBDF5427D9EF7FBFBFB2DFFFA1FFF67FCEDEDFFFFFE5A7EA5",
INIT_19 => X"FF76FCFFF7FB6FFFFFFFFFFA7BFFDFFFFCDFFF7D7E283F654D100180220C41EF",
INIT_1A => X"3F3FFFFA5FFFEEFFEF6F276AFFAB668E9AABD00084D03AFEFFFFFFFDBDFFFFFF",
INIT_1B => X"FB5AFE7D7F7FA156311C5D80020447DFFFFFFDB1F6BFFFFFFFEEF7FFCDFFFFFB",
INIT_1C => X"846A2A2804D119FFFFFEF2CB927FFFFFFFF80FFFF93BFFFDBFF7FFFA77FFF7B7",
INIT_1D => X"FFFFDDB6FFFFFFFFFFFFFFFEFFFDFFFFCFFFFFF87FFFFDC9FA9FFF1E3D28243E",
INIT_1E => X"FFFF7FFFFF7DFFDFFFFFFFF87F77FFD7FDB786DFEC09B425450B4C9659C2CAF5",
INIT_1F => X"FFFDFFFA774FFEA8D95EEEBFA3D7589E13D41B09040089FFFFFFF5CA7FA7FFFF",
INIT_20 => X"3E745C4BF9A82558CC8220A45AC996FAFFFFDFBFFFDFFFFFF7FFFFDAFFFDEFFF",
INIT_21 => X"92D9CD030022606FFFFFFE5EFFFFFFFBBFFEF7FFFFBF7ABFFFF7FEFA7BE5FF65",
INIT_22 => X"FFFFFFF3ADFFFFFFADF7EF7BB97BFDFFFFFDFB3A3FAF7957F91B83B974129084",
INIT_23 => X"73FFAF7FBBBF7FEFFFFDFFEA6EBBFB88BD9B55BB8057098A08973A164984A27A",
INIT_24 => X"FFFDCAB87E9CEC336CEC6A5FD988F554874094E15E43021F7EFFFB79DFFDFFFE",
INIT_25 => X"A9B2A3B4AE278AA52017498E395D10EF8FBB66FF55DF9FB7AFBAF3B94F446FFF",
INIT_26 => X"CAB975617A0243DABAF3FB7BAFBD7F5E7FB7FFABA1BC9DEFFF7EBFF277739546",
INIT_27 => X"292F6AD65D67EBF7F9D5F6F60F766F7BFFAF95C85BDCEAABBFCD49154094AC98",
INIT_28 => X"DF7B954E5FAF763FFEF8AEF246B6D7B4B6E4BC3306A8E17C8122ED60461940C0",
INIT_29 => X"FFDF6F4A4F6B1BD749B2EB45498401C17EC30AFD28DF8D45117FFEFF49E48ADF",
INIT_2A => X"31212A8A3053D4502B326A934138D26AAAAD2E59F75B7DF3FDBBDFA8F9FBB279",
INIT_2B => X"8889B05C2C2600D51C337D792DE59ABD67BDEE9A2E7F1F974FDA93D27DBFEE3F",
INIT_2C => X"D31FB8F6DAB7637ED27271EFD9A7A4CAFFBFD17A2AF3B1894D14156F8A8D4A2E",
INIT_2D => X"4E3C303D7FFFBDDF43431E724EDF5FDC51AB507FAF12A9184D2D2CC922A782EF",
INIT_2E => X"EDE97FD86FFBF76BAF883385002476EF7513C78DDCE151F095FEBFFB5A8BEF7D",
INIT_2F => X"FB77FC76A2854A50054191F62F980A3FBF3FFFFCEFDE851277EEC7FEFDDFBFFD",
INIT_30 => X"B0979A4B785F056FB36E35AF7CC5EF7E8B2237EFFFFFAFDF33FFFDDA5FCF7BBD",
INIT_31 => X"ABBD6BBDBDBCBE86F53CFFEEFFFFF7FBFFEBDFCA7DEEF7DFBDBF7FFC6619219E",
INIT_32 => X"A9DBED3FFDFF7FD9AFFFA44A5DBFD6F3DDFF7D6C8535229B4B43F477DF6763F5",
INIT_33 => X"7AF757E27B4AF9AFEB7BFAAF2428B05E23AE6D3D7089154F73DABFD7F6EF5DEE",
INIT_34 => X"7CEF6EB4CF064D98CD972FAABF679AAF75F349BDB934A6BE7A7EDBF76F3CF7FA",
INIT_35 => X"2B17B8FFF211B6BA4EDCBEF7BEF9DF3696F7A9EDDF7FFF6FCFBF6B6869FB47E5",
INIT_36 => X"360FED6B57A7BDD9AFDD1DFB6FFF6DE9AAFDDFB27DE5F63EA9BF9B5FEA11BC07",
INIT_37 => X"D6F9FFFEB7ECBAF8EAFEFEF23DD4D59EF947DD4DEC7AD43E63557DFE1DBB06FF",
INIT_38 => X"9B676B6A16272C0B4ABB627278DFC5BF8C8397BDF94D2D35C6BDD3BDBD5B935E",
INIT_39 => X"16AEE3B9D5F3C1AA0B3E7BEF56C787CFD75EADF9D9FEBFFDBF642593EBFE5E7F",
INIT_3A => X"3715DE5DC1A54CDFEEBB5FCFEFF1FD97C9DF9BED1B7D6DD576DD2EFA6E3B9DB5",
INIT_3B => X"DBE7E8BFFFFF7B7E7B66D459FDDAFF7A5FB6F7120A9AD397DE64A9ADA75A7DD1",
INIT_3C => X"7A5D975F7FFA3D76397CAEB81CAF0D9E86AFCAF0F7B60E755CB53ABF5DF64D75",
INIT_3D => X"EFAB5E224571503070E45715B8CDD9FE7B176F6F6929235F67F7EF6FCFE9FFAE",
INIT_3E => X"5416C1CBF73B1D37CFEF3DDFE7A349DA7AEDD5DA6DD6CF9511A7CBCDFB67DFCF",
INIT_3F => X"F7FF6FF6BF4F827F3BEFFA61BBDFBBCBEB1FADBB4EF2FFF5727ED4C86C1CB7F6",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(13 downto 0) => addra(13 downto 0),
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 1) => B"000000000000000",
DIADI(0) => dina(0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => \douta[2]\(0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => \addra[14]\,
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized3\ is
port (
\douta[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
\addra[14]\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized3\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized3\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized3\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"FFFFFFFFFFFFFFFFFFFFFFFCFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_01 => X"021002232042042040440440444444444404404484084084FFFFFFFFFFFFFFFF",
INIT_02 => X"B7BB7BB7BB7BB7BBFBFFBFFB6FF6FF6F01101101021021020220220222221101",
INIT_03 => X"C5CC5CC55E15E15EFFEFFEFFFDBFDBFDBDDBDDBDDBDDFEFFFDBFFFD4BFB7FB7F",
INIT_04 => X"73173173857857856A56A56AC6AD31738578E627B0AF0AF0AD4AD4AD58D58D58",
INIT_05 => X"FDAFDAFD2DD2DD2DD0DD0DD49F4DF4DF5FB5FB5FA5BA5BA5BA1BA1BA9BE9BE9B",
INIT_06 => X"4DB4DB47A6DA6DA6DA2DA2DABFEBFEBF69B69B69B4DB4DB486E86E86FA6FA6FA",
INIT_07 => X"36D36D3651651651F75F75F74D34D34D6DA6DA6D36D36D36D16D16D1FF5FF5FF",
INIT_08 => X"3AA3AA3AB1EB1EB1D7DD7DD74D34D34DB69B69B68B28B28BBAFBAFBB69A69A69",
INIT_09 => X"A8EA8EA87AC7AC7A55E55E5575575575D51D51D10F58F58FCABCABCAAEAAEAAE",
INIT_0A => X"96B96B96A92A92A9BA9BA9B909E09E0972D72D725525525537537537C13C13C1",
INIT_0B => X"67E67E61767F67F6FD6FD6FDEFDEFDEFCCFCCFCCFECFECFED4DD4DD44F04F04F",
INIT_0C => X"21759F6DF0D65D5928DA0D41CF51F22F3F33F33FB3FB3FB3EB7EB7EB7EF7EF7E",
INIT_0D => X"F326D2B8BC240D704E58E86A8D5F11F937D52F4BD71D54BC74BD654B2E957FED",
INIT_0E => X"73BEAB9532B4EFA5E56AFFACA8E575E375DCBBF979FEC8B77E9EFE7BECFBF3A6",
INIT_0F => X"34A5FDAFD54AFBB964D4B5612FFCF1B17BEBFFD66BCADF9AB3A315FFFFCE1125",
INIT_10 => X"BF3E7EB11A1FBFB75DBFFFFBDA2934794EDAEDFFFFFF5ED0A6FBD5D3657D4A16",
INIT_11 => X"CB7FFFFF35FAABE3B3BAF3FFFFFF602A4ADF7796DBD66FAE973B6F9D3FAE6A2F",
INIT_12 => X"F595FF7FFFFFD3C5FDBB996B3554BCCB6E25DC5662FFFFE97AA350D955BFDBCE",
INIT_13 => X"2A3966D7BFDFF5AEFECF2DF5D4FFFFDCA5DD9D6146FFFCF77E9FFFFFEA8F8DAD",
INIT_14 => X"FF975EC4B5FFFFFBAAB91BBB7FFFFFF5DFFFFFFFFDBDDE6E48BFFFFFFFFFF22F",
INIT_15 => X"F8DFFFF97FFFFFFF1FFFFFFFFFDEBFFBC56FFFFFFFFFFED0FFFF6578CAD7FFFF",
INIT_16 => X"DFFFFFFFFFDF4DA53B9FFFFFFFFFFF05FFF5DE9FB36FFFFFFFFFFAF84FFFFFFC",
INIT_17 => X"FFEFFFFFFFFFFECAFFEC99215EDFFFFFFFFFD625AFFFFFF2652FFFFB7FFFFFFF",
INIT_18 => X"FFFF6E7AB9FFFFFFFFFFFFFFFFFFFFFFFFFFFFF97FFFFFFF3FFFFFFFFFFDABDF",
INIT_19 => X"FFFFFFFFFFFFFFFFFFFFFFF97FFFFFFFFFFFFFFFFFFFEDDBF3FFFFFFFFFFFF1A",
INIT_1A => X"FFFFFFF97FFFFFFFFFFFFFFFFFFFDBFFFF7FBFFFFFFFEDC1FFFE44CACBFFFFFF",
INIT_1B => X"FFFFFFFFFFFFFFF9FFF3E7FFFFFFFA30FFFFFFFF7FFFFFFFFFFFFFFFFFFFFFFE",
INIT_1C => X"FFFFFDFFFFFFF74AFFFFFFFDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF97FFFFFFF",
INIT_1D => X"FFFFFFFF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB7FFFFFFFFFFFFFFFFFFFFFEF",
INIT_1E => X"FFFFFFFFFFFFFFFFFFFFFFFB7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7FCA",
INIT_1F => X"FFFFFFF97FFFFFFFFFFFFBFFFFFFEFEFEEFFEEFFFFFFFF2AFFFFFFFFFFFFFFFF",
INIT_20 => X"FFFFFFFFFFFFFFF7FB7FFFFFFFFF7F85FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_21 => X"7FFE77FFFFFFFFBAFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF97FFFFFFF",
INIT_22 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF97FFFFFFFFFFFFFFFFFFFFFFF",
INIT_23 => X"FFFFFFFFFD7BFFFFFFFFFFF97FFFFFFFFFFFFFFFFFFFFFFFFFFFC7FFF7FFFFF5",
INIT_24 => X"FFFFFFFB7FFFFFFFFFFFFFFFFFFFDFFFFDFF7B7EFFFFFFEAFFFFFFFFFFFFFFFF",
INIT_25 => X"FFFFFFFFFFFF7FFFFFFFFF79E7FEFFB0FFFFFFFFFFFFFFFFFFFFFFFFFAFFFFFF",
INIT_26 => X"BFFFAEDFDFFFFF35FFFFFFFFFFFFFFFFFFFFFFFFFEDBFFFFFFFFFFF97FFFFFFF",
INIT_27 => X"FFFFFFFFFFFFFFFFFFFFFFFFFDEFFFFFFFFFFFFB7FFFFFFFFFFFFFEFFFFFFBF7",
INIT_28 => X"FFFFFFFFFAFAFFFFFFFFFFF97FFFFB7FFFFFFFFFFFFFFFFFFFFF7F9FBFEFFF3F",
INIT_29 => X"FFFFFDF97FFFFFEFFFFFFDFFFFFFFFFFFFFDF5AAFFFAFFFFFFFFFFFFFFFFFFFF",
INIT_2A => X"FFFFDFFDFFFF7FFFFFFFFF6DFFCFBF95FFFFFFFEFFFFFFFFFFFFFFFF8744DFFF",
INIT_2B => X"FFFF5FF7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9ABFFFFFFFFFFF97FFFFFF6",
INIT_2C => X"FFFFFFFFFFFBFFFFFFFFFFFFB758FFFFFFFF7FF97FFFFFFFFFFFFED6FFFFFFFF",
INIT_2D => X"FFFFFFC280000000FDFDF7893120A027AEFFFFD2FFFFFFFFFFFBFB3EDF7E7F9A",
INIT_2E => X"121680231000001050F7CEFFFFFFFFFFFAFEFDF36FDFFFAFFFFFFFFFFFFCFED7",
INIT_2F => X"0008039BFFFFFFEFFFFE6E7DD16FFFD0FFFFFFFFFFF3FEFFFFFFF80000004000",
INIT_30 => X"FF7DF7B6BFF7FBFAFFFFFFF7FFFF39F5FFFFC800000000000000000100000000",
INIT_31 => X"FFFFFEDAFFFB7FFD7FFF00100000000000000021000000000000002FFFFFFFFB",
INIT_32 => X"7FF40000000000000000000100000000000000037FFFFFFEFFFD9BC9AEFDDC7A",
INIT_33 => X"8000000100000000000000001FFFFFEFFCFBD6EAAFF6FFBAFFFFF67CBF5BAB57",
INIT_34 => X"0000000013FFFFE7BB69DAD5DABFEDF0FFFCFF6B47FFFFDBEFC0000000010000",
INIT_35 => X"F7FED72E2DFE5F4FFFEFE5BEEF16ABFFFD800400008000000000000300000010",
INIT_36 => X"FFF11BDFF8FF56E7720000000000000000000001000000000000000001FFF3FE",
INIT_37 => X"20000000000100000000000100000000000000000007FBD5FEFEE32FE655FDD5",
INIT_38 => X"00000001400002200000000002007FFAFBFD7CD25FF6FFCAFF773F7373EEEEE1",
INIT_39 => X"8000080000083E55F7E38431A9397BFA39A7FA8EAE9171100000000000000000",
INIT_3A => X"FCEFB3EABF7EFF20D77DA030100E026000000000000000000000000100800000",
INIT_3B => X"34DC10000000000000000000000000000000000100000000000000000000027F",
INIT_3C => X"00002000000000000000000300000000000000000000000BEB6FD5D0BB5DFFCA",
INIT_3D => X"0000000100000000000000000000000385E99299B6DEFEAA9D68000000000040",
INIT_3E => X"00000000000000007A34D266997EBEB5AF100000000000000000000000000000",
INIT_3F => X"0891922970B17FC5D40000000000000000000000000000000000000300000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 1,
READ_WIDTH_B => 1,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 1,
WRITE_WIDTH_B => 1
)
port map (
ADDRARDADDR(13 downto 0) => addra(13 downto 0),
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 1) => B"000000000000000",
DIADI(0) => dina(0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 1),
DOADO(0) => \douta[3]\(0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => \addra[14]\,
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized4\ is
port (
\douta[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized4\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized4\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized4\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"09880909880909008888000B09880909880909008888000B0988090988090900",
INIT_01 => X"880988008809000B88880988880988008809000B88880988880988008809000B",
INIT_02 => X"8809880B88090988090988098809880B88090988090988098809880B88090988",
INIT_03 => X"8809888809888809000988008809888809888809000988008809888809888809",
INIT_04 => X"09880909008888000B09880909880909008888000B0988090988090900888800",
INIT_05 => X"09008888000B098809098809090088000B88880988880988008809000B880000",
INIT_06 => X"0B88090988090988098809880B8809880988880988008809000B888809888809",
INIT_07 => X"8809888809000988008809888809888809000988008809888809888809000988",
INIT_08 => X"09008888000B09880909880909008888000B09880909880909008888000B0988",
INIT_09 => X"000B88880988880988008809000B88880988880988008809000B888809888809",
INIT_0A => X"8855777755887777077777778855777755887777077777778855777755887777",
INIT_0B => X"5588557707887777555577075588557707887777555577075588557707887777",
INIT_0C => X"0788777755887707778855770788777755887707778855770788777755887707",
INIT_0D => X"5588550777555577778877775588550777555577778877775588550777555577",
INIT_0E => X"0055887777077777778855777755887777077777778855777755887777077777",
INIT_0F => X"777707777777885577775588777707777755557707558855770788777700FFFF",
INIT_10 => X"7755887707778855770788777755885577075588557707887777555577075588",
INIT_11 => X"0777555577778877775588550777555577778877775588550777555577778877",
INIT_12 => X"7777077777778855777755887777077777778855777755887777077777778855",
INIT_13 => X"7777555577075588557707887777555577075588557707887777555577075588",
INIT_14 => X"770B8877000988098809000D770B8877000988098809000D770B887700098809",
INIT_15 => X"000909098877000D090B8888000909098877000D090B8888000909098877000D",
INIT_16 => X"8877090D09778888770909888877090D09778888770909888877090D09778888",
INIT_17 => X"09770B88770009880977090009770B88770009880977090009770B8877000988",
INIT_18 => X"FF000988098809000D770B8877000988098809000D770B887700098809880900",
INIT_19 => X"88098809000D770B88770009880988000D090B88880009090988770010FF7070",
INIT_1A => X"0D09778888770909888877090D09770B8888000909098877000D090B88880009",
INIT_1B => X"88770009880977090009770B88770009880977090009770B8877000988097709",
INIT_1C => X"88098809000D770B8877000988098809000D770B8877000988098809000D770B",
INIT_1D => X"000D090B8888000909098877000D090B8888000909098877000D090B88880009",
INIT_1E => X"5588440009008855077707005588440009008855077707005588440009008855",
INIT_1F => X"0900775507000700888844070900775507000700888844070900775507000700",
INIT_20 => X"0700770088554407000077880700770088554407000077880700770088554407",
INIT_21 => X"8855880700097788550077078855880700097788550077078855880700097788",
INIT_22 => X"FF00008855077707005588440009008855077707005588440009008855077707",
INIT_23 => X"8855077707005588440009008855070700888844070900775507000700FFFFFF",
INIT_24 => X"0088554407000077880700770088558844070900775507000700888844070900",
INIT_25 => X"0700097788550077078855880700097788550077078855880700097788550077",
INIT_26 => X"8855077707005588440009008855077707005588440009008855077707005588",
INIT_27 => X"0700888844070900775507000700888844070900775507000700888844070900",
INIT_28 => X"097777000B7707BB09880005097777000B7707BB09880005097777000B7707BB",
INIT_29 => X"0B7709BB09770005777777090B7709BB09770005777777090B7709BB09770005",
INIT_2A => X"0977880577097709007709070977880577097709007709070977880577097709",
INIT_2B => X"77097709000B0907BB77880077097709000B0907BB77880077097709000B0907",
INIT_2C => X"FF007707BB09880005097777000B7707BB09880005097777000B7707BB098800",
INIT_2D => X"BB09770005777777090B7709BB09770005777777090B7709BB09770000FF7070",
INIT_2E => X"0577097709007709070977880577097709007709070977880577097709007709",
INIT_2F => X"09000B0907BB77880077097709000B0907BB77880077097709000B0907BB7788",
INIT_30 => X"07BB09880005097777000B7707BB09880005097777000B7707BB098800050977",
INIT_31 => X"0005777777090B7709BB09770005777777090B7709BB09770005777777090B77",
INIT_32 => X"887700097700077777090B99887700097700077777090B998877000977000777",
INIT_33 => X"7700997777770B99887700997700997777770B99887700997700997777770B99",
INIT_34 => X"7777099988880099090099077777099988880099090099077777099988880099",
INIT_35 => X"88887799097799077777090B88887799097799077777090B8888779909779907",
INIT_36 => X"FF0000077777090B99887700097700077777090B99887700097700077777090B",
INIT_37 => X"7777770B99887700997700997777770B99887700997700997777770B00FFFFFF",
INIT_38 => X"9988880099090099077777099988880099090099077777099988880099090099",
INIT_39 => X"99097799077777090B88887799097799077777090B8888779909779907777709",
INIT_3A => X"077777090B99887700097700077777090B99887700097700077777090B998877",
INIT_3B => X"0B99887700997700997777770B99887700997700997777770B99887700997700",
INIT_3C => X"770B77778809770977778800770B77778809770977778800770B777788097709",
INIT_3D => X"8809880977008800070B77778809880977008800070B77778809880977008800",
INIT_3E => X"7700770007777777770988777700770007777777770988777700770007777777",
INIT_3F => X"07770B77778888770900778807770B77778888770900778807770B7777888877",
INIT_40 => X"008809770977778800770B77778809770977778800770B777788097709777788",
INIT_41 => X"0977008800070B77778809880977008800070B7777880988097700880000FFFF",
INIT_42 => X"0007777777770988777700770007777777770988777700770007777777770988",
INIT_43 => X"77778888770900778807770B77778888770900778807770B7777888877090077",
INIT_44 => X"770977778800770B77778809770977778800770B77778809770977778800770B",
INIT_45 => X"8800070B77778809880977008800070B77778809880977008800070B77778809",
INIT_46 => X"0077000B777777880D880B0B0077000B777777880D880B0B0077000B77777788",
INIT_47 => X"777709880D770B0B99770077777709880D770B0B99770077777709880D770B0B",
INIT_48 => X"0D77880B990000770B7709770D77880B990000770B7709770D77880B99000077",
INIT_49 => X"990077770B7709778877880B990077770B7709778877880B990077770B770977",
INIT_4A => X"00777777880D880B0B0077000B777777880D880B0B0077000B777777880D880B",
INIT_4B => X"880D770B0B99770077777709880D770B0B99770077777709880D770B0B0077F8",
INIT_4C => X"0B990000770B7709770D77880B990000770B7709770D77880B990000770B7709",
INIT_4D => X"770B7709778877880B990077770B7709778877880B990077770B770977887788",
INIT_4E => X"77880D880B0B0077000B777777880D880B0B0077000B777777880D880B0B0077",
INIT_4F => X"0B0B99770077777709880D770B0B99770077777709880D770B0B997700777777",
INIT_50 => X"99777777777755885577880B99777777777755885577880B9977777777775588",
INIT_51 => X"77770B885599880B0777777777770B885599880B0777777777770B885599880B",
INIT_52 => X"5599770B0799777777770B555599770B0799777777770B555599770B07997777",
INIT_53 => X"0799777777770B55889977880799777777770B55889977880799777777770B55",
INIT_54 => X"10777755885577880B99777777777755885577880B9977777777775588557788",
INIT_55 => X"885599880B0777777777770B885599880B0777777777770B885599880B00BB99",
INIT_56 => X"0B0799777777770B555599770B0799777777770B555599770B0799777777770B",
INIT_57 => X"7777770B55889977880799777777770B55889977880799777777770B55889977",
INIT_58 => X"55885577880B99777777777755885577880B99777777777755885577880B9977",
INIT_59 => X"880B0777777777770B885599880B0777777777770B885599880B077777777777",
INIT_5A => X"880988880B88097709007777880988880B88097709007777880988880B880977",
INIT_5B => X"0B887777090977770B0988090B887777090977770B0988090B88777709097777",
INIT_5C => X"090900770B88880988887709090900770B88880988887709090900770B888809",
INIT_5D => X"0B880909880B7709770900770B880909880B7709770900770B880909880B7709",
INIT_5E => X"000B88097709007777880988880B88097709007777880988880B880977090077",
INIT_5F => X"77090977770B0988090B887777090977770B0988090B8877770909777700D7F8",
INIT_60 => X"770B88880988887709090900770B88880988887709090900770B888809888877",
INIT_61 => X"09880B7709770900770B880909880B7709770900770B880909880B7709770900",
INIT_62 => X"097709007777880988880B88097709007777880988880B880977090077778809",
INIT_63 => X"77770B0988090B887777090977770B0988090B887777090977770B0988090B88",
INIT_64 => X"0B99777788008809550977770777550009887709777709775577099900098809",
INIT_65 => X"7755885588D77777000055880977007777770755880905885509775555047788",
INIT_66 => X"0B99090B777777998877770055880B7777880B990000770B770B770D09775509",
INIT_67 => X"077788777707778877880088550B77880077778877000988770B887788997788",
INIT_68 => X"0077880B990077770B7705887709778855058809000988880088907788885588",
INIT_69 => X"5588000B7788077709770900990007095588777755007788078877770001F899",
INIT_6A => X"8800070B7777880977777709880955887788550B7700777700770909DD007777",
INIT_6B => X"77770988770909990000770B7700550977079955BB0B99007709550788770900",
INIT_6C => X"887777770B8877887788550B880988880777770B777777000999090900777788",
INIT_6D => X"77887777880B8877550977BB0B77775588000B77880777077709887788770977",
INIT_6E => X"8877999999BB777777770077558870075507775509095588070B770907770577",
INIT_6F => X"098809005507770977770B7777770B770B777700557788558877880988777777",
INIT_70 => X"88778877008877070B0988090B448809000B8800777709880055885577090977",
INIT_71 => X"770B000B008800770B77550909880007990B88098F0B997777885500990B8809",
INIT_72 => X"00000B880077770977008888888877770088057799557755097709005509880B",
INIT_73 => X"770999887709778877007709008877770077880B8877880B990B00880900D799",
INIT_74 => X"0B0B997700777755888800775588770977090988779977099909887707770009",
INIT_75 => X"0009887707887777779900550B778855098877090988008888770055880B7777",
INIT_76 => X"77070B887707880788770988550B770799000B55770088098855887777880788",
INIT_77 => X"07880B0B77550900887788098800097709778877097788880077070055097788",
INIT_78 => X"DDBBDDDDBBDDDDDDBB7707550988990507775509777777885577090577887788",
INIT_79 => X"885509097707000999770B777777098855777709550077008888BBBBBBDDBBBB",
INIT_7A => X"77888877880709000B880577887788770900770B88880588887707098F770955",
INIT_7B => X"550B880988778809008888778877996B88888FBBBB8F8888990B778877888F47",
INIT_7C => X"100700770B888805888888008888557700090977777777888855098804557709",
INIT_7D => X"77880B7777886B770000770B778895778877000977997788070B0B057700D799",
INIT_7E => X"880B078855887799778807770955000788050B00885509888855880988777700",
INIT_7F => X"77078809558877550B7777777709070009880009887777880977887700097799",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[11]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized5\ is
port (
\douta[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized5\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized5\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized5\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"770B09777788778855880B880B887788078855770077007777077788550B0B07",
INIT_01 => X"0B7709047788887788090088777700BB000B770B7700770B880007097755000B",
INIT_02 => X"BBDDBBDDBBDDDDDDBB9999999999998877097777098809558800550077077705",
INIT_03 => X"5588775588990977778877770055880700000077880977099999BBDDBBBBBBBB",
INIT_04 => X"880977880B778877777788550B77077777078888770977557709008800077700",
INIT_05 => X"55887788098877880D7705880B887DDDDDFFFFDDFFDDDD888888880B99058888",
INIT_06 => X"007707888877097755777799000B880B88778809000B0B880B77880955880088",
INIT_07 => X"0B558809000B880877770988770B0B07550B9977090900770B778888550077F8",
INIT_08 => X"77770B0988050B7700778877889999777788995588770977777709770B008809",
INIT_09 => X"8877558877090B88777709888877889955090B770B09880B8807558899777709",
INIT_0A => X"098877000B778809888877055509887777880077098809880077887709888877",
INIT_0B => X"77007777097788558888770B098809097788097777990B88090B777777000977",
INIT_0C => X"BBBBBBBBDDBBDDBBDDBBBBBBBBBB889977880907550777550735997709770977",
INIT_0D => X"00770B0B7707990009078809097709078F99990B777777996B8FBBBBBBBBBBBB",
INIT_0E => X"7777880B55887709090B880B885588770B7788550955880B0977990707770B99",
INIT_0F => X"0B8807778877880B77888F8F88BBBBDDFFFFFFFFFFFFFFFFBBBB6B8877990D09",
INIT_10 => X"000B7788550977880B070B0099889988998877889977888888005555880B0977",
INIT_11 => X"770009779977090499778877777788887788550977770777880955880B00D799",
INIT_12 => X"7788887707778877990099889988778888888888888888886B88887788777788",
INIT_13 => X"550B885509880077557788077700777709887777880977775588770B55097777",
INIT_14 => X"777709997788770977097788778877770055990988887777990B555588770900",
INIT_15 => X"770988888888778809550988097788000977778809775509778800770B779900",
INIT_16 => X"BBBBBBDDBBDDDDDDBBBBBBBBBBBBBBBB99997788777709007788550777007700",
INIT_17 => X"99097788778805099977770977007788998899BB888899BB778899BB99BBBBBB",
INIT_18 => X"0B88055588778855887707770588090B00770477880B778888770B7788885500",
INIT_19 => X"330B880B000B0B778877778888DDDDFFFFFFFFFFFFFFFFFFFFDDDDDDDD889999",
INIT_1A => X"1000770477880B5588889988998F0D0B886B990B880B07B609990B8855888800",
INIT_1B => X"887788770700770B88880788880977880B777788000B7788448888077700BB99",
INIT_1C => X"888833007788770788BB8F8888BB8F7D8F888FBBDD8F8F88886B7788090B0777",
INIT_1D => X"00990900990909770088557709990B09777788770B8807090B880B887788770B",
INIT_1E => X"8807880D770988009988550B0B009988098800995509770B0077007709008877",
INIT_1F => X"77770B04097709775577770B880755887777007755098855880B6B0077000B99",
INIT_20 => X"BBDDBBDDBBBBDDBBBBBB88BBBBDDBBBBBB999999775588777777007777097709",
INIT_21 => X"778877770977075588770B88779988888899BBDD88BB88BBBBBBBB99BBBBBBBB",
INIT_22 => X"DD88DD888F9955880077098800097709880B7700090B99775509007799887777",
INIT_23 => X"09887700880B0B0077DD88DD888F88DDFFFFFFFFFFFFFFDDDDFFFFFFFFFFFF88",
INIT_24 => X"000B0B88998888BB88888F888F6B880B880B6B8888BB8F888F88999977887788",
INIT_25 => X"887788550B7788550955880B0955998877777777097788880B7788000901F899",
INIT_26 => X"88770B007700770B888FBB8FDDFFFFFFFFDDFFFFDDFFDDDDBB88887D0955880B",
INIT_27 => X"0F996B7D889988770B7755887777990077057788090B00550088777777777777",
INIT_28 => X"0B885577887777770B88778877886B009988889999BB88BBBB8FBBBB888F8877",
INIT_29 => X"8FBBBB99886B8F99888888090B880B88550988777709778877880B9988557777",
INIT_2A => X"BB99BBDDBBDDDD88BBBBBBBBBBBBBB8899998899999909778888078805770755",
INIT_2B => X"8809557777887788770988779999BBBBBBBB88BBBB99BB8FBBBBBBBB99BBBB88",
INIT_2C => X"DDDDDDDDDD88880D8F8877880999007709558899888809000977998800070988",
INIT_2D => X"777755BBBB9988BB8FDDDDDDBB88DDFFFFFFDDDDFFFFFFDDFFDDFFFFFFFFDDDD",
INIT_2E => X"00BB88998F77888F88DDBBBBBB88DD88999908888F88BBDDDDDDDDBB8899880B",
INIT_2F => X"0900090B00770477880B44888888889988DD8F888F8899BB8F990F888F00D799",
INIT_30 => X"770B7777888F8F888F8FFFDD8FFFFFFFDDFFBBDDDDBBFFDDDD888F7788880744",
INIT_31 => X"88888888880888BB88880B88009900990988880B007709770988090B00770777",
INIT_32 => X"885588885507098855880B778899888F880B99888FBBDDDDFFFFFFDD8FBB8F7D",
INIT_33 => X"BBDDDDDDDDBB8888888899887709550B0B88550B88880955007777880988880B",
INIT_34 => X"BBBBBBBBDDBBBBBBBBBBBBBBBBBBBBBBBB996B99888899885555777777097709",
INIT_35 => X"777788886B7D0B09997777999988BB9999BBBBBB997D8899BBDDDDBBDDBBBBBB",
INIT_36 => X"DDDDDDDDFFDD9988880B77999977090077885577098877998877887777997799",
INIT_37 => X"888877887DBBDDBBDDDDDDDDBBDDDDDDFFFFFFFFFFFFDDDDDDDDFFFFFFDDFFDD",
INIT_38 => X"108F888FBB8FDDDDFFDDFFFFFFFFFFDD880D6B9988DDDDFFFFFFDDBB8F888F88",
INIT_39 => X"779977777788770B777788070B7D8F8FDD8FFFDDDDFF8FBB88BB888F880099F8",
INIT_3A => X"007700770B8888DDBBFFFFDDDDFFDDFFFF8FFFFFBBFFDDBB88DD888855778877",
INIT_3B => X"7D888F888F7D888899889988880B99889999778855008877777788777788770B",
INIT_3C => X"7709770009888877000977886B888F99887D8F7D88FFFFFFFFFFFFFFFFFFDDBB",
INIT_3D => X"FFFFFFFFFFFFFFFFDDDD885500887777887777880B0777880777885577075588",
INIT_3E => X"BB88BBBBBBDDBBBBBBBBBB99BBBB9999BBBB9999999999770909550588558855",
INIT_3F => X"889999998899998888887D7799BB99998888BB998F88BBBBDDBBDDDDBBBBBBBB",
INIT_40 => X"DDDDFFFFDDFFDDBB9988BB88889977990B778877007700098809776B8F880B88",
INIT_41 => X"777788BB88FFBBDDDD8FDDBBDDDDBBFFDDDDDDDDDDDDDDDDDDDDDDDDDDFFDD8F",
INIT_42 => X"1099BBDDDDDDDDFFDDFFFFFFFFFFFFFFBB88886BBBDDDDDDDDFFDDFFDDDDBBBB",
INIT_43 => X"888F8888886B88888F9988998888BBFFFFFFFFFFFFFFFFFFFFFFFF88DD00D799",
INIT_44 => X"888FBB888F8F8FBB8FDDFFFFBBFFFF8FFFFFDD8FDDBBFFDDFF88DD88888F7D88",
INIT_45 => X"DDBBDD8F88888F8888880F886B8899880B880B99998F886B99880F887D778F88",
INIT_46 => X"88778899887755888F88886B8888888F7D8888DDDDFFFFFFFFFFFFFFFFFFFFFF",
INIT_47 => X"FFFFFFFFFFFFFFFFFFDDDD8F888F8809550B0B77888800777788000900770B77",
INIT_48 => X"BBBBDD99BBBB888F99BB99BB888899996B88998F99999988B677070988778877",
INIT_49 => X"0B889999997799886B999988BB0999090B9999999999BB8888BBBBBBBBBBBBBB",
INIT_4A => X"BBDDDDFFDDDDFFBBBBBBDDBB88BB999999098877888877886B88779999779988",
INIT_4B => X"DDDDDD8FDD88BBBB8F88BBDD8FDDDD8FDDDDDD8FDDDDDD88BBDDDDDDDDDDBBDD",
INIT_4C => X"00DD8FDDDDBBDDFFDDFFFFFFFFFFFFFFFFDDBB8FDDFFDDDDDDDDDDDDDDFFDDFF",
INIT_4D => X"888FDD888F888F8888888888DDDDDDFFFFFFDDFFFFFFDDFFDDFFDDDDDD00D799",
INIT_4E => X"DD8F8F8899DDDDDD88DD8FDDDDBBDDDDBBDD8FBBFFDD8FDDDDDDDDDDDD8F888F",
INIT_4F => X"FFFFFFFFFFDDFF8FBB887D8F6B888899887D8F7D888FBB8F8F888FDDDDDDDDDD",
INIT_50 => X"88997777887709887D88887D8FDDDDFFDDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_51 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFDD885577007777778807778888777700770977",
INIT_52 => X"88BBBBBBBB88999988778F88998F999999998877880B77098808775577075509",
INIT_53 => X"8899997D88BB8899776B889988998888887799886B999999BBBBBBBBBBBBBBBB",
INIT_54 => X"DDDDFFFFFFDDDDDDDDBB88BBDDBB88889988770B9977886B8899999988888899",
INIT_55 => X"DDDD8FBBDD8FDD88BB8F8FBBDD88DD88BBBBDDBBBBDD88DDBB8FDDBBDDBB88BB",
INIT_56 => X"10DDBBFFDDFFFFDDFFFFFFFFFFFFFFFFFFFFDDBBDD8FDDBBDD88DDDDDDDDDDDD",
INIT_57 => X"6BBB88FFDDFFDDDDBB998FDDDDFFFFDDFFFFFF8FFFDDFFDDFFDDFFFFDD00BB99",
INIT_58 => X"DDDDBBBB888FBB88DD8FDDDD88DD88DD8F88DDDD88DDDDDDDD8FFFFFFFBB0D77",
INIT_59 => X"FFFFFFFFFFFFFFFFFFDD88BB88DD8FBB8F888888BB88DD8FDDDDDDFFFFFFFFDD",
INIT_5A => X"778800880B8888BB778FDDDDDDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_5B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFF8F887D88887D88889988886B888899998F88",
INIT_5C => X"BBBBBBBBBBBB88BBBB9999BB9988BBBB998899998F7788770577098877777777",
INIT_5D => X"99998888998F9988BB9999887777999999886B7777888F8888BB99BBBB99BB99",
INIT_5E => X"BBDDDDDDDDDDDDDDBB8F8F88887D887D889988999999998899886B8F8F77770B",
INIT_5F => X"DDDDDDDD88BB888FBBDD998FDDBB88BB88DDDDDDDDDDDDBBBB88DDFFDDDDBBDD",
INIT_60 => X"008FFFDDBBDDDDFFDDFFFFFFFFFFFFFFFFFFFFDDBBDDFFDDDDBBDD8FBBDDDDFF",
INIT_61 => X"88BBDDFFFFFFFFFF8F8888FFBBFFDDFFFFFFFFDDFF8FFFFFFFFFFFDDDD00D7F8",
INIT_62 => X"DDDD888FDDBBBB8FBBBBDD8F8FBB8F88DDFFDDDD8F8FDDDDDDFFFFFFFF8FBB88",
INIT_63 => X"FFFFFFFFFFFFFFDDFFDDDD8F8FBBBBBBBBBBBBBB8FDDDDDDFFFFFFFFFFFFFFFF",
INIT_64 => X"886B998899998FBBBBDDDDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_65 => X"FFDDDDFFFFFFFFFFFFFFFFFFFFFFFFBB888888776B6B886B8888996B888F7700",
INIT_66 => X"BBBBBB99998899998888998899BB99888F999988779999887788777700770077",
INIT_67 => X"88996B99BB8899998F887D9988998899BB8F88BB889977998FBB8899889999BB",
INIT_68 => X"BBBBDDDDDDDDBBDDBBBB888F88998F99998F88BB99888F998F99887788888899",
INIT_69 => X"FFFFFFDDDDBB88BB88BBBB8888888F888F888F8FDD7DDD88BBBBBBDDDDDD8FBB",
INIT_6A => X"00DDDDFFFFDDDDDDDDDDFFFFFFFFFFFFFFFFFFDDDDDDBBDDDDDDBBBBDDBBBBDD",
INIT_6B => X"8F88BBBBFFFFFFFFFFFFDD8FFFDDFFFFFFFFFFDDFFDDDDFFFFDDFFDDFF01F899",
INIT_6C => X"DDDDDDDD8F888FDD888FDD88DDDDBBFF8FDD8FDDDDDDDDDDDDFFDDFFFFFFFFDD",
INIT_6D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF8FFF8FFFFFFFFFFFFFFFFFFFFFFFFFBB",
INIT_6E => X"7788888F888FDD8FFFFF8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_6F => X"DDDDDDFFFFFFFFFFFFFFFFFFFFFFFFFFDD88BB7D88886B88886B8888998888BB",
INIT_70 => X"BB8899888899997D8888BB999999889977889999889988BB888877770B550B55",
INIT_71 => X"9988BB6BBB888F7D9999BB99889988DDBB88BBBB8888996B8899998899888899",
INIT_72 => X"DDDDDDBBDD88BBBB99BBBBBB88BB997D88BB888899889999999988998F7D9988",
INIT_73 => X"8FDDFFDDDDDDBBDD88BBDD8FBB8F888888BB99BBBB7D88BB8F88BBDDDDDDDDDD",
INIT_74 => X"10DDDDDDFFFFDDDDBBDDDD88BB88DDDDDDDDDDFFDD8888DDDD8FBBDDBB88DDDD",
INIT_75 => X"FFFF8FFFFFFFFFFFFFFFDDFFFFFFFFDDFFDDFFFFFFFF8FFFDD8FDDFFDD0099F8",
INIT_76 => X"DDDDDDDDDDDDDD8FBBDDDDDDDDDDBB8FDDFFFFDDDDDD8FFFDDFFBBFFDDFF8FFF",
INIT_77 => X"FFFFFFFFFFFFFFDDFFFFDDFFFFFFDDFFBBFFDDFFFFFFFFDDFF8FFFDD8FFFDDDD",
INIT_78 => X"BB88DDFFFFFFFFFFFFBBDDBBBBFFDDFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_79 => X"DDDDDDFFFFFFFFFFFFFFFFFFFFFFFFFF8FDD888FBB886B8888886BBB88BB88BB",
INIT_7A => X"8F99999999889999999999BB999999997D9999997DBB9988D7770D7788778877",
INIT_7B => X"99999977998F887788886B889988BBBBBBBB8F778899887799BB999977BBBB8F",
INIT_7C => X"DDBBDDBBBBBB888F8F88997799888F88BB888F7788990BBB886BBB778888886B",
INIT_7D => X"DDFFBBDDDDBBBB8FBB889988888F88BB888F888F8F77888F88BB8888DDDDDDDD",
INIT_7E => X"10DDFFFFBBDD8FDDBB88BBBB8F888FDD88DDDDDDFFDDDDBB88BB8FBB8FBBBBBB",
INIT_7F => X"8FDDDD8FDDFFFFFFDDFFFFDDFFDDBBFFFFFFFFDDFFDDDDDDDDDDDDFFFF00D799",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[11]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized6\ is
port (
\douta[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized6\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized6\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized6\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"8FDDDDDD8F88DDDD8F8FDD88888FBB88DDDDDDBBFFFFDDFFFFFFFFDDDDFFFFDD",
INIT_01 => X"DDFFFFFFBBFFFFDDDDFFFFDDDDFFFFFFFFDDFFDDFFDDFFFFDDFFBBFFDDBBFFBB",
INIT_02 => X"8FDDFFFFFFFFFFFFDD8FBB8FFFDDFFFFFFFFFFFFFFFFFFFFFFFFFFFFDDDDDDDD",
INIT_03 => X"DDFFDDFFFFFFDDFFFFFFFFFFFFFFFFFFDDDDBB88888F888F8FBB888F88888888",
INIT_04 => X"99889988888F88998888999988999988770B997799888F8F8877777777097709",
INIT_05 => X"7D88996B88779999779999BBBBBB88BBBB99889999999999886B889999889999",
INIT_06 => X"DDDDDDDD88BBBBDD88BB8FBB8899998FBBBB888F9988BB77BB88998877999999",
INIT_07 => X"BBBBFFDDDD8FDDBBBBDDDD8FBB88BB8FBB88BB88888899998F88BBBBDDBBFFDD",
INIT_08 => X"00DDDDDDFFBBDDDDDDDD8FBBBBDDBB8FDDDD8FDD8F8F888FBB8888BBBB88BB8F",
INIT_09 => X"DDDDDDFFFFDDDDFFFFDD8FDDBBDDDDDDDDFFFFDDFFDDFFBBDD88FFDDDD0077F8",
INIT_0A => X"DDDD8888DDDD7DDD88BB88DDDDDD8FDDBB8888DDDDBBDDBB8FBBFFFFFFFFFFDD",
INIT_0B => X"DDBBDD88DDDDDDDDDDDDFFFFFFDDDDBBFFDDDDFFBBFF8FDDFFDDFFDDDDFFDD8F",
INIT_0C => X"88DDDDDDFFFFDD8F88DD88DD8FFFFFFFFFFFFFFFFFFFFFFFFFFFFFDDDDBB8FDD",
INIT_0D => X"DDDDFFDDDDFFDDDDFFFFFFFFFFFFFFFFFF8FDDDDDD8888BBBB8FBB888FDD8FBB",
INIT_0E => X"BB999999BB9999BBBB998FBBBBBB8899BB888899BBBB99999977880988778877",
INIT_0F => X"77990B8899998F8F88886B887D999977778F999977886B88BB99998F0B997D77",
INIT_10 => X"BBDDDD88BB8FBBBB99BB9988BB8F88BB88BBBB8899BBBBBB88999999BB888F99",
INIT_11 => X"DDDDDD888FBBBB8FBBBBBB8888BB888877BBBBBBBB997D8888BB778F88BBBB88",
INIT_12 => X"00BBDDDDDDDD88DD88BB88BB888F88DDBB88DD88DDBBBB8899889988998F88DD",
INIT_13 => X"DDDD8FFFDDDDFF8FDDDD88DD8F88BBDDFFFFDDDD88BB888FBBBBDDFFFF00D799",
INIT_14 => X"8FBB8FDD7DBBBB88BB888F8888BB88888FDDDDDD88FFBBFFDDFFFFFFDDFFFF8F",
INIT_15 => X"8FBB88BBFF88BBDDFFDDDD8FBBDDFFDDDD8FFFBBFFFFDDFFBBDDDDDDDDBBDDDD",
INIT_16 => X"DDBB8FBBDD8FBB88DD888FFFFFFF8FFFDDFF8FFFFFFFFFFFFFFFFFFFDDFFDDDD",
INIT_17 => X"DDDDDDDDFFDDDDDDDDFFFFFFFFFFFFFFDD888FDDDDFFDDFFFFDD8F8FBBBBDD88",
INIT_18 => X"9988999977BBBB888FBBBBBB9988BB99888F88BBBB997D9999888888770B770B",
INIT_19 => X"BB990B9988BB996B8899BB7799888F88BB9977774799889999998F779988886B",
INIT_1A => X"DDBBBBBBBBBBBBBB8F888F88BB888F88998F8F8F8899997D88998FBB888F8899",
INIT_1B => X"88BB8FDDDD88BBDD88BBBB88DDBB888899889988BB88BB88888F887788BB8F88",
INIT_1C => X"00DDDDBBDDDD8FBB8FBB888F88BB88DD88DDDD888FBB8888886B996B7799BBBB",
INIT_1D => X"DDFFDDFFFFFFFFFFDDDDFFFF88DDBB8FDD888F8888887D88DDDD88BBDD00D7F8",
INIT_1E => X"888F88887D9977887799778888778888BB8888DD8F88888FDDDDFFBB8FDDFFFF",
INIT_1F => X"BB8F88DDBBBBDD888FDD88DDDDFFDDDDFFBBDDBBDDDDDDFFBBDD8888DDDDDD88",
INIT_20 => X"888FBB8F888FDD7DDD888F8888FFBBDDDDDDDDDDDD8FDDDD8FFFFFFFDDFF88BB",
INIT_21 => X"BBDDDDDDDDDDDDBBFFDDDDDD88DDDDDDDD8F888FDDBBDD88BBDDDD888FBBBB8F",
INIT_22 => X"997D998F8F88DDBBBB88BBBBBBBB888FBB99BBBBBB997799098F997788778877",
INIT_23 => X"889999BB9988778899886B9999999999778F99886B778F99778888996B999977",
INIT_24 => X"7D88BB8F88BB8F888899BBBB88BB998F8888778899889988BB88998899889999",
INIT_25 => X"BBDDDDBB88DDBBBB8F88DDBB888FBB8F9988889988997D999988997D888888DD",
INIT_26 => X"00DD8FFF888FDDBBDDBBF8888F88BBBB8F8888BB888FBB6B999988886B998F88",
INIT_27 => X"FFFFFFFFFFFFDDFFDD8FFFFFDD8FBBDD888F99BB8FBB88BB88BBDDDD8F01F899",
INIT_28 => X"BB886B99777788770B886B9999889999BB8888BB88DDDDDDDD8FDDFFDDFFFFDD",
INIT_29 => X"DDBBDDBB888F88DDDDBBFF88DDBBDDBBDDDDDDFFBBBBDD8888BBDD8F88BB9988",
INIT_2A => X"BB88BB88BB88BB88DD88BB88DD88DD8FDDBBBB888FDDDDDDDDBBDDDDBBDDDDDD",
INIT_2B => X"DDBBBBBBDDDDDDDD88BB88DD8FBB88DDBBDDDDBB998F88BB8F88888F88888F88",
INIT_2C => X"999977777799BB88BBDDBB88888F8F7799BBBB8FBB99BBBB8877880977777777",
INIT_2D => X"996B88BBBB8FBBBB99BB99888F887D8899886B998899598877998F99887777BB",
INIT_2E => X"88BB8FBBDD8F88BBBBBB886B997D8888778F99997D6B88998899888F99889988",
INIT_2F => X"8FBB88BB8FBBBB8FDDFF8F88BBBB88BB8899888FBB8F888888998877998FBBBB",
INIT_30 => X"00DDDD88BBDDDD8FBB8F8888BBBB8FDD88BBBB888F8899886B886B9999888899",
INIT_31 => X"FFFFFFFFFFFF8FFFBBFFFFDDDD8888BB88BB888F7788DD88DD8888DDBB00D799",
INIT_32 => X"889988990B990977880B478888776B99888F8F888F88BB88DD88DDBBFFDDDDDD",
INIT_33 => X"BB88DDDDFFDDDDDD88BB8FDDBB88DDDDDDDDFF88DD8F88DDDDBB8FBB888F7D88",
INIT_34 => X"88BB88BB88DD888F88BB778F888FBB88BB8FDD8FDD888F88BBFFBB8FDDDDDDBB",
INIT_35 => X"88BB888F88BBDDBB8F8F8888BBBBDD88DD88DD888FBB888FBB888F88888F8888",
INIT_36 => X"9988778888F88899BB99BB8F999988F8BB88BB9999BB887D77770988770B770B",
INIT_37 => X"8877999988BB888F8899887D8899997D8F778877998899779988779999998F88",
INIT_38 => X"BB88BBBBBB99BBBB88BB99888F88BB8F889988998877990B7D9999887799998F",
INIT_39 => X"88BBDDDD88DDDD88DD888FBB888F99886B888F998899997D8F99997799779988",
INIT_3A => X"10FFBBDD8FBB8F88DD88BB888F88BBBBDD8F8FBB8899888F886B880B8899888F",
INIT_3B => X"FFDDFFFFFFFFFFDDDDBBFFBB88DD8F888FBBBB88BB888F88DD8FBBBB880099F8",
INIT_3C => X"990B990988887788998888776B08880B998888BB88888F88BBDD8FDDDDBBFFFF",
INIT_3D => X"FFDDDD8FDDBBBB8FDDDDBB88BB8FBBDD888FDDDDBBDDFFBB888F8888BB887799",
INIT_3E => X"8F888F888F88BB88BB8F88998F888888DD8888BB88BB88DD88DDDD88BB8FDDDD",
INIT_3F => X"998F8F99888FBB88BBBB88BB888F88DDBB8F8FBB88BB8FBB8F88BBDDBB888FBB",
INIT_40 => X"99D76BBB6B88888F9999BB778F999988BB88BBBBBB99BB997707999999999999",
INIT_41 => X"8899BBBBBBBBBB8899BB886B99BB888F77888899888899886B777799990B9999",
INIT_42 => X"998F99BBBB888F8F8899888F886B9999888888999999998899888888000D6B99",
INIT_43 => X"88BB8888BB8888998888889999886B998F997D8888888F998F9988886B8F888F",
INIT_44 => X"0088BBFFBB8888BB88BB88888F887DBB888F8F8899777D8F7799888899889999",
INIT_45 => X"DDDDDD8FFFFFFFBBFF888F888899BB998FBB889988887D8F8F888F88BB0077F8",
INIT_46 => X"6B88998888778877880988998877887709887D88BB8F88BBBBBB7DDD888FDDDD",
INIT_47 => X"DDDDBBDD8FDDDD8FBBDDDD8FDDBB8888DDBBBBDDBBDDBB8FBB88BB8F888F8899",
INIT_48 => X"BB8FBBBB88BBBB888F88886B9988BB8F88BBBBBB88BB88BBDD8FBBDD88DD88DD",
INIT_49 => X"BBBB997D99BB9988998F88888F888F888F8888888F8F8FBB88DDDDDD8888888F",
INIT_4A => X"995988998899999988886B88777788778FBB99BB88886B889988990B99889988",
INIT_4B => X"BB7D77DD88DDDDBB88889999990B778899998F99779977098877887788770B77",
INIT_4C => X"9988998F7799998888999999998899998F998F0B998F9988887D8F99BBBBBB88",
INIT_4D => X"8F88BBBB88BBBB8F8F997D8899998899778877998F9977089988999999889988",
INIT_4E => X"008F8F998888888FBB887D8F8899888899BB99888F99888808888F7709888888",
INIT_4F => X"DDDD8FDDDDDD8FDDDDDDBB8F8F8888889988886B88887788998899998F00D799",
INIT_50 => X"887707777709090077887707770B7777889977776B99888FBB88888F88BBBB8F",
INIT_51 => X"88DD8888DD88BBDD88BBDD888FBB8FDDDD88BB8F88888F8888BB88BB8899996B",
INIT_52 => X"888888888F88888FBB88BB88886B88886B888F778F888F88DD888888BBBBDD8F",
INIT_53 => X"7D8F88BB88BB888F889988BB888899DDBBBBDDBB888888BBBB88BB8888BBBB77",
INIT_54 => X"0B7799BB99999988999977777D99999988779988999988998F77779977997799",
INIT_55 => X"BB99DDBBDDBB8888BB99887DBB99888F8F888899889988997799097709997788",
INIT_56 => X"99998888BB8F99998F889988999988887788BB88BB88996BBB77998899998FBB",
INIT_57 => X"99998888BB998F8899BB77BB990B998899997799770B88BB88990B99886B778F",
INIT_58 => X"1088888F888FBB8888BB77887D888F7D887788BB7777888F996B888877888877",
INIT_59 => X"BB88BBBB8F88DDFF8888BB88888F8FBB8F9999886B6B888888888F889900BB99",
INIT_5A => X"990B880B887777990B770077007788880999997D88777D888F998F77BB888F88",
INIT_5B => X"BB8FDDBBBB8FDD88DDBBDDDD88DDBB8F888F88BB888888BB8FBBBB887D990899",
INIT_5C => X"8F997D99887D8F88888F888FBB886B7D889999888899889988BB8F8F88DDBB88",
INIT_5D => X"99BBBB88DD8FBBBBBBBB8F88BB8F888FBBDDDD8FDDDDBB8FBB888F8F88BB8F8F",
INIT_5E => X"9999888F0F886B99BB9988BB99888899BB8F6B998F99999988886B886B886B88",
INIT_5F => X"88BBBBBBDDBBBB9988999999886B9988779977889999990B998899887788990B",
INIT_60 => X"886B99998899888F88BB6B997D88BB88BB886B99889988998F9988BB888888BB",
INIT_61 => X"998899BB777D99888F8F998899886B6B8F0B9988998899776B88770B77888877",
INIT_62 => X"008F8FBB88BB8FBB88888F88999977777D997D77996B6B8877999999886B0900",
INIT_63 => X"888F888888DDDD888F8F888F8F88888877888F88999999886B8888777D00D7F8",
INIT_64 => X"88550988770B09885509770B09777777889988998F7D99BB8888BB998899778F",
INIT_65 => X"DD88BBDDBBBB8FBBBB7D8888BBBB88BBBB888F88BBBBBB88888F889988888888",
INIT_66 => X"8888997D8899888F8899887D0B7788776B88888FBB6B887D998888888F8888BB",
INIT_67 => X"8888BBDDBBBB88DDBBBBBBDD88DD8FDD8FBBDDDD8899BBBB88DD8888BB8888BB",
INIT_68 => X"990B778F8FF88899779988999988887777999999999988597D77779988778877",
INIT_69 => X"BB77BBBB8888BB889999889988778F888F8F885988770B9977D7990B880B9977",
INIT_6A => X"886B88BB888F8F88BBBBBB88BB998FBB88998FBB8899998899999988889999BB",
INIT_6B => X"99770B77990B9977889977BB7D99777799776B889999990B0B88778877778877",
INIT_6C => X"0077099977777799777709770555777799770977D70777077777997777888F99",
INIT_6D => X"9988998FBB0B778899888F99999977889999998877887D998F7777779900D799",
INIT_6E => X"097755777755777777777D55556B777D770B776B77770B775577037777557777",
INIT_6F => X"BB88BBBB88888899BBBB8888888FBBBBBBBBDD8FBBBBBBBBBB99777777779977",
INIT_70 => X"BB888F8F88BB88998899990B8809777788888899778888779977778877888F88",
INIT_71 => X"DDBBBBDDBB88BBDD8F888FDDDDDDDDBBFFBBDD8FDDDDDDFFDDFFDDDDDDBBDD88",
INIT_72 => X"7788997788886B998888770B99098F88990099886B996B8888778877990B990B",
INIT_73 => X"997D8888BBDD8F77BB8F99889999887D88089999998877888899999977770B88",
INIT_74 => X"BBBBBBBBBBBBBBBBBB99888FBB88BB8F9988888899887D99887D888F8F887D77",
INIT_75 => X"7799770977D70777888F990B770B99990B9977770909887788990B9999886B88",
INIT_76 => X"1077770955775555556B555555097705470555550955556B0977050977095577",
INIT_77 => X"555577997777095577777799770909778F7777777777777777779977070099F8",
INIT_78 => X"556B555507550B770755097755556B4705996B475555777D7705596B55070B55",
INIT_79 => X"998F77889988888F77888FBB8F888FBB8F8F999999777777770777777777550B",
INIT_7A => X"88DDDDBBDD88888F8808098877778899880999990B880977990B997D990B88BB",
INIT_7B => X"DDBBDD88DDDD88DDBBBBDDDDDDDDDDFFDDFFDDDDDDDDDD88DDDD8888888FBBBB",
INIT_7C => X"999977997777778877999977889999990BBB9999889988999999778877777777",
INIT_7D => X"99999999998899889988998F99996B77779909770B9999777788888899887799",
INIT_7E => X"88BB88BBBBBB88BB88BBBBBB8F88BB888F888F8F889988999977997799BB99BB",
INIT_7F => X"05470555550955550955777799777777D707770777779999097777886B778899",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[11]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized7\ is
port (
\douta[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized7\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized7\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized7\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"1055037705557D5507470F336B746B770F77556B770977475509777405770977",
INIT_01 => X"090F77073309550555077707559555354755350555550955555509055500D799",
INIT_02 => X"475555596B777D4777777D556B595555740F5509776B5555557703556B55776B",
INIT_03 => X"88BBBBBB8F8F8888BBBB8899BBBB88BBBB99777799077759556B550905777777",
INIT_04 => X"BB887DDD88DDBBBB8888BBBB9908098877770809887777880988887777887799",
INIT_05 => X"88BBDDDDBBBBDDDDBBDD88BBDDFFDDBBBBBBDD88BB8899888899880B77778888",
INIT_06 => X"0B7788888899990B998899887788888899999999997799886B88889988778877",
INIT_07 => X"889988886B99998F779999889988778888999988776B889999B60999776B8877",
INIT_08 => X"BB8FDDBBBB8FDD8FBBBBBB8888BB8F8899998899990B998888998F8888777799",
INIT_09 => X"770F77556B77097777097755470555550977556B5577057777778847880D99BB",
INIT_0A => X"000755597707095577557709596B477755776B053377550555770F6B556B746B",
INIT_0B => X"777755597D556B475555770B0703556B550509554755770755055577050077F8",
INIT_0C => X"556B5955505955556B5577076B6B776B550505770F476B5547596B7759095547",
INIT_0D => X"770D888899889988BB8F888F7D88999977776B5547775547056B558F55555509",
INIT_0E => X"88998888DD88BB887D9988008877090B770B887D8888000B0809990B9988778F",
INIT_0F => X"DDBBDDBBDDBBDD88DDBBDDDDDDDDBBDDBB888899880B8877880B778800770977",
INIT_10 => X"8877997788888877998877996B8877000B7777990B99777D7788888899779977",
INIT_11 => X"99886B9988998F8899886B99996B7788887777889977990B9988777799777788",
INIT_12 => X"779999BBBBDDBB88BBBB8F88BB88BB88998F8F8F998F8899886B9988888F8877",
INIT_13 => X"55550F55556B0F05356B476B557705053395550555770F550947050955070909",
INIT_14 => X"1035070577550955330F77075950555505770F557D5555095555555500775505",
INIT_15 => X"0599950B55070555556B4755777755076B35773307557755093307073300BB99",
INIT_16 => X"77555555777D33555577595559555555090747556B55557747550F595509776B",
INIT_17 => X"770B000B08990B8888888F8877097707556B470F7777777D330F770555740755",
INIT_18 => X"887788880988880B778877098877880009770B7788770900778877097788880B",
INIT_19 => X"BBDDDD88BBBB8FDDDDDDBBDDDDBB880B880B8888770088777700098809887777",
INIT_1A => X"6B7788779999990B8899990B77990BDD99999988997799889977099988778877",
INIT_1B => X"6B9988996B997777889988998877888F00887709778899779909880788779977",
INIT_1C => X"09777799BB88BBBBBBBB88BB88BB8FBB889988889999990B998899B6888888BB",
INIT_1D => X"5505770F557D555577550547550F74556B7D056B6B0F5533470F550F77555505",
INIT_1E => X"007D3577057707558F555577470F550F7755550547779977550F7D0977075055",
INIT_1F => X"99556B7D5933470B7777056B070555475507033533055505550555330F00D7F8",
INIT_20 => X"0F557D0F55556B550D0B7D550555078F7755595535596B476B555059770F5533",
INIT_21 => X"0B888877000988990B887777556B777755777755550B77355555055509776B55",
INIT_22 => X"050B5507770B9988999988880B88090B880988990B88888F8809778800770899",
INIT_23 => X"BB88DDDDBBDDBBDD8FDDDD88990B777799880B99888F0B88770B885588770B00",
INIT_24 => X"7709778888778877997788999988888888996B77886B77998899880977777777",
INIT_25 => X"88776B998877998F779999779977D7889999779988778877889977997799770B",
INIT_26 => X"7705099977778888BBBB99BB998888998F888F998888998877990B77D7990B99",
INIT_27 => X"0F775555054777990750550F057705557D3355095555550F5555057409050977",
INIT_28 => X"00550509770999053305555555550574090509775305055555445555096B0F55",
INIT_29 => X"55053533475507477D095555359505330955550B33094755095507335501F899",
INIT_2A => X"770555555555596B5577555977075555555555550747556B0907555505555907",
INIT_2B => X"88990B000988770B8877550709555555050F770F776609056B55557777775305",
INIT_2C => X"080988778888880B777705007709995588770B77880500770999008809880009",
INIT_2D => X"BBDDBBBBDDDDDDBBDD88BB7788880B0B880B8877057777090055888809880077",
INIT_2E => X"7777887709997799999999880B09F877778F77886B88880B77097777880B880B",
INIT_2F => X"8FBB886B776B887799990B8899880D7788997788770B9999777D8F7788888877",
INIT_30 => X"0547740907096B8F998FBB88998FBB888899888877778F996B9999BB090D8877",
INIT_31 => X"550F5907740977556B0F55557755770547099977050F7D350905774777550744",
INIT_32 => X"00056B770533095555590507090577477755074409475533538F056B77055509",
INIT_33 => X"075595090709770955557705777709550574090777770555053347550F00D799",
INIT_34 => X"09556B0F474755555977075505596B050F55550F77550F476B77770F55777759",
INIT_35 => X"770B88097777007777440977476B7777779909555559775555555507550F7759",
INIT_36 => X"0988098809077777000B08990B888800770B77007708995588880B77770B0988",
INIT_37 => X"099988DDBB88DDBBBBBB090B077777887777770B08550B880B00770988098888",
INIT_38 => X"9909997777880B77776B77887709778899998F59990877998888558877887788",
INIT_39 => X"997D77999999887799889988998899559988887777770988777788770D88000B",
INIT_3A => X"74050755055577030D55554777997D6B888F99889977996B990B77887788776B",
INIT_3B => X"05555577950977070F550F530774050755050947055509770905770F55555305",
INIT_3C => X"100B050755050947055509770905770F555553050705097455000B7707555509",
INIT_3D => X"0555550F0577770F55595505770755090747350577774409055959550F00D799",
INIT_3E => X"550F055953556B475559550B0555098F070735056B0977097D47557755553309",
INIT_3F => X"07770955097777097777555577530F5555550555555555555577550555557755",
INIT_40 => X"770B0088077709880B8800778809887700090B770B0988070B88090707777709",
INIT_41 => X"887799099977886B7709000D770D998877770B88990B8888770B888807770988",
INIT_42 => X"77887788008F998899889999778899770B998899887D8F880999777709770977",
INIT_43 => X"7799996B77778F99889909990B997788779999880B887777880B058855779977",
INIT_44 => X"0955556B55778F9974550F7405557777778899999988998888998888887D8877",
INIT_45 => X"09550F3235095577555333550709557709745577090F5532094755550F535599",
INIT_46 => X"008F0F7709745577090F5532094755550F5355990755550933008F3377090755",
INIT_47 => X"05770977770974440905550F77747755553377093309057707475533770077F8",
INIT_48 => X"0555550F55336B6B55596B44597705557747094755775599035577556B054759",
INIT_49 => X"7709776B775555770D356B770F05330F7733770F330509355509033509770559",
INIT_4A => X"8877097788090955880777007755770977098888777777887777558877050977",
INIT_4B => X"057709770B5577770B77997777888805880B8809007709770077777788090955",
INIT_4C => X"0B7799779947779907779999997777887799BBBB997788888888990988778877",
INIT_4D => X"99990B5977998888999988777777888F097777777709777777D7880977777788",
INIT_4E => X"747D7755775577050747777D9909555555559909999999777799070977997799",
INIT_4F => X"550F33590F05053305337D0955747D0907557709553335590577050555330905",
INIT_50 => X"0055740907557709553335590577050555330905557D0F745500555509070F77",
INIT_51 => X"095507050F557D0977770955050709770F5305777755950F770533770500D799",
INIT_52 => X"09770777050F555509595555355509770905557705330F7755550B5959775359",
INIT_53 => X"55770D0F553303743577094777555505500D535577777705557D550905775347",
INIT_54 => X"0777770955777777777707070999097777777707777709557709995500777755",
INIT_55 => X"8888770977888809770B8800000B77880B770977770577770777090955777777",
INIT_56 => X"88770B990B0B0988770B889999880B7799889999888899997777097777777777",
INIT_57 => X"0999887799887D776B9999779988098888550B88777788090900997788770977",
INIT_58 => X"05230577095955557747775574777D530F740577777709777788998899099988",
INIT_59 => X"555533355555470977055977090523775509740F55338F355533477755057755",
INIT_5A => X"100953775509740F55338F355533477755057755092355055500090577554474",
INIT_5B => X"7707775555073555053307770B9577775507550509050595077709740900BB99",
INIT_5C => X"0577057774740F7777470977590F7709447455056B7433470F0777556B330777",
INIT_5D => X"03743577050F55740959950F7705550735550B59335507330F35075555090705",
INIT_5E => X"7705557705555507556B55777755775509555577050977050977550555445533",
INIT_5F => X"55770988770B07778888778F9988777777777799073303337709777705555507",
INIT_60 => X"997709888877998877887788090077099988BBBB888899880B8877770B770B77",
INIT_61 => X"99770B5588778F097799887799880B000B995588550B7709880B558877777777",
INIT_62 => X"777755050F5505774777476B7705550F533577776B7407093377770709B69988",
INIT_63 => X"550F3377095905770777550F0577776B05555309553333775955050733770F53",
INIT_64 => X"0077556B05555309553333775955050733770F5305770374550077056B050753",
INIT_65 => X"77336B55770F09550F55550777550B770509050F55550707590F35050501F899",
INIT_66 => X"095559555555055555555555550F5907770F334747770977337477740F770599",
INIT_67 => X"09777D550553440977770F5577550B0555098F070735056B0977097D47550533",
INIT_68 => X"55440F33076B5577594459033509336B6B55595555770555778F077735055509",
INIT_69 => X"090777990900558807880059997777557707770B0535055503743533076B5577",
INIT_6A => X"0B778899770B0B770B09779988BB99779999888FBBBB88779977997788778877",
INIT_6B => X"0B777777B60B7788990B99770B77778899777709555588550B77770B88777788",
INIT_6C => X"057755557777770D6B550F530555777435590705740F77775505557777078809",
INIT_6D => X"557459053377533355470533090577033355770755595505770353550F473355",
INIT_6E => X"000709033355770755595505770353550F473355097755097709075503330977",
INIT_6F => X"556B05775555770555093309590F745509770955557705330F53550B7700D799",
INIT_70 => X"77054755770F55770F556B0909557405555555474747740555590F095555556B",
INIT_71 => X"990903777707330577775533096B445977055577470947557755990355770955",
INIT_72 => X"0759770F6B55094759550F5509057753474477076B5959770555777D09470F77",
INIT_73 => X"9077880777998809770755F805770B6B05470944770533555574097705534409",
INIT_74 => X"8877770B09D7778877998899990B77770B77999988998F7788770B8877097709",
INIT_75 => X"55000909007788777777880B77887777090B77887777097755880B7755888877",
INIT_76 => X"7405050577050555530F7705550F550555550FB6077733050977555533770577",
INIT_77 => X"094435550705090953530F557774057747473333093507550547095333535505",
INIT_78 => X"1055777747473333093507550547095333535505770507775533550577474733",
INIT_79 => X"09555907335574550933057747500507775577070905590974550F77550099F8",
INIT_7A => X"33550F0D5505550F44553555773307775505055905470577554705740F550959",
INIT_7B => X"7707550B0555555577330305075555355509770905557705330F7755550B556B",
INIT_7C => X"05997774770F777D4777336B77596B5955097435550F35555577093355775533",
INIT_7D => X"0B097788770B55777777550955555559775577075533470F0707550977073305",
INIT_7E => X"770B0088777777779977996B77777788770999998F9988990B88777777887788",
INIT_7F => X"770777770977777700777788770777009955550977558807075588770B775509",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => \douta[11]\(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized8\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized8\ : entity is "blk_mem_gen_prim_wrapper_init";
end \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized8\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_wrapper_init__parameterized8\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => DOADO(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena_array(0),
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid_blk_mem_gen_prim_width is
port (
\douta[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
\addra[14]\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_mid_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end bg_mid_blk_mem_gen_prim_width;
architecture STRUCTURE of bg_mid_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.bg_mid_blk_mem_gen_prim_wrapper_init
port map (
addra(13 downto 0) => addra(13 downto 0),
\addra[14]\ => \addra[14]\,
clka => clka,
dina(0) => dina(0),
\douta[0]\(0) => \douta[0]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized0\ is
port (
\douta[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(3 downto 0) => dina(3 downto 0),
\douta[3]\(3 downto 0) => \douta[3]\(3 downto 0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized1\ is
port (
\douta[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
\addra[14]\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
addra(13 downto 0) => addra(13 downto 0),
\addra[14]\ => \addra[14]\,
clka => clka,
dina(0) => dina(0),
\douta[1]\(0) => \douta[1]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized2\ is
port (
\douta[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
\addra[14]\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
\addra[14]\ => \addra[14]\,
clka => clka,
dina(0) => dina(0),
\douta[2]\(0) => \douta[2]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized3\ is
port (
\douta[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
clka : in STD_LOGIC;
\addra[14]\ : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
\addra[14]\ => \addra[14]\,
clka => clka,
dina(0) => dina(0),
\douta[3]\(0) => \douta[3]\(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized4\ is
port (
\douta[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized4\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[11]\(7 downto 0) => \douta[11]\(7 downto 0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized5\ is
port (
\douta[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized5\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[11]\(7 downto 0) => \douta[11]\(7 downto 0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized6\ is
port (
\douta[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized6\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[11]\(7 downto 0) => \douta[11]\(7 downto 0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized7\ is
port (
\douta[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized7\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized7\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized7\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized7\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
\douta[11]\(7 downto 0) => \douta[11]\(7 downto 0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bg_mid_blk_mem_gen_prim_width__parameterized8\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
ena_array : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bg_mid_blk_mem_gen_prim_width__parameterized8\ : entity is "blk_mem_gen_prim_width";
end \bg_mid_blk_mem_gen_prim_width__parameterized8\;
architecture STRUCTURE of \bg_mid_blk_mem_gen_prim_width__parameterized8\ is
begin
\prim_init.ram\: entity work.\bg_mid_blk_mem_gen_prim_wrapper_init__parameterized8\
port map (
DOADO(7 downto 0) => DOADO(7 downto 0),
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_mid_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end bg_mid_blk_mem_gen_generic_cstr;
architecture STRUCTURE of bg_mid_blk_mem_gen_generic_cstr is
signal ena_array : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ram_douta : STD_LOGIC;
signal ram_ena_n_0 : STD_LOGIC;
signal \ramloop[1].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[1].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[2].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[3].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[4].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[5].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[6].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[7].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[8].ram.r_n_7\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_0\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_1\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_2\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_3\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_4\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_5\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_6\ : STD_LOGIC;
signal \ramloop[9].ram.r_n_7\ : STD_LOGIC;
begin
\bindec_a.bindec_inst_a\: entity work.bg_mid_bindec
port map (
addra(2 downto 0) => addra(14 downto 12),
ena_array(4 downto 0) => ena_array(4 downto 0)
);
\has_mux_a.A\: entity work.bg_mid_blk_mem_gen_mux
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(3) => \ramloop[1].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(2) => \ramloop[1].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(1) => \ramloop[1].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\(0) => \ramloop[1].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_0\(0) => ram_douta,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_1\(0) => \ramloop[2].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_2\(0) => \ramloop[3].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_3\(0) => \ramloop[4].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(7) => \ramloop[8].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(6) => \ramloop[8].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(5) => \ramloop[8].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(4) => \ramloop[8].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(3) => \ramloop[8].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(2) => \ramloop[8].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(1) => \ramloop[8].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\(0) => \ramloop[8].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(7) => \ramloop[7].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(6) => \ramloop[7].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(5) => \ramloop[7].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(4) => \ramloop[7].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(3) => \ramloop[7].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(2) => \ramloop[7].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(1) => \ramloop[7].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_0\(0) => \ramloop[7].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(7) => \ramloop[6].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(6) => \ramloop[6].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(5) => \ramloop[6].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(4) => \ramloop[6].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(3) => \ramloop[6].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(2) => \ramloop[6].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(1) => \ramloop[6].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_1\(0) => \ramloop[6].ram.r_n_7\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(7) => \ramloop[5].ram.r_n_0\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(6) => \ramloop[5].ram.r_n_1\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(5) => \ramloop[5].ram.r_n_2\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(4) => \ramloop[5].ram.r_n_3\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(3) => \ramloop[5].ram.r_n_4\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(2) => \ramloop[5].ram.r_n_5\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(1) => \ramloop[5].ram.r_n_6\,
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_2\(0) => \ramloop[5].ram.r_n_7\,
DOADO(7) => \ramloop[9].ram.r_n_0\,
DOADO(6) => \ramloop[9].ram.r_n_1\,
DOADO(5) => \ramloop[9].ram.r_n_2\,
DOADO(4) => \ramloop[9].ram.r_n_3\,
DOADO(3) => \ramloop[9].ram.r_n_4\,
DOADO(2) => \ramloop[9].ram.r_n_5\,
DOADO(1) => \ramloop[9].ram.r_n_6\,
DOADO(0) => \ramloop[9].ram.r_n_7\,
addra(2 downto 0) => addra(14 downto 12),
clka => clka,
douta(11 downto 0) => douta(11 downto 0)
);
ram_ena: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => addra(14),
O => ram_ena_n_0
);
\ramloop[0].ram.r\: entity work.bg_mid_blk_mem_gen_prim_width
port map (
addra(13 downto 0) => addra(13 downto 0),
\addra[14]\ => ram_ena_n_0,
clka => clka,
dina(0) => dina(0),
\douta[0]\(0) => ram_douta,
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(3 downto 0) => dina(3 downto 0),
\douta[3]\(3) => \ramloop[1].ram.r_n_0\,
\douta[3]\(2) => \ramloop[1].ram.r_n_1\,
\douta[3]\(1) => \ramloop[1].ram.r_n_2\,
\douta[3]\(0) => \ramloop[1].ram.r_n_3\,
ena_array(0) => ena_array(4),
wea(0) => wea(0)
);
\ramloop[2].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized1\
port map (
addra(13 downto 0) => addra(13 downto 0),
\addra[14]\ => ram_ena_n_0,
clka => clka,
dina(0) => dina(1),
\douta[1]\(0) => \ramloop[2].ram.r_n_0\,
wea(0) => wea(0)
);
\ramloop[3].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
\addra[14]\ => ram_ena_n_0,
clka => clka,
dina(0) => dina(2),
\douta[2]\(0) => \ramloop[3].ram.r_n_0\,
wea(0) => wea(0)
);
\ramloop[4].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
\addra[14]\ => ram_ena_n_0,
clka => clka,
dina(0) => dina(3),
\douta[3]\(0) => \ramloop[4].ram.r_n_0\,
wea(0) => wea(0)
);
\ramloop[5].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized4\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(11 downto 4),
\douta[11]\(7) => \ramloop[5].ram.r_n_0\,
\douta[11]\(6) => \ramloop[5].ram.r_n_1\,
\douta[11]\(5) => \ramloop[5].ram.r_n_2\,
\douta[11]\(4) => \ramloop[5].ram.r_n_3\,
\douta[11]\(3) => \ramloop[5].ram.r_n_4\,
\douta[11]\(2) => \ramloop[5].ram.r_n_5\,
\douta[11]\(1) => \ramloop[5].ram.r_n_6\,
\douta[11]\(0) => \ramloop[5].ram.r_n_7\,
ena_array(0) => ena_array(0),
wea(0) => wea(0)
);
\ramloop[6].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized5\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(11 downto 4),
\douta[11]\(7) => \ramloop[6].ram.r_n_0\,
\douta[11]\(6) => \ramloop[6].ram.r_n_1\,
\douta[11]\(5) => \ramloop[6].ram.r_n_2\,
\douta[11]\(4) => \ramloop[6].ram.r_n_3\,
\douta[11]\(3) => \ramloop[6].ram.r_n_4\,
\douta[11]\(2) => \ramloop[6].ram.r_n_5\,
\douta[11]\(1) => \ramloop[6].ram.r_n_6\,
\douta[11]\(0) => \ramloop[6].ram.r_n_7\,
ena_array(0) => ena_array(1),
wea(0) => wea(0)
);
\ramloop[7].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized6\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(11 downto 4),
\douta[11]\(7) => \ramloop[7].ram.r_n_0\,
\douta[11]\(6) => \ramloop[7].ram.r_n_1\,
\douta[11]\(5) => \ramloop[7].ram.r_n_2\,
\douta[11]\(4) => \ramloop[7].ram.r_n_3\,
\douta[11]\(3) => \ramloop[7].ram.r_n_4\,
\douta[11]\(2) => \ramloop[7].ram.r_n_5\,
\douta[11]\(1) => \ramloop[7].ram.r_n_6\,
\douta[11]\(0) => \ramloop[7].ram.r_n_7\,
ena_array(0) => ena_array(2),
wea(0) => wea(0)
);
\ramloop[8].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized7\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(11 downto 4),
\douta[11]\(7) => \ramloop[8].ram.r_n_0\,
\douta[11]\(6) => \ramloop[8].ram.r_n_1\,
\douta[11]\(5) => \ramloop[8].ram.r_n_2\,
\douta[11]\(4) => \ramloop[8].ram.r_n_3\,
\douta[11]\(3) => \ramloop[8].ram.r_n_4\,
\douta[11]\(2) => \ramloop[8].ram.r_n_5\,
\douta[11]\(1) => \ramloop[8].ram.r_n_6\,
\douta[11]\(0) => \ramloop[8].ram.r_n_7\,
ena_array(0) => ena_array(3),
wea(0) => wea(0)
);
\ramloop[9].ram.r\: entity work.\bg_mid_blk_mem_gen_prim_width__parameterized8\
port map (
DOADO(7) => \ramloop[9].ram.r_n_0\,
DOADO(6) => \ramloop[9].ram.r_n_1\,
DOADO(5) => \ramloop[9].ram.r_n_2\,
DOADO(4) => \ramloop[9].ram.r_n_3\,
DOADO(3) => \ramloop[9].ram.r_n_4\,
DOADO(2) => \ramloop[9].ram.r_n_5\,
DOADO(1) => \ramloop[9].ram.r_n_6\,
DOADO(0) => \ramloop[9].ram.r_n_7\,
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(7 downto 0) => dina(11 downto 4),
ena_array(0) => ena_array(4),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_mid_blk_mem_gen_top : entity is "blk_mem_gen_top";
end bg_mid_blk_mem_gen_top;
architecture STRUCTURE of bg_mid_blk_mem_gen_top is
begin
\valid.cstr\: entity work.bg_mid_blk_mem_gen_generic_cstr
port map (
addra(14 downto 0) => addra(14 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_mid_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end bg_mid_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of bg_mid_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.bg_mid_blk_mem_gen_top
port map (
addra(14 downto 0) => addra(14 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 14 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 14 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 14 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of bg_mid_blk_mem_gen_v8_3_5 : entity is 15;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of bg_mid_blk_mem_gen_v8_3_5 : entity is 15;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of bg_mid_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of bg_mid_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of bg_mid_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of bg_mid_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of bg_mid_blk_mem_gen_v8_3_5 : entity is "5";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of bg_mid_blk_mem_gen_v8_3_5 : entity is "5";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of bg_mid_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of bg_mid_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of bg_mid_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of bg_mid_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 7.0707579999999997 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of bg_mid_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of bg_mid_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of bg_mid_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of bg_mid_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of bg_mid_blk_mem_gen_v8_3_5 : entity is "bg_mid.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of bg_mid_blk_mem_gen_v8_3_5 : entity is "bg_mid.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of bg_mid_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of bg_mid_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of bg_mid_blk_mem_gen_v8_3_5 : entity is 18560;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of bg_mid_blk_mem_gen_v8_3_5 : entity is 18560;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of bg_mid_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of bg_mid_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of bg_mid_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of bg_mid_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of bg_mid_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of bg_mid_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of bg_mid_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of bg_mid_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of bg_mid_blk_mem_gen_v8_3_5 : entity is 18560;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of bg_mid_blk_mem_gen_v8_3_5 : entity is 18560;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of bg_mid_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of bg_mid_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of bg_mid_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of bg_mid_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of bg_mid_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_mid_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bg_mid_blk_mem_gen_v8_3_5 : entity is "yes";
end bg_mid_blk_mem_gen_v8_3_5;
architecture STRUCTURE of bg_mid_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(14) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(14) <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.bg_mid_blk_mem_gen_v8_3_5_synth
port map (
addra(14 downto 0) => addra(14 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_mid is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 14 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of bg_mid : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bg_mid : entity is "bg_mid,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bg_mid : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of bg_mid : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end bg_mid;
architecture STRUCTURE of bg_mid is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 14 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 15;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 15;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "5";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "5";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 7.0707579999999997 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "bg_mid.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "bg_mid.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 18560;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 18560;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 18560;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 18560;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.bg_mid_blk_mem_gen_v8_3_5
port map (
addra(14 downto 0) => addra(14 downto 0),
addrb(14 downto 0) => B"000000000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => douta(11 downto 0),
doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(14 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(14 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(14 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(14 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dac_serial is
port(
SPI_SCK: out std_logic; -- spi clock
DAC_CS: out std_logic; -- chip select
SPI_MOSI_1: out std_logic; -- Master output, slave (DAC) input
--SPI_MISO: in std_logic; -- Master input, slave (DAC) output
--- control ---
data_in_1: in std_logic_vector(11 downto 0);
ready_flag: out std_logic; -- sending data flag
send_data: in std_logic; -- send sine data over SPI
clk: in std_logic -- master clock
);
end dac_serial;
architecture Behavioral of dac_serial is
signal current_bit: integer range 0 to 16 := 0;
signal ready_flag_sig: std_logic := '0';
signal spi_clk_delay: std_logic := '0';
signal dac_cs_delay: std_logic := '0';
begin
process(clk)
begin
if(rising_edge(clk)) then
if(send_data = '1') and (ready_flag_sig = '1') then
ready_flag_sig <= '0';
dac_cs_delay <= '0';
DAC_CS <= dac_cs_delay;
elsif ready_flag_sig = '0' then
if(spi_clk_delay = '1') then
spi_clk_delay <= '0';
else
spi_clk_delay <= '1';
current_bit <= current_bit + 1;
case current_bit is
-- don't cares
when 1 => SPI_MOSI_1 <= '0';
when 2 => SPI_MOSI_1 <= '0';
-- command
when 3 => SPI_MOSI_1 <= '0';
when 4 => SPI_MOSI_1 <= '0';
-- data
when 5 => SPI_MOSI_1 <= data_in_1(11);
when 6 => SPI_MOSI_1 <= data_in_1(10);
when 7 => SPI_MOSI_1 <= data_in_1(9);
when 8 => SPI_MOSI_1 <= data_in_1(8);
when 9 => SPI_MOSI_1 <= data_in_1(7);
when 10 => SPI_MOSI_1 <= data_in_1(6);
when 11 => SPI_MOSI_1 <= data_in_1(5);
when 12 => SPI_MOSI_1 <= data_in_1(4);
when 13 => SPI_MOSI_1 <= data_in_1(3);
when 14 => SPI_MOSI_1 <= data_in_1(2);
when 15 => SPI_MOSI_1 <= data_in_1(1);
when 16 => SPI_MOSI_1 <= data_in_1(0);
DAC_CS <= '1';
ready_flag_sig <= '1';
-- other
when others => SPI_MOSI_1 <= '0'; -- used for don't cares
end case;
end if;
else
DAC_CS <= '1';
current_bit <= 0;
spi_clk_delay <= '1';
end if;
--DAC_CS <= dac_cs_delay;
SPI_SCK <= not spi_clk_delay;
ready_flag <= ready_flag_sig;
end if;
end process;
end Behavioral;
--library IEEE;
--use IEEE.std_logic_1164.all;
--use IEEE.numeric_std.all;
--
--entity dac_serial is
-- port (
-- dac_clk: out std_logic;
-- dac_sync: out std_logic;
-- dac_data: out std_logic;
-- data_in: in std_logic_vector(11 downto 0);
-- ready: out std_logic;
-- send: in std_logic;
-- clk: in std_logic
-- );
--end dac_serial;
--
--architecture behavioral of dac_serial is
--
-- current_bit: unsigned(3 downto 0);
-- divide_counter: unsigned(3 downto 0);
-- sending: std_logic;
-- data_en: std_logic;
-- send_en: std_logic;
--
--begin
-- clk_divide:process(clk)
-- begin
-- if(rising_edge(clk)) then
-- if(divide_counter = to_unsigned(5,4)) then
-- divide_counter <= divide_counter + '1';
-- send_en <= '1';
-- elsif(divide_counter = to_unsigned(10,4)) then
-- divide_counter <= (others => '0');
-- data_en <= '1';
-- send_en <= '1';
-- else
-- divide_counter <= divide_counter + '1';
-- data_en <= '0';
-- send_en <= '0';
-- end if;
-- end if;
-- end process;
--
-- serial_clk: process(clk)
-- begin
-- if(rising_edge(clk)) then
-- if(sending = '1') then
--
-- end process;
--
-- serial_data: process(clk)
-- begin
-- if(rising_edge(clk)) then
-- if(send = '1') and (sending = '0') then
-- sending <= '1';
-- sending <= '1';
-- ready <= '0';
-- current_bit <= "0000";
-- dac_data <= '0';
-- elsif(data_en = '1') then
-- if(sending = '1') then
-- current_bit <= current_bit + '1';
-- dac_sync <= '0';
-- case current_bit is
-- when "0000" =>
-- dac_data <= '0'; -- don't care
-- when "0001" =>
-- dac_data <= '0'; -- don't care
-- when "0010" =>
-- dac_data <= '0'; -- 0 for normal operation
-- when "0011" =>
-- dac_data <= '0'; -- 0 for normal operation
-- when "0100" =>
-- dac_data <= data_in(11);
-- when "0101" =>
-- dac_data <= data_in(10);
-- when "0110" =>
-- dac_data <= data_in(9);
-- when "0111" =>
-- dac_data <= data_in(8);
-- when "1000" =>
-- dac_data <= data_in(7);
-- when "1001" =>
-- dac_data <= data_in(6);
-- when "1010" =>
-- dac_data <= data_in(5);
-- when "1011" =>
-- dac_data <= data_in(4);
-- when "1100" =>
-- dac_data <= data_in(3);
-- when "1101" =>
-- dac_data <= data_in(2);
-- when "1110" =>
-- dac_data <= data_in(1);
-- when "1111" =>
-- dac_data <= data_in(0);
-- when others =>
-- dac_data <= '0';
-- end case;
-- else
-- dac_sync <= '1';
-- ready <= '0';
-- current_bit <= "0000";
-- dac_data <= '0';
-- end if;
-- end if;
-- end if;
-- end process;
--
--end behavioral;
|
entity top_entity is
end top_entity;
architecture top_arch of top_entity is
component used_entity
port (
myport1: in sometype;
myport2: inout sometype
);
end component;
signal mysignal1: sometype;
signal mysignal2: sometype;
begin
myinstance1: used_entity
port map (
myport1 => mysignal1,
myport2 => open
);
myinstance2: used_entity
port map (
myport1 => open,
myport2 => open
);
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.xtcpkg.all;
entity romram is
generic (
BITS: integer := 32
);
port (
ram_wb_clk_i: in std_logic;
ram_wb_rst_i: in std_logic;
ram_wb_ack_o: out std_logic;
ram_wb_dat_i: in std_logic_vector(31 downto 0);
ram_wb_dat_o: out std_logic_vector(31 downto 0);
ram_wb_tag_o: out std_logic_vector(31 downto 0);
ram_wb_tag_i: in std_logic_vector(31 downto 0);
ram_wb_adr_i: in std_logic_vector(BITS-1 downto 2);
ram_wb_cyc_i: in std_logic;
ram_wb_stb_i: in std_logic;
ram_wb_we_i: in std_logic;
ram_wb_stall_o: out std_logic;
ram_wb_sel_i: in std_logic_vector(3 downto 0);
rom_wb_clk_i: in std_logic;
rom_wb_rst_i: in std_logic;
rom_wb_ack_o: out std_logic;
rom_wb_dat_o: out std_logic_vector(31 downto 0);
rom_wb_tag_i: in std_logic_vector(31 downto 0);
rom_wb_tag_o: out std_logic_vector(31 downto 0);
rom_wb_adr_i: in std_logic_vector(BITS-1 downto 2);
rom_wb_cyc_i: in std_logic;
rom_wb_stb_i: in std_logic;
rom_wb_stall_o: out std_logic
);
end entity romram;
architecture behave of romram is
component internalram is
port (
CLKA: in std_logic;
WEA: in std_logic;
ENA: in std_logic;
MASKA: in std_logic_vector(3 downto 0);
ADDRA: in std_logic_vector(BITS-1 downto 2);
DIA: in std_logic_vector(31 downto 0);
DOA: out std_logic_vector(31 downto 0);
CLKB: in std_logic;
WEB: in std_logic;
ENB: in std_logic;
ADDRB: in std_logic_vector(BITS-1 downto 2);
DIB: in std_logic_vector(31 downto 0);
MASKB: in std_logic_vector(3 downto 0);
DOB: out std_logic_vector(31 downto 0)
);
end component;
signal rom_enable: std_logic;
signal ram_enable: std_logic;
signal romack, ramack: std_logic;
constant nothing: std_logic_vector(31 downto 0) := (others => '0');
signal rom_data: std_logic_vector(31 downto 0);
begin
rom_enable <= rom_wb_stb_i and rom_wb_cyc_i;
ram_enable <= ram_wb_stb_i and ram_wb_cyc_i;
rom_wb_stall_o <= '0';
ram_wb_stall_o <= '0';
rom_wb_ack_o <= romack;
ram_wb_ack_o <= ramack;
-- ACK processing (pipelined)
cache: if INSTRUCTION_CACHE generate
process(rom_wb_clk_i)
begin
if rising_edge(rom_wb_clk_i) then
if rom_wb_rst_i='1' then
romack <= '0';
else
--if rom_enable='1' then
romack <= rom_enable;
if rom_enable='1' then
rom_wb_tag_o <= rom_wb_tag_i;
end if;
--end if;
end if;
end if;
end process;
end generate;
nocache: if not INSTRUCTION_CACHE generate
process(rom_wb_clk_i)
begin
if rising_edge(rom_wb_clk_i) then
if rom_wb_rst_i='1' then
romack <= '0';
else
romack <= '1';
rom_wb_tag_o <= rom_wb_tag_i;
end if;
end if;
end process;
end generate;
-- ACK processing (pipelined)
process(ram_wb_clk_i)
begin
if rising_edge(ram_wb_clk_i) then
if ram_wb_rst_i='1' then
ramack <= '0';
else
ramack <= ram_enable;
if ram_enable='1' then
ram_wb_tag_o <= ram_wb_tag_i;
end if;
end if;
end if;
end process;
rom_wb_dat_o <= rom_data;
ram: internalram
port map (
CLKA => rom_wb_clk_i,
CLKB => ram_wb_clk_i,
WEA => '0',
ENA => rom_enable,
MASKA => "1111",
ADDRA => rom_wb_adr_i(BITS-1 downto 2),
DIA => nothing,
DOA => rom_data,
WEB => ram_wb_we_i,
ENB => ram_enable,
ADDRB => ram_wb_adr_i(BITS-1 downto 2),
DIB => ram_wb_dat_i,
MASKB => ram_wb_sel_i,
DOB => ram_wb_dat_o
);
end behave;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1672.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p05n01i01672ent IS
END c09s01b00x00p05n01i01672ent;
ARCHITECTURE c09s01b00x00p05n01i01672arch OF c09s01b00x00p05n01i01672ent IS
BEGIN
B:block
begin
return; -- illegal location for return statement
end block;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s01b00x00p05n01i01672 - Sequential statement not allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p05n01i01672arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1672.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p05n01i01672ent IS
END c09s01b00x00p05n01i01672ent;
ARCHITECTURE c09s01b00x00p05n01i01672arch OF c09s01b00x00p05n01i01672ent IS
BEGIN
B:block
begin
return; -- illegal location for return statement
end block;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s01b00x00p05n01i01672 - Sequential statement not allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p05n01i01672arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1672.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p05n01i01672ent IS
END c09s01b00x00p05n01i01672ent;
ARCHITECTURE c09s01b00x00p05n01i01672arch OF c09s01b00x00p05n01i01672ent IS
BEGIN
B:block
begin
return; -- illegal location for return statement
end block;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s01b00x00p05n01i01672 - Sequential statement not allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p05n01i01672arch;
|
--========================================================================================================================
-- Copyright (c) 2016 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis IRQC Library : irqc_pif
--
-- Description : See dedicated powerpoint presentation and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.irqc_pif_pkg.all;
entity irqc_pif is
port(
arst : in std_logic;
clk : in std_logic;
-- CPU interface
cs : in std_logic;
addr : in unsigned;
wr : in std_logic;
rd : in std_logic;
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0) := (others => '0');
--
p2c : out t_p2c;
c2p : in t_c2p
);
end irqc_pif;
architecture rtl of irqc_pif is
signal p2c_i : t_p2c; -- internal version of output
signal dout_i : std_logic_vector(7 downto 0) := (others => '0');
begin
-- Assigning internally used signals to outputs
p2c <= p2c_i;
p_read_reg : process(cs, addr, rd, c2p, p2c_i)
begin
-- default values
dout_i <= (others => '0');
if cs = '1' and rd = '1' then
case to_integer(addr) is
when C_ADDR_IRR =>
dout_i(C_NUM_SOURCES-1 downto 0) <= c2p.aro_irr;
when C_ADDR_IER =>
dout_i(C_NUM_SOURCES-1 downto 0) <= p2c_i.rw_ier;
when C_ADDR_IPR =>
dout_i(C_NUM_SOURCES-1 downto 0) <= c2p.aro_ipr;
when C_ADDR_IRQ2CPU_ALLOWED =>
dout_i(0) <= c2p.aro_irq2cpu_allowed;
when others =>
null;
end case;
end if;
end process p_read_reg;
dout <= dout_i;
-- Writing to registers that are not functionally manipulated
p_write_reg : process(clk, arst)
begin
if arst = '1' then
p2c_i.rw_ier <= (others => '0');
elsif rising_edge(clk) then
if cs = '1' and wr = '1' then
case to_integer(addr) is
when C_ADDR_IER =>
p2c_i.rw_ier <= din(C_NUM_SOURCES-1 downto 0);
-- Auxiliary write (below)
when others =>
null;
end case;
end if;
end if;
end process p_write_reg;
-- Writing to registers that are functionally manipulated and/or located outside PIF (or dummy registers)
p_aux : process(wr, addr, din)
begin
-- Note that arst is not considered here, but must be considered in any clocked process in the core
-- Default - always to return to these values
p2c_i.awt_icr(C_NUM_SOURCES-1 downto 0) <= (others => '0');
p2c_i.awt_itr(C_NUM_SOURCES-1 downto 0) <= (others => '0');
p2c_i.awt_irq2cpu_ena <= '0';
p2c_i.awt_irq2cpu_disable <= '0';
if (cs = '1' and wr = '1') then
case to_integer(addr) is
when C_ADDR_ITR =>
p2c_i.awt_itr <= din(C_NUM_SOURCES-1 downto 0);
when C_ADDR_ICR =>
p2c_i.awt_icr <= din(C_NUM_SOURCES-1 downto 0);
when C_ADDR_IRQ2CPU_ENA =>
p2c_i.awt_irq2cpu_ena <= din(0);
when C_ADDR_IRQ2CPU_DISABLE =>
p2c_i.awt_irq2cpu_disable <= din(0);
when others =>
null;
end case;
end if;
end process p_aux;
end rtl;
|
-------------------------------------------------------------------------------
-- system_stub.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_stub is
port (
fpga_0_clk_1_sys_clk_pin : in std_logic;
fpga_0_rst_1_sys_rst_pin : in std_logic
);
end system_stub;
architecture STRUCTURE of system_stub is
component system is
port (
fpga_0_clk_1_sys_clk_pin : in std_logic;
fpga_0_rst_1_sys_rst_pin : in std_logic
);
end component;
attribute BOX_TYPE : STRING;
attribute BOX_TYPE of system : component is "user_black_box";
begin
system_i : system
port map (
fpga_0_clk_1_sys_clk_pin => fpga_0_clk_1_sys_clk_pin,
fpga_0_rst_1_sys_rst_pin => fpga_0_rst_1_sys_rst_pin
);
end architecture STRUCTURE;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06.03.2014 15:08:57
-- Design Name:
-- Module Name: top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VHDL_lib.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top is
Port ( clk_raw : in STD_LOGIC;
leds : out STD_LOGIC_VECTOR (7 downto 0);
VGA_DATA : out STD_LOGIC_VECTOR (11 downto 0);
VGA_HSYNC : out STD_LOGIC;
VGA_VSYNC : out STD_LOGIC
);
end top;
architecture Behavioral of top is
constant horz : integer := 5;
signal clk_100MHz: std_logic;
signal clk_193MHz: std_logic;
signal clk_250MHz: std_logic;
signal hscnt: std_logic_vector(11 downto 0);
signal vscnt: std_logic_vector(11 downto 0);
signal data: std_logic_vector(11 downto 0):= (others=>'0');
component clk_base is
port (
clk_raw : in STD_LOGIC;
clk_250MHz : out STD_LOGIC;
clk_100MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
end component;
component clk_video is
port (
clk_100MHz : in STD_LOGIC;
clk_193MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
end component;
begin
clk_base1: clk_base port map(clk_raw, clk_250MHz, clk_100MHz, leds(0));
clk_video1: clk_video port map(clk_100MHz, clk_193MHz, leds(1));
vga1: vga generic map(
Hsync=> 112,
Hact=> 1280,
Hfp=>48,
Hbp=>248,
Vsync=>3,
Vact=> 1024,
Vfp=> 1,
Vbp=> 38
) port map( clk_193MHz, hscnt,vscnt,VGA_HSYNC, VGA_VSYNC,open);
leds(7 downto 2) <= (others=>'0');
process(clk_193MHz) begin
if(clk_193MHz'event and clk_193MHz='1')then
if( hscnt < 1280 and vscnt < 1024)then
VGA_DATA <= data;
else
VGA_DATA <= (others=>'0');
end if;
if (vscnt = 512)then
data <= X"07F";
elsif((hscnt = 0) or (hscnt = 128) or (hscnt = 256) or (hscnt = 384) or (hscnt = 512) or (hscnt = 640) or (hscnt = 768) or (hscnt = 896) or (hscnt = 1024) or (hscnt = 1152) or (hscnt = 1280-1)) then
data <= X"0FF";
elsif((vscnt = 0) or (vscnt = 128) or (vscnt = 256) or (vscnt = 384) or (vscnt = 640) or (vscnt = 768) or (vscnt = 896) or (vscnt = 1024-1)) then
data <= X"0FF";
else
data <= X"000";
end if;
end if;
end process;
end Behavioral;
|
-- #################################################################################################
-- # << NEO430 - Processor Top Entity with Avalon-Compatible Master Interface >> #
-- # ********************************************************************************************* #
-- # BSD 3-Clause License #
-- # #
-- # Copyright (c) 2020, Stephan Nolting. All rights reserved. #
-- # #
-- # Redistribution and use in source and binary forms, with or without modification, are #
-- # permitted provided that the following conditions are met: #
-- # #
-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
-- # conditions and the following disclaimer. #
-- # #
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
-- # conditions and the following disclaimer in the documentation and/or other materials #
-- # provided with the distribution. #
-- # #
-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
-- # endorse or promote products derived from this software without specific prior written #
-- # permission. #
-- # #
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
-- # ********************************************************************************************* #
-- # The NEO430 Processor - https://github.com/stnolting/neo430 #
-- #################################################################################################
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library neo430;
use neo430.neo430_package.all;
entity neo430_top_avm is
generic (
-- general configuration --
CLOCK_SPEED : natural := 100000000; -- main clock in Hz
IMEM_SIZE : natural := 4*1024; -- internal IMEM size in bytes, max 48kB (default=4kB)
DMEM_SIZE : natural := 2*1024; -- internal DMEM size in bytes, max 12kB (default=2kB)
-- additional configuration --
USER_CODE : std_logic_vector(15 downto 0) := x"0000"; -- custom user code
-- module configuration --
MULDIV_USE : boolean := true; -- implement multiplier/divider unit? (default=true)
WB32_USE : boolean := true; -- implement WB32 unit? (default=true)
WDT_USE : boolean := true; -- implement WDT? (default=true)
GPIO_USE : boolean := true; -- implement GPIO unit? (default=true)
TIMER_USE : boolean := true; -- implement timer? (default=true)
UART_USE : boolean := true; -- implement UART? (default=true)
CRC_USE : boolean := true; -- implement CRC unit? (default=true)
CFU_USE : boolean := false; -- implement custom functions unit? (default=false)
PWM_USE : boolean := true; -- implement PWM controller?
TWI_USE : boolean := true; -- implement two wire serial interface? (default=true)
SPI_USE : boolean := true; -- implement SPI? (default=true)
TRNG_USE : boolean := false; -- implement TRNG? (default=false)
EXIRQ_USE : boolean := true; -- implement EXIRQ? (default=true)
FREQ_GEN_USE : boolean := true; -- implement FREQ_GEN? (default=true)
-- boot configuration --
BOOTLD_USE : boolean := true; -- implement and use bootloader? (default=true)
IMEM_AS_ROM : boolean := false -- implement IMEM as read-only memory? (default=false)
);
port (
-- global control --
clk_i : in std_logic; -- global clock, rising edge
rst_i : in std_logic; -- global reset, async, low-active
-- GPIO --
gpio_o : out std_logic_vector(15 downto 0); -- parallel output
gpio_i : in std_logic_vector(15 downto 0); -- parallel input
-- pwm channels --
pwm_o : out std_logic_vector(03 downto 0); -- pwm channels
-- arbitrary frequency generator --
freq_gen_o : out std_logic_vector(02 downto 0); -- programmable frequency output
-- UART --
uart_txd_o : out std_logic; -- UART send data
uart_rxd_i : in std_logic; -- UART receive data
-- SPI --
spi_sclk_o : out std_logic; -- serial clock line
spi_mosi_o : out std_logic; -- serial data line out
spi_miso_i : in std_logic; -- serial data line in
spi_cs_o : out std_logic_vector(05 downto 0); -- SPI CS
twi_sda_io : inout std_logic; -- twi serial data line
twi_scl_io : inout std_logic; -- twi serial clock line
-- external interrupts --
ext_irq_i : in std_logic_vector(07 downto 0); -- external interrupt request lines
ext_ack_o : out std_logic_vector(07 downto 0); -- external interrupt request acknowledges
-- Avalon master interface --
avm_address : out std_logic_vector(31 downto 0);
avm_readdata : in std_logic_vector(31 downto 0);
avm_writedata : out std_logic_vector(31 downto 0);
avm_byteenable : out std_logic_vector(03 downto 0);
avm_write : out std_logic;
avm_read : out std_logic;
avm_waitrequest : in std_logic
);
end neo430_top_avm;
architecture neo430_top_avm_rtl of neo430_top_avm is
-- internal wishbone (unresolved) bus --
type wb_bus_ul_t is record
adr : std_ulogic_vector(31 downto 0); -- address
di : std_ulogic_vector(31 downto 0); -- slave input data
do : std_ulogic_vector(31 downto 0); -- slave output data
we : std_ulogic; -- write enable
sel : std_ulogic_vector(03 downto 0); -- byte enable
stb : std_ulogic; -- strobe
cyc : std_ulogic; -- valid cycle
ack : std_ulogic; -- transfer acknowledge
end record;
signal wb_core : wb_bus_ul_t;
-- internal wishbone bus --
type wb_bus_t is record
adr : std_logic_vector(31 downto 0); -- address
di : std_logic_vector(31 downto 0); -- slave input data
do : std_logic_vector(31 downto 0); -- slave output data
we : std_logic; -- write enable
sel : std_logic_vector(03 downto 0); -- byte enable
stb : std_logic; -- strobe
cyc : std_logic; -- valid cycle
ack : std_logic; -- transfer acknowledge
end record;
signal wb_conv : wb_bus_t;
-- other signals for conversion --
signal clk_i_int : std_ulogic;
signal rst_i_int : std_ulogic;
signal gpio_o_int : std_ulogic_vector(15 downto 0);
signal gpio_i_int : std_ulogic_vector(15 downto 0);
signal pwm_o_int : std_ulogic_vector(03 downto 0);
signal uart_txd_o_int : std_ulogic;
signal uart_rxd_i_int : std_ulogic;
signal spi_sclk_o_int : std_ulogic;
signal spi_mosi_o_int : std_ulogic;
signal spi_miso_i_int : std_ulogic;
signal spi_cs_o_int : std_ulogic_vector(05 downto 0);
signal irq_i_int : std_ulogic_vector(07 downto 0);
signal irq_ack_o_int : std_ulogic_vector(07 downto 0);
signal freq_gen_o_int : std_ulogic_vector(02 downto 0);
constant usrcode_c : std_ulogic_vector(15 downto 0) := std_ulogic_vector(USER_CODE);
-- misc --
signal trans_en : std_logic;
begin
-- CPU ----------------------------------------------------------------------
-- -----------------------------------------------------------------------------
neo430_top_inst: neo430_top
generic map (
-- general configuration --
CLOCK_SPEED => CLOCK_SPEED, -- main clock in Hz
IMEM_SIZE => IMEM_SIZE, -- internal IMEM size in bytes, max 48kB (default=4kB)
DMEM_SIZE => DMEM_SIZE, -- internal DMEM size in bytes, max 12kB (default=2kB)
-- additional configuration --
USER_CODE => usrcode_c, -- custom user code
-- module configuration --
MULDIV_USE => MULDIV_USE, -- implement multiplier/divider unit? (default=true)
WB32_USE => WB32_USE, -- implement WB32 unit? (default=true)
WDT_USE => WDT_USE, -- implement WDT? (default=true)
GPIO_USE => GPIO_USE, -- implement GPIO unit? (default=true)
TIMER_USE => TIMER_USE, -- implement timer? (default=true)
UART_USE => UART_USE, -- implement UART? (default=true)
CRC_USE => CRC_USE, -- implement CRC unit? (default=true)
CFU_USE => CFU_USE, -- implement CF unit? (default=false)
PWM_USE => PWM_USE, -- implement PWM controller? (default=true)
TWI_USE => TWI_USE, -- implement two wire serial interface? (default=true)
SPI_USE => SPI_USE, -- implement SPI? (default=true)
TRNG_USE => TRNG_USE, -- implement TRNG? (default=false)
EXIRQ_USE => EXIRQ_USE, -- implement EXIRQ? (default=true)
FREQ_GEN_USE => FREQ_GEN_USE, -- implement FREQ_GEN? (default=true)
-- boot configuration --
BOOTLD_USE => BOOTLD_USE, -- implement and use bootloader? (default=true)
IMEM_AS_ROM => IMEM_AS_ROM -- implement IMEM as read-only memory? (default=false)
)
port map (
-- global control --
clk_i => clk_i_int, -- global clock, rising edge
rst_i => rst_i_int, -- global reset, async, low-active
-- parallel io --
gpio_o => gpio_o_int, -- parallel output
gpio_i => gpio_i_int, -- parallel input
-- pwm channels --
pwm_o => pwm_o_int, -- pwm channels
-- arbitrary frequency generator --
freq_gen_o => freq_gen_o_int, -- programmable frequency output
-- serial com --
uart_txd_o => uart_txd_o_int, -- UART send data
uart_rxd_i => uart_rxd_i_int, -- UART receive data
spi_sclk_o => spi_sclk_o_int, -- serial clock line
spi_mosi_o => spi_mosi_o_int, -- serial data line out
spi_miso_i => spi_miso_i_int, -- serial data line in
spi_cs_o => spi_cs_o_int, -- SPI CS
twi_sda_io => twi_sda_io, -- twi serial data line
twi_scl_io => twi_scl_io, -- twi serial clock line
-- 32-bit wishbone interface --
wb_adr_o => wb_core.adr, -- address
wb_dat_i => wb_core.di, -- read data
wb_dat_o => wb_core.do, -- write data
wb_we_o => wb_core.we, -- read/write
wb_sel_o => wb_core.sel, -- byte enable
wb_stb_o => wb_core.stb, -- strobe
wb_cyc_o => wb_core.cyc, -- valid cycle
wb_ack_i => wb_core.ack, -- transfer acknowledge
-- interrupts --
ext_irq_i => irq_i_int, -- external interrupt request line
ext_ack_o => irq_ack_o_int -- external interrupt request acknowledge
);
-- Output Type Conversion ---------------------------------------------------
-- -----------------------------------------------------------------------------
clk_i_int <= std_ulogic(clk_i);
rst_i_int <= std_ulogic(rst_i);
gpio_i_int <= std_ulogic_vector(gpio_i);
uart_rxd_i_int <= std_ulogic(uart_rxd_i);
spi_miso_i_int <= std_ulogic(spi_miso_i);
irq_i_int <= std_ulogic_vector(ext_irq_i);
gpio_o <= std_logic_vector(gpio_o_int);
pwm_o <= std_logic_vector(pwm_o_int);
uart_txd_o <= std_logic(uart_txd_o_int);
spi_sclk_o <= std_logic(spi_sclk_o_int);
spi_mosi_o <= std_logic(spi_mosi_o_int);
spi_cs_o <= std_logic_vector(spi_cs_o_int);
ext_ack_o <= std_logic_vector(irq_ack_o_int);
freq_gen_o <= std_logic_vector(freq_gen_o_int);
-- Wishbone-to-Avalon Bridge ------------------------------------------------
-- -----------------------------------------------------------------------------
-- Type Conversion --
wb_conv.adr <= std_logic_vector(wb_core.adr);
wb_conv.do <= std_logic_vector(wb_core.do);
wb_conv.we <= std_logic(wb_core.we);
wb_conv.sel <= std_logic_vector(wb_core.sel);
wb_conv.stb <= std_logic(wb_core.stb);
wb_conv.cyc <= std_logic(wb_core.cyc);
wb_core.di <= std_ulogic_vector(wb_conv.di);
wb_core.ack <= std_ulogic(wb_conv.ack);
active_transfer: process(clk_i_int)
begin
if rising_edge(clk_i_int) then
trans_en <= wb_conv.cyc and (trans_en or wb_conv.stb); -- keep STB virtually alive
end if;
end process active_transfer;
-- Wishbone -> Avalon
avm_address <= wb_conv.adr;
avm_writedata <= wb_conv.do;
avm_byteenable <= wb_conv.sel;
avm_write <= wb_conv.cyc and (wb_conv.stb or trans_en) and wb_conv.we;
avm_read <= wb_conv.cyc and (wb_conv.stb or trans_en) and (not wb_conv.we);
-- Avalon -> Wishbone
wb_conv.di <= avm_readdata;
wb_conv.ack <= wb_conv.cyc and (not avm_waitrequest);
end neo430_top_avm_rtl;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Debouncer
-- Project Name: Button Controller
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Debouncer
-- Debounce Input Signal
-- Input is fed through two flip flops
-- If both flip flops(2 cycles) have a high then
-- the counter will increment till it goes to
-- the necessary wait time.
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.all;
entity debounce is
Generic ( wait_time : INTEGER := 20);
-- Wait_time is a fixed time to wait to validate a debounce signal
-- Wait time is based on the Nexys 50 MHZ Clock
-- XX : (2^xx + 2)/CLK
-- 21 : 41.9ms | (2^21 + 2)/50E6
-- 20 : 21.0ms | (2^20 + 2)/50E6
-- 19 : 10.5ms | (2^19 + 2)/50E6
-- 18 : 5.2ms | (2^18 + 2)/50E6
Port ( CLK : in STD_LOGIC;
EN : in STD_LOGIC;
INPUT : in STD_LOGIC;
OUTPUT : out STD_LOGIC);
end debounce;
architecture Logic of debounce is
signal D_STATE : STD_LOGIC_VECTOR (1 downto 0);
signal D_SET : STD_LOGIC;
signal Count : STD_LOGIC_VECTOR( wait_time downto 0) := (others => '0');
begin
D_SET <= D_STATE(0) xor D_STATE(1);
--Check what the deboune states are
-- *if their is a change in state then D_SET will be set to a high
input_monitor: process (EN, CLK)
begin
if (CLK'event and CLK = '1' and EN = '1') then
D_STATE(0) <= INPUT;
D_STATE(1) <= D_STATE(0);
if(D_SET = '1') then
Count <= (others => '0');
elsif(Count(wait_time) = '0') then
Count <= Count + 1;
else
OUTPUT <= D_STATE(1);
end if;
end if;
end process;
end Logic;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Debouncer
-- Project Name: Button Controller
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Debouncer
-- Debounce Input Signal
-- Input is fed through two flip flops
-- If both flip flops(2 cycles) have a high then
-- the counter will increment till it goes to
-- the necessary wait time.
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.all;
entity debounce is
Generic ( wait_time : INTEGER := 20);
-- Wait_time is a fixed time to wait to validate a debounce signal
-- Wait time is based on the Nexys 50 MHZ Clock
-- XX : (2^xx + 2)/CLK
-- 21 : 41.9ms | (2^21 + 2)/50E6
-- 20 : 21.0ms | (2^20 + 2)/50E6
-- 19 : 10.5ms | (2^19 + 2)/50E6
-- 18 : 5.2ms | (2^18 + 2)/50E6
Port ( CLK : in STD_LOGIC;
EN : in STD_LOGIC;
INPUT : in STD_LOGIC;
OUTPUT : out STD_LOGIC);
end debounce;
architecture Logic of debounce is
signal D_STATE : STD_LOGIC_VECTOR (1 downto 0);
signal D_SET : STD_LOGIC;
signal Count : STD_LOGIC_VECTOR( wait_time downto 0) := (others => '0');
begin
D_SET <= D_STATE(0) xor D_STATE(1);
--Check what the deboune states are
-- *if their is a change in state then D_SET will be set to a high
input_monitor: process (EN, CLK)
begin
if (CLK'event and CLK = '1' and EN = '1') then
D_STATE(0) <= INPUT;
D_STATE(1) <= D_STATE(0);
if(D_SET = '1') then
Count <= (others => '0');
elsif(Count(wait_time) = '0') then
Count <= Count + 1;
else
OUTPUT <= D_STATE(1);
end if;
end if;
end process;
end Logic;
|
---------------------------------------------------------------------------
-- This VHDL file was developed by Altera Corporation. It may be
-- freely copied and/or distributed at no cost. Any persons using this
-- file for any purpose do so at their own risk, and are responsible for
-- the results of such use. Altera Corporation does not guarantee that
-- this file is complete, correct, or fit for any particular purpose.
-- NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED. This notice must
-- accompany any copy of this file.
--------------------------------------------------------------------------
--
-- Quartus II 11.0 Build 157 04/27/2011
--
--------------------------------------------------------------------------
-- LPM Synthesizable Models (Support string type generic)
-- These models are based on LPM version 220 (EIA-IS103 October 1998).
--------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Assumptions:
--
-- 1. All ports and signal types are std_logic or std_logic_vector
-- from IEEE 1164 package.
-- 2. Synopsys std_logic_arith, std_logic_unsigned, and std_logic_signed
-- package are assumed to be accessible from IEEE library.
-- 3. lpm_component_package must be accessible from library work.
-- 4. The default value of LPM_SVALUE, LPM_AVALUE, LPM_MODULUS, LPM_HINT,
-- LPM_NUMWORDS, LPM_STRENGTH, LPM_DIRECTION, and LPM_PVALUE is
-- string "UNUSED".
-------------------------------------------------------------------------------
---START_PACKAGE_HEADER-----------------------------------------------------
--
-- Package Name : LPM_COMMON_CONVERSION
--
-- Description : Common conversion functions
--
---END_PACKAGE_HEADER--------------------------------------------------------
-- BEGINING OF PACKAGE
Library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
-- PACKAGE DECLARATION
package LPM_COMMON_CONVERSION is
-- FUNCTION DECLARATION
function STR_TO_INT (str : string) return integer;
function INT_TO_STR (value : in integer) return string;
function HEX_STR_TO_INT (str : in string) return integer;
function BIN_STR_TO_INT (str : in string) return integer;
function OCT_STR_TO_INT (str : in string) return integer;
function INT_STR_TO_INT (str : in string) return integer;
function ALPHA_TOLOWER (given_string : in string) return string;
procedure SHRINK_LINE (str_line : inout line; pos : in integer);
end LPM_COMMON_CONVERSION;
package body LPM_COMMON_CONVERSION is
function STR_TO_INT ( str : string ) return integer is
variable len : integer := str'length;
variable ivalue : integer := 0;
variable digit : integer := 0;
begin
for i in 1 to len loop
case str(i) is
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& str(i) & "in string parameter! "
SEVERITY ERROR;
end case;
ivalue := ivalue * 10 + digit;
end loop;
return ivalue;
end STR_TO_INT;
-- This function converts an integer to a string
function INT_TO_STR (value : in integer) return string is
variable ivalue : integer := 0;
variable index : integer := 0;
variable digit : integer := 0;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 => line_no(index) := '0';
when 1 => line_no(index) := '1';
when 2 => line_no(index) := '2';
when 3 => line_no(index) := '3';
when 4 => line_no(index) := '4';
when 5 => line_no(index) := '5';
when 6 => line_no(index) := '6';
when 7 => line_no(index) := '7';
when 8 => line_no(index) := '8';
when 9 => line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end INT_TO_STR;
-- This function converts a hexadecimal number to an integer
function HEX_STR_TO_INT (str : in string) return integer is
variable len : integer := str'length;
variable ivalue : integer := 0;
variable digit : integer := 0;
begin
for i in len downto 1 loop
case str(i) is
when '0' => digit := 0;
when '1' => digit := 1;
when '2' => digit := 2;
when '3' => digit := 3;
when '4' => digit := 4;
when '5' => digit := 5;
when '6' => digit := 6;
when '7' => digit := 7;
when '8' => digit := 8;
when '9' => digit := 9;
when 'A' => digit := 10;
when 'a' => digit := 10;
when 'B' => digit := 11;
when 'b' => digit := 11;
when 'C' => digit := 12;
when 'c' => digit := 12;
when 'D' => digit := 13;
when 'd' => digit := 13;
when 'E' => digit := 14;
when 'e' => digit := 14;
when 'F' => digit := 15;
when 'f' => digit := 15;
when others =>
ASSERT FALSE
REPORT "Illegal hex character "& str(i) & "! "
SEVERITY ERROR;
end case;
ivalue := ivalue * 16 + digit;
end loop;
return ivalue;
end HEX_STR_TO_INT;
-- This function converts a binary number to an integer
function BIN_STR_TO_INT (str : in string) return integer is
variable len : integer := str'length;
variable ivalue : integer := 0;
variable digit : integer := 0;
begin
for i in len downto 1 loop
case str(i) is
when '0' => digit := 0;
when '1' => digit := 1;
when others =>
ASSERT FALSE
REPORT "Illegal bin character "& str(i) & "! "
SEVERITY ERROR;
end case;
ivalue := ivalue * 2 + digit;
end loop;
return ivalue;
end BIN_STR_TO_INT;
-- This function converts a octadecimal number to an integer
function OCT_STR_TO_INT (str : in string) return integer is
variable len : integer := str'length;
variable ivalue : integer := 0;
variable digit : integer := 0;
begin
for i in len downto 1 loop
case str(i) is
when '0' => digit := 0;
when '1' => digit := 1;
when '2' => digit := 2;
when '3' => digit := 3;
when '4' => digit := 4;
when '5' => digit := 5;
when '6' => digit := 6;
when '7' => digit := 7;
when others =>
ASSERT FALSE
REPORT "Illegal octadecimal character "& str(i) & "! "
SEVERITY ERROR;
end case;
ivalue := ivalue * 8 + digit;
end loop;
return ivalue;
end OCT_STR_TO_INT;
-- This function converts a integer string to an integer
function INT_STR_TO_INT (str : in string) return integer is
variable len : integer := str'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case str(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& str(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& str(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
-- converts uppercase parameter values (e.g. "AUTO") to lowercase ("auto")
function ALPHA_TOLOWER (given_string : in string) return string is
-- VARIABLE DECLARATION
variable result_string : string(given_string'low to given_string'high);
begin
for i in given_string'low to given_string'high loop
case given_string(i) is
when 'A' => result_string(i) := 'a';
when 'B' => result_string(i) := 'b';
when 'C' => result_string(i) := 'c';
when 'D' => result_string(i) := 'd';
when 'E' => result_string(i) := 'e';
when 'F' => result_string(i) := 'f';
when 'G' => result_string(i) := 'g';
when 'H' => result_string(i) := 'h';
when 'I' => result_string(i) := 'i';
when 'J' => result_string(i) := 'j';
when 'K' => result_string(i) := 'k';
when 'L' => result_string(i) := 'l';
when 'M' => result_string(i) := 'm';
when 'N' => result_string(i) := 'n';
when 'O' => result_string(i) := 'o';
when 'P' => result_string(i) := 'p';
when 'Q' => result_string(i) := 'q';
when 'R' => result_string(i) := 'r';
when 'S' => result_string(i) := 's';
when 'T' => result_string(i) := 't';
when 'U' => result_string(i) := 'u';
when 'V' => result_string(i) := 'v';
when 'W' => result_string(i) := 'w';
when 'X' => result_string(i) := 'x';
when 'Y' => result_string(i) := 'y';
when 'Z' => result_string(i) := 'z';
when others => result_string(i) := given_string(i);
end case;
end loop;
return (result_string(given_string'low to given_string'high));
end;
-- This procedure "cuts" the str_line into desired length
procedure SHRINK_LINE (str_line : inout line; pos : in integer) is
subtype nstring is string(1 to pos);
variable str : nstring;
begin
if (pos >= 1) then
read(str_line, str);
end if;
end;
end LPM_COMMON_CONVERSION;
-- END OF PACKAGE
---START_PACKAGE_HEADER-----------------------------------------------------
--
-- Package Name : LPM_HINT_EVALUATION
--
-- Description : Common function to grep the value of altera specific parameters
-- within the lpm_hint parameter.
--
---END_PACKAGE_HEADER--------------------------------------------------------
-- BEGINING OF PACKAGE
Library ieee;
use ieee.std_logic_1164.all;
-- PACKAGE DECLARATION
package LPM_HINT_EVALUATION is
-- FUNCTION DECLARATION
function get_parameter_value( constant given_string : string;
compare_param_name : string) return string;
end LPM_HINT_EVALUATION;
package body LPM_HINT_EVALUATION is
-- This function will search through the string (given string) to look for a match for the
-- a given parameter(compare_param_name). It will return the value for the given parameter.
function get_parameter_value( constant given_string : string;
compare_param_name : string) return string is
variable param_name_left_index : integer := given_string'length;
variable param_name_right_index : integer := given_string'length;
variable param_value_left_index : integer := given_string'length;
variable param_value_right_index : integer := given_string'length;
variable set_right_index : boolean := true;
variable extract_param_value : boolean := true;
variable extract_param_name : boolean := false;
variable param_found : boolean := false;
variable given_string_tmp : string(1 to given_string'length) := given_string;
begin
-- checking every character of the given_string from right to left.
for i in given_string'length downto 1 loop
if (given_string(i) /= ' ') then
if (given_string(i) = '=') then
extract_param_value := false;
extract_param_name := true;
set_right_index := true;
elsif (given_string(i) = ',') then
extract_param_value := true;
extract_param_name := false;
set_right_index := true;
if (compare_param_name = given_string_tmp(param_name_left_index to param_name_right_index)) then
param_found := true; -- the compare_param_name have been found in the given_string
exit;
end if;
else
if (extract_param_value = true) then
if (set_right_index = true) then
param_value_right_index := i;
set_right_index := false;
end if;
param_value_left_index := i;
elsif (extract_param_name = true) then
if (set_right_index = true) then
param_name_right_index := i;
set_right_index := false;
end if;
param_name_left_index := i;
end if;
end if;
end if;
end loop;
-- for the case whether parameter's name is the left most part of the given_string
if (extract_param_name = true) then
if(compare_param_name = given_string_tmp(param_name_left_index to param_name_right_index)) then
param_found := true;
end if;
end if;
if(param_found = true) then
return given_string_tmp(param_value_left_index to param_value_right_index);
else
return ""; -- return empty string if parameter not found
end if;
end get_parameter_value;
end LPM_HINT_EVALUATION;
-- END OF PACKAGE
-- BEGINING OF PACKAGES
Library ieee;
use ieee.std_logic_1164.all;
-- PACKAGE DECLARATION
package LPM_DEVICE_FAMILIES is
-- FUNCTION DECLARATION
function IS_FAMILY_MAX7000B (device : in string) return boolean;
function IS_FAMILY_MAX7000AE (device : in string) return boolean;
function IS_FAMILY_MAX3000A (device : in string) return boolean;
function IS_FAMILY_MAX7000S (device : in string) return boolean;
function IS_FAMILY_STRATIX (device : in string) return boolean;
function IS_FAMILY_STRATIXGX (device : in string) return boolean;
function IS_FAMILY_CYCLONE (device : in string) return boolean;
function FEATURE_FAMILY_BASE_STRATIX (device : in string) return boolean;
function FEATURE_FAMILY_BASE_CYCLONE (device : in string) return boolean;
function FEATURE_FAMILY_MAX (device : in string) return boolean;
function IS_VALID_FAMILY (device: in string) return boolean;
end LPM_DEVICE_FAMILIES;
package body LPM_DEVICE_FAMILIES is
function IS_FAMILY_MAX7000B (device : in string) return boolean is
variable is_max7000b : boolean := false;
begin
if ((device = "MAX7000B") or (device = "max7000b") or (device = "MAX 7000B") or (device = "max 7000b"))
then
is_max7000b := true;
end if;
return is_max7000b;
end IS_FAMILY_MAX7000B;
function IS_FAMILY_MAX7000AE (device : in string) return boolean is
variable is_max7000ae : boolean := false;
begin
if ((device = "MAX7000AE") or (device = "max7000ae") or (device = "MAX 7000AE") or (device = "max 7000ae"))
then
is_max7000ae := true;
end if;
return is_max7000ae;
end IS_FAMILY_MAX7000AE;
function IS_FAMILY_MAX3000A (device : in string) return boolean is
variable is_max3000a : boolean := false;
begin
if ((device = "MAX3000A") or (device = "max3000a") or (device = "MAX 3000A") or (device = "max 3000a"))
then
is_max3000a := true;
end if;
return is_max3000a;
end IS_FAMILY_MAX3000A;
function IS_FAMILY_MAX7000S (device : in string) return boolean is
variable is_max7000s : boolean := false;
begin
if ((device = "MAX7000S") or (device = "max7000s") or (device = "MAX 7000S") or (device = "max 7000s"))
then
is_max7000s := true;
end if;
return is_max7000s;
end IS_FAMILY_MAX7000S;
function IS_FAMILY_STRATIX (device : in string) return boolean is
variable is_stratix : boolean := false;
begin
if ((device = "Stratix") or (device = "STRATIX") or (device = "stratix") or (device = "Yeager") or (device = "YEAGER") or (device = "yeager"))
then
is_stratix := true;
end if;
return is_stratix;
end IS_FAMILY_STRATIX;
function IS_FAMILY_STRATIXGX (device : in string) return boolean is
variable is_stratixgx : boolean := false;
begin
if ((device = "Stratix GX") or (device = "STRATIX GX") or (device = "stratix gx") or (device = "Stratix-GX") or (device = "STRATIX-GX") or (device = "stratix-gx") or (device = "StratixGX") or (device = "STRATIXGX") or (device = "stratixgx") or (device = "Aurora") or (device = "AURORA") or (device = "aurora"))
then
is_stratixgx := true;
end if;
return is_stratixgx;
end IS_FAMILY_STRATIXGX;
function IS_FAMILY_CYCLONE (device : in string) return boolean is
variable is_cyclone : boolean := false;
begin
if ((device = "Cyclone") or (device = "CYCLONE") or (device = "cyclone") or (device = "ACEX2K") or (device = "acex2k") or (device = "ACEX 2K") or (device = "acex 2k") or (device = "Tornado") or (device = "TORNADO") or (device = "tornado"))
then
is_cyclone := true;
end if;
return is_cyclone;
end IS_FAMILY_CYCLONE;
function FEATURE_FAMILY_BASE_STRATIX (device : in string) return boolean is
variable var_family_base_stratix : boolean := false;
begin
if (IS_FAMILY_STRATIX(device) or IS_FAMILY_STRATIXGX(device) )
then
var_family_base_stratix := true;
end if;
return var_family_base_stratix;
end FEATURE_FAMILY_BASE_STRATIX;
function FEATURE_FAMILY_BASE_CYCLONE (device : in string) return boolean is
variable var_family_base_cyclone : boolean := false;
begin
if (IS_FAMILY_CYCLONE(device) )
then
var_family_base_cyclone := true;
end if;
return var_family_base_cyclone;
end FEATURE_FAMILY_BASE_CYCLONE;
function FEATURE_FAMILY_MAX (device : in string) return boolean is
variable var_family_max : boolean := false;
begin
if ((device = "MAX5000") or IS_FAMILY_MAX3000A(device) or (device = "MAX7000") or (device = "MAX7000A") or IS_FAMILY_MAX7000AE(device) or (device = "MAX7000E") or IS_FAMILY_MAX7000S(device) or IS_FAMILY_MAX7000B(device) or (device = "MAX9000") )
then
var_family_max := true;
end if;
return var_family_max;
end FEATURE_FAMILY_MAX;
function IS_VALID_FAMILY (device : in string) return boolean is
variable is_valid : boolean := false;
begin
if (((device = "MAX7000B") or (device = "max7000b") or (device = "MAX 7000B") or (device = "max 7000b"))
or ((device = "MAX7000AE") or (device = "max7000ae") or (device = "MAX 7000AE") or (device = "max 7000ae"))
or ((device = "MAX3000A") or (device = "max3000a") or (device = "MAX 3000A") or (device = "max 3000a"))
or ((device = "MAX7000S") or (device = "max7000s") or (device = "MAX 7000S") or (device = "max 7000s"))
or ((device = "Stratix") or (device = "STRATIX") or (device = "stratix") or (device = "Yeager") or (device = "YEAGER") or (device = "yeager"))
or ((device = "Stratix GX") or (device = "STRATIX GX") or (device = "stratix gx") or (device = "Stratix-GX") or (device = "STRATIX-GX") or (device = "stratix-gx") or (device = "StratixGX") or (device = "STRATIXGX") or (device = "stratixgx") or (device = "Aurora") or (device = "AURORA") or (device = "aurora"))
or ((device = "Cyclone") or (device = "CYCLONE") or (device = "cyclone") or (device = "ACEX2K") or (device = "acex2k") or (device = "ACEX 2K") or (device = "acex 2k") or (device = "Tornado") or (device = "TORNADO") or (device = "tornado"))
or ((device = "MAX II") or (device = "max ii") or (device = "MAXII") or (device = "maxii") or (device = "Tsunami") or (device = "TSUNAMI") or (device = "tsunami"))
or ((device = "Stratix II") or (device = "STRATIX II") or (device = "stratix ii") or (device = "StratixII") or (device = "STRATIXII") or (device = "stratixii") or (device = "Armstrong") or (device = "ARMSTRONG") or (device = "armstrong"))
or ((device = "Stratix II GX") or (device = "STRATIX II GX") or (device = "stratix ii gx") or (device = "StratixIIGX") or (device = "STRATIXIIGX") or (device = "stratixiigx"))
or ((device = "Arria GX") or (device = "ARRIA GX") or (device = "arria gx") or (device = "ArriaGX") or (device = "ARRIAGX") or (device = "arriagx") or (device = "Stratix II GX Lite") or (device = "STRATIX II GX LITE") or (device = "stratix ii gx lite") or (device = "StratixIIGXLite") or (device = "STRATIXIIGXLITE") or (device = "stratixiigxlite"))
or ((device = "Cyclone II") or (device = "CYCLONE II") or (device = "cyclone ii") or (device = "Cycloneii") or (device = "CYCLONEII") or (device = "cycloneii") or (device = "Magellan") or (device = "MAGELLAN") or (device = "magellan"))
or ((device = "HardCopy II") or (device = "HARDCOPY II") or (device = "hardcopy ii") or (device = "HardCopyII") or (device = "HARDCOPYII") or (device = "hardcopyii") or (device = "Fusion") or (device = "FUSION") or (device = "fusion"))
or ((device = "Stratix III") or (device = "STRATIX III") or (device = "stratix iii") or (device = "StratixIII") or (device = "STRATIXIII") or (device = "stratixiii") or (device = "Titan") or (device = "TITAN") or (device = "titan") or (device = "SIII") or (device = "siii"))
or ((device = "Cyclone III") or (device = "CYCLONE III") or (device = "cyclone iii") or (device = "CycloneIII") or (device = "CYCLONEIII") or (device = "cycloneiii") or (device = "Barracuda") or (device = "BARRACUDA") or (device = "barracuda") or (device = "Cuda") or (device = "CUDA") or (device = "cuda") or (device = "CIII") or (device = "ciii"))
or ((device = "BS") or (device = "bs"))
or ((device = "Stratix IV") or (device = "STRATIX IV") or (device = "stratix iv") or (device = "TGX") or (device = "tgx") or (device = "StratixIV") or (device = "STRATIXIV") or (device = "stratixiv") or (device = "Stratix IV (GT)") or (device = "STRATIX IV (GT)") or (device = "stratix iv (gt)") or (device = "Stratix IV (GX)") or (device = "STRATIX IV (GX)") or (device = "stratix iv (gx)") or (device = "Stratix IV (E)") or (device = "STRATIX IV (E)") or (device = "stratix iv (e)") or (device = "StratixIV(GT)") or (device = "STRATIXIV(GT)") or (device = "stratixiv(gt)") or (device = "StratixIV(GX)") or (device = "STRATIXIV(GX)") or (device = "stratixiv(gx)") or (device = "StratixIV(E)") or (device = "STRATIXIV(E)") or (device = "stratixiv(e)") or (device = "StratixIIIGX") or (device = "STRATIXIIIGX") or (device = "stratixiiigx") or (device = "Stratix IV (GT/GX/E)") or (device = "STRATIX IV (GT/GX/E)") or (device = "stratix iv (gt/gx/e)") or (device = "Stratix IV (GT/E/GX)") or (device = "STRATIX IV (GT/E/GX)") or (device = "stratix iv (gt/e/gx)") or (device = "Stratix IV (E/GT/GX)") or (device = "STRATIX IV (E/GT/GX)") or (device = "stratix iv (e/gt/gx)") or (device = "Stratix IV (E/GX/GT)") or (device = "STRATIX IV (E/GX/GT)") or (device = "stratix iv (e/gx/gt)") or (device = "StratixIV(GT/GX/E)") or (device = "STRATIXIV(GT/GX/E)") or (device = "stratixiv(gt/gx/e)") or (device = "StratixIV(GT/E/GX)") or (device = "STRATIXIV(GT/E/GX)") or (device = "stratixiv(gt/e/gx)") or (device = "StratixIV(E/GX/GT)") or (device = "STRATIXIV(E/GX/GT)") or (device = "stratixiv(e/gx/gt)") or (device = "StratixIV(E/GT/GX)") or (device = "STRATIXIV(E/GT/GX)") or (device = "stratixiv(e/gt/gx)") or (device = "Stratix IV (GX/E)") or (device = "STRATIX IV (GX/E)") or (device = "stratix iv (gx/e)") or (device = "StratixIV(GX/E)") or (device = "STRATIXIV(GX/E)") or (device = "stratixiv(gx/e)"))
or ((device = "tgx_commercial_v1_1") or (device = "TGX_COMMERCIAL_V1_1"))
or ((device = "Arria II GX") or (device = "ARRIA II GX") or (device = "arria ii gx") or (device = "ArriaIIGX") or (device = "ARRIAIIGX") or (device = "arriaiigx") or (device = "Arria IIGX") or (device = "ARRIA IIGX") or (device = "arria iigx") or (device = "ArriaII GX") or (device = "ARRIAII GX") or (device = "arriaii gx") or (device = "Arria II") or (device = "ARRIA II") or (device = "arria ii") or (device = "ArriaII") or (device = "ARRIAII") or (device = "arriaii") or (device = "Arria II (GX/E)") or (device = "ARRIA II (GX/E)") or (device = "arria ii (gx/e)") or (device = "ArriaII(GX/E)") or (device = "ARRIAII(GX/E)") or (device = "arriaii(gx/e)") or (device = "PIRANHA") or (device = "piranha"))
or ((device = "HardCopy III") or (device = "HARDCOPY III") or (device = "hardcopy iii") or (device = "HardCopyIII") or (device = "HARDCOPYIII") or (device = "hardcopyiii") or (device = "HCX") or (device = "hcx"))
or ((device = "HardCopy IV") or (device = "HARDCOPY IV") or (device = "hardcopy iv") or (device = "HardCopyIV") or (device = "HARDCOPYIV") or (device = "hardcopyiv") or (device = "HardCopy IV (GX)") or (device = "HARDCOPY IV (GX)") or (device = "hardcopy iv (gx)") or (device = "HardCopy IV (E)") or (device = "HARDCOPY IV (E)") or (device = "hardcopy iv (e)") or (device = "HardCopyIV(GX)") or (device = "HARDCOPYIV(GX)") or (device = "hardcopyiv(gx)") or (device = "HardCopyIV(E)") or (device = "HARDCOPYIV(E)") or (device = "hardcopyiv(e)") or (device = "HCXIV") or (device = "hcxiv") or (device = "HardCopy IV (GX/E)") or (device = "HARDCOPY IV (GX/E)") or (device = "hardcopy iv (gx/e)") or (device = "HardCopy IV (E/GX)") or (device = "HARDCOPY IV (E/GX)") or (device = "hardcopy iv (e/gx)") or (device = "HardCopyIV(GX/E)") or (device = "HARDCOPYIV(GX/E)") or (device = "hardcopyiv(gx/e)") or (device = "HardCopyIV(E/GX)") or (device = "HARDCOPYIV(E/GX)") or (device = "hardcopyiv(e/gx)"))
or ((device = "Cyclone III LS") or (device = "CYCLONE III LS") or (device = "cyclone iii ls") or (device = "CycloneIIILS") or (device = "CYCLONEIIILS") or (device = "cycloneiiils") or (device = "Cyclone III LPS") or (device = "CYCLONE III LPS") or (device = "cyclone iii lps") or (device = "Cyclone LPS") or (device = "CYCLONE LPS") or (device = "cyclone lps") or (device = "CycloneLPS") or (device = "CYCLONELPS") or (device = "cyclonelps") or (device = "Tarpon") or (device = "TARPON") or (device = "tarpon") or (device = "Cyclone IIIE") or (device = "CYCLONE IIIE") or (device = "cyclone iiie"))
or ((device = "Cyclone IV GX") or (device = "CYCLONE IV GX") or (device = "cyclone iv gx") or (device = "Cyclone IVGX") or (device = "CYCLONE IVGX") or (device = "cyclone ivgx") or (device = "CycloneIV GX") or (device = "CYCLONEIV GX") or (device = "cycloneiv gx") or (device = "CycloneIVGX") or (device = "CYCLONEIVGX") or (device = "cycloneivgx") or (device = "Cyclone IV") or (device = "CYCLONE IV") or (device = "cyclone iv") or (device = "CycloneIV") or (device = "CYCLONEIV") or (device = "cycloneiv") or (device = "Cyclone IV (GX)") or (device = "CYCLONE IV (GX)") or (device = "cyclone iv (gx)") or (device = "CycloneIV(GX)") or (device = "CYCLONEIV(GX)") or (device = "cycloneiv(gx)") or (device = "Cyclone III GX") or (device = "CYCLONE III GX") or (device = "cyclone iii gx") or (device = "CycloneIII GX") or (device = "CYCLONEIII GX") or (device = "cycloneiii gx") or (device = "Cyclone IIIGX") or (device = "CYCLONE IIIGX") or (device = "cyclone iiigx") or (device = "CycloneIIIGX") or (device = "CYCLONEIIIGX") or (device = "cycloneiiigx") or (device = "Cyclone III GL") or (device = "CYCLONE III GL") or (device = "cyclone iii gl") or (device = "CycloneIII GL") or (device = "CYCLONEIII GL") or (device = "cycloneiii gl") or (device = "Cyclone IIIGL") or (device = "CYCLONE IIIGL") or (device = "cyclone iiigl") or (device = "CycloneIIIGL") or (device = "CYCLONEIIIGL") or (device = "cycloneiiigl") or (device = "Stingray") or (device = "STINGRAY") or (device = "stingray"))
or ((device = "Cyclone IV E") or (device = "CYCLONE IV E") or (device = "cyclone iv e") or (device = "CycloneIV E") or (device = "CYCLONEIV E") or (device = "cycloneiv e") or (device = "Cyclone IVE") or (device = "CYCLONE IVE") or (device = "cyclone ive") or (device = "CycloneIVE") or (device = "CYCLONEIVE") or (device = "cycloneive"))
or ((device = "Stratix V") or (device = "STRATIX V") or (device = "stratix v") or (device = "StratixV") or (device = "STRATIXV") or (device = "stratixv") or (device = "Stratix V (GS)") or (device = "STRATIX V (GS)") or (device = "stratix v (gs)") or (device = "StratixV(GS)") or (device = "STRATIXV(GS)") or (device = "stratixv(gs)") or (device = "Stratix V (GT)") or (device = "STRATIX V (GT)") or (device = "stratix v (gt)") or (device = "StratixV(GT)") or (device = "STRATIXV(GT)") or (device = "stratixv(gt)") or (device = "Stratix V (GX)") or (device = "STRATIX V (GX)") or (device = "stratix v (gx)") or (device = "StratixV(GX)") or (device = "STRATIXV(GX)") or (device = "stratixv(gx)") or (device = "Stratix V (GS/GX)") or (device = "STRATIX V (GS/GX)") or (device = "stratix v (gs/gx)") or (device = "StratixV(GS/GX)") or (device = "STRATIXV(GS/GX)") or (device = "stratixv(gs/gx)") or (device = "Stratix V (GS/GT)") or (device = "STRATIX V (GS/GT)") or (device = "stratix v (gs/gt)") or (device = "StratixV(GS/GT)") or (device = "STRATIXV(GS/GT)") or (device = "stratixv(gs/gt)") or (device = "Stratix V (GT/GX)") or (device = "STRATIX V (GT/GX)") or (device = "stratix v (gt/gx)") or (device = "StratixV(GT/GX)") or (device = "STRATIXV(GT/GX)") or (device = "stratixv(gt/gx)") or (device = "Stratix V (GX/GS)") or (device = "STRATIX V (GX/GS)") or (device = "stratix v (gx/gs)") or (device = "StratixV(GX/GS)") or (device = "STRATIXV(GX/GS)") or (device = "stratixv(gx/gs)") or (device = "Stratix V (GT/GS)") or (device = "STRATIX V (GT/GS)") or (device = "stratix v (gt/gs)") or (device = "StratixV(GT/GS)") or (device = "STRATIXV(GT/GS)") or (device = "stratixv(gt/gs)") or (device = "Stratix V (GX/GT)") or (device = "STRATIX V (GX/GT)") or (device = "stratix v (gx/gt)") or (device = "StratixV(GX/GT)") or (device = "STRATIXV(GX/GT)") or (device = "stratixv(gx/gt)") or (device = "Stratix V (GS/GT/GX)") or (device = "STRATIX V (GS/GT/GX)") or (device = "stratix v (gs/gt/gx)") or (device = "Stratix V (GS/GX/GT)") or (device = "STRATIX V (GS/GX/GT)") or (device = "stratix v (gs/gx/gt)") or (device = "Stratix V (GT/GS/GX)") or (device = "STRATIX V (GT/GS/GX)") or (device = "stratix v (gt/gs/gx)") or (device = "Stratix V (GT/GX/GS)") or (device = "STRATIX V (GT/GX/GS)") or (device = "stratix v (gt/gx/gs)") or (device = "Stratix V (GX/GS/GT)") or (device = "STRATIX V (GX/GS/GT)") or (device = "stratix v (gx/gs/gt)") or (device = "Stratix V (GX/GT/GS)") or (device = "STRATIX V (GX/GT/GS)") or (device = "stratix v (gx/gt/gs)") or (device = "StratixV(GS/GT/GX)") or (device = "STRATIXV(GS/GT/GX)") or (device = "stratixv(gs/gt/gx)") or (device = "StratixV(GS/GX/GT)") or (device = "STRATIXV(GS/GX/GT)") or (device = "stratixv(gs/gx/gt)") or (device = "StratixV(GT/GS/GX)") or (device = "STRATIXV(GT/GS/GX)") or (device = "stratixv(gt/gs/gx)") or (device = "StratixV(GT/GX/GS)") or (device = "STRATIXV(GT/GX/GS)") or (device = "stratixv(gt/gx/gs)") or (device = "StratixV(GX/GS/GT)") or (device = "STRATIXV(GX/GS/GT)") or (device = "stratixv(gx/gs/gt)") or (device = "StratixV(GX/GT/GS)") or (device = "STRATIXV(GX/GT/GS)") or (device = "stratixv(gx/gt/gs)"))
or ((device = "Arria II GZ") or (device = "ARRIA II GZ") or (device = "arria ii gz") or (device = "ArriaII GZ") or (device = "ARRIAII GZ") or (device = "arriaii gz") or (device = "Arria IIGZ") or (device = "ARRIA IIGZ") or (device = "arria iigz") or (device = "ArriaIIGZ") or (device = "ARRIAIIGZ") or (device = "arriaiigz"))
or ((device = "arriaiigz_commercial_v1_1") or (device = "ARRIAIIGZ_COMMERCIAL_V1_1"))
or ((device = "MAX V") or (device = "max v") or (device = "MAXV") or (device = "maxv") or (device = "Jade") or (device = "JADE") or (device = "jade"))
or ((device = "Arria V") or (device = "ARRIA V") or (device = "arria v") or (device = "ArriaV") or (device = "ARRIAV") or (device = "arriav")))
then
is_valid := true;
end if;
return is_valid;
end IS_VALID_FAMILY;
end LPM_DEVICE_FAMILIES;
-- END OF PACKAGE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_constant
--
-- Description : Parameterized constant generator megafunction. lpm_constant
-- may be useful for convert a parameter into a constant.
--
-- Limitation : n/a
--
-- results Expected: Value specified by the argument to lpm_cvalue.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_CONSTANT is
-- GENERIC DECLARATION
generic (
lpm_width : natural; -- Width of the result[] port. (Required)
lpm_cvalue : natural; -- Constant value to be driven out on the
-- result[] port. (Required)
lpm_strength : string := "UNUSED";
lpm_type : string := "LPM_CONSTANT";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
-- // Value specified by the argument to lpm_cvalue. (Required)
result : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_CONSTANT;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_CONSTANT is
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
result <= conv_std_logic_vector(lpm_cvalue, lpm_width);
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_inv
--
-- Description : Parameterized inverter megafunction.
--
-- Limitation : n/a
--
-- results Expected: Inverted value of input data.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_INV is
-- GENERIC DECLARATION
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_type : string := "LPM_INV";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
data : in std_logic_vector(lpm_width-1 downto 0);
result : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_INV;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_INV is
begin
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
result <= not data;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_and
--
-- Description : Parameterized AND gate. This megafunction takes in data inputs
-- for a number of AND gates.
--
-- Limitation : n/a
--
-- results Expected: Each result[] bit is the result of each AND gate.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity lpm_and is
generic (
-- Width of the data[][] and result[] ports. Number of AND gates. (Required)
lpm_width : natural;
-- Number of inputs to each AND gate. Number of input buses. (Required)
lpm_size : natural;
lpm_type : string := "LPM_AND";
lpm_hint : string := "UNUSED"
);
port (
-- Data input to the AND gates. (Required)
data : in std_logic_2D(lpm_size-1 downto 0, lpm_width-1 downto 0);
-- Result of the AND operators. (Required)
result : out std_logic_vector(lpm_width-1 downto 0)
);
end lpm_and;
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of lpm_and is
-- SIGNAL DECLARATION
signal result_int : std_logic_2d(lpm_size-1 downto 0,lpm_width-1 downto 0);
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_size <= 0) then
ASSERT FALSE
REPORT "Value of lpm_size parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process; -- MSG process
L1: for i in 0 to lpm_width-1 generate
result_int(0,i) <= data(0,i);
L2: for j in 0 to lpm_size-2 generate
result_int(j+1,i) <= result_int(j,i) and data(j+1,i);
L3: if j = lpm_size-2 generate
result(i) <= result_int(lpm_size-1,i);
end generate L3;
end generate L2;
L4: if lpm_size = 1 generate
result(i) <= result_int(0,i);
end generate L4;
end generate L1;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_or
--
-- Description : Parameterized OR gate megafunction. This megafunction takes in
-- data inputs for a number of OR gates.
--
-- Limitation : n/a
--
-- results Expected: Each result[] bit is the result of each OR gate.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_OR is
generic (
-- Width of the data[] and result[] ports. Number of OR gates. (Required)
lpm_width : natural;
-- Number of inputs to each OR gate. Number of input buses. (Required)
lpm_size : natural;
lpm_type : string := "LPM_OR";
lpm_hint : string := "UNUSED"
);
port (
-- Data input to the OR gates. (Required)
data : in std_logic_2D(lpm_size-1 downto 0, lpm_width-1 downto 0);
-- Result of OR operators. (Required)
result : out std_logic_vector(lpm_width-1 downto 0));
end LPM_OR;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_OR is
-- SIGNAL DECLARATION
signal result_int : std_logic_2d(lpm_size-1 downto 0,lpm_width-1 downto 0);
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_size <= 0) then
ASSERT FALSE
REPORT "Value of lpm_size parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
L1: for i in 0 to lpm_width-1 generate
result_int(0,i) <= data(0,i);
L2: for j in 0 to lpm_size-2 generate
result_int(j+1,i) <= result_int(j,i) or data(j+1,i);
L3: if j = lpm_size-2 generate
result(i) <= result_int(lpm_size-1,i);
end generate L3;
end generate L2;
L4: if lpm_size = 1 generate
result(i) <= result_int(0,i);
end generate L4;
end generate L1;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_xor
--
-- Description : Parameterized XOR gate megafunction. This megafunction takes in
-- data inputs for a number of XOR gates.
--
-- Limitation : n/a
--
-- results Expected: Each result[] bit is the result of each XOR gates.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_XOR is
generic (
-- Width of the data[] and result[] ports. Number of XOR gates. (Required)
lpm_width : natural;
-- Number of inputs to each XOR gate. Number of input buses. (Required)
lpm_size : natural;
lpm_type : string := "LPM_XOR";
lpm_hint : string := "UNUSED");
port (
-- data input to the XOR gates. (Required)
data : in std_logic_2D(lpm_size-1 downto 0, lpm_width-1 downto 0);
-- result of XOR operators. (Required)
result : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_XOR;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_XOR is
-- SIGNAL DECLARATION
signal result_int : std_logic_2d(lpm_size-1 downto 0,lpm_width-1 downto 0);
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_size <= 0) then
ASSERT FALSE
REPORT "Value of lpm_size parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
L1: for i in 0 to lpm_width-1 generate
result_int(0,i) <= data(0,i);
L2: for j in 0 to lpm_size-2 generate
result_int(j+1,i) <= result_int(j,i) xor data(j+1,i);
L3: if j = lpm_size-2 generate
result(i) <= result_int(lpm_size-1,i);
end generate L3;
end generate L2;
L4: if lpm_size = 1 generate
result(i) <= result_int(0,i);
end generate L4;
end generate L1;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_bustri
--
-- Description : Parameterized tri-state buffer. lpm_bustri is useful for
-- controlling both unidirectional and bidirectional I/O bus
-- controllers.
--
-- Limitation : n/a
--
-- results Expected: Belows are the three configurations which are valid:
--
-- 1) Only the input ports data[lpm_width-1..0] and enabledt are
-- present, and only the output ports tridata[lpm_width-1..0]
-- are present.
--
-- ----------------------------------------------------
-- | Input | Output |
-- |====================================================|
-- | enabledt | tridata[lpm_width-1..0] |
-- |----------------------------------------------------|
-- | 0 | Z |
-- |----------------------------------------------------|
-- | 1 | data[lpm_width-1..0] |
-- ----------------------------------------------------
--
-- 2) Only the input ports tridata[lpm_width-1..0] and enabletr
-- are present, and only the output ports result[lpm_width-1..0]
-- are present.
--
-- ----------------------------------------------------
-- | Input | Output |
-- |====================================================|
-- | enabletr | result[lpm_width-1..0] |
-- |----------------------------------------------------|
-- | 0 | Z |
-- |----------------------------------------------------|
-- | 1 | tridata[lpm_width-1..0] |
-- ----------------------------------------------------
--
-- 3) All ports are present: input ports data[lpm_width-1..0],
-- enabledt, and enabletr; output ports result[lpm_width-1..0];
-- and bidirectional ports tridata[lpm_width-1..0].
--
-- ----------------------------------------------------------------------------
-- | Input | Bidirectional | Output |
-- |----------------------------------------------------------------------------|
-- | enabledt | enabletr | tridata[lpm_width-1..0] | result[lpm_width-1..0] |
-- |============================================================================|
-- | 0 | 0 | Z (input) | Z |
-- |----------------------------------------------------------------------------|
-- | 0 | 1 | Z (input) | tridata[lpm_width-1..0] |
-- |----------------------------------------------------------------------------|
-- | 1 | 0 | data[lpm_width-1..0] | Z |
-- |----------------------------------------------------------------------------|
-- | 1 | 1 | data[lpm_width-1..0] | data[lpm_width-1..0] |
-- ----------------------------------------------------------------------------
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_BUSTRI is
-- GENERIC DECLARATION
generic (
lpm_width : natural; -- MUST be greater than 0 (Required)
lpm_type : string := "LPM_BUSTRI";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
-- Bidirectional bus signal. (Required)
tridata : inout std_logic_vector(lpm_width-1 downto 0);
-- Data input to the tridata[] bus. (Required)
data : in std_logic_vector(lpm_width-1 downto 0);
-- If high, enables tridata[] onto the result bus.
enabletr : in std_logic := '1';
-- If high, enables data onto the tridata[] bus.
enabledt : in std_logic := '1';
-- Output from the tridata[] bus.
result : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_BUSTRI;
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_BUSTRI is
begin
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
-- get the tri-state buffer output
BUSTRI: process(data, tridata, enabletr, enabledt)
begin
if enabledt = '0' and enabletr = '1' then
result <= tridata;
elsif enabledt = '1' and enabletr = '0' then
result <= (OTHERS => 'Z');
elsif enabledt = '1' and enabletr = '1' then
result <= data;
else
result <= (OTHERS => 'Z');
end if;
end process BUSTRI;
-- SIGNAL ASSIGNMENT
tridata <= data when (enabledt = '1')
else (OTHERS => 'Z');
end LPM_SYN;
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_mux
--
-- Description : Parameterized multiplexer megafunctions.
--
-- Limitation : n/a
--
-- results Expected: Selected input port.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_MUX is
-- GENERIC DECLARATION
generic (
lpm_width : natural; -- Width of the data[][] and result[] ports. (Required)
lpm_size : natural; -- Number of input buses to the multiplexer. (Required)
lpm_widths : natural; -- Width of the sel[] input port. (Required)
lpm_pipeline : natural := 0;-- Specifies the number of Clock cycles of latency
-- associated with the result[] output.
lpm_type : string := "LPM_MUX";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
-- Data input. (Required)
data : in std_logic_2D(lpm_size-1 downto 0, lpm_width-1 downto 0);
-- Selects one of the input buses. (Required)
sel : in std_logic_vector(lpm_widths-1 downto 0);
-- Clock for pipelined usage
clock : in std_logic := '0';
-- Asynchronous clear for pipelined usage.
aclr : in std_logic := '0';
-- Clock enable for pipelined usage.
clken : in std_logic := '1';
-- Selected input port. (Required)
result : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_MUX;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_MUX is
-- TYPE DECLARATION
type t_resulttmp IS ARRAY (0 to lpm_pipeline) of std_logic_vector(lpm_width-1 downto 0);
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_size <= 1) then
ASSERT FALSE
REPORT "Value of lpm_size parameter must be greater than 1!"
SEVERITY ERROR;
end if;
if (lpm_widths <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widths parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_pipeline < 0) then
ASSERT FALSE
REPORT "Value of lpm_pipeline parameter must be greater than or equal to 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process (aclr, clock, sel, data, clken)
variable resulttmp : t_resulttmp;
variable sel_int : integer;
begin
if (lpm_pipeline >= 0) then
sel_int := conv_integer(sel);
for i in 0 to lpm_width-1 loop
if (sel_int < lpm_size) then
resulttmp(lpm_pipeline)(i) := data(sel_int,i);
else
resulttmp(lpm_pipeline)(i) := 'X';
end if;
end loop;
if (lpm_pipeline > 0) then
if (aclr = '1') then
for i in 0 to lpm_pipeline loop
resulttmp(i) := (OTHERS => '0');
end loop;
elsif (rising_edge(clock) and clken = '1') then
resulttmp(0 to lpm_pipeline - 1) := resulttmp(1 to lpm_pipeline);
end if;
end if;
result <= resulttmp(0);
end if;
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_decode
--
-- Description : Parameterized decoder megafunction.
--
-- Limitation : n/a
--
-- Results Expected: Decoded output.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_DECODE is
generic (
-- Width of the data[] port, or the input value to be decoded. (Required)
lpm_width : natural;
-- Number of explicit decoder outputs. (Required)
lpm_decodes : natural;
-- Number of Clock cycles of latency
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_DECODE";
lpm_hint : string := "UNUSED"
);
port (
-- Data input. Treated as an unsigned binary encoded number. (Required)
data : in std_logic_vector(lpm_width-1 downto 0);
-- Enable. All outputs low when not active.
enable : in std_logic := '1';
-- Clock for pipelined usage.
clock : in std_logic := '0';
-- Asynchronous clear for pipelined usage.
aclr : in std_logic := '0';
-- Clock enable for pipelined usage.
clken : in std_logic := '1';
-- Decoded output. (Required)
eq : out std_logic_vector(lpm_decodes-1 downto 0)
);
end LPM_DECODE;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_DECODE is
-- TYPE DECLARATION
type t_eqtmp IS ARRAY (0 to lpm_pipeline) of std_logic_vector(lpm_decodes-1 downto 0);
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_decodes <= 0) then
ASSERT FALSE
REPORT "Value of lpm_decodes parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_decodes > (2**lpm_width)) then
ASSERT FALSE
REPORT "Value of lpm_decodes parameter must be less or equal to 2^lpm_width!"
SEVERITY ERROR;
end if;
if (lpm_pipeline < 0) then
ASSERT FALSE
REPORT "Value of lpm_pipeline parameter must be greater or equal to 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process(aclr, clock, data, enable)
variable eqtmp : t_eqtmp;
begin
for i in 0 to lpm_decodes-1 loop
if (conv_integer(data) = i) then
if (enable = '1') then
eqtmp(lpm_pipeline)(i) := '1';
else
eqtmp(lpm_pipeline)(i) := '0';
end if;
else
eqtmp(lpm_pipeline)(i) := '0';
end if;
end loop;
if (aclr = '1') then
if (lpm_pipeline > 0) then
for i in 0 to lpm_pipeline loop
eqtmp(i) := (OTHERS => '0');
end loop;
end if;
elsif (clock'event and (clock = '1')) then
if ((clken = '1') and (lpm_pipeline > 0)) then
eqtmp(0 to lpm_pipeline - 1) := eqtmp(1 to lpm_pipeline);
end if;
end if;
eq <= eqtmp(0);
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_clshift
--
-- Description : Parameterized combinatorial logic shifter or barrel shifter
-- megafunction.
--
-- Limitation : n/a
--
-- results Expected: Return the shifted data and underflow/overflow status bit.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_CLSHIFT is
-- GENERIC DECLARATION
generic (
lpm_width : natural; -- Width of the data[] and result[] ports.
-- MUST be greater than 0 (Required)
lpm_widthdist : natural; -- Width of the distance[] input port.
-- MUST be greater than 0 (Required)
lpm_shifttype : string := "LOGICAL"; -- Type of shifting operation to be performed.
lpm_pipeline : natural := 0; -- Number of Clock cycles of latency.
lpm_type : string := "LPM_CLSHIFT";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
-- data to be shifted. (Required)
data : in STD_LOGIC_VECTOR(lpm_width-1 downto 0);
-- Number of positions to shift data[] in the direction specified by the
-- direction port. (Required)
distance : in STD_LOGIC_VECTOR(lpm_widthdist-1 downto 0);
-- direction of shift. Low = left (toward the MSB), high = right (toward the LSB).
direction : in STD_LOGIC := '0';
-- Clock for pipelined usage.
clock : in std_logic := '0';
-- Asynchronous clear for pipelined usage.
aclr : in std_logic := '0';
-- Clock enable for pipelined usage.
clken : in std_logic := '1';
-- Shifted data. (Required)
result : out STD_LOGIC_VECTOR(lpm_width-1 downto 0);
-- Logical or arithmetic underflow.
underflow : out STD_LOGIC;
-- Logical or arithmetic overflow.
overflow : out STD_LOGIC
);
end LPM_CLSHIFT;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_CLSHIFT is
-- TYPE DECLARATION
type t_resulttmp IS ARRAY (0 to lpm_pipeline) of std_logic_vector(lpm_width-1 downto 0);
-- SIGNAL DECLARATION
signal i_result : std_logic_vector(lpm_width-1 downto 0);
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_widthdist <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widthdist parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
-- Get the shifted data
process(data, distance, direction)
variable tmpdata : std_logic_vector(lpm_width-1 downto 0);
variable tmpdist : integer;
begin
if ((lpm_shifttype = "ARITHMETIC") or (lpm_shifttype = "LOGICAL")) then
tmpdata := conv_std_logic_vector(unsigned(data), lpm_width);
tmpdist := conv_integer(unsigned(distance));
for i in lpm_width-1 downto 0 loop
if (direction = '0') then
if (i >= tmpdist) then
i_result(i) <= tmpdata(i-tmpdist);
else
i_result(i) <= '0';
end if;
elsif (direction = '1') then
if ((i+tmpdist) < lpm_width) then
i_result(i) <= tmpdata(i+tmpdist);
elsif (lpm_shifttype = "ARITHMETIC") then
i_result(i) <= data(lpm_width-1);
else
i_result(i) <= '0';
end if;
end if;
end loop;
elsif (lpm_shifttype = "ROTATE") then
tmpdata := conv_std_logic_vector(unsigned(data), lpm_width);
tmpdist := conv_integer(unsigned(distance)) mod lpm_width;
for i in lpm_width-1 downto 0 loop
if (direction = '0') then
if (i >= tmpdist) then
i_result(i) <= tmpdata(i-tmpdist);
else
i_result(i) <= tmpdata(i+lpm_width-tmpdist);
end if;
elsif (direction = '1') then
if (i+tmpdist < lpm_width) then
i_result(i) <= tmpdata(i+tmpdist);
else
i_result(i) <= tmpdata(i-lpm_width+tmpdist);
end if;
end if;
end loop;
else
ASSERT FALSE
REPORT "Illegal lpm_shifttype property value for LPM_CLSHIFT!"
SEVERITY ERROR;
end if;
end process;
-- Get the overflow/underflow status bit.
process(aclr, clock, data, distance, direction, i_result)
variable neg_one : signed(lpm_width-1 downto 0) := (OTHERS => '1');
variable tmpdata : std_logic_vector(lpm_width-1 downto 0);
variable tmpdist : integer;
variable msb_cnt : integer := 0;
variable lsb_cnt : integer := 0;
variable sgn_bit : std_logic;
variable result_pipe : t_resulttmp := (OTHERS => (OTHERS => '0'));
variable overflow_pipe : std_logic_vector(0 to lpm_pipeline) := (OTHERS => '0');
variable underflow_pipe : std_logic_vector(0 to lpm_pipeline) := (OTHERS => '0');
begin
tmpdata := conv_std_logic_vector(unsigned(data), lpm_width);
tmpdist := conv_integer(distance);
result_pipe(lpm_pipeline) := i_result;
overflow_pipe(lpm_pipeline) := '0';
underflow_pipe(lpm_pipeline) := '0';
if ((tmpdist /= 0) and (tmpdata /= 0)) then
if (lpm_shifttype = "ROTATE") then
overflow_pipe(lpm_pipeline) := 'U';
underflow_pipe(lpm_pipeline) := 'U';
else
if (tmpdist < lpm_width) then
if (lpm_shifttype = "LOGICAL") then
msb_cnt := 0;
while ((msb_cnt < lpm_width) and
(tmpdata(lpm_width-msb_cnt-1) = '0')) loop
msb_cnt := msb_cnt + 1;
end loop;
if ((tmpdist > msb_cnt) and (direction = '0')) then
overflow_pipe(lpm_pipeline) := '1';
elsif ((tmpdist + msb_cnt >= lpm_width) and (direction = '1')) then
underflow_pipe(lpm_pipeline) := '1';
end if;
elsif (lpm_shifttype = "ARITHMETIC") then
sgn_bit := '0';
if (tmpdata(lpm_width-1) = '1') then
sgn_bit := '1';
end if;
msb_cnt := 0;
while ((msb_cnt < lpm_width) and
(tmpdata(lpm_width-msb_cnt-1) = sgn_bit)) loop
msb_cnt := msb_cnt + 1;
end loop;
lsb_cnt := 0;
while ((lsb_cnt < lpm_width) and (tmpdata(lsb_cnt) = '0')) loop
lsb_cnt := lsb_cnt + 1;
end loop;
if (direction = '1') then -- shift right
if (tmpdata(lpm_width-1) = '1') then -- negative
if ((msb_cnt + tmpdist >= lpm_width) and
(msb_cnt /= lpm_width)) then
underflow_pipe(lpm_pipeline) := '1';
end if;
else -- non-neg
if (((msb_cnt + tmpdist) >= lpm_width) and
(msb_cnt /= lpm_width)) then
underflow_pipe(lpm_pipeline) := '1';
end if;
end if;
elsif (direction = '0') then -- shift left
if (tmpdata(lpm_width-1) = '1') then -- negative
if (((signed(tmpdata) /= neg_one) and
(tmpdist >= lpm_width)) or (tmpdist >= msb_cnt)) then
overflow_pipe(lpm_pipeline) := '1';
end if;
else -- non-neg
if (((tmpdata /= 0) and (tmpdist >= lpm_width-1)) or
(tmpdist >= msb_cnt)) then
overflow_pipe(lpm_pipeline) := '1';
end if;
end if;
end if;
end if;
else
if (direction = '0') then
overflow_pipe(lpm_pipeline) := '1';
elsif (direction = '1') then
underflow_pipe(lpm_pipeline) := '1';
end if;
end if; -- tmpdist < lpm_width
end if; -- lpm_shifttype = "ROTATE"
end if; -- tmpdist /= 0 and tmpdata /= 0
if (aclr = '1') then
if (lpm_pipeline > 0) then
result_pipe := (OTHERS => (OTHERS => '0'));
overflow_pipe := (OTHERS => '0');
underflow_pipe := (OTHERS => '0');
end if;
elsif (clock'event and (clock = '1')) then
if ((clken = '1') and (lpm_pipeline > 0)) then
result_pipe(0 to lpm_pipeline - 1) := result_pipe(1 to lpm_pipeline);
overflow_pipe(0 to lpm_pipeline - 1) := overflow_pipe(1 to lpm_pipeline);
underflow_pipe(0 to lpm_pipeline - 1) := underflow_pipe(1 to lpm_pipeline);
end if;
end if;
result <= result_pipe(0);
overflow <= overflow_pipe(0);
underflow <= underflow_pipe(0);
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_add_sub_signed
--
-- Description : This entity is instiatiated by lpm_add_sub megafunction to perform
-- adder/subtrator function for signed number.
--
-- Limitation : n/a
--
-- Results Expected: If performs as adder, the result will be dataa[]+datab[]+cin.
-- If performs as subtractor, the result will be dataa[]-datab[]+cin-1.
-- Also returns carry out bit and overflow status bit.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_ADD_SUB_SIGNED is
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_direction : string := "UNUSED";
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_ADD_SUB";
lpm_hint : string := "UNUSED"
);
port (
dataa : in std_logic_vector(lpm_width downto 1);
datab : in std_logic_vector(lpm_width downto 1);
cin : in std_logic := 'Z';
add_sub : in std_logic := '1';
clock : in std_logic := '0';
aclr : in std_logic := '0';
clken : in std_logic := '1';
result : out std_logic_vector(lpm_width-1 downto 0);
cout : out std_logic;
overflow : out std_logic
);
end LPM_ADD_SUB_SIGNED;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_ADD_SUB_SIGNED is
-- SIGNAL DECLARATION
signal i_dataa, i_datab : std_logic_vector(lpm_width downto 0);
-- TYPE DECLARATION
type T_RESULTTMP IS ARRAY (0 to lpm_pipeline) of std_logic_vector(lpm_width downto 0);
begin
i_dataa <= (dataa(lpm_width) & dataa);
i_datab <= (datab(lpm_width) & datab);
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_pipeline < 0) then
ASSERT FALSE
REPORT "Value of lpm_pipeline parameter must be greater than or equal to 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process(aclr, clock, i_dataa, i_datab, cin, add_sub)
variable resulttmp : T_RESULTTMP := (OTHERS => (OTHERS => '0'));
variable couttmp : std_logic_vector(0 to lpm_pipeline) := (OTHERS => '0');
variable overflowtmp : std_logic_vector(0 to lpm_pipeline) := (OTHERS => '0');
variable i_cin : std_logic;
begin
if ((lpm_direction = "ADD") or
(((lpm_direction = "UNUSED") or (lpm_direction = "DEFAULT"))and (add_sub = '1'))) then
if (cin = 'Z') then
i_cin := '0';
else
i_cin := cin;
end if;
-- Perform as adder
resulttmp(lpm_pipeline) := i_dataa + i_datab + i_cin;
couttmp(lpm_pipeline) := resulttmp(lpm_pipeline)(lpm_width) xor
i_dataa(lpm_width) xor
i_datab(lpm_width);
if ((i_dataa(lpm_width) = '0') and (i_datab(lpm_width) = '0') and
(resulttmp(lpm_pipeline)(lpm_width-1) = '1')) or
((i_dataa(lpm_width) = '1') and (i_datab(lpm_width) = '1') and
(resulttmp(lpm_pipeline)(lpm_width-1) = '0')) then
overflowtmp(lpm_pipeline) := '1';
else
overflowtmp(lpm_pipeline) := '0';
end if;
elsif ((lpm_direction = "SUB") or
(((lpm_direction = "UNUSED") or (lpm_direction = "DEFAULT")) and (add_sub = '0'))) then
if (cin = 'Z') then
i_cin := '1';
else
i_cin := cin;
end if;
-- Perform as subtrator
resulttmp(lpm_pipeline) := i_dataa - i_datab + i_cin - 1;
couttmp(lpm_pipeline) := (not resulttmp(lpm_pipeline)(lpm_width)) xor
i_dataa(lpm_width) xor
i_datab(lpm_width);
if ((i_dataa(lpm_width) = '0') and (i_datab(lpm_width) = '1') and
(resulttmp(lpm_pipeline)(lpm_width-1) = '1')) or
((i_dataa(lpm_width) = '1') and (i_datab(lpm_width) = '0') and
(resulttmp(lpm_pipeline)(lpm_width-1) = '0')) then
overflowtmp(lpm_pipeline) := '1';
else
overflowtmp(lpm_pipeline) := '0';
end if;
elsif ((lpm_direction /= "UNUSED") and (lpm_direction /= "DEFAULT")) then
ASSERT FALSE
REPORT "Illegal lpm_direction property value for LPM_ADD_SUB!"
SEVERITY ERROR;
end if;
-- Pipeline the result
if (aclr = '1') then
if (lpm_pipeline > 0) then
overflowtmp := (OTHERS => '0');
couttmp := (OTHERS => '0');
for i in 0 to lpm_pipeline loop
resulttmp(i) := (OTHERS => '0');
end loop;
end if;
elsif (clock'event and (clock = '1')) then
if ((clken = '1') and (lpm_pipeline > 0)) then
overflowtmp(0 to lpm_pipeline - 1) := overflowtmp(1 to lpm_pipeline);
couttmp(0 to lpm_pipeline - 1) := couttmp(1 to lpm_pipeline);
resulttmp(0 to lpm_pipeline - 1) := resulttmp(1 to lpm_pipeline);
end if;
end if;
-- send the pipeline result to output ports
cout <= couttmp(0);
overflow <= overflowtmp(0);
result <= resulttmp(0)(lpm_width-1 downto 0);
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_add_sub_unsigned
--
-- Description : This entity is instiatiated by lpm_add_sub megafunction to perform
-- adder/subtrator function for unsigned number.
--
-- Limitation : n/a
--
-- Results Expected: If performs as adder, the result will be dataa[]+datab[]+cin.
-- If performs as subtractor, the result will be dataa[]-datab[]+cin-1.
-- Also returns carry out bit and overflow status bit.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_ADD_SUB_UNSIGNED is
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_direction : string := "UNUSED";
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_ADD_SUB";
lpm_hint : string := "UNUSED"
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
datab : in std_logic_vector(lpm_width-1 downto 0);
cin : in std_logic := 'Z';
add_sub : in std_logic := '1';
clock : in std_logic := '0';
aclr : in std_logic := '0';
clken : in std_logic := '1';
result : out std_logic_vector(lpm_width-1 downto 0);
cout : out std_logic;
overflow : out std_logic
);
end LPM_ADD_SUB_UNSIGNED;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_ADD_SUB_UNSIGNED is
-- SIGNAL DECLARATION
signal i_dataa, i_datab : std_logic_vector(lpm_width downto 0);
-- TYPE DECLARATION
type T_RESULTTMP IS ARRAY (0 to lpm_pipeline) of std_logic_vector(lpm_width downto 0);
begin
i_dataa <= ('0' & dataa);
i_datab <= ('0' & datab);
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_pipeline < 0) then
ASSERT FALSE
REPORT "Value of lpm_pipeline parameter must be greater than or equal to 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process(aclr, clock, i_dataa, i_datab, cin, add_sub)
variable resulttmp : T_RESULTTMP := (OTHERS => (OTHERS => '0'));
variable couttmp : std_logic_vector(0 to lpm_pipeline) := (OTHERS => '0');
variable overflowtmp : std_logic_vector(0 to lpm_pipeline) := (OTHERS => '0');
variable i_cin : std_logic;
begin
if ((lpm_direction = "ADD") or
(((lpm_direction = "UNUSED") or (lpm_direction = "DEFAULT")) and (add_sub = '1'))) then
if (cin = 'Z') then
i_cin := '0';
else
i_cin := cin;
end if;
-- Perform as adder
resulttmp(lpm_pipeline) := i_dataa + i_datab + i_cin;
couttmp(lpm_pipeline) := resulttmp(lpm_pipeline)(lpm_width);
elsif ((lpm_direction = "SUB") or
(((lpm_direction = "UNUSED") or (lpm_direction = "DEFAULT")) and (add_sub = '0'))) then
if (cin = 'Z') then
i_cin := '1';
else
i_cin := cin;
end if;
-- Perform as subtractor
resulttmp(lpm_pipeline) := i_dataa - i_datab + i_cin - 1;
couttmp(lpm_pipeline) := not resulttmp(lpm_pipeline)(lpm_width);
elsif ((lpm_direction /= "UNUSED") and (lpm_direction /= "DEFAULT")) then
ASSERT FALSE
REPORT "Illegal lpm_direction property value for LPM_ADD_SUB!"
SEVERITY ERROR;
end if;
overflowtmp(lpm_pipeline) := resulttmp(lpm_pipeline)(lpm_width);
-- Pipeline the result
if (aclr = '1') then
if (lpm_pipeline > 0) then
overflowtmp := (OTHERS => '0');
couttmp := (OTHERS => '0');
for i in 0 to lpm_pipeline loop
resulttmp(i) := (OTHERS => '0');
end loop;
end if;
elsif (clock'event and (clock = '1') ) then
if ((clken = '1') and (lpm_pipeline > 0)) then
overflowtmp(0 to lpm_pipeline - 1) := overflowtmp(1 to lpm_pipeline);
couttmp(0 to lpm_pipeline - 1) := couttmp(1 to lpm_pipeline);
resulttmp(0 to lpm_pipeline - 1) := resulttmp(1 to lpm_pipeline);
end if;
end if;
-- Send the pipelined result to output ports
cout <= couttmp(0);
overflow <= overflowtmp(0);
result <= resulttmp(0)(lpm_width-1 downto 0);
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_add_sub
--
-- Description : Parameterized adder/subtractor megafunction.
--
-- Limitation : n/a
--
-- Results Expected: If performs as adder, the result will be dataa[]+datab[]+cin.
-- If performs as subtractor, the result will be dataa[]-datab[]+cin-1.
-- Also returns carry out bit and overflow status bit.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
use work.LPM_ADD_SUB_SIGNED;
use work.LPM_ADD_SUB_UNSIGNED;
-- ENTITY DECLARATION
entity LPM_ADD_SUB is
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_representation : string := "SIGNED";
lpm_direction : string := "UNUSED";
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_ADD_SUB";
lpm_hint : string := "UNUSED"
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
datab : in std_logic_vector(lpm_width-1 downto 0);
cin : in std_logic := 'Z';
add_sub : in std_logic := '1';
clock : in std_logic := '0';
aclr : in std_logic := '0';
clken : in std_logic := '1';
result : out std_logic_vector(lpm_width-1 downto 0);
cout : out std_logic;
overflow : out std_logic
);
end LPM_ADD_SUB;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_ADD_SUB is
-- COMPONENT DECLARATION
component LPM_ADD_SUB_SIGNED
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_direction : string := "UNUSED";
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_ADD_SUB";
lpm_hint : string := "UNUSED"
);
port (
dataa : in std_logic_vector(lpm_width downto 1);
datab : in std_logic_vector(lpm_width downto 1);
cin : in std_logic := 'Z';
add_sub : in std_logic := '1';
clock : in std_logic := '0';
aclr : in std_logic := '0';
clken : in std_logic := '1';
result : out std_logic_vector(lpm_width-1 downto 0);
cout : out std_logic;
overflow : out std_logic
);
end component;
component LPM_ADD_SUB_UNSIGNED
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_direction : string := "UNUSED";
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_ADD_SUB";
lpm_hint : string := "UNUSED"
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
datab : in std_logic_vector(lpm_width-1 downto 0);
cin : in std_logic := 'Z';
add_sub : in std_logic := '1';
clock : in std_logic := '0';
aclr : in std_logic := '0';
clken : in std_logic := '1';
result : out std_logic_vector(lpm_width-1 downto 0);
cout : out std_logic;
overflow : out std_logic
);
end component;
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if ((lpm_representation /= "SIGNED") and
(lpm_representation /= "UNSIGNED")) then
ASSERT FALSE
REPORT "Value of lpm_representation parameter must be SIGNED or UNSIGNED!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
L1: if (lpm_representation = "UNSIGNED") generate
U: LPM_ADD_SUB_UNSIGNED
generic map (
lpm_width => lpm_width,
lpm_direction => lpm_direction,
lpm_pipeline => lpm_pipeline,
lpm_type => lpm_type,
lpm_hint => lpm_hint
)
port map (
dataa => dataa,
datab => datab,
cin => cin,
add_sub => add_sub,
clock => clock,
aclr => aclr,
clken => clken,
result => result,
cout => cout,
overflow => overflow
);
end generate;
L2: if (lpm_representation = "SIGNED") generate
V: LPM_ADD_SUB_SIGNED
generic map (
lpm_width => lpm_width,
lpm_direction => lpm_direction,
lpm_pipeline => lpm_pipeline,
lpm_type => lpm_type,
lpm_hint => lpm_hint
)
port map (
dataa => dataa,
datab => datab,
cin => cin,
add_sub => add_sub,
clock => clock,
aclr => aclr,
clken => clken,
result => result,
cout => cout,
overflow => overflow
);
end generate;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_compare_signed
--
-- Description : This module is used in lpm_compare megafunction when
-- type of comparison is "SIGNED".
--
-- Limitation : n/a
--
-- Results Expected: Return status bits of the comparision between dataa[] and
-- datab[].
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_COMPARE_SIGNED is
-- GENERIC DECLARATION
generic (
-- Width of the dataa[] and datab[] ports. (Required)
lpm_width : natural;
-- Specifies the number of clock cycles of latency associated with the
-- alb, aeb, agb, ageb, aleb or aneb output.
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_COMPARE";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
-- Value to be compared to datab[]. (Required)
dataa : in std_logic_vector(lpm_width-1 downto 0);
-- Value to be compared to dataa[]. (Required)
datab : in std_logic_vector(lpm_width-1 downto 0);
-- clock for pipelined usage.
clock : in std_logic := '0';
-- Asynchronous clear for pipelined usage.
aclr : in std_logic := '0';
-- clock enable for pipelined usage.
clken : in std_logic := '1';
-- One of the following ports must be present.
alb : out std_logic; -- High (1) if dataa[] < datab[].
aeb : out std_logic; -- High (1) if dataa[] == datab[].
agb : out std_logic; -- High (1) if dataa[] > datab[].
aleb : out std_logic; -- High (1) if dataa[] <= datab[].
aneb : out std_logic; -- High (1) if dataa[] != datab[].
ageb : out std_logic -- High (1) if dataa[] >= datab[].
);
end LPM_COMPARE_SIGNED;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_COMPARE_SIGNED is
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_pipeline < 0) then
ASSERT FALSE
REPORT "Value of lpm_pipeline parameter must NOT less than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
-- perform the data comparison
process(aclr, clock, dataa, datab)
variable agbtmp : std_logic_vector (0 to lpm_pipeline);
variable agebtmp : std_logic_vector (0 to lpm_pipeline);
variable aebtmp : std_logic_vector (0 to lpm_pipeline);
variable anebtmp : std_logic_vector (0 to lpm_pipeline);
variable albtmp : std_logic_vector (0 to lpm_pipeline);
variable alebtmp : std_logic_vector (0 to lpm_pipeline);
begin
-- get the status of comparation
if (signed(dataa) > signed(datab)) then
agbtmp(lpm_pipeline) := '1';
agebtmp(lpm_pipeline) := '1';
anebtmp(lpm_pipeline) := '1';
aebtmp(lpm_pipeline) := '0';
albtmp(lpm_pipeline) := '0';
alebtmp(lpm_pipeline) := '0';
elsif (signed(dataa) = signed(datab)) then
agbtmp(lpm_pipeline) := '0';
agebtmp(lpm_pipeline) := '1';
anebtmp(lpm_pipeline) := '0';
aebtmp(lpm_pipeline) := '1';
albtmp(lpm_pipeline) := '0';
alebtmp(lpm_pipeline) := '1';
else
agbtmp(lpm_pipeline) := '0';
agebtmp(lpm_pipeline) := '0';
anebtmp(lpm_pipeline) := '1';
aebtmp(lpm_pipeline) := '0';
albtmp(lpm_pipeline) := '1';
alebtmp(lpm_pipeline) := '1';
end if;
-- if lpm_pipine > 0, then create latency on the output result
if (aclr = '1') then
if (lpm_pipeline > 0) then
for i in 0 to lpm_pipeline loop
agbtmp(i) := '0';
agebtmp(i) := '0';
anebtmp(i) := '0';
aebtmp(i) := '0';
albtmp(i) := '0';
alebtmp(i) := '0';
end loop;
end if;
elsif (clock'event and (clock = '1')) then
if ((clken = '1') and (lpm_pipeline > 0)) then
agbtmp(0 to lpm_pipeline-1) := agbtmp(1 to lpm_pipeline);
agebtmp(0 to lpm_pipeline-1) := agebtmp(1 to lpm_pipeline) ;
anebtmp(0 to lpm_pipeline-1) := anebtmp(1 to lpm_pipeline);
aebtmp(0 to lpm_pipeline-1) := aebtmp(1 to lpm_pipeline);
albtmp(0 to lpm_pipeline-1) := albtmp(1 to lpm_pipeline);
alebtmp(0 to lpm_pipeline-1) := alebtmp(1 to lpm_pipeline);
end if;
end if;
agb <= agbtmp(0);
ageb <= agebtmp(0);
aneb <= anebtmp(0);
aeb <= aebtmp(0);
alb <= albtmp(0);
aleb <= alebtmp(0);
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_compare_unsigned
--
-- Description : This module is used in lpm_compare megafunction when
-- type of comparison is "UNSIGNED".
--
-- Limitation : n/a
--
-- Results Expected: Return status bits of the comparision between dataa[] and
-- datab[].
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_COMPARE_UNSIGNED is
-- GENERIC DECLARATION
generic (
-- Width of the dataa[] and datab[] ports. (Required)
lpm_width : natural;
-- Specifies the number of clock cycles of latency associated with the
-- alb, aeb, agb, ageb, aleb or aneb output.
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_COMPARE";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
-- Value to be compared to datab[]. (Required)
dataa : in std_logic_vector(lpm_width-1 downto 0);
-- Value to be compared to dataa[]. (Required)
datab : in std_logic_vector(lpm_width-1 downto 0);
-- clock for pipelined usage.
clock : in std_logic := '0';
-- Asynchronous clear for pipelined usage.
aclr : in std_logic := '0';
-- clock enable for pipelined usage.
clken : in std_logic := '1';
-- One of the following ports must be present.
alb : out std_logic; -- High (1) if dataa[] < datab[].
aeb : out std_logic; -- High (1) if dataa[] == datab[].
agb : out std_logic; -- High (1) if dataa[] > datab[].
aleb : out std_logic; -- High (1) if dataa[] <= datab[].
aneb : out std_logic; -- High (1) if dataa[] != datab[].
ageb : out std_logic -- High (1) if dataa[] >= datab[].
);
end LPM_COMPARE_UNSIGNED;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_COMPARE_UNSIGNED is
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_pipeline < 0) then
ASSERT FALSE
REPORT "Value of lpm_pipeline parameter must NOT less than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
-- perform the data comparison
process(aclr, clock, dataa, datab)
variable agbtmp : std_logic_vector (0 to lpm_pipeline);
variable agebtmp : std_logic_vector (0 to lpm_pipeline);
variable aebtmp : std_logic_vector (0 to lpm_pipeline);
variable anebtmp : std_logic_vector (0 to lpm_pipeline);
variable albtmp : std_logic_vector (0 to lpm_pipeline);
variable alebtmp : std_logic_vector (0 to lpm_pipeline);
begin
-- get the status of comparation
if (unsigned(dataa) > unsigned(datab)) then
agbtmp(lpm_pipeline) := '1';
agebtmp(lpm_pipeline) := '1';
anebtmp(lpm_pipeline) := '1';
aebtmp(lpm_pipeline) := '0';
albtmp(lpm_pipeline) := '0';
alebtmp(lpm_pipeline) := '0';
elsif (unsigned(dataa) = unsigned(datab)) then
agbtmp(lpm_pipeline) := '0';
agebtmp(lpm_pipeline) := '1';
anebtmp(lpm_pipeline) := '0';
aebtmp(lpm_pipeline) := '1';
albtmp(lpm_pipeline) := '0';
alebtmp(lpm_pipeline) := '1';
else
agbtmp(lpm_pipeline) := '0';
agebtmp(lpm_pipeline) := '0';
anebtmp(lpm_pipeline) := '1';
aebtmp(lpm_pipeline) := '0';
albtmp(lpm_pipeline) := '1';
alebtmp(lpm_pipeline) := '1';
end if;
-- if lpm_pipine > 0, then create latency on the output result
if (aclr = '1') then
if (lpm_pipeline > 0) then
for i in 0 to lpm_pipeline loop
agbtmp(i) := '0';
agebtmp(i) := '0';
anebtmp(i) := '0';
aebtmp(i) := '0';
albtmp(i) := '0';
alebtmp(i) := '0';
end loop;
end if;
elsif (clock'event and (clock = '1')) then
if ((clken = '1') and (lpm_pipeline > 0)) then
agbtmp(0 to lpm_pipeline-1) := agbtmp(1 to lpm_pipeline);
agebtmp(0 to lpm_pipeline-1) := agebtmp(1 to lpm_pipeline) ;
anebtmp(0 to lpm_pipeline-1) := anebtmp(1 to lpm_pipeline);
aebtmp(0 to lpm_pipeline-1) := aebtmp(1 to lpm_pipeline);
albtmp(0 to lpm_pipeline-1) := albtmp(1 to lpm_pipeline);
alebtmp(0 to lpm_pipeline-1) := alebtmp(1 to lpm_pipeline);
end if;
end if;
agb <= agbtmp(0);
ageb <= agebtmp(0);
aneb <= anebtmp(0);
aeb <= aebtmp(0);
alb <= albtmp(0);
aleb <= alebtmp(0);
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_compare
--
-- Description : Parameterized comparator megafunction. The comparator will
-- compare between data[] and datab[] and return the status of
-- comparation for the following operation.
-- 1) dataa[] < datab[].
-- 2) dataa[] == datab[].
-- 3) dataa[] > datab[].
-- 4) dataa[] >= datab[].
-- 5) dataa[] != datab[].
-- 6) dataa[] <= datab[].
--
-- Limitation : n/a
--
-- Results Expected: Return status bits of the comparision between dataa[] and
-- datab[].
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
use work.LPM_COMPARE_SIGNED;
use work.LPM_COMPARE_UNSIGNED;
-- ENTITY DECLARATION
entity LPM_COMPARE is
-- GENERIC DECLARATION
generic (
-- Width of the dataa[] and datab[] ports. (Required)
lpm_width : natural;
-- Type of comparison performed: "SIGNED", "UNSIGNED"
lpm_representation : string := "UNSIGNED";
-- Specifies the number of clock cycles of latency associated with the
-- alb, aeb, agb, ageb, aleb or aneb output.
lpm_pipeline : natural := 0;
lpm_type: string := "LPM_COMPARE";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
-- Value to be compared to datab[]. (Required)
dataa : in std_logic_vector(lpm_width-1 downto 0);
-- Value to be compared to dataa[]. (Required)
datab : in std_logic_vector(lpm_width-1 downto 0);
-- clock for pipelined usage.
clock : in std_logic := '0';
-- Asynchronous clear for pipelined usage.
aclr : in std_logic := '0';
-- clock enable for pipelined usage.
clken : in std_logic := '1';
-- One of the following ports must be present.
alb : out std_logic; -- High (1) if dataa[] < datab[].
aeb : out std_logic; -- High (1) if dataa[] == datab[].
agb : out std_logic; -- High (1) if dataa[] > datab[].
aleb : out std_logic; -- High (1) if dataa[] <= datab[].
aneb : out std_logic; -- High (1) if dataa[] != datab[].
ageb : out std_logic -- High (1) if dataa[] >= datab[].
);
end LPM_COMPARE;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_COMPARE is
-- COMPONENT DECLARATION
component LPM_COMPARE_SIGNED
generic (
lpm_width : natural;
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_COMPARE";
lpm_hint : string := "UNUSED"
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
datab : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic := '0';
aclr : in std_logic := '0';
clken : in std_logic := '1';
alb : out std_logic;
aeb : out std_logic;
agb : out std_logic;
aleb : out std_logic;
aneb : out std_logic;
ageb : out std_logic
);
end component;
component LPM_COMPARE_UNSIGNED
generic (
lpm_width : natural;
lpm_pipeline : natural := 0;
lpm_type : string := "LPM_COMPARE";
lpm_hint : string := "UNUSED"
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
datab : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic := '0';
aclr : in std_logic := '0';
clken : in std_logic := '1';
alb : out std_logic;
aeb : out std_logic;
agb : out std_logic;
aleb : out std_logic;
aneb : out std_logic;
ageb : out std_logic
);
end component;
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if ((lpm_representation /= "UNSIGNED") and (lpm_representation /= "SIGNED")) then
ASSERT FALSE
REPORT "Value of lpm_representation parameter must be SIGNED or UNSIGNED!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
-- instantiate LPM_COMPARE_UNSIGNED to perform "UNSIGNED" data comparison
L1: if lpm_representation = "UNSIGNED" generate
U1: LPM_COMPARE_UNSIGNED
generic map (
lpm_width => lpm_width,
lpm_pipeline => lpm_pipeline,
lpm_type => lpm_type,
lpm_hint => lpm_hint
)
port map (
dataa => dataa,
datab => datab,
clock => clock,
aclr => aclr,
clken => clken,
alb => alb,
aeb => aeb,
agb => agb,
aleb => aleb,
aneb => aneb,
ageb => ageb
);
end generate;
-- instantiate LPM_COMPARE_SIGNED to perform "SIGNED" data comparison
L2: if lpm_representation = "SIGNED" generate
U2: LPM_COMPARE_SIGNED
generic map (
lpm_width => lpm_width,
lpm_pipeline => lpm_pipeline,
lpm_type => lpm_type,
lpm_hint => lpm_hint
)
port map (
dataa => dataa,
datab => datab,
clock => clock,
aclr => aclr,
clken => clken,
alb => alb,
aeb => aeb,
agb => agb,
aleb => aleb,
aneb => aneb,
ageb => ageb
);
end generate;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_mult
--
-- Description : Parameterized multiplier megafunction.
--
-- Limitation : n/a
--
-- results Expected: dataa[] * datab[] + sum[].
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.LPM_COMPONENTS.all;
use work.LPM_HINT_EVALUATION.all;
-- ENTITY DECLARATION
entity LPM_MULT is
-- GENERIC DECLARATION
generic (
lpm_widtha : natural; -- Width of the dataa[] port. (Required)
lpm_widthb : natural; -- Width of the datab[] port. (Required)
lpm_widthp : natural; -- Width of the result[] port. (Required)
lpm_widths : natural := 1; -- Width of the sum[] port. (Required)
lpm_representation : string := "UNSIGNED"; -- Type of multiplication performed
lpm_pipeline : natural := 0; -- Number of clock cycles of latency
lpm_type : string := "LPM_MULT";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
-- Multiplicand. (Required)
dataa : in std_logic_vector(lpm_widtha-1 downto 0);
-- Multiplier. (Required)
datab : in std_logic_vector(lpm_widthb-1 downto 0);
-- Partial sum.
sum : in std_logic_vector(lpm_widths-1 downto 0) := (OTHERS => '0');
-- Asynchronous clear for pipelined usage.
aclr : in std_logic := '0';
-- Clock for pipelined usage.
clock : in std_logic := '0';
-- Clock enable for pipelined usage.
clken : in std_logic := '1';
-- result = dataa[] * datab[] + sum. The product LSB is aligned with the sum LSB.
result : out std_logic_vector(lpm_widthp-1 downto 0)
);
end LPM_MULT;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_MULT is
-- FUNCTION DECLARATION
function str2bin (constant i_str : in string;
constant i_width_str : in natural) return std_logic_vector is
variable binary_bits : std_logic_vector (255 downto 0) := (others => '0');
begin
if(i_str'length > 0) then
for i in 0 to (i_str'right - i_str'left) loop
if (i_str'left >= i) then
case i_str(i_str'right - i) is
when '0' => binary_bits(i) := '0';
when '1' => binary_bits(i) := '1';
when others => binary_bits(i) := 'X';
end case;
end if;
end loop;
end if;
return binary_bits(i_width_str -1 downto 0);
end str2bin;
-- TYPE DECLARATION
type T_RESULTTMP IS ARRAY (0 to lpm_pipeline) of std_logic_vector(lpm_widthp-1 downto 0);
-- CONSTANT DECLARATION
constant INPUT_A_IS_CONSTANT : string := GET_PARAMETER_VALUE(lpm_hint, "INPUT_A_IS_CONSTANT");
constant INPUT_B_IS_CONSTANT : string := GET_PARAMETER_VALUE(lpm_hint, "INPUT_B_IS_CONSTANT");
constant INPUT_A_FIXED_VALUE : string := GET_PARAMETER_VALUE(lpm_hint, "INPUT_A_FIXED_VALUE");
constant INPUT_B_FIXED_VALUE : string := GET_PARAMETER_VALUE(lpm_hint, "INPUT_B_FIXED_VALUE");
constant DATAA_FIXED : std_logic_vector(lpm_widtha-1 downto 0) := str2bin(INPUT_A_FIXED_VALUE, lpm_widtha);
constant DATAB_FIXED : std_logic_vector(lpm_widthb-1 downto 0) := str2bin(INPUT_B_FIXED_VALUE, lpm_widthb);
-- SIGNAL DECLARATION
signal i_dataa : std_logic_vector(lpm_widtha-1 downto 0);
signal i_datab : std_logic_vector(lpm_widthb-1 downto 0);
begin
i_dataa <= dataa when (INPUT_A_IS_CONSTANT /= "FIXED")
else DATAA_FIXED;
i_datab <= datab when (INPUT_B_IS_CONSTANT /= "FIXED")
else DATAB_FIXED;
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_widtha <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widtha parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_widthb <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widthb parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_widthp <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widthp parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_widths <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widths parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process (clock, aclr, i_dataa, i_datab, sum)
variable resulttmp : T_RESULTTMP;
variable tmp_prod_ab : std_logic_vector(lpm_widtha+lpm_widthb downto 0);
variable tmp_prod_s : std_logic_vector(lpm_widths downto 0);
variable tmp_prod_p : std_logic_vector(lpm_widthp-1 downto 0);
variable tmp_use : integer;
begin
if (lpm_representation = "SIGNED") then
tmp_prod_ab(lpm_widtha+lpm_widthb-1 downto 0) := signed(i_dataa) * signed(i_datab);
tmp_prod_ab(lpm_widtha+lpm_widthb) := tmp_prod_ab(lpm_widtha+lpm_widthb-1);
elsif (lpm_representation = "UNSIGNED") then
tmp_prod_ab(lpm_widtha+lpm_widthb-1 downto 0) := unsigned(i_dataa) * unsigned(i_datab);
tmp_prod_ab(lpm_widtha+lpm_widthb) := '0';
else
ASSERT FALSE
REPORT "Illegal lpm_representation property value for LPM_MULT!"
SEVERITY ERROR;
end if;
tmp_use := 1; --AB
if (lpm_widths > (lpm_widtha+lpm_widthb)) then
if (lpm_representation = "SIGNED") then
tmp_prod_s := (OTHERS => tmp_prod_ab(lpm_widtha+lpm_widthb));
tmp_prod_s(lpm_widtha+lpm_widthb downto 0) := tmp_prod_ab;
tmp_prod_s := signed(tmp_prod_s) + signed(sum);
tmp_prod_p := (OTHERS => tmp_prod_s(lpm_widths));
else
tmp_prod_s := (OTHERS => '0');
tmp_prod_s(lpm_widtha+lpm_widthb downto 0) := tmp_prod_ab;
tmp_prod_s := unsigned(tmp_prod_s) + unsigned(sum);
tmp_prod_p := (OTHERS => '0');
end if;
tmp_use := 2; --S
elsif (lpm_widths > 0) then
if (lpm_representation = "SIGNED") then
tmp_prod_ab := signed(tmp_prod_ab) + signed(sum);
tmp_prod_p := (OTHERS => tmp_prod_ab(lpm_widtha+lpm_widthb));
else
tmp_prod_ab := unsigned(tmp_prod_ab) + unsigned(sum);
tmp_prod_p := (OTHERS => '0');
end if;
end if;
if (tmp_use = 2) then --S
if (lpm_widthp > lpm_widths) then
tmp_prod_p(lpm_widths downto 0) := tmp_prod_s;
elsif (lpm_widthp = lpm_widths) then
tmp_prod_p := tmp_prod_s(lpm_widthp-1 downto 0);
else
tmp_prod_p := tmp_prod_s(lpm_widths-1 downto lpm_widths-lpm_widthp);
end if;
else --AB
if (lpm_widthp > (lpm_widtha+lpm_widthb)) then
tmp_prod_p(lpm_widtha+lpm_widthb downto 0) := tmp_prod_ab(lpm_widtha+lpm_widthb downto 0);
elsif (lpm_widthp = lpm_widtha+lpm_widthb) then
tmp_prod_p := tmp_prod_ab(lpm_widthp-1 downto 0);
else
tmp_prod_p := tmp_prod_ab(lpm_widtha+lpm_widthb-1 downto lpm_widtha+lpm_widthb-lpm_widthp);
end if;
end if;
resulttmp(lpm_pipeline) := tmp_prod_p;
-- Pipelining the result of multiplication
if (aclr = '1') then
if (lpm_pipeline > 0) then
for i in 0 to lpm_pipeline loop
resulttmp(i) := (OTHERS => '0');
end loop;
end if;
elsif (clock'event and (clock = '1')) then
if((clken = '1') and (lpm_pipeline > 0) and (now > 0 ns)) then
resulttmp(0 to lpm_pipeline - 1) := resulttmp(1 to lpm_pipeline);
end if;
end if;
result <= resulttmp(0);
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_divide
--
-- Description : Parameterized divider megafunction. This function performs a
-- divide operation such that denom * quotient + remain = numer
-- The function allows for all combinations of signed(two's
-- complement) and unsigned inputs. If any of the inputs is
-- signed, the output is signed. Otherwise the output is unsigned.
-- The function also allows the remainder to be specified as
-- always positive (in which case remain >= 0); otherwise remain
-- is zero or the same sign as the numerator
-- (this parameter is ignored in the case of purely unsigned
-- division). Finally the function is also pipelinable.
--
-- Limitation : n/a
--
-- Results Expected: Return quotient and remainder.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
use work.LPM_HINT_EVALUATION.all;
-- ENTITY DECLARATION
entity LPM_DIVIDE is
generic (
lpm_widthn : natural; -- Width of the numer[] and quotient[] port. (Required)
lpm_widthd : natural; -- Width of the denom[] and remain[] port. (Required)
lpm_nrepresentation : string := "UNSIGNED"; -- The representation of numer
lpm_drepresentation : string := "UNSIGNED"; -- The representation of denom
lpm_pipeline : natural := 0; -- Number of Clock cycles of latency
lpm_type : string := "LPM_DIVIDE";
lpm_hint : string := "LPM_REMAINDERPOSITIVE=TRUE"
);
port (
numer : in std_logic_vector(lpm_widthn-1 downto 0); -- The numerator (Required)
denom : in std_logic_vector(lpm_widthd-1 downto 0); -- The denominator (Required)
clock : in std_logic := '0'; -- Clock input for pipelined usage
aclr : in std_logic := '0'; -- Asynchronous clear signal
clken : in std_logic := '1'; -- Clock enable for pipelined usage
quotient : out std_logic_vector(lpm_widthn-1 downto 0); -- Quotient (Required)
remain : out std_logic_vector(lpm_widthd-1 downto 0) -- Remainder (Required)
);
end LPM_DIVIDE;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture behave of lpm_divide is
-- CONSTANT DECLARATION
constant MAX_WIDTH : integer := 256;
constant LPM_REMAINDERPOSITIVE : string := GET_PARAMETER_VALUE(LPM_HINT, "LPM_REMAINDERPOSITIVE");
-- TYPE DECLARATION
type QPIPELINE is array (0 to lpm_pipeline) of std_logic_vector(lpm_widthn-1 downto 0);
type RPIPELINE is array (0 to lpm_pipeline) of std_logic_vector(lpm_widthd-1 downto 0);
-- SIGNAL DECLARATION
signal quotient_pipe : std_logic_vector (lpm_widthn - 1 downto 0)
:= (others => '0');
signal quotient_value : std_logic_vector (lpm_widthn - 1 downto 0)
:= (others => '0');
signal remainder_pipe : std_logic_vector (lpm_widthd - 1 downto 0)
:= (others => '0');
signal remainder_value : std_logic_vector (lpm_widthd - 1 downto 0)
:= (others => '0');
-- FUNCTION DECLARATION
-- Bitwise left shift
procedure shift_left ( val : inout std_logic_vector; num : in integer) is
variable temp : std_logic_vector((val'length - 1) downto 0);
begin
if num /= 0 then
temp := val;
if (val'length > 1) then
for i in temp'high downto num loop
temp(i) := temp(i- num);
end loop;
for i in num-1 downto 0 loop
temp(i) := '0';
end loop;
end if;
temp(0) :='0';
val := temp;
end if;
end shift_left;
-- Bitwise right shift
procedure shift_right ( val : inout std_logic_vector ) is
variable temp : std_logic_vector(val'length-1 downto 0);
begin
temp := val;
if (val'length > 1) then
for i in 0 to temp'high - 1 loop
temp(i) := temp(i+1);
end loop;
end if;
temp(temp'high) := '0';
val := temp;
end shift_right;
begin
-- SIGNAL ASSIGNMENTS
quotient <= quotient_pipe when (lpm_pipeline > 0) else quotient_value;
remain <= remainder_pipe when (lpm_pipeline > 0) else remainder_value;
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_widthn <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widthn parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_widthd <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widthd parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if ((LPM_REMAINDERPOSITIVE /= "TRUE") and
(LPM_REMAINDERPOSITIVE /= "FALSE")) then
ASSERT FALSE
REPORT " LPM_REMAINDERPOSITIVE value must be TRUE or FALSE!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process (numer, denom)
variable i_denom : std_logic_vector(MAX_WIDTH-1 downto 0) := (OTHERS => '0');
variable i_quotient : std_logic_vector(lpm_widthn-1 downto 0) := (OTHERS => '0');
variable i_remain : std_logic_vector(MAX_WIDTH-1 downto 0) := (OTHERS => '0');
variable sign_numer : std_logic;
variable sign_denom : std_logic;
variable trailing_zero_count : integer;
variable int_numer, int_denom, int_quotient, int_remain : integer := 0;
variable signed_quotient : signed(lpm_widthn-1 downto 0);
variable unsigned_quotient : unsigned(lpm_widthn-1 downto 0);
begin
if ((lpm_widthn < 32) and (lpm_widthd < 32)) then
-- perform division using integer division.
if (lpm_nrepresentation = "UNSIGNED") then
int_numer := conv_integer(unsigned(numer));
elsif (lpm_nrepresentation = "SIGNED") then
int_numer := conv_integer(signed(numer));
else
ASSERT FALSE
REPORT "Illegal lpm_nrepresentation property value for LPM_DIVIDE!"
SEVERITY ERROR;
end if;
if (lpm_drepresentation = "UNSIGNED" ) then
int_denom := conv_integer(unsigned(denom));
elsif (lpm_drepresentation = "SIGNED") then
int_denom := conv_integer(signed(denom));
else
ASSERT FALSE
REPORT "Illegal lpm_drepresentation property value for LPM_DIVIDE!"
SEVERITY ERROR;
end if;
if (int_denom = 0) then
remainder_value <= (OTHERS => 'X');
quotient_value <= (OTHERS => 'X');
else
int_quotient := int_numer / int_denom;
int_remain := int_numer rem int_denom;
-- LPM 220 standard
if ((LPM_REMAINDERPOSITIVE="TRUE") and (int_remain < 0)) then
if (int_denom < 0) then
int_quotient := int_quotient + 1;
else
int_quotient := int_quotient - 1;
end if;
int_remain := int_numer - (int_quotient*int_denom);
end if;
signed_quotient := conv_signed(int_quotient, lpm_widthn);
unsigned_quotient := conv_unsigned(int_quotient, lpm_widthn);
remainder_value <= conv_std_logic_vector(int_remain, lpm_widthd);
if ((lpm_nrepresentation = "UNSIGNED") and (lpm_drepresentation = "UNSIGNED")) then
quotient_value <= conv_std_logic_vector(unsigned_quotient, lpm_widthn);
else
quotient_value <= conv_std_logic_vector(signed_quotient, lpm_widthn);
end if;
end if;
else
-- perform division using long division algorithm
sign_numer := '0';
sign_denom := '0';
trailing_zero_count := 0;
i_quotient := (OTHERS => '0');
i_denom := (OTHERS => '0');
i_remain := (OTHERS => '0');
if (lpm_nrepresentation = "UNSIGNED") then
i_remain(lpm_widthn -1 downto 0) := numer;
elsif (lpm_nrepresentation = "SIGNED") then
if (numer(lpm_widthn-1) = '1') then
i_remain(lpm_widthn -1 downto 0) := not numer + 1;
sign_numer := '1';
else
i_remain(lpm_widthn -1 downto 0) := numer;
end if;
else
ASSERT FALSE
REPORT "Illegal lpm_nrepresentation property value for LPM_DIVIDE!"
SEVERITY ERROR;
end if;
if (lpm_drepresentation = "UNSIGNED" ) then
i_denom(MAX_WIDTH-1 downto MAX_WIDTH-lpm_widthd) := denom;
elsif (lpm_drepresentation = "SIGNED") then
if (denom(lpm_widthd-1) = '1') then
i_denom(MAX_WIDTH-1 downto MAX_WIDTH-lpm_widthd) := not denom + 1;
sign_denom := '1';
else
i_denom(MAX_WIDTH-1 downto MAX_WIDTH-lpm_widthd) := denom;
end if;
else
ASSERT FALSE
REPORT "Illegal lpm_drepresentation property value for LPM_DIVIDE!"
SEVERITY ERROR;
end if;
-- if divide with zero, set quotient to all 'X'
if (i_denom = 0) then
i_quotient := (OTHERS => 'X');
i_remain := (OTHERS => 'X');
elsif (numer = 0) then
i_quotient := (OTHERS => '0');
else
-- get number of zero bits in the denom
for i in 0 to lpm_widthd-1 loop
if (i_denom(MAX_WIDTH-lpm_widthd + i) /= '0') then
trailing_zero_count := i;
exit;
end if;
end loop;
-- shift the i_denom until the first non-zero bit become leftmost bit.
for i in 0 to lpm_widthd-1 loop
if (i_denom(MAX_WIDTH-1-i) /= '0') then
shift_left(i_denom, i);
exit;
end if;
end loop;
-- perform division
if (unsigned(i_remain) >= unsigned(i_denom)) then
i_remain := i_remain - i_denom;
i_quotient(0) := '1';
else
i_quotient(0) := '0';
end if;
while (i_denom(trailing_zero_count) = '0') loop
shift_right(i_denom);
shift_left(i_quotient, 1);
if (unsigned(i_remain) >= unsigned(i_denom)) then
i_remain := i_remain - i_denom;
i_quotient(0) := '1';
else
i_quotient(0) := '0';
end if;
end loop;
-- quotient is negative number if either numer or denom (but not both)
-- is negative number
if ((sign_numer xor sign_denom) = '1') then
i_quotient := not i_quotient + 1;
end if;
-- LPM 220 standard
if ((sign_numer = '1') and (i_remain /= 0)) then
if (LPM_REMAINDERPOSITIVE = "TRUE") then
if (sign_denom = '1') then
i_quotient := i_quotient + 1;
else
i_quotient := i_quotient - 1;
end if;
i_remain := i_denom - i_remain;
else
i_remain := not i_remain + 1;
end if;
end if;
end if;
remainder_value <= i_remain(lpm_widthd -1 downto 0);
quotient_value <= i_quotient;
end if;
end process;
process (aclr, clock)
variable tmp_quotient : QPIPELINE := (OTHERS => (OTHERS => '0'));
variable tmp_remain : RPIPELINE := (OTHERS => (OTHERS => '0'));
begin
if (aclr = '1') then
if (lpm_pipeline > 0) then
-- clear the pipeline
for i in 0 to lpm_pipeline loop
tmp_quotient(i) := (OTHERS => '0');
tmp_remain(i) := (OTHERS => '0');
end loop;
end if;
elsif (clock'event and (clock = '1')) then
if (lpm_pipeline > 0) then
if (clken = '1') then
-- pipeline the result
tmp_remain(lpm_pipeline) := remainder_value;
tmp_quotient(lpm_pipeline) := quotient_value;
tmp_quotient(0 to lpm_pipeline-1) := tmp_quotient(1 to lpm_pipeline);
tmp_remain(0 to lpm_pipeline-1) := tmp_remain(1 to lpm_pipeline);
end if;
end if;
end if;
quotient_pipe <= tmp_quotient(0);
remainder_pipe <= tmp_remain(0);
end process;
end behave;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_abs
--
-- Description : Parameterized absolute value megafunction. This megafunction
-- requires the input data to be signed number.
--
-- Limitation :
--
-- results Expected: Return absolute value of data and the overflow status
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity lpm_abs is
generic (
lpm_width : natural; -- Width of the data[] and result[] ports.
-- MUST be greater than 0 (Required)
lpm_type : string := "LPM_ABS";
lpm_hint : string := "UNUSED"
);
port (
data : in std_logic_vector(lpm_width-1 downto 0); -- (Required)
result : out std_logic_vector(lpm_width-1 downto 0); -- (Required)
overflow : out std_logic
);
end LPM_ABS;
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_ABS is
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
GENERATE_ABS : process(data)
begin
if (data(lpm_width-1) = '1') then
if (lpm_width = 1) then
overflow <= '1';
result <= data;
elsif ((lpm_width > 1) and (data(lpm_width -2 downto 0) = 0)) then
overflow <= '1';
result <= data;
else
result <= 0 - data;
overflow <= '0';
end if;
else
result <= data;
overflow <= '0';
end if;
end process GENERATE_ABS;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_counter
--
-- Description : Parameterized counter megafunction. The lpm_counter
-- megafunction is a binary counter that features an up,
-- down, or up/down counter with optional synchronous or
-- asynchronous clear, set, and load ports.
--
-- Limitation : n/a
--
-- Results Expected: data output from the counter and carry-out of the MSB.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
use work.LPM_COMMON_CONVERSION.all;
-- ENTITY DECLARATION
entity LPM_COUNTER is
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_direction : string := "UNUSED";
lpm_modulus : natural := 0;
lpm_avalue : string := "UNUSED";
lpm_svalue : string := "UNUSED";
lpm_pvalue : string := "UNUSED";
lpm_port_updown : string := "PORT_CONNECTIVITY";
lpm_type : string := "LPM_COUNTER";
lpm_hint : string := "UNUSED"
);
port (
clock : in std_logic;
clk_en : in std_logic := '1';
cnt_en : in std_logic := '1';
updown : in std_logic := '1';
aclr : in std_logic := '0';
aset : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sset : in std_logic := '0';
sload : in std_logic := '0';
data : in std_logic_vector(lpm_width-1 downto 0):= (OTHERS => '0');
cin : in std_logic := '1';
q : out std_logic_vector(lpm_width-1 downto 0);
cout : out std_logic := '0';
eq : out std_logic_vector(15 downto 0) := (OTHERS => '0')
);
end LPM_COUNTER;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_COUNTER is
-- CONSTANT DECLARATION
constant ONES : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '1');
-- FUNCTION DECLARATION
function STR_TO_STD_LOGIC_VECTOR ( str : string ) return std_logic_vector is
variable len : integer := str'length;
variable ivalue : std_logic_vector(lpm_width+5 downto 0) := (others => '0');
variable digit : std_logic_vector(3 downto 0) := (others => '0');
variable ten : std_logic_vector(3 downto 0) := "1010";
begin
if (str /= "UNUSED") then
for i in 1 to len loop
case str(i) is
when '0' =>
digit := "0000";
when '1' =>
digit := "0001";
when '2' =>
digit := "0010";
when '3' =>
digit := "0011";
when '4' =>
digit := "0100";
when '5' =>
digit := "0101";
when '6' =>
digit := "0110";
when '7' =>
digit := "0111";
when '8' =>
digit := "1000";
when '9' =>
digit := "1001";
when others =>
ASSERT FALSE
REPORT "Illegal Character "& str(i) & " in string parameter! "
SEVERITY ERROR;
end case;
ivalue(lpm_width+4 downto 0) := unsigned(ivalue(lpm_width downto 0)) * unsigned(ten) + unsigned(digit);
end loop;
end if;
return ivalue(lpm_width downto 0);
end STR_TO_STD_LOGIC_VECTOR;
-- SIGNAL DECLARATION
signal count : std_logic_vector(lpm_width downto 0);
signal dir : std_logic_vector(1 downto 0);
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_modulus < 0) then
ASSERT FALSE
REPORT "Value of lpm_modulus parameter must be greater or equal to 0!"
SEVERITY ERROR;
end if;
if(lpm_width < 31) then
if (lpm_modulus > 2**lpm_width) then
ASSERT FALSE
REPORT "LPM_MODULUS should be within 1 to 2^LPM_WIDTH. Assuming no modulus input."
SEVERITY WARNING;
end if;
end if;
wait;
end process MSG;
DIRECTION: process (updown)
begin
if (lpm_port_updown = "PORT_USED") then
dir(0) <= updown;
if ((updown = '0') or (updown = '1')) then
dir(1) <= '0'; -- increment or decrement
else
dir(1) <= '1'; -- unknown
end if;
elsif (lpm_port_updown = "PORT_UNUSED") then
if (lpm_direction = "DOWN") then
dir <= "00"; -- decrement
else
dir <= "01"; -- increment
end if;
else
if (lpm_direction = "UP") then
dir <= "01"; -- increment
elsif (lpm_direction = "DOWN") then
dir <= "00"; -- decrement
else
dir(0) <= updown;
if ((updown = '0') or (updown = '1')) then
dir(1) <= '0'; -- increment or decrement
else
if ((lpm_direction = "UNUSED") or (lpm_direction = "DEFAULT")) then
dir <= "01"; -- default to increment
else
dir(1) <= '1'; -- unknown
end if;
end if;
end if;
end if;
end process DIRECTION;
COUNTER: process (clock, aclr, aset, aload, data)
variable imodulus : integer := lpm_modulus;
variable init : boolean := false;
variable avalue : std_logic_vector(lpm_width downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_avalue);
variable svalue : std_logic_vector(lpm_width downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_svalue);
variable pvalue : std_logic_vector(lpm_width downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_pvalue);
begin
if (init = false) then
-- Initialize to pvalue and setup variables
if (lpm_pvalue /= "UNUSED") then
count <= pvalue;
else
count <= (OTHERS => '0');
end if;
if (lpm_width < 31) then -- 32 bit integer limit
if (lpm_modulus > (2 ** lpm_width)) then
imodulus := 2 ** lpm_width ;
else
imodulus := lpm_modulus;
end if;
else
imodulus := lpm_modulus;
end if;
-- Check parameters validity
if ((lpm_direction /= "UNUSED") and (lpm_direction /= "DEFAULT") and
(lpm_direction /= "UP") and (lpm_direction /= "DOWN")) then
ASSERT FALSE
REPORT "Illegal lpm_direction property value for lpm_counter!"
SEVERITY ERROR;
end if;
init := true;
end if;
if (aclr = '1') then
count <= (OTHERS => '0');
elsif (aset = '1') then
if (lpm_avalue = "UNUSED") then
count <= (OTHERS => '1');
else
count <= avalue;
end if;
elsif (aload = '1') then
count(lpm_width-1 downto 0) <= data;
elsif (clock'event and (clock = '1')) then
if (clk_en = '1') then
if (sclr = '1') then
count <= (OTHERS => '0');
elsif (sset = '1') then
if (lpm_svalue = "UNUSED") then
count <= (OTHERS => '1');
else
count <= svalue;
end if;
elsif (sload = '1') then
count(lpm_width-1 downto 0) <= data;
elsif (cnt_en = '1') then
if (imodulus = 1) then
count <= (OTHERS => '0');
elsif (cin = '1') then
if ((dir(0) = '1') and (dir(1) = '0')) then
-- Increase the count
if (((lpm_modulus = 0) and (unsigned(count(lpm_width-1 downto 0)) = unsigned(ONES))) or
((lpm_modulus /= 0) and ((count + 1) = imodulus))) then
count <= conv_std_logic_vector(0, lpm_width+1);
else
count <= count + 1;
end if;
elsif ((dir(0) = '0') and (dir(1) = '0')) then
-- Decrease the count
if (count = 0) then
if (lpm_modulus /= 0) then
count <= conv_std_logic_vector(imodulus-1, lpm_width+1);
else
count <= (OTHERS => '1');
end if;
else
count <= count - 1;
end if;
end if;
end if;
end if;
end if;
end if;
count(lpm_width) <= '0';
end process COUNTER;
CARRYOUT: process (count, cin, dir)
variable imodulus : integer := lpm_modulus;
variable init : boolean := false;
begin
if (init = false) then
if (lpm_width < 31) then -- 32 bit integer limit
if (lpm_modulus > (2 ** lpm_width)) then
imodulus := 2 ** lpm_width ;
else
imodulus := lpm_modulus;
end if;
else
imodulus := lpm_modulus;
end if;
init := true;
end if;
if (dir(1) = '0') then
cout <= '0';
if (imodulus = 1) then
cout <= '1';
elsif (cin = '1') then
if (((dir(0) = '0') and (count = 0)) or
((dir(0) = '1') and (((count = imodulus - 1) and (lpm_modulus /= 0)) or
((lpm_modulus = 0) and
(unsigned(count(lpm_width-1 downto 0)) = unsigned(ONES)))) )) then
cout <= '1';
end if;
end if;
end if;
end process CARRYOUT;
q <= count(lpm_width-1 downto 0);
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_latch
--
-- Description : Parameterized latch megafunction.
--
-- Limitation : n/a
--
-- Results Expected: data output from the latch.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.LPM_COMPONENTS.all;
use work.LPM_COMMON_CONVERSION.all;
-- ENTITY DECLARATION
entity LPM_LATCH is
-- GENERIC DECLARATION
generic (
lpm_width : natural; -- Width of the data[] and q[] ports. (Required)
lpm_avalue : string := "UNUSED"; -- Constant value that is loaded when aset is high.
lpm_pvalue : string := "UNUSED";
lpm_type : string := "LPM_LATCH";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
data : in std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
gate : in std_logic;
aclr : in std_logic := '0';
aset : in std_logic := '0';
aconst : in std_logic := '0';
q : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_LATCH;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_LATCH is
-- FUNCTION DECLARATION
function STR_TO_STD_LOGIC_VECTOR ( str : string ) return std_logic_vector is
variable len : integer := str'length;
variable ivalue : std_logic_vector(lpm_width+4 downto 0) := (others => '0');
variable digit : std_logic_vector(3 downto 0) := (others => '0');
variable ten : std_logic_vector(3 downto 0) := "1010";
begin
if (str /= "UNUSED") then
for i in 1 to len loop
case str(i) is
when '0' =>
digit := "0000";
when '1' =>
digit := "0001";
when '2' =>
digit := "0010";
when '3' =>
digit := "0011";
when '4' =>
digit := "0100";
when '5' =>
digit := "0101";
when '6' =>
digit := "0110";
when '7' =>
digit := "0111";
when '8' =>
digit := "1000";
when '9' =>
digit := "1001";
when others =>
ASSERT FALSE
REPORT "Illegal Character "& str(i) & " in string parameter! "
SEVERITY ERROR;
end case;
ivalue(lpm_width+3 downto 0) := unsigned(ivalue(lpm_width-1 downto 0)) * unsigned(ten) + unsigned(digit);
end loop;
end if;
return ivalue(lpm_width-1 downto 0);
end STR_TO_STD_LOGIC_VECTOR;
-- SIGNAL DECLARATION
signal init : std_logic := '0';
signal tmp_init: std_logic := '0';
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process (tmp_init)
begin
if (tmp_init = '1') then
init <= '1';
end if;
end process;
process (data, gate, aclr, aset, init)
variable avalue : std_logic_vector(lpm_width-1 downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_avalue);
variable pvalue : std_logic_vector(lpm_width-1 downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_pvalue);
begin
if (init = '0') then
if (lpm_pvalue /= "UNUSED") then
-- initialize to pvalue
q <= pvalue;
end if;
tmp_init <= '1';
else
if (aclr = '1') then
q <= (OTHERS => '0');
elsif (aset = '1') then
if (lpm_avalue = "UNUSED") then
q <= (OTHERS => '1');
else
q <= avalue;
end if;
elsif (gate = '1') then
q <= data;
end if;
end if;
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_ff
--
-- Description : Parameterized flipflop megafunction. The lpm_ff function
-- contains features that are not available in the DFF, DFFE,
-- DFFEA, TFF, and TFFE primitives, such as synchronous or
-- asynchronous set, clear, and load inputs.
--
-- Limitation : n/a
--
-- Results Expected: Data output from D or T flipflops.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- BEGINNING OF ENTITY
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.LPM_COMPONENTS.all;
use work.LPM_COMMON_CONVERSION.all;
-- ENTITY DECLARATION
entity LPM_FF is
generic (
-- Width of the data[] and q[] ports. (Required)
lpm_width : natural;
-- Constant value that is loaded when aset is high.
lpm_avalue : string := "UNUSED";
-- Constant value that is loaded on the rising edge of clock when sset is high.
lpm_svalue : string := "UNUSED";
lpm_pvalue : string := "UNUSED";
-- Type of flipflop.
lpm_fftype : string := "DFF";
lpm_type : string := "LPM_FF";
lpm_hint : string := "UNUSED"
);
port (
data : in std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '1');
clock : in std_logic;
enable : in std_logic := '1';
aclr : in std_logic := '0';
aset : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sset : in std_logic := '0';
sload : in std_logic := '0';
q : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_FF;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_FF is
-- FUNCTION DECLARATION
function STR_TO_STD_LOGIC_VECTOR ( str : string ) return std_logic_vector is
variable len : integer := str'length;
variable ivalue : std_logic_vector(lpm_width+4 downto 0) := (others => '0');
variable digit : std_logic_vector(3 downto 0) := (others => '0');
variable ten : std_logic_vector(3 downto 0) := "1010";
begin
if (str /= "UNUSED") then
for i in 1 to len loop
case str(i) is
when '0' =>
digit := "0000";
when '1' =>
digit := "0001";
when '2' =>
digit := "0010";
when '3' =>
digit := "0011";
when '4' =>
digit := "0100";
when '5' =>
digit := "0101";
when '6' =>
digit := "0110";
when '7' =>
digit := "0111";
when '8' =>
digit := "1000";
when '9' =>
digit := "1001";
when others =>
ASSERT FALSE
REPORT "Illegal Character "& str(i) & " in string parameter! "
SEVERITY ERROR;
end case;
ivalue(lpm_width+3 downto 0) := unsigned(ivalue(lpm_width-1 downto 0)) * unsigned(ten) + unsigned(digit);
end loop;
end if;
return ivalue(lpm_width-1 downto 0);
end STR_TO_STD_LOGIC_VECTOR;
-- SIGNAL DECLARATION
signal iq : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
begin
-- PROCESS DECLARATION
process (data, clock, aclr, aset, aload)
variable init : std_logic := '0';
variable avalue : std_logic_vector(lpm_width-1 downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_avalue);
variable svalue : std_logic_vector(lpm_width-1 downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_svalue);
variable pvalue : std_logic_vector(lpm_width-1 downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_pvalue);
begin
-- INITIALIZE TO PVALUE --
if (init = '0') then
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of LPM_WIDTH parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if ((lpm_fftype /= "DFF") and (lpm_fftype /= "TFF")) then
ASSERT FALSE
REPORT "Illegal LPM_FFTYPE property value for LPM_FF!"
SEVERITY ERROR;
end if;
if (lpm_pvalue /= "UNUSED") then
iq <= pvalue;
end if;
init := '1';
end if;
if (aclr = '1') then
iq <= (OTHERS => '0');
elsif (aclr = 'X') then
iq <= (OTHERS => 'X');
elsif (aset = '1') then
if (lpm_avalue = "UNUSED") then
iq <= (OTHERS => '1');
else
iq <= avalue;
end if;
elsif (aload = '1') then
if (lpm_fftype = "TFF") then
iq <= data;
end if;
elsif ((aclr = '0') and (now = 0 ps)) then
if (lpm_pvalue = "UNUSED") then
iq <= (OTHERS => '0');
else
iq <= pvalue;
end if;
elsif (clock'event and (clock = '1') and (NOW > 0 ns)) then
if (enable = '1') then
if (sclr = '1') then
iq <= (OTHERS => '0');
elsif (sset = '1') then
if (lpm_svalue = "UNUSED") then
iq <= (OTHERS => '1');
else
iq <= svalue;
end if;
elsif (sload = '1') then
if (lpm_fftype = "TFF") then
iq <= data;
end if;
else
if (lpm_fftype = "TFF") then
for i in 0 to lpm_width-1 loop
if (data(i) = '1') then
iq(i) <= not iq(i);
end if;
end loop;
else
iq <= data;
end if;
end if;
end if;
end if;
end process;
q <= iq;
end LPM_SYN;
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_shiftreg
--
-- Description : Parameterized shift register megafunction.
--
-- Limitation : n/a
--
-- Results Expected: data output from the shift register and the Serial shift data output.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.LPM_COMPONENTS.all;
use work.LPM_COMMON_CONVERSION.all;
-- ENTITY DECLARATION
entity LPM_SHIFTREG is
generic (
-- Width of the data[] and q ports. (Required)
lpm_width : natural;
lpm_direction : string := "LEFT";
-- Constant value that is loaded when aset is high.
lpm_avalue : string := "UNUSED";
-- Constant value that is loaded on the rising edge of clock when sset is high.
lpm_svalue : string := "UNUSED";
lpm_pvalue : string := "UNUSED";
lpm_type : string := "L_SHIFTREG";
lpm_hint : string := "UNUSED"
);
port (
-- Data input to the shift register.
data : in std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
-- Positive-edge-triggered clock. (Required)
clock : in std_logic;
-- Clock enable input
enable : in std_logic := '1';
-- Serial shift data input.
shiftin : in std_logic := '1';
-- Synchronous parallel load. High (1): load operation; low (0): shift operation.
load : in std_logic := '0';
-- Asynchronous clear input.
aclr : in std_logic := '0';
-- Asynchronous set input.
aset : in std_logic := '0';
-- Synchronous clear input.
sclr : in std_logic := '0';
-- Synchronous set input.
sset : in std_logic := '0';
-- Data output from the shift register.
q : out std_logic_vector(lpm_width-1 downto 0);
-- Serial shift data output.
shiftout : out std_logic
);
end LPM_SHIFTREG;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_SHIFTREG is
-- FUNCTION DECLARATION
function STR_TO_STD_LOGIC_VECTOR ( str : string ) return std_logic_vector is
variable len : integer := str'length;
variable ivalue : std_logic_vector(lpm_width+4 downto 0) := (others => '0');
variable digit : std_logic_vector(3 downto 0) := (others => '0');
variable ten : std_logic_vector(3 downto 0) := "1010";
begin
if (str /= "UNUSED") then
for i in 1 to len loop
case str(i) is
when '0' =>
digit := "0000";
when '1' =>
digit := "0001";
when '2' =>
digit := "0010";
when '3' =>
digit := "0011";
when '4' =>
digit := "0100";
when '5' =>
digit := "0101";
when '6' =>
digit := "0110";
when '7' =>
digit := "0111";
when '8' =>
digit := "1000";
when '9' =>
digit := "1001";
when others =>
ASSERT FALSE
REPORT "Illegal Character "& str(i) & " in string parameter! "
SEVERITY ERROR;
end case;
ivalue(lpm_width+3 downto 0) := unsigned(ivalue(lpm_width-1 downto 0)) * unsigned(ten) + unsigned(digit);
end loop;
end if;
return ivalue(lpm_width-1 downto 0);
end STR_TO_STD_LOGIC_VECTOR;
-- SIGNAL DECLARATION
signal i_q : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
signal init : std_logic := '0';
signal tmp_init : std_logic := '0';
signal i_shiftout_pos : natural := lpm_width-1;
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process (tmp_init)
begin
if (tmp_init = '1') then
init <= '1';
end if;
end process;
process (clock, aclr, aset, init)
variable avalue : std_logic_vector(lpm_width-1 downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_avalue);
variable svalue : std_logic_vector(lpm_width-1 downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_svalue);
variable pvalue : std_logic_vector(lpm_width-1 downto 0) := STR_TO_STD_LOGIC_VECTOR(lpm_pvalue);
begin
-- initIALIZE TO PVALUE --
if (init = '0') then
if (lpm_pvalue /= "UNUSED") then
i_q <= pvalue;
end if;
if ((lpm_direction = "LEFT") or (lpm_direction = "UNUSED")) then
i_shiftout_pos <= lpm_width-1;
elsif (lpm_direction = "RIGHT") then
i_shiftout_pos <= 0;
else
ASSERT FALSE
REPORT "Illegal lpm_direction property value for LPM_SHIFTREG!"
SEVERITY ERROR;
end if;
tmp_init <= '1';
elsif (aclr = '1') then
i_q <= (OTHERS => '0');
elsif (aset = '1') then
if (lpm_avalue = "UNUSED") then
i_q <= (OTHERS => '1');
else
i_q <= avalue;
end if;
elsif (rising_edge(clock)) then
if (enable = '1') then
if (sclr = '1') then
i_q <= (OTHERS => '0');
elsif (sset = '1') then
if (lpm_svalue = "UNUSED") then
i_q <= (OTHERS => '1');
else
i_q <= svalue;
end if;
elsif (load = '1') then
i_q <= data;
else
if (lpm_width < 2) then
i_q(0) <= shiftin;
elsif (lpm_direction = "LEFT") then
i_q <= (i_q(lpm_width-2 downto 0) & shiftin);
else
i_q <= (shiftin & i_q(lpm_width-1 downto 1));
end if;
end if;
end if;
end if;
end process;
q <= i_q;
shiftout <= i_q(i_shiftout_pos);
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_ram_dq
--
-- Description : Parameterized RAM with separate input and output ports megafunction.
-- lpm_ram_dp implement asynchronous memory or memory with synchronous
-- inputs and/or outputs.
--
-- Limitation : n/a
--
-- Results Expected: data output from the memory.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
use work.LPM_COMMON_CONVERSION.all;
use work.LPM_DEVICE_FAMILIES.all;
use std.textio.all;
-- ENTITY DECLARATION
entity LPM_RAM_DQ is
generic (
-- Width of data[] and q[] ports. (Required)
lpm_width : natural;
-- Width of the address port. (Required)
lpm_widthad : natural;
-- Number of words stored in memory.
lpm_numwords : natural := 0;
-- Controls whether the data port is registered.
lpm_indata : string := "REGISTERED";
-- Controls whether the address and we ports are registered.
lpm_address_control: string := "REGISTERED";
-- Controls whether the q ports are registered.
lpm_outdata : string := "REGISTERED";
-- Name of the file containing RAM initialization data.
lpm_file : string := "UNUSED";
-- Specified whether to use the EAB or not.
use_eab : string := "ON";
intended_device_family : string := "UNUSED";
lpm_type : string := L_RAM_DQ;
lpm_hint : string := "UNUSED"
);
port (
-- Data input to the memory. (Required)
data : in std_logic_vector(lpm_width-1 downto 0);
-- Address input to the memory. (Required)
address : in std_logic_vector(lpm_widthad-1 downto 0);
-- Synchronizes memory loading.
inclock : in std_logic := '0';
-- Synchronizes q outputs from memory.
outclock : in std_logic := '0';
-- Write enable input. Enables write operations to the memory when high. (Required)
we : in std_logic;
-- Data output from the memory. (Required)
q : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_RAM_DQ;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of lpm_ram_dq is
-- TYPE DECLARATION
type LPM_MEMORY is array((2**lpm_widthad)-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
-- SIGNAL DECLARATION
signal data_tmp : std_logic_vector(lpm_width-1 downto 0);
signal data_reg : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal q_tmp : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal q_reg : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal address_tmp : std_logic_vector(lpm_widthad-1 downto 0);
signal address_reg : std_logic_vector(lpm_widthad-1 downto 0) := (others => '0');
signal we_tmp : std_logic;
signal we_reg : std_logic := '0';
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_widthad <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widthad parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (IS_VALID_FAMILY(intended_device_family) = false) then
ASSERT FALSE
REPORT "Unknown intended_device_family " & intended_device_family
SEVERITY ERROR;
end if;
wait;
end process MSG;
SYNC: process( data, data_reg, address, address_reg,
we, we_reg, q_tmp, q_reg)
begin
if (lpm_address_control = "REGISTERED") then
address_tmp <= address_reg;
we_tmp <= we_reg;
elsif (lpm_address_control = "UNREGISTERED") then
address_tmp <= address;
we_tmp <= we;
else
ASSERT FALSE
REPORT "Illegal lpm_address_control property value for LPM_RAM_DQ!"
SEVERITY ERROR;
end if;
if (lpm_indata = "REGISTERED") then
data_tmp <= data_reg;
elsif (lpm_indata = "UNREGISTERED") then
data_tmp <= data;
else
ASSERT FALSE
REPORT "Illegal lpm_indata property value for LPM_RAM_DQ!"
SEVERITY ERROR;
end if;
if (lpm_outdata = "REGISTERED") then
q <= q_reg;
elsif (lpm_outdata = "UNREGISTERED") then
q <= q_tmp;
else
ASSERT FALSE
REPORT "Illegal lpm_outdata property value for LPM_RAM_DQ!"
SEVERITY ERROR;
end if;
end process SYNC;
INPUT_REG: process (inclock)
begin
if (inclock'event and (inclock = '1')) then
data_reg <= data;
address_reg <= address;
we_reg <= we;
end if;
end process INPUT_REG;
OUTPUT_REG: process (outclock)
begin
if (outclock'event and (outclock = '1')) then
q_reg <= q_tmp;
end if;
end process OUTPUT_REG;
MEMORY: process(data_tmp, we_tmp, address_tmp, inclock)
variable mem_data : LPM_MEMORY;
variable mem_data_word : std_logic_vector(lpm_width-1 downto 0);
variable mem_init: boolean := false;
variable i, j, k, n, m, lineno: integer := 0;
variable buf: line ;
variable booval: boolean ;
FILE mem_data_file: TEXT IS IN lpm_file;
variable char : string(1 downto 1) := " ";
variable base, byte, rec_type, datain, addr, checksum: string(2 downto 1);
variable startadd: string(4 downto 1);
variable ibase: integer := 0;
variable ibyte: integer := 0;
variable istartadd: integer := 0;
variable check_sum_vec, check_sum_vec_tmp: std_logic_vector(7 downto 0);
variable m_string : string(1 to 15);
variable m_data_radix : string(1 to 3);
variable m_address_radix : string(1 to 3);
variable m_width : integer;
variable m_depth : integer;
variable m_start_address_int : integer := 0;
variable m_end_address_int : integer := 0;
variable m_address_int : integer := 0;
variable m_data_int : std_logic_vector(lpm_width+4 downto 0) := (OTHERS => '0');
variable found_keyword_content : boolean := false;
variable get_memory_content : boolean := false;
variable get_start_Address : boolean := false;
variable get_end_Address : boolean := false;
begin
-- Initialize
if not (mem_init) then
-- Initialize to 0
for i in mem_data'LOW to mem_data'HIGH loop
mem_data(i) := (OTHERS => '0');
end loop;
if (lpm_file /= "UNUSED") then
if (ALPHA_TOLOWER(lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) = ".hex") then
while not ENDFILE(mem_data_file) loop
booval := true;
READLINE(mem_data_file, buf);
lineno := lineno + 1;
check_sum_vec := (OTHERS => '0');
if (buf(buf'low) = ':') then
i := 1;
SHRINK_LINE(buf, i);
READ(L=>buf, VALUE=>byte, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format!"
SEVERITY ERROR;
end if;
ibyte := HEX_STR_TO_INT(byte);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(ibyte, 8));
READ(L=>buf, VALUE=>startadd, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
istartadd := HEX_STR_TO_INT(startadd);
addr(2) := startadd(4);
addr(1) := startadd(3);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8));
addr(2) := startadd(2);
addr(1) := startadd(1);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8));
READ(L=>buf, VALUE=>rec_type, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(rec_type), 8));
else
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
case rec_type is
when "00"=> -- data record
i := 0;
k := lpm_width / 8;
if ((lpm_width mod 8) /= 0) then
k := k + 1;
end if;
-- k = no. of bytes per CAM entry.
while (i < ibyte) loop
mem_data_word := (others => '0');
n := (k - 1)*8;
m := lpm_width - 1;
for j in 1 to k loop
READ(L=>buf, VALUE=>datain,good=>booval); -- read in data a byte (2 hex chars) at a time.
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), 8));
mem_data_word(m downto n) := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), m-n+1);
m := n - 1;
n := n - 8;
end loop;
i := i + k;
mem_data(ibase + istartadd) := mem_data_word;
istartadd := istartadd + 1;
end loop;
when "01"=>
exit;
when "02"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format for record type 02! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := (ibase * 256) + HEX_STR_TO_INT(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
ibase := ibase * 16;
when "03"=>
if (ibyte /= 4) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 03! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
when "04"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 04! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := (ibase * 256) + HEX_STR_TO_INT(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
ibase := ibase * 65536;
when "05"=>
if (ibyte /= 4) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 05! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
when OTHERS =>
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal record type in Intel Hex File! "
SEVERITY ERROR;
end case;
READ(L=>buf, VALUE=>checksum,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Checksum is missing! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(not (check_sum_vec)) + 1 ;
check_sum_vec_tmp := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(checksum),8);
if (unsigned(check_sum_vec) /= unsigned(check_sum_vec_tmp)) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Incorrect checksum!"
SEVERITY ERROR;
end if;
end loop;
elsif (ALPHA_TOLOWER(lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) = ".mif") then
-- ************************************************
-- Read in RAM initialization file (mif)
-- ************************************************
while not endfile(mem_data_file) loop
booval := true;
readline(mem_data_file, buf);
lineno := lineno + 1;
LOOP2 : while (buf'length > 0) loop
if (buf(buf'low) = '-') then
if (buf(buf'low) = '-') then
-- ignore comment started with --.
exit LOOP2;
end if;
elsif (buf(buf'low) = '%') then
i := 1;
-- ignore comment which begin with % and end with another %.
while ((i < buf'high) and (buf(buf'low + i) /= '%')) loop
i := i+1;
end loop;
if (i >= buf'high) then
exit LOOP2;
else
SHRINK_LINE(buf, i+1);
end if;
elsif ((buf(buf'low) = ' ') or (buf(buf'low) = HT)) then
i := 1;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i >= buf'high) then
exit LOOP2;
else
SHRINK_LINE(buf, i);
end if;
elsif (get_memory_content = true) then
if (((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "end") or
((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "END") or
((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "End")) then
get_memory_content := false;
exit LOOP2;
else
get_start_address := false;
get_end_address := false;
m_start_address_int := 0;
m_end_address_int := 0;
m_address_int := 0;
m_data_int := (others => '0');
if (buf(buf'low) = '[') then
get_start_Address := true;
SHRINK_LINE(buf, 1);
end if;
case m_address_radix is
when "hex" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *16 + HEX_STR_TO_INT(char);
end loop;
when "bin" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *2 + BIN_STR_TO_INT(char);
end loop;
when "dec" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "uns" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "oct" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *8 + OCT_STR_TO_INT(char);
end loop;
when others =>
assert false
report "Unsupported address_radix!"
severity error;
end case;
if (get_start_Address = true) then
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
if ((buf(buf'low) = '.') and (buf(buf'low+1) = '.')) then
get_start_Address := false;
get_end_Address := true;
m_start_address_int := m_address_int;
SHRINK_LINE(buf, 2);
end if;
end if;
if (get_end_address = true) then
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
m_address_int := 0;
case m_address_radix is
when "hex" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *16 + HEX_STR_TO_INT(char);
end loop;
when "bin" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *2 + BIN_STR_TO_INT(char);
end loop;
when "dec" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "uns" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "oct" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *8 + OCT_STR_TO_INT(char);
end loop;
when others =>
assert false
report "Unsupported address_radix!"
severity error;
end case;
if (buf(buf'low) = ']') then
get_end_address := false;
m_end_address_int := m_address_int;
SHRINK_LINE(buf, 1);
end if;
end if;
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
if (buf(buf'low) = ':') then
SHRINK_LINE(buf, 1);
end if;
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
case m_data_radix is
when "hex" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+4 downto 0) := m_data_int(lpm_width-1 downto 0) * "10000" + conv_std_logic_vector(HEX_STR_TO_INT(char), 4);
end loop;
when "bin" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+1 downto 0) := m_data_int(lpm_width-1 downto 0) * "10" + conv_std_logic_vector(BIN_STR_TO_INT(char), 4);
end loop;
when "dec" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4);
end loop;
when "uns" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4);
end loop;
when "oct" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1000" + conv_std_logic_vector(OCT_STR_TO_INT(char), 4);
end loop;
when others =>
assert false
report "Unsupported data_radix!"
severity error;
end case;
if (m_start_address_int /= m_end_address_int) then
for i in m_start_address_int to m_end_address_int loop
mem_data(i) := m_data_int(lpm_width-1 downto 0);
end loop;
else
mem_data(m_address_int) := m_data_int(lpm_width-1 downto 0);
end if;
exit LOOP2;
end if;
elsif ((buf(buf'low) = 'W') or (buf(buf'low) = 'w')) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "width") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to i));
m_width := INT_STR_TO_INT(m_string(1 to i));
end if;
exit LOOP2;
elsif (((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) and
((buf(buf'low+1) = 'E') or (buf(buf'low+1) = 'e'))) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "depth") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to i));
m_depth := INT_STR_TO_INT(m_string(1 to i));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) then
read(l=>buf, value=>m_string(1 to 10));
if (ALPHA_TOLOWER(m_string(1 to 10)) = "data_radix") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to 3));
m_data_radix := ALPHA_TOLOWER(m_string(1 to 3));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'A') or (buf(buf'low) = 'a')) then
read(l=>buf, value=>m_string(1 to 13));
if (ALPHA_TOLOWER(m_string(1 to 13)) = "address_radix") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to 3));
m_address_radix := ALPHA_TOLOWER(m_string(1 to 3));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'C') or (buf(buf'low) = 'c')) then
read(l=>buf, value=>m_string(1 to 7));
if (ALPHA_TOLOWER(m_string(1 to 7)) = "content") then
found_keyword_content := true;
end if;
elsif ((buf(buf'low) = 'B') or (buf(buf'low) = 'b')) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "begin") then
if (found_keyword_content = true) then
get_memory_content := true;
end if;
end if;
end if;
end loop;
end loop;
else
assert false
report "Unsupported memory initialization file type (" & (lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) & ")!"
severity error;
end if;
end if;
mem_init := TRUE;
end if;
-- MEMORY FUNCTION --
if (we_tmp = '1') then
if (((use_eab = "ON") or
(lpm_hint = "use_eab=ON")) and (lpm_address_control = "REGISTERED")) then
if (inclock = '0') then
mem_data (conv_integer(address_tmp)) := data_tmp ;
end if;
else
mem_data (conv_integer(address_tmp)) := data_tmp;
end if;
end if;
q_tmp <= mem_data(conv_integer(address_tmp));
end process MEMORY;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_ram_dp
--
-- Description : Parameterized dual-port RAM megafunction.
--
-- Limitation : n/a
--
-- Results Expected: Data output from the memory.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
use work.LPM_DEVICE_FAMILIES.all;
use work.LPM_COMMON_CONVERSION.all;
use std.textio.all;
-- ENTITY DECLARATION
entity LPM_RAM_DP is
generic (
-- Width of the data[] and q[] ports. (Required)
lpm_width : natural;
-- Width of the rdaddress[] and wraddress[] ports. (Required)
lpm_widthad : natural;
-- Number of words stored in memory.
lpm_numwords : natural := 0;
-- Determines the clock used by the data port.
lpm_indata : string := "REGISTERED";
-- Determines the clock used by the rdaddress and rden ports.
lpm_rdaddress_control : string := "REGISTERED";
-- Determines the clock used by the wraddress and wren ports.
lpm_wraddress_control : string := "REGISTERED";
-- Determines the clock used by the q[] port.
lpm_outdata : string := "REGISTERED";
-- Name of the file containing RAM initialization data.
lpm_file : string := "UNUSED";
-- Specified whether to use the EAB or not.
use_eab : string := "ON";
-- Specified whether to use the rden port or not.
rden_used : string := "TRUE";
intended_device_family : string := "UNUSED";
lpm_type : string := "LPM_RAM_DP";
lpm_hint : string := "UNUSED"
);
port (
-- Data input to the memory. (Required)
data : in std_logic_vector(lpm_width-1 downto 0);
-- Read address input to the memory. (Required)
rdaddress : in std_logic_vector(lpm_widthad-1 downto 0);
-- Write address input to the memory. (Required)
wraddress : in std_logic_vector(lpm_widthad-1 downto 0);
-- Positive-edge-triggered clock for read operation.
rdclock : in std_logic := '0';
-- Clock enable for rdclock.
rdclken : in std_logic := '1';
-- Positive-edge-triggered clock for write operation.
wrclock : in std_logic := '0';
-- Clock enable for wrclock.
wrclken : in std_logic := '1';
-- Read enable input. Disables reading when low (0).
rden : in std_logic := '1';
-- Write enable input. (Required)
wren : in std_logic;
-- Data output from the memory. (Required)
q : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_RAM_DP;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_RAM_DP is
-- TYPE DECLARATION
type LPM_MEMORY is array((2**lpm_widthad)-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
-- SIGNAL DECLARATION
signal data_tmp : std_logic_vector(lpm_width-1 downto 0);
signal data_reg : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal q_reg : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal q_tmp : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal rdaddress_tmp : std_logic_vector(lpm_widthad-1 downto 0);
signal rdaddress_reg : std_logic_vector(lpm_widthad-1 downto 0) := (others => '0');
signal wraddress_tmp : std_logic_vector(lpm_widthad-1 downto 0);
signal wraddress_reg : std_logic_vector(lpm_widthad-1 downto 0) := (others => '0');
signal wren_tmp : std_logic;
signal wren_reg : std_logic := '0';
signal rden_tmp : std_logic;
signal rden_reg : std_logic := '0';
begin
-- SIGNAL ASSIGNMENTS
rden_tmp <= '1' when (rden_used = "FALSE")
else rden when (lpm_rdaddress_control = "UNREGISTERED")
else rden_reg;
rdaddress_tmp <= rdaddress when (lpm_rdaddress_control = "UNREGISTERED")
else rdaddress_reg;
wren_tmp <= wren when (lpm_wraddress_control = "UNREGISTERED")
else wren_reg;
wraddress_tmp <= wraddress when (lpm_wraddress_control = "UNREGISTERED")
else wraddress_reg;
data_tmp <= data when (lpm_indata = "UNREGISTERED")
else data_reg;
q <= q_tmp when (lpm_outdata = "UNREGISTERED")
else q_reg;
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_widthad <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widthad parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if ((lpm_indata /= "REGISTERED") and (lpm_indata /= "UNREGISTERED")) then
ASSERT FALSE
REPORT "Value lpm_indata must be 'REGISTERED' or 'UNREGISTERED'!"
SEVERITY ERROR;
end if;
if ((lpm_outdata /= "REGISTERED") and (lpm_outdata /= "UNREGISTERED")) then
ASSERT FALSE
REPORT "Value of lpm_outdata parameter must be 'REGISTERED' or 'UNREGISTERED'!"
SEVERITY ERROR;
end if;
if ((lpm_wraddress_control /= "REGISTERED") and
(lpm_wraddress_control /= "UNREGISTERED")) then
ASSERT FALSE
REPORT "Value of lpm_wraddress_control parameter must be 'REGISTERED' or 'UNREGISTERED'!"
SEVERITY ERROR;
end if;
if ((lpm_rdaddress_control /= "REGISTERED") and
(lpm_rdaddress_control /= "UNREGISTERED")) then
ASSERT FALSE
REPORT "Value of lpm_rdaddress_control parameter must be 'REGISTERED' or 'UNREGISTERED'!"
SEVERITY ERROR;
end if;
if (IS_VALID_FAMILY(intended_device_family) = false) then
ASSERT FALSE
REPORT "Unknown INTENDED_DEVICE_FAMILY " & intended_device_family
SEVERITY ERROR;
end if;
wait;
end process MSG;
INPUT_REG: process (wrclock)
begin
if (wrclock'event and (wrclock = '1')) then
if (wrclken = '1') then
data_reg <= data;
wraddress_reg <= wraddress;
wren_reg <= wren;
end if;
end if;
end process INPUT_REG;
OUTPUT_REG: process (rdclock)
begin
if (rdclock'event and (rdclock = '1')) then
if (rdclken = '1') then
rdaddress_reg <= rdaddress;
rden_reg <= rden;
q_reg <= q_tmp;
end if;
end if;
end process OUTPUT_REG;
MEMORY: process(data_tmp, wren_tmp, rdaddress_tmp, wraddress_tmp, rden_tmp, wrclock)
variable mem_data : LPM_MEMORY;
variable mem_data_word : std_logic_vector(lpm_width-1 downto 0);
variable mem_init: boolean := false;
variable i, j, k, n, m, lineno : integer := 0;
variable buf: line ;
variable booval: boolean ;
FILE mem_data_file: TEXT IS IN lpm_file;
variable char : string(1 downto 1) := " ";
variable base, byte, rec_type, datain, addr, checksum : string(2 downto 1) := " ";
variable startadd : string(4 downto 1) := " ";
variable ibase : integer := 0;
variable ibyte : integer := 0;
variable istartadd : integer := 0;
variable check_sum_vec, check_sum_vec_tmp : std_logic_vector(7 downto 0);
variable m_string : string(1 to 15);
variable m_data_radix : string(1 to 3);
variable m_address_radix : string(1 to 3);
variable m_width : integer;
variable m_depth : integer;
variable m_start_address_int : integer := 0;
variable m_end_address_int : integer := 0;
variable m_address_int : integer := 0;
variable m_data_int : std_logic_vector(lpm_width+4 downto 0) := (OTHERS => '0');
variable found_keyword_content : boolean := false;
variable get_memory_content : boolean := false;
variable get_start_Address : boolean := false;
variable get_end_Address : boolean := false;
begin
-- Initialize
if NOT(mem_init) then
-- Initialize to 0
for i in mem_data'LOW to mem_data'HIGH loop
mem_data(i) := (OTHERS => '0');
end loop;
if ((use_eab = "ON") or (lpm_hint = "use_eab=ON")) then
q_tmp <= (others => '1');
end if;
if (lpm_file /= "UNUSED") then
if (ALPHA_TOLOWER(lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) = ".hex") then
while not ENDFILE(mem_data_file) loop
booval := true;
READLINE(mem_data_file, buf);
lineno := lineno + 1;
check_sum_vec := (OTHERS => '0');
if (buf(buf'LOW) = ':') then
i := 1;
SHRINK_LINE(buf, i);
READ(L=>buf, VALUE=>byte, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format!"
SEVERITY ERROR;
end if;
ibyte := HEX_STR_TO_INT(byte);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(ibyte, 8));
READ(L=>buf, VALUE=>startadd, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
istartadd := HEX_STR_TO_INT(startadd);
addr(2) := startadd(4);
addr(1) := startadd(3);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8));
addr(2) := startadd(2);
addr(1) := startadd(1);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8));
READ(L=>buf, VALUE=>rec_type, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(rec_type), 8));
else
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
case rec_type is
when "00" => -- data record
i := 0;
k := lpm_width / 8;
if ((lpm_width mod 8) /= 0) then
k := k + 1;
end if;
-- k = no. of bytes per CAM entry.
while (i < ibyte) loop
mem_data_word := (others => '0');
n := (k - 1)*8;
m := lpm_width - 1;
for j in 1 to k loop
-- read in data a byte (2 hex chars) at a time.
READ(L=>buf, VALUE=>datain,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), 8));
mem_data_word(m downto n) := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), m-n+1);
m := n - 1;
n := n - 8;
end loop;
i := i + k;
mem_data(ibase + istartadd) := mem_data_word;
istartadd := istartadd + 1;
end loop;
when "01"=>
exit;
when "02"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format for record type 02! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := ibase * 256 + HEX_STR_TO_INT(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
ibase := ibase * 16;
when "03"=>
if (ibyte /= 4) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 03! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
when "04"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 04! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := (ibase * 256) + HEX_STR_TO_INT(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
ibase := ibase * 65536;
when "05"=>
if (ibyte /= 4) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 05! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
when OTHERS =>
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal record type in Intel Hex File! "
SEVERITY ERROR;
end case;
READ(L=>buf, VALUE=>checksum,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Checksum is missing! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(not (check_sum_vec)) + 1 ;
check_sum_vec_tmp := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(checksum),8);
if (unsigned(check_sum_vec) /= unsigned(check_sum_vec_tmp)) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Incorrect checksum!"
SEVERITY ERROR;
end if;
end loop;
elsif (ALPHA_TOLOWER(lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) = ".mif") then
-- ************************************************
-- Read in RAM initialization file (mif)
-- ************************************************
while not endfile(mem_data_file) loop
booval := true;
readline(mem_data_file, buf);
lineno := lineno + 1;
LOOP2 : while (buf'length > 0) loop
if (buf(buf'low) = '-') then
if (buf(buf'low) = '-') then
-- ignore comment started with --.
exit LOOP2;
end if;
elsif (buf(buf'low) = '%') then
i := 1;
-- ignore comment which begin with % and end with another %.
while ((i < buf'high) and (buf(buf'low + i) /= '%')) loop
i := i+1;
end loop;
if (i >= buf'high) then
exit LOOP2;
else
SHRINK_LINE(buf, i+1);
end if;
elsif ((buf(buf'low) = ' ') or (buf(buf'low) = HT)) then
i := 1;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i >= buf'high) then
exit LOOP2;
else
SHRINK_LINE(buf, i);
end if;
elsif (get_memory_content = true) then
if (((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "end") or
((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "END") or
((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "End")) then
get_memory_content := false;
exit LOOP2;
else
get_start_address := false;
get_end_address := false;
m_start_address_int := 0;
m_end_address_int := 0;
m_address_int := 0;
m_data_int := (others => '0');
if (buf(buf'low) = '[') then
get_start_Address := true;
SHRINK_LINE(buf, 1);
end if;
case m_address_radix is
when "hex" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *16 + HEX_STR_TO_INT(char);
end loop;
when "bin" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *2 + BIN_STR_TO_INT(char);
end loop;
when "dec" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "uns" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "oct" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *8 + OCT_STR_TO_INT(char);
end loop;
when others =>
assert false
report "Unsupported address_radix!"
severity error;
end case;
if (get_start_Address = true) then
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
if ((buf(buf'low) = '.') and (buf(buf'low+1) = '.')) then
get_start_Address := false;
get_end_Address := true;
m_start_address_int := m_address_int;
SHRINK_LINE(buf, 2);
end if;
end if;
if (get_end_address = true) then
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
m_address_int := 0;
case m_address_radix is
when "hex" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *16 + HEX_STR_TO_INT(char);
end loop;
when "bin" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *2 + BIN_STR_TO_INT(char);
end loop;
when "dec" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "uns" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "oct" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *8 + OCT_STR_TO_INT(char);
end loop;
when others =>
assert false
report "Unsupported address_radix!"
severity error;
end case;
if (buf(buf'low) = ']') then
get_end_address := false;
m_end_address_int := m_address_int;
SHRINK_LINE(buf, 1);
end if;
end if;
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
if (buf(buf'low) = ':') then
SHRINK_LINE(buf, 1);
end if;
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
case m_data_radix is
when "hex" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+4 downto 0) := m_data_int(lpm_width-1 downto 0) * "10000" + conv_std_logic_vector(HEX_STR_TO_INT(char), 4);
end loop;
when "bin" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+1 downto 0) := m_data_int(lpm_width-1 downto 0) * "10" + conv_std_logic_vector(BIN_STR_TO_INT(char), 4);
end loop;
when "dec" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4);
end loop;
when "uns" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4);
end loop;
when "oct" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1000" + conv_std_logic_vector(OCT_STR_TO_INT(char), 4);
end loop;
when others =>
assert false
report "Unsupported data_radix!"
severity error;
end case;
if (m_start_address_int /= m_end_address_int) then
for i in m_start_address_int to m_end_address_int loop
mem_data(i) := m_data_int(lpm_width-1 downto 0);
end loop;
else
mem_data(m_address_int) := m_data_int(lpm_width-1 downto 0);
end if;
exit LOOP2;
end if;
elsif ((buf(buf'low) = 'W') or (buf(buf'low) = 'w')) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "width") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to i));
m_width := INT_STR_TO_INT(m_string(1 to i));
end if;
exit LOOP2;
elsif (((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) and
((buf(buf'low+1) = 'E') or (buf(buf'low+1) = 'e'))) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "depth") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to i));
m_depth := INT_STR_TO_INT(m_string(1 to i));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) then
read(l=>buf, value=>m_string(1 to 10));
if (ALPHA_TOLOWER(m_string(1 to 10)) = "data_radix") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to 3));
m_data_radix := ALPHA_TOLOWER(m_string(1 to 3));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'A') or (buf(buf'low) = 'a')) then
read(l=>buf, value=>m_string(1 to 13));
if (ALPHA_TOLOWER(m_string(1 to 13)) = "address_radix") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to 3));
m_address_radix := ALPHA_TOLOWER(m_string(1 to 3));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'C') or (buf(buf'low) = 'c')) then
read(l=>buf, value=>m_string(1 to 7));
if (ALPHA_TOLOWER(m_string(1 to 7)) = "content") then
found_keyword_content := true;
end if;
elsif ((buf(buf'low) = 'B') or (buf(buf'low) = 'b')) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "begin") then
if (found_keyword_content = true) then
get_memory_content := true;
end if;
end if;
end if;
end loop;
end loop;
else
assert false
report "Unsupported memory initialization file type (" & (lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) & ")!"
severity error;
end if;
end if;
mem_init := TRUE;
end if;
-- MEMORY FUNCTION --
if (wren_tmp = '1') then
if (((use_eab = "ON") or (lpm_hint = "use_eab=ON")) and
(lpm_wraddress_control = "REGISTERED")) then
if (wrclock = '0') then
mem_data (conv_integer(wraddress_tmp)) := data_tmp;
end if;
else
mem_data (conv_integer(wraddress_tmp)) := data_tmp ;
end if;
end if;
if ((rden_tmp = '1') or (rden_used = "FALSE")) then
q_tmp <= mem_data(conv_integer(rdaddress_tmp));
end if;
end process MEMORY;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_ram_io
--
-- Description :
--
-- Limitation :
--
-- Results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
use work.LPM_COMMON_CONVERSION.all;
use std.textio.all;
entity LPM_RAM_IO is
generic ( LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_IO";
USE_EAB : string := "ON";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
port ( ADDRESS : in STD_LOGIC_VECTOR(LPM_WIDTHAD-1 downto 0);
INCLOCK : in STD_LOGIC := '0';
OUTCLOCK : in STD_LOGIC := '0';
MEMENAB : in STD_LOGIC := '1';
OUTENAB : in STD_LOGIC := 'Z';
WE : in STD_LOGIC := 'Z';
DIO : inout STD_LOGIC_VECTOR(LPM_WIDTH-1 downto 0));
end LPM_RAM_IO;
architecture LPM_SYN of lpm_ram_io is
--type lpm_memory is array(lpm_numwords-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
type lpm_memory is array((2**lpm_widthad)-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
signal data_tmp, di, do : std_logic_vector(lpm_width-1 downto 0);
signal data_reg : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal q_tmp, q : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal q_reg : std_logic_vector(lpm_width-1 downto 0) := (others => '0');
signal address_tmp : std_logic_vector(lpm_widthad-1 downto 0);
signal address_reg : std_logic_vector(lpm_widthad-1 downto 0) := (others => '0');
signal we_tmp : std_logic;
signal we_reg : std_logic := '0';
signal memenab_tmp : std_logic;
signal memenab_reg : std_logic := '0';
signal outenab_used : std_logic;
-- provided for MP2 compliance
signal we_used : std_logic;
begin
sync: process( di, data_reg, address, address_reg, memenab, memenab_reg,
we,we_reg, q_tmp, q_reg)
begin
if (lpm_address_control = "REGISTERED") then
address_tmp <= address_reg;
we_tmp <= we_reg;
memenab_tmp <= memenab_reg;
elsif (lpm_address_control = "UNREGISTERED") then
address_tmp <= address;
we_tmp <= we;
memenab_tmp <= memenab;
else
ASSERT FALSE
REPORT "Illegal LPM_ADDRESS_CONTROL property value for LPM_RAM_IO!"
SEVERITY ERROR;
end if;
if (lpm_indata = "REGISTERED") then
data_tmp <= data_reg;
elsif (lpm_indata = "UNREGISTERED") then
data_tmp <= di;
else
ASSERT FALSE
REPORT "Illegal LPM_INDATA property value for LPM_RAM_IO!"
SEVERITY ERROR;
end if;
if (lpm_outdata = "REGISTERED") then
q <= q_reg;
elsif (lpm_outdata = "UNREGISTERED") then
q <= q_tmp;
else
ASSERT FALSE
REPORT "Illegal LPM_OUTDATA property value for LPM_RAM_IO!"
SEVERITY ERROR;
end if;
end process;
input_reg: process (inclock)
begin
if inclock'event and inclock = '1' then
data_reg <= di;
address_reg <= address;
we_reg <= we;
memenab_reg <= memenab;
end if;
end process;
output_reg: process (outclock)
begin
if outclock'event and outclock = '1' then
q_reg <= q_tmp;
end if;
end process;
INITIALIZE : process(we, outenab)
variable init : boolean := FALSE;
begin
if NOT (init) then
if (outenab = 'Z' and we = 'Z') then
ASSERT FALSE
REPORT "One of OutEnab or WE must be used!"
SEVERITY ERROR;
end if;
-- In reality, both are needed in current TDF implementation
if (outenab /= 'Z' and we /= 'Z') then
ASSERT FALSE
REPORT "Only one of OutEnab or WE should be used!"
-- Change severity to ERROR for full LPM 220 compliance
SEVERITY WARNING;
end if;
-- Comment out the following 5 lines for full LPM 220 compliance
if (we = 'Z') then
ASSERT FALSE
REPORT "WE is required!"
SEVERITY WARNING;
end if;
if (outenab = 'Z') then
outenab_used <= '0';
we_used <= '1';
else
outenab_used <= '1';
we_used <= '0';
end if;
-- Comment out the following 5 lines for full LPM 220 compliance
if (we = 'Z') then
we_used <= '0';
else
we_used <= '1';
end if;
init := TRUE;
end if;
end process;
memory: process(data_tmp, we_tmp, memenab_tmp, outenab, address_tmp, inclock, we_used, outenab_used)
variable mem_data : lpm_memory;
variable mem_data_word : std_logic_vector(lpm_width-1 downto 0);
variable mem_init: boolean := false;
variable i,j,k,n,m,lineno: integer := 0;
variable buf: line ;
variable booval: boolean ;
FILE mem_data_file: TEXT IS IN lpm_file;
variable char : string(1 downto 1) := " ";
variable base, byte, rec_type, datain, addr, checksum: string(2 downto 1);
variable startadd: string(4 downto 1);
variable ibase: integer := 0;
variable ibyte: integer := 0;
variable istartadd: integer := 0;
variable check_sum_vec, check_sum_vec_tmp: std_logic_vector(7 downto 0);
variable m_string : string(1 to 15);
variable m_data_radix : string(1 to 3);
variable m_address_radix : string(1 to 3);
variable m_width : integer;
variable m_depth : integer;
variable m_start_address_int : integer := 0;
variable m_end_address_int : integer := 0;
variable m_address_int : integer := 0;
variable m_data_int : std_logic_vector(lpm_width+4 downto 0) := (OTHERS => '0');
variable found_keyword_content : boolean := false;
variable get_memory_content : boolean := false;
variable get_start_Address : boolean := false;
variable get_end_Address : boolean := false;
begin
-- INITIALIZE --
if NOT(mem_init) then
-- INITIALIZE TO 0 --
for i in mem_data'LOW to mem_data'HIGH loop
mem_data(i) := (OTHERS => '0');
end loop;
if (LPM_FILE /= "UNUSED") then
if (ALPHA_TOLOWER(lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) = ".hex") then
WHILE NOT ENDFILE(mem_data_file) loop
booval := true;
READLINE(mem_data_file, buf);
lineno := lineno + 1;
check_sum_vec := (OTHERS => '0');
if (buf(buf'LOW) = ':') then
i := 1;
SHRINK_LINE(buf, i);
READ(L=>buf, VALUE=>byte, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format!"
SEVERITY ERROR;
end if;
ibyte := HEX_STR_TO_INT(byte);
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(ibyte, 8));
READ(L=>buf, VALUE=>startadd, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
istartadd := HEX_STR_TO_INT(startadd);
addr(2) := startadd(4);
addr(1) := startadd(3);
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8));
addr(2) := startadd(2);
addr(1) := startadd(1);
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8));
READ(L=>buf, VALUE=>rec_type, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(rec_type), 8));
else
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
case rec_type is
when "00"=> -- Data record
i := 0;
k := lpm_width / 8;
if ((lpm_width MOD 8) /= 0) then
k := k + 1;
end if;
-- k = no. of bytes per CAM entry.
while (i < ibyte) loop
mem_data_word := (others => '0');
n := (k - 1)*8;
m := lpm_width - 1;
for j in 1 to k loop
READ(L=>buf, VALUE=>datain,good=>booval); -- read in data a byte (2 hex chars) at a time.
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), 8));
mem_data_word(m downto n) := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), m-n+1);
m := n - 1;
n := n - 8;
end loop;
i := i + k;
mem_data(ibase + istartadd) := mem_data_word;
istartadd := istartadd + 1;
end loop;
when "01"=>
exit;
when "02"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format for record type 02! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := ibase * 256 + HEX_STR_TO_INT(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
ibase := ibase * 16;
when "03"=>
if (ibyte /= 4) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 03! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
when "04"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 04! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := (ibase * 256) + HEX_STR_TO_INT(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
ibase := ibase * 65536;
when "05"=>
if (ibyte /= 4) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 05! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
when OTHERS =>
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal record type in Intel Hex File! "
SEVERITY ERROR;
end case;
READ(L=>buf, VALUE=>checksum,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Checksum is missing! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(not (check_sum_vec)) + 1 ;
check_sum_vec_tmp := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(checksum),8);
if (unsigned(check_sum_vec) /= unsigned(check_sum_vec_tmp)) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Incorrect checksum!"
SEVERITY ERROR;
end if;
end loop;
elsif (ALPHA_TOLOWER(lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) = ".mif") then
-- ************************************************
-- Read in RAM initialization file (mif)
-- ************************************************
while not endfile(mem_data_file) loop
booval := true;
readline(mem_data_file, buf);
lineno := lineno + 1;
LOOP2 : while (buf'length > 0) loop
if (buf(buf'low) = '-') then
if (buf(buf'low) = '-') then
-- ignore comment started with --.
exit LOOP2;
end if;
elsif (buf(buf'low) = '%') then
i := 1;
-- ignore comment which begin with % and end with another %.
while ((i < buf'high) and (buf(buf'low + i) /= '%')) loop
i := i+1;
end loop;
if (i >= buf'high) then
exit LOOP2;
else
SHRINK_LINE(buf, i+1);
end if;
elsif ((buf(buf'low) = ' ') or (buf(buf'low) = HT)) then
i := 1;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i >= buf'high) then
exit LOOP2;
else
SHRINK_LINE(buf, i);
end if;
elsif (get_memory_content = true) then
if (((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "end") or
((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "END") or
((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "End")) then
get_memory_content := false;
exit LOOP2;
else
get_start_address := false;
get_end_address := false;
m_start_address_int := 0;
m_end_address_int := 0;
m_address_int := 0;
m_data_int := (others => '0');
if (buf(buf'low) = '[') then
get_start_Address := true;
SHRINK_LINE(buf, 1);
end if;
case m_address_radix is
when "hex" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *16 + HEX_STR_TO_INT(char);
end loop;
when "bin" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *2 + BIN_STR_TO_INT(char);
end loop;
when "dec" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "uns" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "oct" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *8 + OCT_STR_TO_INT(char);
end loop;
when others =>
assert false
report "Unsupported address_radix!"
severity error;
end case;
if (get_start_Address = true) then
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
if ((buf(buf'low) = '.') and (buf(buf'low+1) = '.')) then
get_start_Address := false;
get_end_Address := true;
m_start_address_int := m_address_int;
SHRINK_LINE(buf, 2);
end if;
end if;
if (get_end_address = true) then
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
m_address_int := 0;
case m_address_radix is
when "hex" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *16 + HEX_STR_TO_INT(char);
end loop;
when "bin" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *2 + BIN_STR_TO_INT(char);
end loop;
when "dec" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "uns" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "oct" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *8 + OCT_STR_TO_INT(char);
end loop;
when others =>
assert false
report "Unsupported address_radix!"
severity error;
end case;
if (buf(buf'low) = ']') then
get_end_address := false;
m_end_address_int := m_address_int;
SHRINK_LINE(buf, 1);
end if;
end if;
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
if (buf(buf'low) = ':') then
SHRINK_LINE(buf, 1);
end if;
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
case m_data_radix is
when "hex" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+4 downto 0) := m_data_int(lpm_width-1 downto 0) * "10000" + conv_std_logic_vector(HEX_STR_TO_INT(char), 4);
end loop;
when "bin" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+1 downto 0) := m_data_int(lpm_width-1 downto 0) * "10" + conv_std_logic_vector(BIN_STR_TO_INT(char), 4);
end loop;
when "dec" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4);
end loop;
when "uns" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4);
end loop;
when "oct" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1000" + conv_std_logic_vector(OCT_STR_TO_INT(char), 4);
end loop;
when others =>
assert false
report "Unsupported data_radix!"
severity error;
end case;
if (m_start_address_int /= m_end_address_int) then
for i in m_start_address_int to m_end_address_int loop
mem_data(i) := m_data_int(lpm_width-1 downto 0);
end loop;
else
mem_data(m_address_int) := m_data_int(lpm_width-1 downto 0);
end if;
exit LOOP2;
end if;
elsif ((buf(buf'low) = 'W') or (buf(buf'low) = 'w')) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "width") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to i));
m_width := INT_STR_TO_INT(m_string(1 to i));
end if;
exit LOOP2;
elsif (((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) and
((buf(buf'low+1) = 'E') or (buf(buf'low+1) = 'e'))) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "depth") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to i));
m_depth := INT_STR_TO_INT(m_string(1 to i));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) then
read(l=>buf, value=>m_string(1 to 10));
if (ALPHA_TOLOWER(m_string(1 to 10)) = "data_radix") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to 3));
m_data_radix := ALPHA_TOLOWER(m_string(1 to 3));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'A') or (buf(buf'low) = 'a')) then
read(l=>buf, value=>m_string(1 to 13));
if (ALPHA_TOLOWER(m_string(1 to 13)) = "address_radix") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to 3));
m_address_radix := ALPHA_TOLOWER(m_string(1 to 3));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'C') or (buf(buf'low) = 'c')) then
read(l=>buf, value=>m_string(1 to 7));
if (ALPHA_TOLOWER(m_string(1 to 7)) = "content") then
found_keyword_content := true;
end if;
elsif ((buf(buf'low) = 'B') or (buf(buf'low) = 'b')) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "begin") then
if (found_keyword_content = true) then
get_memory_content := true;
end if;
end if;
end if;
end loop;
end loop;
else
assert false
report "Unsupported memory initialization file type (" & (lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) & ")!"
severity error;
end if;
end if;
mem_init := TRUE;
end if;
-- MEMORY FUNCTION --
if (((we_used = '1' and we_tmp = '1')
or (outenab_used = '1' and we_used = '0' and outenab = '0'))
and memenab_tmp = '1') then
if (((use_eab = "ON") or (lpm_hint = "USE_EAB=ON")) and (lpm_address_control = "REGISTERED")) then
if inclock = '0' then
mem_data (conv_integer(address_tmp)) := data_tmp ;
end if;
else
mem_data (conv_integer(address_tmp)) := data_tmp ;
end if;
q_tmp <= data_tmp ;
else
q_tmp <= mem_data(conv_integer(address_tmp)) ;
end if;
end process;
di <= dio when ((outenab_used = '0' and we = '1')
or (outenab_used = '1' and outenab = '0'))
else (OTHERS => 'Z');
do <= q when memenab_tmp = '1' else (OTHERS => 'Z') ;
dio <= do when ((outenab_used = '0' and we = '0')
or (outenab_used = '1' and outenab = '1'))
else (OTHERS => 'Z');
end LPM_SYN;
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_rom
--
-- Description : Parameterized ROM megafunction. This megafunction is provided
-- only for backward compatibility in Cyclone, Stratix, and
-- Stratix GX designs; instead, Altera recommends using the
-- altsyncram megafunction.
--
-- Limitation : This option is available for all Altera devices supported by
-- the Quartus II software except MAX 3000 and MAX 7000 devices.
--
-- Results Expected: Output of memory.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
use work.LPM_COMMON_CONVERSION.all;
use work.LPM_DEVICE_FAMILIES.all;
use std.textio.all;
-- ENTITY DECLARATION
entity LPM_ROM is
generic (
-- Width of the q[] port. (Required)
lpm_width : natural;
-- Width of the address[] port. (Required)
lpm_widthad : natural;
-- Number of words stored in memory.
lpm_numwords : natural := 0;
-- Indicates whether the address port is registered.
lpm_address_control : string := "REGISTERED";
-- Indicates whether the q and eq ports are registered.
lpm_outdata : string := "REGISTERED";
-- Name of the memory file containing ROM initialization data
lpm_file : string;
intended_device_family : string := "UNUSED";
lpm_type : string := "LPM_ROM";
lpm_hint : string := "UNUSED"
);
port (
-- Address input to the memory. (Required)
address : in STD_LOGIC_VECTOR(lpm_widthad-1 downto 0);
-- Clock for input registers.
inclock : in STD_LOGIC := '0';
-- Clock for output registers.
outclock : in STD_LOGIC := '0';
-- Memory enable input.
memenab : in STD_LOGIC := '1';
-- Output of memory. (Required)
q : out STD_LOGIC_VECTOR(lpm_width-1 downto 0)
);
end LPM_ROM;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of lpm_rom is
-- FUNCTION DECLARATION
--- Get the number of word stored in memory ---
function get_num_words (constant i_lpm_numwords,
i_lpm_widthad : in natural) return natural is
variable i_num_words : natural;
begin
if (i_lpm_numwords = 0) then
i_num_words := (2**lpm_widthad);
elsif (i_lpm_numwords > 0) then
i_num_words := i_lpm_numwords;
else
ASSERT FALSE
REPORT "Value of lpm_numwords parameter must be greater than 0!"
SEVERITY ERROR;
end if;
return i_num_words;
end get_num_words;
-- CONSTANT DECLARATION
constant NUM_WORDS : natural := get_num_words(lpm_numwords, lpm_widthad);
-- TYPE DECLARATION
type LPM_MEMORY is array(NUM_WORDS-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
-- SIGNAL DECLARATION
signal q2, q_tmp, q_reg : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
signal address_tmp, address_reg : std_logic_vector(lpm_widthad-1 downto 0);
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_widthad <= 0) then
ASSERT FALSE
REPORT "Value of lpm_widthad parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (IS_VALID_FAMILY(intended_device_family) = false) then
ASSERT FALSE
REPORT "Unknown INTENDED_DEVICE_FAMILY " & intended_device_family
SEVERITY ERROR;
end if;
if (FEATURE_FAMILY_MAX(intended_device_family) = true) then
ASSERT FALSE
REPORT "LPM_ROM megafunction does not support " & intended_device_family & " devices"
SEVERITY ERROR;
end if;
wait;
end process MSG;
ENABLE_MEM: process(memenab, q2)
begin
if (memenab = '1') then
q <= q2;
else
q <= (OTHERS => 'Z');
end if;
end process ENABLE_MEM;
SYNC: process(address, address_reg, q_tmp, q_reg)
begin
if (lpm_address_control = "REGISTERED") then
address_tmp <= address_reg;
elsif (lpm_address_control = "UNREGISTERED") then
address_tmp <= address;
else
ASSERT FALSE
REPORT "Illegal lpm_address_control property value for LPM_RAM_ROM!"
SEVERITY ERROR;
end if;
if (lpm_outdata = "REGISTERED") then
q2 <= q_reg;
elsif (lpm_outdata = "UNREGISTERED") then
q2 <= q_tmp;
else
ASSERT FALSE
REPORT "Illegal lpm_outdata property value for LPM_RAM_ROM!"
SEVERITY ERROR;
end if;
end process SYNC;
INPUT_REG: process (inclock)
begin
if (inclock'event and (inclock = '1')) then
address_reg <= address;
end if;
end process INPUT_REG;
OUTPUT_REG: process (outclock)
begin
if (outclock'event and (outclock = '1')) then
q_reg <= q_tmp;
end if;
end process OUTPUT_REG;
MEMORY: process(memenab, address_tmp)
variable mem_data : LPM_MEMORY;
variable mem_data_word : std_logic_vector(lpm_width-1 downto 0);
variable mem_init: boolean := false;
variable i, j, k, n, m, lineno : integer := 0;
variable buf: line ;
variable booval: boolean ;
FILE mem_data_file: TEXT IS IN lpm_file;
variable char : string(1 downto 1) := " ";
variable base, byte, rec_type, datain, addr, checksum: string(2 downto 1);
variable startadd: string(4 downto 1);
variable ibase: integer := 0;
variable ibyte: integer := 0;
variable istartadd: integer := 0;
variable check_sum_vec, check_sum_vec_tmp: std_logic_vector(7 downto 0);
variable m_string : string(1 to 15);
variable m_data_radix : string(1 to 3);
variable m_address_radix : string(1 to 3);
variable m_width : integer;
variable m_depth : integer;
variable m_start_address_int : integer := 0;
variable m_end_address_int : integer := 0;
variable m_address_int : integer := 0;
variable m_data_int : std_logic_vector(lpm_width+4 downto 0) := (OTHERS => '0');
variable found_keyword_content : boolean := false;
variable get_memory_content : boolean := false;
variable get_start_Address : boolean := false;
variable get_end_Address : boolean := false;
begin
-- Initialize
if NOT(mem_init) then
-- check for number of words out of bound
if ((NUM_WORDS > (2**lpm_widthad)) or
(NUM_WORDS <= (2**(lpm_widthad-1)))) then
ASSERT FALSE
REPORT "The ceiling of log2(LPM_NUMWORDS) must equal to LPM_WIDTHAD!"
SEVERITY ERROR;
end if;
-- Initialize to zero
for i in mem_data'LOW to mem_data'HIGH loop
mem_data(i) := (OTHERS => '0');
end loop;
if ((lpm_file = "UNUSED") or (lpm_file = "")) then
ASSERT FALSE
REPORT "Initialization file not found!"
SEVERITY ERROR;
else
if (ALPHA_TOLOWER(lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) = ".hex") then
WHILE NOT ENDFILE(mem_data_file) loop
booval := true;
READLINE(mem_data_file, buf);
lineno := lineno + 1;
check_sum_vec := (OTHERS => '0');
if (buf(buf'LOW) = ':') then
i := 1;
SHRINK_LINE(buf, i);
READ(L=>buf, VALUE=>byte, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format!"
SEVERITY ERROR;
end if;
ibyte := HEX_STR_TO_INT(byte);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(ibyte, 8));
READ(L=>buf, VALUE=>startadd, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
istartadd := HEX_STR_TO_INT(startadd);
addr(2) := startadd(4);
addr(1) := startadd(3);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8));
addr(2) := startadd(2);
addr(1) := startadd(1);
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(addr), 8));
READ(L=>buf, VALUE=>rec_type, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(rec_type), 8));
else
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
case rec_type is
when "00"=> -- Data record
i := 0;
k := lpm_width / 8;
if ((lpm_width MOD 8) /= 0) then
k := k + 1;
end if;
-- k = no. of bytes per CAM entry.
while (i < ibyte) loop
mem_data_word := (others => '0');
n := (k - 1)*8;
m := lpm_width - 1;
for j in 1 to k loop
-- read in data a byte (2 hex chars) at a time.
READ(L=>buf, VALUE=>datain,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), 8));
mem_data_word(m downto n) := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(datain), m-n+1);
m := n - 1;
n := n - 8;
end loop;
i := i + k;
mem_data(ibase + istartadd) := mem_data_word;
istartadd := istartadd + 1;
end loop;
when "01"=>
exit;
when "02"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format for record type 02! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := ibase * 256 + HEX_STR_TO_INT(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) +
unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
ibase := ibase * 16;
when "03"=>
if (ibyte /= 4) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 03! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
when "04"=>
ibase := 0;
if (ibyte /= 2) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 04! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
ibase := (ibase * 256) + HEX_STR_TO_INT(base);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
ibase := ibase * 65536;
when "05"=>
if (ibyte /= 4) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format for record type 05! "
SEVERITY ERROR;
end if;
for i in 0 to (ibyte-1) loop
READ(L=>buf, VALUE=>base,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) &
"]:Illegal Intel Hex Format! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(check_sum_vec) + unsigned(CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(base), 8));
end loop;
when OTHERS =>
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Illegal record type in Intel Hex File! "
SEVERITY ERROR;
end case;
READ(L=>buf, VALUE=>checksum,good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Checksum is missing! "
SEVERITY ERROR;
end if;
check_sum_vec := unsigned(not (check_sum_vec)) + 1 ;
check_sum_vec_tmp := CONV_STD_LOGIC_VECTOR(HEX_STR_TO_INT(checksum),8);
if (unsigned(check_sum_vec) /= unsigned(check_sum_vec_tmp)) then
ASSERT FALSE
REPORT "[Line "& INT_TO_STR(lineno) & "]:Incorrect checksum!"
SEVERITY ERROR;
end if;
end loop;
elsif (ALPHA_TOLOWER(lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) = ".mif") then
-- ************************************************
-- Read in RAM initialization file (mif)
-- ************************************************
while not endfile(mem_data_file) loop
booval := true;
readline(mem_data_file, buf);
lineno := lineno + 1;
LOOP2 : while (buf'length > 0) loop
if (buf(buf'low) = '-') then
if (buf(buf'low) = '-') then
-- ignore comment started with --.
exit LOOP2;
end if;
elsif (buf(buf'low) = '%') then
i := 1;
-- ignore comment which begin with % and end with another %.
while ((i < buf'high) and (buf(buf'low + i) /= '%')) loop
i := i+1;
end loop;
if (i >= buf'high) then
exit LOOP2;
else
SHRINK_LINE(buf, i+1);
end if;
elsif ((buf(buf'low) = ' ') or (buf(buf'low) = HT)) then
i := 1;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i >= buf'high) then
exit LOOP2;
else
SHRINK_LINE(buf, i);
end if;
elsif (get_memory_content = true) then
if (((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "end") or
((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "END") or
((buf(buf'low) & buf(buf'low +1) & buf(buf'low +2)) = "End")) then
get_memory_content := false;
exit LOOP2;
else
get_start_address := false;
get_end_address := false;
m_start_address_int := 0;
m_end_address_int := 0;
m_address_int := 0;
m_data_int := (others => '0');
if (buf(buf'low) = '[') then
get_start_Address := true;
SHRINK_LINE(buf, 1);
end if;
case m_address_radix is
when "hex" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *16 + HEX_STR_TO_INT(char);
end loop;
when "bin" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *2 + BIN_STR_TO_INT(char);
end loop;
when "dec" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "uns" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "oct" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ':') and (buf(buf'low) /= '.')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *8 + OCT_STR_TO_INT(char);
end loop;
when others =>
assert false
report "Unsupported address_radix!"
severity error;
end case;
if (get_start_Address = true) then
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
if ((buf(buf'low) = '.') and (buf(buf'low+1) = '.')) then
get_start_Address := false;
get_end_Address := true;
m_start_address_int := m_address_int;
SHRINK_LINE(buf, 2);
end if;
end if;
if (get_end_address = true) then
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
m_address_int := 0;
case m_address_radix is
when "hex" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *16 + HEX_STR_TO_INT(char);
end loop;
when "bin" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *2 + BIN_STR_TO_INT(char);
end loop;
when "dec" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "uns" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *10 + INT_STR_TO_INT(char);
end loop;
when "oct" =>
while ((buf(buf'low) /= ' ') and (buf(buf'low) /= HT) and
(buf(buf'low) /= ']')) loop
read(l => buf, value => char, good => booval);
m_address_int := m_address_int *8 + OCT_STR_TO_INT(char);
end loop;
when others =>
assert false
report "Unsupported address_radix!"
severity error;
end case;
if (buf(buf'low) = ']') then
get_end_address := false;
m_end_address_int := m_address_int;
SHRINK_LINE(buf, 1);
end if;
end if;
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
if (buf(buf'low) = ':') then
SHRINK_LINE(buf, 1);
end if;
i := 0;
-- ignore space or tab character.
while ((i < buf'high-1) and ((buf(buf'low +i) = ' ') or
(buf(buf'low+i) = HT))) loop
i := i+1;
end loop;
if (i > 0) then
SHRINK_LINE(buf, i);
end if;
case m_data_radix is
when "hex" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+4 downto 0) := m_data_int(lpm_width-1 downto 0) * "10000" + conv_std_logic_vector(HEX_STR_TO_INT(char), 4);
end loop;
when "bin" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+1 downto 0) := m_data_int(lpm_width-1 downto 0) * "10" + conv_std_logic_vector(BIN_STR_TO_INT(char), 4);
end loop;
when "dec" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4);
end loop;
when "uns" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1010" + conv_std_logic_vector(INT_STR_TO_INT(char), 4);
end loop;
when "oct" =>
while ((buf(buf'low) /= ';') and (buf(buf'low) /= ' ') and
(buf(buf'low) /= HT)) loop
read(l => buf, value => char, good => booval);
m_data_int(lpm_width+3 downto 0) := m_data_int(lpm_width-1 downto 0) * "1000" + conv_std_logic_vector(OCT_STR_TO_INT(char), 4);
end loop;
when others =>
assert false
report "Unsupported data_radix!"
severity error;
end case;
if (m_start_address_int /= m_end_address_int) then
for i in m_start_address_int to m_end_address_int loop
mem_data(i) := m_data_int(lpm_width-1 downto 0);
end loop;
else
mem_data(m_address_int) := m_data_int(lpm_width-1 downto 0);
end if;
exit LOOP2;
end if;
elsif ((buf(buf'low) = 'W') or (buf(buf'low) = 'w')) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "width") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to i));
m_width := INT_STR_TO_INT(m_string(1 to i));
end if;
exit LOOP2;
elsif (((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) and
((buf(buf'low+1) = 'E') or (buf(buf'low+1) = 'e'))) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "depth") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low +i) = ' ') or (buf(buf'low +i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to i));
m_depth := INT_STR_TO_INT(m_string(1 to i));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'D') or (buf(buf'low) = 'd')) then
read(l=>buf, value=>m_string(1 to 10));
if (ALPHA_TOLOWER(m_string(1 to 10)) = "data_radix") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to 3));
m_data_radix := ALPHA_TOLOWER(m_string(1 to 3));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'A') or (buf(buf'low) = 'a')) then
read(l=>buf, value=>m_string(1 to 13));
if (ALPHA_TOLOWER(m_string(1 to 13)) = "address_radix") then
i := 0;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
if (buf(buf'low + i) = '=') then
i := i+1;
end if;
while ((buf(buf'low+i) = ' ') or (buf(buf'low+i) = HT)) loop
i := i+1;
end loop;
SHRINK_LINE(buf, i);
i := 0;
while (buf(buf'low + i) /= ';') loop
i := i+1;
end loop;
read(l=>buf, value=>m_string(1 to 3));
m_address_radix := ALPHA_TOLOWER(m_string(1 to 3));
end if;
exit LOOP2;
elsif ((buf(buf'low) = 'C') or (buf(buf'low) = 'c')) then
read(l=>buf, value=>m_string(1 to 7));
if (ALPHA_TOLOWER(m_string(1 to 7)) = "content") then
found_keyword_content := true;
end if;
elsif ((buf(buf'low) = 'B') or (buf(buf'low) = 'b')) then
read(l=>buf, value=>m_string(1 to 5));
if (ALPHA_TOLOWER(m_string(1 to 5)) = "begin") then
if (found_keyword_content = true) then
get_memory_content := true;
end if;
end if;
end if;
end loop;
end loop;
else
assert false
report "Unsupported memory initialization file type (" & (lpm_file(lpm_file'length -3) & lpm_file(lpm_file'length -2) & lpm_file(lpm_file'length -1) & lpm_file(lpm_file'length)) & ")!"
severity error;
end if;
end if;
mem_init := TRUE;
end if;
q_tmp <= mem_data(conv_integer(address_tmp));
end process MEMORY;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_fifo
--
-- Description :
--
-- Limitation :
--
-- Results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
library IEEE;
-- BEGINNING OF ENTITY
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_DEVICE_FAMILIES.all;
use work.LPM_HINT_EVALUATION.all;
-- ENTITY DECLARATION
entity LPM_FIFO is
-- GENERIC DECLARATION
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_numwords : natural;
lpm_showahead : string := "OFF";
lpm_type : string := "LPM_FIFO";
lpm_hint : string := "");
-- PORT DECLARATION
port (
-- INPUT PORT DECLARATION
data : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic;
wrreq : in std_logic;
rdreq : in std_logic;
aclr : in std_logic := '0';
sclr : in std_logic := '0';
-- OUTPUT PORT DECLARATION
q : out std_logic_vector(lpm_width-1 downto 0);
usedw : out std_logic_vector(lpm_widthu-1 downto 0);
full : out std_logic;
empty : out std_logic);
end LPM_FIFO;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
-- ARCHITECTURE DECLARATION
architecture behavior of LPM_FIFO is
-- TYPE DECLARATION
type lpm_memory is array (2**lpm_widthu-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
-- FUNCTION DECLARATION
function get_underflow_checking return string is
constant param_value : string := get_parameter_value(LPM_HINT, "UNDERFLOW_CHECKING");
begin
if ( param_value /= "") then
return param_value;
else
return "ON";
end if;
end get_underflow_checking;
function get_overflow_checking return string is
constant param_value : string := get_parameter_value(LPM_HINT, "OVERFLOW_CHECKING");
begin
if ( param_value /= "") then
return param_value;
else
return "ON";
end if;
end get_overflow_checking;
function get_allow_rwcycle_when_full return string is
constant param_value : string := get_parameter_value(LPM_HINT, "ALLOW_RWCYCLE_WHEN_FULL");
begin
if ( param_value /= "") then
return param_value;
else
return "OFF";
end if;
end get_allow_rwcycle_when_full;
function get_intended_device_family return string is
constant param_value : string := get_parameter_value(LPM_HINT, "INTENDED_DEVICE_FAMILY");
begin
if ( param_value /= "") then
return param_value;
else
return "Stratix II";
end if;
end get_intended_device_family;
-- CONSTANT DECLARATION
constant ZEROS : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
constant UNKNOWNS : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => 'X');
constant underflow_checking : string := get_underflow_checking;
constant overflow_checking : string := get_overflow_checking;
constant allow_rwcycle_when_full : string := get_allow_rwcycle_when_full;
constant intended_device_family : string := get_intended_device_family;
-- SIGNAL DECLARATION
signal i_count_id : integer := 0;
signal i_read_id : integer := 0;
signal i_write_id : integer := 0;
signal i_full_flag : std_logic := '0';
signal i_empty_flag : std_logic := '1';
signal i_tmp_q : std_logic_vector(lpm_width-1 downto 0) := ZEROS;
begin
-- PROCESS DECLARATION
process (clock, aclr)
-- VARIABLE DECLARATION
variable mem_data : lpm_memory := (OTHERS => ZEROS);
variable tmp_data : std_logic_vector(lpm_width-1 downto 0) := ZEROS;
variable write_id : integer := 0;
variable write_flag : boolean := false;
variable full_flag : boolean := false;
variable valid_rreq : boolean := false;
variable valid_wreq : boolean := false;
variable max_widthu : integer := 0;
variable numwords_minus_one : integer := 0;
variable need_init : boolean := true;
begin
if (need_init) then
if ((lpm_showahead /= "ON") and (lpm_showahead /= "OFF")) then
ASSERT FALSE
REPORT "Illegal LPM_SHOWAHEAD property value for LPM_FIFO!"
SEVERITY ERROR;
end if;
if ((underflow_checking /= "ON") and (underflow_checking /= "OFF")) then
ASSERT FALSE
REPORT "Illegal UNDERFLOW_CHECKING property value for LPM_FIFO!"
SEVERITY ERROR;
end if;
if ((overflow_checking /= "ON") and (overflow_checking /= "OFF")) then
ASSERT FALSE
REPORT "Illegal OVERFLOW_CHECKING property value for LPM_FIFO!"
SEVERITY ERROR;
end if;
if ((allow_rwcycle_when_full /= "ON") and (allow_rwcycle_when_full /= "OFF")) then
ASSERT FALSE
REPORT "Illegal ALLOW_RWCYCLE_WHEN_FULL property value for LPM_FIFO!"
SEVERITY ERROR;
end if;
if (IS_VALID_FAMILY(intended_device_family) = false) then
ASSERT FALSE
REPORT "Illegal INTENDED_DEVICE_FAMILY for LPM_FIFO!"
SEVERITY ERROR;
end if;
for i in 0 to (lpm_widthu - 1) loop
if (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or
FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) then
mem_data(i) := UNKNOWNS;
else
mem_data(i) := ZEROS;
end if;
end loop;
if (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or
FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) then
i_tmp_q <= UNKNOWNS;
else
i_tmp_q <= ZEROS;
end if;
max_widthu := (2 ** lpm_widthu) - 1;
numwords_minus_one := lpm_numwords - 1;
need_init := false;
end if; -- need_init
if (aclr = '1') then
full_flag := false;
if (not (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or
FEATURE_FAMILY_BASE_CYCLONE(intended_device_family))) then
i_tmp_q <= ZEROS;
end if;
write_id := 0;
if (lpm_showahead = "ON") then
i_tmp_q <= mem_data(0);
end if;
end if; -- aclr event
if (clock'event and (clock = '1') and
((aclr = '0') or (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or
FEATURE_FAMILY_BASE_CYCLONE(intended_device_family))))
then
valid_rreq := rdreq = '1' and ((i_empty_flag = '0') or
(underflow_checking = "OFF"));
valid_wreq := wrreq = '1' and ((i_full_flag = '0') or
(overflow_checking = "OFF") or ((rdreq = '1') and
(allow_rwcycle_when_full = "ON")));
if (sclr = '1')
then
i_tmp_q <= mem_data(i_read_id);
i_read_id <= 0;
i_count_id <= 0;
i_write_id <= 0;
i_full_flag <= '0';
i_empty_flag <= '1';
write_id := 0;
full_flag := false;
if (valid_wreq)
then
tmp_data := data;
write_id := i_write_id;
write_flag := true;
end if;
if ((lpm_showahead = "ON") or (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or
FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)))
then
i_tmp_q <= mem_data(0);
end if;
else
-- Both WRITE and READ operations
if (valid_wreq and valid_rreq)
then
tmp_data := data;
write_id := i_write_id;
write_flag := true;
i_empty_flag <= '0';
if (allow_rwcycle_when_full = "OFF")
then
i_full_flag <= '0';
full_flag := false;
end if;
if (i_write_id >= max_widthu)
then
i_write_id <= 0;
else
i_write_id <= i_write_id + 1;
end if;
i_tmp_q <= mem_data(i_read_id);
if (i_read_id >= max_widthu)
then
i_read_id <= 0;
if (lpm_showahead = "ON")
then
i_tmp_q <= mem_data(0);
end if;
else
i_read_id <= i_read_id + 1;
if (lpm_showahead = "ON")
then
i_tmp_q <= mem_data(i_read_id + 1);
end if;
end if;
-- WRITE operation only
elsif (valid_wreq)
then
tmp_data := data;
write_id := i_write_id;
write_flag := true;
if (lpm_showahead = "ON")
then
i_tmp_q <= mem_data(i_read_id);
end if;
i_count_id <= i_count_id + 1;
i_empty_flag <= '0';
if (i_count_id >= max_widthu)
then
i_count_id <= 0;
end if;
if ((i_count_id = numwords_minus_one) and (i_empty_flag = '0'))
then
i_full_flag <= '1';
full_flag := true;
end if;
if (i_write_id >= max_widthu)
then
i_write_id <= 0;
else
i_write_id <= i_write_id + 1;
end if;
-- READ operation only
elsif (valid_rreq)
then
i_tmp_q <= mem_data(i_read_id);
i_count_id <= i_count_id - 1;
i_full_flag <= '0';
full_flag := false;
if (i_count_id <= 0)
then
i_count_id <= max_widthu;
end if;
if (i_count_id = 1 and i_full_flag = '0')
then
i_empty_flag <= '1';
end if;
if (i_read_id >= max_widthu)
then
i_read_id <= 0;
if (lpm_showahead = "ON")
then
i_tmp_q <= mem_data(0);
end if;
else
i_read_id <= i_read_id + 1;
if (lpm_showahead = "ON")
then
i_tmp_q <= mem_data(i_read_id + 1);
end if;
end if;
end if; -- if Both WRITE and READ operations
end if; -- if sclr = '1'
elsif (clock'event and (clock = '0'))
then
if (write_flag)
then
write_flag := false;
mem_data(write_id) := tmp_data;
end if;
if (lpm_showahead = "ON")
then
i_tmp_q <= mem_data(i_read_id);
end if;
end if; -- clock event
if (aclr = '1')
then
i_full_flag <= '0';
i_empty_flag <= '1';
i_read_id <= 0;
i_write_id <= 0;
i_count_id <= 0;
write_id := 0;
end if;
end process; -- clock, aclr events
q <= i_tmp_q;
full <= i_full_flag;
empty <= i_empty_flag;
usedw <= conv_std_logic_vector(i_count_id, lpm_widthu);
end behavior; -- LPM_FIFO
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_fifo_dc_dffpipe
--
-- Description : Dual Clocks FIFO
--
-- Limitation :
--
-- Results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- BEGINNING OF ENTITY
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_FIFO_DC_DFFPIPE is
-- GENERIC DECLARATION
generic (
lpm_delay : natural;
lpm_width : natural
);
-- PORT DECLARATION
port (
-- INPUT PORT DECLARATION
d : in std_logic_vector (lpm_width-1 downto 0);
clock : in std_logic;
aclr : in std_logic := '0';
-- OUTPUT PORT DECLARATION
q : out std_logic_vector (lpm_width-1 downto 0)
);
end LPM_FIFO_DC_DFFPIPE;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
-- ARCHITECTURE DECLARATION
architecture behavior of LPM_FIFO_DC_DFFPIPE is
-- TYPE DECLARATION
type DELAYPIPE is array (lpm_delay downto 0) of std_logic_vector (lpm_width-1 downto 0);
-- CONSTANT DECLARATION
constant ZEROS : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
begin
-- PROCESS DECLARATION
process (clock, aclr, d)
------ VARIABLE DECLARATION
variable intpipe : DELAYPIPE := (OTHERS => ZEROS);
variable delay : integer := lpm_delay - 1;
variable need_init : boolean := true;
begin
if (lpm_delay = 0)
then
if ((aclr = '1') or need_init)
then
q <= ZEROS;
need_init := false;
else
q <= d;
end if;
else
if ((aclr = '1') or need_init)
then
for i in lpm_delay downto 0 loop
intpipe(i) := ZEROS;
end loop;
need_init := false;
q <= ZEROS;
end if;
if (rising_edge(clock) and (NOW > 0 ns))
then
if (delay > 0) then
for i in delay downto 1 loop
intpipe(i) := intpipe(i-1);
end loop;
end if;
intpipe(0) := d;
q <= intpipe(delay);
end if;
end if; -- (lpm_delay = 0)
end process; -- clock, aclr, d events
end behavior; -- lpm_fifo_dc_dffpipe
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_fifo_dc_fefifo
--
-- Description : Dual Clocks FIFO
--
-- Limitation :
--
-- Results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- BEGINNING OF ENTITY
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_FIFO_DC_FEFIFO is
-- GENERIC DECLARATION
generic (
lpm_widthad : natural;
lpm_numwords : natural;
underflow_checking : string := "ON";
overflow_checking : string := "ON";
lpm_mode : string);
-- PORT DECLARATION
port (
-- INPUT PORT DECLARATION
usedw_in : in std_logic_vector(lpm_widthad-1 downto 0);
wreq : in std_logic := 'Z';
rreq : in std_logic := 'Z';
clock : in std_logic;
aclr : in std_logic := '0';
-- OUTPUT PORT DECLARATION
empty : out std_logic;
full : out std_logic);
end LPM_FIFO_DC_FEFIFO;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
-- ARCHITECTURE DECLARATION
architecture behavior of LPM_FIFO_DC_FEFIFO is
-- SIGNAL DECLARATION
signal i_empty : std_logic := '1';
signal i_full : std_logic := '0';
begin
-- PROCESS DECLARATION
process (clock, aclr)
------ VARIABLE DECLARATION
variable sm_empty : std_logic_vector(1 downto 0) := "00";
variable lrreq : std_logic := '0';
variable almost_full : integer := 0;
variable usedw_is_1 : boolean := false;
variable need_init : boolean := true;
begin
if (need_init)
then
if ((lpm_mode /= "READ") and (lpm_mode /= "WRITE"))
then
ASSERT FALSE
REPORT "Error! LPM_MODE must be READ or WRITE."
SEVERITY ERROR;
end if;
if ((underflow_checking /= "ON") and (underflow_checking /= "OFF"))
then
ASSERT FALSE
REPORT "Error! UNDERFLOW_CHECKING must be ON or OFF."
SEVERITY ERROR;
end if;
if ((overflow_checking /= "ON") and (overflow_checking /= "OFF"))
then
ASSERT FALSE
REPORT "Error! OVERFLOW_CHECKING must be ON or OFF."
SEVERITY ERROR;
end if;
if (lpm_numwords >= 3)
then
almost_full := lpm_numwords - 3;
else
almost_full := 0;
end if;
need_init := false;
end if; -- need_init
if (aclr'event and (aclr = '1'))
then
sm_empty := "00";
lrreq := '0';
i_empty <= '1';
i_full <= '0';
end if; -- aclr event
if (rising_edge(clock) and (aclr = '0') and (NOW > 0 ns))
then
if (lpm_mode = "READ")
then
case sm_empty is
-- state_empty
when "00" =>
if (usedw_in /= 0)
then
sm_empty := "01";
end if;
-- state_non_empty
when "01" =>
if (lpm_widthad > 1)
then
usedw_is_1 := ((usedw_in = 1) and (lrreq = '0')) or ((usedw_in = 2) and (lrreq = '1'));
else
usedw_is_1 := (usedw_in = 1) and (lrreq = '0');
end if;
if ((rreq = '1') and usedw_is_1)
then
sm_empty := "10";
end if;
-- state_emptywait
when "10" =>
if (usedw_in > 1)
then
sm_empty := "01";
else
sm_empty := "00";
end if;
when others =>
ASSERT FALSE
REPORT "Error! Invalid sm_empty state in read mode."
SEVERITY ERROR;
end case;
elsif (lpm_mode = "WRITE")
then
case sm_empty is
-- state_empty
when "00" =>
if (wreq = '1')
then
sm_empty := "01";
end if;
-- state_one
when "01" =>
if (wreq = '0')
then
sm_empty := "11";
end if;
-- state_non_empty
when "11" =>
if (wreq = '1')
then
sm_empty := "01";
elsif (usedw_in = 0)
then
sm_empty := "00";
end if;
when others =>
ASSERT FALSE
REPORT "Error! Invalid sm_empty state in write mode."
SEVERITY ERROR;
end case;
end if;
i_empty <= not sm_empty(0);
if ((aclr = '0') and (usedw_in >= almost_full) and (NOW > 0 ns))
then
i_full <= '1';
else
i_full <= '0';
end if;
if (underflow_checking = "OFF")
then
lrreq := rreq;
else
lrreq := rreq and not i_empty;
end if;
end if; -- clock event
end process; -- clock, aclr events
empty <= i_empty;
full <= i_full;
end behavior; -- lpm_fifo_dc_fefifo
-- END OF ARCHITECTURE
--
-- Entity Name : lpm_fifo_dc_async
--
-- Description : Asynchoronous Dual Clocks FIFO
--
-- Limitation :
--
-- Results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- BEGINNING OF ENTITY
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
use work.LPM_DEVICE_FAMILIES.all;
use work.LPM_FIFO_DC_FEFIFO;
use work.LPM_FIFO_DC_DFFPIPE;
-- ENTITY DECLARATION
entity LPM_FIFO_DC_ASYNC is
-- GENERIC DECLARATION
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_numwords : natural;
delay_rdusedw : natural := 1;
delay_wrusedw : natural := 1;
rdsync_delaypipe : natural := 3;
wrsync_delaypipe : natural := 3;
lpm_showahead : string := "OFF";
underflow_checking : string := "ON";
overflow_checking : string := "ON";
use_eab : string := "ON";
intended_device_family : string := "Stratix");
-- PORT DECLARATION
port (
-- INPUT PORT DECLARATION
data : in std_logic_vector(lpm_width-1 downto 0);
rdclk : in std_logic;
wrclk : in std_logic;
rdreq : in std_logic;
wrreq : in std_logic;
aclr : in std_logic := '0';
-- OUTPUT PORT DECLARATION
rdempty : out std_logic;
wrempty : out std_logic;
rdfull : out std_logic;
wrfull : out std_logic;
rdusedw : out std_logic_vector(lpm_widthu-1 downto 0);
wrusedw : out std_logic_vector(lpm_widthu-1 downto 0);
q : out std_logic_vector(lpm_width-1 downto 0));
end LPM_FIFO_DC_ASYNC;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
-- ARCHITECTURE DECLARATION
architecture behavior of LPM_FIFO_DC_ASYNC is
-- TYPE DECLARATION
type LPM_MEMORY is array (2**lpm_widthu-1 downto 0) of std_logic_vector(lpm_width-1 downto 0);
-- CONSTANT DECLARATION
constant ZEROS : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
constant ZEROU : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
constant GRAY_DELAYPIPE : integer := 1;
constant WRUSEDW_DELAYPIPE : integer := 1; -- delayed usedw to compute empty/full
constant RDUSEDW_DELAYPIPE : integer := 1; -- delayed usedw to compute empty/full
-- SIGNAL DECLARATION
signal i_data_tmp : std_logic_vector(lpm_width-1 downto 0);
signal i_rdptr : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_wrptr : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_wrptr_tmp : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_rdptrrg : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_wrdelaycycle : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_rden : std_logic := '0';
signal i_wren : std_logic := '0';
signal i_rdenclock : std_logic := '0';
signal i_wren_tmp : std_logic := '0';
signal i_rdempty : std_logic := '1';
signal i_wrempty : std_logic := '1';
signal i_rdfull : std_logic := '0';
signal i_wrfull : std_logic := '0';
signal i_rdusedw : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_wrusedw : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_ws_nbrp : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_rs_nbwp : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_ws_dbrp : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_rs_dbwp : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_wr_udwn : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_rd_udwn : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_wr_dbuw : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_rd_dbuw : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_q_tmp : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
signal i_zero : std_logic := '0';
-- COMPONENT DECLARATION
component LPM_FIFO_DC_FEFIFO
generic (
lpm_widthad : natural;
lpm_numwords : natural;
underflow_checking : string := "ON";
overflow_checking : string := "ON";
lpm_mode : string);
port (
usedw_in : in std_logic_vector(lpm_widthad-1 downto 0);
wreq : in std_logic := 'Z';
rreq : in std_logic := 'Z';
clock : in std_logic;
aclr : in std_logic := '0';
empty : out std_logic;
full : out std_logic);
end component;
component LPM_FIFO_DC_DFFPIPE
generic (
lpm_delay : natural;
lpm_width : natural);
port (
d : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic;
aclr : in std_logic := '0';
q : out std_logic_vector(lpm_width-1 downto 0));
end component;
begin
-- COMPONENT ASSIGNMENTS
-- Delays & DFF Pipes
DP_RDPTR_D: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => 0,
lpm_width => lpm_widthu)
port map (
d => i_rdptr,
clock => i_rdenclock,
aclr => aclr,
q => i_rdptrrg);
DP_WRPTR_D: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => 1,
lpm_width => lpm_widthu)
port map (
d => i_wrptr,
clock => wrclk,
aclr => aclr,
q => i_wrdelaycycle);
DP_WS_NBRP: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => WRSYNC_DELAYPIPE,
lpm_width => lpm_widthu)
port map (
d => i_rdptrrg,
clock => wrclk,
aclr => aclr,
q => i_ws_nbrp);
DP_RS_NBWP: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => RDSYNC_DELAYPIPE,
lpm_width => lpm_widthu)
port map (
d => i_wrdelaycycle,
clock => rdclk,
aclr => aclr,
q => i_rs_nbwp);
DP_WS_DBRP: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => GRAY_DELAYPIPE,
lpm_width => lpm_widthu)
port map (
d => i_ws_nbrp,
clock => wrclk,
aclr => aclr,
q => i_ws_dbrp);
DP_RS_DBWP: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => GRAY_DELAYPIPE,
lpm_width => lpm_widthu)
port map (
d => i_rs_nbwp,
clock => rdclk,
aclr => aclr,
q => i_rs_dbwp);
DP_WR_USEDW: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => DELAY_WRUSEDW,
lpm_width => lpm_widthu)
port map (
d => i_wr_udwn,
clock => wrclk,
aclr => aclr,
q => i_wrusedw);
DP_RD_USEDW: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => DELAY_RDUSEDW,
lpm_width => lpm_widthu)
port map (
d => i_rd_udwn,
clock => rdclk,
aclr => aclr,
q => i_rdusedw);
DP_WR_DBUW: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => WRUSEDW_DELAYPIPE,
lpm_width => lpm_widthu)
port map (
d => i_wr_udwn,
clock => wrclk,
aclr => aclr,
q => i_wr_dbuw);
DP_RD_DBUW: LPM_FIFO_DC_DFFPIPE
generic map (
lpm_delay => RDUSEDW_DELAYPIPE,
lpm_width => lpm_widthu)
port map (
d => i_rd_udwn,
clock => rdclk,
aclr => aclr,
q => i_rd_dbuw);
-- Empty/Full
WR_FE: LPM_FIFO_DC_FEFIFO
generic map (
lpm_widthad => lpm_widthu,
lpm_numwords => lpm_numwords,
underflow_checking => underflow_checking,
overflow_checking => overflow_checking,
lpm_mode => "WRITE")
port map (
usedw_in => i_wr_dbuw,
wreq => wrreq,
rreq => i_zero,
clock => wrclk,
aclr => aclr,
empty => i_wrempty,
full => i_wrfull);
RD_FE: LPM_FIFO_DC_FEFIFO
generic map (
lpm_widthad => lpm_widthu,
lpm_numwords => lpm_numwords,
underflow_checking => underflow_checking,
overflow_checking => overflow_checking,
lpm_mode => "READ")
port map (
usedw_in => i_rd_dbuw,
wreq => i_zero,
rreq => rdreq,
clock => rdclk,
aclr => aclr,
empty => i_rdempty,
full => i_rdfull);
-- PROCESS DECLARATION
-- FIFOram
process (wrclk, rdclk, aclr)
------ VARIABLE DECLARATION
variable max_widthu : integer := 0;
variable max_widthu_minus_one : integer := 0;
variable mem_data : LPM_MEMORY := (OTHERS => ZEROS);
variable need_init : boolean := true;
begin
if (need_init) then
if ((lpm_showahead /= "ON") and (lpm_showahead /= "OFF"))
then
ASSERT FALSE
REPORT "Error! LPM_SHOWAHEAD must be ON or OFF."
SEVERITY ERROR;
end if;
if ((underflow_checking /= "ON") and (underflow_checking /= "OFF"))
then
ASSERT FALSE
REPORT "Error! UNDERFLOW_CHECKING must be ON or OFF."
SEVERITY ERROR;
end if;
if ((overflow_checking /= "ON") and (overflow_checking /= "OFF"))
then
ASSERT FALSE
REPORT "Error! OVERFLOW_CHECKING must be ON or OFF."
SEVERITY ERROR;
end if;
if ((use_eab /= "ON") and (use_eab /= "OFF"))
then
ASSERT FALSE
REPORT "Error! USE_EAB must be ON or OFF."
SEVERITY ERROR;
end if;
if (IS_VALID_FAMILY(intended_device_family) = false) then
ASSERT FALSE
REPORT "Error! Illegal INTENDED_DEVICE_FAMILY."
SEVERITY ERROR;
end if;
max_widthu := 2 ** lpm_widthu;
max_widthu_minus_one := (2 ** lpm_widthu) - 1;
for i in lpm_numwords - 1 downto 0 loop
mem_data(i) := ZEROS;
end loop;
need_init := false;
end if; -- need_init
if (aclr'event and (aclr = '1'))
then
i_rdptr <= ZEROU;
i_wrptr <= ZEROU;
if (not (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or
FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) or
(use_eab = "OFF"))
then
if (lpm_showahead = "ON")
then
i_q_tmp <= mem_data(0);
else
i_q_tmp <= ZEROS;
end if;
end if;
end if; -- aclr event
if (rising_edge(wrclk))
then
if ((aclr = '1') and (not (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or
FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) or
(use_eab = "OFF")))
then
i_data_tmp <= ZEROS;
i_wrptr_tmp <= ZEROU;
i_wren_tmp <= '0';
elsif (NOW > 0 ns)
then
i_data_tmp <= data;
i_wrptr_tmp <= i_wrptr;
i_wren_tmp <= i_wren;
if (i_wren = '1')
then
if ((aclr = '0') and (i_wrptr < max_widthu_minus_one))
then
i_wrptr <= i_wrptr + 1;
else
i_wrptr <= ZEROU;
end if;
if (use_eab = "OFF")
then
mem_data(CONV_INTEGER(i_wrptr) mod max_widthu) := data;
if (lpm_showahead = "ON")
then
i_q_tmp <= mem_data(CONV_INTEGER(i_rdptr) mod max_widthu);
end if;
end if;
end if;
end if;
end if; -- wrclk = '1' and wrclk'event
if ((falling_edge(wrclk) and (use_eab = "ON")) and (NOW > 0 ns))
then
if (i_wren_tmp = '1')
then
mem_data(CONV_INTEGER(i_wrptr_tmp) mod max_widthu) := i_data_tmp;
end if;
if (lpm_showahead = "ON")
then
i_q_tmp <= mem_data(CONV_INTEGER(i_rdptr) mod max_widthu);
end if;
end if; -- wrclk = '0' and wrclk event and (use_eab = "ON")) and (NOW > 0 ns)
if (rising_edge(rdclk))
then
if ((aclr = '1') and (not (FEATURE_FAMILY_BASE_STRATIX(intended_device_family) or
FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) or
(use_eab = "OFF")))
then
if (lpm_showahead = "ON")
then
i_q_tmp <= mem_data(0);
else
i_q_tmp <= ZEROS;
end if;
elsif ((i_rden = '1') and (NOW > 0 ns))
then
if ((aclr = '0') and (i_rdptr < max_widthu_minus_one))
then
i_rdptr <= i_rdptr + 1;
else
i_rdptr <= ZEROU;
end if;
if (lpm_showahead = "ON")
then
i_q_tmp <= mem_data(CONV_INTEGER(i_rdptr + 1) mod max_widthu);
else
i_q_tmp <= mem_data(CONV_INTEGER(i_rdptr) mod max_widthu);
end if;
end if;
end if; -- rdclk = '1' and rdclk event
end process; -- aclr, wrclk, rdclk events
i_rden <= rdreq when underflow_checking = "OFF" else
rdreq and not i_rdempty;
i_wren <= wrreq when overflow_checking = "OFF" else
wrreq and not i_wrfull;
-- Delays & DFF Pipes
process (rdclk)
begin
if (falling_edge(rdclk))
then
i_rdenclock <= '0';
elsif (rising_edge(rdclk))
then
if (i_rden = '1')
then
i_rdenclock <= '1';
end if;
end if;
end process; -- rdclk event
process (i_wrptr, i_ws_dbrp)
begin
if (NOW > 0 ns)
then
i_wr_udwn <= i_wrptr - i_ws_dbrp;
end if;
end process; -- i_wrptr, i_ws_dbrp events
process (i_rdptr, i_rs_dbwp)
begin
if (NOW > 0 ns)
then
i_rd_udwn <= i_rs_dbwp - i_rdptr;
end if;
end process; -- i_rdptr, i_rs_dbwp events
-- Outputs
rdempty <= i_rdempty;
rdfull <= i_rdfull;
wrempty <= i_wrempty;
wrfull <= i_wrfull;
rdusedw <= i_rdusedw;
wrusedw <= i_wrusedw;
q <= i_q_tmp;
end behavior; -- lpm_fifo_dc_async
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_fifo_dc
--
-- Description : Dual clocks FIFO
--
-- Limitation :
--
-- Results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
use work.LPM_HINT_EVALUATION.all;
use work.LPM_FIFO_DC_ASYNC;
-- ENTITY DECLARATION
entity LPM_FIFO_DC is
-- GENERIC DECLARATION
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_numwords : natural;
lpm_showahead : string := "OFF";
underflow_checking : string := "ON";
overflow_checking : string := "ON";
lpm_hint : string := "";
lpm_type : string := "LPM_FIFO_DC");
-- PORT DECLARATION
port (
-- INPUT PORT DECLARATION
data : in std_logic_vector(lpm_width-1 downto 0);
rdclock : in std_logic;
wrclock : in std_logic;
aclr : in std_logic := '0';
rdreq : in std_logic;
wrreq : in std_logic;
-- OUTPUT PORT DECLARATION
rdfull : out std_logic;
wrfull : out std_logic;
rdempty : out std_logic;
wrempty : out std_logic;
rdusedw : out std_logic_vector(lpm_widthu-1 downto 0);
wrusedw : out std_logic_vector(lpm_widthu-1 downto 0);
q : out std_logic_vector(lpm_width-1 downto 0));
end LPM_FIFO_DC;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
-- ARCHITECTURE DECLARATION
architecture behavior of LPM_FIFO_DC is
-- FUNCTION DECLARATION
function get_underflow_checking return string is
constant param_value : string := get_parameter_value(LPM_HINT, "UNDERFLOW_CHECKING");
begin
if ( param_value /= "") then
return param_value;
else
return underflow_checking;
end if;
end get_underflow_checking;
function get_overflow_checking return string is
constant param_value : string := get_parameter_value(LPM_HINT, "OVERFLOW_CHECKING");
begin
if ( param_value /= "") then
return param_value;
else
return overflow_checking;
end if;
end get_overflow_checking;
function get_use_eab return string is
constant param_value : string := get_parameter_value(LPM_HINT, "USE_EAB");
begin
if ( param_value /= "") then
return param_value;
else
return "ON";
end if;
end get_use_eab;
function get_intended_device_family return string is
constant param_value : string := get_parameter_value(LPM_HINT, "INTENDED_DEVICE_FAMILY");
begin
if ( param_value /= "") then
return param_value;
else
return "Stratix II";
end if;
end get_intended_device_family;
-- CONSTANT DECLARATION
constant C_UNDERFLOW_CHECKING : string := get_underflow_checking;
constant C_OVERFLOW_CHECKING : string := get_overflow_checking;
constant C_USE_EAB : string := get_use_eab;
constant C_INTENDED_DEVICE_FAMILY : string := get_intended_device_family;
-- SIGNAL DECLARATION
signal i_rdfull_a : std_logic := '0';
signal i_wrfull_a : std_logic := '0';
signal i_rdempty_a : std_logic := '1';
signal i_wrempty_a : std_logic := '1';
signal i_rdfull_s : std_logic := '0';
signal i_wrfull_s : std_logic := '0';
signal i_rdempty_s : std_logic := '1';
signal i_wrempty_s : std_logic := '1';
signal i_rdusedw_a : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_wrusedw_a : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_rdusedw_s : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_wrusedw_s : std_logic_vector(lpm_widthu-1 downto 0) := (OTHERS => '0');
signal i_q_a : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
signal i_q_s : std_logic_vector(lpm_width-1 downto 0) := (OTHERS => '0');
-- COMPONENT DECLARATION
component LPM_FIFO_DC_ASYNC
generic (
lpm_width : natural;
lpm_widthu : natural;
lpm_numwords : natural;
lpm_showahead : string := "OFF";
underflow_checking : string := "ON";
overflow_checking : string := "ON";
use_eab : string := "ON";
intended_device_family : string := "Stratix");
port (
data : in std_logic_vector(lpm_width-1 downto 0);
rdclk : in std_logic;
wrclk : in std_logic;
aclr : in std_logic := '0';
rdreq : in std_logic;
wrreq : in std_logic;
rdfull : out std_logic;
wrfull : out std_logic;
rdempty : out std_logic;
wrempty : out std_logic;
rdusedw : out std_logic_vector(lpm_widthu-1 downto 0);
wrusedw : out std_logic_vector(lpm_widthu-1 downto 0);
q : out std_logic_vector(lpm_width-1 downto 0));
end component;
begin
-- COMPONENT ASSIGNMENTS
ASYNC: LPM_FIFO_DC_ASYNC
generic map (
lpm_width => lpm_width,
lpm_widthu => lpm_widthu,
lpm_numwords => lpm_numwords,
lpm_showahead => lpm_showahead,
underflow_checking => C_UNDERFLOW_CHECKING,
overflow_checking => C_OVERFLOW_CHECKING,
use_eab => C_USE_EAB,
intended_device_family => C_INTENDED_DEVICE_FAMILY)
port map (
data => data,
rdclk => rdclock,
wrclk => wrclock,
aclr => aclr,
rdreq => rdreq,
wrreq => wrreq,
rdfull => i_rdfull_a,
wrfull => i_wrfull_a,
rdempty => i_rdempty_a,
wrempty => i_wrempty_a,
rdusedw => i_rdusedw_a,
wrusedw => i_wrusedw_a,
q => i_q_a);
rdfull <= i_rdfull_a;
wrfull <= i_wrfull_a;
rdempty <= i_rdempty_a;
wrempty <= i_wrempty_a;
rdusedw <= i_rdusedw_a;
wrusedw <= i_wrusedw_a;
q <= i_q_a;
end behavior; -- lpm_fifo_dc
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_inpad
--
-- Description :
--
-- Limitation : n/a
--
-- results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
entity LPM_INpad is
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_type : string := "LPM_INpad";
lpm_hint : string := "UNUSED"
);
port (
pad : in std_logic_vector(lpm_width-1 downto 0);
result : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_INpad;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_INpad is
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
result <= pad;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_outpad
--
-- Description :
--
-- Limitation : n/a
--
-- results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
entity LPM_OUTpad is
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_type : string := "L_OUTpad";
lpm_hint : string := "UNUSED"
);
port (
data : in std_logic_vector(lpm_width-1 downto 0);
pad : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_OUTpad;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_OUTpad is
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
pad <= data;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_bipad
--
-- Description :
--
-- Limitation : n/a
--
-- results Expected:
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
entity LPM_BIpad is
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_type : string := "LPM_BIpad";
lpm_hint : string := "UNUSED"
);
port (
data : in std_logic_vector(lpm_width-1 downto 0);
enable : in std_logic;
result : out std_logic_vector(lpm_width-1 downto 0);
pad : inout std_logic_vector(lpm_width-1 downto 0)
);
end LPM_BIpad;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_BIpad is
signal tmp_pad : std_logic_vector(lpm_width-1 downto 0);
begin
tmp_pad <= pad;
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
process(data, tmp_pad, enable)
begin
if enable = '1' then
pad <= data;
result <= (OTHERS => 'Z');
else
result <= tmp_pad;
pad <= (OTHERS => 'Z');
end if;
end process;
end LPM_SYN;
-- END OF ARCHITECTURE
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 16:31:10 11/14/2015
-- Design Name:
-- Module Name: /home/superus/Vhdl_System_Design_WiSe1516/workspace/idea_rcs1/idea_rcs1/tb_reg_sync.vhd
-- Project Name: idea_rcs1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: reg_sync
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_reg_sync IS
END tb_reg_sync;
ARCHITECTURE behavior OF tb_reg_sync IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT reg_sync
PORT(
D : IN std_logic_vector(15 downto 0);
Q : OUT std_logic_vector(15 downto 0);
en : IN std_logic;
clk : IN std_logic
);
END COMPONENT;
--Inputs
signal D : std_logic_vector(15 downto 0) := (others => '0');
signal en : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal Q : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: reg_sync PORT MAP (
D => D,
Q => Q,
en => en,
clk => clk
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
en <= '0', '1' after 10 ns;
D <= "0101101011110000", "0000000000000000" after 9 ns, "0101101011110000" after 19ns, "0000000000000000" after 29ns;
END;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 16:31:10 11/14/2015
-- Design Name:
-- Module Name: /home/superus/Vhdl_System_Design_WiSe1516/workspace/idea_rcs1/idea_rcs1/tb_reg_sync.vhd
-- Project Name: idea_rcs1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: reg_sync
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_reg_sync IS
END tb_reg_sync;
ARCHITECTURE behavior OF tb_reg_sync IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT reg_sync
PORT(
D : IN std_logic_vector(15 downto 0);
Q : OUT std_logic_vector(15 downto 0);
en : IN std_logic;
clk : IN std_logic
);
END COMPONENT;
--Inputs
signal D : std_logic_vector(15 downto 0) := (others => '0');
signal en : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal Q : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: reg_sync PORT MAP (
D => D,
Q => Q,
en => en,
clk => clk
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
en <= '0', '1' after 10 ns;
D <= "0101101011110000", "0000000000000000" after 9 ns, "0101101011110000" after 19ns, "0000000000000000" after 29ns;
END;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 16:31:10 11/14/2015
-- Design Name:
-- Module Name: /home/superus/Vhdl_System_Design_WiSe1516/workspace/idea_rcs1/idea_rcs1/tb_reg_sync.vhd
-- Project Name: idea_rcs1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: reg_sync
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_reg_sync IS
END tb_reg_sync;
ARCHITECTURE behavior OF tb_reg_sync IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT reg_sync
PORT(
D : IN std_logic_vector(15 downto 0);
Q : OUT std_logic_vector(15 downto 0);
en : IN std_logic;
clk : IN std_logic
);
END COMPONENT;
--Inputs
signal D : std_logic_vector(15 downto 0) := (others => '0');
signal en : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal Q : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: reg_sync PORT MAP (
D => D,
Q => Q,
en => en,
clk => clk
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
en <= '0', '1' after 10 ns;
D <= "0101101011110000", "0000000000000000" after 9 ns, "0101101011110000" after 19ns, "0000000000000000" after 29ns;
END;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Tolga Sel
--
-- Create Date: 16:31:10 11/14/2015
-- Design Name:
-- Module Name: /home/superus/Vhdl_System_Design_WiSe1516/workspace/idea_rcs1/idea_rcs1/tb_reg_sync.vhd
-- Project Name: idea_rcs1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: reg_sync
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_reg_sync IS
END tb_reg_sync;
ARCHITECTURE behavior OF tb_reg_sync IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT reg_sync
PORT(
D : IN std_logic_vector(15 downto 0);
Q : OUT std_logic_vector(15 downto 0);
en : IN std_logic;
clk : IN std_logic
);
END COMPONENT;
--Inputs
signal D : std_logic_vector(15 downto 0) := (others => '0');
signal en : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal Q : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: reg_sync PORT MAP (
D => D,
Q => Q,
en => en,
clk => clk
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
en <= '0', '1' after 10 ns;
D <= "0101101011110000", "0000000000000000" after 9 ns, "0101101011110000" after 19ns, "0000000000000000" after 29ns;
END;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 01:50:56 10/03/2009
-- Design Name:
-- Module Name: TestCPU1_OutPins - Behavioral
-- Project Name: Test CPU 1
-- Target Devices:
-- Tool versions:
-- Description: The output pin controller for Test CPU 1
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TestCPU1_OutPins is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
act : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (15 downto 0);
output_pins : out STD_LOGIC_VECTOR (31 downto 0));
end TestCPU1_OutPins;
architecture Behavioral of TestCPU1_OutPins is
begin
OutPins: process (clock, reset) is
variable opin_reg: STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
begin
if falling_edge(clock) then
if reset = '1' then
opin_reg := (others => '0');
elsif act = '1' then
opin_reg(conv_integer(unsigned(data(4 downto 0)))) := data(5);
end if;
output_pins <= opin_reg;
end if;
end process;
end Behavioral;
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_4 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_4 is
signal val0, val1, val2, val3, min, max , max_out, min_out: std_logic_vector(7 downto 0);
signal max01, max23, max0123, min01, min23, min0123: std_logic_vector(7 downto 0);
begin
val0 <= INPUT_1(31 downto 24 );
val1 <= INPUT_1(23 downto 16 );
val2 <= INPUT_1(15 downto 8 );
val3 <= INPUT_1(7 downto 0 );
min <= INPUT_2(15 downto 8);
max <= INPUT_2(7 downto 0);
compute_max : process(max, val0, val1, val2, val3, max01, max23, max0123)
begin
if(val0 > val1) then
max01 <= val0;
else
max01 <= val1;
end if;
if(val2 > val3) then
max23 <= val2;
else
max23 <= val3;
end if;
if(max01 > max23) then
max0123 <= max01;
else
max0123 <= max23;
end if;
if(max0123 > max) then
max_out <= max0123;
else
max_out <= max;
end if;
end process;
compute_min : process(min, val0, val1, val2, val3, min01, min23, min0123)
begin
if(val0 < val1) then
min01 <= val0;
else
min01 <= val1;
end if;
if(val2 < val3) then
min23 <= val2;
else
min23 <= val3;
end if;
if(min01 < min23) then
min0123 <= min01;
else
min0123 <= min23;
end if;
if(min0123 < min) then
min_out <= min0123;
else
min_out <= min;
end if;
end process;
OUTPUT_1 <= "0000000000000000"&min_out&max_out;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_4 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_4 is
signal val0, val1, val2, val3, min, max , max_out, min_out: std_logic_vector(7 downto 0);
signal max01, max23, max0123, min01, min23, min0123: std_logic_vector(7 downto 0);
begin
val0 <= INPUT_1(31 downto 24 );
val1 <= INPUT_1(23 downto 16 );
val2 <= INPUT_1(15 downto 8 );
val3 <= INPUT_1(7 downto 0 );
min <= INPUT_2(15 downto 8);
max <= INPUT_2(7 downto 0);
compute_max : process(max, val0, val1, val2, val3, max01, max23, max0123)
begin
if(val0 > val1) then
max01 <= val0;
else
max01 <= val1;
end if;
if(val2 > val3) then
max23 <= val2;
else
max23 <= val3;
end if;
if(max01 > max23) then
max0123 <= max01;
else
max0123 <= max23;
end if;
if(max0123 > max) then
max_out <= max0123;
else
max_out <= max;
end if;
end process;
compute_min : process(min, val0, val1, val2, val3, min01, min23, min0123)
begin
if(val0 < val1) then
min01 <= val0;
else
min01 <= val1;
end if;
if(val2 < val3) then
min23 <= val2;
else
min23 <= val3;
end if;
if(min01 < min23) then
min0123 <= min01;
else
min0123 <= min23;
end if;
if(min0123 < min) then
min_out <= min0123;
else
min_out <= min;
end if;
end process;
OUTPUT_1 <= "0000000000000000"&min_out&max_out;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_4 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_4 is
signal val0, val1, val2, val3, min, max , max_out, min_out: std_logic_vector(7 downto 0);
signal max01, max23, max0123, min01, min23, min0123: std_logic_vector(7 downto 0);
begin
val0 <= INPUT_1(31 downto 24 );
val1 <= INPUT_1(23 downto 16 );
val2 <= INPUT_1(15 downto 8 );
val3 <= INPUT_1(7 downto 0 );
min <= INPUT_2(15 downto 8);
max <= INPUT_2(7 downto 0);
compute_max : process(max, val0, val1, val2, val3, max01, max23, max0123)
begin
if(val0 > val1) then
max01 <= val0;
else
max01 <= val1;
end if;
if(val2 > val3) then
max23 <= val2;
else
max23 <= val3;
end if;
if(max01 > max23) then
max0123 <= max01;
else
max0123 <= max23;
end if;
if(max0123 > max) then
max_out <= max0123;
else
max_out <= max;
end if;
end process;
compute_min : process(min, val0, val1, val2, val3, min01, min23, min0123)
begin
if(val0 < val1) then
min01 <= val0;
else
min01 <= val1;
end if;
if(val2 < val3) then
min23 <= val2;
else
min23 <= val3;
end if;
if(min01 < min23) then
min0123 <= min01;
else
min0123 <= min23;
end if;
if(min0123 < min) then
min_out <= min0123;
else
min_out <= min;
end if;
end process;
OUTPUT_1 <= "0000000000000000"&min_out&max_out;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_4 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_4 is
signal val0, val1, val2, val3, min, max , max_out, min_out: std_logic_vector(7 downto 0);
signal max01, max23, max0123, min01, min23, min0123: std_logic_vector(7 downto 0);
begin
val0 <= INPUT_1(31 downto 24 );
val1 <= INPUT_1(23 downto 16 );
val2 <= INPUT_1(15 downto 8 );
val3 <= INPUT_1(7 downto 0 );
min <= INPUT_2(15 downto 8);
max <= INPUT_2(7 downto 0);
compute_max : process(max, val0, val1, val2, val3, max01, max23, max0123)
begin
if(val0 > val1) then
max01 <= val0;
else
max01 <= val1;
end if;
if(val2 > val3) then
max23 <= val2;
else
max23 <= val3;
end if;
if(max01 > max23) then
max0123 <= max01;
else
max0123 <= max23;
end if;
if(max0123 > max) then
max_out <= max0123;
else
max_out <= max;
end if;
end process;
compute_min : process(min, val0, val1, val2, val3, min01, min23, min0123)
begin
if(val0 < val1) then
min01 <= val0;
else
min01 <= val1;
end if;
if(val2 < val3) then
min23 <= val2;
else
min23 <= val3;
end if;
if(min01 < min23) then
min0123 <= min01;
else
min0123 <= min23;
end if;
if(min0123 < min) then
min_out <= min0123;
else
min_out <= min;
end if;
end process;
OUTPUT_1 <= "0000000000000000"&min_out&max_out;
end; --architecture logic
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576)
`protect data_block
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|
`protect begin_protected
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`protect end_protected
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: leon4
-- File: leon4.vhd
-- Author: Cobham Gaisler AB
-- Description: LEON4 types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
use work.leon3.l3_cstat_type;
use work.leon3.cstat_none;
use work.leon3.dsu_astat_type;
use work.leon3.dsu_astat_none;
use work.leon3.l3stat_in_type;
use work.leon3.l3stat_in_none;
use work.leon3.l3_irq_in_type;
use work.leon3.l3_irq_out_type;
use work.leon3.grfpu_in_type;
use work.leon3.grfpu_out_type;
package leon4 is
constant LEON4_VERSION : integer := 0;
type l4_debug_in_type is record
dsuen : std_ulogic; -- DSU enable
denable : std_ulogic; -- diagnostic register access enable
dbreak : std_ulogic; -- debug break-in
step : std_ulogic; -- single step
halt : std_ulogic; -- halt processor
reset : std_ulogic; -- reset processor
dwrite : std_ulogic; -- read/write
daddr : std_logic_vector(23 downto 2); -- diagnostic address
ddata : std_logic_vector(31 downto 0); -- diagnostic data
btrapa : std_ulogic; -- break on IU trap
btrape : std_ulogic; -- break on IU trap
berror : std_ulogic; -- break on IU error mode
bwatch : std_ulogic; -- break on IU watchpoint
bsoft : std_ulogic; -- break on software breakpoint (TA 1)
tenable : std_ulogic;
timer : std_logic_vector(63 downto 0); --
end record;
type l4_debug_out_type is record
data : std_logic_vector(31 downto 0);
crdy : std_ulogic;
dsu : std_ulogic;
dsumode : std_ulogic;
error : std_ulogic;
halt : std_ulogic;
pwd : std_ulogic;
idle : std_ulogic;
ipend : std_ulogic;
icnt : std_ulogic;
fcnt : std_ulogic;
optype : std_logic_vector(5 downto 0); -- instruction type
bpmiss : std_ulogic; -- branch predict miss
istat : l3_cstat_type;
dstat : l3_cstat_type;
wbhold : std_ulogic; -- write buffer hold
su : std_ulogic; -- supervisor state
ducnt : std_ulogic; -- disable timer
end record;
type l4_debug_in_vector is array (natural range <>) of l4_debug_in_type;
type l4_debug_out_vector is array (natural range <>) of l4_debug_out_type;
constant l4_dbgi_none : l4_debug_in_type := ('0', '0', '0', '0', '0', '0',
'0', (others => '0'), (others => '0'), '0', '0', '0', '0', '0', '0',
(others => '0'));
constant l4_dbgo_none : l4_debug_out_type := (X"00000000", '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0', "000000", '0', cstat_none, cstat_none, '0',
'0', '0');
component leon4s
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 16#00000#; -- reset vector address [31:12]
smp : integer range 0 to 31 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0;
wbmask : integer := 0; -- Wide-bus mask
busw : integer := 64; -- AHB/Cache data width (64/128)
netlist : integer := 0;
ft : integer := 0;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l4_debug_in_type;
dbgo : out l4_debug_out_type
);
end component;
component leon4x
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 31 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
clk2x : integer := 0;
scantest : integer := 0;
wbmask : integer := 0; -- Wide-bus mask
busw : integer := 64; -- AHB/Cache data width (64/128)
netlist : integer := 0; -- Use netlist
ft : integer := 0; -- FT option
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
ahbpipe : integer := 0
);
port (
ahbclk : in std_ulogic; -- bus clock
cpuclk : in std_ulogic; -- cpu clock
gcpuclk: in std_ulogic; -- gated cpu clock
fpuclk : in std_ulogic;
hclken : in std_ulogic; -- bus clock enable qualifier
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l4_debug_in_type;
dbgo : out l4_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end component;
component leon4sh
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 31 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0;
wbmask : integer := 0; -- Wide-bus mask
busw : integer := 64; -- AHB/Cache data width (64/128)
netlist : integer := 0;
ft : integer := 0;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l4_debug_in_type;
dbgo : out l4_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end component;
component leon4cg
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart: integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart: integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 16#00000#; -- reset vector address [31:12]
smp : integer range 0 to 31 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0;
wbmask : integer := 0; -- Wide-bus mask
busw : integer := 64; -- AHB/Cache data width (64/128)
netlist : integer := 0;
ft : integer := 0;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l4_debug_in_type;
dbgo : out l4_debug_out_type;
gclk : in std_ulogic
);
end component;
component leon4s2x
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
clk2x : integer := 1;
scantest : integer := 0;
wbmask : integer := 0; -- Wide-bus mask
busw : integer := 64; -- AHB/Cache data width (64/128)
netlist : integer := 0;
ft : integer := 0;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
gclk2 : in std_ulogic;
clk2 : in std_ulogic; -- snoop clock
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l4_debug_in_type;
dbgo : out l4_debug_out_type;
clken : in std_ulogic
);
end component;
component leon4ft
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 63 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 31 := 0; -- support SMP systems
cached : integer := 0; -- cacheability table
scantest : integer := 0;
wbmask : integer := 0; -- Wide-bus mask
busw : integer := 64; -- AHB/Cache data width (64/128)
netlist : integer := 0; -- Netlist option
ft : integer := 0; -- FT option
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l4_debug_in_type;
dbgo : out l4_debug_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type;
gclk : in std_ulogic -- gated clock
);
end component;
type dsu4_in_type is record
enable : std_ulogic;
break : std_ulogic;
end record;
constant dsu4_astat_none : dsu_astat_type := dsu_astat_none;
type dsu4_out_type is record
active : std_ulogic;
tstop : std_ulogic;
pwd : std_logic_vector(15 downto 0);
astat : dsu_astat_type;
end record;
constant dsu4_out_none : dsu4_out_type :=
('0', '0', (others => '0'), dsu_astat_none);
component dsu4
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
bwidth : integer := 64;
ahbpf : integer := 0;
ahbwp : integer := 2;
scantest: integer := 0;
pipedbg : integer range 0 to 1 := 0;
pipeahbt: integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l4_debug_out_vector(0 to NCPU-1);
dbgo : out l4_debug_in_vector(0 to NCPU-1);
dsui : in dsu4_in_type;
dsuo : out dsu4_out_type
);
end component;
component dsu4_2x
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
bwidth : integer := 64;
ahbpf : integer := 0;
ahbwp : integer := 2;
scantest: integer := 0;
pipedbg : integer range 0 to 1 := 0;
pipeahbt: integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l4_debug_out_vector(0 to NCPU-1);
dbgo : out l4_debug_in_vector(0 to NCPU-1);
dsui : in dsu4_in_type;
dsuo : out dsu4_out_type;
hclken : in std_ulogic
);
end component;
component dsu4_mb
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
bwidth : integer := 64;
ahbpf : integer := 0;
ahbwp : integer := 2;
scantest: integer := 0;
pipedbg : integer range 0 to 1 := 0;
pipeahbt: integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
tahbsi : in ahb_slv_in_type;
dbgi : in l4_debug_out_vector(0 to NCPU-1);
dbgo : out l4_debug_in_vector(0 to NCPU-1);
dsui : in dsu4_in_type;
dsuo : out dsu4_out_type
);
end component;
component dsu4x
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
clk2x : integer range 0 to 1 := 0;
bwidth : integer := 64;
ahbpf : integer := 0;
ahbwp : integer := 2;
scantest: integer := 0;
pipedbg : integer := 0;
pipeahbt: integer := 0
);
port (
rst : in std_ulogic;
hclk : in std_ulogic;
cpuclk : in std_ulogic;
fcpuclk: in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
tahbsi : in ahb_slv_in_type;
dbgi : in l4_debug_out_vector(0 to NCPU-1);
dbgo : out l4_debug_in_vector(0 to NCPU-1);
dsui : in dsu4_in_type;
dsuo : out dsu4_out_type;
hclken : in std_ulogic
);
end component;
constant l4stat_in_none : l3stat_in_type := l3stat_in_none;
component l4stat
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncnt : integer range 1 to 64 := 4;
ncpu : integer := 1;
nmax : integer := 0;
lahben : integer := 0;
dsuen : integer := 0;
nextev : integer range 0 to 16 := 0;
apb2en : integer := 0;
pindex2 : integer := 0;
paddr2 : integer := 0;
pmask2 : integer := 16#fff#;
astaten : integer := 0;
selreq : integer := 0;
clatch : integer := 0;
forcer0 : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbsi : in ahb_slv_in_type;
dbgo : in l4_debug_out_vector(0 to NCPU-1);
dsuo : in dsu4_out_type := dsu4_out_none;
stati : in l3stat_in_type := l4stat_in_none;
apb2i : in apb_slv_in_type := apb_slv_in_none;
apb2o : out apb_slv_out_type;
astat : in amba_stat_type := amba_stat_none);
end component;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
entity VOICE_CLOCK is
port(inclk0:in std_logic;
c0,c1:out std_logic);
end entity;
architecture clkx of VOICE_CLOCK is
begin
c0<=inclk0;
c1<=not inclk0;
end clkx;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_c_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:59 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_c_e-rtl-conf-c.vhd,v 1.1 2004/04/06 10:50:39 wig Exp $
-- $Date: 2004/04/06 10:50:39 $
-- $Log: inst_c_e-rtl-conf-c.vhd,v $
-- Revision 1.1 2004/04/06 10:50:39 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_c_e_rtl_conf / inst_c_e
--
configuration inst_c_e_rtl_conf of inst_c_e is
for rtl
-- Generated Configuration
end for;
end inst_c_e_rtl_conf;
--
-- End of Generated Configuration inst_c_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-- $Id: fifo_2c_dram.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: fifo_2c_dram - syn
-- Description: FIFO, two clock domain, distributed RAM based, with
-- enable/busy/valid/hold interface.
--
-- Dependencies: ram_1swar_1ar_gen
-- genlib/gray_cnt_n
-- genlib/gray2bin_gen
--
-- Test bench: tb/tb_fifo_2c_dram
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.35 !! NOT FOR VIVADO !!
-- Note: for usage with Vivado use fifo_2c_dram2
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 424 1.1 use capture+sync flops; reset now glitch free
-- 2011-11-07 421 1.0.2 now numeric_std clean
-- 2007-12-28 107 1.0.1 VAL=0 in cycle after RESETR=1
-- 2007-12-28 106 1.0 Initial version
--
-- Some synthesis results:
-- - 2011-11-13 Rev 424: ise 13.1 for xc3s1000-ft256-4:
-- AWIDTH DWIDTH LUT.l LUT.m LUT.s Flop Slice CLKW CLKR (xst est.)
-- 4 16 41 32 12 38 54 135MHz 115MHz ( 16 words)
-- 5 16 65 64 14 40 80 113MHz 116MHz ( 32 words)
-- - 2007-12-28 Rev 106: ise 8.2.03 for xc3s1000-ft256-4:
-- AWIDTH DWIDTH LUT.l LUT.m Flop CLKW CLKR (xst est.)
-- 4 16 40 32 42 141MHz 165MHz ( 16 words)
-- 5 16 65 64 52 108MHz 108MHz ( 32 words)
-- 6 16 95 128 61 111MHz 113MHz ( 64 words)
-- 7 16 149 256 74 100MHz 96MHz (128 words)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;
use work.memlib.all;
entity fifo_2c_dram is -- fifo, 2 clock, dram based
generic (
AWIDTH : positive := 5; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLKW : in slbit; -- clock (write side)
CLKR : in slbit; -- clock (read side)
RESETW : in slbit; -- W|reset from write side
RESETR : in slbit; -- R|reset from read side
DI : in slv(DWIDTH-1 downto 0); -- W|input data
ENA : in slbit; -- W|write enable
BUSY : out slbit; -- W|write port hold
DO : out slv(DWIDTH-1 downto 0); -- R|output data
VAL : out slbit; -- R|read valid
HOLD : in slbit; -- R|read hold
SIZEW : out slv(AWIDTH-1 downto 0); -- W|number slots to write
SIZER : out slv(AWIDTH-1 downto 0) -- R|number slots to read
);
end fifo_2c_dram;
architecture syn of fifo_2c_dram is
type regw_type is record
raddr_c : slv(AWIDTH-1 downto 0); -- read address (capt from CLKR)
raddr_s : slv(AWIDTH-1 downto 0); -- read address (sync in CLKW)
sizew : slv(AWIDTH-1 downto 0); -- slots to write
busy : slbit; -- busy flag
rstw : slbit; -- resetw active
rstw_sc : slbit; -- resetw (sync-capt from CLKR-CLKW)
rstw_ss : slbit; -- resetw (sync-sync from CLKR-CLKW)
rstr_c : slbit; -- resetr (capt from CLKR)
rstr_s : slbit; -- resetr (sync from CLKR)
end record regw_type;
constant regw_init : regw_type := (
slv(to_unsigned(0,AWIDTH)), -- raddr_c
slv(to_unsigned(0,AWIDTH)), -- raddr_s
slv(to_unsigned(0,AWIDTH)), -- sizew
'0', -- busy
'0','0','0', -- rstw,rstw_sc,rstw_ss
'0','0' -- rstr_c,rstr_s
);
type regr_type is record
waddr_c : slv(AWIDTH-1 downto 0); -- write address (capt from CLKW)
waddr_s : slv(AWIDTH-1 downto 0); -- write address (sync in CLKR)
sizer : slv(AWIDTH-1 downto 0); -- slots to read
val : slbit; -- valid flag
rstr : slbit; -- resetr active
rstr_sc : slbit; -- resetr (sync-capt from CLKW-CLKR)
rstr_ss : slbit; -- resetr (sync-sync from CLKW-CLKR)
rstw_c : slbit; -- resetw (capt from CLKW)
rstw_s : slbit; -- resetw (sync from CLKW)
end record regr_type;
constant regr_init : regr_type := (
slv(to_unsigned(0,AWIDTH)), -- waddr_c
slv(to_unsigned(0,AWIDTH)), -- waddr_s
slv(to_unsigned(0,AWIDTH)), -- sizer
'0', -- val
'0','0','0', -- rstr,rstr_sc,rstr_ss
'0','0' -- rstw_c,rstw_s
);
signal R_REGW : regw_type := regw_init; -- write side state registers
signal N_REGW : regw_type := regw_init; -- next values write side
signal R_REGR : regr_type := regr_init; -- read side state registers
signal N_REGR : regr_type := regr_init; -- next values read side
signal WADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
signal WADDR_BIN : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RADDR_BIN : slv(AWIDTH-1 downto 0) := (others=>'0');
signal WADDR_S_BIN : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RADDR_S_BIN : slv(AWIDTH-1 downto 0) := (others=>'0');
signal GCW_RST : slbit := '0';
signal GCW_CE : slbit := '0';
signal GCR_RST : slbit := '0';
signal GCR_CE : slbit := '0';
begin
RAM : ram_1swar_1ar_gen -- dual ported memory
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH)
port map (
CLK => CLKW,
WE => GCW_CE,
ADDRA => WADDR,
ADDRB => RADDR,
DI => DI,
DOA => open,
DOB => DO
);
GCW : gray_cnt_gen -- gray counter for write address
generic map (
DWIDTH => AWIDTH)
port map (
CLK => CLKW,
RESET => GCW_RST,
CE => GCW_CE,
DATA => WADDR
);
GCR : gray_cnt_gen -- gray counter for read address
generic map (
DWIDTH => AWIDTH)
port map (
CLK => CLKR,
RESET => GCR_RST,
CE => GCR_CE,
DATA => RADDR
);
G2B_WW : gray2bin_gen -- gray->bin for waddr on write side
generic map (DWIDTH => AWIDTH)
port map (DI => WADDR, DO => WADDR_BIN);
G2B_WR : gray2bin_gen -- gray->bin for waddr on read side
generic map (DWIDTH => AWIDTH)
port map (DI => R_REGR.waddr_s, DO => WADDR_S_BIN);
G2B_RR : gray2bin_gen -- gray->bin for raddr on read side
generic map (DWIDTH => AWIDTH)
port map (DI => RADDR, DO => RADDR_BIN);
G2B_RW : gray2bin_gen -- gray->bin for raddr on write side
generic map (DWIDTH => AWIDTH)
port map (DI => R_REGW.raddr_s, DO => RADDR_S_BIN);
--
-- write side --------------------------------------------------------------
--
proc_regw: process (CLKW)
begin
if rising_edge(CLKW) then
R_REGW <= N_REGW;
end if;
end process proc_regw;
proc_nextw: process (R_REGW, RESETW, ENA, R_REGR,
RADDR, RADDR_S_BIN, WADDR_BIN)
variable r : regw_type := regw_init;
variable n : regw_type := regw_init;
variable ibusy : slbit := '0';
variable igcw_ce : slbit := '0';
variable igcw_rst : slbit := '0';
variable isizew : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
r := R_REGW;
n := R_REGW;
isizew := slv(unsigned(RADDR_S_BIN) + unsigned(not WADDR_BIN));
ibusy := '0';
igcw_ce := '0';
igcw_rst := '0';
if unsigned(isizew) = 0 then -- if no free slots
ibusy := '1'; -- next cycle busy=1
end if;
if ENA='1' and r.busy='0' then -- if ena=1 and this cycle busy=0
igcw_ce := '1'; -- write this value
if unsigned(isizew) = 1 then -- if this last free slot
ibusy := '1'; -- next cycle busy=1
end if;
end if;
if RESETW = '1' then -- reset(write side) request
n.rstw := '1'; -- set RSTW flag
elsif r.rstw_ss = '1' then -- request gone and return seen
n.rstw := '0'; -- clear RSTW flag
end if;
if r.rstw='1' and r.rstw_ss='1' then -- RSTW seen on write and read side
igcw_rst := '1'; -- clear write address counter
end if;
if r.rstr_s = '1' then -- RSTR active
igcw_rst := '1'; -- clear write address counter
end if;
if RESETW='1' or r.rstw='1' or r.rstw_ss='1' or r.rstr_s='1'
then -- RESETW or RESETR active
ibusy := '1'; -- signal write side busy
isizew := (others=>'1');
end if;
n.busy := ibusy;
n.sizew := isizew;
n.raddr_c := RADDR; -- data captuture from CLKR
n.raddr_s := r.raddr_c;
n.rstw_sc := R_REGR.rstw_s;
n.rstw_ss := r.rstw_sc;
n.rstr_c := R_REGR.rstr;
n.rstr_s := r.rstr_c;
N_REGW <= n;
GCW_CE <= igcw_ce;
GCW_RST <= igcw_rst;
BUSY <= r.busy;
SIZEW <= r.sizew;
end process proc_nextw;
--
-- read side ---------------------------------------------------------------
--
proc_regr: process (CLKR)
begin
if rising_edge(CLKR) then
R_REGR <= N_REGR;
end if;
end process proc_regr;
proc_nextr: process (R_REGR, RESETR, HOLD, R_REGW,
WADDR, WADDR_S_BIN, RADDR_BIN)
variable r : regr_type := regr_init;
variable n : regr_type := regr_init;
variable ival : slbit := '0';
variable igcr_ce : slbit := '0';
variable igcr_rst : slbit := '0';
variable isizer : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
r := R_REGR;
n := R_REGR;
isizer := slv(unsigned(WADDR_S_BIN) - unsigned(RADDR_BIN));
ival := '1';
igcr_ce := '0';
igcr_rst := '0';
if unsigned(isizer) = 0 then -- if nothing to read
ival := '0'; -- next cycle val=0
end if;
if r.val='1' and HOLD='0' then -- this cycle val=1 and no hold
igcr_ce := '1'; -- retire this value
if unsigned(isizer) = 1 then -- if this is last one
ival := '0'; -- next cycle val=0
end if;
end if;
if RESETR = '1' then -- reset(read side) request
n.rstr := '1'; -- set RSTR flag
elsif r.rstr_ss = '1' then -- request gone and return seen
n.rstr := '0'; -- clear RSTR flag
end if;
if r.rstr='1' and r.rstr_ss='1' then -- RSTR seen on read and write side
igcr_rst := '1'; -- clear read address counter
end if;
if r.rstw_s = '1' then -- RSTW active
igcr_rst := '1'; -- clear read address counter
end if;
if RESETR='1' or r.rstr='1' or r.rstr_ss='1' or r.rstw_s='1'
then -- RESETR or RESETW active
ival := '0'; -- signal read side empty
isizer := (others=>'0');
end if;
n.val := ival;
n.sizer := isizer;
n.waddr_c := WADDR; -- data captuture from CLKW
n.waddr_s := r.waddr_c;
n.rstr_sc := R_REGW.rstr_s;
n.rstr_ss := r.rstr_sc;
n.rstw_c := R_REGW.rstw;
n.rstw_s := r.rstw_c;
N_REGR <= n;
GCR_CE <= igcr_ce;
GCR_RST <= igcr_rst;
VAL <= r.val;
SIZER <= r.sizer;
end process proc_nextr;
end syn;
|
-------------------------------------------------------------------------------
-- file: TOP_EQ.vhd
-- author: Rene Herthel <[email protected]>
-- author: Hauke Sondermann <[email protected]>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-------------------------------------------------------------------------------
-- entity of TOP_EQ.vhd
-------------------------------------------------------------------------------
entity TOP_EQ is
port(
CLK : in std_logic;
ANODES : out std_logic_vector(3 downto 0);
CATHODES : out std_logic_vector(7 downto 0);
NWE : in std_logic;
NE : in std_logic;
NOE : in std_logic;
DATA : inout std_logic_vector(15 downto 0);
RDY : out std_logic;
------------------- OSCILLOPCOPE --------------------
NWE_OUT : out std_logic;
NE_OUT : out std_logic;
NOE_OUT : out std_logic;
RDY_OUT : out std_logic
---------------------- TIMSIM -----------------------
-- ;LOCKED_O : out std_logic
------------------------ SIM ------------------------
-- ;CLK_SYN : in std_logic;
-- CLK_PE : in std_logic;
-- CLK_ORIG : in std_logic;
-- LOCKED : in std_logic
);
end TOP_EQ;
architecture TOP_EQ_ARCH of TOP_EQ is
-------------------------------------------------------------------------------
-- component definition
-------------------------------------------------------------------------------
component FREQ_DIV is
port(
CLK : in std_logic;
RESET_N : in std_logic;
PULSE : out std_logic
);
end component;
component SEVEN_SEG is
port(
CLK : in std_logic;
RESET_N : in std_logic;
CE : in std_logic;
DATA_IN : in std_logic_vector(15 downto 0);
ANODES : out std_logic_vector(3 downto 0);
CATHODES : out std_logic_vector(7 downto 0)
);
end component;
component FSMC is
port (
CLK_SYN : in std_logic;
CLK_PE : in std_logic;
NWE : in std_logic;
NE : in std_logic;
NOE : in std_logic;
RESET_N : in std_logic;
DATA : inout std_logic_vector(15 downto 0);
RDY : out std_logic
);
end component;
component clk_wiz_v3_6
port (
CLK_IN1 : in std_logic;
CLK_SYN : out std_logic;
CLK_PE : out std_logic;
CLK_ORIG : out std_logic;
LOCKED : out std_logic
);
end component;
-------------------------------------------------------------------------------
-- signal definitions
-------------------------------------------------------------------------------
signal PULSE : std_logic;
signal SEVEN_SEG_DATA : std_logic_vector(15 downto 0);
--------------------- PROGRAM -----------------------
signal LOCKED : std_logic;
signal CLK_SYN : std_logic;
signal CLK_PE : std_logic;
signal CLK_ORIG : std_logic;
-----------------------------------------------------
------------------- OSCILLOPCOPE --------------------
signal RDY_INTERNAL : std_logic;
-----------------------------------------------------
begin
SEVEN_SEG_DATA <= DATA;
------------------- OSCILLOPCOPE --------------------
NWE_OUT <= NWE;
NE_OUT <= NE;
NOE_OUT <= NOE;
RDY_OUT <= RDY_INTERNAL;
RDY <= RDY_INTERNAL;
-----------------------------------------------------
---------------------- TIMSIM -----------------------
-- LOCKED_O <= LOCKED;
-----------------------------------------------------
-------------------------------------------------------------------------------
-- instantiations
-------------------------------------------------------------------------------
FREQ_DIV_C : FREQ_DIV
port map (
CLK => CLK_ORIG,
RESET_N => LOCKED,
PULSE => PULSE
);
SEVEN_SEG_C : SEVEN_SEG
port map (
CLK => CLK_ORIG,
RESET_N => LOCKED,
CE => PULSE,
DATA_IN => SEVEN_SEG_DATA,
ANODES => ANODES,
CATHODES => CATHODES
);
FSMC_C : FSMC
port map (
CLK_SYN => CLK_SYN,
CLK_PE => CLK_PE,
NWE => NWE,
NE => NE,
NOE => NOE,
RESET_N => LOCKED,
DATA => DATA,
RDY => RDY_INTERNAL
);
COREGEN : clk_wiz_v3_6
port map (
CLK_IN1 => CLK,
CLK_SYN => CLK_SYN,
CLK_PE => CLK_PE,
CLK_ORIG => CLK_ORIG,
LOCKED => LOCKED
);
end TOP_EQ_ARCH;
|
architecture rtl of fifo is
begin
x <= a and b or c nand d nor e xor f xnor g;
x <= a and b or c nand d nor e xor f xnor g;
end architecture;
|
--------------------------------------------------------------------------------
-- Entity: connector
-- Date:2018-08-05
-- Author: gideon
--
-- Description: This simple module connects two tristate "TTL" buffers
-- This module does not allow external drivers to the net.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity connector is
generic (
g_usedbus : boolean := true;
g_width : natural := 8 );
port (
a_o : in std_logic_vector(g_width-1 downto 0);
a_t : in std_logic_vector(g_width-1 downto 0);
a_i : out std_logic_vector(g_width-1 downto 0);
dbus : in std_logic_vector(g_width-1 downto 0) := (others => '1');
b_o : in std_logic_vector(g_width-1 downto 0);
b_t : in std_logic_vector(g_width-1 downto 0);
b_i : out std_logic_vector(g_width-1 downto 0);
connect : in std_logic );
end entity;
architecture arch of connector is
begin
process(a_o, a_t, b_o, b_t, connect, dbus)
begin
if connect = '0' then
if g_usedbus then
a_i <= dbus;
else
a_i <= a_o or not a_t;
end if;
b_i <= b_o or not b_t;
else -- connected
-- '0' when a_o = '0' and a_t = '1', or b_o = '0' and b_t = '1'
a_i <= not ((not a_o and a_t) or (not b_o and b_t));
b_i <= not ((not a_o and a_t) or (not b_o and b_t));
end if;
end process;
end architecture;
|
entity tb_rotate_testcase is
end tb_rotate_testcase;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_Std.all;
architecture behav of tb_rotate_testcase is
signal in_vec: UNSIGNED(31 downto 0);
signal out_vecl: UNSIGNED(31 downto 0);
signal out_vecr: UNSIGNED(31 downto 0);
begin
dut: entity work.rotate_testcase
port map (in_vec, out_Vecl, out_vecr);
process
begin
in_vec <= x"1234_abcd";
wait for 1 ns;
-- report to_hstring(out_vecr);
assert out_vecl = x"2469579a" severity failure;
assert out_vecr = x"891a55e6" severity failure;
wait;
end process;
end behav;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2cmst
-- File: i2cmst.vhd
-- Author: Jan Andersson - Gaisler Research
-- Contact: [email protected]
-- Description:
--
-- APB interface to OpenCores I2C-master. This is an GRLIB AMBA wrapper
-- that instantiates the byte- and bit-controller of the OpenCores I2C
-- master (OC core developed by Richard Herveille, [email protected]).
-- The OC byte- and bit-controller are located under lib/opencores/i2c
--
-- The original master had a WISHBONE interface with registers
-- aligned at byte boundaries. This wrapper has a slighly different
-- alignment of the registers, and also (optionally) adds a filter
-- filter register (FR):
--
-- +------------+--------------------------------------+
-- | Offset | Bits in word |
-- | |---------+---------+---------+--------+
-- | | 31 - 24 | 23 - 16 | 15 - 8 | 7 - 0 |
-- +------------+---------+---------+---------+--------+
-- | 0x00 | 0x00 | 0x00 | PRERhi | PRERlo |
-- | 0x04 | 0x00 | 0x00 | 0x00 | CTR |
-- | 0x08 | 0x00 | 0x00 | 0x00 | TXR |
-- | 0x08 | 0x00 | 0x00 | 0x00 | RXR |
-- | 0x0C | 0x00 | 0x00 | 0x00 | CR |
-- | 0x0C | 0x00 | 0x00 | 0x00 | SR |
-- | 0x10 | FR |
-- +------------+---------+---------+---------+--------+
--
-- Revision 1 of this core also sets the TIP bit when STO is set.
--
-- Revision 2 of this core adds a filter generic to adjust the low pass filter
--
-- Revision 3 of this core adds yet another filter generic that can be set to
-- make the filter soft configurable.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.i2c.all;
library opencores;
use opencores.i2coc.all;
entity i2cmst is
generic (
-- APB generics
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0; -- interrupt index
oepol : integer range 0 to 1 := 0; -- output enable polarity
filter : integer range 2 to 512 := 2; -- filter bit size
dynfilt : integer range 0 to 1 := 0);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end entity i2cmst;
architecture rtl of i2cmst is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant I2CMST_REV : integer := 3;
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_I2CMST, 0, I2CMST_REV, pirq),
1 => apb_iobar(paddr, pmask));
constant PRER_addr : std_logic_vector(7 downto 2) := "000000";
constant CTR_addr : std_logic_vector(7 downto 2) := "000001";
constant TXR_addr : std_logic_vector(7 downto 2) := "000010";
constant RXR_addr : std_logic_vector(7 downto 2) := "000010";
constant CR_addr : std_logic_vector(7 downto 2) := "000011";
constant SR_addr : std_logic_vector(7 downto 2) := "000011";
constant FR_addr : std_logic_vector(7 downto 2) := "000100";
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
-- Register interface
type ctrl_reg_type is record -- Control register
en : std_ulogic;
ien : std_ulogic;
end record;
type cmd_reg_type is record -- Command register
sta : std_ulogic;
sto : std_ulogic;
rd : std_ulogic;
wr : std_ulogic;
ack : std_ulogic;
end record;
type sts_reg_type is record -- Status register
rxack : std_ulogic;
busy : std_ulogic;
al : std_ulogic;
tip : std_ulogic;
ifl : std_ulogic;
end record;
-- Core registers
type i2c_reg_type is record
-- i2c registers
prer : std_logic_vector(15 downto 0); -- clock prescale register
ctrl : ctrl_reg_type; -- control register
txr : std_logic_vector(7 downto 0); -- transmit register
cmd : cmd_reg_type; -- command register
sts : sts_reg_type; -- status register
filt : std_logic_vector((filter-1)*dynfilt downto 0); -- filter register
--
irq : std_ulogic;
end record;
-- Signals to and from byte controller block
signal rxr : std_logic_vector(7 downto 0); -- Receive register
signal done : std_logic; -- Signals completion of command
signal rxack : std_logic; -- Received acknowledge
signal busy : std_logic; -- I2C core busy
signal al : std_logic; -- Aribitration lost
signal irst : std_ulogic; -- Internal, negated reset signal
signal iscloen : std_ulogic; -- Internal SCL output enable
signal isdaoen : std_ulogic; -- Internal SDA output enable
-- Register interface
signal r, rin : i2c_reg_type;
signal vcc : std_logic;
begin
-- Byte Controller from OpenCores I2C master,
-- by Richard Herveille ([email protected]). The asynchronous
-- reset is tied to '1'. Only the synchronous reset is used.
vcc <= '1';
byte_ctrl: i2c_master_byte_ctrl
generic map (
filter => filter,
dynfilt => dynfilt)
port map (
clk => clk,
rst => irst,
nReset => vcc,
ena => r.ctrl.en,
clk_cnt => r.prer,
start => r.cmd.sta,
stop => r.cmd.sto,
read => r.cmd.rd,
write => r.cmd.wr,
ack_in => r.cmd.ack,
din => r.txr,
filt => r.filt,
cmd_ack => done,
ack_out => rxack,
i2c_busy => busy,
i2c_al => al,
dout => rxr,
scl_i => i2ci.scl,
scl_o => i2co.scl,
scl_oen => iscloen,
sda_i => i2ci.sda,
sda_o => i2co.sda,
sda_oen => isdaoen);
-- OC I2C logic has active high reset.
irst <= not rstn;
i2co.enable <= r.ctrl.en;
-- Fix output enable polarity
soepol0: if oepol = 0 generate
i2co.scloen <= iscloen;
i2co.sdaoen <= isdaoen;
end generate soepol0;
soepol1: if oepol /= 0 generate
i2co.scloen <= not iscloen;
i2co.sdaoen <= not isdaoen;
end generate soepol1;
comb: process (r, rstn, rxr, rxack, busy, al, done, apbi)
variable v : i2c_reg_type;
variable irq : std_logic_vector((NAHBIRQ-1) downto 0);
variable apbaddr : std_logic_vector(7 downto 2);
variable apbout : std_logic_vector(31 downto 0);
begin -- process comb
v := r; v.irq := '0'; irq := (others=>'0'); irq(pirq) := r.irq;
apbaddr := apbi.paddr(7 downto 2); apbout := (others => '0');
-- Command done or arbitration lost, clear command register
if (done or al) = '1' then
v.cmd := ('0', '0', '0', '0', '0');
end if;
-- Update status register
v.sts := (rxack => rxack,
busy => busy,
al => al or (r.sts.al and not r.cmd.sta),
tip => r.cmd.rd or r.cmd.wr or r.cmd.sto,
ifl => done or al or r.sts.ifl);
v.irq := (done or al) and r.ctrl.ien;
-- read registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case apbaddr is
when PRER_addr =>
apbout(15 downto 0) := r.prer;
when CTR_addr =>
apbout(7 downto 6) := r.ctrl.en & r.ctrl.ien;
when RXR_addr =>
apbout(7 downto 0) := rxr;
when SR_addr =>
apbout(7 downto 5) := r.sts.rxack & r.sts.busy & r.sts.al;
apbout(1 downto 0) := r.sts.tip & r.sts.ifl;
when FR_addr =>
if dynfilt /= 0 then apbout(r.filt'range) := r.filt; end if;
when others => null;
end case;
end if;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbaddr is
when PRER_addr => v.prer := apbi.pwdata(15 downto 0);
when CTR_addr => v.ctrl.en := apbi.pwdata(7);
v.ctrl.ien := apbi.pwdata(6);
when TXR_addr => v.txr := apbi.pwdata(7 downto 0);
when CR_addr =>
-- Check that core is enabled and that WR and RD has been cleared
-- before accepting new command.
if (r.ctrl.en and not (r.cmd.wr or r.cmd.rd)) = '1' then
v.cmd.sta := apbi.pwdata(7);
v.cmd.sto := apbi.pwdata(6);
v.cmd.rd := apbi.pwdata(5);
v.cmd.wr := apbi.pwdata(4);
v.cmd.ack := apbi.pwdata(3);
end if;
-- Bit 0 of CR is interrupt acknowledge. The core will only pulse one
-- interrupt per irq event. Software does not have to clear the
-- interrupt flag...
if apbi.pwdata(0) = '1' then
v.sts.ifl := '0';
end if;
when FR_addr =>
if dynfilt /= 0 then v.filt := apbi.pwdata(r.filt'range); end if;
when others => null;
end case;
end if;
if rstn = '0' then
v.prer := (others => '1');
v.ctrl := ('0', '0');
v.txr := (others => '0');
v.cmd := ('0','0','0','0', '0');
v.sts := ('0','0','0','0', '0');
if dynfilt /= 0 then v.filt := (others => '1'); end if;
end if;
if dynfilt = 0 then v.filt := (others => '0'); end if;
-- Update registers
rin <= v;
-- Update outputs
apbo.prdata <= apbout;
apbo.pirq <= irq;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
end process comb;
reg: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"i2cmst" & tost(pindex) & ": AMBA Wrapper for OC I2C-master rev " &
tost(I2CMST_REV) & ", irq " & tost(pirq));
-- pragma translate_on
end architecture rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: apbctrl
-- File: apbctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AMBA AHB/APB bridge with plug&play support
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
entity apbctrldp is
generic (
hindex0 : integer := 0;
haddr0 : integer := 0;
hmask0 : integer := 16#fff#;
hindex1 : integer := 0;
haddr1 : integer := 0;
hmask1 : integer := 16#fff#;
nslaves : integer range 1 to NAPBSLV := NAPBSLV;
wprot : integer range 0 to 1 := 0;
debug : integer range 0 to 2 := 2;
icheck : integer range 0 to 1 := 1;
enbusmon : integer range 0 to 1 := 0;
asserterr : integer range 0 to 1 := 0;
assertwarn : integer range 0 to 1 := 0;
pslvdisable : integer := 0;
mcheck : integer range 0 to 1 := 1;
ccheck : integer range 0 to 1 := 1
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahb0i : in ahb_slv_in_type;
ahb0o : out ahb_slv_out_type;
ahb1i : in ahb_slv_in_type;
ahb1o : out ahb_slv_out_type;
apbi : out apb_slv_in_vector;
apbo : in apb_slv_out_vector;
wp : in std_logic_vector(0 to 1) := (others => '0');
wpv : in std_logic_vector((256*2)-1 downto 0) := (others => '0')
);
end;
architecture struct of apbctrldp is
signal lahbi : ahb_slv_in_vector_type(0 to 1);
signal lahbo : ahb_slv_out_vector_type(0 to 1);
begin
lahbi(0) <= ahb0i;
lahbi(1) <= ahb1i;
ahb0o <= lahbo(0);
ahb1o <= lahbo(1);
apbx : apbctrlx
generic map(
hindex0 => hindex0,
haddr0 => haddr0,
hmask0 => hmask0,
hindex1 => hindex1,
haddr1 => haddr1,
hmask1 => hmask1,
nslaves => nslaves,
nports => 2,
wprot => wprot,
debug => debug,
icheck => icheck,
enbusmon => enbusmon,
asserterr => asserterr,
assertwarn => assertwarn,
pslvdisable => pslvdisable,
mcheck => mcheck,
ccheck => ccheck)
port map(
rst => rst,
clk => clk,
ahbi => lahbi,
ahbo => lahbo,
apbi => apbi,
apbo => apbo,
wp => wp,
wpv => wpv);
end;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity gain is
generic ( k : real := 1.0 ); -- gain multiplier
port ( quantity input : in real;
quantity output : out real );
end entity gain;
----------------------------------------------------------------
architecture simple of gain is
begin
output == k * input;
end architecture simple;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity gain is
generic ( k : real := 1.0 ); -- gain multiplier
port ( quantity input : in real;
quantity output : out real );
end entity gain;
----------------------------------------------------------------
architecture simple of gain is
begin
output == k * input;
end architecture simple;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity gain is
generic ( k : real := 1.0 ); -- gain multiplier
port ( quantity input : in real;
quantity output : out real );
end entity gain;
----------------------------------------------------------------
architecture simple of gain is
begin
output == k * input;
end architecture simple;
|
--
-- Taken from rtl/riverlib/core/stacktrbuf.vhd of https://github.com/sergeykhbr/riscv_vhdl
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Stack trace buffer on hardware level.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity StackTraceBuffer is
generic (
abits : integer := 5;
dbits : integer := 64
);
port (
i_clk : in std_logic;
i_raddr : in std_logic_vector(abits-1 downto 0);
o_rdata : out std_logic_vector(dbits-1 downto 0);
i_we : in std_logic;
i_waddr : in std_logic_vector(abits-1 downto 0);
i_wdata : in std_logic_vector(dbits-1 downto 0)
);
end;
architecture arch_StackTraceBuffer of StackTraceBuffer is
type ram_type is array ((2**abits)-1 downto 0) of std_logic_vector (dbits-1 downto 0);
signal stackbuf : ram_type;
signal raddr : std_logic_vector(abits-1 downto 0);
begin
-- registers:
regs : process(i_clk) begin
if rising_edge(i_clk) then
if i_we = '1' then
stackbuf(conv_integer(i_waddr)) <= i_wdata;
end if;
raddr <= i_raddr;
end if;
end process;
o_rdata <= stackbuf(conv_integer(raddr));
end;
|
--
-- Taken from rtl/riverlib/core/stacktrbuf.vhd of https://github.com/sergeykhbr/riscv_vhdl
--
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Stack trace buffer on hardware level.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity StackTraceBuffer is
generic (
abits : integer := 5;
dbits : integer := 64
);
port (
i_clk : in std_logic;
i_raddr : in std_logic_vector(abits-1 downto 0);
o_rdata : out std_logic_vector(dbits-1 downto 0);
i_we : in std_logic;
i_waddr : in std_logic_vector(abits-1 downto 0);
i_wdata : in std_logic_vector(dbits-1 downto 0)
);
end;
architecture arch_StackTraceBuffer of StackTraceBuffer is
type ram_type is array ((2**abits)-1 downto 0) of std_logic_vector (dbits-1 downto 0);
signal stackbuf : ram_type;
signal raddr : std_logic_vector(abits-1 downto 0);
begin
-- registers:
regs : process(i_clk) begin
if rising_edge(i_clk) then
if i_we = '1' then
stackbuf(conv_integer(i_waddr)) <= i_wdata;
end if;
raddr <= i_raddr;
end if;
end process;
o_rdata <= stackbuf(conv_integer(raddr));
end;
|
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