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`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2039.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02039ent IS
END c07s02b04x00p01n01i02039ent;
ARCHITECTURE c07s02b04x00p01n01i02039arch OF c07s02b04x00p01n01i02039ent IS
BEGIN
TESTING: PROCESS
variable BOOLV : BOOLEAN := FALSE;
BEGIN
BOOLV := BOOLV - FALSE;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02039 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02039arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2039.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02039ent IS
END c07s02b04x00p01n01i02039ent;
ARCHITECTURE c07s02b04x00p01n01i02039arch OF c07s02b04x00p01n01i02039ent IS
BEGIN
TESTING: PROCESS
variable BOOLV : BOOLEAN := FALSE;
BEGIN
BOOLV := BOOLV - FALSE;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02039 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02039arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2039.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02039ent IS
END c07s02b04x00p01n01i02039ent;
ARCHITECTURE c07s02b04x00p01n01i02039arch OF c07s02b04x00p01n01i02039ent IS
BEGIN
TESTING: PROCESS
variable BOOLV : BOOLEAN := FALSE;
BEGIN
BOOLV := BOOLV - FALSE;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02039 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02039arch;
|
-------------------------------------------------------------------------------
--! @file dpRamSplxNbe-e.vhd
--
--! @brief Simplex Dual Port Ram without byteenables entity
--
--! @details This is the Simplex DPRAM without byteenables entity.
--! The DPRAM has one write and one read port only.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity dpRamSplxNbe is
generic (
--! Word width [bit]
gWordWidth : natural := 16;
--! Number of words
gNumberOfWords : natural := 1024;
--! Word width [bit]
--! Initialization file
gInitFile : string := "UNUSED"
);
port (
-- PORT A
--! Clock of port A
iClk_A : in std_logic;
--! Enable of port A
iEnable_A : in std_logic;
--! Write enable of port A
iWriteEnable_A : in std_logic;
--! Address of port A
iAddress_A : in std_logic_vector(logDualis(gNumberOfWords)-1 downto 0);
--! Writedata of port A
iWritedata_A : in std_logic_vector(gWordWidth-1 downto 0);
-- PORT B
--! Clock of port B
iClk_B : in std_logic;
--! Enable of port B
iEnable_B : in std_logic;
--! Address of port B
iAddress_B : in std_logic_vector(logDualis(gNumberOfWords)-1 downto 0);
--! Readdata of port B
oReaddata_B : out std_logic_vector(gWordWidth-1 downto 0)
);
end dpRamSplxNbe;
|
----------------------------------------------------------------------------------
--
-- full_tb.vhd
--
-- (c) 2017
-- N. Huesser
-- R. Frey
--
----------------------------------------------------------------------------------
--
-- A testbench to test the multiplexer with real inputs.
--
----------------------------------------------------------------------------------
library UNISIM;
use UNISIM.VCOMPONENTS.all;
library UNIMACRO;
use UNIMACRO.VCOMPONENTS.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.math_real.all;
entity full_tb is
end full_tb;
architecture Behavioral of full_tb is
signal tbClkxC: std_logic := '0';
signal tbRstxRB: std_logic := '0';
signal tbSelectxDI: std_logic_vector(1 downto 0) := (others => '0');
signal tbData1xDI: std_logic_vector(31 downto 0) := (0 => '1', others => '0');
signal tbData2xDI: std_logic_vector(31 downto 0) := (1 => '1', others => '0');
signal tbDataxDO: std_logic_vector(31 downto 0);
begin
-- generate clock
tbClkxC <= not tbClkxC after 1ns;
DUT : entity work.multiplexer
port map (
ClkxCI => tbClkxC,
RstxRBI => tbRstxRB,
SelectxDI => tbSelectxDI,
Data1xDI => tbData1xDI,
Data2xDI => tbData2xDI,
DataxDO => tbDataxDO
);
process
begin
-- write chain of events here
tbRstxRB <= '0';
wait until rising_edge(tbClkxC);
wait until rising_edge(tbClkxC);
tbRstxRB <= '1';
-- wait 3 clk cycles
for i in 0 to 3 loop
wait until rising_edge(tbClkxC);
end loop;
tbSelectxDI <= (0 => '1', others => '0');
-- wait 3 clk cycles
for i in 0 to 3 loop
wait until rising_edge(tbClkxC);
end loop;
tbSelectxDI <= (1 => '1', 0 => '0', others => '0');
-- wait 3 clk cycles
for i in 0 to 3 loop
wait until rising_edge(tbClkxC);
end loop;
tbSelectxDI <= (1 => '1', 0 => '1', others => '0');
wait;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity iec_processor is
generic (
g_mhz : natural := 50);
port (
clock : in std_logic;
reset : in std_logic;
-- instruction ram interface
instr_addr : out unsigned(8 downto 0);
instr_en : out std_logic;
instr_data : in std_logic_vector(29 downto 0);
-- software fifo interface
up_fifo_full : in std_logic;
up_fifo_put : out std_logic;
up_fifo_din : out std_logic_vector(8 downto 0);
down_fifo_empty : in std_logic;
down_fifo_get : out std_logic;
down_fifo_flush : out std_logic;
down_fifo_dout : in std_logic_vector(8 downto 0);
irq_event : out std_logic;
clk_o : out std_logic;
clk_i : in std_logic;
data_o : out std_logic;
data_i : in std_logic;
atn_o : out std_logic;
atn_i : in std_logic;
srq_o : out std_logic;
srq_i : in std_logic );
attribute opt_mode : string;
attribute opt_mode of iec_processor: entity is "area";
end iec_processor;
architecture mixed of iec_processor is
constant c_opc_load : std_logic_vector(3 downto 0) := X"0";
constant c_opc_pop : std_logic_vector(3 downto 0) := X"1";
constant c_opc_pushc : std_logic_vector(3 downto 0) := X"2";
constant c_opc_pushd : std_logic_vector(3 downto 0) := X"3";
constant c_opc_sub : std_logic_vector(3 downto 0) := X"4";
constant c_opc_copy_bit : std_logic_vector(3 downto 0) := X"5";
constant c_opc_irq : std_logic_vector(3 downto 0) := X"6";
constant c_opc_ret : std_logic_vector(3 downto 0) := X"7";
constant c_opc_if : std_logic_vector(3 downto 0) := X"8";
constant c_opc_clrstack : std_logic_vector(3 downto 0) := X"9";
constant c_opc_reset_st : std_logic_vector(3 downto 0) := X"D";
constant c_opc_reset_drv: std_logic_vector(3 downto 0) := X"E";
constant c_opc_wait : std_logic_vector(3 downto 0) := X"C";
signal inputs : std_logic_vector(3 downto 0);
signal inputs_raw : std_logic_vector(3 downto 0);
signal timer : unsigned(11 downto 0);
signal pc : unsigned(instr_addr'range);
signal pc_ret_std : std_logic_vector(instr_addr'range);
signal pop, push : std_logic;
signal presc : integer range 0 to g_mhz;
signal timer_done : std_logic;
signal atn_i_d : std_logic;
signal valid_reg : std_logic := '0';
signal ctrl_reg : std_logic := '0';
signal timeout_reg : std_logic := '0';
signal flush_stack : std_logic;
type t_state is (idle, get_inst, decode, wait_true);
signal state : t_state;
signal instruction : std_logic_vector(29 downto 0);
alias a_invert : std_logic is instruction(29);
alias a_select : std_logic_vector( 4 downto 0) is instruction(28 downto 24);
alias a_opcode : std_logic_vector( 3 downto 0) is instruction(23 downto 20);
alias a_operand : std_logic_vector(11 downto 0) is instruction(19 downto 8);
alias a_mask : std_logic_vector( 3 downto 0) is instruction(7 downto 4);
alias a_value : std_logic_vector( 3 downto 0) is instruction(3 downto 0);
alias a_databyte : std_logic_vector( 7 downto 0) is instruction(7 downto 0);
signal input_vector : std_logic_vector(31 downto 0);
signal selected_bit : std_logic;
signal out_vector : std_logic_vector(19 downto 0);
alias a_drivers : std_logic_vector(3 downto 0) is out_vector(19 downto 16);
alias a_irq_enable : std_logic is out_vector(8);
alias a_status : std_logic_vector(7 downto 0) is out_vector(15 downto 8);
alias a_data_reg : std_logic_vector(7 downto 0) is out_vector(7 downto 0);
begin
clk_o <= a_drivers(0);
data_o <= a_drivers(1);
atn_o <= a_drivers(2);
srq_o <= a_drivers(3);
inputs_raw <= srq_i & atn_i & data_i & clk_i;
inputs <= std_logic_vector(to_01(unsigned(inputs_raw)));
input_vector(31 downto 30) <= "10";
input_vector(29) <= ctrl_reg;
input_vector(28) <= valid_reg;
input_vector(27) <= timeout_reg;
input_vector(26) <= up_fifo_full;
input_vector(25) <= '1' when (inputs and a_mask) = a_value else '0';
input_vector(24) <= '1' when (a_data_reg = a_databyte) else '0';
input_vector(23 downto 20) <= inputs;
input_vector(19 downto 16) <= a_drivers;
input_vector(15 downto 8) <= a_status;
input_vector(7 downto 0) <= a_data_reg;
selected_bit <= input_vector(to_integer(unsigned(a_select))) xor a_invert;
instr_addr <= pc;
instr_en <= '1' when (state = get_inst) else '0';
instruction <= instr_data;
process(clock)
variable v_bit : std_logic;
begin
if rising_edge(clock) then
up_fifo_put <= '0';
down_fifo_get <= '0';
down_fifo_flush <= '0';
irq_event <= '0';
flush_stack <= '0';
if presc = 0 then
if timer = 1 then
timer_done <= '1';
end if;
if timer /= 0 then
timer <= timer - 1;
end if;
presc <= g_mhz-1;
else
presc <= presc - 1;
end if;
case state is
when idle =>
null;
when get_inst =>
pc <= pc + 1;
state <= decode;
when decode =>
timer_done <= '0';
timer <= unsigned(a_operand);
-- presc <= 0;
state <= get_inst;
case a_opcode is
when c_opc_load =>
a_data_reg <= a_databyte;
when c_opc_reset_st =>
a_status <= X"01";
when c_opc_reset_drv =>
a_drivers <= "1111";
when c_opc_irq =>
irq_event <= '1';
when c_opc_pushc =>
if up_fifo_full='0' then
up_fifo_din <= '1' & a_data_reg;
up_fifo_put <= '1';
else
state <= decode;
end if;
when c_opc_pushd =>
if up_fifo_full='0' then
up_fifo_din <= '0' & a_data_reg;
up_fifo_put <= '1';
else
state <= decode;
end if;
when c_opc_pop =>
a_data_reg <= down_fifo_dout(7 downto 0);
ctrl_reg <= down_fifo_dout(8);
valid_reg <= not down_fifo_empty;
if down_fifo_empty='0' then
down_fifo_get <= '1';
elsif a_databyte(0)='0' then -- empty and non-block bit not set
state <= decode;
end if;
when c_opc_copy_bit =>
out_vector(to_integer(unsigned(a_databyte(4 downto 0)))) <= selected_bit;
when c_opc_if =>
if selected_bit='1' then
pc <= unsigned(a_operand(pc'range));
end if;
when c_opc_wait =>
timeout_reg <= '0';
state <= wait_true;
when c_opc_sub =>
-- pc_ret <= pc; (will be pushed)
pc <= unsigned(a_operand(pc'range));
when c_opc_ret =>
pc <= unsigned(pc_ret_std);
when c_opc_clrstack =>
flush_stack <= '1';
when others =>
null;
end case;
when wait_true =>
if timer_done='1' then
state <= get_inst;
timeout_reg <= '1';
elsif selected_bit='1' then
state <= get_inst;
end if;
when others =>
null;
end case;
atn_i_d <= atn_i;
if atn_i='0' and atn_i_d/='0' and a_irq_enable='1' then
down_fifo_flush <= '1';
pc <= to_unsigned(1, pc'length);
state <= get_inst;
end if;
if reset='1' then
state <= get_inst;
pc <= (others => '0');
out_vector <= X"F0000";
end if;
end if;
end process;
push <= '1' when (state = decode) and (a_opcode = c_opc_sub) else '0';
pop <= '1' when (state = decode) and (a_opcode = c_opc_ret) else '0';
i_stack: entity work.distributed_stack
generic map (
width => pc'length,
simultaneous_pushpop => false )
port map (
clock => clock,
reset => reset,
pop => pop,
push => push,
flush => flush_stack,
data_in => std_logic_vector(pc),
data_out => pc_ret_std,
full => open,
data_valid => open );
end mixed;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity iec_processor is
generic (
g_mhz : natural := 50);
port (
clock : in std_logic;
reset : in std_logic;
-- instruction ram interface
instr_addr : out unsigned(8 downto 0);
instr_en : out std_logic;
instr_data : in std_logic_vector(29 downto 0);
-- software fifo interface
up_fifo_full : in std_logic;
up_fifo_put : out std_logic;
up_fifo_din : out std_logic_vector(8 downto 0);
down_fifo_empty : in std_logic;
down_fifo_get : out std_logic;
down_fifo_flush : out std_logic;
down_fifo_dout : in std_logic_vector(8 downto 0);
irq_event : out std_logic;
clk_o : out std_logic;
clk_i : in std_logic;
data_o : out std_logic;
data_i : in std_logic;
atn_o : out std_logic;
atn_i : in std_logic;
srq_o : out std_logic;
srq_i : in std_logic );
attribute opt_mode : string;
attribute opt_mode of iec_processor: entity is "area";
end iec_processor;
architecture mixed of iec_processor is
constant c_opc_load : std_logic_vector(3 downto 0) := X"0";
constant c_opc_pop : std_logic_vector(3 downto 0) := X"1";
constant c_opc_pushc : std_logic_vector(3 downto 0) := X"2";
constant c_opc_pushd : std_logic_vector(3 downto 0) := X"3";
constant c_opc_sub : std_logic_vector(3 downto 0) := X"4";
constant c_opc_copy_bit : std_logic_vector(3 downto 0) := X"5";
constant c_opc_irq : std_logic_vector(3 downto 0) := X"6";
constant c_opc_ret : std_logic_vector(3 downto 0) := X"7";
constant c_opc_if : std_logic_vector(3 downto 0) := X"8";
constant c_opc_clrstack : std_logic_vector(3 downto 0) := X"9";
constant c_opc_reset_st : std_logic_vector(3 downto 0) := X"D";
constant c_opc_reset_drv: std_logic_vector(3 downto 0) := X"E";
constant c_opc_wait : std_logic_vector(3 downto 0) := X"C";
signal inputs : std_logic_vector(3 downto 0);
signal inputs_raw : std_logic_vector(3 downto 0);
signal timer : unsigned(11 downto 0);
signal pc : unsigned(instr_addr'range);
signal pc_ret_std : std_logic_vector(instr_addr'range);
signal pop, push : std_logic;
signal presc : integer range 0 to g_mhz;
signal timer_done : std_logic;
signal atn_i_d : std_logic;
signal valid_reg : std_logic := '0';
signal ctrl_reg : std_logic := '0';
signal timeout_reg : std_logic := '0';
signal flush_stack : std_logic;
type t_state is (idle, get_inst, decode, wait_true);
signal state : t_state;
signal instruction : std_logic_vector(29 downto 0);
alias a_invert : std_logic is instruction(29);
alias a_select : std_logic_vector( 4 downto 0) is instruction(28 downto 24);
alias a_opcode : std_logic_vector( 3 downto 0) is instruction(23 downto 20);
alias a_operand : std_logic_vector(11 downto 0) is instruction(19 downto 8);
alias a_mask : std_logic_vector( 3 downto 0) is instruction(7 downto 4);
alias a_value : std_logic_vector( 3 downto 0) is instruction(3 downto 0);
alias a_databyte : std_logic_vector( 7 downto 0) is instruction(7 downto 0);
signal input_vector : std_logic_vector(31 downto 0);
signal selected_bit : std_logic;
signal out_vector : std_logic_vector(19 downto 0);
alias a_drivers : std_logic_vector(3 downto 0) is out_vector(19 downto 16);
alias a_irq_enable : std_logic is out_vector(8);
alias a_status : std_logic_vector(7 downto 0) is out_vector(15 downto 8);
alias a_data_reg : std_logic_vector(7 downto 0) is out_vector(7 downto 0);
begin
clk_o <= a_drivers(0);
data_o <= a_drivers(1);
atn_o <= a_drivers(2);
srq_o <= a_drivers(3);
inputs_raw <= srq_i & atn_i & data_i & clk_i;
inputs <= std_logic_vector(to_01(unsigned(inputs_raw)));
input_vector(31 downto 30) <= "10";
input_vector(29) <= ctrl_reg;
input_vector(28) <= valid_reg;
input_vector(27) <= timeout_reg;
input_vector(26) <= up_fifo_full;
input_vector(25) <= '1' when (inputs and a_mask) = a_value else '0';
input_vector(24) <= '1' when (a_data_reg = a_databyte) else '0';
input_vector(23 downto 20) <= inputs;
input_vector(19 downto 16) <= a_drivers;
input_vector(15 downto 8) <= a_status;
input_vector(7 downto 0) <= a_data_reg;
selected_bit <= input_vector(to_integer(unsigned(a_select))) xor a_invert;
instr_addr <= pc;
instr_en <= '1' when (state = get_inst) else '0';
instruction <= instr_data;
process(clock)
variable v_bit : std_logic;
begin
if rising_edge(clock) then
up_fifo_put <= '0';
down_fifo_get <= '0';
down_fifo_flush <= '0';
irq_event <= '0';
flush_stack <= '0';
if presc = 0 then
if timer = 1 then
timer_done <= '1';
end if;
if timer /= 0 then
timer <= timer - 1;
end if;
presc <= g_mhz-1;
else
presc <= presc - 1;
end if;
case state is
when idle =>
null;
when get_inst =>
pc <= pc + 1;
state <= decode;
when decode =>
timer_done <= '0';
timer <= unsigned(a_operand);
-- presc <= 0;
state <= get_inst;
case a_opcode is
when c_opc_load =>
a_data_reg <= a_databyte;
when c_opc_reset_st =>
a_status <= X"01";
when c_opc_reset_drv =>
a_drivers <= "1111";
when c_opc_irq =>
irq_event <= '1';
when c_opc_pushc =>
if up_fifo_full='0' then
up_fifo_din <= '1' & a_data_reg;
up_fifo_put <= '1';
else
state <= decode;
end if;
when c_opc_pushd =>
if up_fifo_full='0' then
up_fifo_din <= '0' & a_data_reg;
up_fifo_put <= '1';
else
state <= decode;
end if;
when c_opc_pop =>
a_data_reg <= down_fifo_dout(7 downto 0);
ctrl_reg <= down_fifo_dout(8);
valid_reg <= not down_fifo_empty;
if down_fifo_empty='0' then
down_fifo_get <= '1';
elsif a_databyte(0)='0' then -- empty and non-block bit not set
state <= decode;
end if;
when c_opc_copy_bit =>
out_vector(to_integer(unsigned(a_databyte(4 downto 0)))) <= selected_bit;
when c_opc_if =>
if selected_bit='1' then
pc <= unsigned(a_operand(pc'range));
end if;
when c_opc_wait =>
timeout_reg <= '0';
state <= wait_true;
when c_opc_sub =>
-- pc_ret <= pc; (will be pushed)
pc <= unsigned(a_operand(pc'range));
when c_opc_ret =>
pc <= unsigned(pc_ret_std);
when c_opc_clrstack =>
flush_stack <= '1';
when others =>
null;
end case;
when wait_true =>
if timer_done='1' then
state <= get_inst;
timeout_reg <= '1';
elsif selected_bit='1' then
state <= get_inst;
end if;
when others =>
null;
end case;
atn_i_d <= atn_i;
if atn_i='0' and atn_i_d/='0' and a_irq_enable='1' then
down_fifo_flush <= '1';
pc <= to_unsigned(1, pc'length);
state <= get_inst;
end if;
if reset='1' then
state <= get_inst;
pc <= (others => '0');
out_vector <= X"F0000";
end if;
end if;
end process;
push <= '1' when (state = decode) and (a_opcode = c_opc_sub) else '0';
pop <= '1' when (state = decode) and (a_opcode = c_opc_ret) else '0';
i_stack: entity work.distributed_stack
generic map (
width => pc'length,
simultaneous_pushpop => false )
port map (
clock => clock,
reset => reset,
pop => pop,
push => push,
flush => flush_stack,
data_in => std_logic_vector(pc),
data_out => pc_ret_std,
full => open,
data_valid => open );
end mixed;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity iec_processor is
generic (
g_mhz : natural := 50);
port (
clock : in std_logic;
reset : in std_logic;
-- instruction ram interface
instr_addr : out unsigned(8 downto 0);
instr_en : out std_logic;
instr_data : in std_logic_vector(29 downto 0);
-- software fifo interface
up_fifo_full : in std_logic;
up_fifo_put : out std_logic;
up_fifo_din : out std_logic_vector(8 downto 0);
down_fifo_empty : in std_logic;
down_fifo_get : out std_logic;
down_fifo_flush : out std_logic;
down_fifo_dout : in std_logic_vector(8 downto 0);
irq_event : out std_logic;
clk_o : out std_logic;
clk_i : in std_logic;
data_o : out std_logic;
data_i : in std_logic;
atn_o : out std_logic;
atn_i : in std_logic;
srq_o : out std_logic;
srq_i : in std_logic );
attribute opt_mode : string;
attribute opt_mode of iec_processor: entity is "area";
end iec_processor;
architecture mixed of iec_processor is
constant c_opc_load : std_logic_vector(3 downto 0) := X"0";
constant c_opc_pop : std_logic_vector(3 downto 0) := X"1";
constant c_opc_pushc : std_logic_vector(3 downto 0) := X"2";
constant c_opc_pushd : std_logic_vector(3 downto 0) := X"3";
constant c_opc_sub : std_logic_vector(3 downto 0) := X"4";
constant c_opc_copy_bit : std_logic_vector(3 downto 0) := X"5";
constant c_opc_irq : std_logic_vector(3 downto 0) := X"6";
constant c_opc_ret : std_logic_vector(3 downto 0) := X"7";
constant c_opc_if : std_logic_vector(3 downto 0) := X"8";
constant c_opc_clrstack : std_logic_vector(3 downto 0) := X"9";
constant c_opc_reset_st : std_logic_vector(3 downto 0) := X"D";
constant c_opc_reset_drv: std_logic_vector(3 downto 0) := X"E";
constant c_opc_wait : std_logic_vector(3 downto 0) := X"C";
signal inputs : std_logic_vector(3 downto 0);
signal inputs_raw : std_logic_vector(3 downto 0);
signal timer : unsigned(11 downto 0);
signal pc : unsigned(instr_addr'range);
signal pc_ret_std : std_logic_vector(instr_addr'range);
signal pop, push : std_logic;
signal presc : integer range 0 to g_mhz;
signal timer_done : std_logic;
signal atn_i_d : std_logic;
signal valid_reg : std_logic := '0';
signal ctrl_reg : std_logic := '0';
signal timeout_reg : std_logic := '0';
signal flush_stack : std_logic;
type t_state is (idle, get_inst, decode, wait_true);
signal state : t_state;
signal instruction : std_logic_vector(29 downto 0);
alias a_invert : std_logic is instruction(29);
alias a_select : std_logic_vector( 4 downto 0) is instruction(28 downto 24);
alias a_opcode : std_logic_vector( 3 downto 0) is instruction(23 downto 20);
alias a_operand : std_logic_vector(11 downto 0) is instruction(19 downto 8);
alias a_mask : std_logic_vector( 3 downto 0) is instruction(7 downto 4);
alias a_value : std_logic_vector( 3 downto 0) is instruction(3 downto 0);
alias a_databyte : std_logic_vector( 7 downto 0) is instruction(7 downto 0);
signal input_vector : std_logic_vector(31 downto 0);
signal selected_bit : std_logic;
signal out_vector : std_logic_vector(19 downto 0);
alias a_drivers : std_logic_vector(3 downto 0) is out_vector(19 downto 16);
alias a_irq_enable : std_logic is out_vector(8);
alias a_status : std_logic_vector(7 downto 0) is out_vector(15 downto 8);
alias a_data_reg : std_logic_vector(7 downto 0) is out_vector(7 downto 0);
begin
clk_o <= a_drivers(0);
data_o <= a_drivers(1);
atn_o <= a_drivers(2);
srq_o <= a_drivers(3);
inputs_raw <= srq_i & atn_i & data_i & clk_i;
inputs <= std_logic_vector(to_01(unsigned(inputs_raw)));
input_vector(31 downto 30) <= "10";
input_vector(29) <= ctrl_reg;
input_vector(28) <= valid_reg;
input_vector(27) <= timeout_reg;
input_vector(26) <= up_fifo_full;
input_vector(25) <= '1' when (inputs and a_mask) = a_value else '0';
input_vector(24) <= '1' when (a_data_reg = a_databyte) else '0';
input_vector(23 downto 20) <= inputs;
input_vector(19 downto 16) <= a_drivers;
input_vector(15 downto 8) <= a_status;
input_vector(7 downto 0) <= a_data_reg;
selected_bit <= input_vector(to_integer(unsigned(a_select))) xor a_invert;
instr_addr <= pc;
instr_en <= '1' when (state = get_inst) else '0';
instruction <= instr_data;
process(clock)
variable v_bit : std_logic;
begin
if rising_edge(clock) then
up_fifo_put <= '0';
down_fifo_get <= '0';
down_fifo_flush <= '0';
irq_event <= '0';
flush_stack <= '0';
if presc = 0 then
if timer = 1 then
timer_done <= '1';
end if;
if timer /= 0 then
timer <= timer - 1;
end if;
presc <= g_mhz-1;
else
presc <= presc - 1;
end if;
case state is
when idle =>
null;
when get_inst =>
pc <= pc + 1;
state <= decode;
when decode =>
timer_done <= '0';
timer <= unsigned(a_operand);
-- presc <= 0;
state <= get_inst;
case a_opcode is
when c_opc_load =>
a_data_reg <= a_databyte;
when c_opc_reset_st =>
a_status <= X"01";
when c_opc_reset_drv =>
a_drivers <= "1111";
when c_opc_irq =>
irq_event <= '1';
when c_opc_pushc =>
if up_fifo_full='0' then
up_fifo_din <= '1' & a_data_reg;
up_fifo_put <= '1';
else
state <= decode;
end if;
when c_opc_pushd =>
if up_fifo_full='0' then
up_fifo_din <= '0' & a_data_reg;
up_fifo_put <= '1';
else
state <= decode;
end if;
when c_opc_pop =>
a_data_reg <= down_fifo_dout(7 downto 0);
ctrl_reg <= down_fifo_dout(8);
valid_reg <= not down_fifo_empty;
if down_fifo_empty='0' then
down_fifo_get <= '1';
elsif a_databyte(0)='0' then -- empty and non-block bit not set
state <= decode;
end if;
when c_opc_copy_bit =>
out_vector(to_integer(unsigned(a_databyte(4 downto 0)))) <= selected_bit;
when c_opc_if =>
if selected_bit='1' then
pc <= unsigned(a_operand(pc'range));
end if;
when c_opc_wait =>
timeout_reg <= '0';
state <= wait_true;
when c_opc_sub =>
-- pc_ret <= pc; (will be pushed)
pc <= unsigned(a_operand(pc'range));
when c_opc_ret =>
pc <= unsigned(pc_ret_std);
when c_opc_clrstack =>
flush_stack <= '1';
when others =>
null;
end case;
when wait_true =>
if timer_done='1' then
state <= get_inst;
timeout_reg <= '1';
elsif selected_bit='1' then
state <= get_inst;
end if;
when others =>
null;
end case;
atn_i_d <= atn_i;
if atn_i='0' and atn_i_d/='0' and a_irq_enable='1' then
down_fifo_flush <= '1';
pc <= to_unsigned(1, pc'length);
state <= get_inst;
end if;
if reset='1' then
state <= get_inst;
pc <= (others => '0');
out_vector <= X"F0000";
end if;
end if;
end process;
push <= '1' when (state = decode) and (a_opcode = c_opc_sub) else '0';
pop <= '1' when (state = decode) and (a_opcode = c_opc_ret) else '0';
i_stack: entity work.distributed_stack
generic map (
width => pc'length,
simultaneous_pushpop => false )
port map (
clock => clock,
reset => reset,
pop => pop,
push => push,
flush => flush_stack,
data_in => std_logic_vector(pc),
data_out => pc_ret_std,
full => open,
data_valid => open );
end mixed;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity iec_processor is
generic (
g_mhz : natural := 50);
port (
clock : in std_logic;
reset : in std_logic;
-- instruction ram interface
instr_addr : out unsigned(8 downto 0);
instr_en : out std_logic;
instr_data : in std_logic_vector(29 downto 0);
-- software fifo interface
up_fifo_full : in std_logic;
up_fifo_put : out std_logic;
up_fifo_din : out std_logic_vector(8 downto 0);
down_fifo_empty : in std_logic;
down_fifo_get : out std_logic;
down_fifo_flush : out std_logic;
down_fifo_dout : in std_logic_vector(8 downto 0);
irq_event : out std_logic;
clk_o : out std_logic;
clk_i : in std_logic;
data_o : out std_logic;
data_i : in std_logic;
atn_o : out std_logic;
atn_i : in std_logic;
srq_o : out std_logic;
srq_i : in std_logic );
attribute opt_mode : string;
attribute opt_mode of iec_processor: entity is "area";
end iec_processor;
architecture mixed of iec_processor is
constant c_opc_load : std_logic_vector(3 downto 0) := X"0";
constant c_opc_pop : std_logic_vector(3 downto 0) := X"1";
constant c_opc_pushc : std_logic_vector(3 downto 0) := X"2";
constant c_opc_pushd : std_logic_vector(3 downto 0) := X"3";
constant c_opc_sub : std_logic_vector(3 downto 0) := X"4";
constant c_opc_copy_bit : std_logic_vector(3 downto 0) := X"5";
constant c_opc_irq : std_logic_vector(3 downto 0) := X"6";
constant c_opc_ret : std_logic_vector(3 downto 0) := X"7";
constant c_opc_if : std_logic_vector(3 downto 0) := X"8";
constant c_opc_clrstack : std_logic_vector(3 downto 0) := X"9";
constant c_opc_reset_st : std_logic_vector(3 downto 0) := X"D";
constant c_opc_reset_drv: std_logic_vector(3 downto 0) := X"E";
constant c_opc_wait : std_logic_vector(3 downto 0) := X"C";
signal inputs : std_logic_vector(3 downto 0);
signal inputs_raw : std_logic_vector(3 downto 0);
signal timer : unsigned(11 downto 0);
signal pc : unsigned(instr_addr'range);
signal pc_ret_std : std_logic_vector(instr_addr'range);
signal pop, push : std_logic;
signal presc : integer range 0 to g_mhz;
signal timer_done : std_logic;
signal atn_i_d : std_logic;
signal valid_reg : std_logic := '0';
signal ctrl_reg : std_logic := '0';
signal timeout_reg : std_logic := '0';
signal flush_stack : std_logic;
type t_state is (idle, get_inst, decode, wait_true);
signal state : t_state;
signal instruction : std_logic_vector(29 downto 0);
alias a_invert : std_logic is instruction(29);
alias a_select : std_logic_vector( 4 downto 0) is instruction(28 downto 24);
alias a_opcode : std_logic_vector( 3 downto 0) is instruction(23 downto 20);
alias a_operand : std_logic_vector(11 downto 0) is instruction(19 downto 8);
alias a_mask : std_logic_vector( 3 downto 0) is instruction(7 downto 4);
alias a_value : std_logic_vector( 3 downto 0) is instruction(3 downto 0);
alias a_databyte : std_logic_vector( 7 downto 0) is instruction(7 downto 0);
signal input_vector : std_logic_vector(31 downto 0);
signal selected_bit : std_logic;
signal out_vector : std_logic_vector(19 downto 0);
alias a_drivers : std_logic_vector(3 downto 0) is out_vector(19 downto 16);
alias a_irq_enable : std_logic is out_vector(8);
alias a_status : std_logic_vector(7 downto 0) is out_vector(15 downto 8);
alias a_data_reg : std_logic_vector(7 downto 0) is out_vector(7 downto 0);
begin
clk_o <= a_drivers(0);
data_o <= a_drivers(1);
atn_o <= a_drivers(2);
srq_o <= a_drivers(3);
inputs_raw <= srq_i & atn_i & data_i & clk_i;
inputs <= std_logic_vector(to_01(unsigned(inputs_raw)));
input_vector(31 downto 30) <= "10";
input_vector(29) <= ctrl_reg;
input_vector(28) <= valid_reg;
input_vector(27) <= timeout_reg;
input_vector(26) <= up_fifo_full;
input_vector(25) <= '1' when (inputs and a_mask) = a_value else '0';
input_vector(24) <= '1' when (a_data_reg = a_databyte) else '0';
input_vector(23 downto 20) <= inputs;
input_vector(19 downto 16) <= a_drivers;
input_vector(15 downto 8) <= a_status;
input_vector(7 downto 0) <= a_data_reg;
selected_bit <= input_vector(to_integer(unsigned(a_select))) xor a_invert;
instr_addr <= pc;
instr_en <= '1' when (state = get_inst) else '0';
instruction <= instr_data;
process(clock)
variable v_bit : std_logic;
begin
if rising_edge(clock) then
up_fifo_put <= '0';
down_fifo_get <= '0';
down_fifo_flush <= '0';
irq_event <= '0';
flush_stack <= '0';
if presc = 0 then
if timer = 1 then
timer_done <= '1';
end if;
if timer /= 0 then
timer <= timer - 1;
end if;
presc <= g_mhz-1;
else
presc <= presc - 1;
end if;
case state is
when idle =>
null;
when get_inst =>
pc <= pc + 1;
state <= decode;
when decode =>
timer_done <= '0';
timer <= unsigned(a_operand);
-- presc <= 0;
state <= get_inst;
case a_opcode is
when c_opc_load =>
a_data_reg <= a_databyte;
when c_opc_reset_st =>
a_status <= X"01";
when c_opc_reset_drv =>
a_drivers <= "1111";
when c_opc_irq =>
irq_event <= '1';
when c_opc_pushc =>
if up_fifo_full='0' then
up_fifo_din <= '1' & a_data_reg;
up_fifo_put <= '1';
else
state <= decode;
end if;
when c_opc_pushd =>
if up_fifo_full='0' then
up_fifo_din <= '0' & a_data_reg;
up_fifo_put <= '1';
else
state <= decode;
end if;
when c_opc_pop =>
a_data_reg <= down_fifo_dout(7 downto 0);
ctrl_reg <= down_fifo_dout(8);
valid_reg <= not down_fifo_empty;
if down_fifo_empty='0' then
down_fifo_get <= '1';
elsif a_databyte(0)='0' then -- empty and non-block bit not set
state <= decode;
end if;
when c_opc_copy_bit =>
out_vector(to_integer(unsigned(a_databyte(4 downto 0)))) <= selected_bit;
when c_opc_if =>
if selected_bit='1' then
pc <= unsigned(a_operand(pc'range));
end if;
when c_opc_wait =>
timeout_reg <= '0';
state <= wait_true;
when c_opc_sub =>
-- pc_ret <= pc; (will be pushed)
pc <= unsigned(a_operand(pc'range));
when c_opc_ret =>
pc <= unsigned(pc_ret_std);
when c_opc_clrstack =>
flush_stack <= '1';
when others =>
null;
end case;
when wait_true =>
if timer_done='1' then
state <= get_inst;
timeout_reg <= '1';
elsif selected_bit='1' then
state <= get_inst;
end if;
when others =>
null;
end case;
atn_i_d <= atn_i;
if atn_i='0' and atn_i_d/='0' and a_irq_enable='1' then
down_fifo_flush <= '1';
pc <= to_unsigned(1, pc'length);
state <= get_inst;
end if;
if reset='1' then
state <= get_inst;
pc <= (others => '0');
out_vector <= X"F0000";
end if;
end if;
end process;
push <= '1' when (state = decode) and (a_opcode = c_opc_sub) else '0';
pop <= '1' when (state = decode) and (a_opcode = c_opc_ret) else '0';
i_stack: entity work.distributed_stack
generic map (
width => pc'length,
simultaneous_pushpop => false )
port map (
clock => clock,
reset => reset,
pop => pop,
push => push,
flush => flush_stack,
data_in => std_logic_vector(pc),
data_out => pc_ret_std,
full => open,
data_valid => open );
end mixed;
|
--*****************************************************************************
-- (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 4.0
-- \ \ Application : MIG
-- / / Filename : example_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
-- \ \ / \ Date Created : Wed Feb 01 2012
-- \___\/\___\
--
-- Device : 7 Series
-- Design Name : DDR2 SDRAM
-- Purpose :
-- Top-level module. This module serves as an example,
-- and allows the user to synthesize a self-contained design,
-- which they can be used to test their hardware.
-- In addition to the memory controller, the module instantiates:
-- 1. Synthesizable testbench - used to model user's backend logic
-- and generate different traffic patterns
-- Reference :
-- Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity example_top is
generic (
--***************************************************************************
-- Traffic Gen related parameters
--***************************************************************************
BL_WIDTH : integer := 10;
PORT_MODE : string := "BI_MODE";
DATA_MODE : std_logic_vector(3 downto 0) := "0010";
ADDR_MODE : std_logic_vector(3 downto 0) := "0011";
TST_MEM_INSTR_MODE : string := "R_W_INSTR_MODE";
EYE_TEST : string := "FALSE";
-- set EYE_TEST = "TRUE" to probe memory
-- signals. Traffic Generator will only
-- write to one single location and no
-- read transactions will be generated.
DATA_PATTERN : string := "DGEN_ALL";
-- For small devices, choose one only.
-- For large device, choose "DGEN_ALL"
-- "DGEN_HAMMER", "DGEN_WALKING1",
-- "DGEN_WALKING0","DGEN_ADDR","
-- "DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
CMD_PATTERN : string := "CGEN_ALL";
-- "CGEN_PRBS","CGEN_FIXED","CGEN_BRAM",
-- "CGEN_SEQUENTIAL", "CGEN_ALL"
BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
END_ADDRESS : std_logic_vector(31 downto 0) := X"00ffffff";
MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
--Possible Parameters
--1.BANK_ROW_COLUMN : Address mapping is
-- in form of Bank Row Column.
--2.ROW_BANK_COLUMN : Address mapping is
-- in the form of Row Bank Column.
--3.TG_TEST : Scrambles Address bits
-- for distributed Addressing.
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"ff000000";
CMD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
WR_WDT : std_logic_vector(31 downto 0) := X"00001fff";
RD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
--***************************************************************************
-- The following parameters refer to width of various ports
--***************************************************************************
BANK_WIDTH : integer := 3;
-- # of memory Bank Address bits.
COL_WIDTH : integer := 10;
-- # of memory Column Address bits.
CS_WIDTH : integer := 1;
-- # of unique CS outputs to memory.
DQ_WIDTH : integer := 16;
-- # of DQ (data)
DQS_WIDTH : integer := 2;
DQS_CNT_WIDTH : integer := 1;
-- = ceil(log2(DQS_WIDTH))
DRAM_WIDTH : integer := 8;
-- # of DQ per DQS
ECC_TEST : string := "OFF";
RANKS : integer := 1;
-- # of Ranks.
ROW_WIDTH : integer := 13;
-- # of memory Row Address bits.
ADDR_WIDTH : integer := 27;
-- # = RANK_WIDTH + BANK_WIDTH
-- + ROW_WIDTH + COL_WIDTH;
-- Chip Select is always tied to low for
-- single rank devices
--***************************************************************************
-- The following parameters are mode register settings
--***************************************************************************
BURST_MODE : string := "8";
-- DDR3 SDRAM:
-- Burst Length (Mode Register 0).
-- # = "8", "4", "OTF".
-- DDR2 SDRAM:
-- Burst Length (Mode Register).
-- # = "8", "4".
--***************************************************************************
-- Simulation parameters
--***************************************************************************
SIMULATION : string := "FALSE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
--***************************************************************************
-- IODELAY and PHY related parameters
--***************************************************************************
TCQ : integer := 100;
DRAM_TYPE : string := "DDR2";
--***************************************************************************
-- System clock frequency parameters
--***************************************************************************
nCK_PER_CLK : integer := 2;
-- # of memory CKs per fabric CLK
--***************************************************************************
-- Debug parameters
--***************************************************************************
DEBUG_PORT : string := "OFF";
-- # = "ON" Enable debug signals/controls.
-- = "OFF" Disable debug signals/controls.
--***************************************************************************
-- Temparature monitor parameter
--***************************************************************************
TEMP_MON_CONTROL : string := "INTERNAL"
-- # = "INTERNAL", "EXTERNAL"
-- RST_ACT_LOW : integer := 1
-- =1 for active low reset,
-- =0 for active high.
);
port (
-- Inouts
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
-- Outputs
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
-- Inputs
-- Single-ended system clock
sys_clk_i : in std_logic;
tg_compare_error : out std_logic;
init_calib_complete : out std_logic;
-- System reset - Default polarity of sys_rst pin is Active Low.
-- System reset polarity will change based on the option
-- selected in GUI.
sys_rst : in std_logic
);
end entity example_top;
architecture arch_example_top of example_top is
-- clogb2 function - ceiling of log base 2
function clogb2 (size : integer) return integer is
variable base : integer := 1;
variable inp : integer := 0;
begin
inp := size - 1;
while (inp > 1) loop
inp := inp/2 ;
base := base + 1;
end loop;
return base;
end function;function STR_TO_INT(BM : string) return integer is
begin
if(BM = "8") then
return 8;
elsif(BM = "4") then
return 4;
else
return 0;
end if;
end function;
constant RANK_WIDTH : integer := clogb2(RANKS);
function XWIDTH return integer is
begin
if(CS_WIDTH = 1) then
return 0;
else
return RANK_WIDTH;
end if;
end function;
constant CMD_PIPE_PLUS1 : string := "ON";
-- add pipeline stage between MC and PHY
constant tPRDI : integer := 1000000;
-- memory tPRDI paramter in pS.
constant DATA_WIDTH : integer := 16;
constant PAYLOAD_WIDTH : integer := DATA_WIDTH;
constant BURST_LENGTH : integer := STR_TO_INT(BURST_MODE);
constant APP_DATA_WIDTH : integer := 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
constant APP_MASK_WIDTH : integer := APP_DATA_WIDTH / 8;
--***************************************************************************
-- Traffic Gen related parameters (derived)
--***************************************************************************
constant TG_ADDR_WIDTH : integer := XWIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH;
constant MASK_SIZE : integer := DATA_WIDTH/8;
-- Start of User Design top component
component ddr
-- generic (
-- #parameters_user_design_top_component#
-- RST_ACT_LOW : integer
-- );
port(
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
app_addr : in std_logic_vector(26 downto 0);
app_cmd : in std_logic_vector(2 downto 0);
app_en : in std_logic;
app_wdf_data : in std_logic_vector(63 downto 0);
app_wdf_end : in std_logic;
app_wdf_mask : in std_logic_vector(7 downto 0);
app_wdf_wren : in std_logic;
app_rd_data : out std_logic_vector(63 downto 0);
app_rd_data_end : out std_logic;
app_rd_data_valid : out std_logic;
app_rdy : out std_logic;
app_wdf_rdy : out std_logic;
app_sr_req : in std_logic;
app_ref_req : in std_logic;
app_zq_req : in std_logic;
app_sr_active : out std_logic;
app_ref_ack : out std_logic;
app_zq_ack : out std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic;
init_calib_complete : out std_logic;
-- System Clock Ports
sys_clk_i : in std_logic;
sys_rst : in std_logic
);
end component ddr;
-- End of User Design top component
component mig_7series_v4_0_traffic_gen_top
generic (
TCQ : integer;
SIMULATION : string;
FAMILY : string;
MEM_TYPE : string;
TST_MEM_INSTR_MODE : string;
--BL_WIDTH : integer;
nCK_PER_CLK : integer;
NUM_DQ_PINS : integer;
MEM_BURST_LEN : integer;
MEM_COL_WIDTH : integer;
DATA_WIDTH : integer;
ADDR_WIDTH : integer;
MASK_SIZE : integer := 8;
DATA_MODE : std_logic_vector(3 downto 0);
BEGIN_ADDRESS : std_logic_vector(31 downto 0);
END_ADDRESS : std_logic_vector(31 downto 0);
PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0);
CMDS_GAP_DELAY : std_logic_vector(5 downto 0) := "000000";
SEL_VICTIM_LINE : integer := 8;
CMD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
WR_WDT : std_logic_vector(31 downto 0) := X"00001fff";
RD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
EYE_TEST : string;
PORT_MODE : string;
DATA_PATTERN : string;
CMD_PATTERN : string
);
port (
clk : in std_logic;
rst : in std_logic;
tg_only_rst : in std_logic;
manual_clear_error : in std_logic;
memc_init_done : in std_logic;
memc_cmd_full : in std_logic;
memc_cmd_en : out std_logic;
memc_cmd_instr : out std_logic_vector(2 downto 0);
memc_cmd_bl : out std_logic_vector(5 downto 0);
memc_cmd_addr : out std_logic_vector(31 downto 0);
memc_wr_en : out std_logic;
memc_wr_end : out std_logic;
memc_wr_mask : out std_logic_vector((DATA_WIDTH/8)-1 downto 0);
memc_wr_data : out std_logic_vector(DATA_WIDTH-1 downto 0);
memc_wr_full : in std_logic;
memc_rd_en : out std_logic;
memc_rd_data : in std_logic_vector(DATA_WIDTH-1 downto 0);
memc_rd_empty : in std_logic;
qdr_wr_cmd_o : out std_logic;
qdr_rd_cmd_o : out std_logic;
vio_pause_traffic : in std_logic;
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(3 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
vio_instr_mode_value : in std_logic_vector(3 downto 0);
vio_bl_mode_value : in std_logic_vector(1 downto 0);
vio_fixed_bl_value : in std_logic_vector(9 downto 0);
vio_fixed_instr_value : in std_logic_vector(2 downto 0);
vio_data_mask_gen : in std_logic;
fixed_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(31 downto 0);
simple_data0 : in std_logic_vector(31 downto 0);
simple_data1 : in std_logic_vector(31 downto 0);
simple_data2 : in std_logic_vector(31 downto 0);
simple_data3 : in std_logic_vector(31 downto 0);
simple_data4 : in std_logic_vector(31 downto 0);
simple_data5 : in std_logic_vector(31 downto 0);
simple_data6 : in std_logic_vector(31 downto 0);
simple_data7 : in std_logic_vector(31 downto 0);
wdt_en_i : in std_logic;
bram_cmd_i : in std_logic_vector(38 downto 0);
bram_valid_i : in std_logic;
bram_rdy_o : out std_logic;
cmp_data : out std_logic_vector(DATA_WIDTH-1 downto 0);
cmp_data_valid : out std_logic;
cmp_error : out std_logic;
wr_data_counts : out std_logic_vector(47 downto 0);
rd_data_counts : out std_logic_vector(47 downto 0);
dq_error_bytelane_cmp : out std_logic_vector((NUM_DQ_PINS/8)-1 downto 0);
error : out std_logic;
error_status : out std_logic_vector((64+(2*DATA_WIDTH))-1 downto 0);
cumlative_dq_lane_error : out std_logic_vector((NUM_DQ_PINS/8)-1 downto 0);
cmd_wdt_err_o : out std_logic;
wr_wdt_err_o : out std_logic;
rd_wdt_err_o : out std_logic;
mem_pattern_init_done : out std_logic
);
end component mig_7series_v4_0_traffic_gen_top;
-- Signal declarations
signal app_ecc_multiple_err : std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
signal app_ecc_single_err : std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
signal app_addr : std_logic_vector(ADDR_WIDTH-1 downto 0);
signal app_addr_i : std_logic_vector(31 downto 0);
signal app_cmd : std_logic_vector(2 downto 0);
signal app_en : std_logic;
signal app_rdy : std_logic;
signal app_rdy_i : std_logic;
signal app_rd_data : std_logic_vector(APP_DATA_WIDTH-1 downto 0);
signal app_rd_data_end : std_logic;
signal app_rd_data_valid : std_logic;
signal app_rd_data_valid_i : std_logic;
signal app_wdf_data : std_logic_vector(APP_DATA_WIDTH-1 downto 0);
signal app_wdf_end : std_logic;
signal app_wdf_mask : std_logic_vector(APP_MASK_WIDTH-1 downto 0);
signal app_wdf_rdy : std_logic;
signal app_wdf_rdy_i : std_logic;
signal app_sr_active : std_logic;
signal app_ref_ack : std_logic;
signal app_zq_ack : std_logic;
signal app_wdf_wren : std_logic;
signal error_status : std_logic_vector((64 + (4*PAYLOAD_WIDTH*nCK_PER_CLK))-1 downto 0);
signal cumlative_dq_lane_error : std_logic_vector((PAYLOAD_WIDTH/8)-1 downto 0);
signal mem_pattern_init_done : std_logic_vector(0 downto 0);
signal modify_enable_sel : std_logic;
signal data_mode_manual_sel : std_logic_vector(2 downto 0);
signal addr_mode_manual_sel : std_logic_vector(2 downto 0);
signal cmp_data : std_logic_vector((PAYLOAD_WIDTH*2*nCK_PER_CLK)-1 downto 0);
signal cmp_data_r : std_logic_vector(63 downto 0);
signal cmp_data_valid : std_logic;
signal cmp_data_valid_r : std_logic;
signal cmp_error : std_logic;
signal tg_wr_data_counts : std_logic_vector(47 downto 0);
signal tg_rd_data_counts : std_logic_vector(47 downto 0);
signal dq_error_bytelane_cmp : std_logic_vector((PAYLOAD_WIDTH/8)-1 downto 0);
signal init_calib_complete_i : std_logic;
signal tg_compare_error_i : std_logic;
signal tg_rst : std_logic;
signal po_win_tg_rst : std_logic;
signal manual_clear_error : std_logic_vector(0 downto 0);
signal clk : std_logic;
signal rst : std_logic;
signal vio_modify_enable : std_logic_vector(0 downto 0);
signal vio_data_mode_value : std_logic_vector(3 downto 0);
signal vio_pause_traffic : std_logic_vector(0 downto 0);
signal vio_addr_mode_value : std_logic_vector(2 downto 0);
signal vio_instr_mode_value : std_logic_vector(3 downto 0);
signal vio_bl_mode_value : std_logic_vector(1 downto 0);
signal vio_fixed_bl_value : std_logic_vector(BL_WIDTH-1 downto 0);
signal vio_fixed_instr_value : std_logic_vector(2 downto 0);
signal vio_data_mask_gen : std_logic_vector(0 downto 0);
signal dbg_clear_error : std_logic_vector(0 downto 0);
signal vio_tg_rst : std_logic_vector(0 downto 0);
signal dbg_sel_pi_incdec : std_logic_vector(0 downto 0);
signal dbg_pi_f_inc : std_logic_vector(0 downto 0);
signal dbg_pi_f_dec : std_logic_vector(0 downto 0);
signal dbg_sel_po_incdec : std_logic_vector(0 downto 0);
signal dbg_po_f_inc : std_logic_vector(0 downto 0);
signal dbg_po_f_stg23_sel : std_logic_vector(0 downto 0);
signal dbg_po_f_dec : std_logic_vector(0 downto 0);
signal vio_dbg_sel_pi_incdec : std_logic_vector(0 downto 0);
signal vio_dbg_pi_f_inc : std_logic_vector(0 downto 0);
signal vio_dbg_pi_f_dec : std_logic_vector(0 downto 0);
signal vio_dbg_sel_po_incdec : std_logic_vector(0 downto 0);
signal vio_dbg_po_f_inc : std_logic_vector(0 downto 0);
signal vio_dbg_po_f_stg23_sel : std_logic_vector(0 downto 0);
signal vio_dbg_po_f_dec : std_logic_vector(0 downto 0);
signal all_zeros1 : std_logic_vector(31 downto 0):= (others => '0');
signal all_zeros2 : std_logic_vector(38 downto 0):= (others => '0');
signal wdt_en_w : std_logic_vector(0 downto 0);
signal cmd_wdt_err_w : std_logic;
signal wr_wdt_err_w : std_logic;
signal rd_wdt_err_w : std_logic;
signal device_temp : std_logic_vector(11 downto 0);
begin
--***************************************************************************
init_calib_complete <= init_calib_complete_i;
tg_compare_error <= tg_compare_error_i;
app_rdy_i <= not(app_rdy);
app_wdf_rdy_i <= not(app_wdf_rdy);
app_rd_data_valid_i <= not(app_rd_data_valid);
app_addr <= app_addr_i(ADDR_WIDTH-1 downto 0);
-- Start of User Design top instance
--***************************************************************************
-- The User design is instantiated below. The memory interface ports are
-- connected to the top-level and the application interface ports are
-- connected to the traffic generator module. This provides a reference
-- for connecting the memory controller to system.
--***************************************************************************
u_ddr : ddr
-- generic map (
-- #parameters_mapping_user_design_top_instance#
-- RST_ACT_LOW => RST_ACT_LOW
-- )
port map (
-- Memory interface ports
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_cas_n => ddr2_cas_n,
ddr2_ck_n => ddr2_ck_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_cke => ddr2_cke,
ddr2_ras_n => ddr2_ras_n,
ddr2_we_n => ddr2_we_n,
ddr2_dq => ddr2_dq,
ddr2_dqs_n => ddr2_dqs_n,
ddr2_dqs_p => ddr2_dqs_p,
init_calib_complete => init_calib_complete_i,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
-- Application interface ports
app_addr => app_addr,
app_cmd => app_cmd,
app_en => app_en,
app_wdf_data => app_wdf_data,
app_wdf_end => app_wdf_end,
app_wdf_wren => app_wdf_wren,
app_rd_data => app_rd_data,
app_rd_data_end => app_rd_data_end,
app_rd_data_valid => app_rd_data_valid,
app_rdy => app_rdy,
app_wdf_rdy => app_wdf_rdy,
app_sr_req => '0',
app_ref_req => '0',
app_zq_req => '0',
app_sr_active => app_sr_active,
app_ref_ack => app_ref_ack,
app_zq_ack => app_zq_ack,
ui_clk => clk,
ui_clk_sync_rst => rst,
app_wdf_mask => app_wdf_mask,
-- System Clock Ports
sys_clk_i => sys_clk_i,
sys_rst => sys_rst
);
-- End of User Design top instance
--***************************************************************************
-- The traffic generation module instantiated below drives traffic (patterns)
-- on the application interface of the memory controller
--***************************************************************************
tg_rst <= vio_tg_rst(0) or po_win_tg_rst;
u_traffic_gen_top : mig_7series_v4_0_traffic_gen_top
generic map (
TCQ => TCQ,
SIMULATION => SIMULATION,
FAMILY => "VIRTEX7",
MEM_TYPE => DRAM_TYPE,
TST_MEM_INSTR_MODE => TST_MEM_INSTR_MODE,
nCK_PER_CLK => nCK_PER_CLK,
NUM_DQ_PINS => PAYLOAD_WIDTH,
MEM_BURST_LEN => BURST_LENGTH,
MEM_COL_WIDTH => COL_WIDTH,
PORT_MODE => PORT_MODE,
DATA_PATTERN => DATA_PATTERN,
CMD_PATTERN => CMD_PATTERN,
ADDR_WIDTH => TG_ADDR_WIDTH,
DATA_WIDTH => APP_DATA_WIDTH,
BEGIN_ADDRESS => BEGIN_ADDRESS,
DATA_MODE => DATA_MODE,
END_ADDRESS => END_ADDRESS,
PRBS_EADDR_MASK_POS => PRBS_EADDR_MASK_POS,
CMD_WDT => CMD_WDT,
RD_WDT => RD_WDT,
WR_WDT => WR_WDT,
EYE_TEST => EYE_TEST
)
port map (
clk => clk,
rst => rst,
tg_only_rst => tg_rst,
manual_clear_error => manual_clear_error(0),
memc_init_done => init_calib_complete_i,
memc_cmd_full => app_rdy_i,
memc_cmd_en => app_en,
memc_cmd_instr => app_cmd,
memc_cmd_bl => open,
memc_cmd_addr => app_addr_i,
memc_wr_en => app_wdf_wren,
memc_wr_end => app_wdf_end,
memc_wr_mask => app_wdf_mask(((PAYLOAD_WIDTH*2*nCK_PER_CLK)/8)-1 downto 0),
memc_wr_data => app_wdf_data((PAYLOAD_WIDTH*2*nCK_PER_CLK)-1 downto 0),
memc_wr_full => app_wdf_rdy_i,
memc_rd_en => open,
memc_rd_data => app_rd_data((PAYLOAD_WIDTH*2*nCK_PER_CLK)-1 downto 0),
memc_rd_empty => app_rd_data_valid_i,
qdr_wr_cmd_o => open,
qdr_rd_cmd_o => open,
vio_pause_traffic => vio_pause_traffic(0),
vio_modify_enable => vio_modify_enable(0),
vio_data_mode_value => vio_data_mode_value,
vio_addr_mode_value => vio_addr_mode_value,
vio_instr_mode_value => vio_instr_mode_value,
vio_bl_mode_value => vio_bl_mode_value,
vio_fixed_bl_value => vio_fixed_bl_value,
vio_fixed_instr_value=> vio_fixed_instr_value,
vio_data_mask_gen => vio_data_mask_gen(0),
fixed_addr_i => all_zeros1,
fixed_data_i => all_zeros1,
simple_data0 => all_zeros1,
simple_data1 => all_zeros1,
simple_data2 => all_zeros1,
simple_data3 => all_zeros1,
simple_data4 => all_zeros1,
simple_data5 => all_zeros1,
simple_data6 => all_zeros1,
simple_data7 => all_zeros1,
wdt_en_i => wdt_en_w(0),
bram_cmd_i => all_zeros2,
bram_valid_i => '0',
bram_rdy_o => open,
cmp_data => cmp_data,
cmp_data_valid => cmp_data_valid,
cmp_error => cmp_error,
wr_data_counts => tg_wr_data_counts,
rd_data_counts => tg_rd_data_counts,
dq_error_bytelane_cmp => dq_error_bytelane_cmp,
error => tg_compare_error_i,
error_status => error_status,
cumlative_dq_lane_error => cumlative_dq_lane_error,
cmd_wdt_err_o => cmd_wdt_err_w,
wr_wdt_err_o => wr_wdt_err_w,
rd_wdt_err_o => rd_wdt_err_w,
mem_pattern_init_done => mem_pattern_init_done(0)
);
--*****************************************************************
-- Default values are assigned to the debug inputs of the traffic
-- generator
--*****************************************************************
vio_modify_enable(0) <= '0';
vio_data_mode_value <= "0010";
vio_addr_mode_value <= "011";
vio_instr_mode_value <= "0010";
vio_bl_mode_value <= "10";
vio_fixed_bl_value <= "0000010000";
vio_data_mask_gen(0) <= '0';
vio_pause_traffic(0) <= '0';
vio_fixed_instr_value <= "001";
dbg_clear_error(0) <= '0';
po_win_tg_rst <= '0';
vio_tg_rst(0) <= '0';
wdt_en_w(0) <= '1';
dbg_sel_pi_incdec(0) <= '0';
dbg_sel_po_incdec(0) <= '0';
dbg_pi_f_inc(0) <= '0';
dbg_pi_f_dec(0) <= '0';
dbg_po_f_inc(0) <= '0';
dbg_po_f_dec(0) <= '0';
dbg_po_f_stg23_sel(0) <= '0';
end architecture arch_example_top;
|
----------------------------------------------------------------------------------
-- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH
-- Engineer: CHRISTOPHER PARKS ([email protected])
--
-- Create Date: 15:33:22 03/11/2016
-- Module Name: PipelineRegisters - Behavioral
-- Target Devices: SPARTAN XC3S500E
-- Description: REGISTER BANK TO BE USED IN PIPELINE DEVICE THAT USES GENERAL PURPOSE REGISTERS FOR PIPELINE USE
--
-- Dependencies: IEEE.STD_LOGIC_1164
--
-- Revision 0.01 - File Created
-- Revision 0.02 - Reset line added
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RegisterBank is
Port ( RAddr : in STD_LOGIC_VECTOR (3 downto 0); --
RBddr : in STD_LOGIC_VECTOR (3 downto 0); --
RWddr : in STD_LOGIC_VECTOR (3 downto 0);
DATAIN : in STD_LOGIC_VECTOR (15 downto 0);
clk : in STD_LOGIC;
RST : in STD_LOGIC;
R : in STD_LOGIC;
W : in STD_LOGIC;
RAout : out STD_LOGIC_VECTOR (15 downto 0); --
RBout : out STD_LOGIC_VECTOR (15 downto 0)); --
end RegisterBank;
architecture Behavioral of RegisterBank is
signal R0dat, R1dat, R2dat, R3dat, R4dat, R5dat, R6dat, R7dat, R8dat, R9dat,
R10dat, R11dat, R12dat, R13dat, R14dat, R15dat : STD_LOGIC_VECTOR(15 downto 0) := (OTHERS => '0');
begin
process(clk,RST) -- Synchronous register bank
begin
if (RST = '0') then
if(rising_edge(clk) and R = '1') then -- Synchronous data read when read line enabled on rising edge (before write back)
case RAddr is
when x"0" => RAout <= R0dat;
when x"1" => RAout <= R1dat;
when x"2" => RAout <= R2dat;
when x"3" => RAout <= R3dat;
when x"4" => RAout <= R4dat;
when x"5" => RAout <= R5dat;
when x"6" => RAout <= R6dat;
when x"7" => RAout <= R7dat;
when x"8" => RAout <= R8dat;
when x"9" => RAout <= R9dat;
when x"A" => RAout <= R10dat;
when x"B" => RAout <= R11dat;
when x"C" => RAout <= R12dat;
when x"D" => RAout <= R13dat;
when x"E" => RAout <= R14dat;
when x"F" => RAout <= R15dat;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
case RBddr is
when x"0" => RBout <= R0dat;
when x"1" => RBout <= R1dat;
when x"2" => RBout <= R2dat;
when x"3" => RBout <= R3dat;
when x"4" => RBout <= R4dat;
when x"5" => RBout <= R5dat;
when x"6" => RBout <= R6dat;
when x"7" => RBout <= R7dat;
when x"8" => RBout <= R8dat;
when x"9" => RBout <= R9dat;
when x"A" => RBout <= R10dat;
when x"B" => RBout <= R11dat;
when x"C" => RBout <= R12dat;
when x"D" => RBout <= R13dat;
when x"E" => RBout <= R14dat;
when x"F" => RBout <= R15dat;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
end if;
if(falling_edge(clk) and W = '1') then -- Synchronous data latching when write line enabled (after data read)
case RWddr is
when x"0" => R0dat <= DATAIN;
when x"1" => R1dat <= DATAIN;
when x"2" => R2dat <= DATAIN;
when x"3" => R3dat <= DATAIN;
when x"4" => R4dat <= DATAIN;
when x"5" => R5dat <= DATAIN;
when x"6" => R6dat <= DATAIN;
when x"7" => R7dat <= DATAIN;
when x"8" => R8dat <= DATAIN;
when x"9" => R9dat <= DATAIN;
when x"A" => R10dat <= DATAIN;
when x"B" => R11dat <= DATAIN;
when x"C" => R12dat <= DATAIN;
when x"D" => R13dat <= DATAIN;
when x"E" => R14dat <= DATAIN;
when x"F" => R15dat <= DATAIN;
when others => -- BY DEFAULT DO NOTHING FOR FAULTY ADDRESS
end case;
end if;
else
R0dat <= (OTHERS => '0');
R1dat <= (OTHERS => '0');
R2dat <= (OTHERS => '0');
R3dat <= (OTHERS => '0');
R4dat <= (OTHERS => '0');
R5dat <= (OTHERS => '0');
R6dat <= (OTHERS => '0');
R7dat <= (OTHERS => '0');
R8dat <= (OTHERS => '0');
R9dat <= (OTHERS => '0');
R10dat <= (OTHERS => '0');
R11dat <= (OTHERS => '0');
R12dat <= (OTHERS => '0');
R13dat <= (OTHERS => '0');
R14dat <= (OTHERS => '0');
R15dat <= (OTHERS => '0');
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: prog_mem - Behavioral
-- Create Date: 14:09:04 10/30/2009
-- Description: the program memory of a CPU.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
-- the content of the program memory.
--
use work.prog_mem_content.all;
entity prog_mem is
port ( I_CLK : in std_logic;
I_WAIT : in std_logic;
I_PC : in std_logic_vector(15 downto 0); -- word address
I_PM_ADR : in std_logic_vector(15 downto 0); -- byte address
Q_OPC : out std_logic_vector(31 downto 0);
Q_PC : out std_logic_vector(15 downto 0);
Q_PM_DOUT : out std_logic_vector( 7 downto 0));
end prog_mem;
architecture Behavioral of prog_mem is
constant zero_256 : bit_vector := X"00000000000000000000000000000000"
& X"00000000000000000000000000000000";
signal M_OPC_E1 : std_logic_vector(15 downto 0);
signal M_OPC_E2 : std_logic_vector(15 downto 0);
signal M_OPC_O1 : std_logic_vector(15 downto 0);
signal M_OPC_O2 : std_logic_vector(15 downto 0);
signal M_PMD_E1 : std_logic_vector(15 downto 0);
signal M_PMD_E2 : std_logic_vector(15 downto 0);
signal M_PMD_O1 : std_logic_vector(15 downto 0);
signal M_PMD_O2 : std_logic_vector(15 downto 0);
signal L_WAIT_N : std_logic;
signal L_PC_0 : std_logic;
signal L_PC_11 : std_logic;
signal L_PC_E : std_logic_vector(10 downto 1);
signal L_PC_O : std_logic_vector(10 downto 1);
signal L_PMD : std_logic_vector(15 downto 0);
signal L_PM_ADR_1_0 : std_logic_vector( 1 downto 0);
signal L_PM_ADR_12 : std_logic;
begin
pe1 : RAMB16_S18_S18
generic map(INIT_00 => p0_00, INIT_01 => p0_01, INIT_02 => p0_02,
INIT_03 => p0_03, INIT_04 => p0_04, INIT_05 => p0_05,
INIT_06 => p0_06, INIT_07 => p0_07, INIT_08 => p0_08,
INIT_09 => p0_09, INIT_0A => p0_0A, INIT_0B => p0_0B,
INIT_0C => p0_0C, INIT_0D => p0_0D, INIT_0E => p0_0E,
INIT_0F => p0_0F,
INIT_10 => p0_10, INIT_11 => p0_11, INIT_12 => p0_12,
INIT_13 => p0_13, INIT_14 => p0_14, INIT_15 => p0_15,
INIT_16 => p0_16, INIT_17 => p0_17, INIT_18 => p0_18,
INIT_19 => p0_19, INIT_1A => p0_1A, INIT_1B => p0_1B,
INIT_1C => p0_1C, INIT_1D => p0_1D, INIT_1E => p0_1E,
INIT_1F => p0_1F,
INIT_20 => p0_20, INIT_21 => p0_21, INIT_22 => p0_22,
INIT_23 => p0_23, INIT_24 => p0_24, INIT_25 => p0_25,
INIT_26 => p0_26, INIT_27 => p0_27, INIT_28 => p0_28,
INIT_29 => p0_29, INIT_2A => p0_2A, INIT_2B => p0_2B,
INIT_2C => p0_2C, INIT_2D => p0_2D, INIT_2E => p0_2E,
INIT_2F => p0_2F,
INIT_30 => p0_30, INIT_31 => p0_31, INIT_32 => p0_32,
INIT_33 => p0_33, INIT_34 => p0_34, INIT_35 => p0_35,
INIT_36 => p0_36, INIT_37 => p0_37, INIT_38 => p0_38,
INIT_39 => p0_39, INIT_3A => p0_3A, INIT_3B => p0_3B,
INIT_3C => p0_3C, INIT_3D => p0_3D, INIT_3E => p0_3E,
INIT_3F => p0_3F)
port map(ADDRA => L_PC_E, ADDRB => I_PM_ADR(11 downto 2),
CLKA => I_CLK, CLKB => I_CLK,
DIA => "0000000000000000", DIB => "0000000000000000",
ENA => L_WAIT_N, ENB => '1',
SSRA => '0', SSRB => '0',
WEA => '0', WEB => '0',
DOA => M_OPC_E1, DOB => M_PMD_E1,
DOPA => open, DOPB => open,
DIPA => "00", DIPB => "00");
pe2 : RAMB16_S18_S18
generic map(INIT_00 => p0_00, INIT_01 => p0_01, INIT_02 => p0_02,
INIT_03 => p0_03, INIT_04 => p0_04, INIT_05 => p0_05,
INIT_06 => p0_06, INIT_07 => p0_07, INIT_08 => p0_08,
INIT_09 => p0_09, INIT_0A => p0_0A, INIT_0B => p0_0B,
INIT_0C => p0_0C, INIT_0D => p0_0D, INIT_0E => p0_0E,
INIT_0F => p0_0F,
INIT_10 => p0_10, INIT_11 => p0_11, INIT_12 => p0_12,
INIT_13 => p0_13, INIT_14 => p0_14, INIT_15 => p0_15,
INIT_16 => p0_16, INIT_17 => p0_17, INIT_18 => p0_18,
INIT_19 => p0_19, INIT_1A => p0_1A, INIT_1B => p0_1B,
INIT_1C => p0_1C, INIT_1D => p0_1D, INIT_1E => p0_1E,
INIT_1F => p0_1F,
INIT_20 => p0_20, INIT_21 => p0_21, INIT_22 => p0_22,
INIT_23 => p0_23, INIT_24 => p0_24, INIT_25 => p0_25,
INIT_26 => p0_26, INIT_27 => p0_27, INIT_28 => p0_28,
INIT_29 => p0_29, INIT_2A => p0_2A, INIT_2B => p0_2B,
INIT_2C => p0_2C, INIT_2D => p0_2D, INIT_2E => p0_2E,
INIT_2F => p0_2F,
INIT_30 => p0_30, INIT_31 => p0_31, INIT_32 => p0_32,
INIT_33 => p0_33, INIT_34 => p0_34, INIT_35 => p0_35,
INIT_36 => p0_36, INIT_37 => p0_37, INIT_38 => p0_38,
INIT_39 => p0_39, INIT_3A => p0_3A, INIT_3B => p0_3B,
INIT_3C => p0_3C, INIT_3D => p0_3D, INIT_3E => p0_3E,
INIT_3F => p0_3F)
port map(ADDRA => L_PC_E, ADDRB => I_PM_ADR(11 downto 2),
CLKA => I_CLK, CLKB => I_CLK,
DIA => "0000000000000000", DIB => "0000000000000000",
ENA => L_WAIT_N, ENB => '1',
SSRA => '0', SSRB => '0',
WEA => '0', WEB => '0',
DOA => M_OPC_E2, DOB => M_PMD_E2,
DOPA => open, DOPB => open,
DIPA => "00", DIPB => "00");
po1 : RAMB16_S18_S18
generic map(INIT_00 => p1_00, INIT_01 => p1_01, INIT_02 => p1_02,
INIT_03 => p1_03, INIT_04 => p1_04, INIT_05 => p1_05,
INIT_06 => p1_06, INIT_07 => p1_07, INIT_08 => p1_08,
INIT_09 => p1_09, INIT_0A => p1_0A, INIT_0B => p1_0B,
INIT_0C => p1_0C, INIT_0D => p1_0D, INIT_0E => p1_0E,
INIT_0F => p1_0F,
INIT_10 => p1_10, INIT_11 => p1_11, INIT_12 => p1_12,
INIT_13 => p1_13, INIT_14 => p1_14, INIT_15 => p1_15,
INIT_16 => p1_16, INIT_17 => p1_17, INIT_18 => p1_18,
INIT_19 => p1_19, INIT_1A => p1_1A, INIT_1B => p1_1B,
INIT_1C => p1_1C, INIT_1D => p1_1D, INIT_1E => p1_1E,
INIT_1F => p1_1F,
INIT_20 => p1_20, INIT_21 => p1_21, INIT_22 => p1_22,
INIT_23 => p1_23, INIT_24 => p1_24, INIT_25 => p1_25,
INIT_26 => p1_26, INIT_27 => p1_27, INIT_28 => p1_28,
INIT_29 => p1_29, INIT_2A => p1_2A, INIT_2B => p1_2B,
INIT_2C => p1_2C, INIT_2D => p1_2D, INIT_2E => p1_2E,
INIT_2F => p1_2F,
INIT_30 => p1_30, INIT_31 => p1_31, INIT_32 => p1_32,
INIT_33 => p1_33, INIT_34 => p1_34, INIT_35 => p1_35,
INIT_36 => p1_36, INIT_37 => p1_37, INIT_38 => p1_38,
INIT_39 => p1_39, INIT_3A => p1_3A, INIT_3B => p1_3B,
INIT_3C => p1_3C, INIT_3D => p1_3D, INIT_3E => p1_3E,
INIT_3F => p1_3F)
port map(ADDRA => L_PC_O, ADDRB => I_PM_ADR(11 downto 2),
CLKA => I_CLK, CLKB => I_CLK,
DIA => "0000000000000000", DIB => "0000000000000000",
ENA => L_WAIT_N, ENB => '1',
SSRA => '0', SSRB => '0',
WEA => '0', WEB => '0',
DOA => M_OPC_O1, DOB => M_PMD_O1,
DOPA => open, DOPB => open,
DIPA => "00", DIPB => "00");
po2 : RAMB16_S18_S18
generic map(INIT_00 => p1_00, INIT_01 => p1_01, INIT_02 => p1_02,
INIT_03 => p1_03, INIT_04 => p1_04, INIT_05 => p1_05,
INIT_06 => p1_06, INIT_07 => p1_07, INIT_08 => p1_08,
INIT_09 => p1_09, INIT_0A => p1_0A, INIT_0B => p1_0B,
INIT_0C => p1_0C, INIT_0D => p1_0D, INIT_0E => p1_0E,
INIT_0F => p1_0F,
INIT_10 => p1_10, INIT_11 => p1_11, INIT_12 => p1_12,
INIT_13 => p1_13, INIT_14 => p1_14, INIT_15 => p1_15,
INIT_16 => p1_16, INIT_17 => p1_17, INIT_18 => p1_18,
INIT_19 => p1_19, INIT_1A => p1_1A, INIT_1B => p1_1B,
INIT_1C => p1_1C, INIT_1D => p1_1D, INIT_1E => p1_1E,
INIT_1F => p1_1F,
INIT_20 => p1_20, INIT_21 => p1_21, INIT_22 => p1_22,
INIT_23 => p1_23, INIT_24 => p1_24, INIT_25 => p1_25,
INIT_26 => p1_26, INIT_27 => p1_27, INIT_28 => p1_28,
INIT_29 => p1_29, INIT_2A => p1_2A, INIT_2B => p1_2B,
INIT_2C => p1_2C, INIT_2D => p1_2D, INIT_2E => p1_2E,
INIT_2F => p1_2F,
INIT_30 => p1_30, INIT_31 => p1_31, INIT_32 => p1_32,
INIT_33 => p1_33, INIT_34 => p1_34, INIT_35 => p1_35,
INIT_36 => p1_36, INIT_37 => p1_37, INIT_38 => p1_38,
INIT_39 => p1_39, INIT_3A => p1_3A, INIT_3B => p1_3B,
INIT_3C => p1_3C, INIT_3D => p1_3D, INIT_3E => p1_3E,
INIT_3F => p1_3F)
port map(ADDRA => L_PC_O, ADDRB => I_PM_ADR(11 downto 2),
CLKA => I_CLK, CLKB => I_CLK,
DIA => "0000000000000000", DIB => "0000000000000000",
ENA => L_WAIT_N, ENB => '1',
SSRA => '0', SSRB => '0',
WEA => '0', WEB => '0',
DOA => M_OPC_O2, DOB => M_PMD_O2,
DOPA => open, DOPB => open,
DIPA => "00", DIPB => "00");
-- remember I_PC0 and I_PM_ADR for the output mux.
--
pc0: process(I_CLK)
begin
if (rising_edge(I_CLK)) then
Q_PC <= I_PC;
L_PM_ADR_1_0 <= I_PM_ADR(1 downto 0);
L_PM_ADR_12 <= I_PM_ADR(12);
if ((I_WAIT = '0')) then
L_PC_0 <= I_PC(0);
L_PC_11 <= I_PC(11);
end if;
end if;
end process;
L_WAIT_N <= not I_WAIT;
-- we use two memory blocks _E and _O (even and odd).
-- This gives us a quad-port memory so that we can access
-- I_PC, I_PC + 1, and PM simultaneously.
--
-- I_PC and I_PC + 1 are handled by port A of the memory while PM
-- is handled by port B.
--
-- Q_OPC(15 ... 0) shall contain the word addressed by I_PC, while
-- Q_OPC(31 ... 16) shall contain the word addressed by I_PC + 1.
--
-- There are two cases:
--
-- case A: I_PC is even, thus I_PC + 1 is odd
-- case B: I_PC + 1 is odd , thus I_PC is even
--
L_PC_O <= I_PC(10 downto 1);
L_PC_E <= I_PC(10 downto 1) + ("000000000" & I_PC(0));
Q_OPC(15 downto 0) <= M_OPC_E1 when L_PC_11 = '0' and L_PC_0 = '0' else
M_OPC_E2 when L_PC_11 = '1' and L_PC_0 = '0' else
M_OPC_O1 when L_PC_11 = '0' and L_PC_0 = '1' else
M_OPC_O2;
Q_OPC(31 downto 16) <= M_OPC_E1 when L_PC_11 = '0' and L_PC_0 = '1' else
M_OPC_E2 when L_PC_11 = '1' and L_PC_0 = '1' else
M_OPC_O1 when L_PC_11 = '0' and L_PC_0 = '0' else
M_OPC_O2;
--Q_OPC(15 downto 0) <= M_OPC_E when L_PC_0 = '0' else M_OPC_O;
--Q_OPC(31 downto 16) <= M_OPC_E when L_PC_0 = '1' else M_OPC_O;
L_PMD <= M_PMD_E1 when L_PM_ADR_12 = '0' and L_PM_ADR_1_0(1) = '0' else
M_PMD_O1 when L_PM_ADR_12 = '0' and L_PM_ADR_1_0(1) = '1' else
M_PMD_E2 when L_PM_ADR_12 = '1' and L_PM_ADR_1_0(1) = '0' else
M_PMD_O2;
--L_PMD <= M_PMD_E when (L_PM_ADR_1_0(1) = '0') else M_PMD_O;
Q_PM_DOUT <= L_PMD(7 downto 0) when (L_PM_ADR_1_0(0) = '0')
else L_PMD(15 downto 8);
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: prog_mem - Behavioral
-- Create Date: 14:09:04 10/30/2009
-- Description: the program memory of a CPU.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
-- the content of the program memory.
--
use work.prog_mem_content.all;
entity prog_mem is
port ( I_CLK : in std_logic;
I_WAIT : in std_logic;
I_PC : in std_logic_vector(15 downto 0); -- word address
I_PM_ADR : in std_logic_vector(15 downto 0); -- byte address
Q_OPC : out std_logic_vector(31 downto 0);
Q_PC : out std_logic_vector(15 downto 0);
Q_PM_DOUT : out std_logic_vector( 7 downto 0));
end prog_mem;
architecture Behavioral of prog_mem is
constant zero_256 : bit_vector := X"00000000000000000000000000000000"
& X"00000000000000000000000000000000";
signal M_OPC_E1 : std_logic_vector(15 downto 0);
signal M_OPC_E2 : std_logic_vector(15 downto 0);
signal M_OPC_O1 : std_logic_vector(15 downto 0);
signal M_OPC_O2 : std_logic_vector(15 downto 0);
signal M_PMD_E1 : std_logic_vector(15 downto 0);
signal M_PMD_E2 : std_logic_vector(15 downto 0);
signal M_PMD_O1 : std_logic_vector(15 downto 0);
signal M_PMD_O2 : std_logic_vector(15 downto 0);
signal L_WAIT_N : std_logic;
signal L_PC_0 : std_logic;
signal L_PC_11 : std_logic;
signal L_PC_E : std_logic_vector(10 downto 1);
signal L_PC_O : std_logic_vector(10 downto 1);
signal L_PMD : std_logic_vector(15 downto 0);
signal L_PM_ADR_1_0 : std_logic_vector( 1 downto 0);
signal L_PM_ADR_12 : std_logic;
begin
pe1 : RAMB16_S18_S18
generic map(INIT_00 => p0_00, INIT_01 => p0_01, INIT_02 => p0_02,
INIT_03 => p0_03, INIT_04 => p0_04, INIT_05 => p0_05,
INIT_06 => p0_06, INIT_07 => p0_07, INIT_08 => p0_08,
INIT_09 => p0_09, INIT_0A => p0_0A, INIT_0B => p0_0B,
INIT_0C => p0_0C, INIT_0D => p0_0D, INIT_0E => p0_0E,
INIT_0F => p0_0F,
INIT_10 => p0_10, INIT_11 => p0_11, INIT_12 => p0_12,
INIT_13 => p0_13, INIT_14 => p0_14, INIT_15 => p0_15,
INIT_16 => p0_16, INIT_17 => p0_17, INIT_18 => p0_18,
INIT_19 => p0_19, INIT_1A => p0_1A, INIT_1B => p0_1B,
INIT_1C => p0_1C, INIT_1D => p0_1D, INIT_1E => p0_1E,
INIT_1F => p0_1F,
INIT_20 => p0_20, INIT_21 => p0_21, INIT_22 => p0_22,
INIT_23 => p0_23, INIT_24 => p0_24, INIT_25 => p0_25,
INIT_26 => p0_26, INIT_27 => p0_27, INIT_28 => p0_28,
INIT_29 => p0_29, INIT_2A => p0_2A, INIT_2B => p0_2B,
INIT_2C => p0_2C, INIT_2D => p0_2D, INIT_2E => p0_2E,
INIT_2F => p0_2F,
INIT_30 => p0_30, INIT_31 => p0_31, INIT_32 => p0_32,
INIT_33 => p0_33, INIT_34 => p0_34, INIT_35 => p0_35,
INIT_36 => p0_36, INIT_37 => p0_37, INIT_38 => p0_38,
INIT_39 => p0_39, INIT_3A => p0_3A, INIT_3B => p0_3B,
INIT_3C => p0_3C, INIT_3D => p0_3D, INIT_3E => p0_3E,
INIT_3F => p0_3F)
port map(ADDRA => L_PC_E, ADDRB => I_PM_ADR(11 downto 2),
CLKA => I_CLK, CLKB => I_CLK,
DIA => "0000000000000000", DIB => "0000000000000000",
ENA => L_WAIT_N, ENB => '1',
SSRA => '0', SSRB => '0',
WEA => '0', WEB => '0',
DOA => M_OPC_E1, DOB => M_PMD_E1,
DOPA => open, DOPB => open,
DIPA => "00", DIPB => "00");
pe2 : RAMB16_S18_S18
generic map(INIT_00 => p0_00, INIT_01 => p0_01, INIT_02 => p0_02,
INIT_03 => p0_03, INIT_04 => p0_04, INIT_05 => p0_05,
INIT_06 => p0_06, INIT_07 => p0_07, INIT_08 => p0_08,
INIT_09 => p0_09, INIT_0A => p0_0A, INIT_0B => p0_0B,
INIT_0C => p0_0C, INIT_0D => p0_0D, INIT_0E => p0_0E,
INIT_0F => p0_0F,
INIT_10 => p0_10, INIT_11 => p0_11, INIT_12 => p0_12,
INIT_13 => p0_13, INIT_14 => p0_14, INIT_15 => p0_15,
INIT_16 => p0_16, INIT_17 => p0_17, INIT_18 => p0_18,
INIT_19 => p0_19, INIT_1A => p0_1A, INIT_1B => p0_1B,
INIT_1C => p0_1C, INIT_1D => p0_1D, INIT_1E => p0_1E,
INIT_1F => p0_1F,
INIT_20 => p0_20, INIT_21 => p0_21, INIT_22 => p0_22,
INIT_23 => p0_23, INIT_24 => p0_24, INIT_25 => p0_25,
INIT_26 => p0_26, INIT_27 => p0_27, INIT_28 => p0_28,
INIT_29 => p0_29, INIT_2A => p0_2A, INIT_2B => p0_2B,
INIT_2C => p0_2C, INIT_2D => p0_2D, INIT_2E => p0_2E,
INIT_2F => p0_2F,
INIT_30 => p0_30, INIT_31 => p0_31, INIT_32 => p0_32,
INIT_33 => p0_33, INIT_34 => p0_34, INIT_35 => p0_35,
INIT_36 => p0_36, INIT_37 => p0_37, INIT_38 => p0_38,
INIT_39 => p0_39, INIT_3A => p0_3A, INIT_3B => p0_3B,
INIT_3C => p0_3C, INIT_3D => p0_3D, INIT_3E => p0_3E,
INIT_3F => p0_3F)
port map(ADDRA => L_PC_E, ADDRB => I_PM_ADR(11 downto 2),
CLKA => I_CLK, CLKB => I_CLK,
DIA => "0000000000000000", DIB => "0000000000000000",
ENA => L_WAIT_N, ENB => '1',
SSRA => '0', SSRB => '0',
WEA => '0', WEB => '0',
DOA => M_OPC_E2, DOB => M_PMD_E2,
DOPA => open, DOPB => open,
DIPA => "00", DIPB => "00");
po1 : RAMB16_S18_S18
generic map(INIT_00 => p1_00, INIT_01 => p1_01, INIT_02 => p1_02,
INIT_03 => p1_03, INIT_04 => p1_04, INIT_05 => p1_05,
INIT_06 => p1_06, INIT_07 => p1_07, INIT_08 => p1_08,
INIT_09 => p1_09, INIT_0A => p1_0A, INIT_0B => p1_0B,
INIT_0C => p1_0C, INIT_0D => p1_0D, INIT_0E => p1_0E,
INIT_0F => p1_0F,
INIT_10 => p1_10, INIT_11 => p1_11, INIT_12 => p1_12,
INIT_13 => p1_13, INIT_14 => p1_14, INIT_15 => p1_15,
INIT_16 => p1_16, INIT_17 => p1_17, INIT_18 => p1_18,
INIT_19 => p1_19, INIT_1A => p1_1A, INIT_1B => p1_1B,
INIT_1C => p1_1C, INIT_1D => p1_1D, INIT_1E => p1_1E,
INIT_1F => p1_1F,
INIT_20 => p1_20, INIT_21 => p1_21, INIT_22 => p1_22,
INIT_23 => p1_23, INIT_24 => p1_24, INIT_25 => p1_25,
INIT_26 => p1_26, INIT_27 => p1_27, INIT_28 => p1_28,
INIT_29 => p1_29, INIT_2A => p1_2A, INIT_2B => p1_2B,
INIT_2C => p1_2C, INIT_2D => p1_2D, INIT_2E => p1_2E,
INIT_2F => p1_2F,
INIT_30 => p1_30, INIT_31 => p1_31, INIT_32 => p1_32,
INIT_33 => p1_33, INIT_34 => p1_34, INIT_35 => p1_35,
INIT_36 => p1_36, INIT_37 => p1_37, INIT_38 => p1_38,
INIT_39 => p1_39, INIT_3A => p1_3A, INIT_3B => p1_3B,
INIT_3C => p1_3C, INIT_3D => p1_3D, INIT_3E => p1_3E,
INIT_3F => p1_3F)
port map(ADDRA => L_PC_O, ADDRB => I_PM_ADR(11 downto 2),
CLKA => I_CLK, CLKB => I_CLK,
DIA => "0000000000000000", DIB => "0000000000000000",
ENA => L_WAIT_N, ENB => '1',
SSRA => '0', SSRB => '0',
WEA => '0', WEB => '0',
DOA => M_OPC_O1, DOB => M_PMD_O1,
DOPA => open, DOPB => open,
DIPA => "00", DIPB => "00");
po2 : RAMB16_S18_S18
generic map(INIT_00 => p1_00, INIT_01 => p1_01, INIT_02 => p1_02,
INIT_03 => p1_03, INIT_04 => p1_04, INIT_05 => p1_05,
INIT_06 => p1_06, INIT_07 => p1_07, INIT_08 => p1_08,
INIT_09 => p1_09, INIT_0A => p1_0A, INIT_0B => p1_0B,
INIT_0C => p1_0C, INIT_0D => p1_0D, INIT_0E => p1_0E,
INIT_0F => p1_0F,
INIT_10 => p1_10, INIT_11 => p1_11, INIT_12 => p1_12,
INIT_13 => p1_13, INIT_14 => p1_14, INIT_15 => p1_15,
INIT_16 => p1_16, INIT_17 => p1_17, INIT_18 => p1_18,
INIT_19 => p1_19, INIT_1A => p1_1A, INIT_1B => p1_1B,
INIT_1C => p1_1C, INIT_1D => p1_1D, INIT_1E => p1_1E,
INIT_1F => p1_1F,
INIT_20 => p1_20, INIT_21 => p1_21, INIT_22 => p1_22,
INIT_23 => p1_23, INIT_24 => p1_24, INIT_25 => p1_25,
INIT_26 => p1_26, INIT_27 => p1_27, INIT_28 => p1_28,
INIT_29 => p1_29, INIT_2A => p1_2A, INIT_2B => p1_2B,
INIT_2C => p1_2C, INIT_2D => p1_2D, INIT_2E => p1_2E,
INIT_2F => p1_2F,
INIT_30 => p1_30, INIT_31 => p1_31, INIT_32 => p1_32,
INIT_33 => p1_33, INIT_34 => p1_34, INIT_35 => p1_35,
INIT_36 => p1_36, INIT_37 => p1_37, INIT_38 => p1_38,
INIT_39 => p1_39, INIT_3A => p1_3A, INIT_3B => p1_3B,
INIT_3C => p1_3C, INIT_3D => p1_3D, INIT_3E => p1_3E,
INIT_3F => p1_3F)
port map(ADDRA => L_PC_O, ADDRB => I_PM_ADR(11 downto 2),
CLKA => I_CLK, CLKB => I_CLK,
DIA => "0000000000000000", DIB => "0000000000000000",
ENA => L_WAIT_N, ENB => '1',
SSRA => '0', SSRB => '0',
WEA => '0', WEB => '0',
DOA => M_OPC_O2, DOB => M_PMD_O2,
DOPA => open, DOPB => open,
DIPA => "00", DIPB => "00");
-- remember I_PC0 and I_PM_ADR for the output mux.
--
pc0: process(I_CLK)
begin
if (rising_edge(I_CLK)) then
Q_PC <= I_PC;
L_PM_ADR_1_0 <= I_PM_ADR(1 downto 0);
L_PM_ADR_12 <= I_PM_ADR(12);
if ((I_WAIT = '0')) then
L_PC_0 <= I_PC(0);
L_PC_11 <= I_PC(11);
end if;
end if;
end process;
L_WAIT_N <= not I_WAIT;
-- we use two memory blocks _E and _O (even and odd).
-- This gives us a quad-port memory so that we can access
-- I_PC, I_PC + 1, and PM simultaneously.
--
-- I_PC and I_PC + 1 are handled by port A of the memory while PM
-- is handled by port B.
--
-- Q_OPC(15 ... 0) shall contain the word addressed by I_PC, while
-- Q_OPC(31 ... 16) shall contain the word addressed by I_PC + 1.
--
-- There are two cases:
--
-- case A: I_PC is even, thus I_PC + 1 is odd
-- case B: I_PC + 1 is odd , thus I_PC is even
--
L_PC_O <= I_PC(10 downto 1);
L_PC_E <= I_PC(10 downto 1) + ("000000000" & I_PC(0));
Q_OPC(15 downto 0) <= M_OPC_E1 when L_PC_11 = '0' and L_PC_0 = '0' else
M_OPC_E2 when L_PC_11 = '1' and L_PC_0 = '0' else
M_OPC_O1 when L_PC_11 = '0' and L_PC_0 = '1' else
M_OPC_O2;
Q_OPC(31 downto 16) <= M_OPC_E1 when L_PC_11 = '0' and L_PC_0 = '1' else
M_OPC_E2 when L_PC_11 = '1' and L_PC_0 = '1' else
M_OPC_O1 when L_PC_11 = '0' and L_PC_0 = '0' else
M_OPC_O2;
--Q_OPC(15 downto 0) <= M_OPC_E when L_PC_0 = '0' else M_OPC_O;
--Q_OPC(31 downto 16) <= M_OPC_E when L_PC_0 = '1' else M_OPC_O;
L_PMD <= M_PMD_E1 when L_PM_ADR_12 = '0' and L_PM_ADR_1_0(1) = '0' else
M_PMD_O1 when L_PM_ADR_12 = '0' and L_PM_ADR_1_0(1) = '1' else
M_PMD_E2 when L_PM_ADR_12 = '1' and L_PM_ADR_1_0(1) = '0' else
M_PMD_O2;
--L_PMD <= M_PMD_E when (L_PM_ADR_1_0(1) = '0') else M_PMD_O;
Q_PM_DOUT <= L_PMD(7 downto 0) when (L_PM_ADR_1_0(0) = '0')
else L_PMD(15 downto 8);
end Behavioral;
|
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 <[email protected]>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use work.pp_types.all;
use work.pp_constants.all;
package pp_utilities is
--! Converts a boolean to an std_logic.
function to_std_logic(input : in boolean) return std_logic;
-- Checks if a number is 2^n:
function is_pow2(input : in natural) return boolean;
--! Calculates log2 with integers.
function log2(input : in natural) return natural;
-- Gets the value of the sel signals to the wishbone interconnect for the specified
-- operand size and address.
function wb_get_data_sel(size : in std_logic_vector(1 downto 0); address : in std_logic_vector)
return std_logic_vector;
end package pp_utilities;
package body pp_utilities is
function to_std_logic(input : in boolean) return std_logic is
begin
if input then
return '1';
else
return '0';
end if;
end function to_std_logic;
function is_pow2(input : in natural) return boolean is
variable c : natural := 1;
begin
for i in 0 to 31 loop
if input = c then
return true;
end if;
c := c * 2;
end loop;
return false;
end function is_pow2;
function log2(input : in natural) return natural is
variable retval : natural := 0;
variable temp : natural := input;
begin
while temp > 1 loop
retval := retval + 1;
temp := temp / 2;
end loop;
return retval;
end function log2;
function wb_get_data_sel(size : in std_logic_vector(1 downto 0); address : in std_logic_vector)
return std_logic_vector is
begin
case size is
when b"01" =>
case address(1 downto 0) is
when b"00" =>
return b"0001";
when b"01" =>
return b"0010";
when b"10" =>
return b"0100";
when b"11" =>
return b"1000";
when others =>
return b"0001";
end case;
when b"10" =>
if address(1) = '0' then
return b"0011";
else
return b"1100";
end if;
when others =>
return b"1111";
end case;
end function wb_get_data_sel;
end package body pp_utilities;
|
-------------------------------------------------------------------------------
-- $Id: blk_mem_gen_wrapper.vhd,v 1.1.2.69 2010/12/17 19:23:25 dougt Exp $
-------------------------------------------------------------------------------
-- blk_mem_gen_wrapper.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ****************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008, 2009. 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ****************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: blk_mem_gen_wrapper.vhd
-- Version: v1.00a
-- Description:
-- This wrapper file performs the direct call to Block Memory Generator
-- during design implementation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- blk_mem_gen_wrapper.vhd
-- |
-- |-- blk_mem_gen_v2_7
-- |
-- |-- blk_mem_gen_v6_2
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: MW
-- Revision: $Revision: 1.1.2.69 $
-- Date: $7/11/2008$
--
-- History:
-- MW 7/11/2008 Initial Version
-- MSH 2/26/2009 Add new blk_mem_gen version
--
-- DET 4/8/2009 EDK 11.2
-- ~~~~~~
-- - Added blk_mem_gen_v3_2 instance callout
-- ^^^^^^
--
-- DET 2/9/2010 for EDK 12.1
-- ~~~~~~
-- - Updated the the Blk Mem Gen version from blk_mem_gen_v3_2
-- to blk_mem_gen_v3_3 (for the S6/V6 IfGen case)
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Updated the the Blk Mem Gen version from blk_mem_gen_v3_3
-- to blk_mem_gen_v4_1 (for the S6/V6 IfGen case)
-- ^^^^^^
--
-- DET 3/17/2010 Initial
-- ~~~~~~
-- -- Per CR554253
-- - Incorporated changes to comment out FLOP_DELAY parameter from the
-- blk_mem_gen_v4_1 instance. This parameter is on the XilinxCoreLib
-- model for blk_mem_gen_v4_1 but is declared as a TIME type for the
-- vhdl version and an integer for the verilog.
-- ^^^^^^
--
-- DET 6/18/2010 EDK_MS2
-- ~~~~~~
-- -- Per IR565916
-- - Added constants FAM_IS_V6_OR_S6 and FAM_IS_NOT_V6_OR_S6.
-- - Added derivative part type checks for S6 or V6.
-- ^^^^^^
--
-- DET 8/27/2010 EDK 12.4
-- ~~~~~~
-- -- Per CR573867
-- - Added the the Blk Mem Gen version blk_mem_gen_v4_3 for the S6/V6
-- and later build case.
-- - Updated method for derivative part support using new family
-- aliasing function in family_support.vhd.
-- - Incorporated an implementation to deal with unsupported FPGA
-- parts passed in on the C_FAMILY parameter.
-- ^^^^^^
--
-- DET 10/4/2010 EDK 13.1
-- ~~~~~~
-- - Updated to blk_mem_gen V5.2.
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Updated to blk_mem_gen V6.1
-- ^^^^^^
--
-- DET 12/17/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR587494
-- - Regressed back to blk_mem_gen V5.2
-- ^^^^^^
--
-- DET 3/2/2011 EDk 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use blk_mem_gen_v6_2 for s6, v6, and later.
-- ^^^^^^
--
-- DET 3/3/2011 EDK 13.2
-- ~~~~~~
-- - Removed C_ELABORATION_DIR parameter from the blk_mem_gen_v6_2
-- instance.
-- ^^^^^^
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synopsys translate_off
Library XilinxCoreLib;
-- synopsys translate_on
library proc_common_v3_00_a;
use proc_common_v3_00_a.coregen_comp_defs.all;
use proc_common_v3_00_a.family_support.all;
------------------------------------------------------------------------------
-- Port Declaration
------------------------------------------------------------------------------
entity blk_mem_gen_wrapper is
generic
(
-- Device Family
c_family : string := "virtex5";
-- "Virtex2"
-- "Virtex4"
-- "Virtex5"
c_xdevicefamily : string := "virtex5";
-- Finest Resolution Device Family
-- "Virtex2"
-- "Virtex2-Pro"
-- "Virtex4"
-- "Virtex5"
-- "Spartan-3A"
-- "Spartan-3A DSP"
-- Memory Specific Configurations
c_mem_type : integer := 2;
-- This wrapper only supports the True Dual Port RAM
-- 0: Single Port RAM
-- 1: Simple Dual Port RAM
-- 2: True Dual Port RAM
-- 3: Single Port Rom
-- 4: Dual Port RAM
c_algorithm : integer := 1;
-- 0: Selectable Primative
-- 1: Minimum Area
c_prim_type : integer := 1;
-- 0: ( 1-bit wide)
-- 1: ( 2-bit wide)
-- 2: ( 4-bit wide)
-- 3: ( 9-bit wide)
-- 4: (18-bit wide)
-- 5: (36-bit wide)
-- 6: (72-bit wide, single port only)
c_byte_size : integer := 9; -- 8 or 9
-- Simulation Behavior Options
c_sim_collision_check : string := "NONE";
-- "None"
-- "Generate_X"
-- "All"
-- "Warnings_only"
c_common_clk : integer := 1; -- 0, 1
c_disable_warn_bhv_coll : integer := 0; -- 0, 1
c_disable_warn_bhv_range : integer := 0; -- 0, 1
-- Initialization Configuration Options
c_load_init_file : integer := 0;
c_init_file_name : string := "no_coe_file_loaded";
c_use_default_data : integer := 0; -- 0, 1
c_default_data : string := "0"; -- "..."
-- Port A Specific Configurations
c_has_mem_output_regs_a : integer := 0; -- 0, 1
c_has_mux_output_regs_a : integer := 0; -- 0, 1
c_write_width_a : integer := 32; -- 1 to 1152
c_read_width_a : integer := 32; -- 1 to 1152
c_write_depth_a : integer := 64; -- 2 to 9011200
c_read_depth_a : integer := 64; -- 2 to 9011200
c_addra_width : integer := 6; -- 1 to 24
c_write_mode_a : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_ena : integer := 1; -- 0, 1
c_has_regcea : integer := 0; -- 0, 1
c_has_ssra : integer := 0; -- 0, 1
c_sinita_val : string := "0"; --"..."
c_use_byte_wea : integer := 0; -- 0, 1
c_wea_width : integer := 1; -- 1 to 128
-- Port B Specific Configurations
c_has_mem_output_regs_b : integer := 0; -- 0, 1
c_has_mux_output_regs_b : integer := 0; -- 0, 1
c_write_width_b : integer := 32; -- 1 to 1152
c_read_width_b : integer := 32; -- 1 to 1152
c_write_depth_b : integer := 64; -- 2 to 9011200
c_read_depth_b : integer := 64; -- 2 to 9011200
c_addrb_width : integer := 6; -- 1 to 24
c_write_mode_b : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_enb : integer := 1; -- 0, 1
c_has_regceb : integer := 0; -- 0, 1
c_has_ssrb : integer := 0; -- 0, 1
c_sinitb_val : string := "0"; -- "..."
c_use_byte_web : integer := 0; -- 0, 1
c_web_width : integer := 1; -- 1 to 128
-- Other Miscellaneous Configurations
c_mux_pipeline_stages : integer := 0; -- 0, 1, 2, 3
-- The number of pipeline stages within the MUX
-- for both Port A and Port B
c_use_ecc : integer := 0;
-- See DS512 for the limited core option selections for ECC support
c_use_ramb16bwer_rst_bhv : integer := 0--; --0, 1
-- c_corename : string := "blk_mem_gen_v2_7"
--Uncommenting the above parameter (C_CORENAME) will cause
--the a failure in NGCBuild!!!
);
port
(
clka : in std_logic;
ssra : in std_logic := '0';
dina : in std_logic_vector(c_write_width_a-1 downto 0) := (OTHERS => '0');
addra : in std_logic_vector(c_addra_width-1 downto 0);
ena : in std_logic := '1';
regcea : in std_logic := '1';
wea : in std_logic_vector(c_wea_width-1 downto 0) := (OTHERS => '0');
douta : out std_logic_vector(c_read_width_a-1 downto 0);
clkb : in std_logic := '0';
ssrb : in std_logic := '0';
dinb : in std_logic_vector(c_write_width_b-1 downto 0) := (OTHERS => '0');
addrb : in std_logic_vector(c_addrb_width-1 downto 0) := (OTHERS => '0');
enb : in std_logic := '1';
regceb : in std_logic := '1';
web : in std_logic_vector(c_web_width-1 downto 0) := (OTHERS => '0');
doutb : out std_logic_vector(c_read_width_b-1 downto 0);
dbiterr : out std_logic;
-- Double bit error that that cannot be auto corrected by ECC
sbiterr : out std_logic
-- Single Bit Error that has been auto corrected on the output bus
);
end entity blk_mem_gen_wrapper;
architecture implementation of blk_mem_gen_wrapper is
Constant FAMILY_TO_USE : string := get_root_family(C_FAMILY); -- function from family_support.vhd
Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily"));
Constant FAMILY_IS_SUPPORTED : boolean := not(FAMILY_NOT_SUPPORTED);
Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or
equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or
equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and
FAMILY_IS_SUPPORTED;
Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and
FAMILY_IS_SUPPORTED;
begin
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_FAMILY
--
-- If Generate Description:
-- This IfGen is implemented if an unsupported FPGA family
-- is passed in on the C_FAMILY parameter,
--
------------------------------------------------------------
GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate
begin
-- synthesis translate_off
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_ASSERTION
--
-- Process Description:
-- Generate a simulation error assertion for an unsupported
-- FPGA family string passed in on the C_FAMILY parameter.
--
-------------------------------------------------------------
DO_ASSERTION : process
begin
-- Wait until second rising clock edge to issue assertion
Wait until clka = '1';
wait until clka = '0';
Wait until clka = '1';
-- Report an error in simulation environment
assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!"
severity ERROR;
Wait; -- halt this process
end process DO_ASSERTION;
-- synthesis translate_on
-- Tie outputs to logic low
douta <= (others => '0'); -- : out std_logic_vector(c_read_width_a-1 downto 0);
doutb <= (others => '0'); -- : out std_logic_vector(c_read_width_b-1 downto 0);
dbiterr <= '0' ; -- : out std_logic;
sbiterr <= '0' ; -- : out std_logic
end generate GEN_NO_FAMILY;
------------------------------------------------------------
-- If Generate
--
-- Label: V5_AND_EARLIER
--
-- If Generate Description:
-- This IFGen Implements the Block Memeory using blk_mem_gen 2.7.
-- This is for legacy cores designed and tested with FPGA
-- Families earlier than Virtex-6 and Spartan-6.
--
------------------------------------------------------------
V5_AND_EARLIER: if(FAM_IS_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen Block Memory Generator Call module
-- for legacy BRAM implementations.
--
-------------------------------------------------------------------------------
I_TRUE_DUAL_PORT_BLK_MEM_GEN : blk_mem_gen_v2_7
generic map
(
-- Device Family
c_family => FAMILY_TO_USE ,
c_xdevicefamily => c_xdevicefamily ,
-- Memory Specific Configurations
c_mem_type => c_mem_type ,
c_algorithm => c_algorithm ,
c_prim_type => c_prim_type ,
c_byte_size => c_byte_size ,
-- Simulation Behavior Options
c_sim_collision_check => c_sim_collision_check ,
c_common_clk => c_common_clk ,
c_disable_warn_bhv_coll => c_disable_warn_bhv_coll ,
c_disable_warn_bhv_range => c_disable_warn_bhv_range,
-- Initialization Configuration Options
c_load_init_file => c_load_init_file ,
c_init_file_name => c_init_file_name ,
c_use_default_data => c_use_default_data ,
c_default_data => c_default_data ,
-- Port A Specific Configurations
c_has_mem_output_regs_a => c_has_mem_output_regs_a ,
c_has_mux_output_regs_a => c_has_mux_output_regs_a ,
c_write_width_a => c_write_width_a ,
c_read_width_a => c_read_width_a ,
c_write_depth_a => c_write_depth_a ,
c_read_depth_a => c_read_depth_a ,
c_addra_width => c_addra_width ,
c_write_mode_a => c_write_mode_a ,
c_has_ena => c_has_ena ,
c_has_regcea => c_has_regcea ,
c_has_ssra => c_has_ssra ,
c_sinita_val => c_sinita_val ,
c_use_byte_wea => c_use_byte_wea ,
c_wea_width => c_wea_width ,
-- Port B Specific Configurations
c_has_mem_output_regs_b => c_has_mem_output_regs_b ,
c_has_mux_output_regs_b => c_has_mux_output_regs_b ,
c_write_width_b => c_write_width_b ,
c_read_width_b => c_read_width_b ,
c_write_depth_b => c_write_depth_b ,
c_read_depth_b => c_read_depth_b ,
c_addrb_width => c_addrb_width ,
c_write_mode_b => c_write_mode_b ,
c_has_enb => c_has_enb ,
c_has_regceb => c_has_regceb ,
c_has_ssrb => c_has_ssrb ,
c_sinitb_val => c_sinitb_val ,
c_use_byte_web => c_use_byte_web ,
c_web_width => c_web_width ,
-- Other Miscellaneous Configurations
c_mux_pipeline_stages => c_mux_pipeline_stages ,
c_use_ecc => c_use_ecc ,
c_use_ramb16bwer_rst_bhv => c_use_ramb16bwer_rst_bhv
-- c_corename => c_corename
--Uncommenting the above parameter (C_CORENAME) will cause
--the a failure in NGCBuild!!!
)
port map
(
clka => clka,
ssra => ssra,
dina => dina,
addra => addra,
ena => ena,
regcea => regcea,
wea => wea,
douta => douta,
clkb => clkb,
ssrb => ssrb,
dinb => dinb,
addrb => addrb,
enb => enb,
regceb => regceb,
web => web,
doutb => doutb,
dbiterr => dbiterr,
sbiterr => sbiterr
);
end generate V5_AND_EARLIER;
------------------------------------------------------------
-- If Generate
--
-- Label: V6_S6_AND_LATER
--
-- If Generate Description:
-- This IFGen Implements the Block Memeory using blk_mem_gen 5.2.
-- This is for new cores designed and tested with FPGA
-- Families of Virtex-6, Spartan-6 and later.
--
------------------------------------------------------------
V6_S6_AND_LATER: if(FAM_IS_NOT_S3_V4_V5) generate
begin
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen Block Memory Generator Call module
-- for new IP BRAM implementations.
--
-------------------------------------------------------------------------------
I_TRUE_DUAL_PORT_BLK_MEM_GEN : blk_mem_gen_v7_3
generic map
(
--C_CORENAME => c_corename ,
-- Device Family
C_FAMILY => FAMILY_TO_USE ,
C_XDEVICEFAMILY => c_xdevicefamily ,
------------------
C_INTERFACE_TYPE => 0 ,
C_USE_BRAM_BLOCK => 0 ,
C_AXI_TYPE => 0 ,
C_AXI_SLAVE_TYPE => 0 ,
C_HAS_AXI_ID => 0 ,
C_AXI_ID_WIDTH => 4 ,
------------------
-- Memory Specific Configurations
C_MEM_TYPE => c_mem_type ,
C_BYTE_SIZE => c_byte_size ,
C_ALGORITHM => c_algorithm ,
C_PRIM_TYPE => c_prim_type ,
C_LOAD_INIT_FILE => c_load_init_file ,
C_INIT_FILE_NAME => c_init_file_name ,
C_INIT_FILE => "" ,
C_USE_DEFAULT_DATA => c_use_default_data ,
C_DEFAULT_DATA => c_default_data ,
-- Port A Specific Configurations
C_RST_TYPE => "SYNC" ,
C_HAS_RSTA => c_has_ssra ,
C_RST_PRIORITY_A => "CE" ,
C_RSTRAM_A => 0 ,
C_INITA_VAL => c_sinita_val ,
C_HAS_ENA => c_has_ena ,
C_HAS_REGCEA => c_has_regcea ,
C_USE_BYTE_WEA => c_use_byte_wea ,
C_WEA_WIDTH => c_wea_width ,
C_WRITE_MODE_A => c_write_mode_a ,
C_WRITE_WIDTH_A => c_write_width_a ,
C_READ_WIDTH_A => c_read_width_a ,
C_WRITE_DEPTH_A => c_write_depth_a ,
C_READ_DEPTH_A => c_read_depth_a ,
C_ADDRA_WIDTH => c_addra_width ,
-- Port B Specific Configurations
C_HAS_RSTB => c_has_ssrb ,
C_RST_PRIORITY_B => "CE" ,
C_RSTRAM_B => 0 ,
C_INITB_VAL => c_sinitb_val ,
C_HAS_ENB => c_has_enb ,
C_HAS_REGCEB => c_has_regceb ,
C_USE_BYTE_WEB => c_use_byte_web ,
C_WEB_WIDTH => c_web_width ,
C_WRITE_MODE_B => c_write_mode_b ,
C_WRITE_WIDTH_B => c_write_width_b ,
C_READ_WIDTH_B => c_read_width_b ,
C_WRITE_DEPTH_B => c_write_depth_b ,
C_READ_DEPTH_B => c_read_depth_b ,
C_ADDRB_WIDTH => c_addrb_width ,
C_HAS_MEM_OUTPUT_REGS_A => c_has_mem_output_regs_a ,
C_HAS_MEM_OUTPUT_REGS_B => c_has_mem_output_regs_b ,
C_HAS_MUX_OUTPUT_REGS_A => c_has_mux_output_regs_a ,
C_HAS_MUX_OUTPUT_REGS_B => c_has_mux_output_regs_b ,
C_HAS_SOFTECC_INPUT_REGS_A => 0 ,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0 ,
-- Other Miscellaneous Configurations
C_MUX_PIPELINE_STAGES => c_mux_pipeline_stages ,
C_USE_SOFTECC => 0 ,
C_USE_ECC => c_use_ecc ,
-- Simulation Behavior Options
C_HAS_INJECTERR => 0 ,
C_SIM_COLLISION_CHECK => c_sim_collision_check ,
C_COMMON_CLK => c_common_clk ,
C_DISABLE_WARN_BHV_COLL => c_disable_warn_bhv_coll ,
C_DISABLE_WARN_BHV_RANGE => c_disable_warn_bhv_range
)
port map
(
CLKA => clka ,
RSTA => ssra ,
ENA => ena ,
REGCEA => regcea ,
WEA => wea ,
ADDRA => addra ,
DINA => dina ,
DOUTA => douta ,
CLKB => clkb ,
RSTB => ssrb ,
ENB => enb ,
REGCEB => regceb ,
WEB => web ,
ADDRB => addrb ,
DINB => dinb ,
DOUTB => doutb ,
INJECTSBITERR => '0' , -- input
INJECTDBITERR => '0' , -- input
SBITERR => sbiterr ,
DBITERR => dbiterr ,
RDADDRECC => open , -- output
-- AXI BMG Input and Output Port Declarations -- new for v6.2
-- new for v6.2
-- AXI Global Signals -- new for v6.2
S_AClk => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_ARESETN => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Write (write side) -- new for v6.2
S_AXI_AWID => (others => '0') , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWADDR => (others => '0') , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWLEN => (others => '0') , -- : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWSIZE => (others => '0') , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWBURST => (others => '0') , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_AWVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_AWREADY => open , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_WDATA => (others => '0') , -- : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WSTRB => (others => '0') , -- : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_WLAST => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_WREADY => open , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_BID => open , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_BRESP => open , -- : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- new for v6.2
S_AXI_BVALID => open , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_BREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Slave Read (Write side) -- new for v6.2
S_AXI_ARID => (others => '0') , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARADDR => (others => '0') , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARLEN => (others => '0') , -- : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARSIZE => (others => '0') , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARBURST => (others => '0') , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_ARVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_ARREADY => open , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RID => open , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2
S_AXI_RDATA => open , -- : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); -- new for v6.2
S_AXI_RRESP => open , -- : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0); -- new for v6.2
S_AXI_RLAST => open , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RVALID => open , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
-- new for v6.2
-- AXI Full/Lite Sideband Signals -- new for v6.2
S_AXI_INJECTSBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_INJECTDBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2
S_AXI_SBITERR => open , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_DBITERR => open , -- : OUT STD_LOGIC; -- new for v6.2
S_AXI_RDADDRECC => open -- : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) -- new for v6.2
);
end generate V6_S6_AND_LATER;
end implementation;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_1;
USE blk_mem_gen_v8_3_1.blk_mem_gen_v8_3_1;
ENTITY rom IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END rom;
ARCHITECTURE rom_arch OF rom IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF rom_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF rom_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_1,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF rom_arch : ARCHITECTURE IS "rom,blk_mem_gen_v8_3_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF rom_arch: ARCHITECTURE IS "rom,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=rom.mif,C_INIT_FILE=rom.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=30720,C_READ_DEPTH_A=30720,C_ADDRA_WIDTH=15,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=30720,C_READ_DEPTH_B=30720,C_ADDRB_WIDTH=15,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=7,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.252613 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_1
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 3,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "rom.mif",
C_INIT_FILE => "rom.mem",
C_USE_DEFAULT_DATA => 1,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 30720,
C_READ_DEPTH_A => 30720,
C_ADDRA_WIDTH => 15,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 30720,
C_READ_DEPTH_B => 30720,
C_ADDRB_WIDTH => 15,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "7",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.252613 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addra => addra,
dina => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 15)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END rom_arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity indexreg is
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
loadindex: in STD_LOGIC;
readindex: in STD_LOGIC;
index: out STD_LOGIC_VECTOR (7 downto 0)
);
end indexreg;
architecture behavioral of indexreg is
signal indexreg: STD_LOGIC_VECTOR (7 downto 0);
begin
aindexreg: process(clk,
ibus,
loadindex,
readindex,
indexreg
)
begin
if clk'event and clk = '1' then
if loadindex = '1' then
indexreg <= ibus(7 downto 0);
end if;
end if;
if readindex = '1' then
obus(7 downto 0) <= indexreg;
obus(15 downto 8) <= "ZZZZZZZZ";
else
obus <= "ZZZZZZZZZZZZZZZZ";
end if;
index <= indexreg;
end process;
end behavioral;
|
entity static is
generic ( G : integer := 1 );
end entity;
architecture test of static is
begin
process is
subtype byte is bit_vector(7 downto 0);
variable bv : byte;
variable i : integer;
attribute hello : integer;
attribute hello of bv : variable is 6;
begin
case i is
when bv'length => -- OK
null;
when bv'left => -- OK
null;
when byte'right => -- OK
null;
when bv'hello => -- OK
null;
when others =>
null;
end case;
end process;
process is
variable v : bit_vector(3 downto 0);
constant c : bit_vector := "1010";
constant d : bit_vector(G downto 0) := (others => '0');
begin
case v is
when c => -- Error
null;
when others =>
null;
end case;
case v is
when d => -- Error
null;
when others =>
null;
end case;
end process;
end architecture;
-------------------------------------------------------------------------------
entity sub is
generic ( N : integer );
port ( x : bit_vector );
end entity;
architecture test of sub is
signal y : bit_vector(N - 1 downto 0) := (others => '0') ;
begin
sub_i: entity work.sub
generic map ( N => N )
port map (
x => x(x'left downto x'right) ); -- Error
gen1: for i in y'range generate -- OK
end generate;
b1: block is
type r is record
x, y : integer;
end record;
signal x : r := (1, 2);
begin
gen2: if (N, 2) = r'(1, 2) generate -- OK
end generate;
end block;
end architecture;
|
entity static is
generic ( G : integer := 1 );
end entity;
architecture test of static is
begin
process is
subtype byte is bit_vector(7 downto 0);
variable bv : byte;
variable i : integer;
attribute hello : integer;
attribute hello of bv : variable is 6;
begin
case i is
when bv'length => -- OK
null;
when bv'left => -- OK
null;
when byte'right => -- OK
null;
when bv'hello => -- OK
null;
when others =>
null;
end case;
end process;
process is
variable v : bit_vector(3 downto 0);
constant c : bit_vector := "1010";
constant d : bit_vector(G downto 0) := (others => '0');
begin
case v is
when c => -- Error
null;
when others =>
null;
end case;
case v is
when d => -- Error
null;
when others =>
null;
end case;
end process;
end architecture;
-------------------------------------------------------------------------------
entity sub is
generic ( N : integer );
port ( x : bit_vector );
end entity;
architecture test of sub is
signal y : bit_vector(N - 1 downto 0) := (others => '0') ;
begin
sub_i: entity work.sub
generic map ( N => N )
port map (
x => x(x'left downto x'right) ); -- Error
gen1: for i in y'range generate -- OK
end generate;
b1: block is
type r is record
x, y : integer;
end record;
signal x : r := (1, 2);
begin
gen2: if (N, 2) = r'(1, 2) generate -- OK
end generate;
end block;
end architecture;
|
-- test_ng_1.vhd
use std.textio.all;
entity TEST_NG_1 is
generic (TIME_WIDTH : integer := 13);
end TEST_NG_1;
architecture MODEL of TEST_NG_1 is
begin
process
variable text_line : LINE;
procedure p(T:in time;M:in string) is
begin
if (TIME_WIDTH > 0) then
WRITE(text_line, T, RIGHT, TIME_WIDTH);
elsif (TIME_WIDTH < 0) then
WRITE(text_line, T, LEFT , -TIME_WIDTH); -- Bounds check fail
-- here
end if;
WRITE(text_line, string'(" ") & M);
WRITELINE(OUTPUT, text_line);
end procedure;
begin
p(Now, string'("Simulation Start."));
wait for 10 ns;
p(Now, string'("Simulation Done."));
wait;
end process;
end MODEL;
|
-- test_ng_1.vhd
use std.textio.all;
entity TEST_NG_1 is
generic (TIME_WIDTH : integer := 13);
end TEST_NG_1;
architecture MODEL of TEST_NG_1 is
begin
process
variable text_line : LINE;
procedure p(T:in time;M:in string) is
begin
if (TIME_WIDTH > 0) then
WRITE(text_line, T, RIGHT, TIME_WIDTH);
elsif (TIME_WIDTH < 0) then
WRITE(text_line, T, LEFT , -TIME_WIDTH); -- Bounds check fail
-- here
end if;
WRITE(text_line, string'(" ") & M);
WRITELINE(OUTPUT, text_line);
end procedure;
begin
p(Now, string'("Simulation Start."));
wait for 10 ns;
p(Now, string'("Simulation Done."));
wait;
end process;
end MODEL;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
ENA : OUT STD_LOGIC :='0';
WEA : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(32,32);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL WEA_VCC : STD_LOGIC_VECTOR(3 DOWNTO 0) :=(OTHERS => '1');
SIGNAL WEA_GND : STD_LOGIC_VECTOR(3 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(31 DOWNTO 0) <= WRITE_ADDR(31 DOWNTO 0);
READ_ADDR_INT(31 DOWNTO 0) <= READ_ADDR(31 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 64
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 64 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 32,
DOUT_WIDTH => 32,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
ENA <= DO_READ OR DO_WRITE ;
WEA <= IF_THEN_ELSE(DO_WRITE='1', WEA_VCC,WEA_GND) ;
END ARCHITECTURE;
|
----------------------------------------------------------------------
-- brdLexSwx (for Fusion Starter Kit )
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- board/kit dependency : LEDs & SW polarity
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------------------------------------------------
entity brdLexSwx is
port ( o_lex, o_pbx : out std_logic );
end brdLexSwx;
----------------------------------------------------------------------
architecture rtl of brdLexSwx is
begin
-- polarity of LED driver output
-- '0' = low idle, high active
-- '1' = high idle, low active
o_lex <= '1';
-- polarity of push button switch
-- '0' = low idle, high active (pressed)
-- '1' = high idle, low active (pressed)
o_pbx <= '0';
end rtl; |
library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity c_divider is
generic
(
width : integer := 4;
const : integer := 16
);
port
(
input1, input2 : in std_logic_vector((width - 1) downto 0);
output : out std_logic_vector((width - 1) downto 0)
);
end c_divider;
architecture behavior of c_divider is
function twocomp_bits_to_int (input : std_logic_vector)return integer is
variable ret_val : integer := 0;
begin
for i in input'range loop
if (i < input'HIGH) then
if (input(input'HIGH) = '0') then
if input(i) = '1' then
ret_val := 2 ** i + ret_val;
end if;
else
if input(i) = '0' then
ret_val := 2 ** i + ret_val;
end if;
end if;
end if;
end loop;
if (input(input'HIGH) = '1') then
ret_val := ret_val + 1;
ret_val := 0 - ret_val;
end if; return ret_val;
end twocomp_bits_to_int;
function twocomp_int_to_bin (INPUT, wid : integer)return STD_LOGIC_VECTOR is
variable TEMP_A, TEMP_B : integer := 0;
variable OUTPUT : STD_LOGIC_VECTOR((wid - 1) downto 0);
variable comp_input, abs_val : integer;
begin
if (input < 0) then
abs_val := 0 - input;
comp_input := (2 ** (wid - 1)) - abs_val;
assert(comp_input >= 0);
else
comp_input := input;
end if;
TEMP_A := comp_input;
for I in (wid - 2) downto 0 loop
TEMP_B := TEMP_A/(2 ** I);
TEMP_A := TEMP_A rem (2 ** I);
if (TEMP_B = 1) then
OUTPUT(I) := '1';
else
OUTPUT(I) := '0';
end if;
end loop;
if (input < 0) then
OUTPUT(wid - 1) := '1';
else
OUTPUT(wid - 1) := '0';
end if; return OUTPUT;
end twocomp_int_to_bin;
begin
P0 : process (input1, input2)
variable l_val, r_val, value : integer;
variable result : std_logic_vector((width - 1) downto 0);
begin
l_val := twocomp_bits_to_int(input1);
r_val := twocomp_bits_to_int(input2);
if not (r_val = 0) then
value := l_val / r_val;
result := twocomp_int_to_bin(value, width);
output <= result;
end if;
end process P0;
end behavior; |
--===========================================================================--
-- --
-- Synthesizable 6809 instruction compatible VHDL CPU core --
-- --
--===========================================================================--
--
-- File name : cpu09l.vhd
--
-- Entity name : cpu09
--
-- Purpose : 6809 instruction compatible CPU core written in VHDL
-- with Last Instruction Cycle, bus available, bus status,
-- and instruction fetch signals.
-- Not cycle compatible with the original 6809 CPU
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_unsigned
--
-- Author : John E. Kent
--
-- Email : [email protected]
--
-- Web : http://opencores.org/project,system09
--
-- Description : VMA (valid memory address) is hight whenever a valid memory
-- access is made by an instruction fetch, interrupt vector fetch
-- or a data read or write otherwise it is low indicating an idle
-- bus cycle.
-- IFETCH (instruction fetch output) is high whenever an
-- instruction byte is read i.e. the program counter is applied
-- to the address bus.
-- LIC (last instruction cycle output) is normally low
-- but goes high on the last cycle of an instruction.
-- BA (bus available output) is normally low but goes high while
-- waiting in a Sync instruction state or the CPU is halted
-- i.e. a DMA grant.
-- BS (bus status output) is normally low but goes high during an
-- interrupt or reset vector fetch or the processor is halted
-- i.e. a DMA grant.
--
-- Copyright (C) 2003 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version 0.1 - 26 June 2003 - John Kent
-- Added extra level in state stack
-- fixed some calls to the extended addressing state
--
-- Version 0.2 - 5 Sept 2003 - John Kent
-- Fixed 16 bit indexed offset (was doing read rather than fetch)
-- Added/Fixed STY and STS instructions.
-- ORCC_STATE ANDed CC state rather than ORed it - Now fixed
-- CMPX Loaded ACCA and ACCB - Now fixed
--
-- Version 1.0 - 6 Sep 2003 - John Kent
-- Initial release to Open Cores
-- reversed clock edge
--
-- Version 1.1 - 29 November 2003 John kent
-- ACCA and ACCB indexed offsets are 2's complement.
-- ALU Right Mux now sign extends ACCA & ACCB offsets
-- Absolute Indirect addressing performed a read on the
-- second byte of the address rather than a fetch
-- so it formed an incorrect address. Now fixed.
--
-- Version 1.2 - 29 November 2003 John Kent
-- LEAX and LEAY affect the Z bit only
-- LEAS and LEAU do not affect any condition codes
-- added an extra ALU control for LEA.
--
-- Version 1.3 - 12 December 2003 John Kent
-- CWAI did not work, was missed a PUSH_ST on calling
-- the ANDCC_STATE. Thanks go to Ghassan Kraidy for
-- finding this fault.
--
-- Version 1.4 - 12 December 2003 John Kent
-- Missing cc_ctrl assignment in otherwise case of
-- lea_state resulted in cc_ctrl being latched in
-- that state.
-- The otherwise statement should never be reached,
-- and has been fixed simply to resolve synthesis warnings.
--
-- Version 1.5 - 17 january 2004 John kent
-- The clear instruction used "alu_ld8" to control the ALU
-- rather than "alu_clr". This mean the Carry was not being
-- cleared correctly.
--
-- Version 1.6 - 24 January 2004 John Kent
-- Fixed problems in PSHU instruction
--
-- Version 1.7 - 25 January 2004 John Kent
-- removed redundant "alu_inx" and "alu_dex'
-- Removed "test_alu" and "test_cc"
-- STD instruction did not set condition codes
-- JMP direct was not decoded properly
-- CLR direct performed an unwanted read cycle
-- Bogus "latch_md" in Page2 indexed addressing
--
-- Version 1.8 - 27 January 2004 John Kent
-- CWAI in decode1_state should increment the PC.
-- ABX is supposed to be an unsigned addition.
-- Added extra ALU function
-- ASR8 slightly changed in the ALU.
--
-- Version 1.9 - 20 August 2005
-- LSR8 is now handled in ASR8 and ROR8 case in the ALU,
-- rather than LSR16. There was a problem with single
-- operand instructions using the MD register which is
-- sign extended on the first 8 bit fetch.
--
-- Version 1.10 - 13 September 2005
-- TFR & EXG instructions did not work for the Condition Code Register
-- An extra case has been added to the ALU for the alu_tfr control
-- to assign the left ALU input (alu_left) to the condition code
-- outputs (cc_out).
--
-- Version 1.11 - 16 September 2005
-- JSR ,X should not predecrement S before calculating the jump address.
-- The reason is that JSR [0,S] needs S to point to the top of the stack
-- to fetch a valid vector address. The solution is to have the addressing
-- mode microcode called before decrementing S and then decrementing S in
-- JSR_STATE. JSR_STATE in turn calls PUSH_RETURN_LO_STATE rather than
-- PUSH_RETURN_HI_STATE so that both the High & Low halves of the PC are
-- pushed on the stack. This adds one extra bus cycle, but resolves the
-- addressing conflict. I've also removed the pre-decement S in
-- JSR EXTENDED as it also calls JSR_STATE.
--
-- Version 1.12 - 6th June 2006
-- 6809 Programming reference manual says V is not affected by ASR, LSR and ROR
-- This is different to the 6800. CLR should reset the V bit.
--
-- Version 1.13 - 7th July 2006
-- Disable NMI on reset until S Stack pointer has been loaded.
-- Added nmi_enable signal in sp_reg process and nmi_handler process.
--
-- Version 1.14 - 11th July 2006
-- 1. Added new state to RTI called rti_entire_state.
-- This state tests the CC register after it has been loaded
-- from the stack. Previously the current CC was tested which
-- was incorrect. The Entire Flag should be set before the
-- interrupt stacks the CC.
-- 2. On bogus Interrupts, int_cc_state went to rti_state,
-- which was an enumerated state, but not defined anywhere.
-- rti_state has been changed to rti_cc_state so that bogus interrupt
-- will perform an RTI after entering that state.
-- 3. Sync should generate an interrupt if the interrupt masks
-- are cleared. If the interrupt masks are set, then an interrupt
-- will cause the the PC to advance to the next instruction.
-- Note that I don't wait for an interrupt to be asserted for
-- three clock cycles.
-- 4. Added new ALU control state "alu_mul". "alu_mul" is used in
-- the Multiply instruction replacing "alu_add16". This is similar
-- to "alu_add16" except it sets the Carry bit to B7 of the result
-- in ACCB, sets the Zero bit if the 16 bit result is zero, but
-- does not affect The Half carry (H), Negative (N) or Overflow (V)
-- flags. The logic was re-arranged so that it adds md or zero so
-- that the Carry condition code is set on zero multiplicands.
-- 5. DAA (Decimal Adjust Accumulator) should set the Negative (N)
-- and Zero Flags. It will also affect the Overflow (V) flag although
-- the operation is undefined. It's anyones guess what DAA does to V.
--
-- Version 1.15 - 25th Feb 2007 - John Kent
-- line 9672 changed "if Halt <= '1' then" to "if Halt = '1' then"
-- Changed sensitivity lists.
--
-- Version 1.16 - 5th February 2008 - John Kent
-- FIRQ interrupts should take priority over IRQ Interrupts.
-- This presumably means they should be tested for before IRQ
-- when they happen concurrently.
--
-- Version 1.17 - 18th February 2008 - John Kent
-- NMI in CWAI should mask IRQ and FIRQ interrupts
--
-- Version 1.18 - 21st February 2008 - John Kent
-- Removed default register settings in each case statement
-- and placed them at the beginning of the state sequencer.
-- Modified the SYNC instruction so that the interrupt vector(iv)
-- is not set unless an unmasked FIRQ or IRQ is received.
--
-- Version 1.19 - 25th February 2008 - John Kent
-- Enumerated separate states for FIRQ/FAST and NMIIRQ/ENTIRE
-- Enumerated separate states for MASKI and MASKIF states
-- Removed code on BSR/JSR in fetch cycle
--
-- Version 1.20 - 8th October 2011 - John Kent
-- added fetch output which should go high during the fetch cycle
--
-- Version 1.21 - 8th October 2011 - John Kent
-- added Last Instruction Cycle signal
-- replaced fetch with ifetch (instruction fetch) signal
-- added ba & bs (bus available & bus status) signals
--
-- Version 1.22 - 2011-10-29 John Kent
-- The halt state isn't correct.
-- The halt state is entered into from the fetch_state
-- It returned to the fetch state which may re-run an execute cycle
-- on the accumulator and it won't necessarily be the last instruction cycle
-- I've changed the halt state to return to the decode1_state
--
-- Version 1.23 - 2011-10-30 John Kent
-- sample halt in the change_state process if lic is high (last instruction cycle)
--
-- Version 1.24 - 2011-11-01 John Kent
-- Handle interrupts in change_state process
-- Sample interrupt inputs on last instruction cycle
-- Remove iv_ctrl and implement iv (interrupt vector) in change_state process.
-- Generate fic (first instruction cycle) from lic (last instruction cycle)
-- and use it to complete the dual operand execute cycle before servicing
-- halt or interrupts requests.
-- rename lic to lic_out on the entity declaration so that lic can be tested internally.
-- add int_firq1_state and int_nmirq1_state to allow for the dual operand execute cycle
-- integrated nmi_ctrl into change_state process
-- Reduces the microcode state stack to one entry (saved_state)
-- imm16_state jumps directly to the fetch_state
-- pull_return_lo states jumps directly to the fetch_state
-- duplicate andcc_state as cwai_state
-- rename exg1_state as exg2 state and duplicate tfr_state as exg1_state
--
-- Version 1.25 - 2011-11-27 John Kent
-- Changed the microcode for saving registers on an interrupt into a microcode subroutine.
-- Removed SWI servicing from the change state process and made SWI, SWI2 & SWI3
-- call the interrupt microcode subroutine.
-- Added additional states for nmi, and irq for interrupt servicing.
-- Added additional states for nmi/irq, firq, and swi interrupts to mask I & F flags.
--
-- Version 1.26 - 2013-03-18 John Kent
-- pre-initialized cond_true variable to true in state sequencer
-- re-arranged change_state process slightly
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cpu09 is
port (
clk : in std_logic; -- E clock input (rising edge)
rst : in std_logic; -- reset input (active high)
vma : out std_logic; -- valid memory address (active high)
lic_out : out std_logic; -- last instruction cycle (active high)
ifetch : out std_logic; -- instruction fetch cycle (active high)
opfetch : out std_logic; -- opcode fetch (active high)
ba : out std_logic; -- bus available (high on sync wait or DMA grant)
bs : out std_logic; -- bus status (high on interrupt or reset vector fetch or DMA grant)
addr : out std_logic_vector(15 downto 0); -- address bus output
rw : out std_logic; -- read not write output
data_out : out std_logic_vector(7 downto 0); -- data bus output
data_in : in std_logic_vector(7 downto 0); -- data bus input
irq : in std_logic; -- interrupt request input (active high)
firq : in std_logic; -- fast interrupt request input (active high)
nmi : in std_logic; -- non maskable interrupt request input (active high)
halt : in std_logic; -- halt input (active high) grants DMA
hold : in std_logic; -- hold input (active high) extend bus cycle
Regs : out std_logic_vector(111 downto 0)
);
end cpu09;
architecture rtl of cpu09 is
constant EBIT : integer := 7;
constant FBIT : integer := 6;
constant HBIT : integer := 5;
constant IBIT : integer := 4;
constant NBIT : integer := 3;
constant ZBIT : integer := 2;
constant VBIT : integer := 1;
constant CBIT : integer := 0;
--
-- Interrupt vector modifiers
--
constant RST_VEC : std_logic_vector(2 downto 0) := "111";
constant NMI_VEC : std_logic_vector(2 downto 0) := "110";
constant SWI_VEC : std_logic_vector(2 downto 0) := "101";
constant IRQ_VEC : std_logic_vector(2 downto 0) := "100";
constant FIRQ_VEC : std_logic_vector(2 downto 0) := "011";
constant SWI2_VEC : std_logic_vector(2 downto 0) := "010";
constant SWI3_VEC : std_logic_vector(2 downto 0) := "001";
constant RESV_VEC : std_logic_vector(2 downto 0) := "000";
type state_type is (-- Start off in Reset
reset_state,
-- Fetch Interrupt Vectors (including reset)
vect_lo_state, vect_hi_state, vect_idle_state,
-- Fetch Instruction Cycle
fetch_state,
-- Decode Instruction Cycles
decode1_state, decode2_state, decode3_state,
-- Calculate Effective Address
imm16_state,
indexed_state, index8_state, index16_state, index16_2_state,
pcrel8_state, pcrel16_state, pcrel16_2_state,
indexaddr_state, indexaddr2_state,
postincr1_state, postincr2_state,
indirect_state, indirect2_state, indirect3_state,
extended_state,
-- single ops
single_op_read_state,
single_op_exec_state,
single_op_write_state,
-- Dual op states
dual_op_read8_state, dual_op_read16_state, dual_op_read16_2_state,
dual_op_write8_state, dual_op_write16_state,
--
sync_state, halt_state, cwai_state,
--
andcc_state, orcc_state,
tfr_state,
exg_state, exg1_state, exg2_state,
lea_state,
-- Multiplication
mul_state, mulea_state, muld_state,
mul0_state, mul1_state, mul2_state, mul3_state,
mul4_state, mul5_state, mul6_state, mul7_state,
-- Branches
lbranch_state, sbranch_state,
-- Jumps, Subroutine Calls and Returns
jsr_state, jmp_state,
push_return_hi_state, push_return_lo_state,
pull_return_hi_state, pull_return_lo_state,
-- Interrupt cycles
int_nmi_state, int_nmi1_state,
int_irq_state, int_irq1_state,
int_firq_state, int_firq1_state,
int_entire_state, int_fast_state,
int_pcl_state, int_pch_state,
int_upl_state, int_uph_state,
int_iyl_state, int_iyh_state,
int_ixl_state, int_ixh_state,
int_dp_state,
int_accb_state, int_acca_state,
int_cc_state,
int_cwai_state,
int_nmimask_state, int_firqmask_state, int_swimask_state, int_irqmask_state,
-- Return From Interrupt
rti_cc_state, rti_entire_state,
rti_acca_state, rti_accb_state,
rti_dp_state,
rti_ixl_state, rti_ixh_state,
rti_iyl_state, rti_iyh_state,
rti_upl_state, rti_uph_state,
rti_pcl_state, rti_pch_state,
-- Push Registers using SP
pshs_state,
pshs_pcl_state, pshs_pch_state,
pshs_upl_state, pshs_uph_state,
pshs_iyl_state, pshs_iyh_state,
pshs_ixl_state, pshs_ixh_state,
pshs_dp_state,
pshs_acca_state, pshs_accb_state,
pshs_cc_state,
-- Pull Registers using SP
puls_state,
puls_cc_state,
puls_acca_state, puls_accb_state,
puls_dp_state,
puls_ixl_state, puls_ixh_state,
puls_iyl_state, puls_iyh_state,
puls_upl_state, puls_uph_state,
puls_pcl_state, puls_pch_state,
-- Push Registers using UP
pshu_state,
pshu_pcl_state, pshu_pch_state,
pshu_spl_state, pshu_sph_state,
pshu_iyl_state, pshu_iyh_state,
pshu_ixl_state, pshu_ixh_state,
pshu_dp_state,
pshu_acca_state, pshu_accb_state,
pshu_cc_state,
-- Pull Registers using UP
pulu_state,
pulu_cc_state,
pulu_acca_state, pulu_accb_state,
pulu_dp_state,
pulu_ixl_state, pulu_ixh_state,
pulu_iyl_state, pulu_iyh_state,
pulu_spl_state, pulu_sph_state,
pulu_pcl_state, pulu_pch_state );
type st_type is (reset_st, push_st, idle_st );
type iv_type is (latch_iv, swi3_iv, swi2_iv, firq_iv, irq_iv, swi_iv, nmi_iv, reset_iv);
type addr_type is (idle_ad, fetch_ad, read_ad, write_ad, pushu_ad, pullu_ad, pushs_ad, pulls_ad, int_hi_ad, int_lo_ad );
type dout_type is (cc_dout, acca_dout, accb_dout, dp_dout,
ix_lo_dout, ix_hi_dout, iy_lo_dout, iy_hi_dout,
up_lo_dout, up_hi_dout, sp_lo_dout, sp_hi_dout,
pc_lo_dout, pc_hi_dout, md_lo_dout, md_hi_dout );
type op_type is (reset_op, fetch_op, latch_op );
type pre_type is (reset_pre, fetch_pre, latch_pre );
type cc_type is (reset_cc, load_cc, pull_cc, latch_cc );
type acca_type is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca );
type accb_type is (reset_accb, load_accb, pull_accb, latch_accb );
type dp_type is (reset_dp, load_dp, pull_dp, latch_dp );
type ix_type is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix );
type iy_type is (reset_iy, load_iy, pull_lo_iy, pull_hi_iy, latch_iy );
type sp_type is (reset_sp, latch_sp, load_sp, pull_hi_sp, pull_lo_sp );
type up_type is (reset_up, latch_up, load_up, pull_hi_up, pull_lo_up );
type pc_type is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc, incr_pc );
type md_type is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md );
type ea_type is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea );
type left_type is (cc_left, acca_left, accb_left, dp_left,
ix_left, iy_left, up_left, sp_left,
accd_left, md_left, pc_left, ea_left );
type right_type is (ea_right, zero_right, one_right, two_right,
acca_right, accb_right, accd_right,
md_right, md_sign5_right, md_sign8_right );
type alu_type is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc,
alu_and, alu_ora, alu_eor,
alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com,
alu_lsr16, alu_lsl16,
alu_ror8, alu_rol8, alu_mul,
alu_asr8, alu_asl8, alu_lsr8,
alu_andcc, alu_orcc, alu_sex, alu_tfr, alu_abx,
alu_seif, alu_sei, alu_see, alu_cle,
alu_ld8, alu_st8, alu_ld16, alu_st16, alu_lea, alu_nop, alu_daa );
signal op_code: std_logic_vector(7 downto 0);
signal pre_code: std_logic_vector(7 downto 0);
signal acca: std_logic_vector(7 downto 0);
signal accb: std_logic_vector(7 downto 0);
signal cc: std_logic_vector(7 downto 0);
signal cc_out: std_logic_vector(7 downto 0);
signal dp: std_logic_vector(7 downto 0);
signal xreg: std_logic_vector(15 downto 0);
signal yreg: std_logic_vector(15 downto 0);
signal sp: std_logic_vector(15 downto 0);
signal up: std_logic_vector(15 downto 0);
signal ea: std_logic_vector(15 downto 0);
signal pc: std_logic_vector(15 downto 0);
signal md: std_logic_vector(15 downto 0);
signal left: std_logic_vector(15 downto 0);
signal right: std_logic_vector(15 downto 0);
signal out_alu: std_logic_vector(15 downto 0);
signal iv: std_logic_vector(2 downto 0);
signal nmi_req: std_logic;
signal nmi_ack: std_logic;
signal nmi_enable: std_logic;
signal fic: std_logic; -- first instruction cycle
signal lic: std_logic; -- last instruction cycle
signal state: state_type;
signal next_state: state_type;
signal return_state: state_type;
signal saved_state: state_type;
signal st_ctrl: st_type;
signal iv_ctrl: iv_type;
signal pc_ctrl: pc_type;
signal ea_ctrl: ea_type;
signal op_ctrl: op_type;
signal pre_ctrl: pre_type;
signal md_ctrl: md_type;
signal acca_ctrl: acca_type;
signal accb_ctrl: accb_type;
signal ix_ctrl: ix_type;
signal iy_ctrl: iy_type;
signal cc_ctrl: cc_type;
signal dp_ctrl: dp_type;
signal sp_ctrl: sp_type;
signal up_ctrl: up_type;
signal left_ctrl: left_type;
signal right_ctrl: right_type;
signal alu_ctrl: alu_type;
signal addr_ctrl: addr_type;
signal dout_ctrl: dout_type;
begin
Regs <= cc & dp & pc & sp & up & yreg & xreg & accb & acca;
----------------------------------
--
-- State machine stack
--
----------------------------------
--state_stack_proc: process( clk, hold, state_stack, st_ctrl,
-- return_state, fetch_state )
state_stack_proc: process( clk, st_ctrl, return_state )
begin
if clk'event and clk = '1' then
if hold = '0' then
case st_ctrl is
when reset_st =>
saved_state <= fetch_state;
when push_st =>
saved_state <= return_state;
when others =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- Interrupt Vector control
--
----------------------------------
--
int_vec_proc: process( clk, iv_ctrl )
begin
if clk'event and clk = '1' then
if hold = '0' then
case iv_ctrl is
when reset_iv =>
iv <= RST_VEC;
when nmi_iv =>
iv <= NMI_VEC;
when swi_iv =>
iv <= SWI_VEC;
when irq_iv =>
iv <= IRQ_VEC;
when firq_iv =>
iv <= FIRQ_VEC;
when swi2_iv =>
iv <= SWI2_VEC;
when swi3_iv =>
iv <= SWI3_VEC;
when others =>
null;
end case;
end if; -- hold
end if; -- clk
end process;
----------------------------------
--
-- Program Counter Control
--
----------------------------------
--pc_reg: process( clk, pc_ctrl, hold, pc, out_alu, data_in )
pc_reg: process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case pc_ctrl is
when reset_pc =>
pc <= (others=>'0');
when load_pc =>
pc <= out_alu(15 downto 0);
when pull_lo_pc =>
pc(7 downto 0) <= data_in;
when pull_hi_pc =>
pc(15 downto 8) <= data_in;
when incr_pc =>
pc <= pc + 1;
when others =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- Effective Address Control
--
----------------------------------
--ea_reg: process( clk, ea_ctrl, hold, ea, out_alu, data_in, dp )
ea_reg: process( clk )
begin
if clk'event and clk = '1' then
if hold= '0' then
case ea_ctrl is
when reset_ea =>
ea <= (others=>'0');
when fetch_first_ea =>
ea(7 downto 0) <= data_in;
ea(15 downto 8) <= dp;
when fetch_next_ea =>
ea(15 downto 8) <= ea(7 downto 0);
ea(7 downto 0) <= data_in;
when load_ea =>
ea <= out_alu(15 downto 0);
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- Accumulator A
--
--------------------------------
--acca_reg : process( clk, acca_ctrl, hold, out_alu, acca, data_in )
acca_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case acca_ctrl is
when reset_acca =>
acca <= (others=>'0');
when load_acca =>
acca <= out_alu(7 downto 0);
when load_hi_acca =>
acca <= out_alu(15 downto 8);
when pull_acca =>
acca <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- Accumulator B
--
--------------------------------
--accb_reg : process( clk, accb_ctrl, hold, out_alu, accb, data_in )
accb_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case accb_ctrl is
when reset_accb =>
accb <= (others=>'0');
when load_accb =>
accb <= out_alu(7 downto 0);
when pull_accb =>
accb <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- X Index register
--
--------------------------------
--ix_reg : process( clk, ix_ctrl, hold, out_alu, xreg, data_in )
ix_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case ix_ctrl is
when reset_ix =>
xreg <= (others=>'0');
when load_ix =>
xreg <= out_alu(15 downto 0);
when pull_hi_ix =>
xreg(15 downto 8) <= data_in;
when pull_lo_ix =>
xreg(7 downto 0) <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- Y Index register
--
--------------------------------
--iy_reg : process( clk, iy_ctrl, hold, out_alu, yreg, data_in )
iy_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case iy_ctrl is
when reset_iy =>
yreg <= (others=>'0');
when load_iy =>
yreg <= out_alu(15 downto 0);
when pull_hi_iy =>
yreg(15 downto 8) <= data_in;
when pull_lo_iy =>
yreg(7 downto 0) <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- S stack pointer
--
--------------------------------
--sp_reg : process( clk, sp_ctrl, hold, sp, out_alu, data_in, nmi_enable )
sp_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case sp_ctrl is
when reset_sp =>
sp <= (others=>'0');
nmi_enable <= '0';
when load_sp =>
sp <= out_alu(15 downto 0);
nmi_enable <= '1';
when pull_hi_sp =>
sp(15 downto 8) <= data_in;
when pull_lo_sp =>
sp(7 downto 0) <= data_in;
nmi_enable <= '1';
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- U stack pointer
--
--------------------------------
--up_reg : process( clk, up_ctrl, hold, up, out_alu, data_in )
up_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case up_ctrl is
when reset_up =>
up <= (others=>'0');
when load_up =>
up <= out_alu(15 downto 0);
when pull_hi_up =>
up(15 downto 8) <= data_in;
when pull_lo_up =>
up(7 downto 0) <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- Memory Data
--
--------------------------------
--md_reg : process( clk, md_ctrl, hold, out_alu, data_in, md )
md_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case md_ctrl is
when reset_md =>
md <= (others=>'0');
when load_md =>
md <= out_alu(15 downto 0);
when fetch_first_md => -- sign extend md for branches
md(15 downto 8) <= data_in(7) & data_in(7) & data_in(7) & data_in(7) &
data_in(7) & data_in(7) & data_in(7) & data_in(7) ;
md(7 downto 0) <= data_in;
when fetch_next_md =>
md(15 downto 8) <= md(7 downto 0);
md(7 downto 0) <= data_in;
when shiftl_md =>
md(15 downto 1) <= md(14 downto 0);
md(0) <= '0';
when others =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- Condition Codes
--
----------------------------------
--cc_reg: process( clk, cc_ctrl, hold, cc_out, cc, data_in )
cc_reg: process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case cc_ctrl is
when reset_cc =>
cc <= "11010000"; -- set EBIT, FBIT & IBIT
when load_cc =>
cc <= cc_out;
when pull_cc =>
cc <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- Direct Page register
--
----------------------------------
--dp_reg: process( clk, dp_ctrl, hold, out_alu, dp, data_in )
dp_reg: process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case dp_ctrl is
when reset_dp =>
dp <= (others=>'0');
when load_dp =>
dp <= out_alu(7 downto 0);
when pull_dp =>
dp <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- op code register
--
----------------------------------
--op_reg: process( clk, op_ctrl, hold, op_code, data_in )
op_reg: process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case op_ctrl is
when reset_op =>
op_code <= "00010010";
when fetch_op =>
op_code <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- pre byte op code register
--
----------------------------------
--pre_reg: process( clk, pre_ctrl, hold, pre_code, data_in )
pre_reg: process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case pre_ctrl is
when reset_pre =>
pre_code <= (others=>'0');
when fetch_pre =>
pre_code <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- state machine
--
--------------------------------
--change_state: process( clk, rst, state, hold, next_state )
change_state: process( clk )
begin
if clk'event and clk = '1' then
if rst = '1' then
fic <= '0';
nmi_ack <= '0';
state <= reset_state;
elsif hold = '0' then
fic <= lic;
--
-- nmi request is not cleared until nmi input goes low
--
if (nmi_req = '0') and (nmi_ack='1') then
nmi_ack <= '0';
end if;
if (nmi_req = '1') and (nmi_ack = '0') and (state = int_nmimask_state) then
nmi_ack <= '1';
end if;
if lic = '1' then
if halt = '1' then
state <= halt_state;
-- service non maskable interrupts
elsif (nmi_req = '1') and (nmi_ack = '0') then
state <= int_nmi_state;
--
-- FIRQ & IRQ are level sensitive
--
elsif (firq = '1') then
if (cc(FBIT) = '0') then
state <= int_firq_state;
else
state <= fetch_state;
end if;
elsif (irq = '1') then
if (cc(IBIT) = '0') then
state <= int_irq_state;
else
state <= fetch_state;
end if;
else
state <= next_state;
end if; -- halt, nmi, firq, irq
else
state <= next_state;
end if; -- lic
end if; -- reset/hold
end if; -- clk
end process;
------------------------------------
--
-- Detect Edge of NMI interrupt
--
------------------------------------
--nmi_handler : process( clk, rst, nmi, nmi_ack, nmi_req, nmi_enable )
nmi_handler : process( rst, clk )
begin
if rst='1' then
nmi_req <= '0';
elsif clk'event and clk='0' then
if (nmi='1') and (nmi_ack='0') and (nmi_enable='1') then
nmi_req <= '1';
else
if (nmi='0') and (nmi_ack='1') then
nmi_req <= '0';
end if;
end if;
end if;
end process;
----------------------------------
--
-- Address output multiplexer
--
----------------------------------
addr_mux: process( addr_ctrl, pc, ea, up, sp, iv )
begin
ifetch <= '0';
vma <= '1';
case addr_ctrl is
when fetch_ad =>
addr <= pc;
rw <= '1';
ifetch <= '1';
when read_ad =>
addr <= ea;
rw <= '1';
when write_ad =>
addr <= ea;
rw <= '0';
when pushs_ad =>
addr <= sp;
rw <= '0';
when pulls_ad =>
addr <= sp;
rw <= '1';
when pushu_ad =>
addr <= up;
rw <= '0';
when pullu_ad =>
addr <= up;
rw <= '1';
when int_hi_ad =>
addr <= "111111111111" & iv & "0";
rw <= '1';
when int_lo_ad =>
addr <= "111111111111" & iv & "1";
rw <= '1';
when others =>
addr <= "1111111111111111";
rw <= '1';
vma <= '0';
end case;
end process;
--------------------------------
--
-- Data Bus output
--
--------------------------------
dout_mux : process( dout_ctrl, md, acca, accb, dp, xreg, yreg, sp, up, pc, cc )
begin
case dout_ctrl is
when cc_dout => -- condition code register
data_out <= cc;
when acca_dout => -- accumulator a
data_out <= acca;
when accb_dout => -- accumulator b
data_out <= accb;
when dp_dout => -- direct page register
data_out <= dp;
when ix_lo_dout => -- X index reg
data_out <= xreg(7 downto 0);
when ix_hi_dout => -- X index reg
data_out <= xreg(15 downto 8);
when iy_lo_dout => -- Y index reg
data_out <= yreg(7 downto 0);
when iy_hi_dout => -- Y index reg
data_out <= yreg(15 downto 8);
when up_lo_dout => -- U stack pointer
data_out <= up(7 downto 0);
when up_hi_dout => -- U stack pointer
data_out <= up(15 downto 8);
when sp_lo_dout => -- S stack pointer
data_out <= sp(7 downto 0);
when sp_hi_dout => -- S stack pointer
data_out <= sp(15 downto 8);
when md_lo_dout => -- alu output
data_out <= md(7 downto 0);
when md_hi_dout => -- alu output
data_out <= md(15 downto 8);
when pc_lo_dout => -- low order pc
data_out <= pc(7 downto 0);
when pc_hi_dout => -- high order pc
data_out <= pc(15 downto 8);
end case;
end process;
----------------------------------
--
-- Left Mux
--
----------------------------------
left_mux: process( left_ctrl, acca, accb, cc, dp, xreg, yreg, up, sp, pc, ea, md )
begin
case left_ctrl is
when cc_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= cc;
when acca_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= acca;
when accb_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= accb;
when dp_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= dp;
when accd_left =>
left(15 downto 8) <= acca;
left(7 downto 0) <= accb;
when md_left =>
left <= md;
when ix_left =>
left <= xreg;
when iy_left =>
left <= yreg;
when sp_left =>
left <= sp;
when up_left =>
left <= up;
when pc_left =>
left <= pc;
when others =>
-- when ea_left =>
left <= ea;
end case;
end process;
----------------------------------
--
-- Right Mux
--
----------------------------------
right_mux: process( right_ctrl, md, acca, accb, ea )
begin
case right_ctrl is
when ea_right =>
right <= ea;
when zero_right =>
right <= "0000000000000000";
when one_right =>
right <= "0000000000000001";
when two_right =>
right <= "0000000000000010";
when acca_right =>
if acca(7) = '0' then
right <= "00000000" & acca(7 downto 0);
else
right <= "11111111" & acca(7 downto 0);
end if;
when accb_right =>
if accb(7) = '0' then
right <= "00000000" & accb(7 downto 0);
else
right <= "11111111" & accb(7 downto 0);
end if;
when accd_right =>
right <= acca & accb;
when md_sign5_right =>
if md(4) = '0' then
right <= "00000000000" & md(4 downto 0);
else
right <= "11111111111" & md(4 downto 0);
end if;
when md_sign8_right =>
if md(7) = '0' then
right <= "00000000" & md(7 downto 0);
else
right <= "11111111" & md(7 downto 0);
end if;
when others =>
-- when md_right =>
right <= md;
end case;
end process;
----------------------------------
--
-- Arithmetic Logic Unit
--
----------------------------------
alu: process( alu_ctrl, cc, left, right, out_alu, cc_out )
variable valid_lo, valid_hi : boolean;
variable carry_in : std_logic;
variable daa_reg : std_logic_vector(7 downto 0);
begin
case alu_ctrl is
when alu_adc | alu_sbc |
alu_rol8 | alu_ror8 =>
carry_in := cc(CBIT);
when alu_asr8 =>
carry_in := left(7);
when others =>
carry_in := '0';
end case;
valid_lo := left(3 downto 0) <= 9;
valid_hi := left(7 downto 4) <= 9;
--
-- CBIT HBIT VHI VLO DAA
-- 0 0 0 0 66 (!VHI : hi_nybble>8)
-- 0 0 0 1 60
-- 0 0 1 1 00
-- 0 0 1 0 06 ( VHI : hi_nybble<=8)
--
-- 0 1 1 0 06
-- 0 1 1 1 06
-- 0 1 0 1 66
-- 0 1 0 0 66
--
-- 1 1 0 0 66
-- 1 1 0 1 66
-- 1 1 1 1 66
-- 1 1 1 0 66
--
-- 1 0 1 0 66
-- 1 0 1 1 60
-- 1 0 0 1 60
-- 1 0 0 0 66
--
-- 66 = (!VHI & !VLO) + (CBIT & HBIT) + (HBIT & !VHI) + (CBIT & !VLO)
-- = (CBIT & (HBIT + !VLO)) + (!VHI & (HBIT + !VLO))
-- = (!VLO & (CBIT + !VHI)) + (HBIT & (CBIT + !VHI))
-- 60 = (CBIT & !HBIT & VLO) + (!HBIT & !VHI & VLO)
-- = (!HBIT & VLO & (CBIT + !VHI))
-- 06 = (!CBIT & VHI & (!VLO + VHI)
-- 00 = (!CBIT & !HBIT & VHI & VLO)
--
if (cc(CBIT) = '0') then
-- CBIT=0
if( cc(HBIT) = '0' ) then
-- HBIT=0
if valid_lo then
-- lo <= 9 (no overflow in low nybble)
if valid_hi then
-- hi <= 9 (no overflow in either low or high nybble)
daa_reg := "00000000";
else
-- hi > 9 (overflow in high nybble only)
daa_reg := "01100000";
end if;
else
-- lo > 9 (overflow in low nybble)
--
-- since there is already an overflow in the low nybble
-- you need to make room in the high nybble for the low nybble carry
-- so compare the high nybble with 8 rather than 9
-- if the high nybble is 9 there will be an overflow on the high nybble
-- after the decimal adjust which means it will roll over to an invalid BCD digit
--
if( left(7 downto 4) <= 8 ) then
-- hi <= 8 (overflow in low nybble only)
daa_reg := "00000110";
else
-- hi > 8 (overflow in low and high nybble)
daa_reg := "01100110";
end if;
end if;
else
-- HBIT=1 (overflow in low nybble)
if valid_hi then
-- hi <= 9 (overflow in low nybble only)
daa_reg := "00000110";
else
-- hi > 9 (overflow in low and high nybble)
daa_reg := "01100110";
end if;
end if;
else
-- CBIT=1 (carry => overflow in high nybble)
if ( cc(HBIT) = '0' )then
-- HBIT=0 (half carry clear => may or may not be an overflow in the low nybble)
if valid_lo then
-- lo <=9 (overflow in high nybble only)
daa_reg := "01100000";
else
-- lo >9 (overflow in low and high nybble)
daa_reg := "01100110";
end if;
else
-- HBIT=1 (overflow in low and high nybble)
daa_reg := "01100110";
end if;
end if;
case alu_ctrl is
when alu_add8 | alu_inc |
alu_add16 | alu_adc | alu_mul =>
out_alu <= left + right + ("000000000000000" & carry_in);
when alu_sub8 | alu_dec |
alu_sub16 | alu_sbc =>
out_alu <= left - right - ("000000000000000" & carry_in);
when alu_abx =>
out_alu <= left + ("00000000" & right(7 downto 0)) ;
when alu_and =>
out_alu <= left and right; -- and/bit
when alu_ora =>
out_alu <= left or right; -- or
when alu_eor =>
out_alu <= left xor right; -- eor/xor
when alu_lsl16 | alu_asl8 | alu_rol8 =>
out_alu <= left(14 downto 0) & carry_in; -- rol8/asl8/lsl16
when alu_lsr16 =>
out_alu <= carry_in & left(15 downto 1); -- lsr16
when alu_lsr8 | alu_asr8 | alu_ror8 =>
out_alu <= "00000000" & carry_in & left(7 downto 1); -- ror8/asr8/lsr8
when alu_neg =>
out_alu <= right - left; -- neg (right=0)
when alu_com =>
out_alu <= not left;
when alu_clr | alu_ld8 | alu_ld16 | alu_lea =>
out_alu <= right; -- clr, ld
when alu_st8 | alu_st16 | alu_andcc | alu_orcc | alu_tfr =>
out_alu <= left;
when alu_daa =>
out_alu <= left + ("00000000" & daa_reg);
when alu_sex =>
if left(7) = '0' then
out_alu <= "00000000" & left(7 downto 0);
else
out_alu <= "11111111" & left(7 downto 0);
end if;
when others =>
out_alu <= left; -- nop
end case;
--
-- carry bit
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(CBIT) <= (left(7) and right(7)) or
(left(7) and not out_alu(7)) or
(right(7) and not out_alu(7));
when alu_sub8 | alu_sbc =>
cc_out(CBIT) <= ((not left(7)) and right(7)) or
((not left(7)) and out_alu(7)) or
(right(7) and out_alu(7));
when alu_add16 =>
cc_out(CBIT) <= (left(15) and right(15)) or
(left(15) and not out_alu(15)) or
(right(15) and not out_alu(15));
when alu_sub16 =>
cc_out(CBIT) <= ((not left(15)) and right(15)) or
((not left(15)) and out_alu(15)) or
(right(15) and out_alu(15));
when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 =>
cc_out(CBIT) <= left(0);
when alu_rol8 | alu_asl8 =>
cc_out(CBIT) <= left(7);
when alu_lsl16 =>
cc_out(CBIT) <= left(15);
when alu_com =>
cc_out(CBIT) <= '1';
when alu_neg | alu_clr =>
cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0);
when alu_mul =>
cc_out(CBIT) <= out_alu(7);
when alu_daa =>
if ( daa_reg(7 downto 4) = "0110" ) then
cc_out(CBIT) <= '1';
else
cc_out(CBIT) <= '0';
end if;
when alu_andcc =>
cc_out(CBIT) <= left(CBIT) and cc(CBIT);
when alu_orcc =>
cc_out(CBIT) <= left(CBIT) or cc(CBIT);
when alu_tfr =>
cc_out(CBIT) <= left(CBIT);
when others =>
cc_out(CBIT) <= cc(CBIT);
end case;
--
-- Zero flag
--
case alu_ctrl is
when alu_add8 | alu_sub8 |
alu_adc | alu_sbc |
alu_and | alu_ora | alu_eor |
alu_inc | alu_dec |
alu_neg | alu_com | alu_clr |
alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
alu_ld8 | alu_st8 | alu_sex | alu_daa =>
cc_out(ZBIT) <= not( out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) );
when alu_add16 | alu_sub16 | alu_mul |
alu_lsl16 | alu_lsr16 |
alu_ld16 | alu_st16 | alu_lea =>
cc_out(ZBIT) <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or
out_alu(11) or out_alu(10) or out_alu(9) or out_alu(8) or
out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) );
when alu_andcc =>
cc_out(ZBIT) <= left(ZBIT) and cc(ZBIT);
when alu_orcc =>
cc_out(ZBIT) <= left(ZBIT) or cc(ZBIT);
when alu_tfr =>
cc_out(ZBIT) <= left(ZBIT);
when others =>
cc_out(ZBIT) <= cc(ZBIT);
end case;
--
-- negative flag
--
case alu_ctrl is
when alu_add8 | alu_sub8 |
alu_adc | alu_sbc |
alu_and | alu_ora | alu_eor |
alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
alu_inc | alu_dec | alu_neg | alu_com | alu_clr |
alu_ld8 | alu_st8 | alu_sex | alu_daa =>
cc_out(NBIT) <= out_alu(7);
when alu_add16 | alu_sub16 |
alu_lsl16 | alu_lsr16 |
alu_ld16 | alu_st16 =>
cc_out(NBIT) <= out_alu(15);
when alu_andcc =>
cc_out(NBIT) <= left(NBIT) and cc(NBIT);
when alu_orcc =>
cc_out(NBIT) <= left(NBIT) or cc(NBIT);
when alu_tfr =>
cc_out(NBIT) <= left(NBIT);
when others =>
cc_out(NBIT) <= cc(NBIT);
end case;
--
-- Interrupt mask flag
--
case alu_ctrl is
when alu_andcc =>
cc_out(IBIT) <= left(IBIT) and cc(IBIT);
when alu_orcc =>
cc_out(IBIT) <= left(IBIT) or cc(IBIT);
when alu_tfr =>
cc_out(IBIT) <= left(IBIT);
when alu_seif | alu_sei =>
cc_out(IBIT) <= '1';
when others =>
cc_out(IBIT) <= cc(IBIT); -- interrupt mask
end case;
--
-- Half Carry flag
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(HBIT) <= (left(3) and right(3)) or
(right(3) and not out_alu(3)) or
(left(3) and not out_alu(3));
when alu_andcc =>
cc_out(HBIT) <= left(HBIT) and cc(HBIT);
when alu_orcc =>
cc_out(HBIT) <= left(HBIT) or cc(HBIT);
when alu_tfr =>
cc_out(HBIT) <= left(HBIT);
when others =>
cc_out(HBIT) <= cc(HBIT);
end case;
--
-- Overflow flag
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(VBIT) <= (left(7) and right(7) and (not out_alu(7))) or
((not left(7)) and (not right(7)) and out_alu(7));
when alu_sub8 | alu_sbc =>
cc_out(VBIT) <= (left(7) and (not right(7)) and (not out_alu(7))) or
((not left(7)) and right(7) and out_alu(7));
when alu_add16 =>
cc_out(VBIT) <= (left(15) and right(15) and (not out_alu(15))) or
((not left(15)) and (not right(15)) and out_alu(15));
when alu_sub16 =>
cc_out(VBIT) <= (left(15) and (not right(15)) and (not out_alu(15))) or
((not left(15)) and right(15) and out_alu(15));
when alu_inc =>
cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and
left(3) and left(2) and left(1) and left(0));
when alu_dec | alu_neg =>
cc_out(VBIT) <= (left(7) and (not left(6)) and (not left(5)) and (not left(4)) and
(not left(3)) and (not left(2)) and (not left(1)) and (not left(0)));
-- 6809 Programming reference manual says
-- V not affected by ASR, LSR and ROR
-- This is different to the 6800
-- John Kent 6th June 2006
-- when alu_asr8 =>
-- cc_out(VBIT) <= left(0) xor left(7);
-- when alu_lsr8 | alu_lsr16 =>
-- cc_out(VBIT) <= left(0);
-- when alu_ror8 =>
-- cc_out(VBIT) <= left(0) xor cc(CBIT);
when alu_lsl16 =>
cc_out(VBIT) <= left(15) xor left(14);
when alu_rol8 | alu_asl8 =>
cc_out(VBIT) <= left(7) xor left(6);
--
-- 11th July 2006 - John Kent
-- What DAA does with V is anyones guess
-- It is undefined in the 6809 programming manual
--
when alu_daa =>
cc_out(VBIT) <= left(7) xor out_alu(7) xor cc(CBIT);
-- CLR resets V Bit
-- John Kent 6th June 2006
when alu_and | alu_ora | alu_eor | alu_com | alu_clr |
alu_st8 | alu_st16 | alu_ld8 | alu_ld16 | alu_sex =>
cc_out(VBIT) <= '0';
when alu_andcc =>
cc_out(VBIT) <= left(VBIT) and cc(VBIT);
when alu_orcc =>
cc_out(VBIT) <= left(VBIT) or cc(VBIT);
when alu_tfr =>
cc_out(VBIT) <= left(VBIT);
when others =>
cc_out(VBIT) <= cc(VBIT);
end case;
case alu_ctrl is
when alu_andcc =>
cc_out(FBIT) <= left(FBIT) and cc(FBIT);
when alu_orcc =>
cc_out(FBIT) <= left(FBIT) or cc(FBIT);
when alu_tfr =>
cc_out(FBIT) <= left(FBIT);
when alu_seif =>
cc_out(FBIT) <= '1';
when others =>
cc_out(FBIT) <= cc(FBIT);
end case;
case alu_ctrl is
when alu_andcc =>
cc_out(EBIT) <= left(EBIT) and cc(EBIT);
when alu_orcc =>
cc_out(EBIT) <= left(EBIT) or cc(EBIT);
when alu_tfr =>
cc_out(EBIT) <= left(EBIT);
when alu_see =>
cc_out(EBIT) <= '1';
when alu_cle =>
cc_out(EBIT) <= '0';
when others =>
cc_out(EBIT) <= cc(EBIT);
end case;
end process;
------------------------------------
--
-- state sequencer
--
------------------------------------
process( state, saved_state,
op_code, pre_code,
cc, ea, md, iv, fic, halt,
nmi_req, firq, irq, lic )
variable cond_true : boolean; -- variable used to evaluate coditional branches
begin
cond_true := (1=1);
ba <= '0';
bs <= '0';
lic <= '0';
opfetch <= '0';
iv_ctrl <= latch_iv;
-- Registers preserved
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
ea_ctrl <= latch_ea;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
-- ALU Idle
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
-- Bus idle
addr_ctrl <= idle_ad;
dout_ctrl <= cc_dout;
-- Next State Fetch
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
case state is
when reset_state => -- released from reset
-- reset the registers
iv_ctrl <= reset_iv;
op_ctrl <= reset_op;
pre_ctrl <= reset_pre;
cc_ctrl <= reset_cc;
acca_ctrl <= reset_acca;
accb_ctrl <= reset_accb;
dp_ctrl <= reset_dp;
ix_ctrl <= reset_ix;
iy_ctrl <= reset_iy;
up_ctrl <= reset_up;
sp_ctrl <= reset_sp;
pc_ctrl <= reset_pc;
ea_ctrl <= reset_ea;
md_ctrl <= reset_md;
st_ctrl <= reset_st;
next_state <= vect_hi_state;
--
-- Jump via interrupt vector
-- iv holds interrupt type
-- fetch PC hi from vector location
--
when vect_hi_state =>
-- fetch pc low interrupt vector
pc_ctrl <= pull_hi_pc;
addr_ctrl <= int_hi_ad;
bs <= '1';
next_state <= vect_lo_state;
--
-- jump via interrupt vector
-- iv holds vector type
-- fetch PC lo from vector location
--
when vect_lo_state =>
-- fetch the vector low byte
pc_ctrl <= pull_lo_pc;
addr_ctrl <= int_lo_ad;
bs <= '1';
next_state <= fetch_state;
when vect_idle_state =>
--
-- Last Instruction Cycle for SWI, SWI2 & SWI3
--
if op_code = "00111111" then
lic <= '1';
end if;
next_state <= fetch_state;
--
-- Here to fetch an instruction
-- PC points to opcode
--
when fetch_state =>
-- fetch the op code
opfetch <= '1';
op_ctrl <= fetch_op;
pre_ctrl <= fetch_pre;
ea_ctrl <= reset_ea;
-- Fetch op code
addr_ctrl <= fetch_ad;
-- Advance the PC to fetch next instruction byte
pc_ctrl <= incr_pc;
next_state <= decode1_state;
--
-- Here to decode instruction
-- and fetch next byte of intruction
-- whether it be necessary or not
--
when decode1_state =>
-- fetch first byte of address or immediate data
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
case op_code(7 downto 4) is
--
-- direct single op (2 bytes)
-- 6809 => 6 cycles
-- cpu09 => 5 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
-- 3 md_lo=(ea) / pc=pc
-- 4 alu_left=md / md=alu_out / pc=pc
-- 5 (ea)=md_lo / pc=pc
--
-- Exception is JMP
-- 6809 => 3 cycles
-- cpu09 => 3 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
-- 3 pc=ea
--
when "0000" =>
-- advance the PC
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "1110" => -- jmp
next_state <= jmp_state;
when "1111" => -- clr
next_state <= single_op_exec_state;
when others =>
next_state <= single_op_read_state;
end case;
-- acca / accb inherent instructions
when "0001" =>
case op_code(3 downto 0) is
--
-- Page2 pre byte
-- pre=(pc) / pc=pc+1
-- op=(pc) / pc=pc+1
--
when "0000" => -- page2
opfetch <= '1';
op_ctrl <= fetch_op;
-- advance pc
pc_ctrl <= incr_pc;
next_state <= decode2_state;
--
-- Page3 pre byte
-- pre=(pc) / pc=pc+1
-- op=(pc) / pc=pc+1
--
when "0001" => -- page3
opfetch <= '1';
op_ctrl <= fetch_op;
-- advance pc
pc_ctrl <= incr_pc;
next_state <= decode3_state;
--
-- nop - No operation ( 1 byte )
-- 6809 => 2 cycles
-- cpu09 => 2 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 decode
--
when "0010" => -- nop
lic <= '1';
next_state <= fetch_state;
--
-- sync - halt execution until an interrupt is received
-- interrupt may be NMI, IRQ or FIRQ
-- program execution continues if the
-- interrupt is asserted for 3 clock cycles
-- note that registers are not pushed onto the stack
-- CPU09 => Interrupts need only be asserted for one clock cycle
--
when "0011" => -- sync
next_state <= sync_state;
--
-- lbra -- long branch (3 bytes)
-- 6809 => 5 cycles
-- cpu09 => 4 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
-- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
-- 4 pc=pc+md
--
when "0110" =>
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= lbranch_state;
--
-- lbsr - long branch to subroutine (3 bytes)
-- 6809 => 9 cycles
-- cpu09 => 6 cycles
-- 1 op=(pc) /pc=pc+1
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / sp=sp-1
-- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
-- 4 (sp)= pc_lo / sp=sp-1 / pc=pc
-- 5 (sp)=pc_hi / pc=pc
-- 6 pc=pc+md
--
when "0111" =>
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= lbranch_state;
--
-- Decimal Adjust Accumulator
--
when "1001" => -- daa
left_ctrl <= acca_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_daa;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
lic <= '1';
next_state <= fetch_state;
--
-- OR Condition Codes
--
when "1010" => -- orcc
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= orcc_state;
--
-- AND Condition Codes
--
when "1100" => -- andcc
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= andcc_state;
--
-- Sign Extend
--
when "1101" => -- sex
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_sex;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
lic <= '1';
next_state <= fetch_state;
--
-- Exchange Registers
--
when "1110" => -- exg
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= exg_state;
--
-- Transfer Registers
--
when "1111" => -- tfr
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= tfr_state;
when others =>
-- increment the pc
pc_ctrl <= incr_pc;
lic <= '1';
next_state <= fetch_state;
end case;
--
-- Short branch conditional
-- 6809 => always 3 cycles
-- cpu09 => always = 3 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / test cc
-- 3 if cc tru pc=pc+md else pc=pc
--
when "0010" => -- branch conditional
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= sbranch_state;
--
-- Single byte stack operators
-- Do not advance PC
--
when "0011" =>
--
-- lea - load effective address (2+ bytes)
-- 6809 => 4 cycles + addressing mode
-- cpu09 => 4 cycles + addressing mode
-- 1 op=(pc) / pc=pc+1
-- 2 md_lo=(pc) / pc=pc+1
-- 3 calculate ea
-- 4 ix/iy/sp/up = ea
--
case op_code(3 downto 0) is
when "0000" | -- leax
"0001" | -- leay
"0010" | -- leas
"0011" => -- leau
-- advance PC
pc_ctrl <= incr_pc;
st_ctrl <= push_st;
return_state <= lea_state;
next_state <= indexed_state;
--
-- pshs - push registers onto sp stack
-- 6809 => 5 cycles + registers
-- cpu09 => 3 cycles + registers
-- 1 op=(pc) / pc=pc+1
-- 2 ea_lo=(pc) / pc=pc+1
-- 3 if ea(7 downto 0) != "00000000" then sp=sp-1
-- 4 if ea(7) = 1 (sp)=pcl, sp=sp-1
-- 5 if ea(7) = 1 (sp)=pch
-- if ea(6 downto 0) != "0000000" then sp=sp-1
-- 6 if ea(6) = 1 (sp)=upl, sp=sp-1
-- 7 if ea(6) = 1 (sp)=uph
-- if ea(5 downto 0) != "000000" then sp=sp-1
-- 8 if ea(5) = 1 (sp)=iyl, sp=sp-1
-- 9 if ea(5) = 1 (sp)=iyh
-- if ea(4 downto 0) != "00000" then sp=sp-1
-- 10 if ea(4) = 1 (sp)=ixl, sp=sp-1
-- 11 if ea(4) = 1 (sp)=ixh
-- if ea(3 downto 0) != "0000" then sp=sp-1
-- 12 if ea(3) = 1 (sp)=dp
-- if ea(2 downto 0) != "000" then sp=sp-1
-- 13 if ea(2) = 1 (sp)=accb
-- if ea(1 downto 0) != "00" then sp=sp-1
-- 14 if ea(1) = 1 (sp)=acca
-- if ea(0 downto 0) != "0" then sp=sp-1
-- 15 if ea(0) = 1 (sp)=cc
--
when "0100" => -- pshs
-- advance PC
pc_ctrl <= incr_pc;
next_state <= pshs_state;
--
-- puls - pull registers of sp stack
-- 6809 => 5 cycles + registers
-- cpu09 => 3 cycles + registers
--
when "0101" => -- puls
-- advance PC
pc_ctrl <= incr_pc;
next_state <= puls_state;
--
-- pshu - push registers onto up stack
-- 6809 => 5 cycles + registers
-- cpu09 => 3 cycles + registers
--
when "0110" => -- pshu
-- advance PC
pc_ctrl <= incr_pc;
next_state <= pshu_state;
--
-- pulu - pull registers of up stack
-- 6809 => 5 cycles + registers
-- cpu09 => 3 cycles + registers
--
when "0111" => -- pulu
-- advance PC
pc_ctrl <= incr_pc;
next_state <= pulu_state;
--
-- rts - return from subroutine
-- 6809 => 5 cycles
-- cpu09 => 4 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 decode op
-- 3 pc_hi = (sp) / sp=sp+1
-- 4 pc_lo = (sp) / sp=sp+1
--
when "1001" =>
next_state <= pull_return_hi_state;
--
-- ADD accb to index register
-- *** Note: this is an unsigned addition.
-- does not affect any condition codes
-- 6809 => 3 cycles
-- cpu09 => 2 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 alu_left=ix / alu_right=accb / ix=alu_out / pc=pc
--
when "1010" => -- abx
lic <= '1';
left_ctrl <= ix_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_abx;
ix_ctrl <= load_ix;
next_state <= fetch_state;
--
-- Return From Interrupt
--
when "1011" => -- rti
next_state <= rti_cc_state;
--
-- CWAI
--
when "1100" => -- cwai #$<cc_mask>
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- increment pc
pc_ctrl <= incr_pc;
next_state <= cwai_state;
--
-- MUL Multiply
--
when "1101" => -- mul
next_state <= mul_state;
--
-- SWI Software Interrupt
--
when "1111" => -- swi
-- predecrement SP
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= swi_iv;
st_ctrl <= push_st;
return_state <= int_swimask_state;
next_state <= int_entire_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
--
-- Accumulator A Single operand
-- source = acca, dest = acca
-- Do not advance PC
-- Typically 2 cycles 1 bytes
-- 1 opcode fetch
-- 2 post byte fetch / instruction decode
-- Note that there is no post byte
-- so do not advance PC in decode cycle
-- Re-run opcode fetch cycle after decode
--
when "0100" => -- acca single op
left_ctrl <= acca_left;
case op_code(3 downto 0) is
when "0000" => -- neg
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0011" => -- com
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0100" => -- lsr
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0110" => -- ror
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0111" => -- asr
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1000" => -- asl
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1001" => -- rol
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1010" => -- dec
right_ctrl <= one_right;
alu_ctrl <= alu_dec;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1011" => -- undefined
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
when "1100" => -- inc
right_ctrl <= one_right;
alu_ctrl <= alu_inc;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1101" => -- tst
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
acca_ctrl <= latch_acca;
cc_ctrl <= load_cc;
when "1110" => -- jmp (not defined)
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when others =>
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
end case;
lic <= '1';
next_state <= fetch_state;
--
-- Single Operand accb
-- source = accb, dest = accb
-- Typically 2 cycles 1 bytes
-- 1 opcode fetch
-- 2 post byte fetch / instruction decode
-- Note that there is no post byte
-- so do not advance PC in decode cycle
-- Re-run opcode fetch cycle after decode
--
when "0101" =>
left_ctrl <= accb_left;
case op_code(3 downto 0) is
when "0000" => -- neg
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0011" => -- com
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0100" => -- lsr
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0110" => -- ror
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0111" => -- asr
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1000" => -- asl
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1001" => -- rol
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1010" => -- dec
right_ctrl <= one_right;
alu_ctrl <= alu_dec;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1011" => -- undefined
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
when "1100" => -- inc
right_ctrl <= one_right;
alu_ctrl <= alu_inc;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1101" => -- tst
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
accb_ctrl <= latch_accb;
cc_ctrl <= load_cc;
when "1110" => -- jmp (undefined)
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when others =>
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
end case;
lic <= '1';
next_state <= fetch_state;
--
-- Single operand indexed
-- Two byte instruction so advance PC
-- EA should hold index offset
--
when "0110" => -- indexed single op
-- increment the pc
pc_ctrl <= incr_pc;
st_ctrl <= push_st;
case op_code(3 downto 0) is
when "1110" => -- jmp
return_state <= jmp_state;
when "1111" => -- clr
return_state <= single_op_exec_state;
when others =>
return_state <= single_op_read_state;
end case;
next_state <= indexed_state;
--
-- Single operand extended addressing
-- three byte instruction so advance the PC
-- Low order EA holds high order address
--
when "0111" => -- extended single op
-- increment PC
pc_ctrl <= incr_pc;
st_ctrl <= push_st;
case op_code(3 downto 0) is
when "1110" => -- jmp
return_state <= jmp_state;
when "1111" => -- clr
return_state <= single_op_exec_state;
when others =>
return_state <= single_op_read_state;
end case;
next_state <= extended_state;
when "1000" => -- acca immediate
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- subd #
"1100" | -- cmpx #
"1110" => -- ldx #
next_state <= imm16_state;
--
-- bsr offset - Branch to subroutine (2 bytes)
-- 6809 => 7 cycles
-- cpu09 => 5 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 md_hi=sign(pc) / md_lo=(pc) / sp=sp-1 / pc=pc+1
-- 3 (sp)=pc_lo / sp=sp-1
-- 4 (sp)=pc_hi
-- 5 pc=pc+md
--
when "1101" => -- bsr
-- pre decrement SP
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
--
st_ctrl <= push_st;
return_state <= sbranch_state;
next_state <= push_return_lo_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1001" => -- acca direct
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- subd
"1100" | -- cmpx
"1110" => -- ldx
next_state <= dual_op_read16_state;
when "0111" => -- sta direct
next_state <= dual_op_write8_state;
--
-- jsr direct - Jump to subroutine in direct page (2 bytes)
-- 6809 => 7 cycles
-- cpu09 => 5 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 ea_hi=0 / ea_lo=(pc) / sp=sp-1 / pc=pc+1
-- 3 (sp)=pc_lo / sp=sp-1
-- 4 (sp)=pc_hi
-- 5 pc=ea
--
when "1101" => -- jsr direct
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
--
st_ctrl <= push_st;
return_state <= jmp_state;
next_state <= push_return_lo_state;
when "1111" => -- stx direct
-- idle ALU
left_ctrl <= ix_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
next_state <= dual_op_write16_state;
when others =>
next_state <= dual_op_read8_state;
end case;
when "1010" => -- acca indexed
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- subd
"1100" | -- cmpx
"1110" => -- ldx
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when "0111" => -- staa ,x
st_ctrl <= push_st;
return_state <= dual_op_write8_state;
next_state <= indexed_state;
when "1101" => -- jsr ,x
-- DO NOT pre decrement SP
st_ctrl <= push_st;
return_state <= jsr_state;
next_state <= indexed_state;
when "1111" => -- stx ,x
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when others =>
st_ctrl <= push_st;
return_state <= dual_op_read8_state;
next_state <= indexed_state;
end case;
when "1011" => -- acca extended
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- subd
"1100" | -- cmpx
"1110" => -- ldx
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when "0111" => -- staa >
st_ctrl <= push_st;
return_state <= dual_op_write8_state;
next_state <= extended_state;
when "1101" => -- jsr >extended
-- DO NOT pre decrement sp
st_ctrl <= push_st;
return_state <= jsr_state;
next_state <= extended_state;
when "1111" => -- stx >
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when others =>
st_ctrl <= push_st;
return_state <= dual_op_read8_state;
next_state <= extended_state;
end case;
when "1100" => -- accb immediate
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- addd #
"1100" | -- ldd #
"1110" => -- ldu #
next_state <= imm16_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1101" => -- accb direct
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- addd
"1100" | -- ldd
"1110" => -- ldu
next_state <= dual_op_read16_state;
when "0111" => -- stab direct
next_state <= dual_op_write8_state;
when "1101" => -- std direct
next_state <= dual_op_write16_state;
when "1111" => -- stu direct
next_state <= dual_op_write16_state;
when others =>
next_state <= dual_op_read8_state;
end case;
when "1110" => -- accb indexed
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- addd
"1100" | -- ldd
"1110" => -- ldu
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when "0111" => -- stab indexed
st_ctrl <= push_st;
return_state <= dual_op_write8_state;
next_state <= indexed_state;
when "1101" => -- std indexed
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when "1111" => -- stu indexed
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when others =>
st_ctrl <= push_st;
return_state <= dual_op_read8_state;
next_state <= indexed_state;
end case;
when "1111" => -- accb extended
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- addd
"1100" | -- ldd
"1110" => -- ldu
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when "0111" => -- stab extended
st_ctrl <= push_st;
return_state <= dual_op_write8_state;
next_state <= extended_state;
when "1101" => -- std extended
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when "1111" => -- stu extended
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when others =>
st_ctrl <= push_st;
return_state <= dual_op_read8_state;
next_state <= extended_state;
end case;
--
-- not sure why I need this
--
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
--
-- Here to decode prefix 2 instruction
-- and fetch next byte of intruction
-- whether it be necessary or not
--
when decode2_state =>
-- fetch first byte of address or immediate data
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
case op_code(7 downto 4) is
--
-- lbcc -- long branch conditional
-- 6809 => branch 6 cycles, no branch 5 cycles
-- cpu09 => always 5 cycles
-- 1 pre=(pc) / pc=pc+1
-- 2 op=(pc) / pc=pc+1
-- 3 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
-- 4 md_hi=md_lo / md_lo=(pc) / pc=pc+1
-- 5 if cond pc=pc+md else pc=pc
--
when "0010" =>
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= lbranch_state;
--
-- Single byte stack operators
-- Do not advance PC
--
when "0011" =>
case op_code(3 downto 0) is
when "1111" => -- swi 2
-- predecrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= swi2_iv;
st_ctrl <= push_st;
return_state <= vect_hi_state;
next_state <= int_entire_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1000" => -- acca immediate
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpd #
"1100" | -- cmpy #
"1110" => -- ldy #
next_state <= imm16_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1001" => -- acca direct
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpd <
"1100" | -- cmpy <
"1110" => -- ldy <
next_state <= dual_op_read16_state;
when "1111" => -- sty <
next_state <= dual_op_write16_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1010" => -- acca indexed
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpd ,ind
"1100" | -- cmpy ,ind
"1110" => -- ldy ,ind
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when "1111" => -- sty ,ind
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1011" => -- acca extended
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpd <
"1100" | -- cmpy <
"1110" => -- ldy <
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when "1111" => -- sty >
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1100" => -- accb immediate
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- undef #
"1100" | -- undef #
"1110" => -- lds #
next_state <= imm16_state;
when others =>
next_state <= fetch_state;
end case;
when "1101" => -- accb direct
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- undef <
"1100" | -- undef <
"1110" => -- lds <
next_state <= dual_op_read16_state;
when "1111" => -- sts <
next_state <= dual_op_write16_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1110" => -- accb indexed
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- undef ,ind
"1100" | -- undef ,ind
"1110" => -- lds ,ind
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when "1111" => -- sts ,ind
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1111" => -- accb extended
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- undef >
"1100" | -- undef >
"1110" => -- lds >
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when "1111" => -- sts >
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
--
-- Here to decode instruction
-- and fetch next byte of intruction
-- whether it be necessary or not
--
when decode3_state =>
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
case op_code(7 downto 4) is
--
-- Single byte stack operators
-- Do not advance PC
--
when "0011" =>
case op_code(3 downto 0) is
when "1111" => -- swi3
-- predecrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= swi3_iv;
st_ctrl <= push_st;
return_state <= vect_hi_state;
next_state <= int_entire_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1000" => -- acca immediate
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpu #
"1100" | -- cmps #
"1110" => -- undef #
next_state <= imm16_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1001" => -- acca direct
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpu <
"1100" | -- cmps <
"1110" => -- undef <
next_state <= dual_op_read16_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1010" => -- acca indexed
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpu ,X
"1100" | -- cmps ,X
"1110" => -- undef ,X
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1011" => -- acca extended
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpu >
"1100" | -- cmps >
"1110" => -- undef >
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
--
-- here if ea holds low byte
-- Direct
-- Extended
-- Indexed
-- read memory location
--
when single_op_read_state =>
-- read memory into md
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
next_state <= single_op_exec_state;
when single_op_exec_state =>
case op_code(3 downto 0) is
when "0000" => -- neg
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "0011" => -- com
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "0100" => -- lsr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "0110" => -- ror
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "0111" => -- asr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "1000" => -- asl
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "1001" => -- rol
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "1010" => -- dec
left_ctrl <= md_left;
right_ctrl <= one_right;
alu_ctrl <= alu_dec;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "1011" => -- undefined
lic <= '1';
next_state <= fetch_state;
when "1100" => -- inc
left_ctrl <= md_left;
right_ctrl <= one_right;
alu_ctrl <= alu_inc;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "1101" => -- tst
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
lic <= '1';
next_state <= fetch_state;
when "1110" => -- jmp
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ld16;
pc_ctrl <= load_pc;
lic <= '1';
next_state <= fetch_state;
when "1111" => -- clr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
--
-- single operand 8 bit write
-- Write low 8 bits of ALU output
-- EA holds address
-- MD holds data
--
when single_op_write_state =>
-- write ALU low byte output
addr_ctrl <= write_ad;
dout_ctrl <= md_lo_dout;
lic <= '1';
next_state <= fetch_state;
--
-- here if ea holds address of low byte
-- read memory location
--
when dual_op_read8_state =>
-- read first data byte from ea
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
lic <= '1';
next_state <= fetch_state;
--
-- Here to read a 16 bit value into MD
-- pointed to by the EA register
-- The first byte is read
-- and the EA is incremented
--
when dual_op_read16_state =>
-- increment the effective address
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- read the high byte of the 16 bit data
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
next_state <= dual_op_read16_2_state;
--
-- here to read the second byte
-- pointed to by EA into MD
--
when dual_op_read16_2_state =>
-- read the low byte of the 16 bit data
md_ctrl <= fetch_next_md;
addr_ctrl <= read_ad;
lic <= '1';
next_state <= fetch_state;
--
-- 16 bit Write state
-- EA hold address of memory to write to
-- Advance the effective address in ALU
-- decode op_code to determine which
-- register to write
--
when dual_op_write16_state =>
-- increment the effective address
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- write the ALU hi byte at ea
addr_ctrl <= write_ad;
if op_code(6) = '0' then
case op_code(3 downto 0) is
when "1111" => -- stx / sty
case pre_code is
when "00010000" => -- page 2 -- sty
dout_ctrl <= iy_hi_dout;
when others => -- page 1 -- stx
dout_ctrl <= ix_hi_dout;
end case;
when others =>
dout_ctrl <= md_hi_dout;
end case;
else
case op_code(3 downto 0) is
when "1101" => -- std
dout_ctrl <= acca_dout; -- acca is high byte of ACCD
when "1111" => -- stu / sts
case pre_code is
when "00010000" => -- page 2 -- sts
dout_ctrl <= sp_hi_dout;
when others => -- page 1 -- stu
dout_ctrl <= up_hi_dout;
end case;
when others =>
dout_ctrl <= md_hi_dout;
end case;
end if;
next_state <= dual_op_write8_state;
--
-- Dual operand 8 bit write
-- Write 8 bit accumulator
-- or low byte of 16 bit register
-- EA holds address
-- decode opcode to determine
-- which register to apply to the bus
-- Also set the condition codes here
--
when dual_op_write8_state =>
if op_code(6) = '0' then
case op_code(3 downto 0) is
when "0111" => -- sta
dout_ctrl <= acca_dout;
when "1111" => -- stx / sty
case pre_code is
when "00010000" => -- page 2 -- sty
dout_ctrl <= iy_lo_dout;
when others => -- page 1 -- stx
dout_ctrl <= ix_lo_dout;
end case;
when others =>
dout_ctrl <= md_lo_dout;
end case;
else
case op_code(3 downto 0) is
when "0111" => -- stb
dout_ctrl <= accb_dout;
when "1101" => -- std
dout_ctrl <= accb_dout; -- accb is low byte of accd
when "1111" => -- stu / sts
case pre_code is
when "00010000" => -- page 2 -- sts
dout_ctrl <= sp_lo_dout;
when others => -- page 1 -- stu
dout_ctrl <= up_lo_dout;
end case;
when others =>
dout_ctrl <= md_lo_dout;
end case;
end if;
-- write ALU low byte output
addr_ctrl <= write_ad;
lic <= '1';
next_state <= fetch_state;
--
-- 16 bit immediate addressing mode
--
when imm16_state =>
-- increment pc
pc_ctrl <= incr_pc;
-- fetch next immediate byte
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
lic <= '1';
next_state <= fetch_state;
--
-- md & ea holds 8 bit index offset
-- calculate the effective memory address
-- using the alu
--
when indexed_state =>
--
-- decode indexing mode
--
if md(7) = '0' then
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= md_sign5_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
next_state <= saved_state;
else
case md(3 downto 0) is
when "0000" => -- ,R+
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
left_ctrl <= sp_left;
end case;
--
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
next_state <= postincr1_state;
when "0001" => -- ,R++
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
next_state <= postincr2_state;
when "0010" => -- ,-R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
ix_ctrl <= load_ix;
when "01" =>
left_ctrl <= iy_left;
iy_ctrl <= load_iy;
when "10" =>
left_ctrl <= up_left;
up_ctrl <= load_up;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
sp_ctrl <= load_sp;
end case;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
ea_ctrl <= load_ea;
next_state <= saved_state;
when "0011" => -- ,--R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
ix_ctrl <= load_ix;
when "01" =>
left_ctrl <= iy_left;
iy_ctrl <= load_iy;
when "10" =>
left_ctrl <= up_left;
up_ctrl <= load_up;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
sp_ctrl <= load_sp;
end case;
right_ctrl <= two_right;
alu_ctrl <= alu_sub16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "0100" => -- ,R (zero offset)
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "0101" => -- ACCB,R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= accb_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "0110" => -- ACCA,R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= acca_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "0111" => -- undefined
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "1000" => -- offset8,R
md_ctrl <= fetch_first_md; -- pick up 8 bit offset
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
next_state <= index8_state;
when "1001" => -- offset16,R
md_ctrl <= fetch_first_md; -- pick up first byte of 16 bit offset
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
next_state <= index16_state;
when "1010" => -- undefined
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
--
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "1011" => -- ACCD,R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= accd_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "1100" => -- offset8,PC
-- fetch 8 bit offset
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
next_state <= pcrel8_state;
when "1101" => -- offset16,PC
-- fetch offset
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
next_state <= pcrel16_state;
when "1110" => -- undefined
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when others =>
-- when "1111" => -- [,address]
-- advance PC to pick up address
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
next_state <= indexaddr_state;
end case;
end if;
-- load index register with ea plus one
when postincr1_state =>
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
case md(6 downto 5) is
when "00" =>
ix_ctrl <= load_ix;
when "01" =>
iy_ctrl <= load_iy;
when "10" =>
up_ctrl <= load_up;
when others =>
-- when "11" =>
sp_ctrl <= load_sp;
end case;
-- return to previous state
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
-- load index register with ea plus two
when postincr2_state =>
-- increment register by two (address)
left_ctrl <= ea_left;
right_ctrl <= two_right;
alu_ctrl <= alu_add16;
case md(6 downto 5) is
when "00" =>
ix_ctrl <= load_ix;
when "01" =>
iy_ctrl <= load_iy;
when "10" =>
up_ctrl <= load_up;
when others =>
-- when "11" =>
sp_ctrl <= load_sp;
end case;
-- return to previous state
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
--
-- ea = index register + md (8 bit signed offset)
-- ea holds post byte
--
when index8_state =>
case ea(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
-- ea = index reg + md
right_ctrl <= md_sign8_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- return to previous state
if ea(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
-- fetch low byte of 16 bit indexed offset
when index16_state =>
-- advance pc
pc_ctrl <= incr_pc;
-- fetch low byte
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
next_state <= index16_2_state;
-- ea = index register + md (16 bit offset)
-- ea holds post byte
when index16_2_state =>
case ea(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
-- ea = index reg + md
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- return to previous state
if ea(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
--
-- pc relative with 8 bit signed offest
-- md holds signed offset
--
when pcrel8_state =>
-- ea = pc + signed md
left_ctrl <= pc_left;
right_ctrl <= md_sign8_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- return to previous state
if ea(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
-- pc relative addressing with 16 bit offset
-- pick up the low byte of the offset in md
-- advance the pc
when pcrel16_state =>
-- advance pc
pc_ctrl <= incr_pc;
-- fetch low byte
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
next_state <= pcrel16_2_state;
-- pc relative with16 bit signed offest
-- md holds signed offset
when pcrel16_2_state =>
-- ea = pc + md
left_ctrl <= pc_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- return to previous state
if ea(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
-- indexed to address
-- pick up the low byte of the address
-- advance the pc
when indexaddr_state =>
-- advance pc
pc_ctrl <= incr_pc;
-- fetch low byte
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
next_state <= indexaddr2_state;
-- indexed to absolute address
-- md holds address
-- ea hold indexing mode byte
when indexaddr2_state =>
-- ea = md
left_ctrl <= pc_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
ea_ctrl <= load_ea;
-- return to previous state
if ea(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
--
-- load md with high byte of indirect address
-- pointed to by ea
-- increment ea
--
when indirect_state =>
-- increment ea
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- fetch high byte
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
next_state <= indirect2_state;
--
-- load md with low byte of indirect address
-- pointed to by ea
-- ea has previously been incremented
--
when indirect2_state =>
-- fetch high byte
md_ctrl <= fetch_next_md;
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
next_state <= indirect3_state;
--
-- complete idirect addressing
-- by loading ea with md
--
when indirect3_state =>
-- load ea with md
left_ctrl <= ea_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
ea_ctrl <= load_ea;
-- return to previous state
next_state <= saved_state;
--
-- ea holds the low byte of the absolute address
-- Move ea low byte into ea high byte
-- load new ea low byte to for absolute 16 bit address
-- advance the program counter
--
when extended_state => -- fetch ea low byte
-- increment pc
pc_ctrl <= incr_pc;
-- fetch next effective address bytes
ea_ctrl <= fetch_next_ea;
addr_ctrl <= fetch_ad;
-- return to previous state
next_state <= saved_state;
when lea_state => -- here on load effective address
-- load index register with effective address
left_ctrl <= pc_left;
right_ctrl <= ea_right;
alu_ctrl <= alu_lea;
case op_code(3 downto 0) is
when "0000" => -- leax
cc_ctrl <= load_cc;
ix_ctrl <= load_ix;
when "0001" => -- leay
cc_ctrl <= load_cc;
iy_ctrl <= load_iy;
when "0010" => -- leas
sp_ctrl <= load_sp;
when "0011" => -- leau
up_ctrl <= load_up;
when others =>
null;
end case;
lic <= '1';
next_state <= fetch_state;
--
-- jump to subroutine
-- sp=sp-1
-- call push_return_lo_state to save pc
-- return to jmp_state
--
when jsr_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- call push_return_state
st_ctrl <= push_st;
return_state <= jmp_state;
next_state <= push_return_lo_state;
--
-- Load pc with ea
-- (JMP)
--
when jmp_state =>
-- load PC with effective address
left_ctrl <= pc_left;
right_ctrl <= ea_right;
alu_ctrl <= alu_ld16;
pc_ctrl <= load_pc;
lic <= '1';
next_state <= fetch_state;
--
-- long branch or branch to subroutine
-- pick up next md byte
-- md_hi = md_lo
-- md_lo = (pc)
-- pc=pc+1
-- if a lbsr push return address
-- continue to sbranch_state
-- to evaluate conditional branches
--
when lbranch_state =>
pc_ctrl <= incr_pc;
-- fetch the next byte into md_lo
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
-- if lbsr - push return address
-- then continue on to short branch
if op_code = "00010111" then
st_ctrl <= push_st;
return_state <= sbranch_state;
next_state <= push_return_lo_state;
else
next_state <= sbranch_state;
end if;
--
-- here to execute conditional branch
-- short conditional branch md = signed 8 bit offset
-- long branch md = 16 bit offset
--
when sbranch_state =>
left_ctrl <= pc_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
-- Test condition for branch
if op_code(7 downto 4) = "0010" then -- conditional branch
case op_code(3 downto 0) is
when "0000" => -- bra
cond_true := (1 = 1);
when "0001" => -- brn
cond_true := (1 = 0);
when "0010" => -- bhi
cond_true := ((cc(CBIT) or cc(ZBIT)) = '0');
when "0011" => -- bls
cond_true := ((cc(CBIT) or cc(ZBIT)) = '1');
when "0100" => -- bcc/bhs
cond_true := (cc(CBIT) = '0');
when "0101" => -- bcs/blo
cond_true := (cc(CBIT) = '1');
when "0110" => -- bne
cond_true := (cc(ZBIT) = '0');
when "0111" => -- beq
cond_true := (cc(ZBIT) = '1');
when "1000" => -- bvc
cond_true := (cc(VBIT) = '0');
when "1001" => -- bvs
cond_true := (cc(VBIT) = '1');
when "1010" => -- bpl
cond_true := (cc(NBIT) = '0');
when "1011" => -- bmi
cond_true := (cc(NBIT) = '1');
when "1100" => -- bge
cond_true := ((cc(NBIT) xor cc(VBIT)) = '0');
when "1101" => -- blt
cond_true := ((cc(NBIT) xor cc(VBIT)) = '1');
when "1110" => -- bgt
cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0');
when "1111" => -- ble
cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1');
when others =>
null;
end case;
end if;
if cond_true then
pc_ctrl <= load_pc;
end if;
lic <= '1';
next_state <= fetch_state;
--
-- push return address onto the S stack
--
-- (sp) = pc_lo
-- sp = sp - 1
--
when push_return_lo_state =>
-- decrement the sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write PC low
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_lo_dout;
next_state <= push_return_hi_state;
--
-- push program counter hi byte onto the stack
-- (sp) = pc_hi
-- sp = sp
-- return to originating state
--
when push_return_hi_state =>
-- write pc hi bytes
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_hi_dout;
next_state <= saved_state;
--
-- RTS pull return address from stack
--
when pull_return_hi_state =>
-- increment the sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pulls_ad;
next_state <= pull_return_lo_state;
when pull_return_lo_state =>
-- increment the SP
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pulls_ad;
dout_ctrl <= pc_lo_dout;
--
lic <= '1';
next_state <= fetch_state;
when andcc_state =>
-- AND CC with md
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_andcc;
cc_ctrl <= load_cc;
--
lic <= '1';
next_state <= fetch_state;
when orcc_state =>
-- OR CC with md
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_orcc;
cc_ctrl <= load_cc;
--
lic <= '1';
next_state <= fetch_state;
when tfr_state =>
-- select source register
case md(7 downto 4) is
when "0000" =>
left_ctrl <= accd_left;
when "0001" =>
left_ctrl <= ix_left;
when "0010" =>
left_ctrl <= iy_left;
when "0011" =>
left_ctrl <= up_left;
when "0100" =>
left_ctrl <= sp_left;
when "0101" =>
left_ctrl <= pc_left;
when "1000" =>
left_ctrl <= acca_left;
when "1001" =>
left_ctrl <= accb_left;
when "1010" =>
left_ctrl <= cc_left;
when "1011" =>
left_ctrl <= dp_left;
when others =>
left_ctrl <= md_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_tfr;
-- select destination register
case md(3 downto 0) is
when "0000" => -- accd
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
when "0001" => -- ix
ix_ctrl <= load_ix;
when "0010" => -- iy
iy_ctrl <= load_iy;
when "0011" => -- up
up_ctrl <= load_up;
when "0100" => -- sp
sp_ctrl <= load_sp;
when "0101" => -- pc
pc_ctrl <= load_pc;
when "1000" => -- acca
acca_ctrl <= load_acca;
when "1001" => -- accb
accb_ctrl <= load_accb;
when "1010" => -- cc
cc_ctrl <= load_cc;
when "1011" => --dp
dp_ctrl <= load_dp;
when others =>
null;
end case;
--
lic <= '1';
next_state <= fetch_state;
when exg_state =>
-- save destination register
case md(3 downto 0) is
when "0000" =>
left_ctrl <= accd_left;
when "0001" =>
left_ctrl <= ix_left;
when "0010" =>
left_ctrl <= iy_left;
when "0011" =>
left_ctrl <= up_left;
when "0100" =>
left_ctrl <= sp_left;
when "0101" =>
left_ctrl <= pc_left;
when "1000" =>
left_ctrl <= acca_left;
when "1001" =>
left_ctrl <= accb_left;
when "1010" =>
left_ctrl <= cc_left;
when "1011" =>
left_ctrl <= dp_left;
when others =>
left_ctrl <= md_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_tfr;
ea_ctrl <= load_ea;
-- call tranfer microcode
next_state <= exg1_state;
when exg1_state =>
-- select source register
case md(7 downto 4) is
when "0000" =>
left_ctrl <= accd_left;
when "0001" =>
left_ctrl <= ix_left;
when "0010" =>
left_ctrl <= iy_left;
when "0011" =>
left_ctrl <= up_left;
when "0100" =>
left_ctrl <= sp_left;
when "0101" =>
left_ctrl <= pc_left;
when "1000" =>
left_ctrl <= acca_left;
when "1001" =>
left_ctrl <= accb_left;
when "1010" =>
left_ctrl <= cc_left;
when "1011" =>
left_ctrl <= dp_left;
when others =>
left_ctrl <= md_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_tfr;
-- select destination register
case md(3 downto 0) is
when "0000" => -- accd
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
when "0001" => -- ix
ix_ctrl <= load_ix;
when "0010" => -- iy
iy_ctrl <= load_iy;
when "0011" => -- up
up_ctrl <= load_up;
when "0100" => -- sp
sp_ctrl <= load_sp;
when "0101" => -- pc
pc_ctrl <= load_pc;
when "1000" => -- acca
acca_ctrl <= load_acca;
when "1001" => -- accb
accb_ctrl <= load_accb;
when "1010" => -- cc
cc_ctrl <= load_cc;
when "1011" => --dp
dp_ctrl <= load_dp;
when others =>
null;
end case;
next_state <= exg2_state;
when exg2_state =>
-- restore destination
left_ctrl <= ea_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_tfr;
-- save as source register
case md(7 downto 4) is
when "0000" => -- accd
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
when "0001" => -- ix
ix_ctrl <= load_ix;
when "0010" => -- iy
iy_ctrl <= load_iy;
when "0011" => -- up
up_ctrl <= load_up;
when "0100" => -- sp
sp_ctrl <= load_sp;
when "0101" => -- pc
pc_ctrl <= load_pc;
when "1000" => -- acca
acca_ctrl <= load_acca;
when "1001" => -- accb
accb_ctrl <= load_accb;
when "1010" => -- cc
cc_ctrl <= load_cc;
when "1011" => --dp
dp_ctrl <= load_dp;
when others =>
null;
end case;
lic <= '1';
next_state <= fetch_state;
when mul_state =>
-- move acca to md
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
md_ctrl <= load_md;
next_state <= mulea_state;
when mulea_state =>
-- move accb to ea
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
ea_ctrl <= load_ea;
next_state <= muld_state;
when muld_state =>
-- clear accd
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ld8;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
next_state <= mul0_state;
when mul0_state =>
-- if bit 0 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(0) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul1_state;
when mul1_state =>
-- if bit 1 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(1) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul2_state;
when mul2_state =>
-- if bit 2 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(2) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul3_state;
when mul3_state =>
-- if bit 3 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(3) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul4_state;
when mul4_state =>
-- if bit 4 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(4) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul5_state;
when mul5_state =>
-- if bit 5 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(5) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul6_state;
when mul6_state =>
-- if bit 6 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(6) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul7_state;
when mul7_state =>
-- if bit 7 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(7) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
lic <= '1';
next_state <= fetch_state;
--
-- Enter here on pushs
-- ea holds post byte
--
when pshs_state =>
-- decrement sp if any registers to be pushed
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
-- idle address
addr_ctrl <= idle_ad;
dout_ctrl <= cc_dout;
if ea(7 downto 0) = "00000000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
if ea(7) = '1' then
next_state <= pshs_pcl_state;
elsif ea(6) = '1' then
next_state <= pshs_upl_state;
elsif ea(5) = '1' then
next_state <= pshs_iyl_state;
elsif ea(4) = '1' then
next_state <= pshs_ixl_state;
elsif ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_pcl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_lo_dout;
next_state <= pshs_pch_state;
when pshs_pch_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(6 downto 0) = "0000000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write pc hi
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_hi_dout;
if ea(6) = '1' then
next_state <= pshs_upl_state;
elsif ea(5) = '1' then
next_state <= pshs_iyl_state;
elsif ea(4) = '1' then
next_state <= pshs_ixl_state;
elsif ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_upl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= pushs_ad;
dout_ctrl <= up_lo_dout;
next_state <= pshs_uph_state;
when pshs_uph_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(5 downto 0) = "000000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write pc hi
addr_ctrl <= pushs_ad;
dout_ctrl <= up_hi_dout;
if ea(5) = '1' then
next_state <= pshs_iyl_state;
elsif ea(4) = '1' then
next_state <= pshs_ixl_state;
elsif ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_iyl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write iy low
addr_ctrl <= pushs_ad;
dout_ctrl <= iy_lo_dout;
next_state <= pshs_iyh_state;
when pshs_iyh_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(4 downto 0) = "00000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write iy hi
addr_ctrl <= pushs_ad;
dout_ctrl <= iy_hi_dout;
if ea(4) = '1' then
next_state <= pshs_ixl_state;
elsif ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_ixl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix low
addr_ctrl <= pushs_ad;
dout_ctrl <= ix_lo_dout;
next_state <= pshs_ixh_state;
when pshs_ixh_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(3 downto 0) = "0000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write ix hi
addr_ctrl <= pushs_ad;
dout_ctrl <= ix_hi_dout;
if ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_dp_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(2 downto 0) = "000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write dp
addr_ctrl <= pushs_ad;
dout_ctrl <= dp_dout;
if ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_accb_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(1 downto 0) = "00" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write accb
addr_ctrl <= pushs_ad;
dout_ctrl <= accb_dout;
if ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_acca_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(0) = '1' then
sp_ctrl <= load_sp;
else
sp_ctrl <= latch_sp;
end if;
-- write acca
addr_ctrl <= pushs_ad;
dout_ctrl <= acca_dout;
if ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_cc_state =>
-- idle sp
-- write cc
addr_ctrl <= pushs_ad;
dout_ctrl <= cc_dout;
lic <= '1';
next_state <= fetch_state;
--
-- enter here on PULS
-- ea hold register mask
--
when puls_state =>
if ea(0) = '1' then
next_state <= puls_cc_state;
elsif ea(1) = '1' then
next_state <= puls_acca_state;
elsif ea(2) = '1' then
next_state <= puls_accb_state;
elsif ea(3) = '1' then
next_state <= puls_dp_state;
elsif ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_cc_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read cc
cc_ctrl <= pull_cc;
addr_ctrl <= pulls_ad;
if ea(1) = '1' then
next_state <= puls_acca_state;
elsif ea(2) = '1' then
next_state <= puls_accb_state;
elsif ea(3) = '1' then
next_state <= puls_dp_state;
elsif ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_acca_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read acca
acca_ctrl <= pull_acca;
addr_ctrl <= pulls_ad;
if ea(2) = '1' then
next_state <= puls_accb_state;
elsif ea(3) = '1' then
next_state <= puls_dp_state;
elsif ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_accb_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read accb
accb_ctrl <= pull_accb;
addr_ctrl <= pulls_ad;
if ea(3) = '1' then
next_state <= puls_dp_state;
elsif ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_dp_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read dp
dp_ctrl <= pull_dp;
addr_ctrl <= pulls_ad;
if ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_ixh_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull ix hi
ix_ctrl <= pull_hi_ix;
addr_ctrl <= pulls_ad;
next_state <= puls_ixl_state;
when puls_ixl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read ix low
ix_ctrl <= pull_lo_ix;
addr_ctrl <= pulls_ad;
if ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_iyh_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull iy hi
iy_ctrl <= pull_hi_iy;
addr_ctrl <= pulls_ad;
next_state <= puls_iyl_state;
when puls_iyl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read iy low
iy_ctrl <= pull_lo_iy;
addr_ctrl <= pulls_ad;
if ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_uph_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull up hi
up_ctrl <= pull_hi_up;
addr_ctrl <= pulls_ad;
next_state <= puls_upl_state;
when puls_upl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read up low
up_ctrl <= pull_lo_up;
addr_ctrl <= pulls_ad;
if ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_pch_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pulls_ad;
next_state <= puls_pcl_state;
when puls_pcl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pulls_ad;
lic <= '1';
next_state <= fetch_state;
--
-- Enter here on pshu
-- ea holds post byte
--
when pshu_state =>
-- decrement up if any registers to be pushed
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(7 downto 0) = "00000000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write idle bus
if ea(7) = '1' then
next_state <= pshu_pcl_state;
elsif ea(6) = '1' then
next_state <= pshu_spl_state;
elsif ea(5) = '1' then
next_state <= pshu_iyl_state;
elsif ea(4) = '1' then
next_state <= pshu_ixl_state;
elsif ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
--
-- push PC onto U stack
--
when pshu_pcl_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
up_ctrl <= load_up;
-- write pc low
addr_ctrl <= pushu_ad;
dout_ctrl <= pc_lo_dout;
next_state <= pshu_pch_state;
when pshu_pch_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(6 downto 0) = "0000000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write pc hi
addr_ctrl <= pushu_ad;
dout_ctrl <= pc_hi_dout;
if ea(6) = '1' then
next_state <= pshu_spl_state;
elsif ea(5) = '1' then
next_state <= pshu_iyl_state;
elsif ea(4) = '1' then
next_state <= pshu_ixl_state;
elsif ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_spl_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
up_ctrl <= load_up;
-- write sp low
addr_ctrl <= pushu_ad;
dout_ctrl <= sp_lo_dout;
next_state <= pshu_sph_state;
when pshu_sph_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(5 downto 0) = "000000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write sp hi
addr_ctrl <= pushu_ad;
dout_ctrl <= sp_hi_dout;
if ea(5) = '1' then
next_state <= pshu_iyl_state;
elsif ea(4) = '1' then
next_state <= pshu_ixl_state;
elsif ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_iyl_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
up_ctrl <= load_up;
-- write iy low
addr_ctrl <= pushu_ad;
dout_ctrl <= iy_lo_dout;
next_state <= pshu_iyh_state;
when pshu_iyh_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(4 downto 0) = "00000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write iy hi
addr_ctrl <= pushu_ad;
dout_ctrl <= iy_hi_dout;
if ea(4) = '1' then
next_state <= pshu_ixl_state;
elsif ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_ixl_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
up_ctrl <= load_up;
-- write ix low
addr_ctrl <= pushu_ad;
dout_ctrl <= ix_lo_dout;
next_state <= pshu_ixh_state;
when pshu_ixh_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(3 downto 0) = "0000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write ix hi
addr_ctrl <= pushu_ad;
dout_ctrl <= ix_hi_dout;
if ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_dp_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(2 downto 0) = "000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write dp
addr_ctrl <= pushu_ad;
dout_ctrl <= dp_dout;
if ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_accb_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(1 downto 0) = "00" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write accb
addr_ctrl <= pushu_ad;
dout_ctrl <= accb_dout;
if ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_acca_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(0) = '0' then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write acca
addr_ctrl <= pushu_ad;
dout_ctrl <= acca_dout;
if ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_cc_state =>
-- idle up
-- write cc
addr_ctrl <= pushu_ad;
dout_ctrl <= cc_dout;
lic <= '1';
next_state <= fetch_state;
--
-- enter here on PULU
-- ea hold register mask
--
when pulu_state =>
-- idle UP
-- idle bus
if ea(0) = '1' then
next_state <= pulu_cc_state;
elsif ea(1) = '1' then
next_state <= pulu_acca_state;
elsif ea(2) = '1' then
next_state <= pulu_accb_state;
elsif ea(3) = '1' then
next_state <= pulu_dp_state;
elsif ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_cc_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read cc
cc_ctrl <= pull_cc;
addr_ctrl <= pullu_ad;
if ea(1) = '1' then
next_state <= pulu_acca_state;
elsif ea(2) = '1' then
next_state <= pulu_accb_state;
elsif ea(3) = '1' then
next_state <= pulu_dp_state;
elsif ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_acca_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read acca
acca_ctrl <= pull_acca;
addr_ctrl <= pullu_ad;
if ea(2) = '1' then
next_state <= pulu_accb_state;
elsif ea(3) = '1' then
next_state <= pulu_dp_state;
elsif ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_accb_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read accb
accb_ctrl <= pull_accb;
addr_ctrl <= pullu_ad;
if ea(3) = '1' then
next_state <= pulu_dp_state;
elsif ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_dp_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read dp
dp_ctrl <= pull_dp;
addr_ctrl <= pullu_ad;
if ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_ixh_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read ix hi
ix_ctrl <= pull_hi_ix;
addr_ctrl <= pullu_ad;
next_state <= pulu_ixl_state;
when pulu_ixl_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read ix low
ix_ctrl <= pull_lo_ix;
addr_ctrl <= pullu_ad;
if ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_iyh_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read iy hi
iy_ctrl <= pull_hi_iy;
addr_ctrl <= pullu_ad;
next_state <= pulu_iyl_state;
when pulu_iyl_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read iy low
iy_ctrl <= pull_lo_iy;
addr_ctrl <= pullu_ad;
if ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_sph_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read sp hi
sp_ctrl <= pull_hi_sp;
addr_ctrl <= pullu_ad;
next_state <= pulu_spl_state;
when pulu_spl_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read sp low
sp_ctrl <= pull_lo_sp;
addr_ctrl <= pullu_ad;
if ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_pch_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- pull pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pullu_ad;
next_state <= pulu_pcl_state;
when pulu_pcl_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pullu_ad;
lic <= '1';
next_state <= fetch_state;
--
-- pop the Condition codes
--
when rti_cc_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read cc
cc_ctrl <= pull_cc;
addr_ctrl <= pulls_ad;
next_state <= rti_entire_state;
--
-- Added RTI cycle 11th July 2006 John Kent.
-- test the "Entire" Flag
-- that has just been popped off the stack
--
when rti_entire_state =>
--
-- The Entire flag must be recovered from the stack
-- before testing.
--
if cc(EBIT) = '1' then
next_state <= rti_acca_state;
else
next_state <= rti_pch_state;
end if;
when rti_acca_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read acca
acca_ctrl <= pull_acca;
addr_ctrl <= pulls_ad;
next_state <= rti_accb_state;
when rti_accb_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read accb
accb_ctrl <= pull_accb;
addr_ctrl <= pulls_ad;
next_state <= rti_dp_state;
when rti_dp_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read dp
dp_ctrl <= pull_dp;
addr_ctrl <= pulls_ad;
next_state <= rti_ixh_state;
when rti_ixh_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read ix hi
ix_ctrl <= pull_hi_ix;
addr_ctrl <= pulls_ad;
next_state <= rti_ixl_state;
when rti_ixl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read ix low
ix_ctrl <= pull_lo_ix;
addr_ctrl <= pulls_ad;
next_state <= rti_iyh_state;
when rti_iyh_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read iy hi
iy_ctrl <= pull_hi_iy;
addr_ctrl <= pulls_ad;
next_state <= rti_iyl_state;
when rti_iyl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read iy low
iy_ctrl <= pull_lo_iy;
addr_ctrl <= pulls_ad;
next_state <= rti_uph_state;
when rti_uph_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read up hi
up_ctrl <= pull_hi_up;
addr_ctrl <= pulls_ad;
next_state <= rti_upl_state;
when rti_upl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read up low
up_ctrl <= pull_lo_up;
addr_ctrl <= pulls_ad;
next_state <= rti_pch_state;
when rti_pch_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pulls_ad;
next_state <= rti_pcl_state;
when rti_pcl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pulls_ad;
lic <= '1';
next_state <= fetch_state;
--
-- here on NMI interrupt
-- Complete execute cycle of the last instruction.
-- If it was a dual operand instruction
--
when int_nmi_state =>
next_state <= int_nmi1_state;
-- Idle bus cycle
when int_nmi1_state =>
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= nmi_iv;
st_ctrl <= push_st;
return_state <= int_nmimask_state;
next_state <= int_entire_state;
--
-- here on IRQ interrupt
-- Complete execute cycle of the last instruction.
-- If it was a dual operand instruction
--
when int_irq_state =>
next_state <= int_irq1_state;
-- pre decrement the sp
-- Idle bus cycle
when int_irq1_state =>
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= irq_iv;
st_ctrl <= push_st;
return_state <= int_irqmask_state;
next_state <= int_entire_state;
--
-- here on FIRQ interrupt
-- Complete execution cycle of the last instruction
-- if it was a dual operand instruction
--
when int_firq_state =>
next_state <= int_firq1_state;
-- Idle bus cycle
when int_firq1_state =>
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= firq_iv;
st_ctrl <= push_st;
return_state <= int_firqmask_state;
next_state <= int_fast_state;
--
-- CWAI entry point
-- stack pointer already pre-decremented
-- mask condition codes
--
when cwai_state =>
-- AND CC with md
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_andcc;
cc_ctrl <= load_cc;
st_ctrl <= push_st;
return_state <= int_cwai_state;
next_state <= int_entire_state;
--
-- wait here for an interrupt
--
when int_cwai_state =>
if (nmi_req = '1') then
iv_ctrl <= nmi_iv;
next_state <= int_nmimask_state;
--
-- FIRQ & IRQ are level sensitive
--
elsif (firq = '1') and (cc(FBIT) = '0') then
iv_ctrl <= firq_iv;
next_state <= int_firqmask_state;
elsif (irq = '1') and (cc(IBIT) = '0') then
iv_ctrl <= irq_iv;
next_state <= int_irqmask_state;
else
next_state <= int_cwai_state;
end if;
--
-- State to mask I Flag and F Flag (NMI)
--
when int_nmimask_state =>
alu_ctrl <= alu_seif;
cc_ctrl <= load_cc;
next_state <= vect_hi_state;
--
-- State to mask I Flag and F Flag (FIRQ)
--
when int_firqmask_state =>
alu_ctrl <= alu_seif;
cc_ctrl <= load_cc;
next_state <= vect_hi_state;
--
-- State to mask I Flag and F Flag (SWI)
--
when int_swimask_state =>
alu_ctrl <= alu_seif;
cc_ctrl <= load_cc;
next_state <= vect_hi_state;
--
-- State to mask I Flag only (IRQ)
--
when int_irqmask_state =>
alu_ctrl <= alu_sei;
cc_ctrl <= load_cc;
next_state <= vect_hi_state;
--
-- set Entire Flag on SWI, SWI2, SWI3 and CWAI, IRQ and NMI
-- before stacking all registers
--
when int_entire_state =>
-- set entire flag
alu_ctrl <= alu_see;
cc_ctrl <= load_cc;
next_state <= int_pcl_state;
--
-- clear Entire Flag on FIRQ
-- before stacking all registers
--
when int_fast_state =>
-- clear entire flag
alu_ctrl <= alu_cle;
cc_ctrl <= load_cc;
next_state <= int_pcl_state;
when int_pcl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_lo_dout;
next_state <= int_pch_state;
when int_pch_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write pc hi
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_hi_dout;
if cc(EBIT) = '1' then
next_state <= int_upl_state;
else
next_state <= int_cc_state;
end if;
when int_upl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write up low
addr_ctrl <= pushs_ad;
dout_ctrl <= up_lo_dout;
next_state <= int_uph_state;
when int_uph_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix hi
addr_ctrl <= pushs_ad;
dout_ctrl <= up_hi_dout;
next_state <= int_iyl_state;
when int_iyl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix low
addr_ctrl <= pushs_ad;
dout_ctrl <= iy_lo_dout;
next_state <= int_iyh_state;
when int_iyh_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix hi
addr_ctrl <= pushs_ad;
dout_ctrl <= iy_hi_dout;
next_state <= int_ixl_state;
when int_ixl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix low
addr_ctrl <= pushs_ad;
dout_ctrl <= ix_lo_dout;
next_state <= int_ixh_state;
when int_ixh_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix hi
addr_ctrl <= pushs_ad;
dout_ctrl <= ix_hi_dout;
next_state <= int_dp_state;
when int_dp_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write accb
addr_ctrl <= pushs_ad;
dout_ctrl <= dp_dout;
next_state <= int_accb_state;
when int_accb_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write accb
addr_ctrl <= pushs_ad;
dout_ctrl <= accb_dout;
next_state <= int_acca_state;
when int_acca_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write acca
addr_ctrl <= pushs_ad;
dout_ctrl <= acca_dout;
next_state <= int_cc_state;
when int_cc_state =>
-- write cc
addr_ctrl <= pushs_ad;
dout_ctrl <= cc_dout;
next_state <= saved_state;
--
-- According to the 6809 programming manual:
-- If an interrupt is received and is masked
-- or lasts for less than three cycles, the PC
-- will advance to the next instruction.
-- If an interrupt is unmasked and lasts
-- for more than three cycles, an interrupt
-- will be generated.
-- Note that I don't wait 3 clock cycles.
-- John Kent 11th July 2006
--
when sync_state =>
lic <= '1';
ba <= '1';
next_state <= sync_state;
when halt_state =>
--
-- 2011-10-30 John Kent
-- ba & bs should be high
ba <= '1';
bs <= '1';
if halt = '1' then
next_state <= halt_state;
else
next_state <= fetch_state;
end if;
end case;
--
-- Ver 1.23 2011-10-30 John Kent
-- First instruction cycle might be
-- fetch_state
-- halt_state
-- int_nmirq_state
-- int_firq_state
--
if fic = '1' then
--
case op_code(7 downto 6) is
when "10" => -- acca
case op_code(3 downto 0) is
when "0000" => -- suba
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "0001" => -- cmpa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
when "0010" => -- sbca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "0011" =>
case pre_code is
when "00010000" => -- page 2 -- cmpd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
when "00010001" => -- page 3 -- cmpu
left_ctrl <= up_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
when others => -- page 1 -- subd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
end case;
when "0100" => -- anda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "0101" => -- bita
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
when "0110" => -- ldaa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "0111" => -- staa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
when "1000" => -- eora
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "1001" => -- adca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "1010" => -- oraa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "1011" => -- adda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "1100" =>
case pre_code is
when "00010000" => -- page 2 -- cmpy
left_ctrl <= iy_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
when "00010001" => -- page 3 -- cmps
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
when others => -- page 1 -- cmpx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
end case;
when "1101" => -- bsr / jsr
null;
when "1110" => -- ldx
case pre_code is
when "00010000" => -- page 2 -- ldy
left_ctrl <= iy_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
iy_ctrl <= load_iy;
when others => -- page 1 -- ldx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
ix_ctrl <= load_ix;
end case;
when "1111" => -- stx
case pre_code is
when "00010000" => -- page 2 -- sty
left_ctrl <= iy_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
when others => -- page 1 -- stx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
end case;
when others =>
null;
end case;
when "11" => -- accb dual op
case op_code(3 downto 0) is
when "0000" => -- subb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "0001" => -- cmpb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
when "0010" => -- sbcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "0011" => -- addd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
when "0100" => -- andb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "0101" => -- bitb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
when "0110" => -- ldab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "0111" => -- stab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
when "1000" => -- eorb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "1001" => -- adcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "1010" => -- orab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "1011" => -- addb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "1100" => -- ldd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
when "1101" => -- std
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
when "1110" => -- ldu
case pre_code is
when "00010000" => -- page 2 -- lds
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
sp_ctrl <= load_sp;
when others => -- page 1 -- ldu
left_ctrl <= up_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
up_ctrl <= load_up;
end case;
when "1111" =>
case pre_code is
when "00010000" => -- page 2 -- sts
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
when others => -- page 1 -- stu
left_ctrl <= up_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
end case;
when others =>
null;
end case;
when others =>
null;
end case;
end if; -- first instruction cycle (fic)
lic_out <= lic;
end process;
end rtl;
|
--===========================================================================--
-- --
-- Synthesizable 6809 instruction compatible VHDL CPU core --
-- --
--===========================================================================--
--
-- File name : cpu09l.vhd
--
-- Entity name : cpu09
--
-- Purpose : 6809 instruction compatible CPU core written in VHDL
-- with Last Instruction Cycle, bus available, bus status,
-- and instruction fetch signals.
-- Not cycle compatible with the original 6809 CPU
--
-- Dependencies : ieee.std_logic_1164
-- ieee.std_logic_unsigned
--
-- Author : John E. Kent
--
-- Email : [email protected]
--
-- Web : http://opencores.org/project,system09
--
-- Description : VMA (valid memory address) is hight whenever a valid memory
-- access is made by an instruction fetch, interrupt vector fetch
-- or a data read or write otherwise it is low indicating an idle
-- bus cycle.
-- IFETCH (instruction fetch output) is high whenever an
-- instruction byte is read i.e. the program counter is applied
-- to the address bus.
-- LIC (last instruction cycle output) is normally low
-- but goes high on the last cycle of an instruction.
-- BA (bus available output) is normally low but goes high while
-- waiting in a Sync instruction state or the CPU is halted
-- i.e. a DMA grant.
-- BS (bus status output) is normally low but goes high during an
-- interrupt or reset vector fetch or the processor is halted
-- i.e. a DMA grant.
--
-- Copyright (C) 2003 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
--
-- Version 0.1 - 26 June 2003 - John Kent
-- Added extra level in state stack
-- fixed some calls to the extended addressing state
--
-- Version 0.2 - 5 Sept 2003 - John Kent
-- Fixed 16 bit indexed offset (was doing read rather than fetch)
-- Added/Fixed STY and STS instructions.
-- ORCC_STATE ANDed CC state rather than ORed it - Now fixed
-- CMPX Loaded ACCA and ACCB - Now fixed
--
-- Version 1.0 - 6 Sep 2003 - John Kent
-- Initial release to Open Cores
-- reversed clock edge
--
-- Version 1.1 - 29 November 2003 John kent
-- ACCA and ACCB indexed offsets are 2's complement.
-- ALU Right Mux now sign extends ACCA & ACCB offsets
-- Absolute Indirect addressing performed a read on the
-- second byte of the address rather than a fetch
-- so it formed an incorrect address. Now fixed.
--
-- Version 1.2 - 29 November 2003 John Kent
-- LEAX and LEAY affect the Z bit only
-- LEAS and LEAU do not affect any condition codes
-- added an extra ALU control for LEA.
--
-- Version 1.3 - 12 December 2003 John Kent
-- CWAI did not work, was missed a PUSH_ST on calling
-- the ANDCC_STATE. Thanks go to Ghassan Kraidy for
-- finding this fault.
--
-- Version 1.4 - 12 December 2003 John Kent
-- Missing cc_ctrl assignment in otherwise case of
-- lea_state resulted in cc_ctrl being latched in
-- that state.
-- The otherwise statement should never be reached,
-- and has been fixed simply to resolve synthesis warnings.
--
-- Version 1.5 - 17 january 2004 John kent
-- The clear instruction used "alu_ld8" to control the ALU
-- rather than "alu_clr". This mean the Carry was not being
-- cleared correctly.
--
-- Version 1.6 - 24 January 2004 John Kent
-- Fixed problems in PSHU instruction
--
-- Version 1.7 - 25 January 2004 John Kent
-- removed redundant "alu_inx" and "alu_dex'
-- Removed "test_alu" and "test_cc"
-- STD instruction did not set condition codes
-- JMP direct was not decoded properly
-- CLR direct performed an unwanted read cycle
-- Bogus "latch_md" in Page2 indexed addressing
--
-- Version 1.8 - 27 January 2004 John Kent
-- CWAI in decode1_state should increment the PC.
-- ABX is supposed to be an unsigned addition.
-- Added extra ALU function
-- ASR8 slightly changed in the ALU.
--
-- Version 1.9 - 20 August 2005
-- LSR8 is now handled in ASR8 and ROR8 case in the ALU,
-- rather than LSR16. There was a problem with single
-- operand instructions using the MD register which is
-- sign extended on the first 8 bit fetch.
--
-- Version 1.10 - 13 September 2005
-- TFR & EXG instructions did not work for the Condition Code Register
-- An extra case has been added to the ALU for the alu_tfr control
-- to assign the left ALU input (alu_left) to the condition code
-- outputs (cc_out).
--
-- Version 1.11 - 16 September 2005
-- JSR ,X should not predecrement S before calculating the jump address.
-- The reason is that JSR [0,S] needs S to point to the top of the stack
-- to fetch a valid vector address. The solution is to have the addressing
-- mode microcode called before decrementing S and then decrementing S in
-- JSR_STATE. JSR_STATE in turn calls PUSH_RETURN_LO_STATE rather than
-- PUSH_RETURN_HI_STATE so that both the High & Low halves of the PC are
-- pushed on the stack. This adds one extra bus cycle, but resolves the
-- addressing conflict. I've also removed the pre-decement S in
-- JSR EXTENDED as it also calls JSR_STATE.
--
-- Version 1.12 - 6th June 2006
-- 6809 Programming reference manual says V is not affected by ASR, LSR and ROR
-- This is different to the 6800. CLR should reset the V bit.
--
-- Version 1.13 - 7th July 2006
-- Disable NMI on reset until S Stack pointer has been loaded.
-- Added nmi_enable signal in sp_reg process and nmi_handler process.
--
-- Version 1.14 - 11th July 2006
-- 1. Added new state to RTI called rti_entire_state.
-- This state tests the CC register after it has been loaded
-- from the stack. Previously the current CC was tested which
-- was incorrect. The Entire Flag should be set before the
-- interrupt stacks the CC.
-- 2. On bogus Interrupts, int_cc_state went to rti_state,
-- which was an enumerated state, but not defined anywhere.
-- rti_state has been changed to rti_cc_state so that bogus interrupt
-- will perform an RTI after entering that state.
-- 3. Sync should generate an interrupt if the interrupt masks
-- are cleared. If the interrupt masks are set, then an interrupt
-- will cause the the PC to advance to the next instruction.
-- Note that I don't wait for an interrupt to be asserted for
-- three clock cycles.
-- 4. Added new ALU control state "alu_mul". "alu_mul" is used in
-- the Multiply instruction replacing "alu_add16". This is similar
-- to "alu_add16" except it sets the Carry bit to B7 of the result
-- in ACCB, sets the Zero bit if the 16 bit result is zero, but
-- does not affect The Half carry (H), Negative (N) or Overflow (V)
-- flags. The logic was re-arranged so that it adds md or zero so
-- that the Carry condition code is set on zero multiplicands.
-- 5. DAA (Decimal Adjust Accumulator) should set the Negative (N)
-- and Zero Flags. It will also affect the Overflow (V) flag although
-- the operation is undefined. It's anyones guess what DAA does to V.
--
-- Version 1.15 - 25th Feb 2007 - John Kent
-- line 9672 changed "if Halt <= '1' then" to "if Halt = '1' then"
-- Changed sensitivity lists.
--
-- Version 1.16 - 5th February 2008 - John Kent
-- FIRQ interrupts should take priority over IRQ Interrupts.
-- This presumably means they should be tested for before IRQ
-- when they happen concurrently.
--
-- Version 1.17 - 18th February 2008 - John Kent
-- NMI in CWAI should mask IRQ and FIRQ interrupts
--
-- Version 1.18 - 21st February 2008 - John Kent
-- Removed default register settings in each case statement
-- and placed them at the beginning of the state sequencer.
-- Modified the SYNC instruction so that the interrupt vector(iv)
-- is not set unless an unmasked FIRQ or IRQ is received.
--
-- Version 1.19 - 25th February 2008 - John Kent
-- Enumerated separate states for FIRQ/FAST and NMIIRQ/ENTIRE
-- Enumerated separate states for MASKI and MASKIF states
-- Removed code on BSR/JSR in fetch cycle
--
-- Version 1.20 - 8th October 2011 - John Kent
-- added fetch output which should go high during the fetch cycle
--
-- Version 1.21 - 8th October 2011 - John Kent
-- added Last Instruction Cycle signal
-- replaced fetch with ifetch (instruction fetch) signal
-- added ba & bs (bus available & bus status) signals
--
-- Version 1.22 - 2011-10-29 John Kent
-- The halt state isn't correct.
-- The halt state is entered into from the fetch_state
-- It returned to the fetch state which may re-run an execute cycle
-- on the accumulator and it won't necessarily be the last instruction cycle
-- I've changed the halt state to return to the decode1_state
--
-- Version 1.23 - 2011-10-30 John Kent
-- sample halt in the change_state process if lic is high (last instruction cycle)
--
-- Version 1.24 - 2011-11-01 John Kent
-- Handle interrupts in change_state process
-- Sample interrupt inputs on last instruction cycle
-- Remove iv_ctrl and implement iv (interrupt vector) in change_state process.
-- Generate fic (first instruction cycle) from lic (last instruction cycle)
-- and use it to complete the dual operand execute cycle before servicing
-- halt or interrupts requests.
-- rename lic to lic_out on the entity declaration so that lic can be tested internally.
-- add int_firq1_state and int_nmirq1_state to allow for the dual operand execute cycle
-- integrated nmi_ctrl into change_state process
-- Reduces the microcode state stack to one entry (saved_state)
-- imm16_state jumps directly to the fetch_state
-- pull_return_lo states jumps directly to the fetch_state
-- duplicate andcc_state as cwai_state
-- rename exg1_state as exg2 state and duplicate tfr_state as exg1_state
--
-- Version 1.25 - 2011-11-27 John Kent
-- Changed the microcode for saving registers on an interrupt into a microcode subroutine.
-- Removed SWI servicing from the change state process and made SWI, SWI2 & SWI3
-- call the interrupt microcode subroutine.
-- Added additional states for nmi, and irq for interrupt servicing.
-- Added additional states for nmi/irq, firq, and swi interrupts to mask I & F flags.
--
-- Version 1.26 - 2013-03-18 John Kent
-- pre-initialized cond_true variable to true in state sequencer
-- re-arranged change_state process slightly
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cpu09 is
port (
clk : in std_logic; -- E clock input (rising edge)
rst : in std_logic; -- reset input (active high)
vma : out std_logic; -- valid memory address (active high)
lic_out : out std_logic; -- last instruction cycle (active high)
ifetch : out std_logic; -- instruction fetch cycle (active high)
opfetch : out std_logic; -- opcode fetch (active high)
ba : out std_logic; -- bus available (high on sync wait or DMA grant)
bs : out std_logic; -- bus status (high on interrupt or reset vector fetch or DMA grant)
addr : out std_logic_vector(15 downto 0); -- address bus output
rw : out std_logic; -- read not write output
data_out : out std_logic_vector(7 downto 0); -- data bus output
data_in : in std_logic_vector(7 downto 0); -- data bus input
irq : in std_logic; -- interrupt request input (active high)
firq : in std_logic; -- fast interrupt request input (active high)
nmi : in std_logic; -- non maskable interrupt request input (active high)
halt : in std_logic; -- halt input (active high) grants DMA
hold : in std_logic; -- hold input (active high) extend bus cycle
Regs : out std_logic_vector(111 downto 0)
);
end cpu09;
architecture rtl of cpu09 is
constant EBIT : integer := 7;
constant FBIT : integer := 6;
constant HBIT : integer := 5;
constant IBIT : integer := 4;
constant NBIT : integer := 3;
constant ZBIT : integer := 2;
constant VBIT : integer := 1;
constant CBIT : integer := 0;
--
-- Interrupt vector modifiers
--
constant RST_VEC : std_logic_vector(2 downto 0) := "111";
constant NMI_VEC : std_logic_vector(2 downto 0) := "110";
constant SWI_VEC : std_logic_vector(2 downto 0) := "101";
constant IRQ_VEC : std_logic_vector(2 downto 0) := "100";
constant FIRQ_VEC : std_logic_vector(2 downto 0) := "011";
constant SWI2_VEC : std_logic_vector(2 downto 0) := "010";
constant SWI3_VEC : std_logic_vector(2 downto 0) := "001";
constant RESV_VEC : std_logic_vector(2 downto 0) := "000";
type state_type is (-- Start off in Reset
reset_state,
-- Fetch Interrupt Vectors (including reset)
vect_lo_state, vect_hi_state, vect_idle_state,
-- Fetch Instruction Cycle
fetch_state,
-- Decode Instruction Cycles
decode1_state, decode2_state, decode3_state,
-- Calculate Effective Address
imm16_state,
indexed_state, index8_state, index16_state, index16_2_state,
pcrel8_state, pcrel16_state, pcrel16_2_state,
indexaddr_state, indexaddr2_state,
postincr1_state, postincr2_state,
indirect_state, indirect2_state, indirect3_state,
extended_state,
-- single ops
single_op_read_state,
single_op_exec_state,
single_op_write_state,
-- Dual op states
dual_op_read8_state, dual_op_read16_state, dual_op_read16_2_state,
dual_op_write8_state, dual_op_write16_state,
--
sync_state, halt_state, cwai_state,
--
andcc_state, orcc_state,
tfr_state,
exg_state, exg1_state, exg2_state,
lea_state,
-- Multiplication
mul_state, mulea_state, muld_state,
mul0_state, mul1_state, mul2_state, mul3_state,
mul4_state, mul5_state, mul6_state, mul7_state,
-- Branches
lbranch_state, sbranch_state,
-- Jumps, Subroutine Calls and Returns
jsr_state, jmp_state,
push_return_hi_state, push_return_lo_state,
pull_return_hi_state, pull_return_lo_state,
-- Interrupt cycles
int_nmi_state, int_nmi1_state,
int_irq_state, int_irq1_state,
int_firq_state, int_firq1_state,
int_entire_state, int_fast_state,
int_pcl_state, int_pch_state,
int_upl_state, int_uph_state,
int_iyl_state, int_iyh_state,
int_ixl_state, int_ixh_state,
int_dp_state,
int_accb_state, int_acca_state,
int_cc_state,
int_cwai_state,
int_nmimask_state, int_firqmask_state, int_swimask_state, int_irqmask_state,
-- Return From Interrupt
rti_cc_state, rti_entire_state,
rti_acca_state, rti_accb_state,
rti_dp_state,
rti_ixl_state, rti_ixh_state,
rti_iyl_state, rti_iyh_state,
rti_upl_state, rti_uph_state,
rti_pcl_state, rti_pch_state,
-- Push Registers using SP
pshs_state,
pshs_pcl_state, pshs_pch_state,
pshs_upl_state, pshs_uph_state,
pshs_iyl_state, pshs_iyh_state,
pshs_ixl_state, pshs_ixh_state,
pshs_dp_state,
pshs_acca_state, pshs_accb_state,
pshs_cc_state,
-- Pull Registers using SP
puls_state,
puls_cc_state,
puls_acca_state, puls_accb_state,
puls_dp_state,
puls_ixl_state, puls_ixh_state,
puls_iyl_state, puls_iyh_state,
puls_upl_state, puls_uph_state,
puls_pcl_state, puls_pch_state,
-- Push Registers using UP
pshu_state,
pshu_pcl_state, pshu_pch_state,
pshu_spl_state, pshu_sph_state,
pshu_iyl_state, pshu_iyh_state,
pshu_ixl_state, pshu_ixh_state,
pshu_dp_state,
pshu_acca_state, pshu_accb_state,
pshu_cc_state,
-- Pull Registers using UP
pulu_state,
pulu_cc_state,
pulu_acca_state, pulu_accb_state,
pulu_dp_state,
pulu_ixl_state, pulu_ixh_state,
pulu_iyl_state, pulu_iyh_state,
pulu_spl_state, pulu_sph_state,
pulu_pcl_state, pulu_pch_state );
type st_type is (reset_st, push_st, idle_st );
type iv_type is (latch_iv, swi3_iv, swi2_iv, firq_iv, irq_iv, swi_iv, nmi_iv, reset_iv);
type addr_type is (idle_ad, fetch_ad, read_ad, write_ad, pushu_ad, pullu_ad, pushs_ad, pulls_ad, int_hi_ad, int_lo_ad );
type dout_type is (cc_dout, acca_dout, accb_dout, dp_dout,
ix_lo_dout, ix_hi_dout, iy_lo_dout, iy_hi_dout,
up_lo_dout, up_hi_dout, sp_lo_dout, sp_hi_dout,
pc_lo_dout, pc_hi_dout, md_lo_dout, md_hi_dout );
type op_type is (reset_op, fetch_op, latch_op );
type pre_type is (reset_pre, fetch_pre, latch_pre );
type cc_type is (reset_cc, load_cc, pull_cc, latch_cc );
type acca_type is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca );
type accb_type is (reset_accb, load_accb, pull_accb, latch_accb );
type dp_type is (reset_dp, load_dp, pull_dp, latch_dp );
type ix_type is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix );
type iy_type is (reset_iy, load_iy, pull_lo_iy, pull_hi_iy, latch_iy );
type sp_type is (reset_sp, latch_sp, load_sp, pull_hi_sp, pull_lo_sp );
type up_type is (reset_up, latch_up, load_up, pull_hi_up, pull_lo_up );
type pc_type is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc, incr_pc );
type md_type is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md );
type ea_type is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea );
type left_type is (cc_left, acca_left, accb_left, dp_left,
ix_left, iy_left, up_left, sp_left,
accd_left, md_left, pc_left, ea_left );
type right_type is (ea_right, zero_right, one_right, two_right,
acca_right, accb_right, accd_right,
md_right, md_sign5_right, md_sign8_right );
type alu_type is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc,
alu_and, alu_ora, alu_eor,
alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com,
alu_lsr16, alu_lsl16,
alu_ror8, alu_rol8, alu_mul,
alu_asr8, alu_asl8, alu_lsr8,
alu_andcc, alu_orcc, alu_sex, alu_tfr, alu_abx,
alu_seif, alu_sei, alu_see, alu_cle,
alu_ld8, alu_st8, alu_ld16, alu_st16, alu_lea, alu_nop, alu_daa );
signal op_code: std_logic_vector(7 downto 0);
signal pre_code: std_logic_vector(7 downto 0);
signal acca: std_logic_vector(7 downto 0);
signal accb: std_logic_vector(7 downto 0);
signal cc: std_logic_vector(7 downto 0);
signal cc_out: std_logic_vector(7 downto 0);
signal dp: std_logic_vector(7 downto 0);
signal xreg: std_logic_vector(15 downto 0);
signal yreg: std_logic_vector(15 downto 0);
signal sp: std_logic_vector(15 downto 0);
signal up: std_logic_vector(15 downto 0);
signal ea: std_logic_vector(15 downto 0);
signal pc: std_logic_vector(15 downto 0);
signal md: std_logic_vector(15 downto 0);
signal left: std_logic_vector(15 downto 0);
signal right: std_logic_vector(15 downto 0);
signal out_alu: std_logic_vector(15 downto 0);
signal iv: std_logic_vector(2 downto 0);
signal nmi_req: std_logic;
signal nmi_ack: std_logic;
signal nmi_enable: std_logic;
signal fic: std_logic; -- first instruction cycle
signal lic: std_logic; -- last instruction cycle
signal state: state_type;
signal next_state: state_type;
signal return_state: state_type;
signal saved_state: state_type;
signal st_ctrl: st_type;
signal iv_ctrl: iv_type;
signal pc_ctrl: pc_type;
signal ea_ctrl: ea_type;
signal op_ctrl: op_type;
signal pre_ctrl: pre_type;
signal md_ctrl: md_type;
signal acca_ctrl: acca_type;
signal accb_ctrl: accb_type;
signal ix_ctrl: ix_type;
signal iy_ctrl: iy_type;
signal cc_ctrl: cc_type;
signal dp_ctrl: dp_type;
signal sp_ctrl: sp_type;
signal up_ctrl: up_type;
signal left_ctrl: left_type;
signal right_ctrl: right_type;
signal alu_ctrl: alu_type;
signal addr_ctrl: addr_type;
signal dout_ctrl: dout_type;
begin
Regs <= cc & dp & pc & sp & up & yreg & xreg & accb & acca;
----------------------------------
--
-- State machine stack
--
----------------------------------
--state_stack_proc: process( clk, hold, state_stack, st_ctrl,
-- return_state, fetch_state )
state_stack_proc: process( clk, st_ctrl, return_state )
begin
if clk'event and clk = '1' then
if hold = '0' then
case st_ctrl is
when reset_st =>
saved_state <= fetch_state;
when push_st =>
saved_state <= return_state;
when others =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- Interrupt Vector control
--
----------------------------------
--
int_vec_proc: process( clk, iv_ctrl )
begin
if clk'event and clk = '1' then
if hold = '0' then
case iv_ctrl is
when reset_iv =>
iv <= RST_VEC;
when nmi_iv =>
iv <= NMI_VEC;
when swi_iv =>
iv <= SWI_VEC;
when irq_iv =>
iv <= IRQ_VEC;
when firq_iv =>
iv <= FIRQ_VEC;
when swi2_iv =>
iv <= SWI2_VEC;
when swi3_iv =>
iv <= SWI3_VEC;
when others =>
null;
end case;
end if; -- hold
end if; -- clk
end process;
----------------------------------
--
-- Program Counter Control
--
----------------------------------
--pc_reg: process( clk, pc_ctrl, hold, pc, out_alu, data_in )
pc_reg: process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case pc_ctrl is
when reset_pc =>
pc <= (others=>'0');
when load_pc =>
pc <= out_alu(15 downto 0);
when pull_lo_pc =>
pc(7 downto 0) <= data_in;
when pull_hi_pc =>
pc(15 downto 8) <= data_in;
when incr_pc =>
pc <= pc + 1;
when others =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- Effective Address Control
--
----------------------------------
--ea_reg: process( clk, ea_ctrl, hold, ea, out_alu, data_in, dp )
ea_reg: process( clk )
begin
if clk'event and clk = '1' then
if hold= '0' then
case ea_ctrl is
when reset_ea =>
ea <= (others=>'0');
when fetch_first_ea =>
ea(7 downto 0) <= data_in;
ea(15 downto 8) <= dp;
when fetch_next_ea =>
ea(15 downto 8) <= ea(7 downto 0);
ea(7 downto 0) <= data_in;
when load_ea =>
ea <= out_alu(15 downto 0);
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- Accumulator A
--
--------------------------------
--acca_reg : process( clk, acca_ctrl, hold, out_alu, acca, data_in )
acca_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case acca_ctrl is
when reset_acca =>
acca <= (others=>'0');
when load_acca =>
acca <= out_alu(7 downto 0);
when load_hi_acca =>
acca <= out_alu(15 downto 8);
when pull_acca =>
acca <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- Accumulator B
--
--------------------------------
--accb_reg : process( clk, accb_ctrl, hold, out_alu, accb, data_in )
accb_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case accb_ctrl is
when reset_accb =>
accb <= (others=>'0');
when load_accb =>
accb <= out_alu(7 downto 0);
when pull_accb =>
accb <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- X Index register
--
--------------------------------
--ix_reg : process( clk, ix_ctrl, hold, out_alu, xreg, data_in )
ix_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case ix_ctrl is
when reset_ix =>
xreg <= (others=>'0');
when load_ix =>
xreg <= out_alu(15 downto 0);
when pull_hi_ix =>
xreg(15 downto 8) <= data_in;
when pull_lo_ix =>
xreg(7 downto 0) <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- Y Index register
--
--------------------------------
--iy_reg : process( clk, iy_ctrl, hold, out_alu, yreg, data_in )
iy_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case iy_ctrl is
when reset_iy =>
yreg <= (others=>'0');
when load_iy =>
yreg <= out_alu(15 downto 0);
when pull_hi_iy =>
yreg(15 downto 8) <= data_in;
when pull_lo_iy =>
yreg(7 downto 0) <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- S stack pointer
--
--------------------------------
--sp_reg : process( clk, sp_ctrl, hold, sp, out_alu, data_in, nmi_enable )
sp_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case sp_ctrl is
when reset_sp =>
sp <= (others=>'0');
nmi_enable <= '0';
when load_sp =>
sp <= out_alu(15 downto 0);
nmi_enable <= '1';
when pull_hi_sp =>
sp(15 downto 8) <= data_in;
when pull_lo_sp =>
sp(7 downto 0) <= data_in;
nmi_enable <= '1';
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- U stack pointer
--
--------------------------------
--up_reg : process( clk, up_ctrl, hold, up, out_alu, data_in )
up_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case up_ctrl is
when reset_up =>
up <= (others=>'0');
when load_up =>
up <= out_alu(15 downto 0);
when pull_hi_up =>
up(15 downto 8) <= data_in;
when pull_lo_up =>
up(7 downto 0) <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- Memory Data
--
--------------------------------
--md_reg : process( clk, md_ctrl, hold, out_alu, data_in, md )
md_reg : process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case md_ctrl is
when reset_md =>
md <= (others=>'0');
when load_md =>
md <= out_alu(15 downto 0);
when fetch_first_md => -- sign extend md for branches
md(15 downto 8) <= data_in(7) & data_in(7) & data_in(7) & data_in(7) &
data_in(7) & data_in(7) & data_in(7) & data_in(7) ;
md(7 downto 0) <= data_in;
when fetch_next_md =>
md(15 downto 8) <= md(7 downto 0);
md(7 downto 0) <= data_in;
when shiftl_md =>
md(15 downto 1) <= md(14 downto 0);
md(0) <= '0';
when others =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- Condition Codes
--
----------------------------------
--cc_reg: process( clk, cc_ctrl, hold, cc_out, cc, data_in )
cc_reg: process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case cc_ctrl is
when reset_cc =>
cc <= "11010000"; -- set EBIT, FBIT & IBIT
when load_cc =>
cc <= cc_out;
when pull_cc =>
cc <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- Direct Page register
--
----------------------------------
--dp_reg: process( clk, dp_ctrl, hold, out_alu, dp, data_in )
dp_reg: process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case dp_ctrl is
when reset_dp =>
dp <= (others=>'0');
when load_dp =>
dp <= out_alu(7 downto 0);
when pull_dp =>
dp <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- op code register
--
----------------------------------
--op_reg: process( clk, op_ctrl, hold, op_code, data_in )
op_reg: process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case op_ctrl is
when reset_op =>
op_code <= "00010010";
when fetch_op =>
op_code <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
----------------------------------
--
-- pre byte op code register
--
----------------------------------
--pre_reg: process( clk, pre_ctrl, hold, pre_code, data_in )
pre_reg: process( clk )
begin
if clk'event and clk = '1' then
if hold = '0' then
case pre_ctrl is
when reset_pre =>
pre_code <= (others=>'0');
when fetch_pre =>
pre_code <= data_in;
when others =>
null;
end case;
end if;
end if;
end process;
--------------------------------
--
-- state machine
--
--------------------------------
--change_state: process( clk, rst, state, hold, next_state )
change_state: process( clk )
begin
if clk'event and clk = '1' then
if rst = '1' then
fic <= '0';
nmi_ack <= '0';
state <= reset_state;
elsif hold = '0' then
fic <= lic;
--
-- nmi request is not cleared until nmi input goes low
--
if (nmi_req = '0') and (nmi_ack='1') then
nmi_ack <= '0';
end if;
if (nmi_req = '1') and (nmi_ack = '0') and (state = int_nmimask_state) then
nmi_ack <= '1';
end if;
if lic = '1' then
if halt = '1' then
state <= halt_state;
-- service non maskable interrupts
elsif (nmi_req = '1') and (nmi_ack = '0') then
state <= int_nmi_state;
--
-- FIRQ & IRQ are level sensitive
--
elsif (firq = '1') then
if (cc(FBIT) = '0') then
state <= int_firq_state;
else
state <= fetch_state;
end if;
elsif (irq = '1') then
if (cc(IBIT) = '0') then
state <= int_irq_state;
else
state <= fetch_state;
end if;
else
state <= next_state;
end if; -- halt, nmi, firq, irq
else
state <= next_state;
end if; -- lic
end if; -- reset/hold
end if; -- clk
end process;
------------------------------------
--
-- Detect Edge of NMI interrupt
--
------------------------------------
--nmi_handler : process( clk, rst, nmi, nmi_ack, nmi_req, nmi_enable )
nmi_handler : process( rst, clk )
begin
if rst='1' then
nmi_req <= '0';
elsif clk'event and clk='0' then
if (nmi='1') and (nmi_ack='0') and (nmi_enable='1') then
nmi_req <= '1';
else
if (nmi='0') and (nmi_ack='1') then
nmi_req <= '0';
end if;
end if;
end if;
end process;
----------------------------------
--
-- Address output multiplexer
--
----------------------------------
addr_mux: process( addr_ctrl, pc, ea, up, sp, iv )
begin
ifetch <= '0';
vma <= '1';
case addr_ctrl is
when fetch_ad =>
addr <= pc;
rw <= '1';
ifetch <= '1';
when read_ad =>
addr <= ea;
rw <= '1';
when write_ad =>
addr <= ea;
rw <= '0';
when pushs_ad =>
addr <= sp;
rw <= '0';
when pulls_ad =>
addr <= sp;
rw <= '1';
when pushu_ad =>
addr <= up;
rw <= '0';
when pullu_ad =>
addr <= up;
rw <= '1';
when int_hi_ad =>
addr <= "111111111111" & iv & "0";
rw <= '1';
when int_lo_ad =>
addr <= "111111111111" & iv & "1";
rw <= '1';
when others =>
addr <= "1111111111111111";
rw <= '1';
vma <= '0';
end case;
end process;
--------------------------------
--
-- Data Bus output
--
--------------------------------
dout_mux : process( dout_ctrl, md, acca, accb, dp, xreg, yreg, sp, up, pc, cc )
begin
case dout_ctrl is
when cc_dout => -- condition code register
data_out <= cc;
when acca_dout => -- accumulator a
data_out <= acca;
when accb_dout => -- accumulator b
data_out <= accb;
when dp_dout => -- direct page register
data_out <= dp;
when ix_lo_dout => -- X index reg
data_out <= xreg(7 downto 0);
when ix_hi_dout => -- X index reg
data_out <= xreg(15 downto 8);
when iy_lo_dout => -- Y index reg
data_out <= yreg(7 downto 0);
when iy_hi_dout => -- Y index reg
data_out <= yreg(15 downto 8);
when up_lo_dout => -- U stack pointer
data_out <= up(7 downto 0);
when up_hi_dout => -- U stack pointer
data_out <= up(15 downto 8);
when sp_lo_dout => -- S stack pointer
data_out <= sp(7 downto 0);
when sp_hi_dout => -- S stack pointer
data_out <= sp(15 downto 8);
when md_lo_dout => -- alu output
data_out <= md(7 downto 0);
when md_hi_dout => -- alu output
data_out <= md(15 downto 8);
when pc_lo_dout => -- low order pc
data_out <= pc(7 downto 0);
when pc_hi_dout => -- high order pc
data_out <= pc(15 downto 8);
end case;
end process;
----------------------------------
--
-- Left Mux
--
----------------------------------
left_mux: process( left_ctrl, acca, accb, cc, dp, xreg, yreg, up, sp, pc, ea, md )
begin
case left_ctrl is
when cc_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= cc;
when acca_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= acca;
when accb_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= accb;
when dp_left =>
left(15 downto 8) <= "00000000";
left(7 downto 0) <= dp;
when accd_left =>
left(15 downto 8) <= acca;
left(7 downto 0) <= accb;
when md_left =>
left <= md;
when ix_left =>
left <= xreg;
when iy_left =>
left <= yreg;
when sp_left =>
left <= sp;
when up_left =>
left <= up;
when pc_left =>
left <= pc;
when others =>
-- when ea_left =>
left <= ea;
end case;
end process;
----------------------------------
--
-- Right Mux
--
----------------------------------
right_mux: process( right_ctrl, md, acca, accb, ea )
begin
case right_ctrl is
when ea_right =>
right <= ea;
when zero_right =>
right <= "0000000000000000";
when one_right =>
right <= "0000000000000001";
when two_right =>
right <= "0000000000000010";
when acca_right =>
if acca(7) = '0' then
right <= "00000000" & acca(7 downto 0);
else
right <= "11111111" & acca(7 downto 0);
end if;
when accb_right =>
if accb(7) = '0' then
right <= "00000000" & accb(7 downto 0);
else
right <= "11111111" & accb(7 downto 0);
end if;
when accd_right =>
right <= acca & accb;
when md_sign5_right =>
if md(4) = '0' then
right <= "00000000000" & md(4 downto 0);
else
right <= "11111111111" & md(4 downto 0);
end if;
when md_sign8_right =>
if md(7) = '0' then
right <= "00000000" & md(7 downto 0);
else
right <= "11111111" & md(7 downto 0);
end if;
when others =>
-- when md_right =>
right <= md;
end case;
end process;
----------------------------------
--
-- Arithmetic Logic Unit
--
----------------------------------
alu: process( alu_ctrl, cc, left, right, out_alu, cc_out )
variable valid_lo, valid_hi : boolean;
variable carry_in : std_logic;
variable daa_reg : std_logic_vector(7 downto 0);
begin
case alu_ctrl is
when alu_adc | alu_sbc |
alu_rol8 | alu_ror8 =>
carry_in := cc(CBIT);
when alu_asr8 =>
carry_in := left(7);
when others =>
carry_in := '0';
end case;
valid_lo := left(3 downto 0) <= 9;
valid_hi := left(7 downto 4) <= 9;
--
-- CBIT HBIT VHI VLO DAA
-- 0 0 0 0 66 (!VHI : hi_nybble>8)
-- 0 0 0 1 60
-- 0 0 1 1 00
-- 0 0 1 0 06 ( VHI : hi_nybble<=8)
--
-- 0 1 1 0 06
-- 0 1 1 1 06
-- 0 1 0 1 66
-- 0 1 0 0 66
--
-- 1 1 0 0 66
-- 1 1 0 1 66
-- 1 1 1 1 66
-- 1 1 1 0 66
--
-- 1 0 1 0 66
-- 1 0 1 1 60
-- 1 0 0 1 60
-- 1 0 0 0 66
--
-- 66 = (!VHI & !VLO) + (CBIT & HBIT) + (HBIT & !VHI) + (CBIT & !VLO)
-- = (CBIT & (HBIT + !VLO)) + (!VHI & (HBIT + !VLO))
-- = (!VLO & (CBIT + !VHI)) + (HBIT & (CBIT + !VHI))
-- 60 = (CBIT & !HBIT & VLO) + (!HBIT & !VHI & VLO)
-- = (!HBIT & VLO & (CBIT + !VHI))
-- 06 = (!CBIT & VHI & (!VLO + VHI)
-- 00 = (!CBIT & !HBIT & VHI & VLO)
--
if (cc(CBIT) = '0') then
-- CBIT=0
if( cc(HBIT) = '0' ) then
-- HBIT=0
if valid_lo then
-- lo <= 9 (no overflow in low nybble)
if valid_hi then
-- hi <= 9 (no overflow in either low or high nybble)
daa_reg := "00000000";
else
-- hi > 9 (overflow in high nybble only)
daa_reg := "01100000";
end if;
else
-- lo > 9 (overflow in low nybble)
--
-- since there is already an overflow in the low nybble
-- you need to make room in the high nybble for the low nybble carry
-- so compare the high nybble with 8 rather than 9
-- if the high nybble is 9 there will be an overflow on the high nybble
-- after the decimal adjust which means it will roll over to an invalid BCD digit
--
if( left(7 downto 4) <= 8 ) then
-- hi <= 8 (overflow in low nybble only)
daa_reg := "00000110";
else
-- hi > 8 (overflow in low and high nybble)
daa_reg := "01100110";
end if;
end if;
else
-- HBIT=1 (overflow in low nybble)
if valid_hi then
-- hi <= 9 (overflow in low nybble only)
daa_reg := "00000110";
else
-- hi > 9 (overflow in low and high nybble)
daa_reg := "01100110";
end if;
end if;
else
-- CBIT=1 (carry => overflow in high nybble)
if ( cc(HBIT) = '0' )then
-- HBIT=0 (half carry clear => may or may not be an overflow in the low nybble)
if valid_lo then
-- lo <=9 (overflow in high nybble only)
daa_reg := "01100000";
else
-- lo >9 (overflow in low and high nybble)
daa_reg := "01100110";
end if;
else
-- HBIT=1 (overflow in low and high nybble)
daa_reg := "01100110";
end if;
end if;
case alu_ctrl is
when alu_add8 | alu_inc |
alu_add16 | alu_adc | alu_mul =>
out_alu <= left + right + ("000000000000000" & carry_in);
when alu_sub8 | alu_dec |
alu_sub16 | alu_sbc =>
out_alu <= left - right - ("000000000000000" & carry_in);
when alu_abx =>
out_alu <= left + ("00000000" & right(7 downto 0)) ;
when alu_and =>
out_alu <= left and right; -- and/bit
when alu_ora =>
out_alu <= left or right; -- or
when alu_eor =>
out_alu <= left xor right; -- eor/xor
when alu_lsl16 | alu_asl8 | alu_rol8 =>
out_alu <= left(14 downto 0) & carry_in; -- rol8/asl8/lsl16
when alu_lsr16 =>
out_alu <= carry_in & left(15 downto 1); -- lsr16
when alu_lsr8 | alu_asr8 | alu_ror8 =>
out_alu <= "00000000" & carry_in & left(7 downto 1); -- ror8/asr8/lsr8
when alu_neg =>
out_alu <= right - left; -- neg (right=0)
when alu_com =>
out_alu <= not left;
when alu_clr | alu_ld8 | alu_ld16 | alu_lea =>
out_alu <= right; -- clr, ld
when alu_st8 | alu_st16 | alu_andcc | alu_orcc | alu_tfr =>
out_alu <= left;
when alu_daa =>
out_alu <= left + ("00000000" & daa_reg);
when alu_sex =>
if left(7) = '0' then
out_alu <= "00000000" & left(7 downto 0);
else
out_alu <= "11111111" & left(7 downto 0);
end if;
when others =>
out_alu <= left; -- nop
end case;
--
-- carry bit
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(CBIT) <= (left(7) and right(7)) or
(left(7) and not out_alu(7)) or
(right(7) and not out_alu(7));
when alu_sub8 | alu_sbc =>
cc_out(CBIT) <= ((not left(7)) and right(7)) or
((not left(7)) and out_alu(7)) or
(right(7) and out_alu(7));
when alu_add16 =>
cc_out(CBIT) <= (left(15) and right(15)) or
(left(15) and not out_alu(15)) or
(right(15) and not out_alu(15));
when alu_sub16 =>
cc_out(CBIT) <= ((not left(15)) and right(15)) or
((not left(15)) and out_alu(15)) or
(right(15) and out_alu(15));
when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 =>
cc_out(CBIT) <= left(0);
when alu_rol8 | alu_asl8 =>
cc_out(CBIT) <= left(7);
when alu_lsl16 =>
cc_out(CBIT) <= left(15);
when alu_com =>
cc_out(CBIT) <= '1';
when alu_neg | alu_clr =>
cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0);
when alu_mul =>
cc_out(CBIT) <= out_alu(7);
when alu_daa =>
if ( daa_reg(7 downto 4) = "0110" ) then
cc_out(CBIT) <= '1';
else
cc_out(CBIT) <= '0';
end if;
when alu_andcc =>
cc_out(CBIT) <= left(CBIT) and cc(CBIT);
when alu_orcc =>
cc_out(CBIT) <= left(CBIT) or cc(CBIT);
when alu_tfr =>
cc_out(CBIT) <= left(CBIT);
when others =>
cc_out(CBIT) <= cc(CBIT);
end case;
--
-- Zero flag
--
case alu_ctrl is
when alu_add8 | alu_sub8 |
alu_adc | alu_sbc |
alu_and | alu_ora | alu_eor |
alu_inc | alu_dec |
alu_neg | alu_com | alu_clr |
alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
alu_ld8 | alu_st8 | alu_sex | alu_daa =>
cc_out(ZBIT) <= not( out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) );
when alu_add16 | alu_sub16 | alu_mul |
alu_lsl16 | alu_lsr16 |
alu_ld16 | alu_st16 | alu_lea =>
cc_out(ZBIT) <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or
out_alu(11) or out_alu(10) or out_alu(9) or out_alu(8) or
out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0) );
when alu_andcc =>
cc_out(ZBIT) <= left(ZBIT) and cc(ZBIT);
when alu_orcc =>
cc_out(ZBIT) <= left(ZBIT) or cc(ZBIT);
when alu_tfr =>
cc_out(ZBIT) <= left(ZBIT);
when others =>
cc_out(ZBIT) <= cc(ZBIT);
end case;
--
-- negative flag
--
case alu_ctrl is
when alu_add8 | alu_sub8 |
alu_adc | alu_sbc |
alu_and | alu_ora | alu_eor |
alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
alu_inc | alu_dec | alu_neg | alu_com | alu_clr |
alu_ld8 | alu_st8 | alu_sex | alu_daa =>
cc_out(NBIT) <= out_alu(7);
when alu_add16 | alu_sub16 |
alu_lsl16 | alu_lsr16 |
alu_ld16 | alu_st16 =>
cc_out(NBIT) <= out_alu(15);
when alu_andcc =>
cc_out(NBIT) <= left(NBIT) and cc(NBIT);
when alu_orcc =>
cc_out(NBIT) <= left(NBIT) or cc(NBIT);
when alu_tfr =>
cc_out(NBIT) <= left(NBIT);
when others =>
cc_out(NBIT) <= cc(NBIT);
end case;
--
-- Interrupt mask flag
--
case alu_ctrl is
when alu_andcc =>
cc_out(IBIT) <= left(IBIT) and cc(IBIT);
when alu_orcc =>
cc_out(IBIT) <= left(IBIT) or cc(IBIT);
when alu_tfr =>
cc_out(IBIT) <= left(IBIT);
when alu_seif | alu_sei =>
cc_out(IBIT) <= '1';
when others =>
cc_out(IBIT) <= cc(IBIT); -- interrupt mask
end case;
--
-- Half Carry flag
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(HBIT) <= (left(3) and right(3)) or
(right(3) and not out_alu(3)) or
(left(3) and not out_alu(3));
when alu_andcc =>
cc_out(HBIT) <= left(HBIT) and cc(HBIT);
when alu_orcc =>
cc_out(HBIT) <= left(HBIT) or cc(HBIT);
when alu_tfr =>
cc_out(HBIT) <= left(HBIT);
when others =>
cc_out(HBIT) <= cc(HBIT);
end case;
--
-- Overflow flag
--
case alu_ctrl is
when alu_add8 | alu_adc =>
cc_out(VBIT) <= (left(7) and right(7) and (not out_alu(7))) or
((not left(7)) and (not right(7)) and out_alu(7));
when alu_sub8 | alu_sbc =>
cc_out(VBIT) <= (left(7) and (not right(7)) and (not out_alu(7))) or
((not left(7)) and right(7) and out_alu(7));
when alu_add16 =>
cc_out(VBIT) <= (left(15) and right(15) and (not out_alu(15))) or
((not left(15)) and (not right(15)) and out_alu(15));
when alu_sub16 =>
cc_out(VBIT) <= (left(15) and (not right(15)) and (not out_alu(15))) or
((not left(15)) and right(15) and out_alu(15));
when alu_inc =>
cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and
left(3) and left(2) and left(1) and left(0));
when alu_dec | alu_neg =>
cc_out(VBIT) <= (left(7) and (not left(6)) and (not left(5)) and (not left(4)) and
(not left(3)) and (not left(2)) and (not left(1)) and (not left(0)));
-- 6809 Programming reference manual says
-- V not affected by ASR, LSR and ROR
-- This is different to the 6800
-- John Kent 6th June 2006
-- when alu_asr8 =>
-- cc_out(VBIT) <= left(0) xor left(7);
-- when alu_lsr8 | alu_lsr16 =>
-- cc_out(VBIT) <= left(0);
-- when alu_ror8 =>
-- cc_out(VBIT) <= left(0) xor cc(CBIT);
when alu_lsl16 =>
cc_out(VBIT) <= left(15) xor left(14);
when alu_rol8 | alu_asl8 =>
cc_out(VBIT) <= left(7) xor left(6);
--
-- 11th July 2006 - John Kent
-- What DAA does with V is anyones guess
-- It is undefined in the 6809 programming manual
--
when alu_daa =>
cc_out(VBIT) <= left(7) xor out_alu(7) xor cc(CBIT);
-- CLR resets V Bit
-- John Kent 6th June 2006
when alu_and | alu_ora | alu_eor | alu_com | alu_clr |
alu_st8 | alu_st16 | alu_ld8 | alu_ld16 | alu_sex =>
cc_out(VBIT) <= '0';
when alu_andcc =>
cc_out(VBIT) <= left(VBIT) and cc(VBIT);
when alu_orcc =>
cc_out(VBIT) <= left(VBIT) or cc(VBIT);
when alu_tfr =>
cc_out(VBIT) <= left(VBIT);
when others =>
cc_out(VBIT) <= cc(VBIT);
end case;
case alu_ctrl is
when alu_andcc =>
cc_out(FBIT) <= left(FBIT) and cc(FBIT);
when alu_orcc =>
cc_out(FBIT) <= left(FBIT) or cc(FBIT);
when alu_tfr =>
cc_out(FBIT) <= left(FBIT);
when alu_seif =>
cc_out(FBIT) <= '1';
when others =>
cc_out(FBIT) <= cc(FBIT);
end case;
case alu_ctrl is
when alu_andcc =>
cc_out(EBIT) <= left(EBIT) and cc(EBIT);
when alu_orcc =>
cc_out(EBIT) <= left(EBIT) or cc(EBIT);
when alu_tfr =>
cc_out(EBIT) <= left(EBIT);
when alu_see =>
cc_out(EBIT) <= '1';
when alu_cle =>
cc_out(EBIT) <= '0';
when others =>
cc_out(EBIT) <= cc(EBIT);
end case;
end process;
------------------------------------
--
-- state sequencer
--
------------------------------------
process( state, saved_state,
op_code, pre_code,
cc, ea, md, iv, fic, halt,
nmi_req, firq, irq, lic )
variable cond_true : boolean; -- variable used to evaluate coditional branches
begin
cond_true := (1=1);
ba <= '0';
bs <= '0';
lic <= '0';
opfetch <= '0';
iv_ctrl <= latch_iv;
-- Registers preserved
cc_ctrl <= latch_cc;
acca_ctrl <= latch_acca;
accb_ctrl <= latch_accb;
dp_ctrl <= latch_dp;
ix_ctrl <= latch_ix;
iy_ctrl <= latch_iy;
up_ctrl <= latch_up;
sp_ctrl <= latch_sp;
pc_ctrl <= latch_pc;
md_ctrl <= latch_md;
ea_ctrl <= latch_ea;
op_ctrl <= latch_op;
pre_ctrl <= latch_pre;
-- ALU Idle
left_ctrl <= pc_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
-- Bus idle
addr_ctrl <= idle_ad;
dout_ctrl <= cc_dout;
-- Next State Fetch
st_ctrl <= idle_st;
return_state <= fetch_state;
next_state <= fetch_state;
case state is
when reset_state => -- released from reset
-- reset the registers
iv_ctrl <= reset_iv;
op_ctrl <= reset_op;
pre_ctrl <= reset_pre;
cc_ctrl <= reset_cc;
acca_ctrl <= reset_acca;
accb_ctrl <= reset_accb;
dp_ctrl <= reset_dp;
ix_ctrl <= reset_ix;
iy_ctrl <= reset_iy;
up_ctrl <= reset_up;
sp_ctrl <= reset_sp;
pc_ctrl <= reset_pc;
ea_ctrl <= reset_ea;
md_ctrl <= reset_md;
st_ctrl <= reset_st;
next_state <= vect_hi_state;
--
-- Jump via interrupt vector
-- iv holds interrupt type
-- fetch PC hi from vector location
--
when vect_hi_state =>
-- fetch pc low interrupt vector
pc_ctrl <= pull_hi_pc;
addr_ctrl <= int_hi_ad;
bs <= '1';
next_state <= vect_lo_state;
--
-- jump via interrupt vector
-- iv holds vector type
-- fetch PC lo from vector location
--
when vect_lo_state =>
-- fetch the vector low byte
pc_ctrl <= pull_lo_pc;
addr_ctrl <= int_lo_ad;
bs <= '1';
next_state <= fetch_state;
when vect_idle_state =>
--
-- Last Instruction Cycle for SWI, SWI2 & SWI3
--
if op_code = "00111111" then
lic <= '1';
end if;
next_state <= fetch_state;
--
-- Here to fetch an instruction
-- PC points to opcode
--
when fetch_state =>
-- fetch the op code
opfetch <= '1';
op_ctrl <= fetch_op;
pre_ctrl <= fetch_pre;
ea_ctrl <= reset_ea;
-- Fetch op code
addr_ctrl <= fetch_ad;
-- Advance the PC to fetch next instruction byte
pc_ctrl <= incr_pc;
next_state <= decode1_state;
--
-- Here to decode instruction
-- and fetch next byte of intruction
-- whether it be necessary or not
--
when decode1_state =>
-- fetch first byte of address or immediate data
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
case op_code(7 downto 4) is
--
-- direct single op (2 bytes)
-- 6809 => 6 cycles
-- cpu09 => 5 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
-- 3 md_lo=(ea) / pc=pc
-- 4 alu_left=md / md=alu_out / pc=pc
-- 5 (ea)=md_lo / pc=pc
--
-- Exception is JMP
-- 6809 => 3 cycles
-- cpu09 => 3 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
-- 3 pc=ea
--
when "0000" =>
-- advance the PC
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "1110" => -- jmp
next_state <= jmp_state;
when "1111" => -- clr
next_state <= single_op_exec_state;
when others =>
next_state <= single_op_read_state;
end case;
-- acca / accb inherent instructions
when "0001" =>
case op_code(3 downto 0) is
--
-- Page2 pre byte
-- pre=(pc) / pc=pc+1
-- op=(pc) / pc=pc+1
--
when "0000" => -- page2
opfetch <= '1';
op_ctrl <= fetch_op;
-- advance pc
pc_ctrl <= incr_pc;
next_state <= decode2_state;
--
-- Page3 pre byte
-- pre=(pc) / pc=pc+1
-- op=(pc) / pc=pc+1
--
when "0001" => -- page3
opfetch <= '1';
op_ctrl <= fetch_op;
-- advance pc
pc_ctrl <= incr_pc;
next_state <= decode3_state;
--
-- nop - No operation ( 1 byte )
-- 6809 => 2 cycles
-- cpu09 => 2 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 decode
--
when "0010" => -- nop
lic <= '1';
next_state <= fetch_state;
--
-- sync - halt execution until an interrupt is received
-- interrupt may be NMI, IRQ or FIRQ
-- program execution continues if the
-- interrupt is asserted for 3 clock cycles
-- note that registers are not pushed onto the stack
-- CPU09 => Interrupts need only be asserted for one clock cycle
--
when "0011" => -- sync
next_state <= sync_state;
--
-- lbra -- long branch (3 bytes)
-- 6809 => 5 cycles
-- cpu09 => 4 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
-- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
-- 4 pc=pc+md
--
when "0110" =>
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= lbranch_state;
--
-- lbsr - long branch to subroutine (3 bytes)
-- 6809 => 9 cycles
-- cpu09 => 6 cycles
-- 1 op=(pc) /pc=pc+1
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / sp=sp-1
-- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
-- 4 (sp)= pc_lo / sp=sp-1 / pc=pc
-- 5 (sp)=pc_hi / pc=pc
-- 6 pc=pc+md
--
when "0111" =>
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= lbranch_state;
--
-- Decimal Adjust Accumulator
--
when "1001" => -- daa
left_ctrl <= acca_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_daa;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
lic <= '1';
next_state <= fetch_state;
--
-- OR Condition Codes
--
when "1010" => -- orcc
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= orcc_state;
--
-- AND Condition Codes
--
when "1100" => -- andcc
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= andcc_state;
--
-- Sign Extend
--
when "1101" => -- sex
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_sex;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
lic <= '1';
next_state <= fetch_state;
--
-- Exchange Registers
--
when "1110" => -- exg
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= exg_state;
--
-- Transfer Registers
--
when "1111" => -- tfr
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= tfr_state;
when others =>
-- increment the pc
pc_ctrl <= incr_pc;
lic <= '1';
next_state <= fetch_state;
end case;
--
-- Short branch conditional
-- 6809 => always 3 cycles
-- cpu09 => always = 3 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / test cc
-- 3 if cc tru pc=pc+md else pc=pc
--
when "0010" => -- branch conditional
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= sbranch_state;
--
-- Single byte stack operators
-- Do not advance PC
--
when "0011" =>
--
-- lea - load effective address (2+ bytes)
-- 6809 => 4 cycles + addressing mode
-- cpu09 => 4 cycles + addressing mode
-- 1 op=(pc) / pc=pc+1
-- 2 md_lo=(pc) / pc=pc+1
-- 3 calculate ea
-- 4 ix/iy/sp/up = ea
--
case op_code(3 downto 0) is
when "0000" | -- leax
"0001" | -- leay
"0010" | -- leas
"0011" => -- leau
-- advance PC
pc_ctrl <= incr_pc;
st_ctrl <= push_st;
return_state <= lea_state;
next_state <= indexed_state;
--
-- pshs - push registers onto sp stack
-- 6809 => 5 cycles + registers
-- cpu09 => 3 cycles + registers
-- 1 op=(pc) / pc=pc+1
-- 2 ea_lo=(pc) / pc=pc+1
-- 3 if ea(7 downto 0) != "00000000" then sp=sp-1
-- 4 if ea(7) = 1 (sp)=pcl, sp=sp-1
-- 5 if ea(7) = 1 (sp)=pch
-- if ea(6 downto 0) != "0000000" then sp=sp-1
-- 6 if ea(6) = 1 (sp)=upl, sp=sp-1
-- 7 if ea(6) = 1 (sp)=uph
-- if ea(5 downto 0) != "000000" then sp=sp-1
-- 8 if ea(5) = 1 (sp)=iyl, sp=sp-1
-- 9 if ea(5) = 1 (sp)=iyh
-- if ea(4 downto 0) != "00000" then sp=sp-1
-- 10 if ea(4) = 1 (sp)=ixl, sp=sp-1
-- 11 if ea(4) = 1 (sp)=ixh
-- if ea(3 downto 0) != "0000" then sp=sp-1
-- 12 if ea(3) = 1 (sp)=dp
-- if ea(2 downto 0) != "000" then sp=sp-1
-- 13 if ea(2) = 1 (sp)=accb
-- if ea(1 downto 0) != "00" then sp=sp-1
-- 14 if ea(1) = 1 (sp)=acca
-- if ea(0 downto 0) != "0" then sp=sp-1
-- 15 if ea(0) = 1 (sp)=cc
--
when "0100" => -- pshs
-- advance PC
pc_ctrl <= incr_pc;
next_state <= pshs_state;
--
-- puls - pull registers of sp stack
-- 6809 => 5 cycles + registers
-- cpu09 => 3 cycles + registers
--
when "0101" => -- puls
-- advance PC
pc_ctrl <= incr_pc;
next_state <= puls_state;
--
-- pshu - push registers onto up stack
-- 6809 => 5 cycles + registers
-- cpu09 => 3 cycles + registers
--
when "0110" => -- pshu
-- advance PC
pc_ctrl <= incr_pc;
next_state <= pshu_state;
--
-- pulu - pull registers of up stack
-- 6809 => 5 cycles + registers
-- cpu09 => 3 cycles + registers
--
when "0111" => -- pulu
-- advance PC
pc_ctrl <= incr_pc;
next_state <= pulu_state;
--
-- rts - return from subroutine
-- 6809 => 5 cycles
-- cpu09 => 4 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 decode op
-- 3 pc_hi = (sp) / sp=sp+1
-- 4 pc_lo = (sp) / sp=sp+1
--
when "1001" =>
next_state <= pull_return_hi_state;
--
-- ADD accb to index register
-- *** Note: this is an unsigned addition.
-- does not affect any condition codes
-- 6809 => 3 cycles
-- cpu09 => 2 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 alu_left=ix / alu_right=accb / ix=alu_out / pc=pc
--
when "1010" => -- abx
lic <= '1';
left_ctrl <= ix_left;
right_ctrl <= accb_right;
alu_ctrl <= alu_abx;
ix_ctrl <= load_ix;
next_state <= fetch_state;
--
-- Return From Interrupt
--
when "1011" => -- rti
next_state <= rti_cc_state;
--
-- CWAI
--
when "1100" => -- cwai #$<cc_mask>
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- increment pc
pc_ctrl <= incr_pc;
next_state <= cwai_state;
--
-- MUL Multiply
--
when "1101" => -- mul
next_state <= mul_state;
--
-- SWI Software Interrupt
--
when "1111" => -- swi
-- predecrement SP
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= swi_iv;
st_ctrl <= push_st;
return_state <= int_swimask_state;
next_state <= int_entire_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
--
-- Accumulator A Single operand
-- source = acca, dest = acca
-- Do not advance PC
-- Typically 2 cycles 1 bytes
-- 1 opcode fetch
-- 2 post byte fetch / instruction decode
-- Note that there is no post byte
-- so do not advance PC in decode cycle
-- Re-run opcode fetch cycle after decode
--
when "0100" => -- acca single op
left_ctrl <= acca_left;
case op_code(3 downto 0) is
when "0000" => -- neg
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0011" => -- com
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0100" => -- lsr
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0110" => -- ror
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "0111" => -- asr
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1000" => -- asl
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1001" => -- rol
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1010" => -- dec
right_ctrl <= one_right;
alu_ctrl <= alu_dec;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1011" => -- undefined
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
when "1100" => -- inc
right_ctrl <= one_right;
alu_ctrl <= alu_inc;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when "1101" => -- tst
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
acca_ctrl <= latch_acca;
cc_ctrl <= load_cc;
when "1110" => -- jmp (not defined)
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
acca_ctrl <= load_acca;
cc_ctrl <= load_cc;
when others =>
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
acca_ctrl <= latch_acca;
cc_ctrl <= latch_cc;
end case;
lic <= '1';
next_state <= fetch_state;
--
-- Single Operand accb
-- source = accb, dest = accb
-- Typically 2 cycles 1 bytes
-- 1 opcode fetch
-- 2 post byte fetch / instruction decode
-- Note that there is no post byte
-- so do not advance PC in decode cycle
-- Re-run opcode fetch cycle after decode
--
when "0101" =>
left_ctrl <= accb_left;
case op_code(3 downto 0) is
when "0000" => -- neg
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0011" => -- com
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0100" => -- lsr
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0110" => -- ror
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "0111" => -- asr
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1000" => -- asl
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1001" => -- rol
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1010" => -- dec
right_ctrl <= one_right;
alu_ctrl <= alu_dec;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1011" => -- undefined
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
when "1100" => -- inc
right_ctrl <= one_right;
alu_ctrl <= alu_inc;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when "1101" => -- tst
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
accb_ctrl <= latch_accb;
cc_ctrl <= load_cc;
when "1110" => -- jmp (undefined)
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
when "1111" => -- clr
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
accb_ctrl <= load_accb;
cc_ctrl <= load_cc;
when others =>
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
accb_ctrl <= latch_accb;
cc_ctrl <= latch_cc;
end case;
lic <= '1';
next_state <= fetch_state;
--
-- Single operand indexed
-- Two byte instruction so advance PC
-- EA should hold index offset
--
when "0110" => -- indexed single op
-- increment the pc
pc_ctrl <= incr_pc;
st_ctrl <= push_st;
case op_code(3 downto 0) is
when "1110" => -- jmp
return_state <= jmp_state;
when "1111" => -- clr
return_state <= single_op_exec_state;
when others =>
return_state <= single_op_read_state;
end case;
next_state <= indexed_state;
--
-- Single operand extended addressing
-- three byte instruction so advance the PC
-- Low order EA holds high order address
--
when "0111" => -- extended single op
-- increment PC
pc_ctrl <= incr_pc;
st_ctrl <= push_st;
case op_code(3 downto 0) is
when "1110" => -- jmp
return_state <= jmp_state;
when "1111" => -- clr
return_state <= single_op_exec_state;
when others =>
return_state <= single_op_read_state;
end case;
next_state <= extended_state;
when "1000" => -- acca immediate
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- subd #
"1100" | -- cmpx #
"1110" => -- ldx #
next_state <= imm16_state;
--
-- bsr offset - Branch to subroutine (2 bytes)
-- 6809 => 7 cycles
-- cpu09 => 5 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 md_hi=sign(pc) / md_lo=(pc) / sp=sp-1 / pc=pc+1
-- 3 (sp)=pc_lo / sp=sp-1
-- 4 (sp)=pc_hi
-- 5 pc=pc+md
--
when "1101" => -- bsr
-- pre decrement SP
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
--
st_ctrl <= push_st;
return_state <= sbranch_state;
next_state <= push_return_lo_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1001" => -- acca direct
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- subd
"1100" | -- cmpx
"1110" => -- ldx
next_state <= dual_op_read16_state;
when "0111" => -- sta direct
next_state <= dual_op_write8_state;
--
-- jsr direct - Jump to subroutine in direct page (2 bytes)
-- 6809 => 7 cycles
-- cpu09 => 5 cycles
-- 1 op=(pc) / pc=pc+1
-- 2 ea_hi=0 / ea_lo=(pc) / sp=sp-1 / pc=pc+1
-- 3 (sp)=pc_lo / sp=sp-1
-- 4 (sp)=pc_hi
-- 5 pc=ea
--
when "1101" => -- jsr direct
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
--
st_ctrl <= push_st;
return_state <= jmp_state;
next_state <= push_return_lo_state;
when "1111" => -- stx direct
-- idle ALU
left_ctrl <= ix_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_nop;
cc_ctrl <= latch_cc;
sp_ctrl <= latch_sp;
next_state <= dual_op_write16_state;
when others =>
next_state <= dual_op_read8_state;
end case;
when "1010" => -- acca indexed
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- subd
"1100" | -- cmpx
"1110" => -- ldx
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when "0111" => -- staa ,x
st_ctrl <= push_st;
return_state <= dual_op_write8_state;
next_state <= indexed_state;
when "1101" => -- jsr ,x
-- DO NOT pre decrement SP
st_ctrl <= push_st;
return_state <= jsr_state;
next_state <= indexed_state;
when "1111" => -- stx ,x
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when others =>
st_ctrl <= push_st;
return_state <= dual_op_read8_state;
next_state <= indexed_state;
end case;
when "1011" => -- acca extended
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- subd
"1100" | -- cmpx
"1110" => -- ldx
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when "0111" => -- staa >
st_ctrl <= push_st;
return_state <= dual_op_write8_state;
next_state <= extended_state;
when "1101" => -- jsr >extended
-- DO NOT pre decrement sp
st_ctrl <= push_st;
return_state <= jsr_state;
next_state <= extended_state;
when "1111" => -- stx >
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when others =>
st_ctrl <= push_st;
return_state <= dual_op_read8_state;
next_state <= extended_state;
end case;
when "1100" => -- accb immediate
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- addd #
"1100" | -- ldd #
"1110" => -- ldu #
next_state <= imm16_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1101" => -- accb direct
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- addd
"1100" | -- ldd
"1110" => -- ldu
next_state <= dual_op_read16_state;
when "0111" => -- stab direct
next_state <= dual_op_write8_state;
when "1101" => -- std direct
next_state <= dual_op_write16_state;
when "1111" => -- stu direct
next_state <= dual_op_write16_state;
when others =>
next_state <= dual_op_read8_state;
end case;
when "1110" => -- accb indexed
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- addd
"1100" | -- ldd
"1110" => -- ldu
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when "0111" => -- stab indexed
st_ctrl <= push_st;
return_state <= dual_op_write8_state;
next_state <= indexed_state;
when "1101" => -- std indexed
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when "1111" => -- stu indexed
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when others =>
st_ctrl <= push_st;
return_state <= dual_op_read8_state;
next_state <= indexed_state;
end case;
when "1111" => -- accb extended
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- addd
"1100" | -- ldd
"1110" => -- ldu
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when "0111" => -- stab extended
st_ctrl <= push_st;
return_state <= dual_op_write8_state;
next_state <= extended_state;
when "1101" => -- std extended
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when "1111" => -- stu extended
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when others =>
st_ctrl <= push_st;
return_state <= dual_op_read8_state;
next_state <= extended_state;
end case;
--
-- not sure why I need this
--
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
--
-- Here to decode prefix 2 instruction
-- and fetch next byte of intruction
-- whether it be necessary or not
--
when decode2_state =>
-- fetch first byte of address or immediate data
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
case op_code(7 downto 4) is
--
-- lbcc -- long branch conditional
-- 6809 => branch 6 cycles, no branch 5 cycles
-- cpu09 => always 5 cycles
-- 1 pre=(pc) / pc=pc+1
-- 2 op=(pc) / pc=pc+1
-- 3 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
-- 4 md_hi=md_lo / md_lo=(pc) / pc=pc+1
-- 5 if cond pc=pc+md else pc=pc
--
when "0010" =>
-- increment the pc
pc_ctrl <= incr_pc;
next_state <= lbranch_state;
--
-- Single byte stack operators
-- Do not advance PC
--
when "0011" =>
case op_code(3 downto 0) is
when "1111" => -- swi 2
-- predecrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= swi2_iv;
st_ctrl <= push_st;
return_state <= vect_hi_state;
next_state <= int_entire_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1000" => -- acca immediate
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpd #
"1100" | -- cmpy #
"1110" => -- ldy #
next_state <= imm16_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1001" => -- acca direct
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpd <
"1100" | -- cmpy <
"1110" => -- ldy <
next_state <= dual_op_read16_state;
when "1111" => -- sty <
next_state <= dual_op_write16_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1010" => -- acca indexed
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpd ,ind
"1100" | -- cmpy ,ind
"1110" => -- ldy ,ind
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when "1111" => -- sty ,ind
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1011" => -- acca extended
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpd <
"1100" | -- cmpy <
"1110" => -- ldy <
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when "1111" => -- sty >
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1100" => -- accb immediate
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- undef #
"1100" | -- undef #
"1110" => -- lds #
next_state <= imm16_state;
when others =>
next_state <= fetch_state;
end case;
when "1101" => -- accb direct
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- undef <
"1100" | -- undef <
"1110" => -- lds <
next_state <= dual_op_read16_state;
when "1111" => -- sts <
next_state <= dual_op_write16_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1110" => -- accb indexed
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- undef ,ind
"1100" | -- undef ,ind
"1110" => -- lds ,ind
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when "1111" => -- sts ,ind
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= indexed_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1111" => -- accb extended
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- undef >
"1100" | -- undef >
"1110" => -- lds >
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when "1111" => -- sts >
st_ctrl <= push_st;
return_state <= dual_op_write16_state;
next_state <= extended_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
--
-- Here to decode instruction
-- and fetch next byte of intruction
-- whether it be necessary or not
--
when decode3_state =>
ea_ctrl <= fetch_first_ea;
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
dout_ctrl <= md_lo_dout;
case op_code(7 downto 4) is
--
-- Single byte stack operators
-- Do not advance PC
--
when "0011" =>
case op_code(3 downto 0) is
when "1111" => -- swi3
-- predecrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= swi3_iv;
st_ctrl <= push_st;
return_state <= vect_hi_state;
next_state <= int_entire_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1000" => -- acca immediate
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpu #
"1100" | -- cmps #
"1110" => -- undef #
next_state <= imm16_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1001" => -- acca direct
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpu <
"1100" | -- cmps <
"1110" => -- undef <
next_state <= dual_op_read16_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1010" => -- acca indexed
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpu ,X
"1100" | -- cmps ,X
"1110" => -- undef ,X
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= indexed_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when "1011" => -- acca extended
-- increment the pc
pc_ctrl <= incr_pc;
case op_code(3 downto 0) is
when "0011" | -- cmpu >
"1100" | -- cmps >
"1110" => -- undef >
st_ctrl <= push_st;
return_state <= dual_op_read16_state;
next_state <= extended_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
--
-- here if ea holds low byte
-- Direct
-- Extended
-- Indexed
-- read memory location
--
when single_op_read_state =>
-- read memory into md
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
next_state <= single_op_exec_state;
when single_op_exec_state =>
case op_code(3 downto 0) is
when "0000" => -- neg
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_neg;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "0011" => -- com
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_com;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "0100" => -- lsr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_lsr8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "0110" => -- ror
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ror8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "0111" => -- asr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_asr8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "1000" => -- asl
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_asl8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "1001" => -- rol
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_rol8;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "1010" => -- dec
left_ctrl <= md_left;
right_ctrl <= one_right;
alu_ctrl <= alu_dec;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "1011" => -- undefined
lic <= '1';
next_state <= fetch_state;
when "1100" => -- inc
left_ctrl <= md_left;
right_ctrl <= one_right;
alu_ctrl <= alu_inc;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when "1101" => -- tst
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
lic <= '1';
next_state <= fetch_state;
when "1110" => -- jmp
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ld16;
pc_ctrl <= load_pc;
lic <= '1';
next_state <= fetch_state;
when "1111" => -- clr
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_clr;
cc_ctrl <= load_cc;
md_ctrl <= load_md;
next_state <= single_op_write_state;
when others =>
lic <= '1';
next_state <= fetch_state;
end case;
--
-- single operand 8 bit write
-- Write low 8 bits of ALU output
-- EA holds address
-- MD holds data
--
when single_op_write_state =>
-- write ALU low byte output
addr_ctrl <= write_ad;
dout_ctrl <= md_lo_dout;
lic <= '1';
next_state <= fetch_state;
--
-- here if ea holds address of low byte
-- read memory location
--
when dual_op_read8_state =>
-- read first data byte from ea
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
lic <= '1';
next_state <= fetch_state;
--
-- Here to read a 16 bit value into MD
-- pointed to by the EA register
-- The first byte is read
-- and the EA is incremented
--
when dual_op_read16_state =>
-- increment the effective address
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- read the high byte of the 16 bit data
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
next_state <= dual_op_read16_2_state;
--
-- here to read the second byte
-- pointed to by EA into MD
--
when dual_op_read16_2_state =>
-- read the low byte of the 16 bit data
md_ctrl <= fetch_next_md;
addr_ctrl <= read_ad;
lic <= '1';
next_state <= fetch_state;
--
-- 16 bit Write state
-- EA hold address of memory to write to
-- Advance the effective address in ALU
-- decode op_code to determine which
-- register to write
--
when dual_op_write16_state =>
-- increment the effective address
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- write the ALU hi byte at ea
addr_ctrl <= write_ad;
if op_code(6) = '0' then
case op_code(3 downto 0) is
when "1111" => -- stx / sty
case pre_code is
when "00010000" => -- page 2 -- sty
dout_ctrl <= iy_hi_dout;
when others => -- page 1 -- stx
dout_ctrl <= ix_hi_dout;
end case;
when others =>
dout_ctrl <= md_hi_dout;
end case;
else
case op_code(3 downto 0) is
when "1101" => -- std
dout_ctrl <= acca_dout; -- acca is high byte of ACCD
when "1111" => -- stu / sts
case pre_code is
when "00010000" => -- page 2 -- sts
dout_ctrl <= sp_hi_dout;
when others => -- page 1 -- stu
dout_ctrl <= up_hi_dout;
end case;
when others =>
dout_ctrl <= md_hi_dout;
end case;
end if;
next_state <= dual_op_write8_state;
--
-- Dual operand 8 bit write
-- Write 8 bit accumulator
-- or low byte of 16 bit register
-- EA holds address
-- decode opcode to determine
-- which register to apply to the bus
-- Also set the condition codes here
--
when dual_op_write8_state =>
if op_code(6) = '0' then
case op_code(3 downto 0) is
when "0111" => -- sta
dout_ctrl <= acca_dout;
when "1111" => -- stx / sty
case pre_code is
when "00010000" => -- page 2 -- sty
dout_ctrl <= iy_lo_dout;
when others => -- page 1 -- stx
dout_ctrl <= ix_lo_dout;
end case;
when others =>
dout_ctrl <= md_lo_dout;
end case;
else
case op_code(3 downto 0) is
when "0111" => -- stb
dout_ctrl <= accb_dout;
when "1101" => -- std
dout_ctrl <= accb_dout; -- accb is low byte of accd
when "1111" => -- stu / sts
case pre_code is
when "00010000" => -- page 2 -- sts
dout_ctrl <= sp_lo_dout;
when others => -- page 1 -- stu
dout_ctrl <= up_lo_dout;
end case;
when others =>
dout_ctrl <= md_lo_dout;
end case;
end if;
-- write ALU low byte output
addr_ctrl <= write_ad;
lic <= '1';
next_state <= fetch_state;
--
-- 16 bit immediate addressing mode
--
when imm16_state =>
-- increment pc
pc_ctrl <= incr_pc;
-- fetch next immediate byte
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
lic <= '1';
next_state <= fetch_state;
--
-- md & ea holds 8 bit index offset
-- calculate the effective memory address
-- using the alu
--
when indexed_state =>
--
-- decode indexing mode
--
if md(7) = '0' then
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= md_sign5_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
next_state <= saved_state;
else
case md(3 downto 0) is
when "0000" => -- ,R+
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
left_ctrl <= sp_left;
end case;
--
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
next_state <= postincr1_state;
when "0001" => -- ,R++
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
next_state <= postincr2_state;
when "0010" => -- ,-R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
ix_ctrl <= load_ix;
when "01" =>
left_ctrl <= iy_left;
iy_ctrl <= load_iy;
when "10" =>
left_ctrl <= up_left;
up_ctrl <= load_up;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
sp_ctrl <= load_sp;
end case;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
ea_ctrl <= load_ea;
next_state <= saved_state;
when "0011" => -- ,--R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
ix_ctrl <= load_ix;
when "01" =>
left_ctrl <= iy_left;
iy_ctrl <= load_iy;
when "10" =>
left_ctrl <= up_left;
up_ctrl <= load_up;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
sp_ctrl <= load_sp;
end case;
right_ctrl <= two_right;
alu_ctrl <= alu_sub16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "0100" => -- ,R (zero offset)
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "0101" => -- ACCB,R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= accb_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "0110" => -- ACCA,R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= acca_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "0111" => -- undefined
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "1000" => -- offset8,R
md_ctrl <= fetch_first_md; -- pick up 8 bit offset
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
next_state <= index8_state;
when "1001" => -- offset16,R
md_ctrl <= fetch_first_md; -- pick up first byte of 16 bit offset
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
next_state <= index16_state;
when "1010" => -- undefined
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
--
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "1011" => -- ACCD,R
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= accd_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when "1100" => -- offset8,PC
-- fetch 8 bit offset
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
next_state <= pcrel8_state;
when "1101" => -- offset16,PC
-- fetch offset
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
next_state <= pcrel16_state;
when "1110" => -- undefined
case md(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
when others =>
-- when "1111" => -- [,address]
-- advance PC to pick up address
md_ctrl <= fetch_first_md;
addr_ctrl <= fetch_ad;
pc_ctrl <= incr_pc;
next_state <= indexaddr_state;
end case;
end if;
-- load index register with ea plus one
when postincr1_state =>
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
case md(6 downto 5) is
when "00" =>
ix_ctrl <= load_ix;
when "01" =>
iy_ctrl <= load_iy;
when "10" =>
up_ctrl <= load_up;
when others =>
-- when "11" =>
sp_ctrl <= load_sp;
end case;
-- return to previous state
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
-- load index register with ea plus two
when postincr2_state =>
-- increment register by two (address)
left_ctrl <= ea_left;
right_ctrl <= two_right;
alu_ctrl <= alu_add16;
case md(6 downto 5) is
when "00" =>
ix_ctrl <= load_ix;
when "01" =>
iy_ctrl <= load_iy;
when "10" =>
up_ctrl <= load_up;
when others =>
-- when "11" =>
sp_ctrl <= load_sp;
end case;
-- return to previous state
if md(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
--
-- ea = index register + md (8 bit signed offset)
-- ea holds post byte
--
when index8_state =>
case ea(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
-- ea = index reg + md
right_ctrl <= md_sign8_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- return to previous state
if ea(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
-- fetch low byte of 16 bit indexed offset
when index16_state =>
-- advance pc
pc_ctrl <= incr_pc;
-- fetch low byte
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
next_state <= index16_2_state;
-- ea = index register + md (16 bit offset)
-- ea holds post byte
when index16_2_state =>
case ea(6 downto 5) is
when "00" =>
left_ctrl <= ix_left;
when "01" =>
left_ctrl <= iy_left;
when "10" =>
left_ctrl <= up_left;
when others =>
-- when "11" =>
left_ctrl <= sp_left;
end case;
-- ea = index reg + md
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- return to previous state
if ea(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
--
-- pc relative with 8 bit signed offest
-- md holds signed offset
--
when pcrel8_state =>
-- ea = pc + signed md
left_ctrl <= pc_left;
right_ctrl <= md_sign8_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- return to previous state
if ea(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
-- pc relative addressing with 16 bit offset
-- pick up the low byte of the offset in md
-- advance the pc
when pcrel16_state =>
-- advance pc
pc_ctrl <= incr_pc;
-- fetch low byte
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
next_state <= pcrel16_2_state;
-- pc relative with16 bit signed offest
-- md holds signed offset
when pcrel16_2_state =>
-- ea = pc + md
left_ctrl <= pc_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- return to previous state
if ea(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
-- indexed to address
-- pick up the low byte of the address
-- advance the pc
when indexaddr_state =>
-- advance pc
pc_ctrl <= incr_pc;
-- fetch low byte
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
next_state <= indexaddr2_state;
-- indexed to absolute address
-- md holds address
-- ea hold indexing mode byte
when indexaddr2_state =>
-- ea = md
left_ctrl <= pc_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
ea_ctrl <= load_ea;
-- return to previous state
if ea(4) = '0' then
next_state <= saved_state;
else
next_state <= indirect_state;
end if;
--
-- load md with high byte of indirect address
-- pointed to by ea
-- increment ea
--
when indirect_state =>
-- increment ea
left_ctrl <= ea_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
ea_ctrl <= load_ea;
-- fetch high byte
md_ctrl <= fetch_first_md;
addr_ctrl <= read_ad;
next_state <= indirect2_state;
--
-- load md with low byte of indirect address
-- pointed to by ea
-- ea has previously been incremented
--
when indirect2_state =>
-- fetch high byte
md_ctrl <= fetch_next_md;
addr_ctrl <= read_ad;
dout_ctrl <= md_lo_dout;
next_state <= indirect3_state;
--
-- complete idirect addressing
-- by loading ea with md
--
when indirect3_state =>
-- load ea with md
left_ctrl <= ea_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
ea_ctrl <= load_ea;
-- return to previous state
next_state <= saved_state;
--
-- ea holds the low byte of the absolute address
-- Move ea low byte into ea high byte
-- load new ea low byte to for absolute 16 bit address
-- advance the program counter
--
when extended_state => -- fetch ea low byte
-- increment pc
pc_ctrl <= incr_pc;
-- fetch next effective address bytes
ea_ctrl <= fetch_next_ea;
addr_ctrl <= fetch_ad;
-- return to previous state
next_state <= saved_state;
when lea_state => -- here on load effective address
-- load index register with effective address
left_ctrl <= pc_left;
right_ctrl <= ea_right;
alu_ctrl <= alu_lea;
case op_code(3 downto 0) is
when "0000" => -- leax
cc_ctrl <= load_cc;
ix_ctrl <= load_ix;
when "0001" => -- leay
cc_ctrl <= load_cc;
iy_ctrl <= load_iy;
when "0010" => -- leas
sp_ctrl <= load_sp;
when "0011" => -- leau
up_ctrl <= load_up;
when others =>
null;
end case;
lic <= '1';
next_state <= fetch_state;
--
-- jump to subroutine
-- sp=sp-1
-- call push_return_lo_state to save pc
-- return to jmp_state
--
when jsr_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- call push_return_state
st_ctrl <= push_st;
return_state <= jmp_state;
next_state <= push_return_lo_state;
--
-- Load pc with ea
-- (JMP)
--
when jmp_state =>
-- load PC with effective address
left_ctrl <= pc_left;
right_ctrl <= ea_right;
alu_ctrl <= alu_ld16;
pc_ctrl <= load_pc;
lic <= '1';
next_state <= fetch_state;
--
-- long branch or branch to subroutine
-- pick up next md byte
-- md_hi = md_lo
-- md_lo = (pc)
-- pc=pc+1
-- if a lbsr push return address
-- continue to sbranch_state
-- to evaluate conditional branches
--
when lbranch_state =>
pc_ctrl <= incr_pc;
-- fetch the next byte into md_lo
md_ctrl <= fetch_next_md;
addr_ctrl <= fetch_ad;
-- if lbsr - push return address
-- then continue on to short branch
if op_code = "00010111" then
st_ctrl <= push_st;
return_state <= sbranch_state;
next_state <= push_return_lo_state;
else
next_state <= sbranch_state;
end if;
--
-- here to execute conditional branch
-- short conditional branch md = signed 8 bit offset
-- long branch md = 16 bit offset
--
when sbranch_state =>
left_ctrl <= pc_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
-- Test condition for branch
if op_code(7 downto 4) = "0010" then -- conditional branch
case op_code(3 downto 0) is
when "0000" => -- bra
cond_true := (1 = 1);
when "0001" => -- brn
cond_true := (1 = 0);
when "0010" => -- bhi
cond_true := ((cc(CBIT) or cc(ZBIT)) = '0');
when "0011" => -- bls
cond_true := ((cc(CBIT) or cc(ZBIT)) = '1');
when "0100" => -- bcc/bhs
cond_true := (cc(CBIT) = '0');
when "0101" => -- bcs/blo
cond_true := (cc(CBIT) = '1');
when "0110" => -- bne
cond_true := (cc(ZBIT) = '0');
when "0111" => -- beq
cond_true := (cc(ZBIT) = '1');
when "1000" => -- bvc
cond_true := (cc(VBIT) = '0');
when "1001" => -- bvs
cond_true := (cc(VBIT) = '1');
when "1010" => -- bpl
cond_true := (cc(NBIT) = '0');
when "1011" => -- bmi
cond_true := (cc(NBIT) = '1');
when "1100" => -- bge
cond_true := ((cc(NBIT) xor cc(VBIT)) = '0');
when "1101" => -- blt
cond_true := ((cc(NBIT) xor cc(VBIT)) = '1');
when "1110" => -- bgt
cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0');
when "1111" => -- ble
cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1');
when others =>
null;
end case;
end if;
if cond_true then
pc_ctrl <= load_pc;
end if;
lic <= '1';
next_state <= fetch_state;
--
-- push return address onto the S stack
--
-- (sp) = pc_lo
-- sp = sp - 1
--
when push_return_lo_state =>
-- decrement the sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write PC low
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_lo_dout;
next_state <= push_return_hi_state;
--
-- push program counter hi byte onto the stack
-- (sp) = pc_hi
-- sp = sp
-- return to originating state
--
when push_return_hi_state =>
-- write pc hi bytes
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_hi_dout;
next_state <= saved_state;
--
-- RTS pull return address from stack
--
when pull_return_hi_state =>
-- increment the sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pulls_ad;
next_state <= pull_return_lo_state;
when pull_return_lo_state =>
-- increment the SP
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pulls_ad;
dout_ctrl <= pc_lo_dout;
--
lic <= '1';
next_state <= fetch_state;
when andcc_state =>
-- AND CC with md
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_andcc;
cc_ctrl <= load_cc;
--
lic <= '1';
next_state <= fetch_state;
when orcc_state =>
-- OR CC with md
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_orcc;
cc_ctrl <= load_cc;
--
lic <= '1';
next_state <= fetch_state;
when tfr_state =>
-- select source register
case md(7 downto 4) is
when "0000" =>
left_ctrl <= accd_left;
when "0001" =>
left_ctrl <= ix_left;
when "0010" =>
left_ctrl <= iy_left;
when "0011" =>
left_ctrl <= up_left;
when "0100" =>
left_ctrl <= sp_left;
when "0101" =>
left_ctrl <= pc_left;
when "1000" =>
left_ctrl <= acca_left;
when "1001" =>
left_ctrl <= accb_left;
when "1010" =>
left_ctrl <= cc_left;
when "1011" =>
left_ctrl <= dp_left;
when others =>
left_ctrl <= md_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_tfr;
-- select destination register
case md(3 downto 0) is
when "0000" => -- accd
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
when "0001" => -- ix
ix_ctrl <= load_ix;
when "0010" => -- iy
iy_ctrl <= load_iy;
when "0011" => -- up
up_ctrl <= load_up;
when "0100" => -- sp
sp_ctrl <= load_sp;
when "0101" => -- pc
pc_ctrl <= load_pc;
when "1000" => -- acca
acca_ctrl <= load_acca;
when "1001" => -- accb
accb_ctrl <= load_accb;
when "1010" => -- cc
cc_ctrl <= load_cc;
when "1011" => --dp
dp_ctrl <= load_dp;
when others =>
null;
end case;
--
lic <= '1';
next_state <= fetch_state;
when exg_state =>
-- save destination register
case md(3 downto 0) is
when "0000" =>
left_ctrl <= accd_left;
when "0001" =>
left_ctrl <= ix_left;
when "0010" =>
left_ctrl <= iy_left;
when "0011" =>
left_ctrl <= up_left;
when "0100" =>
left_ctrl <= sp_left;
when "0101" =>
left_ctrl <= pc_left;
when "1000" =>
left_ctrl <= acca_left;
when "1001" =>
left_ctrl <= accb_left;
when "1010" =>
left_ctrl <= cc_left;
when "1011" =>
left_ctrl <= dp_left;
when others =>
left_ctrl <= md_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_tfr;
ea_ctrl <= load_ea;
-- call tranfer microcode
next_state <= exg1_state;
when exg1_state =>
-- select source register
case md(7 downto 4) is
when "0000" =>
left_ctrl <= accd_left;
when "0001" =>
left_ctrl <= ix_left;
when "0010" =>
left_ctrl <= iy_left;
when "0011" =>
left_ctrl <= up_left;
when "0100" =>
left_ctrl <= sp_left;
when "0101" =>
left_ctrl <= pc_left;
when "1000" =>
left_ctrl <= acca_left;
when "1001" =>
left_ctrl <= accb_left;
when "1010" =>
left_ctrl <= cc_left;
when "1011" =>
left_ctrl <= dp_left;
when others =>
left_ctrl <= md_left;
end case;
right_ctrl <= zero_right;
alu_ctrl <= alu_tfr;
-- select destination register
case md(3 downto 0) is
when "0000" => -- accd
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
when "0001" => -- ix
ix_ctrl <= load_ix;
when "0010" => -- iy
iy_ctrl <= load_iy;
when "0011" => -- up
up_ctrl <= load_up;
when "0100" => -- sp
sp_ctrl <= load_sp;
when "0101" => -- pc
pc_ctrl <= load_pc;
when "1000" => -- acca
acca_ctrl <= load_acca;
when "1001" => -- accb
accb_ctrl <= load_accb;
when "1010" => -- cc
cc_ctrl <= load_cc;
when "1011" => --dp
dp_ctrl <= load_dp;
when others =>
null;
end case;
next_state <= exg2_state;
when exg2_state =>
-- restore destination
left_ctrl <= ea_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_tfr;
-- save as source register
case md(7 downto 4) is
when "0000" => -- accd
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
when "0001" => -- ix
ix_ctrl <= load_ix;
when "0010" => -- iy
iy_ctrl <= load_iy;
when "0011" => -- up
up_ctrl <= load_up;
when "0100" => -- sp
sp_ctrl <= load_sp;
when "0101" => -- pc
pc_ctrl <= load_pc;
when "1000" => -- acca
acca_ctrl <= load_acca;
when "1001" => -- accb
accb_ctrl <= load_accb;
when "1010" => -- cc
cc_ctrl <= load_cc;
when "1011" => --dp
dp_ctrl <= load_dp;
when others =>
null;
end case;
lic <= '1';
next_state <= fetch_state;
when mul_state =>
-- move acca to md
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
md_ctrl <= load_md;
next_state <= mulea_state;
when mulea_state =>
-- move accb to ea
left_ctrl <= accb_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_st16;
ea_ctrl <= load_ea;
next_state <= muld_state;
when muld_state =>
-- clear accd
left_ctrl <= acca_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_ld8;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
next_state <= mul0_state;
when mul0_state =>
-- if bit 0 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(0) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul1_state;
when mul1_state =>
-- if bit 1 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(1) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul2_state;
when mul2_state =>
-- if bit 2 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(2) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul3_state;
when mul3_state =>
-- if bit 3 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(3) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul4_state;
when mul4_state =>
-- if bit 4 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(4) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul5_state;
when mul5_state =>
-- if bit 5 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(5) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul6_state;
when mul6_state =>
-- if bit 6 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(6) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
next_state <= mul7_state;
when mul7_state =>
-- if bit 7 of ea set, add accd to md
left_ctrl <= accd_left;
if ea(7) = '1' then
right_ctrl <= md_right;
else
right_ctrl <= zero_right;
end if;
alu_ctrl <= alu_mul;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
md_ctrl <= shiftl_md;
lic <= '1';
next_state <= fetch_state;
--
-- Enter here on pushs
-- ea holds post byte
--
when pshs_state =>
-- decrement sp if any registers to be pushed
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
-- idle address
addr_ctrl <= idle_ad;
dout_ctrl <= cc_dout;
if ea(7 downto 0) = "00000000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
if ea(7) = '1' then
next_state <= pshs_pcl_state;
elsif ea(6) = '1' then
next_state <= pshs_upl_state;
elsif ea(5) = '1' then
next_state <= pshs_iyl_state;
elsif ea(4) = '1' then
next_state <= pshs_ixl_state;
elsif ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_pcl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_lo_dout;
next_state <= pshs_pch_state;
when pshs_pch_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(6 downto 0) = "0000000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write pc hi
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_hi_dout;
if ea(6) = '1' then
next_state <= pshs_upl_state;
elsif ea(5) = '1' then
next_state <= pshs_iyl_state;
elsif ea(4) = '1' then
next_state <= pshs_ixl_state;
elsif ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_upl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= pushs_ad;
dout_ctrl <= up_lo_dout;
next_state <= pshs_uph_state;
when pshs_uph_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(5 downto 0) = "000000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write pc hi
addr_ctrl <= pushs_ad;
dout_ctrl <= up_hi_dout;
if ea(5) = '1' then
next_state <= pshs_iyl_state;
elsif ea(4) = '1' then
next_state <= pshs_ixl_state;
elsif ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_iyl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write iy low
addr_ctrl <= pushs_ad;
dout_ctrl <= iy_lo_dout;
next_state <= pshs_iyh_state;
when pshs_iyh_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(4 downto 0) = "00000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write iy hi
addr_ctrl <= pushs_ad;
dout_ctrl <= iy_hi_dout;
if ea(4) = '1' then
next_state <= pshs_ixl_state;
elsif ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_ixl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix low
addr_ctrl <= pushs_ad;
dout_ctrl <= ix_lo_dout;
next_state <= pshs_ixh_state;
when pshs_ixh_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(3 downto 0) = "0000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write ix hi
addr_ctrl <= pushs_ad;
dout_ctrl <= ix_hi_dout;
if ea(3) = '1' then
next_state <= pshs_dp_state;
elsif ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_dp_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(2 downto 0) = "000" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write dp
addr_ctrl <= pushs_ad;
dout_ctrl <= dp_dout;
if ea(2) = '1' then
next_state <= pshs_accb_state;
elsif ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_accb_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(1 downto 0) = "00" then
sp_ctrl <= latch_sp;
else
sp_ctrl <= load_sp;
end if;
-- write accb
addr_ctrl <= pushs_ad;
dout_ctrl <= accb_dout;
if ea(1) = '1' then
next_state <= pshs_acca_state;
elsif ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_acca_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(0) = '1' then
sp_ctrl <= load_sp;
else
sp_ctrl <= latch_sp;
end if;
-- write acca
addr_ctrl <= pushs_ad;
dout_ctrl <= acca_dout;
if ea(0) = '1' then
next_state <= pshs_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshs_cc_state =>
-- idle sp
-- write cc
addr_ctrl <= pushs_ad;
dout_ctrl <= cc_dout;
lic <= '1';
next_state <= fetch_state;
--
-- enter here on PULS
-- ea hold register mask
--
when puls_state =>
if ea(0) = '1' then
next_state <= puls_cc_state;
elsif ea(1) = '1' then
next_state <= puls_acca_state;
elsif ea(2) = '1' then
next_state <= puls_accb_state;
elsif ea(3) = '1' then
next_state <= puls_dp_state;
elsif ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_cc_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read cc
cc_ctrl <= pull_cc;
addr_ctrl <= pulls_ad;
if ea(1) = '1' then
next_state <= puls_acca_state;
elsif ea(2) = '1' then
next_state <= puls_accb_state;
elsif ea(3) = '1' then
next_state <= puls_dp_state;
elsif ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_acca_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read acca
acca_ctrl <= pull_acca;
addr_ctrl <= pulls_ad;
if ea(2) = '1' then
next_state <= puls_accb_state;
elsif ea(3) = '1' then
next_state <= puls_dp_state;
elsif ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_accb_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read accb
accb_ctrl <= pull_accb;
addr_ctrl <= pulls_ad;
if ea(3) = '1' then
next_state <= puls_dp_state;
elsif ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_dp_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read dp
dp_ctrl <= pull_dp;
addr_ctrl <= pulls_ad;
if ea(4) = '1' then
next_state <= puls_ixh_state;
elsif ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_ixh_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull ix hi
ix_ctrl <= pull_hi_ix;
addr_ctrl <= pulls_ad;
next_state <= puls_ixl_state;
when puls_ixl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read ix low
ix_ctrl <= pull_lo_ix;
addr_ctrl <= pulls_ad;
if ea(5) = '1' then
next_state <= puls_iyh_state;
elsif ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_iyh_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull iy hi
iy_ctrl <= pull_hi_iy;
addr_ctrl <= pulls_ad;
next_state <= puls_iyl_state;
when puls_iyl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read iy low
iy_ctrl <= pull_lo_iy;
addr_ctrl <= pulls_ad;
if ea(6) = '1' then
next_state <= puls_uph_state;
elsif ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_uph_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull up hi
up_ctrl <= pull_hi_up;
addr_ctrl <= pulls_ad;
next_state <= puls_upl_state;
when puls_upl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read up low
up_ctrl <= pull_lo_up;
addr_ctrl <= pulls_ad;
if ea(7) = '1' then
next_state <= puls_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when puls_pch_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pulls_ad;
next_state <= puls_pcl_state;
when puls_pcl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pulls_ad;
lic <= '1';
next_state <= fetch_state;
--
-- Enter here on pshu
-- ea holds post byte
--
when pshu_state =>
-- decrement up if any registers to be pushed
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(7 downto 0) = "00000000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write idle bus
if ea(7) = '1' then
next_state <= pshu_pcl_state;
elsif ea(6) = '1' then
next_state <= pshu_spl_state;
elsif ea(5) = '1' then
next_state <= pshu_iyl_state;
elsif ea(4) = '1' then
next_state <= pshu_ixl_state;
elsif ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
--
-- push PC onto U stack
--
when pshu_pcl_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
up_ctrl <= load_up;
-- write pc low
addr_ctrl <= pushu_ad;
dout_ctrl <= pc_lo_dout;
next_state <= pshu_pch_state;
when pshu_pch_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(6 downto 0) = "0000000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write pc hi
addr_ctrl <= pushu_ad;
dout_ctrl <= pc_hi_dout;
if ea(6) = '1' then
next_state <= pshu_spl_state;
elsif ea(5) = '1' then
next_state <= pshu_iyl_state;
elsif ea(4) = '1' then
next_state <= pshu_ixl_state;
elsif ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_spl_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
up_ctrl <= load_up;
-- write sp low
addr_ctrl <= pushu_ad;
dout_ctrl <= sp_lo_dout;
next_state <= pshu_sph_state;
when pshu_sph_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(5 downto 0) = "000000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write sp hi
addr_ctrl <= pushu_ad;
dout_ctrl <= sp_hi_dout;
if ea(5) = '1' then
next_state <= pshu_iyl_state;
elsif ea(4) = '1' then
next_state <= pshu_ixl_state;
elsif ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_iyl_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
up_ctrl <= load_up;
-- write iy low
addr_ctrl <= pushu_ad;
dout_ctrl <= iy_lo_dout;
next_state <= pshu_iyh_state;
when pshu_iyh_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(4 downto 0) = "00000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write iy hi
addr_ctrl <= pushu_ad;
dout_ctrl <= iy_hi_dout;
if ea(4) = '1' then
next_state <= pshu_ixl_state;
elsif ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_ixl_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
up_ctrl <= load_up;
-- write ix low
addr_ctrl <= pushu_ad;
dout_ctrl <= ix_lo_dout;
next_state <= pshu_ixh_state;
when pshu_ixh_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(3 downto 0) = "0000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write ix hi
addr_ctrl <= pushu_ad;
dout_ctrl <= ix_hi_dout;
if ea(3) = '1' then
next_state <= pshu_dp_state;
elsif ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_dp_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(2 downto 0) = "000" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write dp
addr_ctrl <= pushu_ad;
dout_ctrl <= dp_dout;
if ea(2) = '1' then
next_state <= pshu_accb_state;
elsif ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_accb_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(1 downto 0) = "00" then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write accb
addr_ctrl <= pushu_ad;
dout_ctrl <= accb_dout;
if ea(1) = '1' then
next_state <= pshu_acca_state;
elsif ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_acca_state =>
-- decrement up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
if ea(0) = '0' then
up_ctrl <= latch_up;
else
up_ctrl <= load_up;
end if;
-- write acca
addr_ctrl <= pushu_ad;
dout_ctrl <= acca_dout;
if ea(0) = '1' then
next_state <= pshu_cc_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pshu_cc_state =>
-- idle up
-- write cc
addr_ctrl <= pushu_ad;
dout_ctrl <= cc_dout;
lic <= '1';
next_state <= fetch_state;
--
-- enter here on PULU
-- ea hold register mask
--
when pulu_state =>
-- idle UP
-- idle bus
if ea(0) = '1' then
next_state <= pulu_cc_state;
elsif ea(1) = '1' then
next_state <= pulu_acca_state;
elsif ea(2) = '1' then
next_state <= pulu_accb_state;
elsif ea(3) = '1' then
next_state <= pulu_dp_state;
elsif ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_cc_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read cc
cc_ctrl <= pull_cc;
addr_ctrl <= pullu_ad;
if ea(1) = '1' then
next_state <= pulu_acca_state;
elsif ea(2) = '1' then
next_state <= pulu_accb_state;
elsif ea(3) = '1' then
next_state <= pulu_dp_state;
elsif ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_acca_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read acca
acca_ctrl <= pull_acca;
addr_ctrl <= pullu_ad;
if ea(2) = '1' then
next_state <= pulu_accb_state;
elsif ea(3) = '1' then
next_state <= pulu_dp_state;
elsif ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_accb_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read accb
accb_ctrl <= pull_accb;
addr_ctrl <= pullu_ad;
if ea(3) = '1' then
next_state <= pulu_dp_state;
elsif ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_dp_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read dp
dp_ctrl <= pull_dp;
addr_ctrl <= pullu_ad;
if ea(4) = '1' then
next_state <= pulu_ixh_state;
elsif ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_ixh_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read ix hi
ix_ctrl <= pull_hi_ix;
addr_ctrl <= pullu_ad;
next_state <= pulu_ixl_state;
when pulu_ixl_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read ix low
ix_ctrl <= pull_lo_ix;
addr_ctrl <= pullu_ad;
if ea(5) = '1' then
next_state <= pulu_iyh_state;
elsif ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_iyh_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read iy hi
iy_ctrl <= pull_hi_iy;
addr_ctrl <= pullu_ad;
next_state <= pulu_iyl_state;
when pulu_iyl_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read iy low
iy_ctrl <= pull_lo_iy;
addr_ctrl <= pullu_ad;
if ea(6) = '1' then
next_state <= pulu_sph_state;
elsif ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_sph_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read sp hi
sp_ctrl <= pull_hi_sp;
addr_ctrl <= pullu_ad;
next_state <= pulu_spl_state;
when pulu_spl_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read sp low
sp_ctrl <= pull_lo_sp;
addr_ctrl <= pullu_ad;
if ea(7) = '1' then
next_state <= pulu_pch_state;
else
lic <= '1';
next_state <= fetch_state;
end if;
when pulu_pch_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- pull pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pullu_ad;
next_state <= pulu_pcl_state;
when pulu_pcl_state =>
-- increment up
left_ctrl <= up_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
up_ctrl <= load_up;
-- read pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pullu_ad;
lic <= '1';
next_state <= fetch_state;
--
-- pop the Condition codes
--
when rti_cc_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read cc
cc_ctrl <= pull_cc;
addr_ctrl <= pulls_ad;
next_state <= rti_entire_state;
--
-- Added RTI cycle 11th July 2006 John Kent.
-- test the "Entire" Flag
-- that has just been popped off the stack
--
when rti_entire_state =>
--
-- The Entire flag must be recovered from the stack
-- before testing.
--
if cc(EBIT) = '1' then
next_state <= rti_acca_state;
else
next_state <= rti_pch_state;
end if;
when rti_acca_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read acca
acca_ctrl <= pull_acca;
addr_ctrl <= pulls_ad;
next_state <= rti_accb_state;
when rti_accb_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read accb
accb_ctrl <= pull_accb;
addr_ctrl <= pulls_ad;
next_state <= rti_dp_state;
when rti_dp_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read dp
dp_ctrl <= pull_dp;
addr_ctrl <= pulls_ad;
next_state <= rti_ixh_state;
when rti_ixh_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read ix hi
ix_ctrl <= pull_hi_ix;
addr_ctrl <= pulls_ad;
next_state <= rti_ixl_state;
when rti_ixl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read ix low
ix_ctrl <= pull_lo_ix;
addr_ctrl <= pulls_ad;
next_state <= rti_iyh_state;
when rti_iyh_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read iy hi
iy_ctrl <= pull_hi_iy;
addr_ctrl <= pulls_ad;
next_state <= rti_iyl_state;
when rti_iyl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read iy low
iy_ctrl <= pull_lo_iy;
addr_ctrl <= pulls_ad;
next_state <= rti_uph_state;
when rti_uph_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read up hi
up_ctrl <= pull_hi_up;
addr_ctrl <= pulls_ad;
next_state <= rti_upl_state;
when rti_upl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- read up low
up_ctrl <= pull_lo_up;
addr_ctrl <= pulls_ad;
next_state <= rti_pch_state;
when rti_pch_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull pc hi
pc_ctrl <= pull_hi_pc;
addr_ctrl <= pulls_ad;
next_state <= rti_pcl_state;
when rti_pcl_state =>
-- increment sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_add16;
sp_ctrl <= load_sp;
-- pull pc low
pc_ctrl <= pull_lo_pc;
addr_ctrl <= pulls_ad;
lic <= '1';
next_state <= fetch_state;
--
-- here on NMI interrupt
-- Complete execute cycle of the last instruction.
-- If it was a dual operand instruction
--
when int_nmi_state =>
next_state <= int_nmi1_state;
-- Idle bus cycle
when int_nmi1_state =>
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= nmi_iv;
st_ctrl <= push_st;
return_state <= int_nmimask_state;
next_state <= int_entire_state;
--
-- here on IRQ interrupt
-- Complete execute cycle of the last instruction.
-- If it was a dual operand instruction
--
when int_irq_state =>
next_state <= int_irq1_state;
-- pre decrement the sp
-- Idle bus cycle
when int_irq1_state =>
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= irq_iv;
st_ctrl <= push_st;
return_state <= int_irqmask_state;
next_state <= int_entire_state;
--
-- here on FIRQ interrupt
-- Complete execution cycle of the last instruction
-- if it was a dual operand instruction
--
when int_firq_state =>
next_state <= int_firq1_state;
-- Idle bus cycle
when int_firq1_state =>
-- pre decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
iv_ctrl <= firq_iv;
st_ctrl <= push_st;
return_state <= int_firqmask_state;
next_state <= int_fast_state;
--
-- CWAI entry point
-- stack pointer already pre-decremented
-- mask condition codes
--
when cwai_state =>
-- AND CC with md
left_ctrl <= md_left;
right_ctrl <= zero_right;
alu_ctrl <= alu_andcc;
cc_ctrl <= load_cc;
st_ctrl <= push_st;
return_state <= int_cwai_state;
next_state <= int_entire_state;
--
-- wait here for an interrupt
--
when int_cwai_state =>
if (nmi_req = '1') then
iv_ctrl <= nmi_iv;
next_state <= int_nmimask_state;
--
-- FIRQ & IRQ are level sensitive
--
elsif (firq = '1') and (cc(FBIT) = '0') then
iv_ctrl <= firq_iv;
next_state <= int_firqmask_state;
elsif (irq = '1') and (cc(IBIT) = '0') then
iv_ctrl <= irq_iv;
next_state <= int_irqmask_state;
else
next_state <= int_cwai_state;
end if;
--
-- State to mask I Flag and F Flag (NMI)
--
when int_nmimask_state =>
alu_ctrl <= alu_seif;
cc_ctrl <= load_cc;
next_state <= vect_hi_state;
--
-- State to mask I Flag and F Flag (FIRQ)
--
when int_firqmask_state =>
alu_ctrl <= alu_seif;
cc_ctrl <= load_cc;
next_state <= vect_hi_state;
--
-- State to mask I Flag and F Flag (SWI)
--
when int_swimask_state =>
alu_ctrl <= alu_seif;
cc_ctrl <= load_cc;
next_state <= vect_hi_state;
--
-- State to mask I Flag only (IRQ)
--
when int_irqmask_state =>
alu_ctrl <= alu_sei;
cc_ctrl <= load_cc;
next_state <= vect_hi_state;
--
-- set Entire Flag on SWI, SWI2, SWI3 and CWAI, IRQ and NMI
-- before stacking all registers
--
when int_entire_state =>
-- set entire flag
alu_ctrl <= alu_see;
cc_ctrl <= load_cc;
next_state <= int_pcl_state;
--
-- clear Entire Flag on FIRQ
-- before stacking all registers
--
when int_fast_state =>
-- clear entire flag
alu_ctrl <= alu_cle;
cc_ctrl <= load_cc;
next_state <= int_pcl_state;
when int_pcl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write pc low
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_lo_dout;
next_state <= int_pch_state;
when int_pch_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write pc hi
addr_ctrl <= pushs_ad;
dout_ctrl <= pc_hi_dout;
if cc(EBIT) = '1' then
next_state <= int_upl_state;
else
next_state <= int_cc_state;
end if;
when int_upl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write up low
addr_ctrl <= pushs_ad;
dout_ctrl <= up_lo_dout;
next_state <= int_uph_state;
when int_uph_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix hi
addr_ctrl <= pushs_ad;
dout_ctrl <= up_hi_dout;
next_state <= int_iyl_state;
when int_iyl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix low
addr_ctrl <= pushs_ad;
dout_ctrl <= iy_lo_dout;
next_state <= int_iyh_state;
when int_iyh_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix hi
addr_ctrl <= pushs_ad;
dout_ctrl <= iy_hi_dout;
next_state <= int_ixl_state;
when int_ixl_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix low
addr_ctrl <= pushs_ad;
dout_ctrl <= ix_lo_dout;
next_state <= int_ixh_state;
when int_ixh_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write ix hi
addr_ctrl <= pushs_ad;
dout_ctrl <= ix_hi_dout;
next_state <= int_dp_state;
when int_dp_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write accb
addr_ctrl <= pushs_ad;
dout_ctrl <= dp_dout;
next_state <= int_accb_state;
when int_accb_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write accb
addr_ctrl <= pushs_ad;
dout_ctrl <= accb_dout;
next_state <= int_acca_state;
when int_acca_state =>
-- decrement sp
left_ctrl <= sp_left;
right_ctrl <= one_right;
alu_ctrl <= alu_sub16;
sp_ctrl <= load_sp;
-- write acca
addr_ctrl <= pushs_ad;
dout_ctrl <= acca_dout;
next_state <= int_cc_state;
when int_cc_state =>
-- write cc
addr_ctrl <= pushs_ad;
dout_ctrl <= cc_dout;
next_state <= saved_state;
--
-- According to the 6809 programming manual:
-- If an interrupt is received and is masked
-- or lasts for less than three cycles, the PC
-- will advance to the next instruction.
-- If an interrupt is unmasked and lasts
-- for more than three cycles, an interrupt
-- will be generated.
-- Note that I don't wait 3 clock cycles.
-- John Kent 11th July 2006
--
when sync_state =>
lic <= '1';
ba <= '1';
next_state <= sync_state;
when halt_state =>
--
-- 2011-10-30 John Kent
-- ba & bs should be high
ba <= '1';
bs <= '1';
if halt = '1' then
next_state <= halt_state;
else
next_state <= fetch_state;
end if;
end case;
--
-- Ver 1.23 2011-10-30 John Kent
-- First instruction cycle might be
-- fetch_state
-- halt_state
-- int_nmirq_state
-- int_firq_state
--
if fic = '1' then
--
case op_code(7 downto 6) is
when "10" => -- acca
case op_code(3 downto 0) is
when "0000" => -- suba
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "0001" => -- cmpa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
when "0010" => -- sbca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "0011" =>
case pre_code is
when "00010000" => -- page 2 -- cmpd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
when "00010001" => -- page 3 -- cmpu
left_ctrl <= up_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
when others => -- page 1 -- subd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
end case;
when "0100" => -- anda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "0101" => -- bita
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
when "0110" => -- ldaa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "0111" => -- staa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
when "1000" => -- eora
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "1001" => -- adca
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "1010" => -- oraa
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "1011" => -- adda
left_ctrl <= acca_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
acca_ctrl <= load_acca;
when "1100" =>
case pre_code is
when "00010000" => -- page 2 -- cmpy
left_ctrl <= iy_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
when "00010001" => -- page 3 -- cmps
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
when others => -- page 1 -- cmpx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub16;
cc_ctrl <= load_cc;
end case;
when "1101" => -- bsr / jsr
null;
when "1110" => -- ldx
case pre_code is
when "00010000" => -- page 2 -- ldy
left_ctrl <= iy_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
iy_ctrl <= load_iy;
when others => -- page 1 -- ldx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
ix_ctrl <= load_ix;
end case;
when "1111" => -- stx
case pre_code is
when "00010000" => -- page 2 -- sty
left_ctrl <= iy_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
when others => -- page 1 -- stx
left_ctrl <= ix_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
end case;
when others =>
null;
end case;
when "11" => -- accb dual op
case op_code(3 downto 0) is
when "0000" => -- subb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "0001" => -- cmpb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sub8;
cc_ctrl <= load_cc;
when "0010" => -- sbcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_sbc;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "0011" => -- addd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
when "0100" => -- andb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "0101" => -- bitb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_and;
cc_ctrl <= load_cc;
when "0110" => -- ldab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld8;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "0111" => -- stab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st8;
cc_ctrl <= load_cc;
when "1000" => -- eorb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_eor;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "1001" => -- adcb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_adc;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "1010" => -- orab
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ora;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "1011" => -- addb
left_ctrl <= accb_left;
right_ctrl <= md_right;
alu_ctrl <= alu_add8;
cc_ctrl <= load_cc;
accb_ctrl <= load_accb;
when "1100" => -- ldd
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
acca_ctrl <= load_hi_acca;
accb_ctrl <= load_accb;
when "1101" => -- std
left_ctrl <= accd_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
when "1110" => -- ldu
case pre_code is
when "00010000" => -- page 2 -- lds
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
sp_ctrl <= load_sp;
when others => -- page 1 -- ldu
left_ctrl <= up_left;
right_ctrl <= md_right;
alu_ctrl <= alu_ld16;
cc_ctrl <= load_cc;
up_ctrl <= load_up;
end case;
when "1111" =>
case pre_code is
when "00010000" => -- page 2 -- sts
left_ctrl <= sp_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
when others => -- page 1 -- stu
left_ctrl <= up_left;
right_ctrl <= md_right;
alu_ctrl <= alu_st16;
cc_ctrl <= load_cc;
end case;
when others =>
null;
end case;
when others =>
null;
end case;
end if; -- first instruction cycle (fic)
lic_out <= lic;
end process;
end rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncrambw
-- File: syncrambw.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Description: Synchronous 1-port ram with 8-bit write strobes
-- and tech selection
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allmem.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
entity syncrambw is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
testen : integer := 0; custombits: integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits-1 downto 0);
datain : in std_logic_vector (dbits-1 downto 0);
dataout : out std_logic_vector (dbits-1 downto 0);
enable : in std_logic_vector (dbits/8-1 downto 0);
write : in std_logic_vector (dbits/8-1 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none
);
end;
architecture rtl of syncrambw is
constant nctrl : integer := abits + (TESTIN_WIDTH-2) + 2*dbits/8;
signal dataoutx, databp, testdata : std_logic_vector((dbits -1) downto 0);
constant SCANTESTBP : boolean := (testen = 1) and syncram_add_scan_bypass(tech)=1;
signal xenable, xwrite : std_logic_vector(dbits/8-1 downto 0);
signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0);
begin
xenable <= enable when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
xwrite <= write when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
sbw : if has_srambw(tech) = 1 generate
-- RAM bypass for scan
scanbp : if SCANTESTBP generate
comb : process (address, datain, enable, write, testin)
variable tmp : std_logic_vector((dbits -1) downto 0);
variable ctrlsigs : std_logic_vector((nctrl -1) downto 0);
begin
ctrlsigs := testin(TESTIN_WIDTH-3 downto 0) & write & enable & address;
tmp := datain;
for i in 0 to nctrl-1 loop
tmp(i mod dbits) := tmp(i mod dbits) xor ctrlsigs(i);
end loop;
testdata <= tmp;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
databp <= testdata;
end if;
end process;
dmuxout : for i in 0 to dbits-1 generate
x0: grmux2 generic map (tech)
port map (dataoutx(i), databp(i), testin(TESTIN_WIDTH-1), dataout(i));
end generate;
end generate;
noscanbp : if not SCANTESTBP generate dataout <= dataoutx; end generate;
n2x : if tech = easic45 generate
x0 : n2x_syncram_be generic map (abits, dbits)
port map (clk, address, datain, dataout, xenable, xwrite);
end generate;
-- pragma translate_off
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "syncrambw: " & tost(2**abits) & "x" & tost(dbits) &
" (" & tech_table(tech) & ")"
severity note;
wait;
end process;
end generate;
-- pragma translate_on
end generate;
nosbw : if has_srambw(tech) = 0 generate
rx : for i in 0 to dbits/8-1 generate
x0 : syncram generic map (tech, abits, 8, testen, custombits)
port map (clk, address, datain(i*8+7 downto i*8),
dataoutx(i*8+7 downto i*8), enable(i), write(i), testin
);
end generate;
dataout <= dataoutx;
end generate;
custominx <= (others => '0');
nocust: if has_srambw(tech)=0 or syncram_has_customif(tech)=0 generate
customoutx <= (others => '0');
end generate;
end;
|
entity g is
end entity;
architecture test of g is
constant c : integer := 5;
signal x : integer;
signal b : bit_vector(1 to 5);
begin
g1: if true generate -- OK
begin
x <= 5;
end generate;
g2: if x generate -- Error
begin
end generate;
g3: if false generate -- OK
signal y : integer;
begin
y <= x;
end generate;
g4: if false generate
y <= 5; -- Error
end generate;
g5: for i in 1 to 5 generate -- OK
b(i) <= '1';
end generate;
g6: for x in b'range generate -- OK
constant k : bit := '1';
begin
b(x) <= k;
end generate;
g7: for x in b'range generate
alias a is b(x); -- OK
begin
a <= '1';
end generate;
g8: if x > 4 generate -- Error
end generate;
g9: for i in 1 to x generate -- Error
end generate;
g10: for i in integer (-4) to integer (-1) generate -- OK
end generate;
end architecture;
|
entity g is
end entity;
architecture test of g is
constant c : integer := 5;
signal x : integer;
signal b : bit_vector(1 to 5);
begin
g1: if true generate -- OK
begin
x <= 5;
end generate;
g2: if x generate -- Error
begin
end generate;
g3: if false generate -- OK
signal y : integer;
begin
y <= x;
end generate;
g4: if false generate
y <= 5; -- Error
end generate;
g5: for i in 1 to 5 generate -- OK
b(i) <= '1';
end generate;
g6: for x in b'range generate -- OK
constant k : bit := '1';
begin
b(x) <= k;
end generate;
g7: for x in b'range generate
alias a is b(x); -- OK
begin
a <= '1';
end generate;
g8: if x > 4 generate -- Error
end generate;
g9: for i in 1 to x generate -- Error
end generate;
g10: for i in integer (-4) to integer (-1) generate -- OK
end generate;
end architecture;
|
entity g is
end entity;
architecture test of g is
constant c : integer := 5;
signal x : integer;
signal b : bit_vector(1 to 5);
begin
g1: if true generate -- OK
begin
x <= 5;
end generate;
g2: if x generate -- Error
begin
end generate;
g3: if false generate -- OK
signal y : integer;
begin
y <= x;
end generate;
g4: if false generate
y <= 5; -- Error
end generate;
g5: for i in 1 to 5 generate -- OK
b(i) <= '1';
end generate;
g6: for x in b'range generate -- OK
constant k : bit := '1';
begin
b(x) <= k;
end generate;
g7: for x in b'range generate
alias a is b(x); -- OK
begin
a <= '1';
end generate;
g8: if x > 4 generate -- Error
end generate;
g9: for i in 1 to x generate -- Error
end generate;
g10: for i in integer (-4) to integer (-1) generate -- OK
end generate;
end architecture;
|
entity g is
end entity;
architecture test of g is
constant c : integer := 5;
signal x : integer;
signal b : bit_vector(1 to 5);
begin
g1: if true generate -- OK
begin
x <= 5;
end generate;
g2: if x generate -- Error
begin
end generate;
g3: if false generate -- OK
signal y : integer;
begin
y <= x;
end generate;
g4: if false generate
y <= 5; -- Error
end generate;
g5: for i in 1 to 5 generate -- OK
b(i) <= '1';
end generate;
g6: for x in b'range generate -- OK
constant k : bit := '1';
begin
b(x) <= k;
end generate;
g7: for x in b'range generate
alias a is b(x); -- OK
begin
a <= '1';
end generate;
g8: if x > 4 generate -- Error
end generate;
g9: for i in 1 to x generate -- Error
end generate;
g10: for i in integer (-4) to integer (-1) generate -- OK
end generate;
end architecture;
|
entity g is
end entity;
architecture test of g is
constant c : integer := 5;
signal x : integer;
signal b : bit_vector(1 to 5);
begin
g1: if true generate -- OK
begin
x <= 5;
end generate;
g2: if x generate -- Error
begin
end generate;
g3: if false generate -- OK
signal y : integer;
begin
y <= x;
end generate;
g4: if false generate
y <= 5; -- Error
end generate;
g5: for i in 1 to 5 generate -- OK
b(i) <= '1';
end generate;
g6: for x in b'range generate -- OK
constant k : bit := '1';
begin
b(x) <= k;
end generate;
g7: for x in b'range generate
alias a is b(x); -- OK
begin
a <= '1';
end generate;
g8: if x > 4 generate -- Error
end generate;
g9: for i in 1 to x generate -- Error
end generate;
g10: for i in integer (-4) to integer (-1) generate -- OK
end generate;
end architecture;
|
library verilog;
use verilog.vl_types.all;
entity controller_vlg_check_tst is
port(
enable_change_reg: in vl_logic;
enable_total_reg: in vl_logic;
price : in vl_logic_vector(7 downto 0);
register_rst : in vl_logic;
reset_system : in vl_logic;
soda_Dispense : in vl_logic_vector(1 downto 0);
value_Coin : in vl_logic_vector(7 downto 0);
sampler_rx : in vl_logic
);
end controller_vlg_check_tst;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "imotor_receiver"
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.imotor_module_pkg.all;
-------------------------------------------------------------------------------
entity imotor_receiver_tb is
end entity imotor_receiver_tb;
-------------------------------------------------------------------------------
architecture behavourial of imotor_receiver_tb is
-- component generics
constant DATA_WORDS : positive := 2;
constant DATA_WIDTH : positive := 16;
-- Component ports
-- clock
signal clk : std_logic := '1';
signal clock_s : imotor_timer_type;
signal data_rx_in_s : std_logic_vector(7 downto 0) := (others => '0');
signal imotor_output_s : imotor_output_type(1 downto 0);
signal ready_rx_s : std_logic := '0';
begin -- architecture behavourial
-- component instantiation
imotor_receiver_1 : entity work.imotor_receiver
generic map (
DATA_WORDS => DATA_WORDS,
DATA_WIDTH => DATA_WIDTH)
port map (
data_out_p => imotor_output_s,
data_in_p => data_rx_in_s,
parity_error_in_p => '0', -- parity_error_in_p,
ready_in_p => ready_rx_s,
clk => clk);
imotor_timer_1 : imotor_timer
generic map (
CLOCK => 50E6,
BAUD => 1E6,
SEND_FREQUENCY => 1E5)
port map (
clock_out_p => clock_s,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
variable test_vector : unsigned(7 downto 0) := x"01";
begin
while true loop
-- Start byte of slave
wait until clock_s.rx = '1';
data_rx_in_s <= x"51";
ready_rx_s <= '1';
wait until clk = '1';
ready_rx_s <= '0';
-- Four data bytes
for ii in 0 to 3 loop
wait until clock_s.rx = '1';
data_rx_in_s <= std_logic_vector(test_vector);
test_vector := test_vector + x"22";
ready_rx_s <= '1';
wait until clk = '1';
ready_rx_s <= '0';
end loop; -- ii
-- End Byte
wait until clock_s.rx = '1';
data_rx_in_s <= x"A1";
ready_rx_s <= '1';
wait until clk = '1';
ready_rx_s <= '0';
-- Next Message, after a small pause
wait until clock_s.rx = '1';
wait until clock_s.rx = '0';
wait until clock_s.rx = '1';
wait until clock_s.rx = '0';
end loop;
wait until false;
end process WaveGen_Proc;
end architecture behavourial;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "imotor_receiver"
-------------------------------------------------------------------------------
-- Author : strongly-typed
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 strongly-typed
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.imotor_module_pkg.all;
-------------------------------------------------------------------------------
entity imotor_receiver_tb is
end entity imotor_receiver_tb;
-------------------------------------------------------------------------------
architecture behavourial of imotor_receiver_tb is
-- component generics
constant DATA_WORDS : positive := 2;
constant DATA_WIDTH : positive := 16;
-- Component ports
-- clock
signal clk : std_logic := '1';
signal clock_s : imotor_timer_type;
signal data_rx_in_s : std_logic_vector(7 downto 0) := (others => '0');
signal imotor_output_s : imotor_output_type(1 downto 0);
signal ready_rx_s : std_logic := '0';
begin -- architecture behavourial
-- component instantiation
imotor_receiver_1 : entity work.imotor_receiver
generic map (
DATA_WORDS => DATA_WORDS,
DATA_WIDTH => DATA_WIDTH)
port map (
data_out_p => imotor_output_s,
data_in_p => data_rx_in_s,
parity_error_in_p => '0', -- parity_error_in_p,
ready_in_p => ready_rx_s,
clk => clk);
imotor_timer_1 : imotor_timer
generic map (
CLOCK => 50E6,
BAUD => 1E6,
SEND_FREQUENCY => 1E5)
port map (
clock_out_p => clock_s,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
variable test_vector : unsigned(7 downto 0) := x"01";
begin
while true loop
-- Start byte of slave
wait until clock_s.rx = '1';
data_rx_in_s <= x"51";
ready_rx_s <= '1';
wait until clk = '1';
ready_rx_s <= '0';
-- Four data bytes
for ii in 0 to 3 loop
wait until clock_s.rx = '1';
data_rx_in_s <= std_logic_vector(test_vector);
test_vector := test_vector + x"22";
ready_rx_s <= '1';
wait until clk = '1';
ready_rx_s <= '0';
end loop; -- ii
-- End Byte
wait until clock_s.rx = '1';
data_rx_in_s <= x"A1";
ready_rx_s <= '1';
wait until clk = '1';
ready_rx_s <= '0';
-- Next Message, after a small pause
wait until clock_s.rx = '1';
wait until clock_s.rx = '0';
wait until clock_s.rx = '1';
wait until clock_s.rx = '0';
end loop;
wait until false;
end process WaveGen_Proc;
end architecture behavourial;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
CONSTANT rd_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 36
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
CONSTANT rd_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 36
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
CONSTANT rd_clk_period_by_2 : TIME := 24 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 110 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 36
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1390.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p04n03i01390ent IS
END c08s05b00x00p04n03i01390ent;
ARCHITECTURE c08s05b00x00p04n03i01390arch OF c08s05b00x00p04n03i01390ent IS
BEGIN
TESTING: PROCESS
variable A : integer := 0;
variable B : integer := 0;
variable C : integer := 1;
variable D : integer := 2;
type array_of_ints is array (Positive range <>) of integer;
BEGIN
(A,B) := array_of_ints'(C,D);
assert NOT( (A=1) and (B=2) )
report "***PASSED TEST: c08s05b00x00p04n03i01390"
severity NOTE;
assert ( (A=1) and (B=2) )
report "***FAILED TEST: c08s05b00x00p04n03i01390 - Each element association of the aggregate must be a locally static name that denotes a variable"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p04n03i01390arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1390.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p04n03i01390ent IS
END c08s05b00x00p04n03i01390ent;
ARCHITECTURE c08s05b00x00p04n03i01390arch OF c08s05b00x00p04n03i01390ent IS
BEGIN
TESTING: PROCESS
variable A : integer := 0;
variable B : integer := 0;
variable C : integer := 1;
variable D : integer := 2;
type array_of_ints is array (Positive range <>) of integer;
BEGIN
(A,B) := array_of_ints'(C,D);
assert NOT( (A=1) and (B=2) )
report "***PASSED TEST: c08s05b00x00p04n03i01390"
severity NOTE;
assert ( (A=1) and (B=2) )
report "***FAILED TEST: c08s05b00x00p04n03i01390 - Each element association of the aggregate must be a locally static name that denotes a variable"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p04n03i01390arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1390.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p04n03i01390ent IS
END c08s05b00x00p04n03i01390ent;
ARCHITECTURE c08s05b00x00p04n03i01390arch OF c08s05b00x00p04n03i01390ent IS
BEGIN
TESTING: PROCESS
variable A : integer := 0;
variable B : integer := 0;
variable C : integer := 1;
variable D : integer := 2;
type array_of_ints is array (Positive range <>) of integer;
BEGIN
(A,B) := array_of_ints'(C,D);
assert NOT( (A=1) and (B=2) )
report "***PASSED TEST: c08s05b00x00p04n03i01390"
severity NOTE;
assert ( (A=1) and (B=2) )
report "***FAILED TEST: c08s05b00x00p04n03i01390 - Each element association of the aggregate must be a locally static name that denotes a variable"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p04n03i01390arch;
|
library verilog;
use verilog.vl_types.all;
entity Servo_Rom is
generic(
ADDR_LEN : integer := 8;
DATA_LEN : integer := 13
);
port(
clock : in vl_logic;
address : in vl_logic_vector;
data : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of ADDR_LEN : constant is 1;
attribute mti_svvh_generic_type of DATA_LEN : constant is 1;
end Servo_Rom;
|
entity record34 is
end entity;
architecture test of record34 is
type rec is record
x : bit_vector;
y : natural;
end record;
type rec_array is array (natural range <>) of rec;
type wrapper is record
f : rec_array(1 to 3)(x(1 to 2));
end record;
signal s : wrapper;
begin
p1: process is
begin
s.f(1) <= (x => "10", y => 1);
wait for 1 ns;
assert s.f = (1 => ("10", 1), 2 to 3 => ("00", 0));
s.f(2).x(1) <= '1';
wait for 1 ns;
assert s.f = (1 => ("10", 1), 2 => ("10", 0), 3 => ("00", 0));
wait;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1824.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s01b00x00p08n01i01824pkg is
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
constant bus_width : small_int := 7;
end c07s01b00x00p08n01i01824pkg;
use work.c07s01b00x00p08n01i01824pkg.all;
entity c07s01b00x00p08n01i01824ent_a is
port ( signal in_bus : in cmd_bus (0 to bus_width);
signal out_bus : out cmd_bus (0 to bus_width));
end c07s01b00x00p08n01i01824ent_a;
architecture c07s01b00x00p08n01i01824arch_a of c07s01b00x00p08n01i01824ent_a is
begin
end c07s01b00x00p08n01i01824arch_a;
use work.c07s01b00x00p08n01i01824pkg.all;
ENTITY c07s01b00x00p08n01i01824ent IS
END c07s01b00x00p08n01i01824ent;
ARCHITECTURE c07s01b00x00p08n01i01824arch OF c07s01b00x00p08n01i01824ent IS
signal ibus, obus : cmd_bus(small_int);
component test
port ( signal in_bus : in cmd_bus (0 to small_int(bus_width - 1));
signal out_bus : out cmd_bus (0 to small_int(bus_width - 1)));
end component;
for err : test use entity work.c07s01b00x00p08n01i01824ent_a(c07s01b00x00p08n01i01824arch_a);
BEGIN
err : test port map ( ibus, small_int ); -- type name illegal here
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01824 - Type names are not permitted as primaries in a component instantiation port map statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01824arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1824.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s01b00x00p08n01i01824pkg is
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
constant bus_width : small_int := 7;
end c07s01b00x00p08n01i01824pkg;
use work.c07s01b00x00p08n01i01824pkg.all;
entity c07s01b00x00p08n01i01824ent_a is
port ( signal in_bus : in cmd_bus (0 to bus_width);
signal out_bus : out cmd_bus (0 to bus_width));
end c07s01b00x00p08n01i01824ent_a;
architecture c07s01b00x00p08n01i01824arch_a of c07s01b00x00p08n01i01824ent_a is
begin
end c07s01b00x00p08n01i01824arch_a;
use work.c07s01b00x00p08n01i01824pkg.all;
ENTITY c07s01b00x00p08n01i01824ent IS
END c07s01b00x00p08n01i01824ent;
ARCHITECTURE c07s01b00x00p08n01i01824arch OF c07s01b00x00p08n01i01824ent IS
signal ibus, obus : cmd_bus(small_int);
component test
port ( signal in_bus : in cmd_bus (0 to small_int(bus_width - 1));
signal out_bus : out cmd_bus (0 to small_int(bus_width - 1)));
end component;
for err : test use entity work.c07s01b00x00p08n01i01824ent_a(c07s01b00x00p08n01i01824arch_a);
BEGIN
err : test port map ( ibus, small_int ); -- type name illegal here
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01824 - Type names are not permitted as primaries in a component instantiation port map statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01824arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1824.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c07s01b00x00p08n01i01824pkg is
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
constant bus_width : small_int := 7;
end c07s01b00x00p08n01i01824pkg;
use work.c07s01b00x00p08n01i01824pkg.all;
entity c07s01b00x00p08n01i01824ent_a is
port ( signal in_bus : in cmd_bus (0 to bus_width);
signal out_bus : out cmd_bus (0 to bus_width));
end c07s01b00x00p08n01i01824ent_a;
architecture c07s01b00x00p08n01i01824arch_a of c07s01b00x00p08n01i01824ent_a is
begin
end c07s01b00x00p08n01i01824arch_a;
use work.c07s01b00x00p08n01i01824pkg.all;
ENTITY c07s01b00x00p08n01i01824ent IS
END c07s01b00x00p08n01i01824ent;
ARCHITECTURE c07s01b00x00p08n01i01824arch OF c07s01b00x00p08n01i01824ent IS
signal ibus, obus : cmd_bus(small_int);
component test
port ( signal in_bus : in cmd_bus (0 to small_int(bus_width - 1));
signal out_bus : out cmd_bus (0 to small_int(bus_width - 1)));
end component;
for err : test use entity work.c07s01b00x00p08n01i01824ent_a(c07s01b00x00p08n01i01824arch_a);
BEGIN
err : test port map ( ibus, small_int ); -- type name illegal here
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01824 - Type names are not permitted as primaries in a component instantiation port map statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01824arch;
|
--==============================================================================
-- File: mux2_to_1.vhd
-- Author: Pietro Lorefice
--==============================================================================
-- Description:
-- 2-to-1 multiplexer
--
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
entity mux2_to_1 is
generic (
W : integer
);
port (
a : in std_logic_vector(W-1 downto 0);
b : in std_logic_vector(W-1 downto 0);
sel : in std_logic;
q : out std_logic_vector(W-1 downto 0)
);
end entity mux2_to_1;
architecture comb of mux2_to_1 is
begin
q <= a when sel = '0' else
b;
end architecture comb;
|
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Lbz/V00izw==
`protect end_protected
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:19:59 10/31/2013
-- Design Name:
-- Module Name: D:/AY1314/CG3207/Lab3/MEM_TEST.vhd
-- Project Name: Lab3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: DataMemory
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY MEM_TEST IS
END MEM_TEST;
ARCHITECTURE behavior OF MEM_TEST IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT DataMemory
PORT(
CLK : IN std_logic;
RESET : IN std_logic;
MEM_MemWrite : IN std_logic;
MEM_MemToReg : IN std_logic;
MEM_MemRead : IN std_logic;
MEM_Branch : IN std_logic;
MEM_OVF : IN std_logic;
MEM_Zero : IN std_logic;
MEM_ALU_Result : IN std_logic_vector(31 downto 0);
MEM_BEQ_Addr : IN std_logic_vector(31 downto 0);
MEM_Data2 : IN std_logic_vector(31 downto 0);
MEM_REG_WriteAddr : IN std_logic_vector(4 downto 0);
WB_PCSrc : OUT std_logic;
WB_Data : OUT std_logic_vector(31 downto 0);
WB_ALU_Result : OUT std_logic_vector(31 downto 0);
WB_BEQ_Addr : OUT std_logic_vector(31 downto 0);
WB_REG_WriteAddr : OUT std_logic_vector(4 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RESET : std_logic := '0';
signal MEM_MemWrite : std_logic := '0';
signal MEM_MemToReg : std_logic := '0';
signal MEM_MemRead : std_logic := '0';
signal MEM_Branch : std_logic := '0';
signal MEM_OVF : std_logic := '0';
signal MEM_Zero : std_logic := '0';
signal MEM_ALU_Result : std_logic_vector(31 downto 0) := (others => '0');
signal MEM_BEQ_Addr : std_logic_vector(31 downto 0) := (others => '0');
signal MEM_Data2 : std_logic_vector(31 downto 0) := (others => '0');
signal MEM_REG_WriteAddr : std_logic_vector(4 downto 0) := (others => '0');
--Outputs
signal WB_PCSrc : std_logic;
signal WB_Data : std_logic_vector(31 downto 0);
signal WB_ALU_Result : std_logic_vector(31 downto 0);
signal WB_BEQ_Addr : std_logic_vector(31 downto 0);
signal WB_REG_WriteAddr : std_logic_vector(4 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: DataMemory PORT MAP (
CLK => CLK,
RESET => RESET,
MEM_MemWrite => MEM_MemWrite,
MEM_MemToReg => MEM_MemToReg,
MEM_MemRead => MEM_MemRead,
MEM_Branch => MEM_Branch,
MEM_OVF => MEM_OVF,
MEM_Zero => MEM_Zero,
MEM_ALU_Result => MEM_ALU_Result,
MEM_BEQ_Addr => MEM_BEQ_Addr,
MEM_Data2 => MEM_Data2,
MEM_REG_WriteAddr => MEM_REG_WriteAddr,
WB_PCSrc => WB_PCSrc,
WB_Data => WB_Data,
WB_ALU_Result => WB_ALU_Result,
WB_BEQ_Addr => WB_BEQ_Addr,
WB_REG_WriteAddr => WB_REG_WriteAddr
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for CLK_period;
-- insert stimulus here
-- read from address 0x4
MEM_MemRead <= '1';
MEM_MemWrite <= '0';
MEM_ALU_Result <= X"00000004";
wait until rising_edge(CLK);
-- write 0xe to address 0x4
MEM_MemRead <= '0';
MEM_MemWrite <= '1';
MEM_ALU_Result <= X"00000004";
MEM_Data2 <= X"0000000E";
wait until rising_edge(CLK);
-- read again from address 0x4
MEM_MemRead <= '1';
MEM_MemWrite <= '0';
MEM_ALU_Result <= X"00000004";
wait;
end process;
END;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
-- OR1KND in-order 5-stage minimal simulator
entity cpu_or1knd_i5_min_sim_top is
generic (options_filename : string := "STD_INPUT");
end;
|
-- This is Package STANDARD as defined in the VHDL 1992 Language Reference Manual.
package standard is
type boolean is (false,true);
type bit is ('0', '1');
type character is (
nul, soh, stx, etx, eot, enq, ack, bel,
bs, ht, lf, vt, ff, cr, so, si,
dle, dc1, dc2, dc3, dc4, nak, syn, etb,
can, em, sub, esc, fsp, gsp, rsp, usp,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'A', 'B', 'C', 'D', 'E', 'F', 'G',
'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W',
'X', 'Y', 'Z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', del,
c128, c129, c130, c131, c132, c133, c134, c135,
c136, c137, c138, c139, c140, c141, c142, c143,
c144, c145, c146, c147, c148, c149, c150, c151,
c152, c153, c154, c155, c156, c157, c158, c159,
-- the character code for 160 is there (NBSP),
-- but prints as no char
' ', '¡', '¢', '£', '¤', '¥', '¦', '§',
'¨', '©', 'ª', '«', '¬', '', '®', '¯',
'°', '±', '²', '³', '´', 'µ', '¶', '·',
'¸', '¹', 'º', '»', '¼', '½', '¾', '¿',
'À', 'Á', 'Â', 'Ã', 'Ä', 'Å', 'Æ', 'Ç',
'È', 'É', 'Ê', 'Ë', 'Ì', 'Í', 'Î', 'Ï',
'Ð', 'Ñ', 'Ò', 'Ó', 'Ô', 'Õ', 'Ö', '×',
'Ø', 'Ù', 'Ú', 'Û', 'Ü', 'Ý', 'Þ', 'ß',
'à', 'á', 'â', 'ã', 'ä', 'å', 'æ', 'ç',
'è', 'é', 'ê', 'ë', 'ì', 'í', 'î', 'ï',
'ð', 'ñ', 'ò', 'ó', 'ô', 'õ', 'ö', '÷',
'ø', 'ù', 'ú', 'û', 'ü', 'ý', 'þ', 'ÿ' );
type severity_level is (note, warning, error, failure);
type integer is range -2147483647 to 2147483647;
type real is range -1.0E308 to 1.0E308;
type time is range -2147483647 to 2147483647
units
fs;
ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
ms = 1000 us;
sec = 1000 ms;
min = 60 sec;
hr = 60 min;
end units;
subtype delay_length is time range 0 fs to time'high;
impure function now return delay_length;
subtype natural is integer range 0 to integer'high;
subtype positive is integer range 1 to integer'high;
type string is array (positive range <>) of character;
type bit_vector is array (natural range <>) of bit;
type file_open_kind is (
read_mode,
write_mode,
append_mode);
type file_open_status is (
open_ok,
status_error,
name_error,
mode_error);
attribute foreign : string;
end standard;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:32:53 04/14/2014
-- Design Name:
-- Module Name: BoxDisplay - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity BoxDisplay is
Port ( pixel_x : in STD_LOGIC_VECTOR (9 downto 0);
pixel_y : in STD_LOGIC_VECTOR (9 downto 0);
boxValue : in STD_LOGIC_VECTOR (15 downto 0);
rgbOut : out STD_LOGIC_VECTOR (7 downto 0);
drawOutput : out STD_LOGIC);
end BoxDisplay;
architecture Behavioral of BoxDisplay is
signal drawBox : UNSIGNED(5 downto 0);
signal drawNumber : STD_LOGIC;
begin
end Behavioral;
|
--------------------------------------------------------------------------------------------------
-- FIR Tap
--------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
--------------------------------------------------------------------------------------------------
-- PACKAGE
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.dsp_pkg.all;
package fir_tap_pkg is
--FIR tap component declaration
component fir_tap is
port( clk : in std_logic;
rst : in std_logic;
coef : in coefficient;
sig_in : in sig;
sig_out : out sig;
sum_in : in fir_sig;
sum_out : out fir_sig);
end component;
end package;
--------------------------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_pkg.all;
--This entity represents a single tap in a FIR filter. The taps are designed to implement a
--cascade adder allowing for chaining an indefinite (tho definitely finite) number of taps.
entity fir_tap is
port( clk : in std_logic;
rst : in std_logic;
coef : in coefficient;
sig_in : in sig;
sig_out : out sig;
sum_in : in fir_sig;
sum_out : out fir_sig);
end fir_tap;
--------------------------------------------------------------------------------------------------
-- ARCHITECTURE (behavioral)
--------------------------------------------------------------------------------------------------
architecture behave of fir_tap is
signal sig_delay : sig_array(1 to 2) := (others => (others => '0'));
signal product : fir_sig := (others => '0');
begin
--delay the input signal
delay_sig : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
sig_delay <= (others => (others => '0'));
else
sig_delay(1) <= sig_in;
sig_delay(2) <= sig_delay(1);
end if;
end if;
end process;
sig_out <= sig_delay(2);
--multiply the signal to the tap coefficient
multiply : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
product <= (others => '0');
else
product <= resize(sig_delay(2) * coef, NUM_FIR_BITS);
end if;
end if;
end process;
--update the sum
update_sum : process(clk)
begin
if(rising_edge(clk)) then
if(rst = '1') then
sum_out <= (others => '0');
else
sum_out <= sum_in + product;
end if;
end if;
end process;
end behave;
|
-- Automatically generated: write_netlist -wrapapp -vhdl -architecture reconflogic-wrapslowadt7410-a.vhd
architecture WrapSlowADT7410 of MyReconfigLogic is
component CfgIntf
generic (
-- Number of configuration chains
NumCfgs : integer := 3;
BaseAddr : integer := 16#0180#
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
-- OpenMSP430 Interface
PerAddr_i : in std_logic_vector(13 downto 0);
PerDIn_i : in std_logic_vector(15 downto 0);
PerDOut_o : out std_logic_vector(15 downto 0);
PerWr_i : in std_logic_vector(1 downto 0);
PerEn_i : in std_logic;
CfgClk_o : out std_logic_vector(NumCfgs-1 downto 0);
CfgMode_o : out std_logic;
CfgShift_o : out std_logic_vector(NumCfgs-1 downto 0);
CfgDataOut_o : out std_logic;
CfgDataIn_i : in std_logic_vector(NumCfgs-1 downto 0)
);
end component;
component ParamIntf
generic (
WrAddrWidth : integer range 1 to 15 := 4;
RdAddrWidth : integer range 1 to 15 := 4;
BaseAddr : integer := 16#0180#
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
-- OpenMSP430 Interface
PerAddr_i : in std_logic_vector(13 downto 0);
PerDIn_i : in std_logic_vector(15 downto 0);
PerDOut_o : out std_logic_vector(15 downto 0);
PerWr_i : in std_logic_vector(1 downto 0);
PerEn_i : in std_logic;
-- Param Out
ParamWrAddr_o : out std_logic_vector(WrAddrWidth-1 downto 0);
ParamWrData_o : out std_logic_vector(15 downto 0);
ParamWr_o : out std_logic;
-- Param In
ParamRdAddr_o : out std_logic_vector(RdAddrWidth-1 downto 0);
ParamRdData_i : in std_logic_vector(15 downto 0)
);
end component;
component ParamOutReg
generic (
Width : integer := 16
);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
ParamWrData_i : in std_logic_vector(Width-1 downto 0);
Param_o : out std_logic_vector(Width-1 downto 0)
);
end component;
component SlowADT7410
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
CpuIntr_o : out std_logic;
I2C_ReceiveSend_n_o : out std_logic;
I2C_ReadCount_o : out std_logic_vector(7 downto 0);
I2C_StartProcess_o : out std_logic;
I2C_Busy_i : in std_logic;
I2C_FIFOReadNext_o : out std_logic;
I2C_FIFOWrite_o : out std_logic;
I2C_Data_o : out std_logic_vector(7 downto 0);
I2C_Data_i : in std_logic_vector(7 downto 0);
I2C_Error_i : in std_logic;
PeriodCounterPresetH_i : in std_logic_vector(15 downto 0);
PeriodCounterPresetL_i : in std_logic_vector(15 downto 0);
SensorValue_o : out std_logic_vector(15 downto 0);
Threshold_i : in std_logic_vector(15 downto 0);
WaitCounterPresetH_i : in std_logic_vector(15 downto 0);
WaitCounterPresetL_i : in std_logic_vector(15 downto 0)
);
end component;
signal I2C_ReadCount_s : std_logic_vector(7 downto 0);
signal PeriodCounterPresetH_s : std_logic_vector(15 downto 0);
signal PeriodCounterPresetL_s : std_logic_vector(15 downto 0);
signal SensorValue_s : std_logic_vector(15 downto 0);
signal Threshold_s : std_logic_vector(15 downto 0);
signal WaitCounterPresetH_s : std_logic_vector(15 downto 0);
signal WaitCounterPresetL_s : std_logic_vector(15 downto 0);
signal CfgClk_s : std_logic_vector(0 downto 0);
signal CfgMode_s : std_logic;
signal CfgShift_s : std_logic_vector(0 downto 0);
signal CfgDataOut_s : std_logic;
signal CfgDataIn_s : std_logic_vector(0 downto 0);
signal ParamWrAddr_s : std_logic_vector(2 downto 0);
signal ParamWrData_s : std_logic_vector(15 downto 0);
signal ParamWr_s : std_logic;
signal ParamRdAddr_s : std_logic_vector(0 downto 0);
signal ParamRdData_s : std_logic_vector(15 downto 0);
type Params_t is array(0 to 1) of std_logic_vector(15 downto 0);
signal Params_s : Params_t;
signal I2C_ErrAckParam_s : std_logic_vector(0 downto 0);
signal ParamI2C_Divider800Enable_s : std_logic;
signal ParamI2C_ErrAckParamEnable_s : std_logic;
signal ParamPeriodCounterPresetHEnable_s : std_logic;
signal ParamPeriodCounterPresetLEnable_s : std_logic;
signal ParamThresholdEnable_s : std_logic;
signal ParamWaitCounterPresetHEnable_s : std_logic;
signal ParamWaitCounterPresetLEnable_s : std_logic;
begin
-- Configuration Interface
CfgIntf_0: CfgIntf
generic map (
BaseAddr => 16#0180#,
NumCfgs => 1
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
PerAddr_i => PerAddr_i,
PerDIn_i => PerDIn_i,
PerDOut_o => CfgIntfDOut_o,
PerWr_i => PerWr_i,
PerEn_i => PerEn_i,
CfgClk_o => CfgClk_s,
CfgMode_o => CfgMode_s,
CfgShift_o => CfgShift_s,
CfgDataOut_o => CfgDataOut_s,
CfgDataIn_i => CfgDataIn_s
);
-- Parameterization Interface: 7 write addresses, 2 read addresses
ParamIntf_0: ParamIntf
generic map (
BaseAddr => 16#0188#,
WrAddrWidth => 3,
RdAddrWidth => 1
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
PerAddr_i => PerAddr_i,
PerDIn_i => PerDIn_i,
PerDOut_o => ParamIntfDOut_o,
PerWr_i => PerWr_i,
PerEn_i => PerEn_i,
ParamWrAddr_o => ParamWrAddr_s,
ParamWrData_o => ParamWrData_s,
ParamWr_o => ParamWr_s,
ParamRdAddr_o => ParamRdAddr_s,
ParamRdData_i => ParamRdData_s
);
SlowADT7410_0: SlowADT7410
port map (
I2C_Busy_i => I2C_Busy_i,
I2C_Data_o => I2C_DataIn_o,
I2C_Data_i => I2C_DataOut_i,
I2C_Error_i => I2C_Error_i,
I2C_FIFOReadNext_o => I2C_FIFOReadNext_o,
I2C_FIFOWrite_o => I2C_FIFOWrite_o,
I2C_ReadCount_o => I2C_ReadCount_s,
I2C_ReceiveSend_n_o => I2C_ReceiveSend_n_o,
I2C_StartProcess_o => I2C_StartProcess_o,
CpuIntr_o => ReconfModuleIRQs_o(0),
Enable_i => ReconfModuleIn_i(0),
Clk_i => Clk_i,
Reset_n_i => Reset_n_i,
PeriodCounterPresetH_i => PeriodCounterPresetH_s,
PeriodCounterPresetL_i => PeriodCounterPresetL_s,
SensorValue_o => SensorValue_s,
Threshold_i => Threshold_s,
WaitCounterPresetH_i => WaitCounterPresetH_s,
WaitCounterPresetL_i => WaitCounterPresetL_s
);
AdcDoConvert_o <= '0';
I2C_F100_400_n_o <= '1';
I2C_ReadCount_o <= I2C_ReadCount_s(3 downto 0);
Outputs_o(0) <= '0';
Outputs_o(1) <= '0';
Outputs_o(2) <= '0';
Outputs_o(3) <= '0';
Outputs_o(4) <= '0';
Outputs_o(5) <= '0';
Outputs_o(6) <= '0';
Outputs_o(7) <= '0';
ReconfModuleIRQs_o(1) <= '0';
ReconfModuleIRQs_o(2) <= '0';
ReconfModuleIRQs_o(3) <= '0';
ReconfModuleIRQs_o(4) <= '0';
SPI_CPHA_o <= '0';
SPI_CPOL_o <= '0';
SPI_DataIn_o <= "00000000";
SPI_LSBFE_o <= '0';
SPI_ReadNext_o <= '0';
SPI_SPPR_SPR_o <= "00000000";
SPI_Write_o <= '0';
ReconfModuleOut_o(0) <= '0';
ReconfModuleOut_o(1) <= '0';
ReconfModuleOut_o(2) <= '0';
ReconfModuleOut_o(3) <= '0';
ReconfModuleOut_o(4) <= '0';
ReconfModuleOut_o(5) <= '0';
ReconfModuleOut_o(6) <= '0';
ReconfModuleOut_o(7) <= '0';
-- just a fixed value for the config interface
CfgDataIn_s <= "0";
-- Param read address decoder
-- Synthesis: Accept undefined behavior if ParamRdAddr_s >= NumParams and
-- hope that the synthesis optimizes the MUX
-- Simulation: ModelSim complains "Fatal: (vsim-3421) Value x is out of range
-- 0 to n.", even during param write cycles, because ParamRdAddr has the
-- source as ParamWrAddr. Use the parameter "-noindexcheck" during
-- compilation ("vcom"). Simulation works fine then, but ModelSim generates
-- numerous "INTERNAL ERROR"s to stdout, which seem harmless.
ParamRdData_s <= Params_s(to_integer(unsigned(ParamRdAddr_s)));
ParamOutReg_I2C_Divider800: ParamOutReg
generic map (
Width => 16
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => I2C_Divider800_o,
Enable_i => ParamI2C_Divider800Enable_s,
ParamWrData_i => ParamWrData_s
);
ParamOutReg_I2C_ErrAckParam: ParamOutReg
generic map (
Width => 1
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => I2C_ErrAckParam_s,
Enable_i => ParamI2C_ErrAckParamEnable_s,
ParamWrData_i => ParamWrData_s(0 downto 0)
);
ParamOutReg_PeriodCounterPresetH: ParamOutReg
generic map (
Width => 16
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => PeriodCounterPresetH_s,
Enable_i => ParamPeriodCounterPresetHEnable_s,
ParamWrData_i => ParamWrData_s
);
ParamOutReg_PeriodCounterPresetL: ParamOutReg
generic map (
Width => 16
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => PeriodCounterPresetL_s,
Enable_i => ParamPeriodCounterPresetLEnable_s,
ParamWrData_i => ParamWrData_s
);
ParamOutReg_Threshold: ParamOutReg
generic map (
Width => 16
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => Threshold_s,
Enable_i => ParamThresholdEnable_s,
ParamWrData_i => ParamWrData_s
);
ParamOutReg_WaitCounterPresetH: ParamOutReg
generic map (
Width => 16
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => WaitCounterPresetH_s,
Enable_i => ParamWaitCounterPresetHEnable_s,
ParamWrData_i => ParamWrData_s
);
ParamOutReg_WaitCounterPresetL: ParamOutReg
generic map (
Width => 16
)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Param_o => WaitCounterPresetL_s,
Enable_i => ParamWaitCounterPresetLEnable_s,
ParamWrData_i => ParamWrData_s
);
I2C_ErrAckParam_o <= I2C_ErrAckParam_s(0);
-- Address $00
Params_s(0) <= "00000000" & I2C_Errors_i;
-- Address $01
Params_s(1) <= SensorValue_s;
-- Address $00
ParamI2C_Divider800Enable_s <= ParamWr_s when ParamWrAddr_s = "000" else
'0';
-- Address $01
ParamI2C_ErrAckParamEnable_s <= ParamWr_s when ParamWrAddr_s = "001" else
'0';
-- Address $02
ParamPeriodCounterPresetHEnable_s <= ParamWr_s when ParamWrAddr_s = "010" else
'0';
-- Address $03
ParamPeriodCounterPresetLEnable_s <= ParamWr_s when ParamWrAddr_s = "011" else
'0';
-- Address $04
ParamThresholdEnable_s <= ParamWr_s when ParamWrAddr_s = "100" else
'0';
-- Address $05
ParamWaitCounterPresetHEnable_s <= ParamWr_s when ParamWrAddr_s = "101" else
'0';
-- Address $06
ParamWaitCounterPresetLEnable_s <= ParamWr_s when ParamWrAddr_s = "110" else
'0';
end WrapSlowADT7410;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc994.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p08n03i00994ent IS
END c06s03b00x00p08n03i00994ent;
architecture a19a of c06s03b00x00p08n03i00994ent is
begin
end;
ARCHITECTURE c06s03b00x00p08n03i00994arch OF c06s03b00x00p08n03i00994ent IS
use work.a19a; --illegal
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c06s03b00x00p08n03i00994 - Expanded name is not allowed for an architectural body."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p08n03i00994arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc994.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p08n03i00994ent IS
END c06s03b00x00p08n03i00994ent;
architecture a19a of c06s03b00x00p08n03i00994ent is
begin
end;
ARCHITECTURE c06s03b00x00p08n03i00994arch OF c06s03b00x00p08n03i00994ent IS
use work.a19a; --illegal
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c06s03b00x00p08n03i00994 - Expanded name is not allowed for an architectural body."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p08n03i00994arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc994.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p08n03i00994ent IS
END c06s03b00x00p08n03i00994ent;
architecture a19a of c06s03b00x00p08n03i00994ent is
begin
end;
ARCHITECTURE c06s03b00x00p08n03i00994arch OF c06s03b00x00p08n03i00994ent IS
use work.a19a; --illegal
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c06s03b00x00p08n03i00994 - Expanded name is not allowed for an architectural body."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p08n03i00994arch;
|
-- Projeto MasterMind
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Bin7SegDecoder is
port( binInput : in std_logic_vector(3 downto 0);
decOut_n : out std_logic_vector(6 downto 0);
ledOut : out std_logic_vector(3 downto 0);
enable : in std_logic);
end Bin7SegDecoder;
-- Descodificador de BCD para decimal fornecido num guião com algumas alterações.
architecture Behavioral of Bin7SegDecoder is
begin
decOut_n <= "1111111" when enable='0' else
"1111001" when binInput="0001" else --1
"0100100" when binInput="0010" else --2
"0110000" when binInput="0011" else --3
"0011001" when binInput="0100" else --4
"0010010" when binInput="0101" else --5
"0000010" when binInput="0110" else --6
"1111000" when binInput="0111" else --7
"0000000" when binInput="1000" else --8
"0010000" when binInput="1001" else --9
"0001000" when binInput="1010" else --A
"0000011" when binInput="1011" else --B
"1000110" when binInput="1100" else --C
"0100001" when binInput="1101" else --D
"0000110" when binInput="1110" else --E
"1111111" when binInput="1111" else -- Nulo
"1000000"; --0
ledOut <= binInput;
end Behavioral; |
-------------------------------------------------------------------------------
-- Title : Testbench for design "ConfigRegister"
-- Project :
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.math_real.all;
use work.trfsmparts.all;
use work.tbfuncs.all;
-------------------------------------------------------------------------------
entity tb_ConfigRegister is
end tb_ConfigRegister;
-------------------------------------------------------------------------------
architecture behavior of tb_ConfigRegister is
constant CfgClkHalfPeriode : time := 100 ns;
constant CheckOutputDelay : time := 20 ns;
constant SetupNextInputDelay : time := 20 ns;
-- component generics
constant Width : integer range 1 to 256 := 29; -- prime number :-)
-- component ports
signal Reset_n_i : std_logic;
signal Output_o : std_logic_vector(Width-1 downto 0);
signal CfgMode_i : std_logic;
signal CfgClk_i : std_logic;
signal CfgShift_i : std_logic;
signal CfgDataIn_i : std_logic;
signal CfgDataOut_o : std_logic;
-- Configuration
---------------------------------------------------------------------------
-- shift in the config bit stream with LSB first, the ConfigRegister will
-- shift this from right to left (=MSB to LSB), so after everything is
-- shifted, the bits have the same order as setup above and as visible at
-- the screen.
procedure Configure (
constant NewBitStream : in std_logic_vector;
variable OldBitStream : out std_logic_vector;
signal CfgMode : out std_logic; -- TODO: remove this signal, not required here
signal CfgClk : out std_logic;
signal CfgDataIn : out std_logic;
signal CfgDataOut : in std_logic
) is
begin -- Configure
for i in 0 to NewBitStream'length-1 loop
CfgDataIn <= NewBitStream(i);
OldBitStream(i) := CfgDataOut;
CfgClk <= '1';
wait for CfgClkHalfPeriode;
CfgClk <= '0';
wait for CfgClkHalfPeriode;
end loop; -- i
end Configure;
-- purpose: Check the output of the ConfigRegister
procedure CheckOutput (
constant Nominal : in std_logic_vector(Width-1 downto 0);
signal Output_o : in std_logic_vector(Width-1 downto 0)
) is
begin -- CheckOutput
assert Output_o = Nominal report "Invalid output " & Vector2String(Output_o) & ", should be " & Vector2String(Nominal) severity error;
end CheckOutput;
-- purpose: Create a random bitstream
function CreateBitStream (
constant Width : natural;
constant S1 : positive;
constant S2 : positive
) return std_logic_vector is
variable CfgValue : std_logic_vector(Width-1 downto 0);
variable Seed1 : positive;
variable Seed2 : positive;
variable Rand : real;
begin -- CreateBitStream
Seed1 := S1;
Seed2 := S2;
for i in 0 to Width-1 loop
uniform(Seed1,Seed2,Rand);
CfgValue(i) := conv_std_logic_vector(integer(round(Rand)),1)(0);
end loop; -- i
return CfgValue;
end CreateBitStream;
begin -- behavior
-- component instantiation
DUT: ConfigRegister
generic map (
Width => Width)
port map (
Reset_n_i => Reset_n_i,
Output_o => Output_o,
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgDataIn_i,
CfgDataOut_o => CfgDataOut_o);
-- waveform generation
WaveGen_Proc: process
variable OutputA : std_logic_vector(Width-1 downto 0);
variable OutputB : std_logic_vector(Width-1 downto 0);
variable OutputC : std_logic_vector(Width-1 downto 0);
begin
CfgMode_i <= '0';
CfgClk_i <= '0';
CfgShift_i <= '0';
CfgDataIn_i <= '0';
---------------------------------------------------------------------------
-- Reset
---------------------------------------------------------------------------
Reset_n_i <= '1';
wait for 1 us;
Reset_n_i <= '0';
wait for 1 us;
Reset_n_i <= '1';
wait for 1 ns;
---------------------------------------------------------------------------
-- Action
---------------------------------------------------------------------------
-- all zero after reset
OutputA := (others => '0');
CheckOutput(OutputA,Output_o);
-- set CfgMode_i = '1', still the same value
CfgMode_i <= '1';
wait for CheckOutputDelay;
CheckOutput(OutputA,Output_o);
-- shift in the config bit stream without CfgShift_i, Output_o must stay the same
OutputB := CreateBitStream(Width,8395931,123456789);
Configure(OutputB,OutputC,CfgMode_i,CfgClk_i,CfgDataIn_i,CfgDataOut_o);
assert OutputC = OutputA report "Shifted out some bit stream " & Vector2String(OutputC) & ", should be " & Vector2String(OutputA) severity error;
CfgMode_i <= '0';
wait for CheckOutputDelay;
CheckOutput(OutputA,Output_o); -- should still be old value
CfgMode_i <= '1';
CfgShift_i <= '1'; -- now for real
-- shift in the config bit stream, Output_o must stay the same
Configure(OutputB,OutputC,CfgMode_i,CfgClk_i,CfgDataIn_i,CfgDataOut_o);
assert OutputC = OutputA report "Shifted out wrong bit stream " & Vector2String(OutputC) & ", should be " & Vector2String(OutputA) severity error;
CheckOutput(OutputA,Output_o);
-- set CfgMode_i = '0', new value
CfgMode_i <= '0';
wait for CheckOutputDelay;
CheckOutput(OutputB,Output_o);
-- assert CfgClk -> nothing should change
CfgClk_i <= '1';
wait for CfgClkHalfPeriode;
CheckOutput(OutputB,Output_o);
CfgClk_i <= '0';
wait for CfgClkHalfPeriode;
CheckOutput(OutputB,Output_o);
-- Reset => everything 0
Reset_n_i <= '0';
wait for 1 us;
CheckOutput(OutputA,Output_o);
Reset_n_i <= '1';
wait for 1 us;
CheckOutput(OutputA,Output_o);
-- shift in new bit stream
OutputB := CreateBitStream(Width,98765432,98765432);
CfgMode_i <= '1';
wait for CheckOutputDelay;
CheckOutput(OutputA,Output_o);
Configure(OutputB,OutputC,CfgMode_i,CfgClk_i,CfgDataIn_i,CfgDataOut_o);
assert OutputC = OutputA report "Shifted out wrong bit stream " & Vector2String(OutputC) & ", should be " & Vector2String(OutputA) severity error;
-- set CfgMode_i = '0', new value
CfgMode_i <= '0';
wait for CheckOutputDelay;
CheckOutput(OutputB,Output_o);
-- shift in new bit stream
OutputC := CreateBitStream(Width,178192753,1111122222);
CfgMode_i <= '1';
wait for CheckOutputDelay;
CheckOutput(OutputA,Output_o);
Configure(OutputC,OutputA,CfgMode_i,CfgClk_i,CfgDataIn_i,CfgDataOut_o);
-- check output
CfgMode_i <= '0';
wait for CheckOutputDelay;
CheckOutput(OutputC,Output_o);
-- check shifted out bits, must be the same as previous bit stream
assert OutputA = OutputB report "Shifted out wrong bit stream " & Vector2String(OutputC) & ", should be " & Vector2String(OutputA) severity error;
---------------------------------------------------------------------------
-- Simulation is finished
---------------------------------------------------------------------------
assert false
report "### simulation is finished ###"
severity failure;
end process WaveGen_Proc;
end behavior;
-------------------------------------------------------------------------------
configuration tb_ConfigRegister_behavior_cfg of tb_ConfigRegister is
for behavior
end for;
end tb_ConfigRegister_behavior_cfg;
-------------------------------------------------------------------------------
|
-- ********************************************************************
-- Actel Corporation Proprietary and Confidential
-- Copyright 2008 Actel Corporation. All rights reserved.
--
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
--
-- Description: CoreUART/ CoreUARTapb UART core
--
--
-- Revision Information:
-- Date Description
-- Jun09 Revision 4.1
-- Aug10 Revision 4.2
--
-- SVN Revision Information:
-- SVN $Revision: 8508 $
-- SVN $Date: 2009-06-15 16:49:49 -0700 (Mon, 15 Jun 2009) $
--
-- Resolved SARs
-- SAR Date Who Description
-- 20741 2Sep10 AS Increased baud rate by ensuring fifo ctrl runs off
-- sys clk (not baud clock). See note below.
-- Notes:
-- best viewed with tabstops set to "4"
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
entity CU_TOP_FPGA_UART_Clock_gen is
GENERIC (BAUD_VAL_FRCTN_EN : integer := 0;
SYNC_RESET : integer := 0);
port ( clk : in std_logic; -- system clock
reset_n : in std_logic; -- active low async reset
baud_val : in std_logic_vector(12 downto 0); -- value loaded into cntr
BAUD_VAL_FRACTION : in std_logic_vector(2 downto 0); -- fractional part of baud value
baud_clock : out std_logic; -- 16x baud clock pulse
xmit_pulse : out std_logic -- transmit pulse
);
end entity CU_TOP_FPGA_UART_Clock_gen;
architecture rtl of CU_TOP_FPGA_UART_Clock_gen is
signal baud_cntr : std_logic_vector(12 downto 0); -- 16x clock division counter reg.
signal baud_clock_int : std_logic; -- internal 16x baud clock pulse
signal xmit_clock : std_logic;
signal xmit_cntr : std_logic_vector(3 downto 0); -- baud tx counter reg.
signal baud_cntr_one : std_logic;
signal aresetn : std_logic;
signal sresetn : std_logic;
begin
aresetn <= '1' WHEN (SYNC_RESET=1) ELSE reset_n;
sresetn <= reset_n WHEN (SYNC_RESET=1) ELSE '1';
--------------------------------------------------
-- generate a x16 baud clock pulse
--------------------------------------------------
UG09:IF(BAUD_VAL_FRCTN_EN = 1) GENERATE
-- Add one cycle 1/8, 2/8, 3/8, 4/8, 5/8, 6/8, 7/8 of the time by freezing
-- baud_cntr for one cycle when count reaches 0 for certain xmit_cntr values.
-- xmit_cntr values are identifed by looking for bits of this counter
-- being certain combinations.
make_baud_cntr_one: process(clk,aresetn)
begin
if (aresetn = '0') then
baud_cntr_one <= '0';
elsif(clk'event and clk='1') then
if (sresetn = '0') then
baud_cntr_one <= '0';
else
if (baud_cntr = "0000000000001") then
baud_cntr_one <= '1';
else
baud_cntr_one <= '0';
end if;
end if;
end if;
end process make_baud_cntr_one;
make_baud_cntr1: process(clk, aresetn)
begin
if (aresetn = '0') then
baud_cntr <= "0000000000000";
baud_clock_int <= '0';
elsif(clk'event and clk='1') then
if (sresetn = '0') then
baud_cntr <= "0000000000000";
baud_clock_int <= '0';
else
case BAUD_VAL_FRACTION is
when "000" => if (baud_cntr = "0000000000000") then --0
baud_cntr <= baud_val;
baud_clock_int <= '1';
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
when "001" => if (baud_cntr = "0000000000000") then
if (xmit_cntr(2 downto 0) = "111" and baud_cntr_one = '1') then --0.125
baud_cntr <= baud_cntr;
baud_clock_int <= '0';
else
baud_cntr <= baud_val;
baud_clock_int <= '1';
end if;
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
when "010" => if (baud_cntr = "0000000000000") then
if (xmit_cntr(1 downto 0) = "11" and baud_cntr_one = '1') then --0.25
baud_cntr <= baud_cntr;
baud_clock_int <= '0';
else
baud_cntr <= baud_val;
baud_clock_int <= '1';
end if;
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
when "011" => if (baud_cntr = "0000000000000") then
if ((((xmit_cntr(2) = '1') or (xmit_cntr(1) = '1')) and xmit_cntr(0) ='1') and (baud_cntr_one = '1')) then --0.375
baud_cntr <= baud_cntr;
baud_clock_int <= '0';
else
baud_cntr <= baud_val;
baud_clock_int <= '1';
end if;
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
when "100" => if (baud_cntr = "0000000000000") then
if (xmit_cntr(0) = '1' and baud_cntr_one = '1') then --0.5
baud_cntr <= baud_cntr;
baud_clock_int <= '0';
else
baud_cntr <= baud_val;
baud_clock_int <= '1';
end if;
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
when "101" => if (baud_cntr = "0000000000000") then
if (((xmit_cntr(2) = '1' and xmit_cntr(1) = '1') or xmit_cntr(0) = '1') and baud_cntr_one = '1') then --0.625
baud_cntr <= baud_cntr;
baud_clock_int <= '0';
else
baud_cntr <= baud_val;
baud_clock_int <= '1';
end if;
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
when "110" => if (baud_cntr = "0000000000000") then
if ((xmit_cntr(1) = '1' or xmit_cntr(0) = '1') and baud_cntr_one = '1') then -- 0.75
baud_cntr <= baud_cntr;
baud_clock_int <= '0';
else
baud_cntr <= baud_val;
baud_clock_int <= '1';
end if;
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
when "111" => if (baud_cntr = "0000000000000") then
if (((xmit_cntr(1) = '1' or xmit_cntr(0) = '1') or xmit_cntr(2 downto 0) = "100") and baud_cntr_one = '1') then -- 0.875
baud_cntr <= baud_cntr;
baud_clock_int <= '0';
else
baud_cntr <= baud_val;
baud_clock_int <= '1';
end if;
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
when others => if (baud_cntr = "0000000000000") then --0
baud_cntr <= baud_val;
baud_clock_int <= '1';
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
end case;
end if;
end if;
end process make_baud_cntr1;
END GENERATE;
UG10:IF(BAUD_VAL_FRCTN_EN= 0) GENERATE
make_baud_cntr2:process(clk,aresetn)
begin
if (aresetn = '0') then
baud_cntr <= "0000000000000";
baud_clock_int <= '0';
elsif(clk'event and clk='1') then
if (sresetn = '0') then
baud_cntr <= "0000000000000";
baud_clock_int <= '0';
else
if (baud_cntr = "0000000000000") then
baud_cntr <= baud_val;
baud_clock_int <= '1';
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
end if;
end if;
end process make_baud_cntr2;
END GENERATE;
--baud_clock_int <= '1' when baud_cntr = "00000000" else
-- '0';
----------------------------------------------------
-- generate a transmit clock pulse
----------------------------------------------------
make_xmit_clock: process(clk,aresetn)
begin
if(aresetn = '0') then
xmit_cntr <= "0000";
xmit_clock <= '0';
elsif(clk'event and clk='1') then
if(sresetn = '0') then
xmit_cntr <= "0000";
xmit_clock <= '0';
else
if(baud_clock_int = '1') then
xmit_cntr <= xmit_cntr + '1';
if(xmit_cntr = "1111") then
xmit_clock <= '1';
else
xmit_clock <= '0';
end if;
end if;
end if;
end if;
end process;
xmit_pulse <= xmit_clock and baud_clock_int;
baud_clock <= baud_clock_int;
end rtl;
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`protect end_protected
|
-------------------------------------------------------------------------------
-- Entree:
-- clk, reset : la clock et le reset
-- T : un tick
-- Config : la configuration du serpentin (32 * 7 + 6 = 230)
--
-- Sortie:
-- S(i) : '1' ou '0' selon que le i-ème segment du 7-segment doit
-- etre allumé ou éteinds
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity serpentinprog is
port(
-- entrées
clk : in STD_LOGIC;
reset : in STD_LOGIC;
T : in STD_LOGIC;
Config : in STD_LOGIC_VECTOR(229 downto 0);
-- sorties vers le 7-segment
S : OUT STD_LOGIC_VECTOR(6 downto 0);
SI : OUT STD_LOGIC_VECTOR(3 downto 0)
);
end serpentinprog;
architecture montage of serpentinprog is
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
-- registre de comptage de 1 à N
signal I : unsigned(5 downto 0);
signal I_EQ_N : STD_LOGIC;
-- Registre de commande
type T_CMD is (INIT, GO_NEXT, NOOP);
signal CMD : T_CMD ;
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
type STATE_TYPE is (
ST_INIT, ST_NEXT, ST_WAIT
);
signal state : STATE_TYPE;
begin
-------------------------------------------------------------------------------
-- Partie Opérative
-------------------------------------------------------------------------------
PROCESS (clk, reset)
begin
IF reset = '1' THEN
I <= to_unsigned(1, 6);
ELSIF clk'event and clk = '1' then
-- si on initialise, on met le compteur à 1
IF CMD = INIT THEN
I <= to_unsigned(1, 6);
-- si on doit passer à la frame suivante
ELSIF CMD = GO_NEXT THEN
I <= I + 1;
END IF;
END IF;
END PROCESS;
I_EQ_N <= '1' WHEN (I = unsigned(Config(229 downto 224))) ELSE '0';
-- debug, affiche 'I'
SI <= STD_LOGIC_VECTOR(I(3 downto 0));
-------------------------------------------------------------------------------
-- Partie Contrôle
-------------------------------------------------------------------------------
-- Inputs: T
-- Outputs: S, CMD
-------------------------------------------------------------------------------
-- fonction de transitition
PROCESS (reset, clk)
begin
IF reset = '1' THEN
state <= ST_INIT;
ELSIF clk'event and clk = '1' THEN
CASE state IS
when ST_INIT =>
state <= ST_WAIT ;
WHEN ST_WAIT =>
IF T = '1' THEN
IF I_EQ_N = '1' THEN
state <= ST_INIT;
ELSE
state <= ST_NEXT;
END IF;
END IF;
WHEN ST_NEXT =>
state <= ST_WAIT;
END CASE;
END IF;
END PROCESS;
-- fonction de sortie
with state select CMD <=
INIT when ST_INIT,
GO_NEXT when ST_NEXT,
NOOP when ST_WAIT
;
WITH I SELECT S <=
Config( 6 downto 0) WHEN to_unsigned(1, 6),
Config( 13 downto 7) WHEN to_unsigned(2, 6),
Config( 20 downto 14) WHEN to_unsigned(3, 6),
Config( 27 downto 21) WHEN to_unsigned(4, 6),
Config( 34 downto 28) WHEN to_unsigned(5, 6),
Config( 41 downto 35) WHEN to_unsigned(6, 6),
Config( 48 downto 42) WHEN to_unsigned(7, 6),
Config( 55 downto 49) WHEN to_unsigned(8, 6),
Config( 62 downto 56) WHEN to_unsigned(9, 6),
Config( 69 downto 63) WHEN to_unsigned(10, 6),
Config( 76 downto 70) WHEN to_unsigned(11, 6),
Config( 83 downto 77) WHEN to_unsigned(12, 6),
Config( 90 downto 84) WHEN to_unsigned(13, 6),
Config( 97 downto 91) WHEN to_unsigned(14, 6),
Config(104 downto 98) WHEN to_unsigned(15, 6),
Config(111 downto 105) WHEN to_unsigned(16, 6),
Config(118 downto 112) WHEN to_unsigned(17, 6),
Config(125 downto 119) WHEN to_unsigned(18, 6),
Config(132 downto 126) WHEN to_unsigned(19, 6),
Config(139 downto 133) WHEN to_unsigned(20, 6),
Config(146 downto 140) WHEN to_unsigned(21, 6),
Config(153 downto 147) WHEN to_unsigned(22, 6),
Config(160 downto 154) WHEN to_unsigned(23, 6),
Config(167 downto 161) WHEN to_unsigned(24, 6),
Config(174 downto 168) WHEN to_unsigned(25, 6),
Config(181 downto 175) WHEN to_unsigned(26, 6),
Config(188 downto 182) WHEN to_unsigned(27, 6),
Config(195 downto 189) WHEN to_unsigned(28, 6),
Config(202 downto 196) WHEN to_unsigned(29, 6),
Config(209 downto 203) WHEN to_unsigned(30, 6),
Config(216 downto 210) WHEN to_unsigned(31, 6),
Config(223 downto 217) WHEN to_unsigned(32, 6),
"0000110" WHEN OTHERS
;
end montage;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity Add_Frame_example is
port(
Avalon_ST_Sink_data : in STD_LOGIC_VECTOR(23 downto 0);
Avalon_ST_Sink_endofpacket : in STD_LOGIC;
Avalon_MM_Slave_address : in STD_LOGIC_VECTOR(2 downto 0);
Avalon_MM_Slave_writedata : in STD_LOGIC_VECTOR(31 downto 0);
Avalon_ST_Source_valid : out STD_LOGIC;
Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_col : out STD_LOGIC_VECTOR(15 downto 0);
Avalon_ST_Sink_valid : in STD_LOGIC;
Clock : in STD_LOGIC;
Avalon_ST_Source_endofpacket : out STD_LOGIC;
Add_Frame_Add_Frame_Module_frame_in : out STD_LOGIC_VECTOR(0 downto 0);
Add_Frame_Add_Frame_Module_row_counter : out STD_LOGIC_VECTOR(15 downto 0);
Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_row : out STD_LOGIC_VECTOR(15 downto 0);
Avalon_ST_Source_startofpacket : out STD_LOGIC;
Add_Frame_Add_Frame_Module_col_counter : out STD_LOGIC_VECTOR(15 downto 0);
Avalon_MM_Slave_write : in STD_LOGIC;
Avalon_ST_Source_ready : in STD_LOGIC;
aclr : in STD_LOGIC;
Avalon_ST_Sink_ready : out STD_LOGIC;
Add_Frame_Add_Frame_Module_state : out STD_LOGIC_VECTOR(2 downto 0);
Avalon_ST_Sink_startofpacket : in STD_LOGIC;
Avalon_ST_Source_data : out STD_LOGIC_VECTOR(23 downto 0));
end entity;
architecture rtl of Add_Frame_example is
component Add_Frame
port(
Avalon_ST_Sink_data : in STD_LOGIC_VECTOR(23 downto 0);
Avalon_ST_Sink_endofpacket : in STD_LOGIC;
Avalon_MM_Slave_address : in STD_LOGIC_VECTOR(2 downto 0);
Avalon_MM_Slave_writedata : in STD_LOGIC_VECTOR(31 downto 0);
Avalon_ST_Source_valid : out STD_LOGIC;
Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_col : out STD_LOGIC_VECTOR(15 downto 0);
Avalon_ST_Sink_valid : in STD_LOGIC;
Clock : in STD_LOGIC;
Avalon_ST_Source_endofpacket : out STD_LOGIC;
Add_Frame_Add_Frame_Module_frame_in : out STD_LOGIC_VECTOR(0 downto 0);
Add_Frame_Add_Frame_Module_row_counter : out STD_LOGIC_VECTOR(15 downto 0);
Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_row : out STD_LOGIC_VECTOR(15 downto 0);
Avalon_ST_Source_startofpacket : out STD_LOGIC;
Add_Frame_Add_Frame_Module_col_counter : out STD_LOGIC_VECTOR(15 downto 0);
Avalon_MM_Slave_write : in STD_LOGIC;
Avalon_ST_Source_ready : in STD_LOGIC;
aclr : in STD_LOGIC;
Avalon_ST_Sink_ready : out STD_LOGIC;
Add_Frame_Add_Frame_Module_state : out STD_LOGIC_VECTOR(2 downto 0);
Avalon_ST_Sink_startofpacket : in STD_LOGIC;
Avalon_ST_Source_data : out STD_LOGIC_VECTOR(23 downto 0));
end component;
begin
Add_Frame_instance :
component Add_Frame
port map(
Avalon_ST_Sink_data => Avalon_ST_Sink_data,
Avalon_ST_Sink_endofpacket => Avalon_ST_Sink_endofpacket,
Avalon_MM_Slave_address => Avalon_MM_Slave_address,
Avalon_MM_Slave_writedata => Avalon_MM_Slave_writedata,
Avalon_ST_Source_valid => Avalon_ST_Source_valid,
Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_col => Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_col,
Avalon_ST_Sink_valid => Avalon_ST_Sink_valid,
Clock => Clock,
Avalon_ST_Source_endofpacket => Avalon_ST_Source_endofpacket,
Add_Frame_Add_Frame_Module_frame_in => Add_Frame_Add_Frame_Module_frame_in,
Add_Frame_Add_Frame_Module_row_counter => Add_Frame_Add_Frame_Module_row_counter,
Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_row => Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_row,
Avalon_ST_Source_startofpacket => Avalon_ST_Source_startofpacket,
Add_Frame_Add_Frame_Module_col_counter => Add_Frame_Add_Frame_Module_col_counter,
Avalon_MM_Slave_write => Avalon_MM_Slave_write,
Avalon_ST_Source_ready => Avalon_ST_Source_ready,
aclr => aclr,
Avalon_ST_Sink_ready => Avalon_ST_Sink_ready,
Add_Frame_Add_Frame_Module_state => Add_Frame_Add_Frame_Module_state,
Avalon_ST_Sink_startofpacket => Avalon_ST_Sink_startofpacket,
Avalon_ST_Source_data => Avalon_ST_Source_data);
end architecture rtl;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Example to test prefix for VTypeArray (and using function as index).
library ieee;
use ieee.std_logic_1164.all;
entity prefix_array is
port(sel_word : in std_logic_vector(1 downto 0);
out_word : out integer);
end entity prefix_array;
architecture test of prefix_array is
type t_timeouts is
record
a : integer;
b : integer;
end record;
type t_timeouts_table is array (natural range <>) of t_timeouts;
constant c_TIMEOUTS_TABLE : t_timeouts_table(3 downto 0) :=
(0 => (a => 1, b => 2),
1 => (a => 3, b => 4),
2 => (a => 5, b => 6),
3 => (a => 7, b => 8));
begin
process(sel_word)
begin
out_word <= to_unsigned((c_TIMEOUTS_TABLE(to_integer(unsigned(sel_word))).a), 32);
end process;
end architecture test;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Example to test prefix for VTypeArray (and using function as index).
library ieee;
use ieee.std_logic_1164.all;
entity prefix_array is
port(sel_word : in std_logic_vector(1 downto 0);
out_word : out integer);
end entity prefix_array;
architecture test of prefix_array is
type t_timeouts is
record
a : integer;
b : integer;
end record;
type t_timeouts_table is array (natural range <>) of t_timeouts;
constant c_TIMEOUTS_TABLE : t_timeouts_table(3 downto 0) :=
(0 => (a => 1, b => 2),
1 => (a => 3, b => 4),
2 => (a => 5, b => 6),
3 => (a => 7, b => 8));
begin
process(sel_word)
begin
out_word <= to_unsigned((c_TIMEOUTS_TABLE(to_integer(unsigned(sel_word))).a), 32);
end process;
end architecture test;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Example to test prefix for VTypeArray (and using function as index).
library ieee;
use ieee.std_logic_1164.all;
entity prefix_array is
port(sel_word : in std_logic_vector(1 downto 0);
out_word : out integer);
end entity prefix_array;
architecture test of prefix_array is
type t_timeouts is
record
a : integer;
b : integer;
end record;
type t_timeouts_table is array (natural range <>) of t_timeouts;
constant c_TIMEOUTS_TABLE : t_timeouts_table(3 downto 0) :=
(0 => (a => 1, b => 2),
1 => (a => 3, b => 4),
2 => (a => 5, b => 6),
3 => (a => 7, b => 8));
begin
process(sel_word)
begin
out_word <= to_unsigned((c_TIMEOUTS_TABLE(to_integer(unsigned(sel_word))).a), 32);
end process;
end architecture test;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rdw_gt_wrw <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(wr_en_rd2 = '1' AND rd_en_i= '0' AND EMPTY = '1') THEN
rdw_gt_wrw <= rdw_gt_wrw + '1';
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rdw_gt_wrw <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(wr_en_rd2 = '1' AND rd_en_i= '0' AND EMPTY = '1') THEN
rdw_gt_wrw <= rdw_gt_wrw + '1';
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rdw_gt_wrw <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(wr_en_rd2 = '1' AND rd_en_i= '0' AND EMPTY = '1') THEN
rdw_gt_wrw <= rdw_gt_wrw + '1';
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rdw_gt_wrw <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(wr_en_rd2 = '1' AND rd_en_i= '0' AND EMPTY = '1') THEN
rdw_gt_wrw <= rdw_gt_wrw + '1';
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rdw_gt_wrw <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(wr_en_rd2 = '1' AND rd_en_i= '0' AND EMPTY = '1') THEN
rdw_gt_wrw <= rdw_gt_wrw + '1';
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
-----------------------------------------------------------------------------------------
-- Project : Invent a Chip
-- Module : LC-Display
-- Author : Christian Leibold / Jan Dürre
-- Last update : 29.04.2015
-- Description : -
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity lcd is
generic(
SIMULATION : boolean := false
);
port(
-- global signals
clock : in std_ulogic;
reset_n : in std_ulogic;
-- bus signals
iobus_cs : in std_ulogic;
iobus_wr : in std_ulogic;
iobus_addr : in std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
iobus_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0);
iobus_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0);
iobus_irq_rdy : out std_ulogic;
iobus_ack_rdy : in std_ulogic;
-- display signals
disp_en : out std_ulogic;
disp_rs : out std_ulogic;
disp_rw : out std_ulogic;
disp_dat : out std_ulogic_vector(7 downto 0);
disp_pwr : out std_ulogic;
disp_blon : out std_ulogic
);
end lcd;
architecture rtl of lcd is
-- buffer for incoming lcd-commands
component fifo is
generic (
DEPTH : natural;
WORDWIDTH : natural
);
port (
clock : in std_ulogic;
reset_n : in std_ulogic;
write_en : in std_ulogic;
data_in : in std_ulogic_vector(WORDWIDTH-1 downto 0);
read_en : in std_ulogic;
data_out : out std_ulogic_vector(WORDWIDTH-1 downto 0);
empty : out std_ulogic;
full : out std_ulogic;
fill_cnt : out unsigned(to_log2(DEPTH+1)-1 downto 0)
);
end component fifo;
signal buf_write_en : std_ulogic;
signal buf_data_in : std_ulogic_vector(7 downto 0);
signal buf_read_en : std_ulogic;
signal buf_data_out : std_ulogic_vector(7 downto 0);
signal buf_empty : std_ulogic;
signal buf_full : std_ulogic;
type state_t IS (S_POWER_UP, S_INIT, S_READY, S_SEND, S_CURSOR_DATA, S_CURSOR_SET);
signal state, state_nxt : state_t;
signal clk_count, clk_count_nxt : unsigned(42 downto 0) := (others => '0');
signal count_inc, count_rst : std_ulogic;
signal rs, rs_nxt : std_ulogic;
signal data, data_nxt : std_ulogic_vector(7 downto 0);
-- LCD state registers
signal cursor_on, cursor_on_nxt : std_ulogic; -- Static cursor (1 = on , 0 = off)
signal blink_on, blink_on_nxt : std_ulogic; -- Cursor blinks (1 = on , 0 = off)
signal col, col_nxt : unsigned(3 downto 0);
signal row, row_nxt : unsigned(0 downto 0);
signal cursor_home : std_ulogic;
signal cursor_right : std_ulogic;
signal cursor_left : std_ulogic;
signal cursor_set : std_ulogic;
constant CYCLES_POWER_UP : natural := 50*(CV_SYS_CLOCK_RATE/1000); -- 50 ms
signal CYCLES_INIT_FUNC : natural;
signal CYCLES_INIT_FUNC_WAIT : natural;
signal CYCLES_INIT_DISP : natural;
signal CYCLES_INIT_DISP_WAIT : natural;
signal CYCLES_INIT_CLR : natural;
signal CYCLES_INIT_CLR_WAIT : natural;
signal CYCLES_INIT_ENTRY : natural;
signal CYCLES_INIT_ENTRY_WAIT : natural;
signal TIME_1us : natural;
signal TIME_50us : natural;
signal TIME_14us : natural;
signal TIME_27us : natural;
begin
CYCLES_INIT_FUNC <= 10*(CV_SYS_CLOCK_RATE/1000000) when SIMULATION = false else 10;
CYCLES_INIT_FUNC_WAIT <= CYCLES_INIT_FUNC + 50*(CV_SYS_CLOCK_RATE/1000000) when SIMULATION = false else CYCLES_INIT_FUNC + 50; -- + 50 us
CYCLES_INIT_DISP <= CYCLES_INIT_FUNC_WAIT + 10*(CV_SYS_CLOCK_RATE/1000000) when SIMULATION = false else CYCLES_INIT_FUNC_WAIT + 10; -- + 10 us
CYCLES_INIT_DISP_WAIT <= CYCLES_INIT_DISP + 50*(CV_SYS_CLOCK_RATE/1000000) when SIMULATION = false else CYCLES_INIT_DISP + 50; -- + 50 us
CYCLES_INIT_CLR <= CYCLES_INIT_DISP_WAIT + 10*(CV_SYS_CLOCK_RATE/1000000) when SIMULATION = false else CYCLES_INIT_DISP_WAIT + 10; -- + 10 us
CYCLES_INIT_CLR_WAIT <= CYCLES_INIT_CLR + 02*(CV_SYS_CLOCK_RATE/1000) when SIMULATION = false else CYCLES_INIT_CLR + 02; -- + 2 ms
CYCLES_INIT_ENTRY <= CYCLES_INIT_CLR_WAIT + 10*(CV_SYS_CLOCK_RATE/1000000) when SIMULATION = false else CYCLES_INIT_CLR_WAIT + 10; -- + 10 us
CYCLES_INIT_ENTRY_WAIT <= CYCLES_INIT_ENTRY + 60*(CV_SYS_CLOCK_RATE/1000000) when SIMULATION = false else CYCLES_INIT_ENTRY + 60; -- + 60 us
TIME_1us <= 01*(CV_SYS_CLOCK_RATE/1000000) when SIMULATION = false else 1; -- 1 us
TIME_50us <= 50*(CV_SYS_CLOCK_RATE/1000000) when SIMULATION = false else 50; -- 50 us
TIME_14us <= 14*(CV_SYS_CLOCK_RATE/1000000) when SIMULATION = false else 14; -- 14 us
TIME_27us <= 27*(CV_SYS_CLOCK_RATE/1000000) when SIMULATION = false else 27; -- 27 us
buf_inst : fifo
generic map (
DEPTH => CS_LCD_BUFFER,
WORDWIDTH => 8
)
port map (
clock => clock,
reset_n => reset_n,
write_en => buf_write_en,
data_in => buf_data_in,
read_en => buf_read_en,
data_out => buf_data_out,
empty => buf_empty,
full => buf_full,
fill_cnt => open
);
process(clock, reset_n)
begin
if reset_n = '0' then
clk_count <= (others => '0');
rs <= '0';
data <= (others => '0');
state <= S_POWER_UP;
-- LCD registers
cursor_on <= '0';
blink_on <= '0';
col <= (others => '0');
row <= (others => '0');
elsif rising_edge(clock) then
clk_count <= clk_count_nxt;
rs <= rs_nxt;
data <= data_nxt;
state <= state_nxt;
-- LCD registers
cursor_on <= cursor_on_nxt;
blink_on <= blink_on_nxt;
col <= col_nxt;
row <= row_nxt;
end if;
end process;
iobus_if : process(iobus_cs, iobus_wr, iobus_addr, iobus_din, buf_empty, buf_full, state)
begin
buf_write_en <= '0';
buf_data_in <= (others => '0');
iobus_irq_rdy <= not buf_full;
iobus_dout <= (others => '0');
-- chipselect
if iobus_cs = '1' then
-- write
if iobus_wr = '1' then
-- data
if iobus_addr = CV_ADDR_LCD_DATA then
-- avoid overflow
if buf_full = '0' then
buf_write_en <= '1';
buf_data_in <= iobus_din;
end if;
end if;
-- read
else
-- status
if iobus_addr = CV_ADDR_LCD_STATUS then
-- working
if buf_empty = '0' or state /= S_READY then
iobus_dout(0) <= '1';
else
iobus_dout(0) <= '0';
end if;
end if;
end if;
end if;
end process;
clk_count_nxt <= (others => '0') when count_rst = '1' else
clk_count + 1 when count_inc = '1' else
clk_count;
disp_rs <= rs;
disp_dat <= data;
disp_rw <= '0';
disp_pwr <= '1';
disp_blon <= '0';
process(state, clk_count, data, rs, cursor_on, blink_on, col, row, buf_empty, buf_data_out, CYCLES_INIT_FUNC, CYCLES_INIT_FUNC_WAIT, CYCLES_INIT_DISP, CYCLES_INIT_DISP_WAIT, CYCLES_INIT_CLR, CYCLES_INIT_CLR_WAIT, CYCLES_INIT_ENTRY, CYCLES_INIT_ENTRY_WAIT, TIME_1us, TIME_50us, TIME_14us, TIME_27us)
variable data_in : unsigned(7 downto 0) := (others => '0');
begin
state_nxt <= state;
data_nxt <= data;
rs_nxt <= rs;
cursor_on_nxt <= cursor_on;
blink_on_nxt <= blink_on;
count_rst <= '0';
count_inc <= '0';
disp_en <= '0';
buf_read_en <= '0';
cursor_home <= '0';
cursor_right <= '0';
cursor_left <= '0';
cursor_set <= '0';
case state is
-- Wait 50 ms to ensure VDD has risen and required LCD wait is met
WHEN S_POWER_UP =>
if (clk_count < CYCLES_POWER_UP) and not SIMULATION then
count_inc <= '1';
elsif (clk_count < 10) and SIMULATION then
count_inc <= '1';
else -- Power-up complete
count_rst <= '1';
rs_nxt <= '0';
data_nxt <= "00111100"; -- 2-line mode, display on
state_nxt <= S_INIT;
end if;
-- Cycle through initialization sequence
WHEN S_INIT =>
count_inc <= '1';
if clk_count < CYCLES_INIT_FUNC then -- Function set
disp_en <= '1';
elsif clk_count < CYCLES_INIT_FUNC_WAIT then -- Wait 50 us
disp_en <= '0';
data_nxt <= "00001100"; -- Display on, Cursor off, Blink off
elsif clk_count < CYCLES_INIT_DISP THEN -- Display on/off control
cursor_on_nxt <= '0'; -- Save cursor off state
blink_on_nxt <= '0'; -- Save blink off state
disp_en <= '1';
elsif clk_count < CYCLES_INIT_DISP_WAIT then -- Wait 50 us
disp_en <= '0';
data_nxt <= x"01";
elsif clk_count < CYCLES_INIT_CLR then -- Display clear
cursor_home <= '1';
disp_en <= '1';
elsif clk_count < CYCLES_INIT_CLR_WAIT then -- Wait 2 ms
disp_en <= '0';
data_nxt <= "00000110"; -- Increment mode, entire shift off
elsif clk_count < CYCLES_INIT_ENTRY then -- Entry mode set
disp_en <= '1';
elsif clk_count < CYCLES_INIT_ENTRY_WAIT then -- Wait 60 us
data_nxt <= (others => '0');
disp_en <= '0';
else -- Initialization complete
count_rst <= '1';
state_nxt <= S_READY;
END IF;
-- Wait for the enable signal (iobus_cs & iobus_wr) and then latch in the instruction
when S_READY =>
count_rst <= '1';
if buf_empty = '0' then
state_nxt <= S_SEND;
buf_read_en <= '1';
data_in := unsigned(buf_data_out(7 downto 0));
-- Code for a character
if (data_in>=16#20# and data_in<=16#7F#) or (data_in>=16#A0# and data_in<=16#FE#) then
rs_nxt <= '1';
data_nxt <= buf_data_out(7 downto 0);
cursor_right <= '1';
-- Code for a function
elsif (data_in>=16#00# and data_in<=16#06#) or (data_in>=16#80# and data_in<=16#9F#) then
rs_nxt <= '0';
if data_in = 16#00# then -- Display clear
data_nxt <= x"01";
cursor_home <= '1';
elsif data_in = 16#01# then -- Cursor on
data_nxt <= x"0" & '1' & '1' & '1' & blink_on;
cursor_on_nxt <= '1';
elsif data_in = 16#02# then -- Cursor off
data_nxt <= x"0" & '1' & '1' & '0' & blink_on;
cursor_on_nxt <= '0';
elsif data_in = 16#03# then -- Blinking on
data_nxt <= x"0" & '1' & '1' & cursor_on & '1';
blink_on_nxt <= '1';
elsif data_in = 16#04# then -- Blinking off
data_nxt <= x"0" & '1' & '1' & cursor_on & '0';
blink_on_nxt <= '0';
elsif data_in = 16#05# then -- Move cursor right
cursor_right <= '1';
state_nxt <= S_CURSOR_DATA;
elsif data_in = 16#06# then -- Move cursor left
cursor_left <= '1';
state_nxt <= S_CURSOR_DATA;
else
cursor_set <= '1';
state_nxt <= S_CURSOR_DATA;
end if;
-- Invalid codes will be ignored and the display won't get busy
else
rs_nxt <= '0';
data_nxt <= (others => '0');
state_nxt <= S_READY;
end if;
else
rs_nxt <= '0';
data_nxt <= (others => '0');
end if;
-- Send instruction to LCD
when S_SEND =>
if clk_count < TIME_50us then -- Do not exit for 50us
count_inc <= '1';
if clk_count < TIME_1us then -- Negative enable
disp_en <= '0';
elsif clk_count < TIME_14us then -- Positive enable half-cycle
disp_en <= '1';
elsif clk_count < TIME_27us then -- Negative enable half-cycle
disp_en <= '0';
end if;
else
rs_nxt <= '0';
data_nxt <= '1' & row(0) & "00" & std_ulogic_vector(col);
count_rst <= '1';
state_nxt <= S_CURSOR_SET;
end if;
when S_CURSOR_DATA =>
rs_nxt <= '0';
data_nxt <= '1' & row(0) & "00" & std_ulogic_vector(col);
count_rst <= '1';
state_nxt <= S_CURSOR_SET;
when S_CURSOR_SET =>
if clk_count < TIME_50us then -- Do not exit for 50us
count_inc <= '1';
if clk_count < TIME_1us then -- Negative enable
disp_en <= '0';
elsif clk_count < TIME_14us then -- Positive enable half-cycle
disp_en <= '1';
elsif clk_count < TIME_27us then -- Negative enable half-cycle
disp_en <= '0';
end if;
else
count_rst <= '1';
state_nxt <= S_READY;
end if;
end case;
end process;
process(col, row, cursor_home, cursor_right, cursor_left, cursor_set, buf_data_out)
begin
col_nxt <= col;
row_nxt <= row;
if cursor_home = '1' then
col_nxt <= (others => '0');
row_nxt <= (others => '0');
elsif cursor_right = '1' then
if col = 15 then
col_nxt <= (others => '0');
row_nxt <= row + 1;
else
col_nxt <= col + 1;
end if;
elsif cursor_left = '1' then
if col = 15 then
col_nxt <= (others => '0');
row_nxt <= row - 1;
else
col_nxt <= col - 1;
end if;
elsif cursor_set = '1' then
col_nxt <= unsigned(buf_data_out(3 downto 0));
row_nxt <= unsigned(buf_data_out(4 downto 4));
end if;
end process;
end rtl; |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
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-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- related to, arising under or in connection with these
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-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_11;
USE axi_gpio_v2_0_11.axi_gpio;
ENTITY PmodNAV_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END PmodNAV_axi_gpio_0_0;
ARCHITECTURE PmodNAV_axi_gpio_0_0_arch OF PmodNAV_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF PmodNAV_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 1,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"0000000F",
C_TRI_DEFAULT => X"00000000",
C_IS_DUAL => 1,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"00000001"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => gpio2_io_i,
gpio2_io_o => gpio2_io_o,
gpio2_io_t => gpio2_io_t
);
END PmodNAV_axi_gpio_0_0_arch;
|
-- Design unit: distortion_component
-- Authors : Aaron Arnason, Byron Maroney, Edrick De Guzman
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity distort is
port(
clk : in std_logic;
reset : in std_logic;
dist_en : in std_logic; -- 1-bit distortion enable signal
ready : in std_logic;
done : out std_logic;
data_in : in std_logic_vector(15 downto 0); -- 16-bit data stream input
clipping_write : in std_logic;
clipping_read : in std_logic;
clipping_value: in std_logic_vector(15 downto 0); -- 16-bit input clipping threshold
clipping_readdata: out std_logic_vector(15 downto 0);
data_out: out std_logic_vector(15 downto 0) -- 16-bit data stream output (either clipped or not)
);
end entity distort;
architecture behavior of distort is
constant clipping_default : std_logic_vector(15 downto 0) := "0000101110111000"; -- constant value of 3000 in decimal
constant clipping_high : std_logic_vector(15 downto 0) := "0000000001100100"; -- constant value of 1000 in decimal
constant clipping_low : std_logic_vector(15 downto 0) := "0000001111101000"; -- constant value of 5000 in decimal
constant clipping_inc : std_logic_vector(15 downto 0) := X"01F4";
signal gain_constant : std_logic_vector(2 downto 0) := "001"; -- constant gain: default at 1
signal clip_threshold,clip_sample : std_logic_vector(15 downto 0);
signal completed : std_logic :='0';
signal counter: unsigned(15 downto 0);
begin
clipping_readdata <= clip_threshold;
done <= completed;
c1: process(clk,clipping_write)
begin
if rising_edge(clk) then
if dist_en = '1' then
if clipping_write = '0' then -- Active Low
clip_sample <= clipping_value;
else
case clip_sample is
when X"0001" =>
clip_threshold <= X"0BB8"; -- Level: 1 - 3000
gain_constant <= "001"; -- Gain: 1
when X"0002" =>
clip_threshold <= X"076C"; -- Level: 2 - 1900
gain_constant <= "010"; -- Gain: 2
when X"0003" =>
clip_threshold <= X"0514"; -- Level: 3 - 1300
gain_constant <= "010"; -- Gain: 2
when X"0004" =>
clip_threshold <= X"02BC"; -- Level: 4 - 700
gain_constant <= "011"; -- Gain: 3
when X"0005" =>
clip_threshold <= X"012C"; -- Level: 5 - 300
gain_constant <= "111"; -- Gain: 5
when others =>
clip_threshold <= X"012C"; -- Level: X - 300
gain_constant <= "111";
end case;
end if;
end if;
end if;
end process;
g0:process(clk,reset,dist_en,ready)
variable mult_result : std_logic_vector(18 downto 0);
begin
if reset = '0' then
data_out <= X"0000";
elsif (rising_edge(clk)) then
if(ready = '1') then
-- End Clipping Configurations
if dist_en = '1' then -- Check if Distortion is Enabled
if data_in(15) = '1' then -- Check sign of sample (If negative...)
if (not data_in(14 downto 0)) >= clip_threshold(14 downto 0) then -- compare data to clip_threshold (without sign bits)
mult_result := gain_constant * clip_threshold;
data_out <= '1' & (not mult_result(14 downto 0));
--data_out <= '1' & (not clip_threshold(14 downto 0)); -- if data is greater than threshold, data_out = clip_threshold, concatenate '1' to complement
else
mult_result := gain_constant * data_in;
data_out <= mult_result(15 downto 0);
--data_out <= data_in;
end if;
elsif data_in(15) = '0' then -- Check sign of sample (If positive...)
if data_in(14 downto 0) >= clip_threshold(14 downto 0) then
mult_result := gain_constant * clip_threshold;
data_out <= '0' & mult_result(14 downto 0);
--data_out <= '0' & clip_threshold(14 downto 0);
else
mult_result := gain_constant * data_in;
data_out <= mult_result(15 downto 0);
--data_out <= data_in;
end if;
end if;
else
data_out <= data_in;
end if;
completed <= '1';
else
completed <= '0';
end if;
end if;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Parallel port (8/16bit) for PDI
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity pdi_spi is
generic (
spiSize_g : integer := 8;
cpol_g : boolean := false;
cpha_g : boolean := false;
spiBigEnd_g : boolean := false
);
port (
-- SPI
spi_clk : in std_logic;
spi_sel : in std_logic;
spi_miso : out std_logic;
spi_mosi : in std_logic;
-- clock for AP side
ap_reset : in std_logic;
ap_clk : in std_logic;
-- Avalon Slave Interface for AP
ap_chipselect : out std_logic;
ap_read : out std_logic;
ap_write : out std_logic;
ap_byteenable : out std_logic_vector(3 DOWNTO 0);
ap_address : out std_logic_vector(12 DOWNTO 0);
ap_writedata : out std_logic_vector(31 DOWNTO 0);
ap_readdata : in std_logic_vector(31 DOWNTO 0)
);
end entity pdi_spi;
architecture rtl of pdi_spi is
--wake up command
constant cmdWakeUp : std_logic_vector(7 downto 0) := x"03"; --0b00000011
constant cmdWakeUp1 : std_logic_vector(7 downto 0) := x"0A"; --0b00001010
constant cmdWakeUp2 : std_logic_vector(7 downto 0) := x"0C"; --0b00001100
constant cmdWakeUp3 : std_logic_vector(7 downto 0) := x"0F"; --0b00001111
--spi frame constants
constant cmdHighaddr_c : std_logic_vector(2 downto 0) := "100";
constant cmdMidaddr_c : std_logic_vector(2 downto 0) := "101";
constant cmdWr_c : std_logic_vector(2 downto 0) := "110";
constant cmdRd_c : std_logic_vector(2 downto 0) := "111";
constant cmdWRSQ_c : std_logic_vector(2 downto 0) := "001";
constant cmdRDSQ_c : std_logic_vector(2 downto 0) := "010";
constant cmdLowaddr_c : std_logic_vector(2 downto 0) := "011";
constant cmdIdle_c : std_logic_vector(2 downto 0) := "000";
--pdi_spi control signals
type fsm_t is (reset, reset1, reset2, reset3, idle, decode, waitwr, waitrd, wr, rd);
signal fsm : fsm_t;
signal addrReg : std_logic_vector(ap_address'left+2 downto 0);
signal cmd : std_logic_vector(2 downto 0);
signal highPriorLoad : std_logic;
signal highPriorLoadVal : std_logic_vector(spiSize_g-1 downto 0);
--spi core signals
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic_vector(spiSize_g-1 downto 0);
signal load : std_logic;
signal dout : std_logic_vector(spiSize_g-1 downto 0);
signal valid : std_logic;
--
signal ap_byteenable_s : std_logic_vector(ap_byteenable'range);
begin
clk <= ap_clk;
rst <= ap_reset;
ap_chipselect <= '1' when fsm = wr or fsm = rd or fsm = waitrd else '0';
ap_write <= '1' when fsm = wr else '0';
ap_read <= '1' when fsm = waitrd or fsm = rd else '0';
ap_address <= addrReg(addrReg'left downto 2);
ap_byteenable <= ap_byteenable_s;
ap_byteenable_s <= --little endian
"0001" when addrReg(1 downto 0) = "00" and spiBigEnd_g = false else
"0010" when addrReg(1 downto 0) = "01" and spiBigEnd_g = false else
"0100" when addrReg(1 downto 0) = "10" and spiBigEnd_g = false else
"1000" when addrReg(1 downto 0) = "11" and spiBigEnd_g = false else
--big endian
--"0001" when addrReg(1 downto 0) = "11" and spiBigEnd_g = true else
--"0010" when addrReg(1 downto 0) = "10" and spiBigEnd_g = true else
--"0100" when addrReg(1 downto 0) = "01" and spiBigEnd_g = true else
--"1000" when addrReg(1 downto 0) = "00" and spiBigEnd_g = true else
"0000";
ap_writedata <= (dout & dout & dout & dout);
din <= highPriorLoadVal when highPriorLoad = '1' else --load value that was just received
ap_readdata( 7 downto 0) when ap_byteenable_s = "0001" else
ap_readdata(15 downto 8) when ap_byteenable_s = "0010" else
ap_readdata(23 downto 16) when ap_byteenable_s = "0100" else
ap_readdata(31 downto 24) when ap_byteenable_s = "1000" else
(others => '0');
load <= '1' when highPriorLoad = '1' else --load value that was just received
'1' when fsm = rd else --load data from pdi to spi shift register
'0';
cmd <= dout(dout'left downto dout'left-2); --get cmd pattern
highPriorLoadVal <= not dout; --create inverse of received pattern
thePdiSpiFsm : process(clk, rst)
variable timeout : integer range 0 to 3;
variable writes : integer range 0 to 32;
variable reads : integer range 0 to 32;
begin
if rst = '1' then
fsm <= reset;
timeout := 0;
writes := 0; reads := 0;
addrReg <= (others => '0');
highPriorLoad <= '0';
elsif clk = '1' and clk'event then
--default assignment
highPriorLoad <= '0';
case fsm is
when reset =>
fsm <= reset;
if valid = '1' then
--load inverse pattern of received pattern
highPriorLoad <= '1';
if dout = cmdWakeUp then
--wake up command (1/4) received
fsm <= reset1;
else
--wake up command not decoded correctly
fsm <= reset;
end if;
end if;
when reset1 =>
fsm <= reset1;
if valid = '1' then
--load inverse pattern of received pattern
highPriorLoad <= '1';
if dout = cmdWakeUp1 then
--wake up command (2/4) sequence was correctly decoded!
fsm <= reset2;
else
--wake up command not decoded correctly
fsm <= reset;
end if;
end if;
when reset2 =>
fsm <= reset2;
if valid = '1' then
--load inverse pattern of received pattern
highPriorLoad <= '1';
if dout = cmdWakeUp2 then
--wake up command (3/4) sequence was correctly decoded!
fsm <= reset3;
else
--wake up command not decoded correctly
fsm <= reset;
end if;
end if;
when reset3 =>
fsm <= reset3;
if valid = '1' then
--load inverse pattern of received pattern
highPriorLoad <= '1';
if dout = cmdWakeUp3 then
--wake up command (4/4) sequence was correctly decoded!
fsm <= idle;
else
--wake up command not decoded correctly
fsm <= reset;
end if;
end if;
when idle =>
if writes /= 0 then
fsm <= waitwr;
elsif reads /= 0 and valid = '1' then
fsm <= waitrd;
elsif valid = '1' then
fsm <= decode;
else
fsm <= idle;
end if;
when decode =>
fsm <= idle; --default
case cmd is
when cmdHighaddr_c =>
addrReg(addrReg'left downto addrReg'left-4) <= dout(spiSize_g-4 downto 0);
when cmdMidaddr_c =>
addrReg(addrReg'left-5 downto addrReg'left-9) <= dout(spiSize_g-4 downto 0);
when cmdLowaddr_c =>
addrReg(addrReg'left-10 downto 0) <= dout(spiSize_g-4 downto 0);
when cmdWr_c =>
addrReg(addrReg'left-10 downto 0) <= dout(spiSize_g-4 downto 0);
fsm <= waitwr;
writes := 1;
when cmdRd_c =>
addrReg(addrReg'left-10 downto 0) <= dout(spiSize_g-4 downto 0);
fsm <= waitrd;
reads := 1;
when cmdWRSQ_c =>
fsm <= waitwr;
writes := conv_integer(dout(spiSize_g-4 downto 0)) + 1; --BYTES byte are written
when cmdRDSQ_c =>
fsm <= waitrd;
reads := conv_integer(dout(spiSize_g-4 downto 0)) + 1; --BYTES byte are read
when cmdIdle_c =>
--don't interpret the command, inverse pattern and goto idle
when others =>
--error, goto idle
end case;
when waitwr =>
--wait for data from spi master
if valid = '1' then
fsm <= wr;
else
fsm <= waitwr;
end if;
when waitrd =>
--spi master wants to read
--wait for dpr to read
if timeout = 3 then
fsm <= rd;
timeout := 0;
else
timeout := timeout + 1;
fsm <= waitrd;
end if;
when wr =>
fsm <= idle;
writes := writes - 1;
addrReg <= addrReg + 1;
when rd =>
fsm <= idle;
reads := reads - 1;
addrReg <= addrReg + 1;
end case;
end if;
end process;
theSpiCore : entity work.spi
generic map (
frameSize_g => spiSize_g,
cpol_g => cpol_g,
cpha_g => cpha_g
)
port map (
-- Control Interface
clk => clk,
rst => rst,
din => din,
load => load,
dout => dout,
valid => valid,
-- SPI
sck => spi_clk,
ss => spi_sel,
miso => spi_miso,
mosi => spi_mosi
);
end architecture rtl;
|
-------------------------------------------------------------------------------
-- Parallel port (8/16bit) for PDI
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity pdi_spi is
generic (
spiSize_g : integer := 8;
cpol_g : boolean := false;
cpha_g : boolean := false;
spiBigEnd_g : boolean := false
);
port (
-- SPI
spi_clk : in std_logic;
spi_sel : in std_logic;
spi_miso : out std_logic;
spi_mosi : in std_logic;
-- clock for AP side
ap_reset : in std_logic;
ap_clk : in std_logic;
-- Avalon Slave Interface for AP
ap_chipselect : out std_logic;
ap_read : out std_logic;
ap_write : out std_logic;
ap_byteenable : out std_logic_vector(3 DOWNTO 0);
ap_address : out std_logic_vector(12 DOWNTO 0);
ap_writedata : out std_logic_vector(31 DOWNTO 0);
ap_readdata : in std_logic_vector(31 DOWNTO 0)
);
end entity pdi_spi;
architecture rtl of pdi_spi is
--wake up command
constant cmdWakeUp : std_logic_vector(7 downto 0) := x"03"; --0b00000011
constant cmdWakeUp1 : std_logic_vector(7 downto 0) := x"0A"; --0b00001010
constant cmdWakeUp2 : std_logic_vector(7 downto 0) := x"0C"; --0b00001100
constant cmdWakeUp3 : std_logic_vector(7 downto 0) := x"0F"; --0b00001111
--spi frame constants
constant cmdHighaddr_c : std_logic_vector(2 downto 0) := "100";
constant cmdMidaddr_c : std_logic_vector(2 downto 0) := "101";
constant cmdWr_c : std_logic_vector(2 downto 0) := "110";
constant cmdRd_c : std_logic_vector(2 downto 0) := "111";
constant cmdWRSQ_c : std_logic_vector(2 downto 0) := "001";
constant cmdRDSQ_c : std_logic_vector(2 downto 0) := "010";
constant cmdLowaddr_c : std_logic_vector(2 downto 0) := "011";
constant cmdIdle_c : std_logic_vector(2 downto 0) := "000";
--pdi_spi control signals
type fsm_t is (reset, reset1, reset2, reset3, idle, decode, waitwr, waitrd, wr, rd);
signal fsm : fsm_t;
signal addrReg : std_logic_vector(ap_address'left+2 downto 0);
signal cmd : std_logic_vector(2 downto 0);
signal highPriorLoad : std_logic;
signal highPriorLoadVal : std_logic_vector(spiSize_g-1 downto 0);
--spi core signals
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic_vector(spiSize_g-1 downto 0);
signal load : std_logic;
signal dout : std_logic_vector(spiSize_g-1 downto 0);
signal valid : std_logic;
--
signal ap_byteenable_s : std_logic_vector(ap_byteenable'range);
begin
clk <= ap_clk;
rst <= ap_reset;
ap_chipselect <= '1' when fsm = wr or fsm = rd or fsm = waitrd else '0';
ap_write <= '1' when fsm = wr else '0';
ap_read <= '1' when fsm = waitrd or fsm = rd else '0';
ap_address <= addrReg(addrReg'left downto 2);
ap_byteenable <= ap_byteenable_s;
ap_byteenable_s <= --little endian
"0001" when addrReg(1 downto 0) = "00" and spiBigEnd_g = false else
"0010" when addrReg(1 downto 0) = "01" and spiBigEnd_g = false else
"0100" when addrReg(1 downto 0) = "10" and spiBigEnd_g = false else
"1000" when addrReg(1 downto 0) = "11" and spiBigEnd_g = false else
--big endian
--"0001" when addrReg(1 downto 0) = "11" and spiBigEnd_g = true else
--"0010" when addrReg(1 downto 0) = "10" and spiBigEnd_g = true else
--"0100" when addrReg(1 downto 0) = "01" and spiBigEnd_g = true else
--"1000" when addrReg(1 downto 0) = "00" and spiBigEnd_g = true else
"0000";
ap_writedata <= (dout & dout & dout & dout);
din <= highPriorLoadVal when highPriorLoad = '1' else --load value that was just received
ap_readdata( 7 downto 0) when ap_byteenable_s = "0001" else
ap_readdata(15 downto 8) when ap_byteenable_s = "0010" else
ap_readdata(23 downto 16) when ap_byteenable_s = "0100" else
ap_readdata(31 downto 24) when ap_byteenable_s = "1000" else
(others => '0');
load <= '1' when highPriorLoad = '1' else --load value that was just received
'1' when fsm = rd else --load data from pdi to spi shift register
'0';
cmd <= dout(dout'left downto dout'left-2); --get cmd pattern
highPriorLoadVal <= not dout; --create inverse of received pattern
thePdiSpiFsm : process(clk, rst)
variable timeout : integer range 0 to 3;
variable writes : integer range 0 to 32;
variable reads : integer range 0 to 32;
begin
if rst = '1' then
fsm <= reset;
timeout := 0;
writes := 0; reads := 0;
addrReg <= (others => '0');
highPriorLoad <= '0';
elsif clk = '1' and clk'event then
--default assignment
highPriorLoad <= '0';
case fsm is
when reset =>
fsm <= reset;
if valid = '1' then
--load inverse pattern of received pattern
highPriorLoad <= '1';
if dout = cmdWakeUp then
--wake up command (1/4) received
fsm <= reset1;
else
--wake up command not decoded correctly
fsm <= reset;
end if;
end if;
when reset1 =>
fsm <= reset1;
if valid = '1' then
--load inverse pattern of received pattern
highPriorLoad <= '1';
if dout = cmdWakeUp1 then
--wake up command (2/4) sequence was correctly decoded!
fsm <= reset2;
else
--wake up command not decoded correctly
fsm <= reset;
end if;
end if;
when reset2 =>
fsm <= reset2;
if valid = '1' then
--load inverse pattern of received pattern
highPriorLoad <= '1';
if dout = cmdWakeUp2 then
--wake up command (3/4) sequence was correctly decoded!
fsm <= reset3;
else
--wake up command not decoded correctly
fsm <= reset;
end if;
end if;
when reset3 =>
fsm <= reset3;
if valid = '1' then
--load inverse pattern of received pattern
highPriorLoad <= '1';
if dout = cmdWakeUp3 then
--wake up command (4/4) sequence was correctly decoded!
fsm <= idle;
else
--wake up command not decoded correctly
fsm <= reset;
end if;
end if;
when idle =>
if writes /= 0 then
fsm <= waitwr;
elsif reads /= 0 and valid = '1' then
fsm <= waitrd;
elsif valid = '1' then
fsm <= decode;
else
fsm <= idle;
end if;
when decode =>
fsm <= idle; --default
case cmd is
when cmdHighaddr_c =>
addrReg(addrReg'left downto addrReg'left-4) <= dout(spiSize_g-4 downto 0);
when cmdMidaddr_c =>
addrReg(addrReg'left-5 downto addrReg'left-9) <= dout(spiSize_g-4 downto 0);
when cmdLowaddr_c =>
addrReg(addrReg'left-10 downto 0) <= dout(spiSize_g-4 downto 0);
when cmdWr_c =>
addrReg(addrReg'left-10 downto 0) <= dout(spiSize_g-4 downto 0);
fsm <= waitwr;
writes := 1;
when cmdRd_c =>
addrReg(addrReg'left-10 downto 0) <= dout(spiSize_g-4 downto 0);
fsm <= waitrd;
reads := 1;
when cmdWRSQ_c =>
fsm <= waitwr;
writes := conv_integer(dout(spiSize_g-4 downto 0)) + 1; --BYTES byte are written
when cmdRDSQ_c =>
fsm <= waitrd;
reads := conv_integer(dout(spiSize_g-4 downto 0)) + 1; --BYTES byte are read
when cmdIdle_c =>
--don't interpret the command, inverse pattern and goto idle
when others =>
--error, goto idle
end case;
when waitwr =>
--wait for data from spi master
if valid = '1' then
fsm <= wr;
else
fsm <= waitwr;
end if;
when waitrd =>
--spi master wants to read
--wait for dpr to read
if timeout = 3 then
fsm <= rd;
timeout := 0;
else
timeout := timeout + 1;
fsm <= waitrd;
end if;
when wr =>
fsm <= idle;
writes := writes - 1;
addrReg <= addrReg + 1;
when rd =>
fsm <= idle;
reads := reads - 1;
addrReg <= addrReg + 1;
end case;
end if;
end process;
theSpiCore : entity work.spi
generic map (
frameSize_g => spiSize_g,
cpol_g => cpol_g,
cpha_g => cpha_g
)
port map (
-- Control Interface
clk => clk,
rst => rst,
din => din,
load => load,
dout => dout,
valid => valid,
-- SPI
sck => spi_clk,
ss => spi_sel,
miso => spi_miso,
mosi => spi_mosi
);
end architecture rtl;
|
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_Std.all;
entity LED_mov is
port
(
Clk : in std_logic;
CalculateSIGNAL: in std_logic;
Uin : in std_logic_vector(7 downto 0);
Vin : in std_logic_vector(7 downto 0);
AverageValU : in std_logic_vector(15 downto 0);
AverageValV : in std_logic_vector(15 downto 0);
Column : unsigned(10 downto 0);
aclr : in std_logic;
LED1 : out std_logic;
LED2 : out std_logic
);
end LED_mov;
architecture str_LED of LED_mov is
signal AvUHigh : std_logic_vector(15 downto 0); --Threshold high value
signal AvULow : std_logic_vector(15 downto 0); --Threshold low value
begin
Average_thresh : process (AverageValU, AverageValV, aclr)
begin
if (aclr = '1') then
AvUHigh <= AverageValU + "0000000000000010";
AvULow <= AverageValU - "0000000000000010";
end if;
end process Average_thresh;
compare : process(Clk, Column, CalculateSIGNAL, Uin, Vin, AverageValU)
begin
if (CalculateSIGNAL'event) and (CalculateSIGNAL='1') then
if(Column <= "0010100000") then
if(AverageValU = Uin) then
LED1 <= '1';
else
LED1 <= '0';
end if;
end if;
end if;
end process compare;
end str_LED; |
-- quadrature_decoder_testbench - testbench for quadrature decoder
-- Written in 2016 by <Ahmet Inan> <[email protected]>
-- To the extent possible under law, the author(s) have dedicated all copyright and related and neighboring rights to this software to the public domain worldwide. This software is distributed without any warranty.
-- You should have received a copy of the CC0 Public Domain Dedication along with this software. If not, see <http://creativecommons.org/publicdomain/zero/1.0/>.
library ieee;
use ieee.std_logic_1164.all;
entity quadrature_decoder_testbench is
end quadrature_decoder_testbench;
architecture behavioral of quadrature_decoder_testbench is
signal clock : std_logic := '0';
signal a, b : std_logic := '0';
signal rotary : std_logic_vector (1 downto 0);
signal direction : std_logic;
signal pulse : std_logic;
signal done : boolean := false;
procedure noise(variable n : inout std_logic_vector(15 downto 0)) is
begin
-- Thanks Maxim on smspower for (reverse engineered?) specs.
-- Generator polynomial for noise channel of SN76489
-- used on the SMS is not irrereducible: X^16 + X^13 + 1
n := (n(0) xor n(3)) & n(15 downto 1);
end procedure;
procedure switch(
signal s : out std_logic;
constant v : std_logic;
variable n : inout std_logic_vector(15 downto 0)) is
begin
s <= v;
wait for 10 us;
for i in 1 to 19 loop
s <= n(0);
noise(n);
wait for 10 us;
end loop;
s <= v;
wait for 800 us;
end procedure;
begin
rotary <= b & a;
quadrature_decoder_inst : entity work.quadrature_decoder
port map (clock, rotary, direction, pulse);
clk_gen : process
begin
if done then
wait;
else
wait for 1 us;
clock <= not clock;
end if;
end process;
stimulus : process
variable n : std_logic_vector(15 downto 0) := (15 => '1', others => '0');
begin
-- start position
a <= '0';
b <= '0';
wait for 2 ms;
for j in 0 to 2 loop
for i in 0 to j loop
-- one step left
switch(a, '1', n);
switch(b, '1', n);
switch(a, '0', n);
switch(b, '0', n);
wait for 1 ms;
end loop;
for i in 0 to j loop
-- one step right
switch(b, '1', n);
switch(a, '1', n);
switch(b, '0', n);
switch(a, '0', n);
wait for 1 ms;
end loop;
end loop;
done <= true;
wait;
end process;
end behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity bin2bcd_12bit is
Port ( binIN : in STD_LOGIC_VECTOR (11 downto 0);
ones : out STD_LOGIC_VECTOR (3 downto 0);
tens : out STD_LOGIC_VECTOR (3 downto 0);
hundreds : out STD_LOGIC_VECTOR (3 downto 0);
thousands : out STD_LOGIC_VECTOR (3 downto 0)
);
end bin2bcd_12bit;
architecture Behavioral of bin2bcd_12bit is
begin
bcd1: process(binIN)
-- temporary variable
variable temp : STD_LOGIC_VECTOR (11 downto 0);
-- variable to store the output BCD number
-- organized as follows
-- thousands = bcd(15 downto 12)
-- hundreds = bcd(11 downto 8)
-- tens = bcd(7 downto 4)
-- units = bcd(3 downto 0)
variable bcd : UNSIGNED (15 downto 0) := (others => '0');
-- by
-- https://en.wikipedia.org/wiki/Double_dabble
begin
-- zero the bcd variable
bcd := (others => '0');
-- read input into temp variable
temp(11 downto 0) := binIN;
-- cycle 12 times as we have 12 input bits
-- this could be optimized, we dont need to check and add 3 for the
-- first 3 iterations as the number can never be >4
for i in 0 to 11 loop
if bcd(3 downto 0) > 4 then
bcd(3 downto 0) := bcd(3 downto 0) + 3;
end if;
if bcd(7 downto 4) > 4 then
bcd(7 downto 4) := bcd(7 downto 4) + 3;
end if;
if bcd(11 downto 8) > 4 then
bcd(11 downto 8) := bcd(11 downto 8) + 3;
end if;
-- thousands can't be >4 for a 12-bit input number
-- so don't need to do anything to upper 4 bits of bcd
-- shift bcd left by 1 bit, copy MSB of temp into LSB of bcd
bcd := bcd(14 downto 0) & temp(11);
-- shift temp left by 1 bit
temp := temp(10 downto 0) & '0';
end loop;
-- set outputs
ones <= STD_LOGIC_VECTOR(bcd(3 downto 0));
tens <= STD_LOGIC_VECTOR(bcd(7 downto 4));
hundreds <= STD_LOGIC_VECTOR(bcd(11 downto 8));
thousands <= STD_LOGIC_VECTOR(bcd(15 downto 12));
end process bcd1;
end Behavioral;
|
entity top is
end top;
architecture sim of top is
-------------- static value ----------------------
-- static value : enumeration
constant boolstr : string := "false";
constant off : boolean := boolean'value("FALSE");
-- static value : integer
constant numstr : string := "5";
-- static value : float
constant fpstr1 : string := "123.4567";
constant fpstr2 : string := "123.4567e-3";
constant fpstr3 : string := "-123.4567e4";
constant fp0 : real := real'value("123.4567");
constant fp1 : real := real'value(fpstr1);
constant fp2 : real := real'value(fpstr2);
constant fp3 : real := real'value(fpstr3);
-- static value : physical
constant t_val_static : time := time'value("123 ns");
-------------- static image ----------------------
-- static image : enumeration
constant bool_img1 : string := boolean'image(False);
constant bool_img2 : string := boolean'image(True);
-- static image : integer
constant int_img : string := integer'image(123);
-- static image : float
constant fpimg0 : string := real'image(fp0);
constant fpimg1 : string := real'image(fp1);
constant fpimg2 : string := real'image(fp2);
constant fpimg3 : string := real'image(fp3);
constant t_img_static : string := time'image(456 ps);
-- physical types always evaluated at runtime...
-------------- runtime value ----------------------
-- runtime integer
signal my_int : integer := 5;
signal my_str1 : string(1 to 1) := "5";
-- runtime boolean
signal my_bool : boolean := true;
-- runtime float
signal my_flt : real := 0.0;
-------------- runtime image ----------------------
-- runtime(signal) physical
signal t : time := time'value("789 US");
function t_img (t : time) return string is
begin
return time'image(t);
end t_img;
begin
-- Value tests : static enumeration expressions.
Assert boolean'value("FALSE") report "Bool Assertion triggered" severity NOTE;
Assert boolean'value(boolstr) report "Bool Assertion triggered" severity NOTE;
-- Value tests : static integer expressions.
Assert 2 + 2 = natural'value("5") report "Integer Assertion triggered" severity NOTE;
Assert 2 + 2 = natural'value(numstr) report "Integer Assertion triggered" severity NOTE;
-- Value tests : static real expressions.
Assert false report "real'value(""123.4567"" = " & real'image(fp0) severity NOTE;
-- Value tests : static physical expressions. Use time and at least one other phys unit.
Assert false report "123 ns is " & time'image(t_val_static) severity note;
-- To check compiler error diagnosis, uncomment these.
-- Assert boolean'value(79) report "Assertion triggered" severity NOTE;
-- Assert boolean'value(False) report "Assertion triggered" severity NOTE;
-- Assert boolean'value("SILLY") report "Assertion triggered" severity NOTE;
-- Image tests : static enumeration expressions.
Assert false report "Boolean can be " & boolean'image(True) & " or " & boolean'image(False) severity Note;
Assert false report "Static Boolean can be " & bool_img1 & " or " & bool_img2 severity Note;
-- Image tests : static integer expressions.
Assert false report "Integer image of 123 is " & int_img severity note;
-- Image tests : static real expressions.
Assert false report "123.4567" & " = " & fpimg0 severity note;
Assert false report "123.4567" & " = " & real'image(fp0) severity note;
Assert false report "124.4567" & " = " & real'image(fp0 + 1.0) severity note;
-- These assert despite nominally equal values.
Assert fp0 = real'value(fpimg0) report "123.4567" & " = " & fpimg0 severity note;
Assert fp1 = real'value(fpimg1) report fpstr1 & " = " & fpimg1 severity note;
Assert fp2 = real'value(fpimg2) report fpstr2 & " = " & fpimg2 severity note;
Assert fp3 = real'value(fpimg3) report fpstr3 & " = " & fpimg3 severity note;
-- So verify that the differences are not actually 0
Assert false report "fp0 - real'value(fpimg0) = " & real'image(fp0 - real'value(fpimg0)) severity note;
Assert false report "fp1 - real'value(fpimg1) = " & real'image(fp1 - real'value(fpimg1)) severity note;
Assert false report "fp2 - real'value(fpimg2) = " & real'image(fp2 - real'value(fpimg2)) severity note;
Assert false report "fp3 - real'value(fpimg3) = " & real'image(fp3 - real'value(fpimg3)) severity note;
-- Image tests : static physical expressions
Assert false report "456 ps is " & t_img_static severity note;
-- Value tests : runtime expressions
Assert boolean'value("FALSE") report "Assertion triggered" severity NOTE;
Assert boolean'value(boolstr) report "Assertion triggered" severity NOTE;
Assert my_bool report "Boolean my_bool = " & boolean'image(my_bool) severity NOTE;
my_str1(1) <= '6' after 1 ns, '4' after 2 ns;
my_flt <= fp0 after 3 ns;
my_bool <= False after 4 ns;
Assert my_flt = 0.0 report "my_flt = " & real'image(my_flt) severity note;
Assert 2 + 2 = natural'value(my_str1) report "RT Assertion 1 triggered" severity NOTE;
Assert 2 + 2 /= natural'value(my_str1) report "RT Assertion 2 triggered" severity NOTE;
Assert my_bool report "Boolean my_bool = " & boolean'image(my_bool) severity NOTE;
-- Image tests : runtime physical expressions.
Assert false report "Time " & t_img(123 us) severity note;
end sim;
|
entity top is
end top;
architecture sim of top is
-------------- static value ----------------------
-- static value : enumeration
constant boolstr : string := "false";
constant off : boolean := boolean'value("FALSE");
-- static value : integer
constant numstr : string := "5";
-- static value : float
constant fpstr1 : string := "123.4567";
constant fpstr2 : string := "123.4567e-3";
constant fpstr3 : string := "-123.4567e4";
constant fp0 : real := real'value("123.4567");
constant fp1 : real := real'value(fpstr1);
constant fp2 : real := real'value(fpstr2);
constant fp3 : real := real'value(fpstr3);
-- static value : physical
constant t_val_static : time := time'value("123 ns");
-------------- static image ----------------------
-- static image : enumeration
constant bool_img1 : string := boolean'image(False);
constant bool_img2 : string := boolean'image(True);
-- static image : integer
constant int_img : string := integer'image(123);
-- static image : float
constant fpimg0 : string := real'image(fp0);
constant fpimg1 : string := real'image(fp1);
constant fpimg2 : string := real'image(fp2);
constant fpimg3 : string := real'image(fp3);
constant t_img_static : string := time'image(456 ps);
-- physical types always evaluated at runtime...
-------------- runtime value ----------------------
-- runtime integer
signal my_int : integer := 5;
signal my_str1 : string(1 to 1) := "5";
-- runtime boolean
signal my_bool : boolean := true;
-- runtime float
signal my_flt : real := 0.0;
-------------- runtime image ----------------------
-- runtime(signal) physical
signal t : time := time'value("789 US");
function t_img (t : time) return string is
begin
return time'image(t);
end t_img;
begin
-- Value tests : static enumeration expressions.
Assert boolean'value("FALSE") report "Bool Assertion triggered" severity NOTE;
Assert boolean'value(boolstr) report "Bool Assertion triggered" severity NOTE;
-- Value tests : static integer expressions.
Assert 2 + 2 = natural'value("5") report "Integer Assertion triggered" severity NOTE;
Assert 2 + 2 = natural'value(numstr) report "Integer Assertion triggered" severity NOTE;
-- Value tests : static real expressions.
Assert false report "real'value(""123.4567"" = " & real'image(fp0) severity NOTE;
-- Value tests : static physical expressions. Use time and at least one other phys unit.
Assert false report "123 ns is " & time'image(t_val_static) severity note;
-- To check compiler error diagnosis, uncomment these.
-- Assert boolean'value(79) report "Assertion triggered" severity NOTE;
-- Assert boolean'value(False) report "Assertion triggered" severity NOTE;
-- Assert boolean'value("SILLY") report "Assertion triggered" severity NOTE;
-- Image tests : static enumeration expressions.
Assert false report "Boolean can be " & boolean'image(True) & " or " & boolean'image(False) severity Note;
Assert false report "Static Boolean can be " & bool_img1 & " or " & bool_img2 severity Note;
-- Image tests : static integer expressions.
Assert false report "Integer image of 123 is " & int_img severity note;
-- Image tests : static real expressions.
Assert false report "123.4567" & " = " & fpimg0 severity note;
Assert false report "123.4567" & " = " & real'image(fp0) severity note;
Assert false report "124.4567" & " = " & real'image(fp0 + 1.0) severity note;
-- These assert despite nominally equal values.
Assert fp0 = real'value(fpimg0) report "123.4567" & " = " & fpimg0 severity note;
Assert fp1 = real'value(fpimg1) report fpstr1 & " = " & fpimg1 severity note;
Assert fp2 = real'value(fpimg2) report fpstr2 & " = " & fpimg2 severity note;
Assert fp3 = real'value(fpimg3) report fpstr3 & " = " & fpimg3 severity note;
-- So verify that the differences are not actually 0
Assert false report "fp0 - real'value(fpimg0) = " & real'image(fp0 - real'value(fpimg0)) severity note;
Assert false report "fp1 - real'value(fpimg1) = " & real'image(fp1 - real'value(fpimg1)) severity note;
Assert false report "fp2 - real'value(fpimg2) = " & real'image(fp2 - real'value(fpimg2)) severity note;
Assert false report "fp3 - real'value(fpimg3) = " & real'image(fp3 - real'value(fpimg3)) severity note;
-- Image tests : static physical expressions
Assert false report "456 ps is " & t_img_static severity note;
-- Value tests : runtime expressions
Assert boolean'value("FALSE") report "Assertion triggered" severity NOTE;
Assert boolean'value(boolstr) report "Assertion triggered" severity NOTE;
Assert my_bool report "Boolean my_bool = " & boolean'image(my_bool) severity NOTE;
my_str1(1) <= '6' after 1 ns, '4' after 2 ns;
my_flt <= fp0 after 3 ns;
my_bool <= False after 4 ns;
Assert my_flt = 0.0 report "my_flt = " & real'image(my_flt) severity note;
Assert 2 + 2 = natural'value(my_str1) report "RT Assertion 1 triggered" severity NOTE;
Assert 2 + 2 /= natural'value(my_str1) report "RT Assertion 2 triggered" severity NOTE;
Assert my_bool report "Boolean my_bool = " & boolean'image(my_bool) severity NOTE;
-- Image tests : runtime physical expressions.
Assert false report "Time " & t_img(123 us) severity note;
end sim;
|
entity top is
end top;
architecture sim of top is
-------------- static value ----------------------
-- static value : enumeration
constant boolstr : string := "false";
constant off : boolean := boolean'value("FALSE");
-- static value : integer
constant numstr : string := "5";
-- static value : float
constant fpstr1 : string := "123.4567";
constant fpstr2 : string := "123.4567e-3";
constant fpstr3 : string := "-123.4567e4";
constant fp0 : real := real'value("123.4567");
constant fp1 : real := real'value(fpstr1);
constant fp2 : real := real'value(fpstr2);
constant fp3 : real := real'value(fpstr3);
-- static value : physical
constant t_val_static : time := time'value("123 ns");
-------------- static image ----------------------
-- static image : enumeration
constant bool_img1 : string := boolean'image(False);
constant bool_img2 : string := boolean'image(True);
-- static image : integer
constant int_img : string := integer'image(123);
-- static image : float
constant fpimg0 : string := real'image(fp0);
constant fpimg1 : string := real'image(fp1);
constant fpimg2 : string := real'image(fp2);
constant fpimg3 : string := real'image(fp3);
constant t_img_static : string := time'image(456 ps);
-- physical types always evaluated at runtime...
-------------- runtime value ----------------------
-- runtime integer
signal my_int : integer := 5;
signal my_str1 : string(1 to 1) := "5";
-- runtime boolean
signal my_bool : boolean := true;
-- runtime float
signal my_flt : real := 0.0;
-------------- runtime image ----------------------
-- runtime(signal) physical
signal t : time := time'value("789 US");
function t_img (t : time) return string is
begin
return time'image(t);
end t_img;
begin
-- Value tests : static enumeration expressions.
Assert boolean'value("FALSE") report "Bool Assertion triggered" severity NOTE;
Assert boolean'value(boolstr) report "Bool Assertion triggered" severity NOTE;
-- Value tests : static integer expressions.
Assert 2 + 2 = natural'value("5") report "Integer Assertion triggered" severity NOTE;
Assert 2 + 2 = natural'value(numstr) report "Integer Assertion triggered" severity NOTE;
-- Value tests : static real expressions.
Assert false report "real'value(""123.4567"" = " & real'image(fp0) severity NOTE;
-- Value tests : static physical expressions. Use time and at least one other phys unit.
Assert false report "123 ns is " & time'image(t_val_static) severity note;
-- To check compiler error diagnosis, uncomment these.
-- Assert boolean'value(79) report "Assertion triggered" severity NOTE;
-- Assert boolean'value(False) report "Assertion triggered" severity NOTE;
-- Assert boolean'value("SILLY") report "Assertion triggered" severity NOTE;
-- Image tests : static enumeration expressions.
Assert false report "Boolean can be " & boolean'image(True) & " or " & boolean'image(False) severity Note;
Assert false report "Static Boolean can be " & bool_img1 & " or " & bool_img2 severity Note;
-- Image tests : static integer expressions.
Assert false report "Integer image of 123 is " & int_img severity note;
-- Image tests : static real expressions.
Assert false report "123.4567" & " = " & fpimg0 severity note;
Assert false report "123.4567" & " = " & real'image(fp0) severity note;
Assert false report "124.4567" & " = " & real'image(fp0 + 1.0) severity note;
-- These assert despite nominally equal values.
Assert fp0 = real'value(fpimg0) report "123.4567" & " = " & fpimg0 severity note;
Assert fp1 = real'value(fpimg1) report fpstr1 & " = " & fpimg1 severity note;
Assert fp2 = real'value(fpimg2) report fpstr2 & " = " & fpimg2 severity note;
Assert fp3 = real'value(fpimg3) report fpstr3 & " = " & fpimg3 severity note;
-- So verify that the differences are not actually 0
Assert false report "fp0 - real'value(fpimg0) = " & real'image(fp0 - real'value(fpimg0)) severity note;
Assert false report "fp1 - real'value(fpimg1) = " & real'image(fp1 - real'value(fpimg1)) severity note;
Assert false report "fp2 - real'value(fpimg2) = " & real'image(fp2 - real'value(fpimg2)) severity note;
Assert false report "fp3 - real'value(fpimg3) = " & real'image(fp3 - real'value(fpimg3)) severity note;
-- Image tests : static physical expressions
Assert false report "456 ps is " & t_img_static severity note;
-- Value tests : runtime expressions
Assert boolean'value("FALSE") report "Assertion triggered" severity NOTE;
Assert boolean'value(boolstr) report "Assertion triggered" severity NOTE;
Assert my_bool report "Boolean my_bool = " & boolean'image(my_bool) severity NOTE;
my_str1(1) <= '6' after 1 ns, '4' after 2 ns;
my_flt <= fp0 after 3 ns;
my_bool <= False after 4 ns;
Assert my_flt = 0.0 report "my_flt = " & real'image(my_flt) severity note;
Assert 2 + 2 = natural'value(my_str1) report "RT Assertion 1 triggered" severity NOTE;
Assert 2 + 2 /= natural'value(my_str1) report "RT Assertion 2 triggered" severity NOTE;
Assert my_bool report "Boolean my_bool = " & boolean'image(my_bool) severity NOTE;
-- Image tests : runtime physical expressions.
Assert false report "Time " & t_img(123 us) severity note;
end sim;
|
-- Copyright (C) 2014 Roland Dobai
--
-- This file is part of ZyEHW.
--
-- ZyEHW is free software: you can redistribute it and/or modify it under the
-- terms of the GNU General Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your option) any later
-- version.
--
-- ZyEHW is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ZyEHW. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all;
use work.zyehw_pkg.all;
entity cgp_sync is
port (
cgp_clk: in std_logic;
axi_clk: in std_logic;
axi_start: in std_logic;
axi_mux_chromosome_arr: in mux_chromosome_arr_t;
cgp_fifo_almostfull: in std_logic;
cgp_fifo_ready: in std_logic;
cgp_data: in fifo_t;
cgp_datard: out std_logic;
axi_end: out std_logic;
axi_start_rst: out std_logic;
axi_frame_count: out frame_count_t;
axi_fitness_arr: out fitness_arr_t
);
end cgp_sync;
architecture struct_cgp_sync of cgp_sync is
component cgp is
port (
clk: in std_logic;
start: in std_logic;
mux_chromosome_arr: in mux_chromosome_arr_t;
fifo_almostfull: in std_logic;
fifo_ready: in std_logic;
data: in fifo_t;
datard: out std_logic;
frame_count: out frame_count_t;
fitness_arr: out fitness_arr_t;
fitness_wr: out std_logic;
start_rst: out std_logic
);
end component;
signal cgp_start, start_sync: std_logic;
signal cgp_mux_chromosome_arr, chrom_sync: mux_chromosome_arr_t;
signal cgp_fitness_arr, fitness_sync: fitness_arr_t;
signal fitness_reg: fitness_arr_t:= (others => (others => '1'));
signal cgp_fitness_wr: std_logic;
signal cgp_start_rst, start_rst_sync: std_logic;
signal end_arst, end_arst_sync, end_reg, end_sync: std_logic;
signal cgp_frame_count, frame_count_sync: frame_count_t;
begin
cgp_i: cgp
port map (
clk => cgp_clk,
start => cgp_start,
mux_chromosome_arr => cgp_mux_chromosome_arr,
fifo_almostfull => cgp_fifo_almostfull,
fifo_ready => cgp_fifo_ready,
data => cgp_data,
datard => cgp_datard,
frame_count => cgp_frame_count,
fitness_arr => cgp_fitness_arr,
fitness_wr => cgp_fitness_wr,
start_rst => cgp_start_rst
);
process (cgp_clk)
begin
if (cgp_clk'event and cgp_clk = '1') then
chrom_sync <= axi_mux_chromosome_arr;
cgp_mux_chromosome_arr <= chrom_sync;
start_sync <= axi_start;
cgp_start <= start_sync;
if (cgp_fitness_wr = '1') then
fitness_reg <= cgp_fitness_arr;
end if;
end if;
end process;
process (cgp_clk, end_arst)
begin
if (end_arst = '1') then
end_reg <= '0';
else
if (cgp_clk'event and cgp_clk = '1') then
if (cgp_fitness_wr = '1') then
end_reg <= '1';
end if;
end if;
end if;
end process;
process (axi_clk, cgp_start_rst)
begin
if (cgp_start_rst = '1') then
axi_start_rst <= '1';
start_rst_sync <= '1';
else
if (axi_clk'event and axi_clk = '1') then
start_rst_sync <= '0';
axi_start_rst <= start_rst_sync;
end if;
end if;
end process;
process (cgp_clk, axi_start)
begin
if (axi_start = '1') then
end_arst <= '1';
end_arst_sync <= '1';
else
if (cgp_clk'event and cgp_clk = '1') then
end_arst_sync <= '0';
end_arst <= end_arst_sync;
end if;
end if;
end process;
process (axi_clk)
begin
if (axi_clk'event and axi_clk = '1') then
end_sync <= end_reg;
axi_end <= end_sync;
fitness_sync <= fitness_reg;
axi_fitness_arr <= fitness_sync;
frame_count_sync <= cgp_frame_count;
axi_frame_count <= frame_count_sync;
end if;
end process;
end struct_cgp_sync;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/26/2015 01:55:45 PM
-- Design Name:
-- Module Name: AES128_V1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity AES128_V1 is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
ENABLE : in STD_LOGIC;
READY_TO_DECRYPT : out STD_LOGIC;
WORD_IN : in STD_LOGIC_VECTOR (31 downto 0);
WORD_OUT : out STD_LOGIC_VECTOR (31 downto 0));
end AES128_V1;
architecture Behavioral of AES128_V1 is
component keyExpansion is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
START : in STD_LOGIC;
cipherKey : in STD_LOGIC_VECTOR (127 downto 0);
DONE : out STD_LOGIC;
IDLE : out STD_LOGIC;
MUTATING : out STD_LOGIC;
expandedKey : out STD_LOGIC_VECTOR (1407 downto 0));
end component;
component controlUnit is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
ENABLE : in STD_LOGIC;
loadSourceSelector : out STD_LOGIC;
addRoundKeySelector1 : out STD_LOGIC_VECTOR(1 downto 0);
addRoundKeySelector2 : out STD_LOGIC_VECTOR(1 downto 0)
);
end component;
component addRoundKey is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
wordIn : in STD_LOGIC_VECTOR (31 downto 0);
keyIn : in STD_LOGIC_VECTOR (31 downto 0);
wordOut : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component memoryUnit is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
SELB : in STD_LOGIC;
wordAIn : in STD_LOGIC_VECTOR (31 downto 0);
wordBin : in STD_LOGIC_VECTOR (31 downto 0);
wordOut : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component invShiftRows is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
blockIn : in STD_LOGIC_VECTOR (127 downto 0);
blockOut : out STD_LOGIC_VECTOR (127 downto 0));
end component;
component invSubByte is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
byteIn : in STD_LOGIC_VECTOR(7 downto 0);
byteOut : out STD_LOGIC_VECTOR(7 downto 0));
end component;
component invMixColumn is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
wordIn : in STD_LOGIC_VECTOR (31 downto 0);
wordOut : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component decryptionLoopCore_V1 is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
memorySourceSelector : in STD_LOGIC;
keySelector : in STD_LOGIC_VECTOR (1 downto 0);
cipherKey : in STD_LOGIC_VECTOR (127 downto 0);
WORD_IN : in STD_LOGIC_VECTOR (31 downto 0);
WORD_OUT : out STD_LOGIC_VECTOR (31 downto 0));
end component;
component decryptionFinalCore_V1 is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
memorySourceSelector : in STD_LOGIC;
keySelector : in STD_LOGIC_VECTOR (1 downto 0);
cipherKey : in STD_LOGIC_VECTOR (127 downto 0);
WORD_IN : in STD_LOGIC_VECTOR (31 downto 0);
WORD_OUT : out STD_LOGIC_VECTOR (31 downto 0));
end component;
signal keyExpansion_EN : STD_LOGIC;
signal controlUnit_EN : STD_LOGIC;
signal keyExpansion_DONE : STD_LOGIC;
signal controlUnit_ENABLE : STD_LOGIC;
signal mu1_Out, mu2_Out, mu3_out : STD_LOGIC_VECTOR(31 downto 0);
signal cipherKey : STD_LOGIC_VECTOR(127 downto 0);
--The expanded key and aliases to improve readability.
--Key0 is the original key (same key as was input)
--Key10 is the last expanded key (first used in decrption / last used in encryption)
signal expandedKey : STD_LOGIC_VECTOR(1407 downto 0);
alias key0 : STD_LOGIC_VECTOR(127 downto 0) is expandedKey(1407 downto 1280);
alias key1 : STD_LOGIC_VECTOR(127 downto 0) is expandedKey(1279 downto 1152);
alias key2 : STD_LOGIC_VECTOR(127 downto 0) is expandedKey(1151 downto 1024);
alias key3 : STD_LOGIC_VECTOR(127 downto 0) is expandedKey(1023 downto 896);
alias key4 : STD_LOGIC_VECTOR(127 downto 0) is expandedKey(895 downto 768);
alias key5 : STD_LOGIC_VECTOR(127 downto 0) is expandedKey(767 downto 640);
alias key6 : STD_LOGIC_VECTOR(127 downto 0) is expandedKey(639 downto 512);
alias key7 : STD_LOGIC_VECTOR(127 downto 0) is expandedKey(511 downto 384);
alias key8 : STD_LOGIC_VECTOR(127 downto 0) is expandedKey(383 downto 256);
alias key9 : STD_LOGIC_VECTOR(127 downto 0) is expandedKey(255 downto 128);
alias key10 : STD_LOGIC_VECTOR(127 downto 0) is expandedKey(127 downto 0);
signal addRoundKey_Key10 : STD_LOGIC_VECTOR(31 downto 0);
signal addRoundKey0_Out : STD_LOGIC_VECTOR(31 downto 0);
--Control Unit output Signals
signal loadSourceSelector : STD_LOGIC;
signal addRoundKeySelector1, addRoundKeySelector2 : STD_LOGIC_VECTOR(1 downto 0);
--Decryption loop interconnect signals.
signal decryptLoop8_Out,
decryptLoop7_Out,
decryptLoop6_Out,
decryptLoop5_Out,
decryptLoop4_Out,
decryptLoop3_Out,
decryptLoop2_Out,
decryptLoop1_Out,
decryptLoop0_Out : STD_LOGIC_VECTOR(31 downto 0);
--ZERO signals to connect to the unused ports in some of the memory units
signal ZERO : STD_LOGIC:= '0';
signal ZEROES : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
begin
ZERO <= '0';
ZEROES <= (others => '0');
READY_TO_DECRYPT <= controlUnit_ENABLE;
mainProcess: process(CLK, RESET)
variable wordCount : NATURAL range 0 to 2 := 0;
type STATE_TYPE is (RECEIVE_KEY, EXPAND_KEY, DECRYPT);
variable state : STATE_TYPE := RECEIVE_KEY;
begin
if RESET = '1' then
state := RECEIVE_KEY;
wordCount := 0;
elsif rising_edge(CLK)then
keyExpansion_EN <= '0';
if ENABLE = '1' then
case state is
when RECEIVE_KEY =>
if wordCount >= 2 then
keyExpansion_EN <= '1';
state := EXPAND_KEY;
else
wordCount := wordCount + 1;
end if;
when EXPAND_KEY =>
if keyExpansion_DONE = '1' then
state := DECRYPT;
end if;
when DECRYPT =>
state := DECRYPT;
when others =>
state := RECEIVE_KEY;
end case;
end if;
end if;
end process;
enableControlUnitLatch: process(keyExpansion_DONE, RESET)
begin
if RESET = '1' then
controlUnit_Enable <= '0';
elsif keyExpansion_DONE = '1' then
controlUnit_Enable <= '1';
end if;
end process;
mu1: memoryUnit port map( CLK => CLK,
RESET => RESET,
SELB => ZERO,
wordAIn => WORD_IN,
wordBIn => ZEROES,
wordOut => mu1_Out);
mu2: memoryUnit port map( CLK => CLK,
RESET => RESET,
SELB => ZERO,
wordAIn => mu1_Out,
wordBIn => ZEROES,
wordOut => mu2_Out);
mu3: memoryUnit port map( CLK => CLK,
RESET => RESET,
SELB => ZERO,
wordAIn => mu2_Out,
wordBIn => ZEROES,
wordOut => mu3_Out);
cipherKey <= mu3_Out & mu2_Out & mu1_Out & WORD_IN;
keyExp: keyExpansion port map( CLK => CLK,
RESET => RESET,
START => keyExpansion_EN,
cipherKey => cipherKey,
DONE => keyExpansion_DONE,
IDLE => open,
MUTATING => open,
expandedKey => expandedKey);
ctrlUnit: controlUnit port map( CLK => CLK,
RESET => RESET,
ENABLE => controlUnit_ENABLE,
loadSourceSelector => loadSourceSelector,
addRoundKeySelector1 => addRoundKeySelector1,
addRoundKeySelector2 => addRoundKeySelector2);
--This is the selector for the word that needs to be added in the addRoundKey stage BEFORE the decryption loop.
addRoundKeySelector0: process(key10, addRoundKeySelector1)
begin
case addRoundKeySelector1 is
when "11" => addRoundKey_Key10 <= key10(127 downto 96);
when "10" => addRoundKey_Key10 <= key10(95 downto 64);
when "01" => addRoundKey_Key10 <= key10(63 downto 32);
when "00" => addRoundKey_Key10 <= key10(31 downto 0);
when others => addRoundKey_Key10 <= (others => '0');
end case;
end process;
addRoundKey0: addRoundKey port map( CLK => CLK,
RESET => RESET,
wordIn => WORD_IN,
keyIn => addRoundKey_Key10,
wordOut => addRoundKey0_Out);
--BEGIN DECRYPTION LOOP
--The decryption loop consists of 9 iterations of the steps:
-- 1) invertShiftRows
-- 2) invertSubBytes
-- 3) addRoundKey
-- 4) invertMixColumns
decryptLoop0: decryptionLoopCore_V1 port map( CLK => CLK,
RESET => RESET,
memorySourceSelector => loadSourceSelector,
keySelector => addRoundKeySelector2,
cipherKey => key9,
WORD_IN => addRoundKey0_Out,
WORD_OUT => decryptLoop0_out);
decryptLoop1: decryptionLoopCore_V1 port map( CLK => CLK,
RESET => RESET,
memorySourceSelector => loadSourceSelector,
keySelector => addRoundKeySelector2,
cipherKey => key8,
WORD_IN => decryptLoop0_out,
WORD_OUT => decryptLoop1_out);
decryptLoop2: decryptionLoopCore_V1 port map( CLK => CLK,
RESET => RESET,
memorySourceSelector => loadSourceSelector,
keySelector => addRoundKeySelector2,
cipherKey => key7,
WORD_IN => decryptLoop1_out,
WORD_OUT => decryptLoop2_out);
decryptLoop3: decryptionLoopCore_V1 port map( CLK => CLK,
RESET => RESET,
memorySourceSelector => loadSourceSelector,
keySelector => addRoundKeySelector2,
cipherKey => key6,
WORD_IN => decryptLoop2_out,
WORD_OUT => decryptLoop3_out);
decryptLoop4: decryptionLoopCore_V1 port map( CLK => CLK,
RESET => RESET,
memorySourceSelector => loadSourceSelector,
keySelector => addRoundKeySelector2,
cipherKey => key5,
WORD_IN => decryptLoop3_out,
WORD_OUT => decryptLoop4_out);
decryptLoop5: decryptionLoopCore_V1 port map( CLK => CLK,
RESET => RESET,
memorySourceSelector => loadSourceSelector,
keySelector => addRoundKeySelector2,
cipherKey => key4,
WORD_IN => decryptLoop4_out,
WORD_OUT => decryptLoop5_out);
decryptLoop6: decryptionLoopCore_V1 port map( CLK => CLK,
RESET => RESET,
memorySourceSelector => loadSourceSelector,
keySelector => addRoundKeySelector2,
cipherKey => key3,
WORD_IN => decryptLoop5_out,
WORD_OUT => decryptLoop6_out);
decryptLoop7: decryptionLoopCore_V1 port map( CLK => CLK,
RESET => RESET,
memorySourceSelector => loadSourceSelector,
keySelector => addRoundKeySelector2,
cipherKey => key2,
WORD_IN => decryptLoop6_out,
WORD_OUT => decryptLoop7_out);
decryptLoop8: decryptionLoopCore_V1 port map( CLK => CLK,
RESET => RESET,
memorySourceSelector => loadSourceSelector,
keySelector => addRoundKeySelector2,
cipherKey => key1,
WORD_IN => decryptLoop7_out,
WORD_OUT => decryptLoop8_out);
decryptFinalStep: decryptionFinalCore_V1 port map( CLK => CLK,
RESET => RESET,
memorySourceSelector => loadSourceSelector,
keySelector => addRoundKeySelector2,
cipherKey => key0,
WORD_IN => decryptLoop8_out,
WORD_OUT => WORD_OUT);
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity antirrebote_vector is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
vector_IN : in STD_LOGIC_VECTOR (2 downto 0);
vector_OUT : out STD_LOGIC_VECTOR(2 downto 0));
end antirrebote_vector;
architecture Dataflow of antirrebote_vector is
COMPONENT antirrebote
PORT (
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
logic_IN : in STD_LOGIC;
logic_OUT : out STD_LOGIC);
END COMPONENT;
begin
inst_antirrebote_1:antirrebote port map(
CLK => CLK,
RST => RST,
logic_IN => vector_IN(0),
logic_OUT => vector_OUT(0)
);
inst_antirrebote_2:antirrebote port map(
CLK => CLK,
RST => RST,
logic_IN => vector_IN(1),
logic_OUT => vector_OUT(1)
);
inst_antirrebote_3:antirrebote port map(
CLK => CLK,
RST => RST,
logic_IN => vector_IN(2),
logic_OUT => vector_OUT(2)
);
end Dataflow; |
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_aa_e
--
-- Generated
-- by: wig
-- on: Fri Jul 25 11:14:37 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_aa_e-e.vhd,v 1.1 2004/04/06 11:06:39 wig Exp $
-- $Date: 2004/04/06 11:06:39 $
-- $Log: inst_aa_e-e.vhd,v $
-- Revision 1.1 2004/04/06 11:06:39 wig
-- Adding result/init
--
-- Revision 1.1 2003/11/27 09:15:06 abauer
-- *** empty log message ***
--
-- Revision 1.1 2003/10/13 08:55:35 wig
-- Add lots of testcases:
-- padio
-- padio2
-- verilog
-- autoopen
-- typecast
-- ....
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.22 2003/07/23 13:34:40 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.13 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_aa_e
--
entity inst_aa_e is
-- Generics:
generic(
-- Generated Generics for Entity inst_aa_e
NO_DEFAULT : string; -- __W_NODEFAULT
NO_NAME : string; -- __W_NODEFAULT
WIDTH : integer := 7
-- End of Generated Generics for Entity inst_aa_e
);
-- Generated Port Declaration:
-- No Generated Port for Entity inst_aa_e
end inst_aa_e;
--
-- End of Generated Entity inst_aa_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_tofpt-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
architecture bench of to_fp_test is
signal vec : std_ulogic_vector(15 downto 0);
signal r : real;
begin
dut : entity work.to_fp(behavioral)
port map (vec, r);
stimulus : process is
begin
vec <= X"0000"; wait for 10 ns;
vec <= X"8000"; wait for 10 ns;
vec <= X"7FFF"; wait for 10 ns;
vec <= X"4000"; wait for 10 ns;
vec <= X"C000"; wait for 10 ns;
wait;
end process stimulus;
end architecture bench;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_tofpt-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
architecture bench of to_fp_test is
signal vec : std_ulogic_vector(15 downto 0);
signal r : real;
begin
dut : entity work.to_fp(behavioral)
port map (vec, r);
stimulus : process is
begin
vec <= X"0000"; wait for 10 ns;
vec <= X"8000"; wait for 10 ns;
vec <= X"7FFF"; wait for 10 ns;
vec <= X"4000"; wait for 10 ns;
vec <= X"C000"; wait for 10 ns;
wait;
end process stimulus;
end architecture bench;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_tofpt-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
architecture bench of to_fp_test is
signal vec : std_ulogic_vector(15 downto 0);
signal r : real;
begin
dut : entity work.to_fp(behavioral)
port map (vec, r);
stimulus : process is
begin
vec <= X"0000"; wait for 10 ns;
vec <= X"8000"; wait for 10 ns;
vec <= X"7FFF"; wait for 10 ns;
vec <= X"4000"; wait for 10 ns;
vec <= X"C000"; wait for 10 ns;
wait;
end process stimulus;
end architecture bench;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 13:53:00 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top affine_block_ieee754_fp_adder_subtractor_0_0 -prefix
-- affine_block_ieee754_fp_adder_subtractor_0_0_ affine_block_ieee754_fp_adder_subtractor_0_1_stub.vhdl
-- Design : affine_block_ieee754_fp_adder_subtractor_0_1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity affine_block_ieee754_fp_adder_subtractor_0_0 is
Port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end affine_block_ieee754_fp_adder_subtractor_0_0;
architecture stub of affine_block_ieee754_fp_adder_subtractor_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "x[31:0],y[31:0],z[31:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "ieee754_fp_adder_subtractor,Vivado 2016.4";
begin
end;
|
-- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - square.vhd
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: Square wave generator
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity square is
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
incr : in signed(31 downto 0);
offset : in signed(31 downto 0);
duty_on : in signed(31 downto 0);
duty_off: in signed(31 downto 0);
sq : out signed(31 downto 0)
);
end square;
architecture Behavioral of square is
constant last_int : integer := integer(SOUNDGATE_FIX_PT_SCALING) + 1;
constant pi : signed (31 downto 0) := to_signed(integer(real(MATH_PI * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
constant two_pi : signed (31 downto 0) := to_signed(integer(real(2.0 *MATH_PI* 2**SOUNDGATE_FIX_PT_SCALING)), 32);
constant upper : signed (31 downto 0) := to_signed(integer(real( 1.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
constant lower : signed (31 downto 0) := to_signed(integer(real(-1.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
--constant add : signed (31 downto 0) := to_signed(integer(real(0.01 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal x : signed (31 downto 0) := to_signed(integer(real( 0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal square : signed (31 downto 0) := upper;
begin
sq <= square;
CALC_SQ : process (clk, rst)
begin
if rst = '1' then
x <= offset;
else
if rising_edge(clk) then
if ce = '1' then
x <= x + incr;
if x >= to_signed(integer(real( 0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32) then
square <= upper;
elsif x >= duty_on then --to_signed(integer(real( 1.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32) then
square <= lower;
elsif x >= duty_off then --to_signed(integer(real( 2.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32) then
square <= upper;
x <= to_signed(integer(real(0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_eab_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_eab_e-rtl-a.vhd,v 1.1 2004/04/06 10:49:57 wig Exp $
-- $Date: 2004/04/06 10:49:57 $
-- $Log: inst_eab_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:49:57 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_eab_e
--
architecture rtl of inst_eab_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_69x512_top IS
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(69-1 DOWNTO 0);
DOUT : OUT std_logic_vector(69-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
--!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Helper package with useful functions
--! @author Markus Fehrenz
--! @date 2011/12/02
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pkg_helper is
--!
--! Return the log_2 of an natural value, i.e. the number of bits required
--! to represent this unsigned value.
--!
function no_bits_natural(value_in : natural) return natural;
--! Return maximum of two input values
function max(value_in_a, value_in_b : natural) return natural;
end pkg_helper;
package body pkg_helper is
function no_bits_natural(value_in: natural) return natural is
variable v_n_bit : unsigned(31 downto 0);
begin
if value_in = 0 then
return 0;
end if;
v_n_bit := to_unsigned(value_in, 32);
for i in 31 downto 0 loop
if v_n_bit(i) = '1' then
return i + 1;
end if;
end loop;
return 1;
end no_bits_natural;
function max(value_in_a, value_in_b : natural) return natural is
begin
if value_in_a > value_in_b then
return value_in_a;
else
return value_in_b;
end if;
end function;
end pkg_helper;
|
--!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Helper package with useful functions
--! @author Markus Fehrenz
--! @date 2011/12/02
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pkg_helper is
--!
--! Return the log_2 of an natural value, i.e. the number of bits required
--! to represent this unsigned value.
--!
function no_bits_natural(value_in : natural) return natural;
--! Return maximum of two input values
function max(value_in_a, value_in_b : natural) return natural;
end pkg_helper;
package body pkg_helper is
function no_bits_natural(value_in: natural) return natural is
variable v_n_bit : unsigned(31 downto 0);
begin
if value_in = 0 then
return 0;
end if;
v_n_bit := to_unsigned(value_in, 32);
for i in 31 downto 0 loop
if v_n_bit(i) = '1' then
return i + 1;
end if;
end loop;
return 1;
end no_bits_natural;
function max(value_in_a, value_in_b : natural) return natural is
begin
if value_in_a > value_in_b then
return value_in_a;
else
return value_in_b;
end if;
end function;
end pkg_helper;
|
-- file: pll_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
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--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity pll_tb is
end pll_tb;
architecture test of pll_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 10.000 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(2 downto 1);
-- Status and control signals
signal RESET : std_logic := '0';
signal LOCKED : std_logic;
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(2 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component pll_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(2 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1);
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
RESET <= '1';
wait for (PER1*6);
RESET <= '0';
wait until LOCKED = '1';
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : pll_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT,
-- Status and control signals
RESET => RESET,
LOCKED => LOCKED);
-- Freq Check
end test;
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