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-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_gnd is
port (
output : out std_logic
);
end entity alt_dspbuilder_gnd;
architecture rtl of alt_dspbuilder_gnd is
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_gnd_GN;
begin
alt_dspbuilder_gnd_GN_0: if true generate
inst_alt_dspbuilder_gnd_GN_0: alt_dspbuilder_gnd_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_gnd is
port (
output : out std_logic
);
end entity alt_dspbuilder_gnd;
architecture rtl of alt_dspbuilder_gnd is
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_gnd_GN;
begin
alt_dspbuilder_gnd_GN_0: if true generate
inst_alt_dspbuilder_gnd_GN_0: alt_dspbuilder_gnd_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_gnd is
port (
output : out std_logic
);
end entity alt_dspbuilder_gnd;
architecture rtl of alt_dspbuilder_gnd is
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_gnd_GN;
begin
alt_dspbuilder_gnd_GN_0: if true generate
inst_alt_dspbuilder_gnd_GN_0: alt_dspbuilder_gnd_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_gnd is
port (
output : out std_logic
);
end entity alt_dspbuilder_gnd;
architecture rtl of alt_dspbuilder_gnd is
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_gnd_GN;
begin
alt_dspbuilder_gnd_GN_0: if true generate
inst_alt_dspbuilder_gnd_GN_0: alt_dspbuilder_gnd_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_gnd is
port (
output : out std_logic
);
end entity alt_dspbuilder_gnd;
architecture rtl of alt_dspbuilder_gnd is
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_gnd_GN;
begin
alt_dspbuilder_gnd_GN_0: if true generate
inst_alt_dspbuilder_gnd_GN_0: alt_dspbuilder_gnd_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_gnd is
port (
output : out std_logic
);
end entity alt_dspbuilder_gnd;
architecture rtl of alt_dspbuilder_gnd is
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_gnd_GN;
begin
alt_dspbuilder_gnd_GN_0: if true generate
inst_alt_dspbuilder_gnd_GN_0: alt_dspbuilder_gnd_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_gnd is
port (
output : out std_logic
);
end entity alt_dspbuilder_gnd;
architecture rtl of alt_dspbuilder_gnd is
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_gnd_GN;
begin
alt_dspbuilder_gnd_GN_0: if true generate
inst_alt_dspbuilder_gnd_GN_0: alt_dspbuilder_gnd_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_gnd is
port (
output : out std_logic
);
end entity alt_dspbuilder_gnd;
architecture rtl of alt_dspbuilder_gnd is
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_gnd_GN;
begin
alt_dspbuilder_gnd_GN_0: if true generate
inst_alt_dspbuilder_gnd_GN_0: alt_dspbuilder_gnd_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_gnd is
port (
output : out std_logic
);
end entity alt_dspbuilder_gnd;
architecture rtl of alt_dspbuilder_gnd is
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_gnd_GN;
begin
alt_dspbuilder_gnd_GN_0: if true generate
inst_alt_dspbuilder_gnd_GN_0: alt_dspbuilder_gnd_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_gnd is
port (
output : out std_logic
);
end entity alt_dspbuilder_gnd;
architecture rtl of alt_dspbuilder_gnd is
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_gnd_GN;
begin
alt_dspbuilder_gnd_GN_0: if true generate
inst_alt_dspbuilder_gnd_GN_0: alt_dspbuilder_gnd_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_gnd is
port (
output : out std_logic
);
end entity alt_dspbuilder_gnd;
architecture rtl of alt_dspbuilder_gnd is
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_gnd_GN;
begin
alt_dspbuilder_gnd_GN_0: if true generate
inst_alt_dspbuilder_gnd_GN_0: alt_dspbuilder_gnd_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_gnd is
port (
output : out std_logic
);
end entity alt_dspbuilder_gnd;
architecture rtl of alt_dspbuilder_gnd is
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_gnd_GN;
begin
alt_dspbuilder_gnd_GN_0: if true generate
inst_alt_dspbuilder_gnd_GN_0: alt_dspbuilder_gnd_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_gnd is
port (
output : out std_logic
);
end entity alt_dspbuilder_gnd;
architecture rtl of alt_dspbuilder_gnd is
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_gnd_GN;
begin
alt_dspbuilder_gnd_GN_0: if true generate
inst_alt_dspbuilder_gnd_GN_0: alt_dspbuilder_gnd_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_gnd is
port (
output : out std_logic
);
end entity alt_dspbuilder_gnd;
architecture rtl of alt_dspbuilder_gnd is
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_gnd_GN;
begin
alt_dspbuilder_gnd_GN_0: if true generate
inst_alt_dspbuilder_gnd_GN_0: alt_dspbuilder_gnd_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_gnd is
port (
output : out std_logic
);
end entity alt_dspbuilder_gnd;
architecture rtl of alt_dspbuilder_gnd is
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_gnd_GN;
begin
alt_dspbuilder_gnd_GN_0: if true generate
inst_alt_dspbuilder_gnd_GN_0: alt_dspbuilder_gnd_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_gnd is
port (
output : out std_logic
);
end entity alt_dspbuilder_gnd;
architecture rtl of alt_dspbuilder_gnd is
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_gnd_GN;
begin
alt_dspbuilder_gnd_GN_0: if true generate
inst_alt_dspbuilder_gnd_GN_0: alt_dspbuilder_gnd_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_gnd is
port (
output : out std_logic
);
end entity alt_dspbuilder_gnd;
architecture rtl of alt_dspbuilder_gnd is
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_gnd_GN;
begin
alt_dspbuilder_gnd_GN_0: if true generate
inst_alt_dspbuilder_gnd_GN_0: alt_dspbuilder_gnd_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_gnd is
port (
output : out std_logic
);
end entity alt_dspbuilder_gnd;
architecture rtl of alt_dspbuilder_gnd is
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_gnd_GN;
begin
alt_dspbuilder_gnd_GN_0: if true generate
inst_alt_dspbuilder_gnd_GN_0: alt_dspbuilder_gnd_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_gnd is
port (
output : out std_logic
);
end entity alt_dspbuilder_gnd;
architecture rtl of alt_dspbuilder_gnd is
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_gnd_GN;
begin
alt_dspbuilder_gnd_GN_0: if true generate
inst_alt_dspbuilder_gnd_GN_0: alt_dspbuilder_gnd_GN
port map(output => output);
end generate;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_gnd is
port (
output : out std_logic
);
end entity alt_dspbuilder_gnd;
architecture rtl of alt_dspbuilder_gnd is
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_gnd_GN;
begin
alt_dspbuilder_gnd_GN_0: if true generate
inst_alt_dspbuilder_gnd_GN_0: alt_dspbuilder_gnd_GN
port map(output => output);
end generate;
end architecture rtl;
|
--
-- Transceiver Loop
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2016-2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library FPGALIB;
use FPGALIB.verif.all;
entity TransLoop is
generic (
DBYTES : positive:=4; -- Data bytes
TSIZE : positive:=1e4; -- Total size
FSIZE : positive:=2048 -- Frame size
);
port (
-- TX side
tx_clk_i : in std_logic;
tx_rst_i : in std_logic;
tx_data_i : in std_logic_vector(DBYTES*8-1 downto 0);
tx_data_o : out std_logic_vector(DBYTES*8-1 downto 0);
tx_isk_o : out std_logic_vector(DBYTES-1 downto 0);
tx_ready_i : in std_logic;
-- RX side
rx_clk_i : in std_logic;
rx_rst_i : in std_logic;
rx_data_i : in std_logic_vector(DBYTES*8-1 downto 0);
rx_isk_i : in std_logic_vector(DBYTES-1 downto 0);
rx_errors_o : out std_logic_vector(4 downto 0);
rx_finish_o : out std_logic;
rx_cycles_o : out std_logic_vector(31 downto 0)
);
end entity TransLoop;
architecture RTL of TransLoop is
constant K28_5 : std_logic_vector(7 downto 0):=x"BC";
constant K28_1 : std_logic_vector(7 downto 0):=x"3C";
constant DWIDTH : positive:=DBYTES*8;
signal rx_data, tx_data : std_logic_vector(DWIDTH-1 downto 0);
signal rx_stb, tx_stb : std_logic;
signal rx_cnt, tx_cnt : unsigned(DWIDTH-1 downto 0);
signal rx_cycles : unsigned(31 downto 0);
type state_t is (IDLE, STROBE, ACK, TRANSFER, GAP, FINISH);
signal tx_state, rx_state : state_t:=IDLE;
function repeat (value: std_logic_vector; num: positive) return std_logic_vector is
variable retval : std_logic_vector(num*8-1 downto 0);
begin
for i in 1 to num loop
retval(i*8-1 downto (i-1)*8):=value;
end loop;
return retval;
end repeat;
constant tied_to_vcc : std_logic_vector(DWIDTH-1 downto 0):=(others => '1');
constant tied_to_gnd : std_logic_vector(DWIDTH-1 downto 0):=(others => '0');
begin
loop_i: LoopCheck
generic map (DWIDTH => DWIDTH)
port map(
-- TX side
tx_clk_i => tx_clk_i,
tx_rst_i => tx_rst_i,
tx_stb_i => tx_stb,
tx_data_i => tx_data_i,
tx_data_o => tx_data,
-- RX side
rx_clk_i => rx_clk_i,
rx_rst_i => rx_rst_i,
rx_stb_i => rx_stb,
rx_data_i => rx_data,
rx_errors_o => rx_errors_o
);
tx_fsm: process(tx_clk_i) is
begin
if rising_edge(tx_clk_i) then
if tx_rst_i='1' then
tx_state <= IDLE;
tx_isk_o <= (others => '0');
tx_data_o <= (others => '0');
tx_cnt <= (others => '0');
tx_stb <= '0';
else
case tx_state is
when IDLE =>
if tx_ready_i='1' then
tx_state <= STROBE;
end if;
when STROBE =>
tx_isk_o <= (others => '1');
tx_data_o <= repeat(K28_5,DBYTES);
tx_state <= ACK;
when ACK =>
if rx_data_i=repeat(K28_5,DBYTES) and rx_isk_i=tied_to_vcc(DBYTES-1 downto 0) then
tx_state <= TRANSFER;
tx_stb <= '1';
end if;
when TRANSFER =>
tx_isk_o <= (others => '0');
tx_data_o <= tx_data;
tx_cnt <= tx_cnt+1;
if tx_cnt=TSIZE-1 then
tx_stb <= '0';
tx_state <= FINISH;
elsif (tx_cnt mod FSIZE = FSIZE-1) then
tx_state <= GAP;
tx_stb <= '0';
end if;
when GAP =>
tx_isk_o <= (others => '1');
tx_data_o <= repeat(K28_1,DBYTES);
tx_state <= TRANSFER;
tx_stb <= '1';
when FINISH =>
tx_isk_o <= (others => '1');
tx_data_o <= repeat(K28_5,DBYTES);
when others =>
tx_state <= IDLE;
end case;
end if;
end if;
end process tx_fsm;
rx_fsm: process(rx_clk_i) is
begin
if rising_edge(rx_clk_i) then
rx_finish_o <= '0';
if rx_rst_i='1' then
rx_state <= IDLE;
rx_cnt <= (others => '0');
else
case rx_state is
when IDLE =>
if rx_data_i=repeat(K28_5,DBYTES) and rx_isk_i=tied_to_vcc(DBYTES-1 downto 0) then
rx_state <= ACK;
end if;
when ACK =>
rx_state <= TRANSFER;
rx_cycles <= (others => '0');
when TRANSFER =>
rx_cycles <= rx_cycles + 1;
if rx_isk_i=tied_to_gnd(DBYTES-1 downto 0) then
rx_data <= rx_data_i;
rx_stb <= '1';
rx_cnt <= rx_cnt + 1;
else
rx_stb <= '0';
if rx_cnt>0 and rx_data_i=repeat(K28_5,DBYTES) then
rx_state <= FINISH;
rx_finish_o <= '1';
end if;
end if;
when FINISH =>
rx_finish_o <= '1';
when others =>
rx_state <= IDLE;
end case;
end if;
end if;
end process rx_fsm;
rx_cycles_o <= std_logic_vector(rx_cycles);
end architecture RTL;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CONVERSION - TOP LEVEL ***
--*** ***
--*** DP_FIXFLOAT.VHD ***
--*** ***
--*** Function: Convert Fixed Point to Floating ***
--*** Point Number ***
--*** ***
--*** 01/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** LATENCY : unsigned = 3 + 3*speed ***
--*** LATENCY : signed = 4 + 4*speed ***
--***************************************************
ENTITY dp_fixfloat IS
GENERIC (
unsigned : integer := 0; -- unsigned = 0, signed = 1
decimal : integer := 18;
fractional : integer := 14;
precision : integer := 0; -- single = 0, double = 1
speed : integer := 0 -- low speed = 0, high speed = 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fixed_number : IN STD_LOGIC_VECTOR (decimal+fractional DOWNTO 1);
sign : OUT STD_LOGIC;
exponent : OUT STD_LOGIC_VECTOR (8+3*precision DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23+29*precision DOWNTO 1)
);
END dp_fixfloat;
ARCHITECTURE rtl of dp_fixfloat IS
constant fixed_width : positive := decimal + fractional;
-- unsigned has 1 bit less (due to leading 1), signed has 2 less (leading 1 and sign)
constant fixed_precision : positive := fixed_width - unsigned - 1;
constant mantissa_width : positive := 23 + 29*precision;
constant exponent_width : positive := 8 + 3*precision;
constant exponent_base_number : positive := 126+896*precision+decimal;
-- input stage
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentbase : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
signal invfixed : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
signal absnode, delabsnode : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
-- detect range stage
signal clzinbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal count, delcount : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal zerochk, delzerochk : STD_LOGIC;
signal exponentnode, delexponentnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
-- normalize stage
signal shiftinbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal delshift : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
signal shiftvalue : STD_LOGIC_VECTOR (64 DOWNTO 1);
-- output stage
signal mantissaroundbit : STD_LOGIC;
signal exponentoutnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
signal exponentroundnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
component dp_addpipe IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_clz64 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component dp_clzpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mantissa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component dp_lsft64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component dp_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_delbit IS
GENERIC (
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC;
cc : OUT STD_LOGIC
);
end component;
BEGIN
gera : IF NOT((precision = 0) OR
(precision = 1)) GENERATE
assert false report "precision must be 0 (single precision) or 1 (double precision)" severity error;
END GENERATE;
gerb : IF NOT((speed = 0) OR
(speed = 1)) GENERATE
assert false report "speed must be 0 or 1" severity error;
END GENERATE;
gerc : IF NOT((unsigned = 0) OR
(unsigned = 1)) GENERATE
assert false report "unsigned must be 0 or 1" severity error;
END GENERATE;
gerd : IF (decimal < 1) GENERATE
assert false report "decimal must be greater than 1" severity error;
END GENERATE;
gere : IF (fixed_width > 64) GENERATE
assert false report "maximum fixed point precision must be 64 or less" severity error;
END GENERATE;
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
exponentbase <= conv_std_logic_vector (exponent_base_number,exponent_width);
--*** LEVEL 0 - 2 (ABSNODE) ***
-- level 0 if unsigned = 0,
-- level 1 if signed = 1 & speed = 0,
-- level 2 if signed = 1 & speed = 1
gabsa: IF (unsigned = 1) GENERATE
giva: FOR k IN 1 TO fixed_width GENERATE
invfixed(k) <= fixed_number(k) XOR fixed_number(fixed_width);
END GENERATE;
aabs: dp_addpipe
GENERIC MAP (width=>fixed_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>invfixed,bb=>zerovec(fixed_width DOWNTO 1),carryin=>fixed_number(fixed_width),
cc=>absnode);
END GENERATE;
gabsb: IF (unsigned = 0) GENERATE
invfixed <= fixed_number;
absnode <= invfixed;
END GENERATE;
gczc: IF (fixed_width < 64) GENERATE
clzinbus <= absnode & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
gczd: IF (fixed_width = 64) GENERATE
clzinbus <= absnode;
END GENERATE;
--*** LEVEL 1-4 (ABSDELNODE, COUNTFF) ***
-- level 1 if unsigned = 0 & speed = 0,
-- level 2 if unsigned = 0 & speed = 1,
-- level 2 if signed = 1 & speed = 0,
-- level 4 if signed = 1 & speed = 1
gcca: IF (speed = 0) GENERATE
cntzip: dp_clz64
PORT MAP (mantissa=>clzinbus,leading=>count);
END GENERATE;
gccb: IF (speed = 1) GENERATE
cntone: dp_clzpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mantissa=>clzinbus,leading=>count);
END GENERATE;
delabsbus: fp_del
GENERIC MAP (width=>fixed_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absnode,cc=>delabsnode);
ddc: fp_del
GENERIC MAP (width=>6,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>count,cc=>delcount);
-- check for 0 input - when countff = 0 and absdelnode(64) (unsigned) or
-- absdelnode(63) (signed) not '1'
zerochk <= NOT(delcount(6) OR delcount(5) OR delcount(4) OR delcount(3) OR
delcount(2) OR delcount(1) OR delabsnode(fixed_width) OR delabsnode(fixed_width-1));
delzc: fp_delbit
GENERIC MAP (pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>zerochk,cc=>delzerochk);
exponentnode <= exponentbase - (zerovec(2+3*precision DOWNTO 1) & delcount);
delx: fp_del
GENERIC MAP (width=>exponent_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>exponentnode,cc=>delexponentnode);
--*** LEVEL 2-6 (SHIFTFF) ***
-- level 2 if unsigned = 0 & speed = 0,
-- level 3 if unsigned = 0 & speed = 1,
-- level 3 if signed = 1 & speed = 0,
-- level 6 if signed = 1 & speed = 1
gfsc: IF (fixed_width < 64) GENERATE
shiftinbus <= delabsnode & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
gfsd: IF (fixed_width = 64) GENERATE
shiftinbus <= delabsnode;
END GENERATE;
gssa: IF (speed = 0) GENERATE
sftzip: dp_lsft64
PORT MAP (inbus=>shiftinbus,shift=>delcount,
outbus=>shiftnode);
END GENERATE;
gssb: IF (speed = 1) GENERATE
sftone: dp_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>shiftinbus,shift=>delcount,
outbus=>shiftnode);
END GENERATE;
dels: fp_del
GENERIC MAP (width=>fixed_width,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>shiftnode(64 DOWNTO 65-fixed_width),cc=>delshift);
gsoa: IF (fixed_width = 64) GENERATE
shiftvalue <= delshift;
END GENERATE;
gsob: IF (fixed_width < 64) GENERATE
shiftvalue <= delshift & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
--*** LEVEL 3-8 (OUTPUT) ***
-- level 3 if unsigned = 0 & speed = 0,
-- level 5 if unsigned = 0 & speed = 1,
-- level 4 if signed = 1 & speed = 0,
-- level 8 if signed = 1 & speed = 1
-- single precision
goa: IF (fixed_precision <= 23 AND mantissa_width = 23) GENERATE
mantissaroundbit <= '0';
exponentroundnode <= delexponentnode;
goax: FOR k IN 1 TO 8 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
gob: IF (fixed_precision > 23 AND mantissa_width = 23) GENERATE
mantissaroundbit <= ( shiftvalue(41) AND shiftvalue(40) ) OR
(NOT(shiftvalue(41)) AND shiftvalue(40) AND
(shiftvalue(39) OR shiftvalue(38) OR shiftvalue(37) OR shiftvalue(36) OR
shiftvalue(35) OR shiftvalue(34) OR shiftvalue(33) OR shiftvalue(32) OR
shiftvalue(31) OR shiftvalue(30) OR shiftvalue(29) OR shiftvalue(28)));
-- check for mantissa overflow here
exponentroundnode <= delexponentnode;
gobx: FOR k IN 1 TO 8 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
-- double precision
goc: IF (fixed_precision <= 52 AND mantissa_width = 52) GENERATE
mantissaroundbit <= '0';
exponentroundnode <= delexponentnode;
gocx: FOR k IN 1 TO 11 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
god: IF (fixed_width > 52 AND mantissa_width = 52) GENERATE
mantissaroundbit <= (shiftvalue(12) AND shiftvalue(11)) OR
(NOT(shiftvalue(12)) AND shiftvalue(11) AND
(shiftvalue(10) OR shiftvalue(9) OR shiftvalue(8) OR shiftvalue(7) OR
shiftvalue(6) OR shiftvalue(5) OR shiftvalue(4) OR shiftvalue(3) OR
shiftvalue(2) OR shiftvalue(1)));
-- check for mantissa overflow here
exponentroundnode <= delexponentnode;
godx: FOR k IN 1 TO 11 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
gsgna: IF (unsigned = 0) GENERATE
sign <= '0';
END GENERATE;
gsgnb: IF (unsigned = 1) GENERATE
delss: fp_delbit
GENERIC MAP (pipes=>4+4*speed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fixed_number(decimal+fractional),cc=>sign);
END GENERATE;
mno: dp_addpipe
GENERIC MAP (width=>mantissa_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>shiftvalue(63 DOWNTO 64-mantissa_width),
bb=>zerovec(mantissa_width DOWNTO 1),
carryin=>mantissaroundbit,
cc=>mantissa);
exo: dp_addpipe
GENERIC MAP (width=>exponent_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>exponentoutnode,
bb=>zerovec(exponent_width DOWNTO 1),
--carryin=>mantissaoverflowbit,
carryin=>'0',
cc=>exponent);
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CONVERSION - TOP LEVEL ***
--*** ***
--*** DP_FIXFLOAT.VHD ***
--*** ***
--*** Function: Convert Fixed Point to Floating ***
--*** Point Number ***
--*** ***
--*** 01/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** LATENCY : unsigned = 3 + 3*speed ***
--*** LATENCY : signed = 4 + 4*speed ***
--***************************************************
ENTITY dp_fixfloat IS
GENERIC (
unsigned : integer := 0; -- unsigned = 0, signed = 1
decimal : integer := 18;
fractional : integer := 14;
precision : integer := 0; -- single = 0, double = 1
speed : integer := 0 -- low speed = 0, high speed = 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fixed_number : IN STD_LOGIC_VECTOR (decimal+fractional DOWNTO 1);
sign : OUT STD_LOGIC;
exponent : OUT STD_LOGIC_VECTOR (8+3*precision DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23+29*precision DOWNTO 1)
);
END dp_fixfloat;
ARCHITECTURE rtl of dp_fixfloat IS
constant fixed_width : positive := decimal + fractional;
-- unsigned has 1 bit less (due to leading 1), signed has 2 less (leading 1 and sign)
constant fixed_precision : positive := fixed_width - unsigned - 1;
constant mantissa_width : positive := 23 + 29*precision;
constant exponent_width : positive := 8 + 3*precision;
constant exponent_base_number : positive := 126+896*precision+decimal;
-- input stage
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentbase : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
signal invfixed : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
signal absnode, delabsnode : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
-- detect range stage
signal clzinbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal count, delcount : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal zerochk, delzerochk : STD_LOGIC;
signal exponentnode, delexponentnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
-- normalize stage
signal shiftinbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal delshift : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
signal shiftvalue : STD_LOGIC_VECTOR (64 DOWNTO 1);
-- output stage
signal mantissaroundbit : STD_LOGIC;
signal exponentoutnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
signal exponentroundnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
component dp_addpipe IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_clz64 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component dp_clzpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mantissa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component dp_lsft64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component dp_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_delbit IS
GENERIC (
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC;
cc : OUT STD_LOGIC
);
end component;
BEGIN
gera : IF NOT((precision = 0) OR
(precision = 1)) GENERATE
assert false report "precision must be 0 (single precision) or 1 (double precision)" severity error;
END GENERATE;
gerb : IF NOT((speed = 0) OR
(speed = 1)) GENERATE
assert false report "speed must be 0 or 1" severity error;
END GENERATE;
gerc : IF NOT((unsigned = 0) OR
(unsigned = 1)) GENERATE
assert false report "unsigned must be 0 or 1" severity error;
END GENERATE;
gerd : IF (decimal < 1) GENERATE
assert false report "decimal must be greater than 1" severity error;
END GENERATE;
gere : IF (fixed_width > 64) GENERATE
assert false report "maximum fixed point precision must be 64 or less" severity error;
END GENERATE;
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
exponentbase <= conv_std_logic_vector (exponent_base_number,exponent_width);
--*** LEVEL 0 - 2 (ABSNODE) ***
-- level 0 if unsigned = 0,
-- level 1 if signed = 1 & speed = 0,
-- level 2 if signed = 1 & speed = 1
gabsa: IF (unsigned = 1) GENERATE
giva: FOR k IN 1 TO fixed_width GENERATE
invfixed(k) <= fixed_number(k) XOR fixed_number(fixed_width);
END GENERATE;
aabs: dp_addpipe
GENERIC MAP (width=>fixed_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>invfixed,bb=>zerovec(fixed_width DOWNTO 1),carryin=>fixed_number(fixed_width),
cc=>absnode);
END GENERATE;
gabsb: IF (unsigned = 0) GENERATE
invfixed <= fixed_number;
absnode <= invfixed;
END GENERATE;
gczc: IF (fixed_width < 64) GENERATE
clzinbus <= absnode & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
gczd: IF (fixed_width = 64) GENERATE
clzinbus <= absnode;
END GENERATE;
--*** LEVEL 1-4 (ABSDELNODE, COUNTFF) ***
-- level 1 if unsigned = 0 & speed = 0,
-- level 2 if unsigned = 0 & speed = 1,
-- level 2 if signed = 1 & speed = 0,
-- level 4 if signed = 1 & speed = 1
gcca: IF (speed = 0) GENERATE
cntzip: dp_clz64
PORT MAP (mantissa=>clzinbus,leading=>count);
END GENERATE;
gccb: IF (speed = 1) GENERATE
cntone: dp_clzpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mantissa=>clzinbus,leading=>count);
END GENERATE;
delabsbus: fp_del
GENERIC MAP (width=>fixed_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absnode,cc=>delabsnode);
ddc: fp_del
GENERIC MAP (width=>6,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>count,cc=>delcount);
-- check for 0 input - when countff = 0 and absdelnode(64) (unsigned) or
-- absdelnode(63) (signed) not '1'
zerochk <= NOT(delcount(6) OR delcount(5) OR delcount(4) OR delcount(3) OR
delcount(2) OR delcount(1) OR delabsnode(fixed_width) OR delabsnode(fixed_width-1));
delzc: fp_delbit
GENERIC MAP (pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>zerochk,cc=>delzerochk);
exponentnode <= exponentbase - (zerovec(2+3*precision DOWNTO 1) & delcount);
delx: fp_del
GENERIC MAP (width=>exponent_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>exponentnode,cc=>delexponentnode);
--*** LEVEL 2-6 (SHIFTFF) ***
-- level 2 if unsigned = 0 & speed = 0,
-- level 3 if unsigned = 0 & speed = 1,
-- level 3 if signed = 1 & speed = 0,
-- level 6 if signed = 1 & speed = 1
gfsc: IF (fixed_width < 64) GENERATE
shiftinbus <= delabsnode & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
gfsd: IF (fixed_width = 64) GENERATE
shiftinbus <= delabsnode;
END GENERATE;
gssa: IF (speed = 0) GENERATE
sftzip: dp_lsft64
PORT MAP (inbus=>shiftinbus,shift=>delcount,
outbus=>shiftnode);
END GENERATE;
gssb: IF (speed = 1) GENERATE
sftone: dp_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>shiftinbus,shift=>delcount,
outbus=>shiftnode);
END GENERATE;
dels: fp_del
GENERIC MAP (width=>fixed_width,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>shiftnode(64 DOWNTO 65-fixed_width),cc=>delshift);
gsoa: IF (fixed_width = 64) GENERATE
shiftvalue <= delshift;
END GENERATE;
gsob: IF (fixed_width < 64) GENERATE
shiftvalue <= delshift & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
--*** LEVEL 3-8 (OUTPUT) ***
-- level 3 if unsigned = 0 & speed = 0,
-- level 5 if unsigned = 0 & speed = 1,
-- level 4 if signed = 1 & speed = 0,
-- level 8 if signed = 1 & speed = 1
-- single precision
goa: IF (fixed_precision <= 23 AND mantissa_width = 23) GENERATE
mantissaroundbit <= '0';
exponentroundnode <= delexponentnode;
goax: FOR k IN 1 TO 8 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
gob: IF (fixed_precision > 23 AND mantissa_width = 23) GENERATE
mantissaroundbit <= ( shiftvalue(41) AND shiftvalue(40) ) OR
(NOT(shiftvalue(41)) AND shiftvalue(40) AND
(shiftvalue(39) OR shiftvalue(38) OR shiftvalue(37) OR shiftvalue(36) OR
shiftvalue(35) OR shiftvalue(34) OR shiftvalue(33) OR shiftvalue(32) OR
shiftvalue(31) OR shiftvalue(30) OR shiftvalue(29) OR shiftvalue(28)));
-- check for mantissa overflow here
exponentroundnode <= delexponentnode;
gobx: FOR k IN 1 TO 8 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
-- double precision
goc: IF (fixed_precision <= 52 AND mantissa_width = 52) GENERATE
mantissaroundbit <= '0';
exponentroundnode <= delexponentnode;
gocx: FOR k IN 1 TO 11 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
god: IF (fixed_width > 52 AND mantissa_width = 52) GENERATE
mantissaroundbit <= (shiftvalue(12) AND shiftvalue(11)) OR
(NOT(shiftvalue(12)) AND shiftvalue(11) AND
(shiftvalue(10) OR shiftvalue(9) OR shiftvalue(8) OR shiftvalue(7) OR
shiftvalue(6) OR shiftvalue(5) OR shiftvalue(4) OR shiftvalue(3) OR
shiftvalue(2) OR shiftvalue(1)));
-- check for mantissa overflow here
exponentroundnode <= delexponentnode;
godx: FOR k IN 1 TO 11 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
gsgna: IF (unsigned = 0) GENERATE
sign <= '0';
END GENERATE;
gsgnb: IF (unsigned = 1) GENERATE
delss: fp_delbit
GENERIC MAP (pipes=>4+4*speed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fixed_number(decimal+fractional),cc=>sign);
END GENERATE;
mno: dp_addpipe
GENERIC MAP (width=>mantissa_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>shiftvalue(63 DOWNTO 64-mantissa_width),
bb=>zerovec(mantissa_width DOWNTO 1),
carryin=>mantissaroundbit,
cc=>mantissa);
exo: dp_addpipe
GENERIC MAP (width=>exponent_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>exponentoutnode,
bb=>zerovec(exponent_width DOWNTO 1),
--carryin=>mantissaoverflowbit,
carryin=>'0',
cc=>exponent);
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CONVERSION - TOP LEVEL ***
--*** ***
--*** DP_FIXFLOAT.VHD ***
--*** ***
--*** Function: Convert Fixed Point to Floating ***
--*** Point Number ***
--*** ***
--*** 01/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** LATENCY : unsigned = 3 + 3*speed ***
--*** LATENCY : signed = 4 + 4*speed ***
--***************************************************
ENTITY dp_fixfloat IS
GENERIC (
unsigned : integer := 0; -- unsigned = 0, signed = 1
decimal : integer := 18;
fractional : integer := 14;
precision : integer := 0; -- single = 0, double = 1
speed : integer := 0 -- low speed = 0, high speed = 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fixed_number : IN STD_LOGIC_VECTOR (decimal+fractional DOWNTO 1);
sign : OUT STD_LOGIC;
exponent : OUT STD_LOGIC_VECTOR (8+3*precision DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23+29*precision DOWNTO 1)
);
END dp_fixfloat;
ARCHITECTURE rtl of dp_fixfloat IS
constant fixed_width : positive := decimal + fractional;
-- unsigned has 1 bit less (due to leading 1), signed has 2 less (leading 1 and sign)
constant fixed_precision : positive := fixed_width - unsigned - 1;
constant mantissa_width : positive := 23 + 29*precision;
constant exponent_width : positive := 8 + 3*precision;
constant exponent_base_number : positive := 126+896*precision+decimal;
-- input stage
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentbase : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
signal invfixed : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
signal absnode, delabsnode : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
-- detect range stage
signal clzinbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal count, delcount : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal zerochk, delzerochk : STD_LOGIC;
signal exponentnode, delexponentnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
-- normalize stage
signal shiftinbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal delshift : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
signal shiftvalue : STD_LOGIC_VECTOR (64 DOWNTO 1);
-- output stage
signal mantissaroundbit : STD_LOGIC;
signal exponentoutnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
signal exponentroundnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
component dp_addpipe IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_clz64 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component dp_clzpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mantissa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component dp_lsft64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component dp_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_delbit IS
GENERIC (
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC;
cc : OUT STD_LOGIC
);
end component;
BEGIN
gera : IF NOT((precision = 0) OR
(precision = 1)) GENERATE
assert false report "precision must be 0 (single precision) or 1 (double precision)" severity error;
END GENERATE;
gerb : IF NOT((speed = 0) OR
(speed = 1)) GENERATE
assert false report "speed must be 0 or 1" severity error;
END GENERATE;
gerc : IF NOT((unsigned = 0) OR
(unsigned = 1)) GENERATE
assert false report "unsigned must be 0 or 1" severity error;
END GENERATE;
gerd : IF (decimal < 1) GENERATE
assert false report "decimal must be greater than 1" severity error;
END GENERATE;
gere : IF (fixed_width > 64) GENERATE
assert false report "maximum fixed point precision must be 64 or less" severity error;
END GENERATE;
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
exponentbase <= conv_std_logic_vector (exponent_base_number,exponent_width);
--*** LEVEL 0 - 2 (ABSNODE) ***
-- level 0 if unsigned = 0,
-- level 1 if signed = 1 & speed = 0,
-- level 2 if signed = 1 & speed = 1
gabsa: IF (unsigned = 1) GENERATE
giva: FOR k IN 1 TO fixed_width GENERATE
invfixed(k) <= fixed_number(k) XOR fixed_number(fixed_width);
END GENERATE;
aabs: dp_addpipe
GENERIC MAP (width=>fixed_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>invfixed,bb=>zerovec(fixed_width DOWNTO 1),carryin=>fixed_number(fixed_width),
cc=>absnode);
END GENERATE;
gabsb: IF (unsigned = 0) GENERATE
invfixed <= fixed_number;
absnode <= invfixed;
END GENERATE;
gczc: IF (fixed_width < 64) GENERATE
clzinbus <= absnode & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
gczd: IF (fixed_width = 64) GENERATE
clzinbus <= absnode;
END GENERATE;
--*** LEVEL 1-4 (ABSDELNODE, COUNTFF) ***
-- level 1 if unsigned = 0 & speed = 0,
-- level 2 if unsigned = 0 & speed = 1,
-- level 2 if signed = 1 & speed = 0,
-- level 4 if signed = 1 & speed = 1
gcca: IF (speed = 0) GENERATE
cntzip: dp_clz64
PORT MAP (mantissa=>clzinbus,leading=>count);
END GENERATE;
gccb: IF (speed = 1) GENERATE
cntone: dp_clzpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mantissa=>clzinbus,leading=>count);
END GENERATE;
delabsbus: fp_del
GENERIC MAP (width=>fixed_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absnode,cc=>delabsnode);
ddc: fp_del
GENERIC MAP (width=>6,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>count,cc=>delcount);
-- check for 0 input - when countff = 0 and absdelnode(64) (unsigned) or
-- absdelnode(63) (signed) not '1'
zerochk <= NOT(delcount(6) OR delcount(5) OR delcount(4) OR delcount(3) OR
delcount(2) OR delcount(1) OR delabsnode(fixed_width) OR delabsnode(fixed_width-1));
delzc: fp_delbit
GENERIC MAP (pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>zerochk,cc=>delzerochk);
exponentnode <= exponentbase - (zerovec(2+3*precision DOWNTO 1) & delcount);
delx: fp_del
GENERIC MAP (width=>exponent_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>exponentnode,cc=>delexponentnode);
--*** LEVEL 2-6 (SHIFTFF) ***
-- level 2 if unsigned = 0 & speed = 0,
-- level 3 if unsigned = 0 & speed = 1,
-- level 3 if signed = 1 & speed = 0,
-- level 6 if signed = 1 & speed = 1
gfsc: IF (fixed_width < 64) GENERATE
shiftinbus <= delabsnode & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
gfsd: IF (fixed_width = 64) GENERATE
shiftinbus <= delabsnode;
END GENERATE;
gssa: IF (speed = 0) GENERATE
sftzip: dp_lsft64
PORT MAP (inbus=>shiftinbus,shift=>delcount,
outbus=>shiftnode);
END GENERATE;
gssb: IF (speed = 1) GENERATE
sftone: dp_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>shiftinbus,shift=>delcount,
outbus=>shiftnode);
END GENERATE;
dels: fp_del
GENERIC MAP (width=>fixed_width,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>shiftnode(64 DOWNTO 65-fixed_width),cc=>delshift);
gsoa: IF (fixed_width = 64) GENERATE
shiftvalue <= delshift;
END GENERATE;
gsob: IF (fixed_width < 64) GENERATE
shiftvalue <= delshift & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
--*** LEVEL 3-8 (OUTPUT) ***
-- level 3 if unsigned = 0 & speed = 0,
-- level 5 if unsigned = 0 & speed = 1,
-- level 4 if signed = 1 & speed = 0,
-- level 8 if signed = 1 & speed = 1
-- single precision
goa: IF (fixed_precision <= 23 AND mantissa_width = 23) GENERATE
mantissaroundbit <= '0';
exponentroundnode <= delexponentnode;
goax: FOR k IN 1 TO 8 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
gob: IF (fixed_precision > 23 AND mantissa_width = 23) GENERATE
mantissaroundbit <= ( shiftvalue(41) AND shiftvalue(40) ) OR
(NOT(shiftvalue(41)) AND shiftvalue(40) AND
(shiftvalue(39) OR shiftvalue(38) OR shiftvalue(37) OR shiftvalue(36) OR
shiftvalue(35) OR shiftvalue(34) OR shiftvalue(33) OR shiftvalue(32) OR
shiftvalue(31) OR shiftvalue(30) OR shiftvalue(29) OR shiftvalue(28)));
-- check for mantissa overflow here
exponentroundnode <= delexponentnode;
gobx: FOR k IN 1 TO 8 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
-- double precision
goc: IF (fixed_precision <= 52 AND mantissa_width = 52) GENERATE
mantissaroundbit <= '0';
exponentroundnode <= delexponentnode;
gocx: FOR k IN 1 TO 11 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
god: IF (fixed_width > 52 AND mantissa_width = 52) GENERATE
mantissaroundbit <= (shiftvalue(12) AND shiftvalue(11)) OR
(NOT(shiftvalue(12)) AND shiftvalue(11) AND
(shiftvalue(10) OR shiftvalue(9) OR shiftvalue(8) OR shiftvalue(7) OR
shiftvalue(6) OR shiftvalue(5) OR shiftvalue(4) OR shiftvalue(3) OR
shiftvalue(2) OR shiftvalue(1)));
-- check for mantissa overflow here
exponentroundnode <= delexponentnode;
godx: FOR k IN 1 TO 11 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
gsgna: IF (unsigned = 0) GENERATE
sign <= '0';
END GENERATE;
gsgnb: IF (unsigned = 1) GENERATE
delss: fp_delbit
GENERIC MAP (pipes=>4+4*speed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fixed_number(decimal+fractional),cc=>sign);
END GENERATE;
mno: dp_addpipe
GENERIC MAP (width=>mantissa_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>shiftvalue(63 DOWNTO 64-mantissa_width),
bb=>zerovec(mantissa_width DOWNTO 1),
carryin=>mantissaroundbit,
cc=>mantissa);
exo: dp_addpipe
GENERIC MAP (width=>exponent_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>exponentoutnode,
bb=>zerovec(exponent_width DOWNTO 1),
--carryin=>mantissaoverflowbit,
carryin=>'0',
cc=>exponent);
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CONVERSION - TOP LEVEL ***
--*** ***
--*** DP_FIXFLOAT.VHD ***
--*** ***
--*** Function: Convert Fixed Point to Floating ***
--*** Point Number ***
--*** ***
--*** 01/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** LATENCY : unsigned = 3 + 3*speed ***
--*** LATENCY : signed = 4 + 4*speed ***
--***************************************************
ENTITY dp_fixfloat IS
GENERIC (
unsigned : integer := 0; -- unsigned = 0, signed = 1
decimal : integer := 18;
fractional : integer := 14;
precision : integer := 0; -- single = 0, double = 1
speed : integer := 0 -- low speed = 0, high speed = 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fixed_number : IN STD_LOGIC_VECTOR (decimal+fractional DOWNTO 1);
sign : OUT STD_LOGIC;
exponent : OUT STD_LOGIC_VECTOR (8+3*precision DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23+29*precision DOWNTO 1)
);
END dp_fixfloat;
ARCHITECTURE rtl of dp_fixfloat IS
constant fixed_width : positive := decimal + fractional;
-- unsigned has 1 bit less (due to leading 1), signed has 2 less (leading 1 and sign)
constant fixed_precision : positive := fixed_width - unsigned - 1;
constant mantissa_width : positive := 23 + 29*precision;
constant exponent_width : positive := 8 + 3*precision;
constant exponent_base_number : positive := 126+896*precision+decimal;
-- input stage
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentbase : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
signal invfixed : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
signal absnode, delabsnode : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
-- detect range stage
signal clzinbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal count, delcount : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal zerochk, delzerochk : STD_LOGIC;
signal exponentnode, delexponentnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
-- normalize stage
signal shiftinbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal delshift : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
signal shiftvalue : STD_LOGIC_VECTOR (64 DOWNTO 1);
-- output stage
signal mantissaroundbit : STD_LOGIC;
signal exponentoutnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
signal exponentroundnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
component dp_addpipe IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_clz64 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component dp_clzpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mantissa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component dp_lsft64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component dp_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_delbit IS
GENERIC (
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC;
cc : OUT STD_LOGIC
);
end component;
BEGIN
gera : IF NOT((precision = 0) OR
(precision = 1)) GENERATE
assert false report "precision must be 0 (single precision) or 1 (double precision)" severity error;
END GENERATE;
gerb : IF NOT((speed = 0) OR
(speed = 1)) GENERATE
assert false report "speed must be 0 or 1" severity error;
END GENERATE;
gerc : IF NOT((unsigned = 0) OR
(unsigned = 1)) GENERATE
assert false report "unsigned must be 0 or 1" severity error;
END GENERATE;
gerd : IF (decimal < 1) GENERATE
assert false report "decimal must be greater than 1" severity error;
END GENERATE;
gere : IF (fixed_width > 64) GENERATE
assert false report "maximum fixed point precision must be 64 or less" severity error;
END GENERATE;
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
exponentbase <= conv_std_logic_vector (exponent_base_number,exponent_width);
--*** LEVEL 0 - 2 (ABSNODE) ***
-- level 0 if unsigned = 0,
-- level 1 if signed = 1 & speed = 0,
-- level 2 if signed = 1 & speed = 1
gabsa: IF (unsigned = 1) GENERATE
giva: FOR k IN 1 TO fixed_width GENERATE
invfixed(k) <= fixed_number(k) XOR fixed_number(fixed_width);
END GENERATE;
aabs: dp_addpipe
GENERIC MAP (width=>fixed_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>invfixed,bb=>zerovec(fixed_width DOWNTO 1),carryin=>fixed_number(fixed_width),
cc=>absnode);
END GENERATE;
gabsb: IF (unsigned = 0) GENERATE
invfixed <= fixed_number;
absnode <= invfixed;
END GENERATE;
gczc: IF (fixed_width < 64) GENERATE
clzinbus <= absnode & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
gczd: IF (fixed_width = 64) GENERATE
clzinbus <= absnode;
END GENERATE;
--*** LEVEL 1-4 (ABSDELNODE, COUNTFF) ***
-- level 1 if unsigned = 0 & speed = 0,
-- level 2 if unsigned = 0 & speed = 1,
-- level 2 if signed = 1 & speed = 0,
-- level 4 if signed = 1 & speed = 1
gcca: IF (speed = 0) GENERATE
cntzip: dp_clz64
PORT MAP (mantissa=>clzinbus,leading=>count);
END GENERATE;
gccb: IF (speed = 1) GENERATE
cntone: dp_clzpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mantissa=>clzinbus,leading=>count);
END GENERATE;
delabsbus: fp_del
GENERIC MAP (width=>fixed_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absnode,cc=>delabsnode);
ddc: fp_del
GENERIC MAP (width=>6,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>count,cc=>delcount);
-- check for 0 input - when countff = 0 and absdelnode(64) (unsigned) or
-- absdelnode(63) (signed) not '1'
zerochk <= NOT(delcount(6) OR delcount(5) OR delcount(4) OR delcount(3) OR
delcount(2) OR delcount(1) OR delabsnode(fixed_width) OR delabsnode(fixed_width-1));
delzc: fp_delbit
GENERIC MAP (pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>zerochk,cc=>delzerochk);
exponentnode <= exponentbase - (zerovec(2+3*precision DOWNTO 1) & delcount);
delx: fp_del
GENERIC MAP (width=>exponent_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>exponentnode,cc=>delexponentnode);
--*** LEVEL 2-6 (SHIFTFF) ***
-- level 2 if unsigned = 0 & speed = 0,
-- level 3 if unsigned = 0 & speed = 1,
-- level 3 if signed = 1 & speed = 0,
-- level 6 if signed = 1 & speed = 1
gfsc: IF (fixed_width < 64) GENERATE
shiftinbus <= delabsnode & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
gfsd: IF (fixed_width = 64) GENERATE
shiftinbus <= delabsnode;
END GENERATE;
gssa: IF (speed = 0) GENERATE
sftzip: dp_lsft64
PORT MAP (inbus=>shiftinbus,shift=>delcount,
outbus=>shiftnode);
END GENERATE;
gssb: IF (speed = 1) GENERATE
sftone: dp_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>shiftinbus,shift=>delcount,
outbus=>shiftnode);
END GENERATE;
dels: fp_del
GENERIC MAP (width=>fixed_width,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>shiftnode(64 DOWNTO 65-fixed_width),cc=>delshift);
gsoa: IF (fixed_width = 64) GENERATE
shiftvalue <= delshift;
END GENERATE;
gsob: IF (fixed_width < 64) GENERATE
shiftvalue <= delshift & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
--*** LEVEL 3-8 (OUTPUT) ***
-- level 3 if unsigned = 0 & speed = 0,
-- level 5 if unsigned = 0 & speed = 1,
-- level 4 if signed = 1 & speed = 0,
-- level 8 if signed = 1 & speed = 1
-- single precision
goa: IF (fixed_precision <= 23 AND mantissa_width = 23) GENERATE
mantissaroundbit <= '0';
exponentroundnode <= delexponentnode;
goax: FOR k IN 1 TO 8 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
gob: IF (fixed_precision > 23 AND mantissa_width = 23) GENERATE
mantissaroundbit <= ( shiftvalue(41) AND shiftvalue(40) ) OR
(NOT(shiftvalue(41)) AND shiftvalue(40) AND
(shiftvalue(39) OR shiftvalue(38) OR shiftvalue(37) OR shiftvalue(36) OR
shiftvalue(35) OR shiftvalue(34) OR shiftvalue(33) OR shiftvalue(32) OR
shiftvalue(31) OR shiftvalue(30) OR shiftvalue(29) OR shiftvalue(28)));
-- check for mantissa overflow here
exponentroundnode <= delexponentnode;
gobx: FOR k IN 1 TO 8 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
-- double precision
goc: IF (fixed_precision <= 52 AND mantissa_width = 52) GENERATE
mantissaroundbit <= '0';
exponentroundnode <= delexponentnode;
gocx: FOR k IN 1 TO 11 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
god: IF (fixed_width > 52 AND mantissa_width = 52) GENERATE
mantissaroundbit <= (shiftvalue(12) AND shiftvalue(11)) OR
(NOT(shiftvalue(12)) AND shiftvalue(11) AND
(shiftvalue(10) OR shiftvalue(9) OR shiftvalue(8) OR shiftvalue(7) OR
shiftvalue(6) OR shiftvalue(5) OR shiftvalue(4) OR shiftvalue(3) OR
shiftvalue(2) OR shiftvalue(1)));
-- check for mantissa overflow here
exponentroundnode <= delexponentnode;
godx: FOR k IN 1 TO 11 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
gsgna: IF (unsigned = 0) GENERATE
sign <= '0';
END GENERATE;
gsgnb: IF (unsigned = 1) GENERATE
delss: fp_delbit
GENERIC MAP (pipes=>4+4*speed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fixed_number(decimal+fractional),cc=>sign);
END GENERATE;
mno: dp_addpipe
GENERIC MAP (width=>mantissa_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>shiftvalue(63 DOWNTO 64-mantissa_width),
bb=>zerovec(mantissa_width DOWNTO 1),
carryin=>mantissaroundbit,
cc=>mantissa);
exo: dp_addpipe
GENERIC MAP (width=>exponent_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>exponentoutnode,
bb=>zerovec(exponent_width DOWNTO 1),
--carryin=>mantissaoverflowbit,
carryin=>'0',
cc=>exponent);
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CONVERSION - TOP LEVEL ***
--*** ***
--*** DP_FIXFLOAT.VHD ***
--*** ***
--*** Function: Convert Fixed Point to Floating ***
--*** Point Number ***
--*** ***
--*** 01/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** LATENCY : unsigned = 3 + 3*speed ***
--*** LATENCY : signed = 4 + 4*speed ***
--***************************************************
ENTITY dp_fixfloat IS
GENERIC (
unsigned : integer := 0; -- unsigned = 0, signed = 1
decimal : integer := 18;
fractional : integer := 14;
precision : integer := 0; -- single = 0, double = 1
speed : integer := 0 -- low speed = 0, high speed = 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fixed_number : IN STD_LOGIC_VECTOR (decimal+fractional DOWNTO 1);
sign : OUT STD_LOGIC;
exponent : OUT STD_LOGIC_VECTOR (8+3*precision DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23+29*precision DOWNTO 1)
);
END dp_fixfloat;
ARCHITECTURE rtl of dp_fixfloat IS
constant fixed_width : positive := decimal + fractional;
-- unsigned has 1 bit less (due to leading 1), signed has 2 less (leading 1 and sign)
constant fixed_precision : positive := fixed_width - unsigned - 1;
constant mantissa_width : positive := 23 + 29*precision;
constant exponent_width : positive := 8 + 3*precision;
constant exponent_base_number : positive := 126+896*precision+decimal;
-- input stage
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentbase : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
signal invfixed : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
signal absnode, delabsnode : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
-- detect range stage
signal clzinbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal count, delcount : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal zerochk, delzerochk : STD_LOGIC;
signal exponentnode, delexponentnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
-- normalize stage
signal shiftinbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal delshift : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
signal shiftvalue : STD_LOGIC_VECTOR (64 DOWNTO 1);
-- output stage
signal mantissaroundbit : STD_LOGIC;
signal exponentoutnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
signal exponentroundnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
component dp_addpipe IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_clz64 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component dp_clzpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mantissa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component dp_lsft64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component dp_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_delbit IS
GENERIC (
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC;
cc : OUT STD_LOGIC
);
end component;
BEGIN
gera : IF NOT((precision = 0) OR
(precision = 1)) GENERATE
assert false report "precision must be 0 (single precision) or 1 (double precision)" severity error;
END GENERATE;
gerb : IF NOT((speed = 0) OR
(speed = 1)) GENERATE
assert false report "speed must be 0 or 1" severity error;
END GENERATE;
gerc : IF NOT((unsigned = 0) OR
(unsigned = 1)) GENERATE
assert false report "unsigned must be 0 or 1" severity error;
END GENERATE;
gerd : IF (decimal < 1) GENERATE
assert false report "decimal must be greater than 1" severity error;
END GENERATE;
gere : IF (fixed_width > 64) GENERATE
assert false report "maximum fixed point precision must be 64 or less" severity error;
END GENERATE;
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
exponentbase <= conv_std_logic_vector (exponent_base_number,exponent_width);
--*** LEVEL 0 - 2 (ABSNODE) ***
-- level 0 if unsigned = 0,
-- level 1 if signed = 1 & speed = 0,
-- level 2 if signed = 1 & speed = 1
gabsa: IF (unsigned = 1) GENERATE
giva: FOR k IN 1 TO fixed_width GENERATE
invfixed(k) <= fixed_number(k) XOR fixed_number(fixed_width);
END GENERATE;
aabs: dp_addpipe
GENERIC MAP (width=>fixed_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>invfixed,bb=>zerovec(fixed_width DOWNTO 1),carryin=>fixed_number(fixed_width),
cc=>absnode);
END GENERATE;
gabsb: IF (unsigned = 0) GENERATE
invfixed <= fixed_number;
absnode <= invfixed;
END GENERATE;
gczc: IF (fixed_width < 64) GENERATE
clzinbus <= absnode & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
gczd: IF (fixed_width = 64) GENERATE
clzinbus <= absnode;
END GENERATE;
--*** LEVEL 1-4 (ABSDELNODE, COUNTFF) ***
-- level 1 if unsigned = 0 & speed = 0,
-- level 2 if unsigned = 0 & speed = 1,
-- level 2 if signed = 1 & speed = 0,
-- level 4 if signed = 1 & speed = 1
gcca: IF (speed = 0) GENERATE
cntzip: dp_clz64
PORT MAP (mantissa=>clzinbus,leading=>count);
END GENERATE;
gccb: IF (speed = 1) GENERATE
cntone: dp_clzpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mantissa=>clzinbus,leading=>count);
END GENERATE;
delabsbus: fp_del
GENERIC MAP (width=>fixed_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absnode,cc=>delabsnode);
ddc: fp_del
GENERIC MAP (width=>6,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>count,cc=>delcount);
-- check for 0 input - when countff = 0 and absdelnode(64) (unsigned) or
-- absdelnode(63) (signed) not '1'
zerochk <= NOT(delcount(6) OR delcount(5) OR delcount(4) OR delcount(3) OR
delcount(2) OR delcount(1) OR delabsnode(fixed_width) OR delabsnode(fixed_width-1));
delzc: fp_delbit
GENERIC MAP (pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>zerochk,cc=>delzerochk);
exponentnode <= exponentbase - (zerovec(2+3*precision DOWNTO 1) & delcount);
delx: fp_del
GENERIC MAP (width=>exponent_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>exponentnode,cc=>delexponentnode);
--*** LEVEL 2-6 (SHIFTFF) ***
-- level 2 if unsigned = 0 & speed = 0,
-- level 3 if unsigned = 0 & speed = 1,
-- level 3 if signed = 1 & speed = 0,
-- level 6 if signed = 1 & speed = 1
gfsc: IF (fixed_width < 64) GENERATE
shiftinbus <= delabsnode & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
gfsd: IF (fixed_width = 64) GENERATE
shiftinbus <= delabsnode;
END GENERATE;
gssa: IF (speed = 0) GENERATE
sftzip: dp_lsft64
PORT MAP (inbus=>shiftinbus,shift=>delcount,
outbus=>shiftnode);
END GENERATE;
gssb: IF (speed = 1) GENERATE
sftone: dp_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>shiftinbus,shift=>delcount,
outbus=>shiftnode);
END GENERATE;
dels: fp_del
GENERIC MAP (width=>fixed_width,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>shiftnode(64 DOWNTO 65-fixed_width),cc=>delshift);
gsoa: IF (fixed_width = 64) GENERATE
shiftvalue <= delshift;
END GENERATE;
gsob: IF (fixed_width < 64) GENERATE
shiftvalue <= delshift & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
--*** LEVEL 3-8 (OUTPUT) ***
-- level 3 if unsigned = 0 & speed = 0,
-- level 5 if unsigned = 0 & speed = 1,
-- level 4 if signed = 1 & speed = 0,
-- level 8 if signed = 1 & speed = 1
-- single precision
goa: IF (fixed_precision <= 23 AND mantissa_width = 23) GENERATE
mantissaroundbit <= '0';
exponentroundnode <= delexponentnode;
goax: FOR k IN 1 TO 8 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
gob: IF (fixed_precision > 23 AND mantissa_width = 23) GENERATE
mantissaroundbit <= ( shiftvalue(41) AND shiftvalue(40) ) OR
(NOT(shiftvalue(41)) AND shiftvalue(40) AND
(shiftvalue(39) OR shiftvalue(38) OR shiftvalue(37) OR shiftvalue(36) OR
shiftvalue(35) OR shiftvalue(34) OR shiftvalue(33) OR shiftvalue(32) OR
shiftvalue(31) OR shiftvalue(30) OR shiftvalue(29) OR shiftvalue(28)));
-- check for mantissa overflow here
exponentroundnode <= delexponentnode;
gobx: FOR k IN 1 TO 8 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
-- double precision
goc: IF (fixed_precision <= 52 AND mantissa_width = 52) GENERATE
mantissaroundbit <= '0';
exponentroundnode <= delexponentnode;
gocx: FOR k IN 1 TO 11 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
god: IF (fixed_width > 52 AND mantissa_width = 52) GENERATE
mantissaroundbit <= (shiftvalue(12) AND shiftvalue(11)) OR
(NOT(shiftvalue(12)) AND shiftvalue(11) AND
(shiftvalue(10) OR shiftvalue(9) OR shiftvalue(8) OR shiftvalue(7) OR
shiftvalue(6) OR shiftvalue(5) OR shiftvalue(4) OR shiftvalue(3) OR
shiftvalue(2) OR shiftvalue(1)));
-- check for mantissa overflow here
exponentroundnode <= delexponentnode;
godx: FOR k IN 1 TO 11 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
gsgna: IF (unsigned = 0) GENERATE
sign <= '0';
END GENERATE;
gsgnb: IF (unsigned = 1) GENERATE
delss: fp_delbit
GENERIC MAP (pipes=>4+4*speed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fixed_number(decimal+fractional),cc=>sign);
END GENERATE;
mno: dp_addpipe
GENERIC MAP (width=>mantissa_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>shiftvalue(63 DOWNTO 64-mantissa_width),
bb=>zerovec(mantissa_width DOWNTO 1),
carryin=>mantissaroundbit,
cc=>mantissa);
exo: dp_addpipe
GENERIC MAP (width=>exponent_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>exponentoutnode,
bb=>zerovec(exponent_width DOWNTO 1),
--carryin=>mantissaoverflowbit,
carryin=>'0',
cc=>exponent);
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CONVERSION - TOP LEVEL ***
--*** ***
--*** DP_FIXFLOAT.VHD ***
--*** ***
--*** Function: Convert Fixed Point to Floating ***
--*** Point Number ***
--*** ***
--*** 01/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** LATENCY : unsigned = 3 + 3*speed ***
--*** LATENCY : signed = 4 + 4*speed ***
--***************************************************
ENTITY dp_fixfloat IS
GENERIC (
unsigned : integer := 0; -- unsigned = 0, signed = 1
decimal : integer := 18;
fractional : integer := 14;
precision : integer := 0; -- single = 0, double = 1
speed : integer := 0 -- low speed = 0, high speed = 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fixed_number : IN STD_LOGIC_VECTOR (decimal+fractional DOWNTO 1);
sign : OUT STD_LOGIC;
exponent : OUT STD_LOGIC_VECTOR (8+3*precision DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23+29*precision DOWNTO 1)
);
END dp_fixfloat;
ARCHITECTURE rtl of dp_fixfloat IS
constant fixed_width : positive := decimal + fractional;
-- unsigned has 1 bit less (due to leading 1), signed has 2 less (leading 1 and sign)
constant fixed_precision : positive := fixed_width - unsigned - 1;
constant mantissa_width : positive := 23 + 29*precision;
constant exponent_width : positive := 8 + 3*precision;
constant exponent_base_number : positive := 126+896*precision+decimal;
-- input stage
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentbase : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
signal invfixed : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
signal absnode, delabsnode : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
-- detect range stage
signal clzinbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal count, delcount : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal zerochk, delzerochk : STD_LOGIC;
signal exponentnode, delexponentnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
-- normalize stage
signal shiftinbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal delshift : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
signal shiftvalue : STD_LOGIC_VECTOR (64 DOWNTO 1);
-- output stage
signal mantissaroundbit : STD_LOGIC;
signal exponentoutnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
signal exponentroundnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
component dp_addpipe IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_clz64 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component dp_clzpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mantissa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component dp_lsft64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component dp_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_delbit IS
GENERIC (
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC;
cc : OUT STD_LOGIC
);
end component;
BEGIN
gera : IF NOT((precision = 0) OR
(precision = 1)) GENERATE
assert false report "precision must be 0 (single precision) or 1 (double precision)" severity error;
END GENERATE;
gerb : IF NOT((speed = 0) OR
(speed = 1)) GENERATE
assert false report "speed must be 0 or 1" severity error;
END GENERATE;
gerc : IF NOT((unsigned = 0) OR
(unsigned = 1)) GENERATE
assert false report "unsigned must be 0 or 1" severity error;
END GENERATE;
gerd : IF (decimal < 1) GENERATE
assert false report "decimal must be greater than 1" severity error;
END GENERATE;
gere : IF (fixed_width > 64) GENERATE
assert false report "maximum fixed point precision must be 64 or less" severity error;
END GENERATE;
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
exponentbase <= conv_std_logic_vector (exponent_base_number,exponent_width);
--*** LEVEL 0 - 2 (ABSNODE) ***
-- level 0 if unsigned = 0,
-- level 1 if signed = 1 & speed = 0,
-- level 2 if signed = 1 & speed = 1
gabsa: IF (unsigned = 1) GENERATE
giva: FOR k IN 1 TO fixed_width GENERATE
invfixed(k) <= fixed_number(k) XOR fixed_number(fixed_width);
END GENERATE;
aabs: dp_addpipe
GENERIC MAP (width=>fixed_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>invfixed,bb=>zerovec(fixed_width DOWNTO 1),carryin=>fixed_number(fixed_width),
cc=>absnode);
END GENERATE;
gabsb: IF (unsigned = 0) GENERATE
invfixed <= fixed_number;
absnode <= invfixed;
END GENERATE;
gczc: IF (fixed_width < 64) GENERATE
clzinbus <= absnode & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
gczd: IF (fixed_width = 64) GENERATE
clzinbus <= absnode;
END GENERATE;
--*** LEVEL 1-4 (ABSDELNODE, COUNTFF) ***
-- level 1 if unsigned = 0 & speed = 0,
-- level 2 if unsigned = 0 & speed = 1,
-- level 2 if signed = 1 & speed = 0,
-- level 4 if signed = 1 & speed = 1
gcca: IF (speed = 0) GENERATE
cntzip: dp_clz64
PORT MAP (mantissa=>clzinbus,leading=>count);
END GENERATE;
gccb: IF (speed = 1) GENERATE
cntone: dp_clzpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mantissa=>clzinbus,leading=>count);
END GENERATE;
delabsbus: fp_del
GENERIC MAP (width=>fixed_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absnode,cc=>delabsnode);
ddc: fp_del
GENERIC MAP (width=>6,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>count,cc=>delcount);
-- check for 0 input - when countff = 0 and absdelnode(64) (unsigned) or
-- absdelnode(63) (signed) not '1'
zerochk <= NOT(delcount(6) OR delcount(5) OR delcount(4) OR delcount(3) OR
delcount(2) OR delcount(1) OR delabsnode(fixed_width) OR delabsnode(fixed_width-1));
delzc: fp_delbit
GENERIC MAP (pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>zerochk,cc=>delzerochk);
exponentnode <= exponentbase - (zerovec(2+3*precision DOWNTO 1) & delcount);
delx: fp_del
GENERIC MAP (width=>exponent_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>exponentnode,cc=>delexponentnode);
--*** LEVEL 2-6 (SHIFTFF) ***
-- level 2 if unsigned = 0 & speed = 0,
-- level 3 if unsigned = 0 & speed = 1,
-- level 3 if signed = 1 & speed = 0,
-- level 6 if signed = 1 & speed = 1
gfsc: IF (fixed_width < 64) GENERATE
shiftinbus <= delabsnode & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
gfsd: IF (fixed_width = 64) GENERATE
shiftinbus <= delabsnode;
END GENERATE;
gssa: IF (speed = 0) GENERATE
sftzip: dp_lsft64
PORT MAP (inbus=>shiftinbus,shift=>delcount,
outbus=>shiftnode);
END GENERATE;
gssb: IF (speed = 1) GENERATE
sftone: dp_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>shiftinbus,shift=>delcount,
outbus=>shiftnode);
END GENERATE;
dels: fp_del
GENERIC MAP (width=>fixed_width,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>shiftnode(64 DOWNTO 65-fixed_width),cc=>delshift);
gsoa: IF (fixed_width = 64) GENERATE
shiftvalue <= delshift;
END GENERATE;
gsob: IF (fixed_width < 64) GENERATE
shiftvalue <= delshift & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
--*** LEVEL 3-8 (OUTPUT) ***
-- level 3 if unsigned = 0 & speed = 0,
-- level 5 if unsigned = 0 & speed = 1,
-- level 4 if signed = 1 & speed = 0,
-- level 8 if signed = 1 & speed = 1
-- single precision
goa: IF (fixed_precision <= 23 AND mantissa_width = 23) GENERATE
mantissaroundbit <= '0';
exponentroundnode <= delexponentnode;
goax: FOR k IN 1 TO 8 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
gob: IF (fixed_precision > 23 AND mantissa_width = 23) GENERATE
mantissaroundbit <= ( shiftvalue(41) AND shiftvalue(40) ) OR
(NOT(shiftvalue(41)) AND shiftvalue(40) AND
(shiftvalue(39) OR shiftvalue(38) OR shiftvalue(37) OR shiftvalue(36) OR
shiftvalue(35) OR shiftvalue(34) OR shiftvalue(33) OR shiftvalue(32) OR
shiftvalue(31) OR shiftvalue(30) OR shiftvalue(29) OR shiftvalue(28)));
-- check for mantissa overflow here
exponentroundnode <= delexponentnode;
gobx: FOR k IN 1 TO 8 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
-- double precision
goc: IF (fixed_precision <= 52 AND mantissa_width = 52) GENERATE
mantissaroundbit <= '0';
exponentroundnode <= delexponentnode;
gocx: FOR k IN 1 TO 11 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
god: IF (fixed_width > 52 AND mantissa_width = 52) GENERATE
mantissaroundbit <= (shiftvalue(12) AND shiftvalue(11)) OR
(NOT(shiftvalue(12)) AND shiftvalue(11) AND
(shiftvalue(10) OR shiftvalue(9) OR shiftvalue(8) OR shiftvalue(7) OR
shiftvalue(6) OR shiftvalue(5) OR shiftvalue(4) OR shiftvalue(3) OR
shiftvalue(2) OR shiftvalue(1)));
-- check for mantissa overflow here
exponentroundnode <= delexponentnode;
godx: FOR k IN 1 TO 11 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
gsgna: IF (unsigned = 0) GENERATE
sign <= '0';
END GENERATE;
gsgnb: IF (unsigned = 1) GENERATE
delss: fp_delbit
GENERIC MAP (pipes=>4+4*speed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fixed_number(decimal+fractional),cc=>sign);
END GENERATE;
mno: dp_addpipe
GENERIC MAP (width=>mantissa_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>shiftvalue(63 DOWNTO 64-mantissa_width),
bb=>zerovec(mantissa_width DOWNTO 1),
carryin=>mantissaroundbit,
cc=>mantissa);
exo: dp_addpipe
GENERIC MAP (width=>exponent_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>exponentoutnode,
bb=>zerovec(exponent_width DOWNTO 1),
--carryin=>mantissaoverflowbit,
carryin=>'0',
cc=>exponent);
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CONVERSION - TOP LEVEL ***
--*** ***
--*** DP_FIXFLOAT.VHD ***
--*** ***
--*** Function: Convert Fixed Point to Floating ***
--*** Point Number ***
--*** ***
--*** 01/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** LATENCY : unsigned = 3 + 3*speed ***
--*** LATENCY : signed = 4 + 4*speed ***
--***************************************************
ENTITY dp_fixfloat IS
GENERIC (
unsigned : integer := 0; -- unsigned = 0, signed = 1
decimal : integer := 18;
fractional : integer := 14;
precision : integer := 0; -- single = 0, double = 1
speed : integer := 0 -- low speed = 0, high speed = 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fixed_number : IN STD_LOGIC_VECTOR (decimal+fractional DOWNTO 1);
sign : OUT STD_LOGIC;
exponent : OUT STD_LOGIC_VECTOR (8+3*precision DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23+29*precision DOWNTO 1)
);
END dp_fixfloat;
ARCHITECTURE rtl of dp_fixfloat IS
constant fixed_width : positive := decimal + fractional;
-- unsigned has 1 bit less (due to leading 1), signed has 2 less (leading 1 and sign)
constant fixed_precision : positive := fixed_width - unsigned - 1;
constant mantissa_width : positive := 23 + 29*precision;
constant exponent_width : positive := 8 + 3*precision;
constant exponent_base_number : positive := 126+896*precision+decimal;
-- input stage
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentbase : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
signal invfixed : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
signal absnode, delabsnode : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
-- detect range stage
signal clzinbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal count, delcount : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal zerochk, delzerochk : STD_LOGIC;
signal exponentnode, delexponentnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
-- normalize stage
signal shiftinbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal delshift : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
signal shiftvalue : STD_LOGIC_VECTOR (64 DOWNTO 1);
-- output stage
signal mantissaroundbit : STD_LOGIC;
signal exponentoutnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
signal exponentroundnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
component dp_addpipe IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_clz64 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component dp_clzpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mantissa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component dp_lsft64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component dp_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_delbit IS
GENERIC (
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC;
cc : OUT STD_LOGIC
);
end component;
BEGIN
gera : IF NOT((precision = 0) OR
(precision = 1)) GENERATE
assert false report "precision must be 0 (single precision) or 1 (double precision)" severity error;
END GENERATE;
gerb : IF NOT((speed = 0) OR
(speed = 1)) GENERATE
assert false report "speed must be 0 or 1" severity error;
END GENERATE;
gerc : IF NOT((unsigned = 0) OR
(unsigned = 1)) GENERATE
assert false report "unsigned must be 0 or 1" severity error;
END GENERATE;
gerd : IF (decimal < 1) GENERATE
assert false report "decimal must be greater than 1" severity error;
END GENERATE;
gere : IF (fixed_width > 64) GENERATE
assert false report "maximum fixed point precision must be 64 or less" severity error;
END GENERATE;
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
exponentbase <= conv_std_logic_vector (exponent_base_number,exponent_width);
--*** LEVEL 0 - 2 (ABSNODE) ***
-- level 0 if unsigned = 0,
-- level 1 if signed = 1 & speed = 0,
-- level 2 if signed = 1 & speed = 1
gabsa: IF (unsigned = 1) GENERATE
giva: FOR k IN 1 TO fixed_width GENERATE
invfixed(k) <= fixed_number(k) XOR fixed_number(fixed_width);
END GENERATE;
aabs: dp_addpipe
GENERIC MAP (width=>fixed_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>invfixed,bb=>zerovec(fixed_width DOWNTO 1),carryin=>fixed_number(fixed_width),
cc=>absnode);
END GENERATE;
gabsb: IF (unsigned = 0) GENERATE
invfixed <= fixed_number;
absnode <= invfixed;
END GENERATE;
gczc: IF (fixed_width < 64) GENERATE
clzinbus <= absnode & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
gczd: IF (fixed_width = 64) GENERATE
clzinbus <= absnode;
END GENERATE;
--*** LEVEL 1-4 (ABSDELNODE, COUNTFF) ***
-- level 1 if unsigned = 0 & speed = 0,
-- level 2 if unsigned = 0 & speed = 1,
-- level 2 if signed = 1 & speed = 0,
-- level 4 if signed = 1 & speed = 1
gcca: IF (speed = 0) GENERATE
cntzip: dp_clz64
PORT MAP (mantissa=>clzinbus,leading=>count);
END GENERATE;
gccb: IF (speed = 1) GENERATE
cntone: dp_clzpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mantissa=>clzinbus,leading=>count);
END GENERATE;
delabsbus: fp_del
GENERIC MAP (width=>fixed_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absnode,cc=>delabsnode);
ddc: fp_del
GENERIC MAP (width=>6,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>count,cc=>delcount);
-- check for 0 input - when countff = 0 and absdelnode(64) (unsigned) or
-- absdelnode(63) (signed) not '1'
zerochk <= NOT(delcount(6) OR delcount(5) OR delcount(4) OR delcount(3) OR
delcount(2) OR delcount(1) OR delabsnode(fixed_width) OR delabsnode(fixed_width-1));
delzc: fp_delbit
GENERIC MAP (pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>zerochk,cc=>delzerochk);
exponentnode <= exponentbase - (zerovec(2+3*precision DOWNTO 1) & delcount);
delx: fp_del
GENERIC MAP (width=>exponent_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>exponentnode,cc=>delexponentnode);
--*** LEVEL 2-6 (SHIFTFF) ***
-- level 2 if unsigned = 0 & speed = 0,
-- level 3 if unsigned = 0 & speed = 1,
-- level 3 if signed = 1 & speed = 0,
-- level 6 if signed = 1 & speed = 1
gfsc: IF (fixed_width < 64) GENERATE
shiftinbus <= delabsnode & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
gfsd: IF (fixed_width = 64) GENERATE
shiftinbus <= delabsnode;
END GENERATE;
gssa: IF (speed = 0) GENERATE
sftzip: dp_lsft64
PORT MAP (inbus=>shiftinbus,shift=>delcount,
outbus=>shiftnode);
END GENERATE;
gssb: IF (speed = 1) GENERATE
sftone: dp_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>shiftinbus,shift=>delcount,
outbus=>shiftnode);
END GENERATE;
dels: fp_del
GENERIC MAP (width=>fixed_width,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>shiftnode(64 DOWNTO 65-fixed_width),cc=>delshift);
gsoa: IF (fixed_width = 64) GENERATE
shiftvalue <= delshift;
END GENERATE;
gsob: IF (fixed_width < 64) GENERATE
shiftvalue <= delshift & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
--*** LEVEL 3-8 (OUTPUT) ***
-- level 3 if unsigned = 0 & speed = 0,
-- level 5 if unsigned = 0 & speed = 1,
-- level 4 if signed = 1 & speed = 0,
-- level 8 if signed = 1 & speed = 1
-- single precision
goa: IF (fixed_precision <= 23 AND mantissa_width = 23) GENERATE
mantissaroundbit <= '0';
exponentroundnode <= delexponentnode;
goax: FOR k IN 1 TO 8 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
gob: IF (fixed_precision > 23 AND mantissa_width = 23) GENERATE
mantissaroundbit <= ( shiftvalue(41) AND shiftvalue(40) ) OR
(NOT(shiftvalue(41)) AND shiftvalue(40) AND
(shiftvalue(39) OR shiftvalue(38) OR shiftvalue(37) OR shiftvalue(36) OR
shiftvalue(35) OR shiftvalue(34) OR shiftvalue(33) OR shiftvalue(32) OR
shiftvalue(31) OR shiftvalue(30) OR shiftvalue(29) OR shiftvalue(28)));
-- check for mantissa overflow here
exponentroundnode <= delexponentnode;
gobx: FOR k IN 1 TO 8 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
-- double precision
goc: IF (fixed_precision <= 52 AND mantissa_width = 52) GENERATE
mantissaroundbit <= '0';
exponentroundnode <= delexponentnode;
gocx: FOR k IN 1 TO 11 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
god: IF (fixed_width > 52 AND mantissa_width = 52) GENERATE
mantissaroundbit <= (shiftvalue(12) AND shiftvalue(11)) OR
(NOT(shiftvalue(12)) AND shiftvalue(11) AND
(shiftvalue(10) OR shiftvalue(9) OR shiftvalue(8) OR shiftvalue(7) OR
shiftvalue(6) OR shiftvalue(5) OR shiftvalue(4) OR shiftvalue(3) OR
shiftvalue(2) OR shiftvalue(1)));
-- check for mantissa overflow here
exponentroundnode <= delexponentnode;
godx: FOR k IN 1 TO 11 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
gsgna: IF (unsigned = 0) GENERATE
sign <= '0';
END GENERATE;
gsgnb: IF (unsigned = 1) GENERATE
delss: fp_delbit
GENERIC MAP (pipes=>4+4*speed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fixed_number(decimal+fractional),cc=>sign);
END GENERATE;
mno: dp_addpipe
GENERIC MAP (width=>mantissa_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>shiftvalue(63 DOWNTO 64-mantissa_width),
bb=>zerovec(mantissa_width DOWNTO 1),
carryin=>mantissaroundbit,
cc=>mantissa);
exo: dp_addpipe
GENERIC MAP (width=>exponent_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>exponentoutnode,
bb=>zerovec(exponent_width DOWNTO 1),
--carryin=>mantissaoverflowbit,
carryin=>'0',
cc=>exponent);
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CONVERSION - TOP LEVEL ***
--*** ***
--*** DP_FIXFLOAT.VHD ***
--*** ***
--*** Function: Convert Fixed Point to Floating ***
--*** Point Number ***
--*** ***
--*** 01/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** LATENCY : unsigned = 3 + 3*speed ***
--*** LATENCY : signed = 4 + 4*speed ***
--***************************************************
ENTITY dp_fixfloat IS
GENERIC (
unsigned : integer := 0; -- unsigned = 0, signed = 1
decimal : integer := 18;
fractional : integer := 14;
precision : integer := 0; -- single = 0, double = 1
speed : integer := 0 -- low speed = 0, high speed = 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fixed_number : IN STD_LOGIC_VECTOR (decimal+fractional DOWNTO 1);
sign : OUT STD_LOGIC;
exponent : OUT STD_LOGIC_VECTOR (8+3*precision DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23+29*precision DOWNTO 1)
);
END dp_fixfloat;
ARCHITECTURE rtl of dp_fixfloat IS
constant fixed_width : positive := decimal + fractional;
-- unsigned has 1 bit less (due to leading 1), signed has 2 less (leading 1 and sign)
constant fixed_precision : positive := fixed_width - unsigned - 1;
constant mantissa_width : positive := 23 + 29*precision;
constant exponent_width : positive := 8 + 3*precision;
constant exponent_base_number : positive := 126+896*precision+decimal;
-- input stage
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentbase : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
signal invfixed : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
signal absnode, delabsnode : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
-- detect range stage
signal clzinbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal count, delcount : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal zerochk, delzerochk : STD_LOGIC;
signal exponentnode, delexponentnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
-- normalize stage
signal shiftinbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal delshift : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
signal shiftvalue : STD_LOGIC_VECTOR (64 DOWNTO 1);
-- output stage
signal mantissaroundbit : STD_LOGIC;
signal exponentoutnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
signal exponentroundnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
component dp_addpipe IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_clz64 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component dp_clzpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mantissa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component dp_lsft64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component dp_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_delbit IS
GENERIC (
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC;
cc : OUT STD_LOGIC
);
end component;
BEGIN
gera : IF NOT((precision = 0) OR
(precision = 1)) GENERATE
assert false report "precision must be 0 (single precision) or 1 (double precision)" severity error;
END GENERATE;
gerb : IF NOT((speed = 0) OR
(speed = 1)) GENERATE
assert false report "speed must be 0 or 1" severity error;
END GENERATE;
gerc : IF NOT((unsigned = 0) OR
(unsigned = 1)) GENERATE
assert false report "unsigned must be 0 or 1" severity error;
END GENERATE;
gerd : IF (decimal < 1) GENERATE
assert false report "decimal must be greater than 1" severity error;
END GENERATE;
gere : IF (fixed_width > 64) GENERATE
assert false report "maximum fixed point precision must be 64 or less" severity error;
END GENERATE;
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
exponentbase <= conv_std_logic_vector (exponent_base_number,exponent_width);
--*** LEVEL 0 - 2 (ABSNODE) ***
-- level 0 if unsigned = 0,
-- level 1 if signed = 1 & speed = 0,
-- level 2 if signed = 1 & speed = 1
gabsa: IF (unsigned = 1) GENERATE
giva: FOR k IN 1 TO fixed_width GENERATE
invfixed(k) <= fixed_number(k) XOR fixed_number(fixed_width);
END GENERATE;
aabs: dp_addpipe
GENERIC MAP (width=>fixed_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>invfixed,bb=>zerovec(fixed_width DOWNTO 1),carryin=>fixed_number(fixed_width),
cc=>absnode);
END GENERATE;
gabsb: IF (unsigned = 0) GENERATE
invfixed <= fixed_number;
absnode <= invfixed;
END GENERATE;
gczc: IF (fixed_width < 64) GENERATE
clzinbus <= absnode & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
gczd: IF (fixed_width = 64) GENERATE
clzinbus <= absnode;
END GENERATE;
--*** LEVEL 1-4 (ABSDELNODE, COUNTFF) ***
-- level 1 if unsigned = 0 & speed = 0,
-- level 2 if unsigned = 0 & speed = 1,
-- level 2 if signed = 1 & speed = 0,
-- level 4 if signed = 1 & speed = 1
gcca: IF (speed = 0) GENERATE
cntzip: dp_clz64
PORT MAP (mantissa=>clzinbus,leading=>count);
END GENERATE;
gccb: IF (speed = 1) GENERATE
cntone: dp_clzpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mantissa=>clzinbus,leading=>count);
END GENERATE;
delabsbus: fp_del
GENERIC MAP (width=>fixed_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absnode,cc=>delabsnode);
ddc: fp_del
GENERIC MAP (width=>6,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>count,cc=>delcount);
-- check for 0 input - when countff = 0 and absdelnode(64) (unsigned) or
-- absdelnode(63) (signed) not '1'
zerochk <= NOT(delcount(6) OR delcount(5) OR delcount(4) OR delcount(3) OR
delcount(2) OR delcount(1) OR delabsnode(fixed_width) OR delabsnode(fixed_width-1));
delzc: fp_delbit
GENERIC MAP (pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>zerochk,cc=>delzerochk);
exponentnode <= exponentbase - (zerovec(2+3*precision DOWNTO 1) & delcount);
delx: fp_del
GENERIC MAP (width=>exponent_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>exponentnode,cc=>delexponentnode);
--*** LEVEL 2-6 (SHIFTFF) ***
-- level 2 if unsigned = 0 & speed = 0,
-- level 3 if unsigned = 0 & speed = 1,
-- level 3 if signed = 1 & speed = 0,
-- level 6 if signed = 1 & speed = 1
gfsc: IF (fixed_width < 64) GENERATE
shiftinbus <= delabsnode & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
gfsd: IF (fixed_width = 64) GENERATE
shiftinbus <= delabsnode;
END GENERATE;
gssa: IF (speed = 0) GENERATE
sftzip: dp_lsft64
PORT MAP (inbus=>shiftinbus,shift=>delcount,
outbus=>shiftnode);
END GENERATE;
gssb: IF (speed = 1) GENERATE
sftone: dp_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>shiftinbus,shift=>delcount,
outbus=>shiftnode);
END GENERATE;
dels: fp_del
GENERIC MAP (width=>fixed_width,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>shiftnode(64 DOWNTO 65-fixed_width),cc=>delshift);
gsoa: IF (fixed_width = 64) GENERATE
shiftvalue <= delshift;
END GENERATE;
gsob: IF (fixed_width < 64) GENERATE
shiftvalue <= delshift & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
--*** LEVEL 3-8 (OUTPUT) ***
-- level 3 if unsigned = 0 & speed = 0,
-- level 5 if unsigned = 0 & speed = 1,
-- level 4 if signed = 1 & speed = 0,
-- level 8 if signed = 1 & speed = 1
-- single precision
goa: IF (fixed_precision <= 23 AND mantissa_width = 23) GENERATE
mantissaroundbit <= '0';
exponentroundnode <= delexponentnode;
goax: FOR k IN 1 TO 8 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
gob: IF (fixed_precision > 23 AND mantissa_width = 23) GENERATE
mantissaroundbit <= ( shiftvalue(41) AND shiftvalue(40) ) OR
(NOT(shiftvalue(41)) AND shiftvalue(40) AND
(shiftvalue(39) OR shiftvalue(38) OR shiftvalue(37) OR shiftvalue(36) OR
shiftvalue(35) OR shiftvalue(34) OR shiftvalue(33) OR shiftvalue(32) OR
shiftvalue(31) OR shiftvalue(30) OR shiftvalue(29) OR shiftvalue(28)));
-- check for mantissa overflow here
exponentroundnode <= delexponentnode;
gobx: FOR k IN 1 TO 8 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
-- double precision
goc: IF (fixed_precision <= 52 AND mantissa_width = 52) GENERATE
mantissaroundbit <= '0';
exponentroundnode <= delexponentnode;
gocx: FOR k IN 1 TO 11 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
god: IF (fixed_width > 52 AND mantissa_width = 52) GENERATE
mantissaroundbit <= (shiftvalue(12) AND shiftvalue(11)) OR
(NOT(shiftvalue(12)) AND shiftvalue(11) AND
(shiftvalue(10) OR shiftvalue(9) OR shiftvalue(8) OR shiftvalue(7) OR
shiftvalue(6) OR shiftvalue(5) OR shiftvalue(4) OR shiftvalue(3) OR
shiftvalue(2) OR shiftvalue(1)));
-- check for mantissa overflow here
exponentroundnode <= delexponentnode;
godx: FOR k IN 1 TO 11 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
gsgna: IF (unsigned = 0) GENERATE
sign <= '0';
END GENERATE;
gsgnb: IF (unsigned = 1) GENERATE
delss: fp_delbit
GENERIC MAP (pipes=>4+4*speed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fixed_number(decimal+fractional),cc=>sign);
END GENERATE;
mno: dp_addpipe
GENERIC MAP (width=>mantissa_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>shiftvalue(63 DOWNTO 64-mantissa_width),
bb=>zerovec(mantissa_width DOWNTO 1),
carryin=>mantissaroundbit,
cc=>mantissa);
exo: dp_addpipe
GENERIC MAP (width=>exponent_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>exponentoutnode,
bb=>zerovec(exponent_width DOWNTO 1),
--carryin=>mantissaoverflowbit,
carryin=>'0',
cc=>exponent);
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CONVERSION - TOP LEVEL ***
--*** ***
--*** DP_FIXFLOAT.VHD ***
--*** ***
--*** Function: Convert Fixed Point to Floating ***
--*** Point Number ***
--*** ***
--*** 01/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** LATENCY : unsigned = 3 + 3*speed ***
--*** LATENCY : signed = 4 + 4*speed ***
--***************************************************
ENTITY dp_fixfloat IS
GENERIC (
unsigned : integer := 0; -- unsigned = 0, signed = 1
decimal : integer := 18;
fractional : integer := 14;
precision : integer := 0; -- single = 0, double = 1
speed : integer := 0 -- low speed = 0, high speed = 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fixed_number : IN STD_LOGIC_VECTOR (decimal+fractional DOWNTO 1);
sign : OUT STD_LOGIC;
exponent : OUT STD_LOGIC_VECTOR (8+3*precision DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23+29*precision DOWNTO 1)
);
END dp_fixfloat;
ARCHITECTURE rtl of dp_fixfloat IS
constant fixed_width : positive := decimal + fractional;
-- unsigned has 1 bit less (due to leading 1), signed has 2 less (leading 1 and sign)
constant fixed_precision : positive := fixed_width - unsigned - 1;
constant mantissa_width : positive := 23 + 29*precision;
constant exponent_width : positive := 8 + 3*precision;
constant exponent_base_number : positive := 126+896*precision+decimal;
-- input stage
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentbase : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
signal invfixed : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
signal absnode, delabsnode : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
-- detect range stage
signal clzinbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal count, delcount : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal zerochk, delzerochk : STD_LOGIC;
signal exponentnode, delexponentnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
-- normalize stage
signal shiftinbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal delshift : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
signal shiftvalue : STD_LOGIC_VECTOR (64 DOWNTO 1);
-- output stage
signal mantissaroundbit : STD_LOGIC;
signal exponentoutnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
signal exponentroundnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
component dp_addpipe IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_clz64 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component dp_clzpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mantissa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component dp_lsft64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component dp_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_delbit IS
GENERIC (
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC;
cc : OUT STD_LOGIC
);
end component;
BEGIN
gera : IF NOT((precision = 0) OR
(precision = 1)) GENERATE
assert false report "precision must be 0 (single precision) or 1 (double precision)" severity error;
END GENERATE;
gerb : IF NOT((speed = 0) OR
(speed = 1)) GENERATE
assert false report "speed must be 0 or 1" severity error;
END GENERATE;
gerc : IF NOT((unsigned = 0) OR
(unsigned = 1)) GENERATE
assert false report "unsigned must be 0 or 1" severity error;
END GENERATE;
gerd : IF (decimal < 1) GENERATE
assert false report "decimal must be greater than 1" severity error;
END GENERATE;
gere : IF (fixed_width > 64) GENERATE
assert false report "maximum fixed point precision must be 64 or less" severity error;
END GENERATE;
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
exponentbase <= conv_std_logic_vector (exponent_base_number,exponent_width);
--*** LEVEL 0 - 2 (ABSNODE) ***
-- level 0 if unsigned = 0,
-- level 1 if signed = 1 & speed = 0,
-- level 2 if signed = 1 & speed = 1
gabsa: IF (unsigned = 1) GENERATE
giva: FOR k IN 1 TO fixed_width GENERATE
invfixed(k) <= fixed_number(k) XOR fixed_number(fixed_width);
END GENERATE;
aabs: dp_addpipe
GENERIC MAP (width=>fixed_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>invfixed,bb=>zerovec(fixed_width DOWNTO 1),carryin=>fixed_number(fixed_width),
cc=>absnode);
END GENERATE;
gabsb: IF (unsigned = 0) GENERATE
invfixed <= fixed_number;
absnode <= invfixed;
END GENERATE;
gczc: IF (fixed_width < 64) GENERATE
clzinbus <= absnode & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
gczd: IF (fixed_width = 64) GENERATE
clzinbus <= absnode;
END GENERATE;
--*** LEVEL 1-4 (ABSDELNODE, COUNTFF) ***
-- level 1 if unsigned = 0 & speed = 0,
-- level 2 if unsigned = 0 & speed = 1,
-- level 2 if signed = 1 & speed = 0,
-- level 4 if signed = 1 & speed = 1
gcca: IF (speed = 0) GENERATE
cntzip: dp_clz64
PORT MAP (mantissa=>clzinbus,leading=>count);
END GENERATE;
gccb: IF (speed = 1) GENERATE
cntone: dp_clzpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mantissa=>clzinbus,leading=>count);
END GENERATE;
delabsbus: fp_del
GENERIC MAP (width=>fixed_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absnode,cc=>delabsnode);
ddc: fp_del
GENERIC MAP (width=>6,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>count,cc=>delcount);
-- check for 0 input - when countff = 0 and absdelnode(64) (unsigned) or
-- absdelnode(63) (signed) not '1'
zerochk <= NOT(delcount(6) OR delcount(5) OR delcount(4) OR delcount(3) OR
delcount(2) OR delcount(1) OR delabsnode(fixed_width) OR delabsnode(fixed_width-1));
delzc: fp_delbit
GENERIC MAP (pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>zerochk,cc=>delzerochk);
exponentnode <= exponentbase - (zerovec(2+3*precision DOWNTO 1) & delcount);
delx: fp_del
GENERIC MAP (width=>exponent_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>exponentnode,cc=>delexponentnode);
--*** LEVEL 2-6 (SHIFTFF) ***
-- level 2 if unsigned = 0 & speed = 0,
-- level 3 if unsigned = 0 & speed = 1,
-- level 3 if signed = 1 & speed = 0,
-- level 6 if signed = 1 & speed = 1
gfsc: IF (fixed_width < 64) GENERATE
shiftinbus <= delabsnode & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
gfsd: IF (fixed_width = 64) GENERATE
shiftinbus <= delabsnode;
END GENERATE;
gssa: IF (speed = 0) GENERATE
sftzip: dp_lsft64
PORT MAP (inbus=>shiftinbus,shift=>delcount,
outbus=>shiftnode);
END GENERATE;
gssb: IF (speed = 1) GENERATE
sftone: dp_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>shiftinbus,shift=>delcount,
outbus=>shiftnode);
END GENERATE;
dels: fp_del
GENERIC MAP (width=>fixed_width,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>shiftnode(64 DOWNTO 65-fixed_width),cc=>delshift);
gsoa: IF (fixed_width = 64) GENERATE
shiftvalue <= delshift;
END GENERATE;
gsob: IF (fixed_width < 64) GENERATE
shiftvalue <= delshift & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
--*** LEVEL 3-8 (OUTPUT) ***
-- level 3 if unsigned = 0 & speed = 0,
-- level 5 if unsigned = 0 & speed = 1,
-- level 4 if signed = 1 & speed = 0,
-- level 8 if signed = 1 & speed = 1
-- single precision
goa: IF (fixed_precision <= 23 AND mantissa_width = 23) GENERATE
mantissaroundbit <= '0';
exponentroundnode <= delexponentnode;
goax: FOR k IN 1 TO 8 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
gob: IF (fixed_precision > 23 AND mantissa_width = 23) GENERATE
mantissaroundbit <= ( shiftvalue(41) AND shiftvalue(40) ) OR
(NOT(shiftvalue(41)) AND shiftvalue(40) AND
(shiftvalue(39) OR shiftvalue(38) OR shiftvalue(37) OR shiftvalue(36) OR
shiftvalue(35) OR shiftvalue(34) OR shiftvalue(33) OR shiftvalue(32) OR
shiftvalue(31) OR shiftvalue(30) OR shiftvalue(29) OR shiftvalue(28)));
-- check for mantissa overflow here
exponentroundnode <= delexponentnode;
gobx: FOR k IN 1 TO 8 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
-- double precision
goc: IF (fixed_precision <= 52 AND mantissa_width = 52) GENERATE
mantissaroundbit <= '0';
exponentroundnode <= delexponentnode;
gocx: FOR k IN 1 TO 11 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
god: IF (fixed_width > 52 AND mantissa_width = 52) GENERATE
mantissaroundbit <= (shiftvalue(12) AND shiftvalue(11)) OR
(NOT(shiftvalue(12)) AND shiftvalue(11) AND
(shiftvalue(10) OR shiftvalue(9) OR shiftvalue(8) OR shiftvalue(7) OR
shiftvalue(6) OR shiftvalue(5) OR shiftvalue(4) OR shiftvalue(3) OR
shiftvalue(2) OR shiftvalue(1)));
-- check for mantissa overflow here
exponentroundnode <= delexponentnode;
godx: FOR k IN 1 TO 11 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
gsgna: IF (unsigned = 0) GENERATE
sign <= '0';
END GENERATE;
gsgnb: IF (unsigned = 1) GENERATE
delss: fp_delbit
GENERIC MAP (pipes=>4+4*speed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fixed_number(decimal+fractional),cc=>sign);
END GENERATE;
mno: dp_addpipe
GENERIC MAP (width=>mantissa_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>shiftvalue(63 DOWNTO 64-mantissa_width),
bb=>zerovec(mantissa_width DOWNTO 1),
carryin=>mantissaroundbit,
cc=>mantissa);
exo: dp_addpipe
GENERIC MAP (width=>exponent_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>exponentoutnode,
bb=>zerovec(exponent_width DOWNTO 1),
--carryin=>mantissaoverflowbit,
carryin=>'0',
cc=>exponent);
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CONVERSION - TOP LEVEL ***
--*** ***
--*** DP_FIXFLOAT.VHD ***
--*** ***
--*** Function: Convert Fixed Point to Floating ***
--*** Point Number ***
--*** ***
--*** 01/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** LATENCY : unsigned = 3 + 3*speed ***
--*** LATENCY : signed = 4 + 4*speed ***
--***************************************************
ENTITY dp_fixfloat IS
GENERIC (
unsigned : integer := 0; -- unsigned = 0, signed = 1
decimal : integer := 18;
fractional : integer := 14;
precision : integer := 0; -- single = 0, double = 1
speed : integer := 0 -- low speed = 0, high speed = 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fixed_number : IN STD_LOGIC_VECTOR (decimal+fractional DOWNTO 1);
sign : OUT STD_LOGIC;
exponent : OUT STD_LOGIC_VECTOR (8+3*precision DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23+29*precision DOWNTO 1)
);
END dp_fixfloat;
ARCHITECTURE rtl of dp_fixfloat IS
constant fixed_width : positive := decimal + fractional;
-- unsigned has 1 bit less (due to leading 1), signed has 2 less (leading 1 and sign)
constant fixed_precision : positive := fixed_width - unsigned - 1;
constant mantissa_width : positive := 23 + 29*precision;
constant exponent_width : positive := 8 + 3*precision;
constant exponent_base_number : positive := 126+896*precision+decimal;
-- input stage
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentbase : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
signal invfixed : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
signal absnode, delabsnode : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
-- detect range stage
signal clzinbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal count, delcount : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal zerochk, delzerochk : STD_LOGIC;
signal exponentnode, delexponentnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
-- normalize stage
signal shiftinbus : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal delshift : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
signal shiftvalue : STD_LOGIC_VECTOR (64 DOWNTO 1);
-- output stage
signal mantissaroundbit : STD_LOGIC;
signal exponentoutnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
signal exponentroundnode : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
component dp_addpipe IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_clz64 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component dp_clzpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mantissa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component dp_lsft64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component dp_lsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_delbit IS
GENERIC (
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC;
cc : OUT STD_LOGIC
);
end component;
BEGIN
gera : IF NOT((precision = 0) OR
(precision = 1)) GENERATE
assert false report "precision must be 0 (single precision) or 1 (double precision)" severity error;
END GENERATE;
gerb : IF NOT((speed = 0) OR
(speed = 1)) GENERATE
assert false report "speed must be 0 or 1" severity error;
END GENERATE;
gerc : IF NOT((unsigned = 0) OR
(unsigned = 1)) GENERATE
assert false report "unsigned must be 0 or 1" severity error;
END GENERATE;
gerd : IF (decimal < 1) GENERATE
assert false report "decimal must be greater than 1" severity error;
END GENERATE;
gere : IF (fixed_width > 64) GENERATE
assert false report "maximum fixed point precision must be 64 or less" severity error;
END GENERATE;
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
exponentbase <= conv_std_logic_vector (exponent_base_number,exponent_width);
--*** LEVEL 0 - 2 (ABSNODE) ***
-- level 0 if unsigned = 0,
-- level 1 if signed = 1 & speed = 0,
-- level 2 if signed = 1 & speed = 1
gabsa: IF (unsigned = 1) GENERATE
giva: FOR k IN 1 TO fixed_width GENERATE
invfixed(k) <= fixed_number(k) XOR fixed_number(fixed_width);
END GENERATE;
aabs: dp_addpipe
GENERIC MAP (width=>fixed_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>invfixed,bb=>zerovec(fixed_width DOWNTO 1),carryin=>fixed_number(fixed_width),
cc=>absnode);
END GENERATE;
gabsb: IF (unsigned = 0) GENERATE
invfixed <= fixed_number;
absnode <= invfixed;
END GENERATE;
gczc: IF (fixed_width < 64) GENERATE
clzinbus <= absnode & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
gczd: IF (fixed_width = 64) GENERATE
clzinbus <= absnode;
END GENERATE;
--*** LEVEL 1-4 (ABSDELNODE, COUNTFF) ***
-- level 1 if unsigned = 0 & speed = 0,
-- level 2 if unsigned = 0 & speed = 1,
-- level 2 if signed = 1 & speed = 0,
-- level 4 if signed = 1 & speed = 1
gcca: IF (speed = 0) GENERATE
cntzip: dp_clz64
PORT MAP (mantissa=>clzinbus,leading=>count);
END GENERATE;
gccb: IF (speed = 1) GENERATE
cntone: dp_clzpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mantissa=>clzinbus,leading=>count);
END GENERATE;
delabsbus: fp_del
GENERIC MAP (width=>fixed_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absnode,cc=>delabsnode);
ddc: fp_del
GENERIC MAP (width=>6,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>count,cc=>delcount);
-- check for 0 input - when countff = 0 and absdelnode(64) (unsigned) or
-- absdelnode(63) (signed) not '1'
zerochk <= NOT(delcount(6) OR delcount(5) OR delcount(4) OR delcount(3) OR
delcount(2) OR delcount(1) OR delabsnode(fixed_width) OR delabsnode(fixed_width-1));
delzc: fp_delbit
GENERIC MAP (pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>zerochk,cc=>delzerochk);
exponentnode <= exponentbase - (zerovec(2+3*precision DOWNTO 1) & delcount);
delx: fp_del
GENERIC MAP (width=>exponent_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>exponentnode,cc=>delexponentnode);
--*** LEVEL 2-6 (SHIFTFF) ***
-- level 2 if unsigned = 0 & speed = 0,
-- level 3 if unsigned = 0 & speed = 1,
-- level 3 if signed = 1 & speed = 0,
-- level 6 if signed = 1 & speed = 1
gfsc: IF (fixed_width < 64) GENERATE
shiftinbus <= delabsnode & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
gfsd: IF (fixed_width = 64) GENERATE
shiftinbus <= delabsnode;
END GENERATE;
gssa: IF (speed = 0) GENERATE
sftzip: dp_lsft64
PORT MAP (inbus=>shiftinbus,shift=>delcount,
outbus=>shiftnode);
END GENERATE;
gssb: IF (speed = 1) GENERATE
sftone: dp_lsftpipe64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>shiftinbus,shift=>delcount,
outbus=>shiftnode);
END GENERATE;
dels: fp_del
GENERIC MAP (width=>fixed_width,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>shiftnode(64 DOWNTO 65-fixed_width),cc=>delshift);
gsoa: IF (fixed_width = 64) GENERATE
shiftvalue <= delshift;
END GENERATE;
gsob: IF (fixed_width < 64) GENERATE
shiftvalue <= delshift & zerovec(64-fixed_width DOWNTO 1);
END GENERATE;
--*** LEVEL 3-8 (OUTPUT) ***
-- level 3 if unsigned = 0 & speed = 0,
-- level 5 if unsigned = 0 & speed = 1,
-- level 4 if signed = 1 & speed = 0,
-- level 8 if signed = 1 & speed = 1
-- single precision
goa: IF (fixed_precision <= 23 AND mantissa_width = 23) GENERATE
mantissaroundbit <= '0';
exponentroundnode <= delexponentnode;
goax: FOR k IN 1 TO 8 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
gob: IF (fixed_precision > 23 AND mantissa_width = 23) GENERATE
mantissaroundbit <= ( shiftvalue(41) AND shiftvalue(40) ) OR
(NOT(shiftvalue(41)) AND shiftvalue(40) AND
(shiftvalue(39) OR shiftvalue(38) OR shiftvalue(37) OR shiftvalue(36) OR
shiftvalue(35) OR shiftvalue(34) OR shiftvalue(33) OR shiftvalue(32) OR
shiftvalue(31) OR shiftvalue(30) OR shiftvalue(29) OR shiftvalue(28)));
-- check for mantissa overflow here
exponentroundnode <= delexponentnode;
gobx: FOR k IN 1 TO 8 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
-- double precision
goc: IF (fixed_precision <= 52 AND mantissa_width = 52) GENERATE
mantissaroundbit <= '0';
exponentroundnode <= delexponentnode;
gocx: FOR k IN 1 TO 11 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
god: IF (fixed_width > 52 AND mantissa_width = 52) GENERATE
mantissaroundbit <= (shiftvalue(12) AND shiftvalue(11)) OR
(NOT(shiftvalue(12)) AND shiftvalue(11) AND
(shiftvalue(10) OR shiftvalue(9) OR shiftvalue(8) OR shiftvalue(7) OR
shiftvalue(6) OR shiftvalue(5) OR shiftvalue(4) OR shiftvalue(3) OR
shiftvalue(2) OR shiftvalue(1)));
-- check for mantissa overflow here
exponentroundnode <= delexponentnode;
godx: FOR k IN 1 TO 11 GENERATE
exponentoutnode(k) <= exponentroundnode(k) AND NOT(delzerochk);
END GENERATE;
END GENERATE;
gsgna: IF (unsigned = 0) GENERATE
sign <= '0';
END GENERATE;
gsgnb: IF (unsigned = 1) GENERATE
delss: fp_delbit
GENERIC MAP (pipes=>4+4*speed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fixed_number(decimal+fractional),cc=>sign);
END GENERATE;
mno: dp_addpipe
GENERIC MAP (width=>mantissa_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>shiftvalue(63 DOWNTO 64-mantissa_width),
bb=>zerovec(mantissa_width DOWNTO 1),
carryin=>mantissaroundbit,
cc=>mantissa);
exo: dp_addpipe
GENERIC MAP (width=>exponent_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>exponentoutnode,
bb=>zerovec(exponent_width DOWNTO 1),
--carryin=>mantissaoverflowbit,
carryin=>'0',
cc=>exponent);
END rtl;
|
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
|
---------------------------------------------------------------------
---- ----
---- Run-Once Counter ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
--
-- CVS Log
--
-- $Id: ro_cnt.vhd,v 1.1 2002/03/01 03:49:03 rherveille Exp $
--
-- $Date: 2002/03/01 03:49:03 $
-- $Revision: 1.1 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: ro_cnt.vhd,v $
-- Revision 1.1 2002/03/01 03:49:03 rherveille
-- Changed internal counter libraries.
-- Split counter.vhd into separate files.
-- Core is in same state as Verilog version now.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ro_cnt is
generic(
SIZE : natural := 8;
UD : integer := 0; -- default count down
ID : natural := 0 -- initial data after reset
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic := '1'; -- asynchronous active low reset
rst : in std_logic := '0'; -- synchronous active high reset
cnt_en : in std_logic := '1'; -- count enable
go : in std_logic; -- load counter and start sequence
done : out std_logic; -- done counting
d : in std_logic_vector(SIZE -1 downto 0); -- load counter value
q : out std_logic_vector(SIZE -1 downto 0) -- current counter value
);
end entity ro_cnt;
architecture structural of ro_cnt is
component ud_cnt is
generic(
SIZE : natural := 8;
RESD : natural := 0 -- initial data after reset
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic := '1'; -- asynchronous active low reset
rst : in std_logic := '0'; -- synchronous active high reset
cnt_en : in std_logic := '1'; -- count enable
ud : in std_logic := '0'; -- up / not down
nld : in std_logic := '1'; -- synchronous active low load
d : in std_logic_vector(SIZE -1 downto 0); -- load counter value
q : out std_logic_vector(SIZE -1 downto 0); -- current counter value
rci : in std_logic := '1'; -- carry input
rco : out std_logic -- carry output
);
end component ud_cnt;
signal rci, rco, nld, UDP : std_logic;
begin
gen_ctrl: process(clk, nReset)
begin
if (nReset = '0') then
rci <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
rci <= '0';
else
rci <= go or (rci and not rco);
end if;
end if;
end process;
nld <= not go;
UDP <= '0' when UD = 0 else '1';
-- hookup counter
cnt : ud_cnt
generic map (
SIZE => SIZE,
RESD => ID
)
port map (
clk => clk,
nReset => nReset,
rst => rst,
cnt_en => cnt_en,
ud => UDP,
nld => nld,
D => D,
Q => Q,
rci => rci,
rco => rco
);
done <= rco;
end architecture structural;
|
---------------------------------------------------------------------
---- ----
---- Run-Once Counter ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2001, 2002 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
--
-- CVS Log
--
-- $Id: ro_cnt.vhd,v 1.1 2002/03/01 03:49:03 rherveille Exp $
--
-- $Date: 2002/03/01 03:49:03 $
-- $Revision: 1.1 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: ro_cnt.vhd,v $
-- Revision 1.1 2002/03/01 03:49:03 rherveille
-- Changed internal counter libraries.
-- Split counter.vhd into separate files.
-- Core is in same state as Verilog version now.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ro_cnt is
generic(
SIZE : natural := 8;
UD : integer := 0; -- default count down
ID : natural := 0 -- initial data after reset
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic := '1'; -- asynchronous active low reset
rst : in std_logic := '0'; -- synchronous active high reset
cnt_en : in std_logic := '1'; -- count enable
go : in std_logic; -- load counter and start sequence
done : out std_logic; -- done counting
d : in std_logic_vector(SIZE -1 downto 0); -- load counter value
q : out std_logic_vector(SIZE -1 downto 0) -- current counter value
);
end entity ro_cnt;
architecture structural of ro_cnt is
component ud_cnt is
generic(
SIZE : natural := 8;
RESD : natural := 0 -- initial data after reset
);
port(
clk : in std_logic; -- master clock
nReset : in std_logic := '1'; -- asynchronous active low reset
rst : in std_logic := '0'; -- synchronous active high reset
cnt_en : in std_logic := '1'; -- count enable
ud : in std_logic := '0'; -- up / not down
nld : in std_logic := '1'; -- synchronous active low load
d : in std_logic_vector(SIZE -1 downto 0); -- load counter value
q : out std_logic_vector(SIZE -1 downto 0); -- current counter value
rci : in std_logic := '1'; -- carry input
rco : out std_logic -- carry output
);
end component ud_cnt;
signal rci, rco, nld, UDP : std_logic;
begin
gen_ctrl: process(clk, nReset)
begin
if (nReset = '0') then
rci <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
rci <= '0';
else
rci <= go or (rci and not rco);
end if;
end if;
end process;
nld <= not go;
UDP <= '0' when UD = 0 else '1';
-- hookup counter
cnt : ud_cnt
generic map (
SIZE => SIZE,
RESD => ID
)
port map (
clk => clk,
nReset => nReset,
rst => rst,
cnt_en => cnt_en,
ud => UDP,
nld => nld,
D => D,
Q => Q,
rci => rci,
rco => rco
);
done <= rco;
end architecture structural;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2173.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n01i02173ent IS
END c07s02b05x00p01n01i02173ent;
ARCHITECTURE c07s02b05x00p01n01i02173arch OF c07s02b05x00p01n01i02173ent IS
BEGIN
TESTING: PROCESS
constant x1: integer := - 10;
BEGIN
assert NOT(x1=-10)
report "***PASSED TEST: c07s02b05x00p01n01i02173"
severity NOTE;
assert (x1=-10)
report "***FAILED TEST: c07s02b05x00p01n01i02173 - Signs - can be used with only numeric types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n01i02173arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2173.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n01i02173ent IS
END c07s02b05x00p01n01i02173ent;
ARCHITECTURE c07s02b05x00p01n01i02173arch OF c07s02b05x00p01n01i02173ent IS
BEGIN
TESTING: PROCESS
constant x1: integer := - 10;
BEGIN
assert NOT(x1=-10)
report "***PASSED TEST: c07s02b05x00p01n01i02173"
severity NOTE;
assert (x1=-10)
report "***FAILED TEST: c07s02b05x00p01n01i02173 - Signs - can be used with only numeric types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n01i02173arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2173.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n01i02173ent IS
END c07s02b05x00p01n01i02173ent;
ARCHITECTURE c07s02b05x00p01n01i02173arch OF c07s02b05x00p01n01i02173ent IS
BEGIN
TESTING: PROCESS
constant x1: integer := - 10;
BEGIN
assert NOT(x1=-10)
report "***PASSED TEST: c07s02b05x00p01n01i02173"
severity NOTE;
assert (x1=-10)
report "***FAILED TEST: c07s02b05x00p01n01i02173 - Signs - can be used with only numeric types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n01i02173arch;
|
-------------------------------------------------------------------------------
-- $Id: proc_common_pkg.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_common_pkg.vhd
-- Version: v1.21b
-- Description: This file contains the constants and functions used in the
-- processor common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 09/12/01 -- Created from opb_arb_pkg.vhd
--
-- ALS 09/21/01
-- ^^^^^^
-- Added pwr function. Replaced log2 function with one that works for XST.
-- ~~~~~~
--
-- ALS 12/07/01
-- ^^^^^^
-- Added Addr_bits function.
-- ~~~~~~
-- ALS 01/31/02
-- ^^^^^^
-- Added max2 function.
-- ~~~~~~
-- FLO 02/22/02
-- ^^^^^^
-- Extended input argument range of log2 function to 2^30. Also, added
-- a check that the argument does not exceed this value; a failure
-- assertion violation is generated if it does not.
-- ~~~~~~
-- FLO 08/31/06
-- ^^^^^^
-- Removed type TARGET_FAMILY_TYPE and functions Get_Reg_File_Area and
-- Get_RLOC_Name. These objects are not used. Further, the functions
-- produced misleading warnings (CR419886, CR419898).
-- ~~~~~~
-- FLO 05/25/07
-- ^^^^^^
-- -Reimplemented function pad_power2 to correct error when the input
-- argument is 1. (fixes CR 303469)
-- -Added function clog2(x), which returns the integer ceiling of the
-- base 2 logarithm of x. This function can be used in place of log2
-- when wishing to avoid the XST warning, "VHDL Assertion Statement
-- with non constant condition is ignored".
-- ~~~~~~
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package proc_common_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
-- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63);
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer;
function min2 (num1, num2 : integer) return integer;
function Addr_Bits(x,y : std_logic_vector) return integer;
function clog2(x : positive) return natural;
function pad_power2 ( in_num : integer ) return integer;
function pad_4 ( in_num : integer ) return integer;
function log2(x : natural) return integer;
function pwr(x: integer; y: integer) return integer;
function String_To_Int(S : string) return integer;
function itoa (int : integer) return string;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- the RESET_ACTIVE constant should denote the logic level of an active reset
constant RESET_ACTIVE : std_logic := '1';
-- table containing strings representing hex characters for conversion to
-- integers
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
end proc_common_pkg;
package body proc_common_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function min2
--
-- This function returns the lesser of two numbers.
-------------------------------------------------------------------------------
function min2 (num1, num2 : integer) return integer is
begin
if num1 <= num2 then
return num1;
else
return num2;
end if;
end function min2;
-------------------------------------------------------------------------------
-- Function Addr_bits
--
-- function to convert an address range (base address and an upper address)
-- into the number of upper address bits needed for decoding a device
-- select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits(x,y : std_logic_vector) return integer is
variable addr_xor : std_logic_vector(x'range);
variable count : integer := 0;
begin
assert x'length = y'length and (x'ascending xnor y'ascending)
report "Addr_Bits: arguments are not the same type"
severity ERROR;
addr_xor := x xor y;
for i in x'range
loop
if addr_xor(i) = '1' then return count;
end if;
count := count + 1;
end loop;
return x'length;
end Addr_Bits;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function pad_power2
--
-- This function returns the next power of 2 from the input number. If the
-- input number is a power of 2, this function returns the input number.
--
-- This function is used to round up the number of masters to the next power
-- of 2 if the number of masters is not already a power of 2.
--
-- Input argument 0, which is not a power of two, is accepted and returns 0.
-- Input arguments less than 0 are not allowed.
-------------------------------------------------------------------------------
--
function pad_power2 (in_num : integer ) return integer is
begin
if in_num = 0 then
return 0;
else
return 2**(clog2(in_num));
end if;
end pad_power2;
-------------------------------------------------------------------------------
-- Function pad_4
--
-- This function returns the next multiple of 4 from the input number. If the
-- input number is a multiple of 4, this function returns the input number.
--
-------------------------------------------------------------------------------
--
function pad_4 (in_num : integer ) return integer is
variable out_num : integer;
begin
out_num := (((in_num-1)/4) + 1)*4;
return out_num;
end pad_4;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- x**y
-- negative numbers not allowed for y
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
-------------------------------------------------------------------------------
-- Function itoa
--
-- The itoa function converts an integer to a text string.
-- This function is required since `image doesn't work in Synplicity
-- Valid input range is -9999 to 9999
-------------------------------------------------------------------------------
--
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end itoa;
-----------------------------------------------------------------------------
-- Function String_To_Int
--
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
-- ASCII value - 42 TBD
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end String_To_Int;
end package body proc_common_pkg;
|
-------------------------------------------------------------------------------
-- $Id: proc_common_pkg.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_common_pkg.vhd
-- Version: v1.21b
-- Description: This file contains the constants and functions used in the
-- processor common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 09/12/01 -- Created from opb_arb_pkg.vhd
--
-- ALS 09/21/01
-- ^^^^^^
-- Added pwr function. Replaced log2 function with one that works for XST.
-- ~~~~~~
--
-- ALS 12/07/01
-- ^^^^^^
-- Added Addr_bits function.
-- ~~~~~~
-- ALS 01/31/02
-- ^^^^^^
-- Added max2 function.
-- ~~~~~~
-- FLO 02/22/02
-- ^^^^^^
-- Extended input argument range of log2 function to 2^30. Also, added
-- a check that the argument does not exceed this value; a failure
-- assertion violation is generated if it does not.
-- ~~~~~~
-- FLO 08/31/06
-- ^^^^^^
-- Removed type TARGET_FAMILY_TYPE and functions Get_Reg_File_Area and
-- Get_RLOC_Name. These objects are not used. Further, the functions
-- produced misleading warnings (CR419886, CR419898).
-- ~~~~~~
-- FLO 05/25/07
-- ^^^^^^
-- -Reimplemented function pad_power2 to correct error when the input
-- argument is 1. (fixes CR 303469)
-- -Added function clog2(x), which returns the integer ceiling of the
-- base 2 logarithm of x. This function can be used in place of log2
-- when wishing to avoid the XST warning, "VHDL Assertion Statement
-- with non constant condition is ignored".
-- ~~~~~~
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package proc_common_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
-- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63);
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer;
function min2 (num1, num2 : integer) return integer;
function Addr_Bits(x,y : std_logic_vector) return integer;
function clog2(x : positive) return natural;
function pad_power2 ( in_num : integer ) return integer;
function pad_4 ( in_num : integer ) return integer;
function log2(x : natural) return integer;
function pwr(x: integer; y: integer) return integer;
function String_To_Int(S : string) return integer;
function itoa (int : integer) return string;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- the RESET_ACTIVE constant should denote the logic level of an active reset
constant RESET_ACTIVE : std_logic := '1';
-- table containing strings representing hex characters for conversion to
-- integers
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
end proc_common_pkg;
package body proc_common_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function min2
--
-- This function returns the lesser of two numbers.
-------------------------------------------------------------------------------
function min2 (num1, num2 : integer) return integer is
begin
if num1 <= num2 then
return num1;
else
return num2;
end if;
end function min2;
-------------------------------------------------------------------------------
-- Function Addr_bits
--
-- function to convert an address range (base address and an upper address)
-- into the number of upper address bits needed for decoding a device
-- select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits(x,y : std_logic_vector) return integer is
variable addr_xor : std_logic_vector(x'range);
variable count : integer := 0;
begin
assert x'length = y'length and (x'ascending xnor y'ascending)
report "Addr_Bits: arguments are not the same type"
severity ERROR;
addr_xor := x xor y;
for i in x'range
loop
if addr_xor(i) = '1' then return count;
end if;
count := count + 1;
end loop;
return x'length;
end Addr_Bits;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function pad_power2
--
-- This function returns the next power of 2 from the input number. If the
-- input number is a power of 2, this function returns the input number.
--
-- This function is used to round up the number of masters to the next power
-- of 2 if the number of masters is not already a power of 2.
--
-- Input argument 0, which is not a power of two, is accepted and returns 0.
-- Input arguments less than 0 are not allowed.
-------------------------------------------------------------------------------
--
function pad_power2 (in_num : integer ) return integer is
begin
if in_num = 0 then
return 0;
else
return 2**(clog2(in_num));
end if;
end pad_power2;
-------------------------------------------------------------------------------
-- Function pad_4
--
-- This function returns the next multiple of 4 from the input number. If the
-- input number is a multiple of 4, this function returns the input number.
--
-------------------------------------------------------------------------------
--
function pad_4 (in_num : integer ) return integer is
variable out_num : integer;
begin
out_num := (((in_num-1)/4) + 1)*4;
return out_num;
end pad_4;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- x**y
-- negative numbers not allowed for y
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
-------------------------------------------------------------------------------
-- Function itoa
--
-- The itoa function converts an integer to a text string.
-- This function is required since `image doesn't work in Synplicity
-- Valid input range is -9999 to 9999
-------------------------------------------------------------------------------
--
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end itoa;
-----------------------------------------------------------------------------
-- Function String_To_Int
--
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
-- ASCII value - 42 TBD
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end String_To_Int;
end package body proc_common_pkg;
|
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Mon Jun 05 08:32:55 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system.bd
--Design : system
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
clk_100 : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
enable_nm : in STD_LOGIC;
hdmi_clk : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hsync : in STD_LOGIC;
pclk : in STD_LOGIC;
ready : out STD_LOGIC;
reset : in STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
vsync : in STD_LOGIC;
xclk : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of system : entity is "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=22,numReposBlks=22,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system : entity is "system.hwdef";
end system;
architecture STRUCTURE of system is
component system_ov7670_controller_0_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
end component system_ov7670_controller_0_0;
component system_zed_hdmi_0_0 is
port (
clk : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
clk_100 : in STD_LOGIC;
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC
);
end component system_zed_hdmi_0_0;
component system_rgb565_to_rgb888_0_0 is
port (
clk : in STD_LOGIC;
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_rgb565_to_rgb888_0_0;
component system_vga_buffer_0_0 is
port (
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
wen : in STD_LOGIC;
x_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
data_w : in STD_LOGIC_VECTOR ( 23 downto 0 );
data_r : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_buffer_0_0;
component system_vga_sync_reset_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_reset_0_0;
component system_vga_sync_ref_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
start : out STD_LOGIC;
active : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_ref_0_0;
component system_debounce_0_0 is
port (
clk : in STD_LOGIC;
signal_in : in STD_LOGIC;
signal_out : out STD_LOGIC
);
end component system_debounce_0_0;
component system_ov7670_vga_0_0 is
port (
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end component system_ov7670_vga_0_0;
component system_clock_splitter_0_0 is
port (
clk_in : in STD_LOGIC;
latch_edge : in STD_LOGIC;
clk_out : out STD_LOGIC
);
end component system_clock_splitter_0_0;
component system_rgb888_to_g8_0_0 is
port (
clk : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
g8 : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component system_rgb888_to_g8_0_0;
component system_rgb888_mux_2_0_0 is
port (
clk : in STD_LOGIC;
sel : in STD_LOGIC;
rgb888_0 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb888_1 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_rgb888_mux_2_0_0;
component system_xlconstant_0_0 is
port (
dout : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_xlconstant_0_0;
component system_comparator_0_0 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC
);
end component system_comparator_0_0;
component system_xlconstant_0_1 is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_xlconstant_0_1;
component system_clk_wiz_0_0 is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC
);
end component system_clk_wiz_0_0;
component system_clk_wiz_1_0 is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC
);
end component system_clk_wiz_1_0;
component system_xlconstant_0_2 is
port (
dout : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component system_xlconstant_0_2;
component system_buffer_register_0_0 is
port (
clk : in STD_LOGIC;
val_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
val_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_buffer_register_0_0;
component system_inverter_0_0 is
port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
end component system_inverter_0_0;
component system_vga_hessian_0_0 is
port (
clk_x16 : in STD_LOGIC;
active : in STD_LOGIC;
rst : in STD_LOGIC;
x_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr : in STD_LOGIC_VECTOR ( 9 downto 0 );
g_in : in STD_LOGIC_VECTOR ( 7 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_vga_hessian_0_0;
component system_vga_nmsuppression_0_0 is
port (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
active : in STD_LOGIC;
x_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
x_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component system_vga_nmsuppression_0_0;
component system_vga_pll_0_0 is
port (
clk_100 : in STD_LOGIC;
clk_50 : out STD_LOGIC;
clk_25 : out STD_LOGIC;
clk_12_5 : out STD_LOGIC;
clk_6_25 : out STD_LOGIC
);
end component system_vga_pll_0_0;
signal Net : STD_LOGIC;
signal Net1 : STD_LOGIC;
signal buffer_register_0_val_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal clk_100_1 : STD_LOGIC;
signal clk_wiz_0_clk_out1 : STD_LOGIC;
signal clk_wiz_1_clk_out1 : STD_LOGIC;
signal clock_splitter_0_clk_out : STD_LOGIC;
signal comparator_0_z : STD_LOGIC;
signal data_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal debounce_0_o : STD_LOGIC;
signal enable_1 : STD_LOGIC;
signal hsync_1 : STD_LOGIC;
signal inverter_0_x_not : STD_LOGIC;
signal ov7670_controller_0_config_finished : STD_LOGIC;
signal ov7670_controller_0_sioc : STD_LOGIC;
signal ov7670_vga_0_rgb : STD_LOGIC_VECTOR ( 15 downto 0 );
signal pclk_1 : STD_LOGIC;
signal reset_1 : STD_LOGIC;
signal rgb565_to_rgb888_0_rgb_888 : STD_LOGIC_VECTOR ( 23 downto 0 );
signal rgb888_mux_2_0_rgb888 : STD_LOGIC_VECTOR ( 23 downto 0 );
signal rgb888_to_g8_0_g8 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal threshold_dout : STD_LOGIC_VECTOR ( 31 downto 0 );
signal vdd_dout : STD_LOGIC_VECTOR ( 0 to 0 );
signal vga_buffer_0_data_r : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_hessian_0_hessian_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal vga_nmsuppression_0_hessian_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal vga_pll_0_clk_12_6 : STD_LOGIC;
signal vga_pll_0_clk_25 : STD_LOGIC;
signal vga_sync_ref_0_active : STD_LOGIC;
signal vga_sync_ref_0_start : STD_LOGIC;
signal vga_sync_ref_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_ref_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_reset_0_active : STD_LOGIC;
signal vga_sync_reset_0_hsync : STD_LOGIC;
signal vga_sync_reset_0_vsync : STD_LOGIC;
signal vga_sync_reset_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_reset_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vsync_1 : STD_LOGIC;
signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 23 downto 0 );
signal zed_hdmi_0_hdmi_clk : STD_LOGIC;
signal zed_hdmi_0_hdmi_d : STD_LOGIC_VECTOR ( 15 downto 0 );
signal zed_hdmi_0_hdmi_de : STD_LOGIC;
signal zed_hdmi_0_hdmi_hsync : STD_LOGIC;
signal zed_hdmi_0_hdmi_scl : STD_LOGIC;
signal zed_hdmi_0_hdmi_vsync : STD_LOGIC;
signal NLW_clk_wiz_0_locked_UNCONNECTED : STD_LOGIC;
signal NLW_clk_wiz_1_locked_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_0_pwdn_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_0_reset_UNCONNECTED : STD_LOGIC;
signal NLW_ov7670_controller_0_xclk_UNCONNECTED : STD_LOGIC;
signal NLW_vga_nmsuppression_0_x_addr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_vga_nmsuppression_0_y_addr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_vga_pll_0_clk_50_UNCONNECTED : STD_LOGIC;
signal NLW_vga_pll_0_clk_6_25_UNCONNECTED : STD_LOGIC;
begin
clk_100_1 <= clk_100;
data_1(7 downto 0) <= data(7 downto 0);
enable_1 <= enable_nm;
hdmi_clk <= zed_hdmi_0_hdmi_clk;
hdmi_d(15 downto 0) <= zed_hdmi_0_hdmi_d(15 downto 0);
hdmi_de <= zed_hdmi_0_hdmi_de;
hdmi_hsync <= zed_hdmi_0_hdmi_hsync;
hdmi_scl <= zed_hdmi_0_hdmi_scl;
hdmi_vsync <= zed_hdmi_0_hdmi_vsync;
hsync_1 <= hsync;
pclk_1 <= pclk;
ready <= ov7670_controller_0_config_finished;
reset_1 <= reset;
sioc <= ov7670_controller_0_sioc;
vsync_1 <= vsync;
xclk <= clk_wiz_0_clk_out1;
buffer_register_0: component system_buffer_register_0_0
port map (
clk => vga_pll_0_clk_12_6,
val_in(31 downto 0) => vga_hessian_0_hessian_out(31 downto 0),
val_out(31 downto 0) => buffer_register_0_val_out(31 downto 0)
);
clk_wiz_0: component system_clk_wiz_0_0
port map (
clk_in1 => clk_100_1,
clk_out1 => clk_wiz_0_clk_out1,
locked => NLW_clk_wiz_0_locked_UNCONNECTED
);
clk_wiz_1: component system_clk_wiz_1_0
port map (
clk_in1 => clk_100_1,
clk_out1 => clk_wiz_1_clk_out1,
locked => NLW_clk_wiz_1_locked_UNCONNECTED
);
clock_splitter_0: component system_clock_splitter_0_0
port map (
clk_in => pclk_1,
clk_out => clock_splitter_0_clk_out,
latch_edge => vsync_1
);
comparator_0: component system_comparator_0_0
port map (
x(31 downto 0) => vga_nmsuppression_0_hessian_out(31 downto 0),
y(31 downto 0) => threshold_dout(31 downto 0),
z => comparator_0_z
);
debounce_0: component system_debounce_0_0
port map (
clk => vga_pll_0_clk_25,
signal_in => reset_1,
signal_out => debounce_0_o
);
inverter_0: component system_inverter_0_0
port map (
x => vga_sync_ref_0_start,
x_not => inverter_0_x_not
);
ov7670_controller_0: component system_ov7670_controller_0_0
port map (
clk => vga_pll_0_clk_25,
config_finished => ov7670_controller_0_config_finished,
pwdn => NLW_ov7670_controller_0_pwdn_UNCONNECTED,
resend => debounce_0_o,
reset => NLW_ov7670_controller_0_reset_UNCONNECTED,
sioc => ov7670_controller_0_sioc,
siod => siod,
xclk => NLW_ov7670_controller_0_xclk_UNCONNECTED
);
ov7670_vga_0: component system_ov7670_vga_0_0
port map (
active => vga_sync_ref_0_active,
clk_x2 => pclk_1,
data(7 downto 0) => data_1(7 downto 0),
rgb(15 downto 0) => ov7670_vga_0_rgb(15 downto 0)
);
rgb565_to_rgb888_0: component system_rgb565_to_rgb888_0_0
port map (
clk => clock_splitter_0_clk_out,
rgb_565(15 downto 0) => ov7670_vga_0_rgb(15 downto 0),
rgb_888(23 downto 0) => rgb565_to_rgb888_0_rgb_888(23 downto 0)
);
rgb888_mux_2_0: component system_rgb888_mux_2_0_0
port map (
clk => vga_pll_0_clk_12_6,
rgb888(23 downto 0) => rgb888_mux_2_0_rgb888(23 downto 0),
rgb888_0(23 downto 0) => vga_buffer_0_data_r(23 downto 0),
rgb888_1(23 downto 0) => xlconstant_0_dout(23 downto 0),
sel => comparator_0_z
);
rgb888_to_g8_0: component system_rgb888_to_g8_0_0
port map (
clk => vga_pll_0_clk_12_6,
g8(7 downto 0) => rgb888_to_g8_0_g8(7 downto 0),
rgb888(23 downto 0) => vga_buffer_0_data_r(23 downto 0)
);
threshold: component system_xlconstant_0_1
port map (
dout(31 downto 0) => threshold_dout(31 downto 0)
);
vdd: component system_xlconstant_0_2
port map (
dout(0) => vdd_dout(0)
);
vga_buffer_0: component system_vga_buffer_0_0
port map (
clk_r => vga_pll_0_clk_12_6,
clk_w => clock_splitter_0_clk_out,
data_r(23 downto 0) => vga_buffer_0_data_r(23 downto 0),
data_w(23 downto 0) => rgb565_to_rgb888_0_rgb_888(23 downto 0),
wen => vga_sync_ref_0_active,
x_addr_r(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
x_addr_w(9 downto 0) => vga_sync_ref_0_xaddr(9 downto 0),
y_addr_r(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0),
y_addr_w(9 downto 0) => vga_sync_ref_0_yaddr(9 downto 0)
);
vga_hessian_0: component system_vga_hessian_0_0
port map (
active => vga_sync_reset_0_active,
clk_x16 => clk_wiz_1_clk_out1,
g_in(7 downto 0) => rgb888_to_g8_0_g8(7 downto 0),
hessian_out(31 downto 0) => vga_hessian_0_hessian_out(31 downto 0),
rst => vdd_dout(0),
x_addr(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
y_addr(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0)
);
vga_nmsuppression_0: component system_vga_nmsuppression_0_0
port map (
active => vga_sync_reset_0_active,
clk => vga_pll_0_clk_12_6,
enable => enable_1,
hessian_in(31 downto 0) => buffer_register_0_val_out(31 downto 0),
hessian_out(31 downto 0) => vga_nmsuppression_0_hessian_out(31 downto 0),
x_addr_in(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
x_addr_out(9 downto 0) => NLW_vga_nmsuppression_0_x_addr_out_UNCONNECTED(9 downto 0),
y_addr_in(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0),
y_addr_out(9 downto 0) => NLW_vga_nmsuppression_0_y_addr_out_UNCONNECTED(9 downto 0)
);
vga_pll_0: component system_vga_pll_0_0
port map (
clk_100 => clk_100_1,
clk_12_5 => vga_pll_0_clk_12_6,
clk_25 => vga_pll_0_clk_25,
clk_50 => NLW_vga_pll_0_clk_50_UNCONNECTED,
clk_6_25 => NLW_vga_pll_0_clk_6_25_UNCONNECTED
);
vga_sync_ref_0: component system_vga_sync_ref_0_0
port map (
active => vga_sync_ref_0_active,
clk => clock_splitter_0_clk_out,
hsync => hsync_1,
rst => ov7670_controller_0_config_finished,
start => vga_sync_ref_0_start,
vsync => vsync_1,
xaddr(9 downto 0) => vga_sync_ref_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_ref_0_yaddr(9 downto 0)
);
vga_sync_reset_0: component system_vga_sync_reset_0_0
port map (
active => vga_sync_reset_0_active,
clk => vga_pll_0_clk_12_6,
hsync => vga_sync_reset_0_hsync,
rst => inverter_0_x_not,
vsync => vga_sync_reset_0_vsync,
xaddr(9 downto 0) => vga_sync_reset_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_reset_0_yaddr(9 downto 0)
);
white: component system_xlconstant_0_0
port map (
dout(23 downto 0) => xlconstant_0_dout(23 downto 0)
);
zed_hdmi_0: component system_zed_hdmi_0_0
port map (
active => vga_sync_reset_0_active,
clk => vga_pll_0_clk_12_6,
clk_100 => clk_100_1,
clk_x2 => vga_pll_0_clk_25,
hdmi_clk => zed_hdmi_0_hdmi_clk,
hdmi_d(15 downto 0) => zed_hdmi_0_hdmi_d(15 downto 0),
hdmi_de => zed_hdmi_0_hdmi_de,
hdmi_hsync => zed_hdmi_0_hdmi_hsync,
hdmi_scl => zed_hdmi_0_hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => zed_hdmi_0_hdmi_vsync,
hsync => vga_sync_reset_0_hsync,
rgb888(23 downto 0) => rgb888_mux_2_0_rgb888(23 downto 0),
vsync => vga_sync_reset_0_vsync
);
end STRUCTURE;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY sl2 IS
PORT(a: IN std_logic_vector(0 TO 31);
y: OUT std_logic_vector(0 TO 31));
END Sl2;
ARCHITECTURE sl2_est OF sl2 IS
BEGIN
PROCESS(a)
VARIABLE temp: std_logic_vector(0 TO 31);
VARIABLE length: integer := 0;
BEGIN
length := a'LENGTH;
FOR i IN 0 TO length-3 LOOP --los primeros 29 bits
temp(i) := a(i+2);
END LOOP;
temp(length-2) := '0';
temp(length-1) := '0';
y <= temp;
END PROCESS;
END sl2_est;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY sl2 IS
PORT(a: IN std_logic_vector(0 TO 31);
y: OUT std_logic_vector(0 TO 31));
END Sl2;
ARCHITECTURE sl2_est OF sl2 IS
BEGIN
PROCESS(a)
VARIABLE temp: std_logic_vector(0 TO 31);
VARIABLE length: integer := 0;
BEGIN
length := a'LENGTH;
FOR i IN 0 TO length-3 LOOP --los primeros 29 bits
temp(i) := a(i+2);
END LOOP;
temp(length-2) := '0';
temp(length-1) := '0';
y <= temp;
END PROCESS;
END sl2_est;
|
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: scfifo
-- ============================================================
-- File Name: sniff_fifo.vhd
-- Megafunction Name(s):
-- scfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 18.1.0 Build 625 09/12/2018 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2018 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors. Please
--refer to the applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY sniff_fifo IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
);
END sniff_fifo;
ARCHITECTURE SYN OF sniff_fifo IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (10 DOWNTO 0);
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdreq : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
);
END COMPONENT;
BEGIN
empty <= sub_wire0;
full <= sub_wire1;
q <= sub_wire2(15 DOWNTO 0);
usedw <= sub_wire3(10 DOWNTO 0);
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "OFF",
intended_device_family => "MAX 10",
lpm_numwords => 2048,
lpm_showahead => "ON",
lpm_type => "scfifo",
lpm_width => 16,
lpm_widthu => 11,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
PORT MAP (
clock => clock,
data => data,
rdreq => rdreq,
wrreq => wrreq,
empty => sub_wire0,
full => sub_wire1,
q => sub_wire2,
usedw => sub_wire3
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Depth NUMERIC "2048"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "16"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "16"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: usedw 0 0 11 0 OUTPUT NODEFVAL "usedw[10..0]"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
-- Retrieval info: CONNECT: usedw 0 0 11 0 @usedw 0 0 11 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL sniff_fifo.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sniff_fifo.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sniff_fifo.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sniff_fifo.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sniff_fifo_inst.vhd TRUE
-- Retrieval info: LIB_FILE: altera_mf
|
library verilog;
use verilog.vl_types.all;
entity usb_system_cpu_jtag_debug_module_tck is
port(
MonDReg : in vl_logic_vector(31 downto 0);
break_readreg : in vl_logic_vector(31 downto 0);
dbrk_hit0_latch : in vl_logic;
dbrk_hit1_latch : in vl_logic;
dbrk_hit2_latch : in vl_logic;
dbrk_hit3_latch : in vl_logic;
debugack : in vl_logic;
ir_in : in vl_logic_vector(1 downto 0);
jtag_state_rti : in vl_logic;
monitor_error : in vl_logic;
monitor_ready : in vl_logic;
reset_n : in vl_logic;
resetlatch : in vl_logic;
tck : in vl_logic;
tdi : in vl_logic;
tracemem_on : in vl_logic;
tracemem_trcdata: in vl_logic_vector(35 downto 0);
tracemem_tw : in vl_logic;
trc_im_addr : in vl_logic_vector(6 downto 0);
trc_on : in vl_logic;
trc_wrap : in vl_logic;
trigbrktype : in vl_logic;
trigger_state_1 : in vl_logic;
vs_cdr : in vl_logic;
vs_sdr : in vl_logic;
vs_uir : in vl_logic;
ir_out : out vl_logic_vector(1 downto 0);
jrst_n : out vl_logic;
sr : out vl_logic_vector(37 downto 0);
st_ready_test_idle: out vl_logic;
tdo : out vl_logic
);
end usb_system_cpu_jtag_debug_module_tck;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hfrisc_soc is
generic(
address_width: integer := 15;
memory_file : string := "code.txt"
);
port ( clk_i: in std_logic;
rst_i: in std_logic;
gpioa_in: in std_logic_vector(15 downto 0);
gpioa_out: out std_logic_vector(15 downto 0);
gpioa_ddr: out std_logic_vector(15 downto 0);
gpiob_in: in std_logic_vector(15 downto 0);
gpiob_out: out std_logic_vector(15 downto 0);
gpiob_ddr: out std_logic_vector(15 downto 0)
);
end hfrisc_soc;
architecture top_level of hfrisc_soc is
signal clock, boot_enable, ram_enable_n, stall, ram_dly, rff1, reset: std_logic;
signal address, data_read, data_write, data_read_boot, data_read_ram: std_logic_vector(31 downto 0);
signal ext_irq: std_logic_vector(7 downto 0);
signal data_we, data_w_n_ram: std_logic_vector(3 downto 0);
signal periph, periph_dly, periph_wr, periph_irq: std_logic;
signal data_read_periph, data_read_periph_s, data_write_periph: std_logic_vector(31 downto 0);
begin
-- clock divider (25MHz clock from 50MHz main clock for Spartan3 Starter Kit)
process (rst_i, clk_i, clock)
begin
if rst_i = '1' then
clock <= '0';
else
if clk_i'event and clk_i = '1' then
clock <= not clock;
end if;
end if;
end process;
-- reset synchronizer
process (clock, rst_i)
begin
if (rst_i = '1') then
rff1 <= '1';
reset <= '1';
elsif (clock'event and clock = '1') then
rff1 <= '0';
reset <= rff1;
end if;
end process;
process (reset, clock, ext_irq, ram_enable_n)
begin
if reset = '1' then
ram_dly <= '0';
periph_dly <= '0';
elsif clock'event and clock = '1' then
ram_dly <= not ram_enable_n;
periph_dly <= periph;
end if;
end process;
stall <= '0';
boot_enable <= '1' when address(31 downto 28) = "0000" else '0';
ram_enable_n <= '0' when address(31 downto 28) = "0100" else '1';
data_read <= data_read_periph when periph = '1' or periph_dly = '1' else data_read_boot when address(31 downto 28) = "0000" and ram_dly = '0' else data_read_ram;
data_w_n_ram <= not data_we;
ext_irq <= "0000000" & periph_irq;
-- HF-RISCV core
processor: entity work.processor
port map( clk_i => clock,
rst_i => reset,
stall_i => stall,
addr_o => address,
data_i => data_read,
data_o => data_write,
data_w_o => data_we,
data_mode_o => open,
extio_in => ext_irq,
extio_out => open
);
data_read_periph <= data_read_periph_s(7 downto 0) & data_read_periph_s(15 downto 8) & data_read_periph_s(23 downto 16) & data_read_periph_s(31 downto 24);
data_write_periph <= data_write(7 downto 0) & data_write(15 downto 8) & data_write(23 downto 16) & data_write(31 downto 24);
periph_wr <= '1' when data_we /= "0000" else '0';
periph <= '1' when address(31 downto 28) = x"e" else '0';
peripherals: entity work.peripherals
port map(
clk_i => clock,
rst_i => reset,
addr_i => address,
data_i => data_write_periph,
data_o => data_read_periph_s,
sel_i => periph,
wr_i => periph_wr,
irq_o => periph_irq,
gpioa_in => gpioa_in,
gpioa_out => gpioa_out,
gpioa_ddr => gpioa_ddr,
gpiob_in => gpiob_in,
gpiob_out => gpiob_out,
gpiob_ddr => gpiob_ddr
);
-- instruction and data memory (boot RAM)
boot_ram: entity work.ram
generic map (memory_type => "DEFAULT")
port map (
clk => clock,
enable => boot_enable,
write_byte_enable => "0000",
address => address(31 downto 2),
data_write => (others => '0'),
data_read => data_read_boot
);
-- instruction and data memory (external RAM)
memory0lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 0)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(0),
data_i => data_write(7 downto 0),
data_o => data_read_ram(7 downto 0)
);
memory0ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 1)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(1),
data_i => data_write(15 downto 8),
data_o => data_read_ram(15 downto 8)
);
memory1lb: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 2)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(2),
data_i => data_write(23 downto 16),
data_o => data_read_ram(23 downto 16)
);
memory1ub: entity work.bram
generic map ( memory_file => memory_file,
data_width => 8,
address_width => address_width,
bank => 3)
port map(
clk => clock,
addr => address(address_width -1 downto 2),
cs_n => ram_enable_n,
we_n => data_w_n_ram(3),
data_i => data_write(31 downto 24),
data_o => data_read_ram(31 downto 24)
);
end top_level;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2458.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02458ent IS
END c07s03b02x02p03n02i02458ent;
ARCHITECTURE c07s03b02x02p03n02i02458arch OF c07s03b02x02p03n02i02458ent IS
BEGIN
TESTING: PROCESS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
subtype CONSTRAINED_ARRAY is UNCONSTRAINED_ARRAY ( 1 to 3 );
variable V : CONSTRAINED_ARRAY ;
-- check in declaration of constrained array variable.
BEGIN
V := ( 'd','x',others => '$' );
-- check in variable assignment to constrained array object.
wait for 5 ns;
assert NOT( V(1)='d' and V(2)='x' and V(3)='$' )
report "***PASSED TEST: c07s03b02x02p03n02i02458"
severity NOTE;
assert ( V(1)='d' and V(2)='x' and V(3)='$' )
report "***FAILED TEST: c07s03b02x02p03n02i02458 - An array aggregate with an others choice may appear as a value expression in an assignment statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02458arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2458.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02458ent IS
END c07s03b02x02p03n02i02458ent;
ARCHITECTURE c07s03b02x02p03n02i02458arch OF c07s03b02x02p03n02i02458ent IS
BEGIN
TESTING: PROCESS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
subtype CONSTRAINED_ARRAY is UNCONSTRAINED_ARRAY ( 1 to 3 );
variable V : CONSTRAINED_ARRAY ;
-- check in declaration of constrained array variable.
BEGIN
V := ( 'd','x',others => '$' );
-- check in variable assignment to constrained array object.
wait for 5 ns;
assert NOT( V(1)='d' and V(2)='x' and V(3)='$' )
report "***PASSED TEST: c07s03b02x02p03n02i02458"
severity NOTE;
assert ( V(1)='d' and V(2)='x' and V(3)='$' )
report "***FAILED TEST: c07s03b02x02p03n02i02458 - An array aggregate with an others choice may appear as a value expression in an assignment statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02458arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2458.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02458ent IS
END c07s03b02x02p03n02i02458ent;
ARCHITECTURE c07s03b02x02p03n02i02458arch OF c07s03b02x02p03n02i02458ent IS
BEGIN
TESTING: PROCESS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
subtype CONSTRAINED_ARRAY is UNCONSTRAINED_ARRAY ( 1 to 3 );
variable V : CONSTRAINED_ARRAY ;
-- check in declaration of constrained array variable.
BEGIN
V := ( 'd','x',others => '$' );
-- check in variable assignment to constrained array object.
wait for 5 ns;
assert NOT( V(1)='d' and V(2)='x' and V(3)='$' )
report "***PASSED TEST: c07s03b02x02p03n02i02458"
severity NOTE;
assert ( V(1)='d' and V(2)='x' and V(3)='$' )
report "***FAILED TEST: c07s03b02x02p03n02i02458 - An array aggregate with an others choice may appear as a value expression in an assignment statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02458arch;
|
--========================================================================================================================
-- This VVC was generated with Bitvis VVC Generator
--========================================================================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
--========================================================================================================================
--========================================================================================================================
package vvc_methods_pkg is
--========================================================================================================================
-- Types and constants for the CLOCK_GENERATOR VVC
--========================================================================================================================
constant C_VVC_NAME : string := "CLOCK_GENERATOR_VVC";
signal CLOCK_GENERATOR_VVCT: t_vvc_target_record := set_vvc_target_defaults(C_VVC_NAME);
alias THIS_VVCT : t_vvc_target_record is CLOCK_GENERATOR_VVCT;
alias t_bfm_config is t_void_bfm_config;
-- Type found in UVVM-Util types_pkg
constant C_CLOCK_GENERATOR_INTER_BFM_DELAY_DEFAULT : t_inter_bfm_delay := (
delay_type => NO_DELAY,
delay_in_time => 0 ns,
inter_bfm_delay_violation_severity => WARNING
);
type t_vvc_config is
record
inter_bfm_delay : t_inter_bfm_delay;-- Minimum delay between BFM accesses from the VVC. If parameter delay_type is set to NO_DELAY, BFM accesses will be back to back, i.e. no delay.
cmd_queue_count_max : natural; -- Maximum pending number in command executor before executor is full. Adding additional commands will result in an ERROR.
cmd_queue_count_threshold : natural; -- An alert with severity 'cmd_queue_count_threshold_severity' will be issued if command executor exceeds this count. Used for early warning if command executor is almost full. Will be ignored if set to 0.
cmd_queue_count_threshold_severity : t_alert_level; -- Severity of alert to be initiated if exceeding cmd_queue_count_threshold
result_queue_count_max : natural;
result_queue_count_threshold_severity : t_alert_level;
result_queue_count_threshold : natural;
bfm_config : t_bfm_config;
msg_id_panel : t_msg_id_panel; -- VVC dedicated message ID panel
clock_name : string(1 to 30);
clock_period : time;
clock_high_time : time;
end record;
type t_vvc_config_array is array (natural range <>) of t_vvc_config;
constant C_CLOCK_GENERATOR_VVC_CONFIG_DEFAULT : t_vvc_config := (
inter_bfm_delay => C_CLOCK_GENERATOR_INTER_BFM_DELAY_DEFAULT,
cmd_queue_count_max => C_CMD_QUEUE_COUNT_MAX, -- from adaptation package
cmd_queue_count_threshold => C_CMD_QUEUE_COUNT_THRESHOLD,
cmd_queue_count_threshold_severity => C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_max => C_RESULT_QUEUE_COUNT_MAX,
result_queue_count_threshold_severity => C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_threshold => C_RESULT_QUEUE_COUNT_THRESHOLD,
bfm_config => C_VOID_BFM_CONFIG,
msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT,
clock_name => ("Set clock name", others => NUL),
clock_period => 10 ns,
clock_high_time => 5 ns
);
type t_vvc_status is
record
current_cmd_idx : natural;
previous_cmd_idx : natural;
pending_cmd_cnt : natural;
end record;
type t_vvc_status_array is array (natural range <>) of t_vvc_status;
constant C_VVC_STATUS_DEFAULT : t_vvc_status := (
current_cmd_idx => 0,
previous_cmd_idx => 0,
pending_cmd_cnt => 0
);
-- Transaction information to include in the wave view during simulation
type t_transaction_info is
record
operation : t_operation;
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
--<USER_INPUT> Fields that could be useful to track in the waveview can be placed in this record.
-- Example:
-- addr : unsigned(C_VVC_CMD_ADDR_MAX_LENGTH-1 downto 0);
-- data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
end record;
type t_transaction_info_array is array (natural range <>) of t_transaction_info;
constant C_TRANSACTION_INFO_DEFAULT : t_transaction_info := (
--<USER_INPUT> Set the data fields added to the t_transaction_info record to
-- their default values here.
-- Example:
-- addr => (others => '0'),
-- data => (others => '0'),
operation => NO_OPERATION,
msg => (others => ' ')
);
shared variable shared_clock_generator_vvc_config : t_vvc_config_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_CLOCK_GENERATOR_VVC_CONFIG_DEFAULT);
shared variable shared_clock_generator_vvc_status : t_vvc_status_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_VVC_STATUS_DEFAULT);
shared variable shared_clock_generator_transaction_info : t_transaction_info_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_TRANSACTION_INFO_DEFAULT);
--==========================================================================================
-- Methods dedicated to this VVC
-- - These procedures are called from the testbench in order for the VVC to execute
-- BFM calls towards the given interface. The VVC interpreter will queue these calls
-- and then the VVC executor will fetch the commands from the queue and handle the
-- actual BFM execution.
-- For details on how the BFM procedures work, see the QuickRef.
--==========================================================================================
procedure start_clock(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure stop_clock(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure set_clock_period(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant clock_period : in time;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure set_clock_high_time(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant clock_high_time : in time;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
end package vvc_methods_pkg;
package body vvc_methods_pkg is
--========================================================================================================================
-- Methods dedicated to this VVC
--========================================================================================================================
procedure start_clock(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "start_clock";
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ")";
begin
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, START_CLOCK);
send_command_to_vvc(VVCT, scope => scope);
end procedure start_clock;
procedure stop_clock(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "stop_clock";
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ")";
begin
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, STOP_CLOCK);
send_command_to_vvc(VVCT, scope => scope);
end procedure stop_clock;
procedure set_clock_period(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant clock_period : in time;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "set_clock_period";
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(clock_period) & ")";
begin
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SET_CLOCK_PERIOD);
shared_vvc_cmd.clock_period := clock_period;
send_command_to_vvc(VVCT, scope => scope);
end procedure set_clock_period;
procedure set_clock_high_time(
signal VVCT : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant clock_high_time : in time;
constant msg : in string;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "set_clock_high_time";
constant proc_call : string := proc_name & "(" & to_string(VVCT, vvc_instance_idx) -- First part common for all
& ", " & to_string(clock_high_time) & ")";
begin
set_general_target_and_command_fields(VVCT, vvc_instance_idx, proc_call, msg, QUEUED, SET_CLOCK_HIGH_TIME);
shared_vvc_cmd.clock_high_time := clock_high_time;
send_command_to_vvc(VVCT, scope => scope);
end procedure set_clock_high_time;
end package body vvc_methods_pkg;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: acache
-- File: acache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Interface module between I/D cache controllers and Amba AHB
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.leon3.all;
entity acache is
generic (
hindex : integer range 0 to NAHBMST-1 := 0;
ilinesize : integer range 4 to 8 := 4;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
mcii : in memory_ic_in_type;
mcio : out memory_ic_out_type;
mcdi : in memory_dc_in_type;
mcdo : out memory_dc_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbso : in ahb_slv_out_vector;
hclken : in std_ulogic
);
end;
architecture rtl of acache is
-- cache control register type
type reg_type is record
bg : std_ulogic; -- bus grant
bo : std_ulogic; -- bus owner
ba : std_ulogic; -- bus active
lb : std_ulogic; -- last burst cycle
retry : std_ulogic; -- retry/split pending
werr : std_ulogic; -- write error
hlocken : std_ulogic; -- ready to perform locked transaction
lock : std_ulogic; -- keep bus locked during SWAP sequence
hcache : std_ulogic;
iacc : std_ulogic;
dannul : std_ulogic;
end record;
type reg2_type is record
reqmsk : std_logic_vector(1 downto 0);
hclken2 : std_ulogic;
end record;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LEON3, 0, LEON3_VERSION, 0),
others => zero32);
constant ctbl : std_logic_vector(15 downto 0) := conv_std_logic_vector(cached, 16);
function dec_fixed(scache : std_ulogic;
haddr : std_logic_vector(3 downto 0); cached : integer) return std_ulogic is
begin
if (cached /= 0) then return ctbl(conv_integer(haddr(3 downto 0)));
else return(scache); end if;
end;
signal r, rin : reg_type;
signal r2, r2in : reg2_type;
begin
comb : process(ahbi, r, rst, mcii, mcdi, hclken, ahbso, r2)
variable v : reg_type;
variable v2 : reg2_type;
variable haddr : std_logic_vector(31 downto 0); -- address bus
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_ulogic; -- read/write
variable hlock : std_ulogic; -- bus lock
variable hsize : std_logic_vector(2 downto 0); -- transfer size
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable hwdata : std_logic_vector(31 downto 0); -- write data
variable hbusreq : std_ulogic; -- bus request
variable iready, dready : std_ulogic;
variable igrant, dgrant : std_ulogic;
variable iretry, dretry : std_ulogic;
variable ihcache, dhcache, dec_hcache : std_ulogic;
variable imexc, dmexc, nbo, ireq, dreq : std_ulogic;
variable su, nb : std_ulogic;
variable scanen : std_ulogic;
begin
-- initialisation
htrans := HTRANS_IDLE;
v := r; iready := '0'; v.werr := '0'; v2 := r2;
dready := '0'; igrant := '0'; dgrant := '0';
imexc := '0'; dmexc := '0'; hlock := '0'; iretry := '0'; dretry := '0';
ihcache := '0'; dhcache := '0'; su := '0'; --hcache := ahbi.hcache;
if ahbi.hready = '1' then v.lb := '0'; end if;
if scantest = 1 then scanen := ahbi.scanen; else scanen := '0'; end if;
-- generate AHB signals
ireq := mcii.req;
dreq := mcdi.req and not r.dannul;
if (clk2x /= 0) then ireq := ireq and r2.reqmsk(1); dreq := dreq and r2.reqmsk(0); end if;
hbusreq := ireq or dreq;
if hbusreq = '1' then htrans := HTRANS_NONSEQ; end if;
hwdata := mcdi.data;
nbo := (dreq and not (r.ba and mcii.req and not r.bo));
if (nbo and mcdi.lock and not r.hlocken) = '1' then htrans := HTRANS_IDLE; end if;
dec_hcache := ahb_slv_dec_cache(mcdi.address, ahbso, cached);
if nbo = '0' then
haddr := mcii.address; hwrite := '0'; hsize := HSIZE_WORD; hlock := '0';
su := mcii.su;
if (ireq and r.ba and not r.bo and not r.retry) = '1' then
htrans := HTRANS_SEQ; haddr(4 downto 2) := haddr(4 downto 2) +1;
if (((ilinesize = 4) and haddr(3 downto 2) = "10")
or ((ilinesize = 8) and haddr(4 downto 2) = "110")) and (ahbi.hready = '1')
then v.lb := '1'; end if;
end if;
if mcii.burst = '1' then
hburst := HBURST_INCR;
else hburst := HBURST_SINGLE; end if;
if (ireq and r.bg and ahbi.hready and not r.retry) = '1'
then igrant := '1'; v.hcache := dec_fixed(ahbi.hcache, haddr(31 downto 28), cached); end if;
else
haddr := mcdi.address; hwrite := not mcdi.read; hsize := '0' & mcdi.size;
hlock := mcdi.lock;
if mcdi.asi /= "1010" then su := '1'; else su := '0'; end if;
if mcdi.burst = '1' then hburst := HBURST_INCR;
else hburst := HBURST_SINGLE; end if;
if (dreq and r.ba and r.bo and not r.retry) = '1' then
htrans := HTRANS_SEQ; haddr(4 downto 2) := haddr(4 downto 2) +1;
hburst := HBURST_INCR;
end if;
if (dreq and r.bg and ahbi.hready and not r.retry) = '1'
then dgrant := not mcdi.lock or r.hlocken; v.hcache := dec_hcache; end if;
end if;
if (hclken = '1') or (clk2x = 0) then
if (r.ba = '1') and ((ahbi.hresp = HRESP_RETRY) or (ahbi.hresp = HRESP_SPLIT))
then v.retry := not ahbi.hready; else v.retry := '0'; end if;
end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
if r.bo = '0' then
if r.ba = '1' then
ihcache := r.hcache;
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => iready := '1';
when HRESP_RETRY | HRESP_SPLIT=> iretry := '1';
when others => iready := '1'; imexc := '1';
end case;
end if;
end if;
else
if r.ba = '1' then
dhcache := r.hcache;
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => dready := '1'; v.lock := mcdi.lock and mcdi.read;
when HRESP_RETRY | HRESP_SPLIT=> dretry := '1';
when others => dready := '1'; dmexc := '1'; v.werr := not mcdi.read;
end case;
end if;
end if;
hlock := mcdi.lock;
end if;
if r.lock = '1' then hlock := mcdi.lock; end if;
if (r.lock and nbo) = '1' then v.lock := '0'; end if;
-- decode cacheability
if (nbo = '1') and ((hsize = "011") or ((dec_hcache and mcdi.read and mcdi.cache) = '1')) then
hsize := "010"; haddr(1 downto 0) := "00";
end if;
if ahbi.hready = '1' then
v.iacc := r.bg and igrant;
if r.iacc = '1' then v.dannul := iretry;
elsif r.bg = '1' then v.dannul := '0'; end if;
v.bo := nbo; v.bg := ahbi.hgrant(hindex);
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) then
v.ba := r.bg;
else v.ba := '0'; end if;
v.hlocken := hlock and ahbi.hgrant(hindex);
if (clk2x /= 0) then v.hlocken := v.hlocken and r2.reqmsk(0); end if;
end if;
if hburst = HBURST_SINGLE then nb := '1'; else nb := '0'; end if;
if (clk2x /= 0) then
v2.hclken2 := hclken;
if (hclken = '1') then
v2.reqmsk := mcii.req & mcdi.req;
if (clk2x > 8) and (r2.hclken2 = '1') then v2.reqmsk := "11"; end if;
end if;
end if;
-- reset operation
if rst = '0' then
v.bg := '0'; v.bo := '0'; v.ba := '0'; v.retry := '0'; v.werr := '0'; v.lb := '0';
v.lock := '0'; v.hlocken := '0'; v2.reqmsk := "00";
end if;
-- drive ports
ahbo.haddr <= haddr ;
ahbo.htrans <= htrans;
ahbo.hbusreq <= hbusreq and not r.lb and not (((r.bo and r.ba) or nb) and r.bg and nbo);
ahbo.hwdata <= hwdata;
ahbo.hlock <= hlock;
ahbo.hwrite <= hwrite;
ahbo.hsize <= hsize;
ahbo.hburst <= hburst;
ahbo.hprot <= "11" & su & nbo;
ahbo.hindex <= hindex;
mcio.grant <= igrant;
mcio.ready <= iready;
mcio.mexc <= imexc;
mcio.retry <= iretry;
mcio.cache <= ihcache;
mcdo.grant <= dgrant;
mcdo.ready <= dready;
mcdo.mexc <= dmexc;
mcdo.retry <= dretry;
mcdo.werr <= r.werr;
mcdo.cache <= dhcache;
mcdo.ba <= r.ba;
mcdo.bg <= r.bg;
mcio.scanen <= scanen;
mcdo.scanen <= scanen;
mcdo.testen <= ahbi.testen;
mcdo.par <= (others => '0');
mcio.par <= (others => '0');
rin <= v; r2in <= v2;
end process;
mcio.data <= ahbi.hrdata; mcdo.data <= ahbi.hrdata;
ahbo.hirq <= (others => '0');
ahbo.hconfig <= hconfig;
reg : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
reg2gen : if (clk2x /= 0) generate
reg2 : process(clk)
begin
if rising_edge(clk) then r2 <= r2in; end if;
end process;
end generate;
noreg2gen : if (clk2x = 0) generate
r2.reqmsk <= "00";
end generate;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: acache
-- File: acache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Interface module between I/D cache controllers and Amba AHB
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.leon3.all;
entity acache is
generic (
hindex : integer range 0 to NAHBMST-1 := 0;
ilinesize : integer range 4 to 8 := 4;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
mcii : in memory_ic_in_type;
mcio : out memory_ic_out_type;
mcdi : in memory_dc_in_type;
mcdo : out memory_dc_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbso : in ahb_slv_out_vector;
hclken : in std_ulogic
);
end;
architecture rtl of acache is
-- cache control register type
type reg_type is record
bg : std_ulogic; -- bus grant
bo : std_ulogic; -- bus owner
ba : std_ulogic; -- bus active
lb : std_ulogic; -- last burst cycle
retry : std_ulogic; -- retry/split pending
werr : std_ulogic; -- write error
hlocken : std_ulogic; -- ready to perform locked transaction
lock : std_ulogic; -- keep bus locked during SWAP sequence
hcache : std_ulogic;
iacc : std_ulogic;
dannul : std_ulogic;
end record;
type reg2_type is record
reqmsk : std_logic_vector(1 downto 0);
hclken2 : std_ulogic;
end record;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LEON3, 0, LEON3_VERSION, 0),
others => zero32);
constant ctbl : std_logic_vector(15 downto 0) := conv_std_logic_vector(cached, 16);
function dec_fixed(scache : std_ulogic;
haddr : std_logic_vector(3 downto 0); cached : integer) return std_ulogic is
begin
if (cached /= 0) then return ctbl(conv_integer(haddr(3 downto 0)));
else return(scache); end if;
end;
signal r, rin : reg_type;
signal r2, r2in : reg2_type;
begin
comb : process(ahbi, r, rst, mcii, mcdi, hclken, ahbso, r2)
variable v : reg_type;
variable v2 : reg2_type;
variable haddr : std_logic_vector(31 downto 0); -- address bus
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_ulogic; -- read/write
variable hlock : std_ulogic; -- bus lock
variable hsize : std_logic_vector(2 downto 0); -- transfer size
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable hwdata : std_logic_vector(31 downto 0); -- write data
variable hbusreq : std_ulogic; -- bus request
variable iready, dready : std_ulogic;
variable igrant, dgrant : std_ulogic;
variable iretry, dretry : std_ulogic;
variable ihcache, dhcache, dec_hcache : std_ulogic;
variable imexc, dmexc, nbo, ireq, dreq : std_ulogic;
variable su, nb : std_ulogic;
variable scanen : std_ulogic;
begin
-- initialisation
htrans := HTRANS_IDLE;
v := r; iready := '0'; v.werr := '0'; v2 := r2;
dready := '0'; igrant := '0'; dgrant := '0';
imexc := '0'; dmexc := '0'; hlock := '0'; iretry := '0'; dretry := '0';
ihcache := '0'; dhcache := '0'; su := '0'; --hcache := ahbi.hcache;
if ahbi.hready = '1' then v.lb := '0'; end if;
if scantest = 1 then scanen := ahbi.scanen; else scanen := '0'; end if;
-- generate AHB signals
ireq := mcii.req;
dreq := mcdi.req and not r.dannul;
if (clk2x /= 0) then ireq := ireq and r2.reqmsk(1); dreq := dreq and r2.reqmsk(0); end if;
hbusreq := ireq or dreq;
if hbusreq = '1' then htrans := HTRANS_NONSEQ; end if;
hwdata := mcdi.data;
nbo := (dreq and not (r.ba and mcii.req and not r.bo));
if (nbo and mcdi.lock and not r.hlocken) = '1' then htrans := HTRANS_IDLE; end if;
dec_hcache := ahb_slv_dec_cache(mcdi.address, ahbso, cached);
if nbo = '0' then
haddr := mcii.address; hwrite := '0'; hsize := HSIZE_WORD; hlock := '0';
su := mcii.su;
if (ireq and r.ba and not r.bo and not r.retry) = '1' then
htrans := HTRANS_SEQ; haddr(4 downto 2) := haddr(4 downto 2) +1;
if (((ilinesize = 4) and haddr(3 downto 2) = "10")
or ((ilinesize = 8) and haddr(4 downto 2) = "110")) and (ahbi.hready = '1')
then v.lb := '1'; end if;
end if;
if mcii.burst = '1' then
hburst := HBURST_INCR;
else hburst := HBURST_SINGLE; end if;
if (ireq and r.bg and ahbi.hready and not r.retry) = '1'
then igrant := '1'; v.hcache := dec_fixed(ahbi.hcache, haddr(31 downto 28), cached); end if;
else
haddr := mcdi.address; hwrite := not mcdi.read; hsize := '0' & mcdi.size;
hlock := mcdi.lock;
if mcdi.asi /= "1010" then su := '1'; else su := '0'; end if;
if mcdi.burst = '1' then hburst := HBURST_INCR;
else hburst := HBURST_SINGLE; end if;
if (dreq and r.ba and r.bo and not r.retry) = '1' then
htrans := HTRANS_SEQ; haddr(4 downto 2) := haddr(4 downto 2) +1;
hburst := HBURST_INCR;
end if;
if (dreq and r.bg and ahbi.hready and not r.retry) = '1'
then dgrant := not mcdi.lock or r.hlocken; v.hcache := dec_hcache; end if;
end if;
if (hclken = '1') or (clk2x = 0) then
if (r.ba = '1') and ((ahbi.hresp = HRESP_RETRY) or (ahbi.hresp = HRESP_SPLIT))
then v.retry := not ahbi.hready; else v.retry := '0'; end if;
end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
if r.bo = '0' then
if r.ba = '1' then
ihcache := r.hcache;
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => iready := '1';
when HRESP_RETRY | HRESP_SPLIT=> iretry := '1';
when others => iready := '1'; imexc := '1';
end case;
end if;
end if;
else
if r.ba = '1' then
dhcache := r.hcache;
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => dready := '1'; v.lock := mcdi.lock and mcdi.read;
when HRESP_RETRY | HRESP_SPLIT=> dretry := '1';
when others => dready := '1'; dmexc := '1'; v.werr := not mcdi.read;
end case;
end if;
end if;
hlock := mcdi.lock;
end if;
if r.lock = '1' then hlock := mcdi.lock; end if;
if (r.lock and nbo) = '1' then v.lock := '0'; end if;
-- decode cacheability
if (nbo = '1') and ((hsize = "011") or ((dec_hcache and mcdi.read and mcdi.cache) = '1')) then
hsize := "010"; haddr(1 downto 0) := "00";
end if;
if ahbi.hready = '1' then
v.iacc := r.bg and igrant;
if r.iacc = '1' then v.dannul := iretry;
elsif r.bg = '1' then v.dannul := '0'; end if;
v.bo := nbo; v.bg := ahbi.hgrant(hindex);
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) then
v.ba := r.bg;
else v.ba := '0'; end if;
v.hlocken := hlock and ahbi.hgrant(hindex);
if (clk2x /= 0) then v.hlocken := v.hlocken and r2.reqmsk(0); end if;
end if;
if hburst = HBURST_SINGLE then nb := '1'; else nb := '0'; end if;
if (clk2x /= 0) then
v2.hclken2 := hclken;
if (hclken = '1') then
v2.reqmsk := mcii.req & mcdi.req;
if (clk2x > 8) and (r2.hclken2 = '1') then v2.reqmsk := "11"; end if;
end if;
end if;
-- reset operation
if rst = '0' then
v.bg := '0'; v.bo := '0'; v.ba := '0'; v.retry := '0'; v.werr := '0'; v.lb := '0';
v.lock := '0'; v.hlocken := '0'; v2.reqmsk := "00";
end if;
-- drive ports
ahbo.haddr <= haddr ;
ahbo.htrans <= htrans;
ahbo.hbusreq <= hbusreq and not r.lb and not (((r.bo and r.ba) or nb) and r.bg and nbo);
ahbo.hwdata <= hwdata;
ahbo.hlock <= hlock;
ahbo.hwrite <= hwrite;
ahbo.hsize <= hsize;
ahbo.hburst <= hburst;
ahbo.hprot <= "11" & su & nbo;
ahbo.hindex <= hindex;
mcio.grant <= igrant;
mcio.ready <= iready;
mcio.mexc <= imexc;
mcio.retry <= iretry;
mcio.cache <= ihcache;
mcdo.grant <= dgrant;
mcdo.ready <= dready;
mcdo.mexc <= dmexc;
mcdo.retry <= dretry;
mcdo.werr <= r.werr;
mcdo.cache <= dhcache;
mcdo.ba <= r.ba;
mcdo.bg <= r.bg;
mcio.scanen <= scanen;
mcdo.scanen <= scanen;
mcdo.testen <= ahbi.testen;
mcdo.par <= (others => '0');
mcio.par <= (others => '0');
rin <= v; r2in <= v2;
end process;
mcio.data <= ahbi.hrdata; mcdo.data <= ahbi.hrdata;
ahbo.hirq <= (others => '0');
ahbo.hconfig <= hconfig;
reg : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
reg2gen : if (clk2x /= 0) generate
reg2 : process(clk)
begin
if rising_edge(clk) then r2 <= r2in; end if;
end process;
end generate;
noreg2gen : if (clk2x = 0) generate
r2.reqmsk <= "00";
end generate;
end;
|
-- wasca.vhd
-- Generated using ACDS version 14.1 186 at 2015.05.28.08:37:08
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_toplevel is
port (
clk_clk : in std_logic := '0'; -- clk.clk
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- .ba
external_sdram_controller_wire_cas_n : out std_logic; -- .cas_n
external_sdram_controller_wire_cke : out std_logic; -- .cke
external_sdram_controller_wire_cs_n : out std_logic; -- .cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- .dqm
external_sdram_controller_wire_ras_n : out std_logic; -- .ras_n
external_sdram_controller_wire_we_n : out std_logic; -- .we_n
external_sdram_controller_wire_clk : out std_logic; -- .clk
reset_reset_n : in std_logic := '0'; -- reset.reset_n
sega_saturn_abus_slave_0_abus_address : in std_logic_vector(25 downto 16) := (others => '0'); -- sega_saturn_abus_slave_0_abus.address
sega_saturn_abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- .data
sega_saturn_abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
sega_saturn_abus_slave_0_abus_read : in std_logic := '0'; -- .read
sega_saturn_abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
sega_saturn_abus_slave_0_abus_waitrequest : out std_logic; -- .waitrequest
sega_saturn_abus_slave_0_abus_interrupt : out std_logic := '0'; -- .interrupt
sega_saturn_abus_slave_0_abus_disableout : out std_logic := '0'; -- .muxing
sega_saturn_abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0) := (others => '0'); -- .muxing
sega_saturn_abus_slave_0_abus_direction : out std_logic := '0'; -- .direction
spi_sd_card_MISO : in std_logic := '0'; -- MISO
spi_sd_card_MOSI : out std_logic; -- MOSI
spi_sd_card_SCLK : out std_logic; -- SCLK
spi_sd_card_SS_n : out std_logic; -- SS_n
audio_out_BCLK : in std_logic := '0'; -- BCLK
audio_out_DACDAT : out std_logic; -- DACDAT
audio_out_DACLRCK : in std_logic := '0'; -- DACLRCK
audio_SSEL : out std_logic := '0'
);
end entity wasca_toplevel;
architecture rtl of wasca_toplevel is
component wasca is
port (
altpll_0_areset_conduit_export : in std_logic := '0'; -- altpll_0_areset_conduit.export
altpll_0_locked_conduit_export : out std_logic; -- altpll_0_locked_conduit.export
altpll_0_phasedone_conduit_export : out std_logic; -- altpll_0_phasedone_conduit.export
clk_clk : in std_logic := '0'; -- clk.clk
clock_116_mhz_clk : out std_logic ; -- cl
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- .ba
external_sdram_controller_wire_cas_n : out std_logic; -- .cas_n
external_sdram_controller_wire_cke : out std_logic; -- .cke
external_sdram_controller_wire_cs_n : out std_logic; -- .cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- .dqm
external_sdram_controller_wire_ras_n : out std_logic; -- .ras_n
external_sdram_controller_wire_we_n : out std_logic; -- .we_n
sega_saturn_abus_slave_0_abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- sega_saturn_abus_slave_0_abus.address
sega_saturn_abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
sega_saturn_abus_slave_0_abus_read : in std_logic := '0'; -- .read
sega_saturn_abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
sega_saturn_abus_slave_0_abus_waitrequest : out std_logic; -- .waitrequest
sega_saturn_abus_slave_0_abus_interrupt : out std_logic := '0'; -- .interrupt
sega_saturn_abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
sega_saturn_abus_slave_0_abus_direction : out std_logic := '0';
sega_saturn_abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0) := (others => '0');
sega_saturn_abus_slave_0_abus_disableout : out std_logic := '0' ; -- .muxing
sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset : in std_logic := '0'; -- saturn_reset
spi_sd_card_MISO : in std_logic := '0'; -- MISO
spi_sd_card_MOSI : out std_logic; -- MOSI
spi_sd_card_SCLK : out std_logic; -- SCLK
spi_sd_card_SS_n : out std_logic; -- SS_n
audio_out_BCLK : in std_logic := '0'; -- BCLK
audio_out_DACDAT : out std_logic; -- DACDAT
audio_out_DACLRCK : in std_logic := '0' -- DACLRCK
);
end component;
--signal altpll_0_areset_conduit_export : std_logic := '0';
signal altpll_0_locked_conduit_export : std_logic := '0';
--signal altpll_0_phasedone_conduit_export : std_logic := '0';
--signal sega_saturn_abus_slave_0_abus_address_demuxed : std_logic_vector(25 downto 0) := (others => '0');
--signal sega_saturn_abus_slave_0_abus_data_demuxed : std_logic_vector(15 downto 0) := (others => '0');
signal clock_116_mhz : std_logic := '0';
begin
--sega_saturn_abus_slave_0_abus_muxing (0) <= not sega_saturn_abus_slave_0_abus_muxing(1);
external_sdram_controller_wire_clk <= clock_116_mhz;
my_little_wasca : component wasca
port map (
clk_clk => clk_clk,
clock_116_mhz_clk => clock_116_mhz,
external_sdram_controller_wire_addr => external_sdram_controller_wire_addr,
external_sdram_controller_wire_ba => external_sdram_controller_wire_ba,
external_sdram_controller_wire_cas_n => external_sdram_controller_wire_cas_n,
external_sdram_controller_wire_cke => external_sdram_controller_wire_cke,
external_sdram_controller_wire_cs_n => external_sdram_controller_wire_cs_n,
external_sdram_controller_wire_dq => external_sdram_controller_wire_dq,
external_sdram_controller_wire_dqm => external_sdram_controller_wire_dqm,
external_sdram_controller_wire_ras_n => external_sdram_controller_wire_ras_n,
external_sdram_controller_wire_we_n => external_sdram_controller_wire_we_n,
sega_saturn_abus_slave_0_abus_address => sega_saturn_abus_slave_0_abus_address,
sega_saturn_abus_slave_0_abus_chipselect => "1"&sega_saturn_abus_slave_0_abus_chipselect(1 downto 0),--work only with CS1 and CS0 for now
sega_saturn_abus_slave_0_abus_read => sega_saturn_abus_slave_0_abus_read,
sega_saturn_abus_slave_0_abus_write => sega_saturn_abus_slave_0_abus_write,
sega_saturn_abus_slave_0_abus_waitrequest => sega_saturn_abus_slave_0_abus_waitrequest,
sega_saturn_abus_slave_0_abus_interrupt => sega_saturn_abus_slave_0_abus_interrupt,
sega_saturn_abus_slave_0_abus_addressdata => sega_saturn_abus_slave_0_abus_addressdata,
sega_saturn_abus_slave_0_abus_direction => sega_saturn_abus_slave_0_abus_direction,
sega_saturn_abus_slave_0_abus_muxing => sega_saturn_abus_slave_0_abus_muxing,
sega_saturn_abus_slave_0_abus_disableout => sega_saturn_abus_slave_0_abus_disableout,
sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset => reset_reset_n,
spi_sd_card_MISO => spi_sd_card_MISO,
spi_sd_card_MOSI => spi_sd_card_MOSI,
spi_sd_card_SCLK => spi_sd_card_SCLK,
spi_sd_card_SS_n => spi_sd_card_SS_n,
altpll_0_areset_conduit_export => open,
altpll_0_locked_conduit_export => altpll_0_locked_conduit_export,
altpll_0_phasedone_conduit_export => open,
audio_out_BCLK => audio_out_BCLK,
audio_out_DACDAT => audio_out_DACDAT,
audio_out_DACLRCK => audio_out_DACLRCK
);
audio_SSEL <= '0';
--sega_saturn_abus_slave_0_abus_waitrequest <= '1';
--sega_saturn_abus_slave_0_abus_direction <= '0';
--sega_saturn_abus_slave_0_abus_muxing <= "01";
end architecture rtl; -- of wasca_toplevel
|
-- wasca.vhd
-- Generated using ACDS version 14.1 186 at 2015.05.28.08:37:08
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity wasca_toplevel is
port (
clk_clk : in std_logic := '0'; -- clk.clk
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- .ba
external_sdram_controller_wire_cas_n : out std_logic; -- .cas_n
external_sdram_controller_wire_cke : out std_logic; -- .cke
external_sdram_controller_wire_cs_n : out std_logic; -- .cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- .dqm
external_sdram_controller_wire_ras_n : out std_logic; -- .ras_n
external_sdram_controller_wire_we_n : out std_logic; -- .we_n
external_sdram_controller_wire_clk : out std_logic; -- .clk
reset_reset_n : in std_logic := '0'; -- reset.reset_n
sega_saturn_abus_slave_0_abus_address : in std_logic_vector(25 downto 16) := (others => '0'); -- sega_saturn_abus_slave_0_abus.address
sega_saturn_abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- .data
sega_saturn_abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
sega_saturn_abus_slave_0_abus_read : in std_logic := '0'; -- .read
sega_saturn_abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
sega_saturn_abus_slave_0_abus_waitrequest : out std_logic; -- .waitrequest
sega_saturn_abus_slave_0_abus_interrupt : out std_logic := '0'; -- .interrupt
sega_saturn_abus_slave_0_abus_disableout : out std_logic := '0'; -- .muxing
sega_saturn_abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0) := (others => '0'); -- .muxing
sega_saturn_abus_slave_0_abus_direction : out std_logic := '0'; -- .direction
spi_sd_card_MISO : in std_logic := '0'; -- MISO
spi_sd_card_MOSI : out std_logic; -- MOSI
spi_sd_card_SCLK : out std_logic; -- SCLK
spi_sd_card_SS_n : out std_logic; -- SS_n
audio_out_BCLK : in std_logic := '0'; -- BCLK
audio_out_DACDAT : out std_logic; -- DACDAT
audio_out_DACLRCK : in std_logic := '0'; -- DACLRCK
audio_SSEL : out std_logic := '0'
);
end entity wasca_toplevel;
architecture rtl of wasca_toplevel is
component wasca is
port (
altpll_0_areset_conduit_export : in std_logic := '0'; -- altpll_0_areset_conduit.export
altpll_0_locked_conduit_export : out std_logic; -- altpll_0_locked_conduit.export
altpll_0_phasedone_conduit_export : out std_logic; -- altpll_0_phasedone_conduit.export
clk_clk : in std_logic := '0'; -- clk.clk
clock_116_mhz_clk : out std_logic ; -- cl
external_sdram_controller_wire_addr : out std_logic_vector(12 downto 0); -- external_sdram_controller_wire.addr
external_sdram_controller_wire_ba : out std_logic_vector(1 downto 0); -- .ba
external_sdram_controller_wire_cas_n : out std_logic; -- .cas_n
external_sdram_controller_wire_cke : out std_logic; -- .cke
external_sdram_controller_wire_cs_n : out std_logic; -- .cs_n
external_sdram_controller_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
external_sdram_controller_wire_dqm : out std_logic_vector(1 downto 0); -- .dqm
external_sdram_controller_wire_ras_n : out std_logic; -- .ras_n
external_sdram_controller_wire_we_n : out std_logic; -- .we_n
sega_saturn_abus_slave_0_abus_address : in std_logic_vector(9 downto 0) := (others => '0'); -- sega_saturn_abus_slave_0_abus.address
sega_saturn_abus_slave_0_abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
sega_saturn_abus_slave_0_abus_read : in std_logic := '0'; -- .read
sega_saturn_abus_slave_0_abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
sega_saturn_abus_slave_0_abus_waitrequest : out std_logic; -- .waitrequest
sega_saturn_abus_slave_0_abus_interrupt : out std_logic := '0'; -- .interrupt
sega_saturn_abus_slave_0_abus_addressdata : inout std_logic_vector(15 downto 0) := (others => '0'); -- .writedata
sega_saturn_abus_slave_0_abus_direction : out std_logic := '0';
sega_saturn_abus_slave_0_abus_muxing : out std_logic_vector(1 downto 0) := (others => '0');
sega_saturn_abus_slave_0_abus_disableout : out std_logic := '0' ; -- .muxing
sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset : in std_logic := '0'; -- saturn_reset
spi_sd_card_MISO : in std_logic := '0'; -- MISO
spi_sd_card_MOSI : out std_logic; -- MOSI
spi_sd_card_SCLK : out std_logic; -- SCLK
spi_sd_card_SS_n : out std_logic; -- SS_n
audio_out_BCLK : in std_logic := '0'; -- BCLK
audio_out_DACDAT : out std_logic; -- DACDAT
audio_out_DACLRCK : in std_logic := '0' -- DACLRCK
);
end component;
--signal altpll_0_areset_conduit_export : std_logic := '0';
signal altpll_0_locked_conduit_export : std_logic := '0';
--signal altpll_0_phasedone_conduit_export : std_logic := '0';
--signal sega_saturn_abus_slave_0_abus_address_demuxed : std_logic_vector(25 downto 0) := (others => '0');
--signal sega_saturn_abus_slave_0_abus_data_demuxed : std_logic_vector(15 downto 0) := (others => '0');
signal clock_116_mhz : std_logic := '0';
begin
--sega_saturn_abus_slave_0_abus_muxing (0) <= not sega_saturn_abus_slave_0_abus_muxing(1);
external_sdram_controller_wire_clk <= clock_116_mhz;
my_little_wasca : component wasca
port map (
clk_clk => clk_clk,
clock_116_mhz_clk => clock_116_mhz,
external_sdram_controller_wire_addr => external_sdram_controller_wire_addr,
external_sdram_controller_wire_ba => external_sdram_controller_wire_ba,
external_sdram_controller_wire_cas_n => external_sdram_controller_wire_cas_n,
external_sdram_controller_wire_cke => external_sdram_controller_wire_cke,
external_sdram_controller_wire_cs_n => external_sdram_controller_wire_cs_n,
external_sdram_controller_wire_dq => external_sdram_controller_wire_dq,
external_sdram_controller_wire_dqm => external_sdram_controller_wire_dqm,
external_sdram_controller_wire_ras_n => external_sdram_controller_wire_ras_n,
external_sdram_controller_wire_we_n => external_sdram_controller_wire_we_n,
sega_saturn_abus_slave_0_abus_address => sega_saturn_abus_slave_0_abus_address,
sega_saturn_abus_slave_0_abus_chipselect => "1"&sega_saturn_abus_slave_0_abus_chipselect(1 downto 0),--work only with CS1 and CS0 for now
sega_saturn_abus_slave_0_abus_read => sega_saturn_abus_slave_0_abus_read,
sega_saturn_abus_slave_0_abus_write => sega_saturn_abus_slave_0_abus_write,
sega_saturn_abus_slave_0_abus_waitrequest => sega_saturn_abus_slave_0_abus_waitrequest,
sega_saturn_abus_slave_0_abus_interrupt => sega_saturn_abus_slave_0_abus_interrupt,
sega_saturn_abus_slave_0_abus_addressdata => sega_saturn_abus_slave_0_abus_addressdata,
sega_saturn_abus_slave_0_abus_direction => sega_saturn_abus_slave_0_abus_direction,
sega_saturn_abus_slave_0_abus_muxing => sega_saturn_abus_slave_0_abus_muxing,
sega_saturn_abus_slave_0_abus_disableout => sega_saturn_abus_slave_0_abus_disableout,
sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset => reset_reset_n,
spi_sd_card_MISO => spi_sd_card_MISO,
spi_sd_card_MOSI => spi_sd_card_MOSI,
spi_sd_card_SCLK => spi_sd_card_SCLK,
spi_sd_card_SS_n => spi_sd_card_SS_n,
altpll_0_areset_conduit_export => open,
altpll_0_locked_conduit_export => altpll_0_locked_conduit_export,
altpll_0_phasedone_conduit_export => open,
audio_out_BCLK => audio_out_BCLK,
audio_out_DACDAT => audio_out_DACDAT,
audio_out_DACLRCK => audio_out_DACLRCK
);
audio_SSEL <= '0';
--sega_saturn_abus_slave_0_abus_waitrequest <= '1';
--sega_saturn_abus_slave_0_abus_direction <= '0';
--sega_saturn_abus_slave_0_abus_muxing <= "01";
end architecture rtl; -- of wasca_toplevel
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_AXIvideo2Mat is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
INPUT_STREAM_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
INPUT_STREAM_TVALID : IN STD_LOGIC;
INPUT_STREAM_TREADY : OUT STD_LOGIC;
INPUT_STREAM_TKEEP : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TID : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
img_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_full_n : IN STD_LOGIC;
img_data_stream_0_V_write : OUT STD_LOGIC;
img_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_full_n : IN STD_LOGIC;
img_data_stream_1_V_write : OUT STD_LOGIC;
img_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_full_n : IN STD_LOGIC;
img_data_stream_2_V_write : OUT STD_LOGIC );
end;
architecture behav of image_filter_AXIvideo2Mat is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (6 downto 0) := "0000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (6 downto 0) := "0000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (6 downto 0) := "0001000";
constant ap_ST_pp1_stg0_fsm_4 : STD_LOGIC_VECTOR (6 downto 0) := "0010000";
constant ap_ST_st7_fsm_5 : STD_LOGIC_VECTOR (6 downto 0) := "0100000";
constant ap_ST_st8_fsm_6 : STD_LOGIC_VECTOR (6 downto 0) := "1000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv12_0 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
constant ap_const_lv12_1 : STD_LOGIC_VECTOR (11 downto 0) := "000000000001";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_true : BOOLEAN := true;
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_26 : BOOLEAN;
signal eol_1_reg_184 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_data_V_1_reg_195 : STD_LOGIC_VECTOR (31 downto 0);
signal p_1_reg_206 : STD_LOGIC_VECTOR (11 downto 0);
signal eol_reg_217 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_last_V_2_reg_229 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_s_reg_241 : STD_LOGIC_VECTOR (31 downto 0);
signal eol_2_reg_253 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_75 : BOOLEAN;
signal tmp_data_V_reg_402 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_87 : BOOLEAN;
signal tmp_last_V_reg_410 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond1_fu_319_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_101 : BOOLEAN;
signal i_V_fu_324_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal i_V_reg_426 : STD_LOGIC_VECTOR (11 downto 0);
signal exitcond2_fu_330_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond2_reg_431 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_pp1_stg0_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_112 : BOOLEAN;
signal brmerge_fu_344_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_120 : BOOLEAN;
signal ap_reg_ppiten_pp1_it0 : STD_LOGIC := '0';
signal ap_sig_bdd_133 : BOOLEAN;
signal ap_reg_ppiten_pp1_it1 : STD_LOGIC := '0';
signal j_V_fu_335_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_34_fu_363_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_34_reg_444 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_6_reg_449 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_7_reg_454 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st7_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_158 : BOOLEAN;
signal ap_sig_bdd_163 : BOOLEAN;
signal axi_last_V_3_reg_264 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_last_V1_reg_153 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st8_fsm_6 : STD_LOGIC;
signal ap_sig_bdd_181 : BOOLEAN;
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_188 : BOOLEAN;
signal axi_data_V_3_reg_276 : STD_LOGIC_VECTOR (31 downto 0);
signal axi_data_V1_reg_163 : STD_LOGIC_VECTOR (31 downto 0);
signal p_s_reg_173 : STD_LOGIC_VECTOR (11 downto 0);
signal eol_1_phi_fu_187_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_data_V_1_phi_fu_198_p4 : STD_LOGIC_VECTOR (31 downto 0);
signal eol_phi_fu_221_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_phiprechg_axi_last_V_2_reg_229pp1_it0 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0 : STD_LOGIC_VECTOR (31 downto 0);
signal p_Val2_s_phi_fu_245_p4 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_phiprechg_eol_2_reg_253pp1_it0 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_last_V_1_mux_fu_356_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal eol_3_reg_288 : STD_LOGIC_VECTOR (0 downto 0);
signal sof_1_fu_98 : STD_LOGIC_VECTOR (0 downto 0);
signal not_sof_2_fu_350_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_user_V_fu_310_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (6 downto 0);
signal ap_sig_bdd_119 : BOOLEAN;
signal ap_sig_bdd_211 : BOOLEAN;
signal ap_sig_bdd_144 : BOOLEAN;
signal ap_sig_bdd_229 : BOOLEAN;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_done_reg assign process. --
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((exitcond1_fu_319_p2 = ap_const_lv1_0)))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp1_it0 assign process. --
ap_reg_ppiten_pp1_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0)))) then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (exitcond1_fu_319_p2 = ap_const_lv1_0))) then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp1_it1 assign process. --
ap_reg_ppiten_pp1_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_1;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (exitcond1_fu_319_p2 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0))))) then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- axi_data_V1_reg_163 assign process. --
axi_data_V1_reg_163_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
axi_data_V1_reg_163 <= tmp_data_V_reg_402;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_6)) then
axi_data_V1_reg_163 <= axi_data_V_3_reg_276;
end if;
end if;
end process;
-- axi_data_V_1_reg_195 assign process. --
axi_data_V_1_reg_195_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
axi_data_V_1_reg_195 <= p_Val2_s_reg_241;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (exitcond1_fu_319_p2 = ap_const_lv1_0))) then
axi_data_V_1_reg_195 <= axi_data_V1_reg_163;
end if;
end if;
end process;
-- axi_data_V_3_reg_276 assign process. --
axi_data_V_3_reg_276_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0)))) then
axi_data_V_3_reg_276 <= axi_data_V_1_phi_fu_198_p4;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_5) and (ap_const_lv1_0 = eol_3_reg_288) and not(ap_sig_bdd_163))) then
axi_data_V_3_reg_276 <= INPUT_STREAM_TDATA;
end if;
end if;
end process;
-- axi_last_V1_reg_153 assign process. --
axi_last_V1_reg_153_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
axi_last_V1_reg_153 <= tmp_last_V_reg_410;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_6)) then
axi_last_V1_reg_153 <= axi_last_V_3_reg_264;
end if;
end if;
end process;
-- axi_last_V_2_reg_229 assign process. --
axi_last_V_2_reg_229_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_144) then
if (ap_sig_bdd_211) then
axi_last_V_2_reg_229 <= eol_1_phi_fu_187_p4;
elsif (ap_sig_bdd_119) then
axi_last_V_2_reg_229 <= INPUT_STREAM_TLAST;
elsif ((ap_true = ap_true)) then
axi_last_V_2_reg_229 <= ap_reg_phiprechg_axi_last_V_2_reg_229pp1_it0;
end if;
end if;
end if;
end process;
-- axi_last_V_3_reg_264 assign process. --
axi_last_V_3_reg_264_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0)))) then
axi_last_V_3_reg_264 <= eol_1_phi_fu_187_p4;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_5) and (ap_const_lv1_0 = eol_3_reg_288) and not(ap_sig_bdd_163))) then
axi_last_V_3_reg_264 <= INPUT_STREAM_TLAST;
end if;
end if;
end process;
-- eol_1_reg_184 assign process. --
eol_1_reg_184_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
eol_1_reg_184 <= axi_last_V_2_reg_229;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (exitcond1_fu_319_p2 = ap_const_lv1_0))) then
eol_1_reg_184 <= axi_last_V1_reg_153;
end if;
end if;
end process;
-- eol_2_reg_253 assign process. --
eol_2_reg_253_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_144) then
if (ap_sig_bdd_211) then
eol_2_reg_253 <= axi_last_V_1_mux_fu_356_p2;
elsif (ap_sig_bdd_119) then
eol_2_reg_253 <= INPUT_STREAM_TLAST;
elsif ((ap_true = ap_true)) then
eol_2_reg_253 <= ap_reg_phiprechg_eol_2_reg_253pp1_it0;
end if;
end if;
end if;
end process;
-- eol_3_reg_288 assign process. --
eol_3_reg_288_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0)))) then
eol_3_reg_288 <= eol_phi_fu_221_p4;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_5) and (ap_const_lv1_0 = eol_3_reg_288) and not(ap_sig_bdd_163))) then
eol_3_reg_288 <= INPUT_STREAM_TLAST;
end if;
end if;
end process;
-- eol_reg_217 assign process. --
eol_reg_217_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
eol_reg_217 <= eol_2_reg_253;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (exitcond1_fu_319_p2 = ap_const_lv1_0))) then
eol_reg_217 <= ap_const_lv1_0;
end if;
end if;
end process;
-- p_1_reg_206 assign process. --
p_1_reg_206_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
p_1_reg_206 <= j_V_fu_335_p2;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (exitcond1_fu_319_p2 = ap_const_lv1_0))) then
p_1_reg_206 <= ap_const_lv12_0;
end if;
end if;
end process;
-- p_Val2_s_reg_241 assign process. --
p_Val2_s_reg_241_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_144) then
if (ap_sig_bdd_211) then
p_Val2_s_reg_241 <= axi_data_V_1_phi_fu_198_p4;
elsif (ap_sig_bdd_119) then
p_Val2_s_reg_241 <= INPUT_STREAM_TDATA;
elsif ((ap_true = ap_true)) then
p_Val2_s_reg_241 <= ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0;
end if;
end if;
end if;
end process;
-- p_s_reg_173 assign process. --
p_s_reg_173_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
p_s_reg_173 <= ap_const_lv12_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_6)) then
p_s_reg_173 <= i_V_reg_426;
end if;
end if;
end process;
-- sof_1_fu_98 assign process. --
sof_1_fu_98_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
sof_1_fu_98 <= ap_const_lv1_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
sof_1_fu_98 <= ap_const_lv1_1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
exitcond2_reg_431 <= exitcond2_fu_330_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
i_V_reg_426 <= i_V_fu_324_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
tmp_34_reg_444 <= tmp_34_fu_363_p1;
tmp_6_reg_449 <= p_Val2_s_phi_fu_245_p4(15 downto 8);
tmp_7_reg_454 <= p_Val2_s_phi_fu_245_p4(23 downto 16);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((INPUT_STREAM_TVALID = ap_const_logic_0)))) then
tmp_data_V_reg_402 <= INPUT_STREAM_TDATA;
tmp_last_V_reg_410 <= INPUT_STREAM_TLAST;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, INPUT_STREAM_TVALID, ap_sig_bdd_75, exitcond1_fu_319_p2, exitcond2_fu_330_p2, ap_sig_bdd_120, ap_reg_ppiten_pp1_it0, ap_sig_bdd_133, ap_reg_ppiten_pp1_it1, ap_sig_bdd_163, eol_3_reg_288, tmp_user_V_fu_310_p1)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not(ap_sig_bdd_75)) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if ((not((INPUT_STREAM_TVALID = ap_const_logic_0)) and (ap_const_lv1_0 = tmp_user_V_fu_310_p1))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif ((not((INPUT_STREAM_TVALID = ap_const_logic_0)) and not((ap_const_lv1_0 = tmp_user_V_fu_310_p1)))) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
if (not((exitcond1_fu_319_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_4;
end if;
when ap_ST_pp1_stg0_fsm_4 =>
if (not(((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0))))) then
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_4;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0)))) then
ap_NS_fsm <= ap_ST_st7_fsm_5;
else
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_4;
end if;
when ap_ST_st7_fsm_5 =>
if (((ap_const_lv1_0 = eol_3_reg_288) and not(ap_sig_bdd_163))) then
ap_NS_fsm <= ap_ST_st7_fsm_5;
elsif ((not(ap_sig_bdd_163) and not((ap_const_lv1_0 = eol_3_reg_288)))) then
ap_NS_fsm <= ap_ST_st8_fsm_6;
else
ap_NS_fsm <= ap_ST_st7_fsm_5;
end if;
when ap_ST_st8_fsm_6 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when others =>
ap_NS_fsm <= "XXXXXXX";
end case;
end process;
-- INPUT_STREAM_TREADY assign process. --
INPUT_STREAM_TREADY_assign_proc : process(INPUT_STREAM_TVALID, ap_sig_cseq_ST_st2_fsm_1, exitcond2_fu_330_p2, ap_sig_cseq_ST_pp1_stg0_fsm_4, brmerge_fu_344_p2, ap_sig_bdd_120, ap_reg_ppiten_pp1_it0, ap_sig_bdd_133, ap_reg_ppiten_pp1_it1, ap_sig_cseq_ST_st7_fsm_5, ap_sig_bdd_163, eol_3_reg_288)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((INPUT_STREAM_TVALID = ap_const_logic_0))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_5) and (ap_const_lv1_0 = eol_3_reg_288) and not(ap_sig_bdd_163)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = brmerge_fu_344_p2) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1))))))) then
INPUT_STREAM_TREADY <= ap_const_logic_1;
else
INPUT_STREAM_TREADY <= ap_const_logic_0;
end if;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_done_reg, exitcond1_fu_319_p2, ap_sig_cseq_ST_st4_fsm_3)
begin
if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((exitcond1_fu_319_p2 = ap_const_lv1_0))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(exitcond1_fu_319_p2, ap_sig_cseq_ST_st4_fsm_3)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((exitcond1_fu_319_p2 = ap_const_lv1_0)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_phiprechg_axi_last_V_2_reg_229pp1_it0 <= "X";
ap_reg_phiprechg_eol_2_reg_253pp1_it0 <= "X";
ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
-- ap_sig_bdd_101 assign process. --
ap_sig_bdd_101_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_101 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_112 assign process. --
ap_sig_bdd_112_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_112 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_119 assign process. --
ap_sig_bdd_119_assign_proc : process(exitcond2_fu_330_p2, brmerge_fu_344_p2)
begin
ap_sig_bdd_119 <= ((exitcond2_fu_330_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = brmerge_fu_344_p2));
end process;
-- ap_sig_bdd_120 assign process. --
ap_sig_bdd_120_assign_proc : process(INPUT_STREAM_TVALID, exitcond2_fu_330_p2, brmerge_fu_344_p2)
begin
ap_sig_bdd_120 <= ((INPUT_STREAM_TVALID = ap_const_logic_0) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = brmerge_fu_344_p2));
end process;
-- ap_sig_bdd_133 assign process. --
ap_sig_bdd_133_assign_proc : process(img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, exitcond2_reg_431)
begin
ap_sig_bdd_133 <= (((img_data_stream_0_V_full_n = ap_const_logic_0) and (exitcond2_reg_431 = ap_const_lv1_0)) or ((exitcond2_reg_431 = ap_const_lv1_0) and (img_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond2_reg_431 = ap_const_lv1_0) and (img_data_stream_2_V_full_n = ap_const_logic_0)));
end process;
-- ap_sig_bdd_144 assign process. --
ap_sig_bdd_144_assign_proc : process(ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_sig_bdd_120, ap_reg_ppiten_pp1_it0, ap_sig_bdd_133, ap_reg_ppiten_pp1_it1)
begin
ap_sig_bdd_144 <= ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))));
end process;
-- ap_sig_bdd_158 assign process. --
ap_sig_bdd_158_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_158 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_bdd_163 assign process. --
ap_sig_bdd_163_assign_proc : process(INPUT_STREAM_TVALID, eol_3_reg_288)
begin
ap_sig_bdd_163 <= ((INPUT_STREAM_TVALID = ap_const_logic_0) and (ap_const_lv1_0 = eol_3_reg_288));
end process;
-- ap_sig_bdd_181 assign process. --
ap_sig_bdd_181_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_181 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
-- ap_sig_bdd_188 assign process. --
ap_sig_bdd_188_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_188 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_211 assign process. --
ap_sig_bdd_211_assign_proc : process(exitcond2_fu_330_p2, brmerge_fu_344_p2)
begin
ap_sig_bdd_211 <= ((exitcond2_fu_330_p2 = ap_const_lv1_0) and not((ap_const_lv1_0 = brmerge_fu_344_p2)));
end process;
-- ap_sig_bdd_229 assign process. --
ap_sig_bdd_229_assign_proc : process(exitcond2_fu_330_p2, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_reg_ppiten_pp1_it0)
begin
ap_sig_bdd_229 <= ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0));
end process;
-- ap_sig_bdd_26 assign process. --
ap_sig_bdd_26_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_26 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_75 assign process. --
ap_sig_bdd_75_assign_proc : process(ap_start, ap_done_reg)
begin
ap_sig_bdd_75 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
-- ap_sig_bdd_87 assign process. --
ap_sig_bdd_87_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_87 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_cseq_ST_pp1_stg0_fsm_4 assign process. --
ap_sig_cseq_ST_pp1_stg0_fsm_4_assign_proc : process(ap_sig_bdd_112)
begin
if (ap_sig_bdd_112) then
ap_sig_cseq_ST_pp1_stg0_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp1_stg0_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_26)
begin
if (ap_sig_bdd_26) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_87)
begin
if (ap_sig_bdd_87) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_188)
begin
if (ap_sig_bdd_188) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_101)
begin
if (ap_sig_bdd_101) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st7_fsm_5 assign process. --
ap_sig_cseq_ST_st7_fsm_5_assign_proc : process(ap_sig_bdd_158)
begin
if (ap_sig_bdd_158) then
ap_sig_cseq_ST_st7_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st8_fsm_6 assign process. --
ap_sig_cseq_ST_st8_fsm_6_assign_proc : process(ap_sig_bdd_181)
begin
if (ap_sig_bdd_181) then
ap_sig_cseq_ST_st8_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_6 <= ap_const_logic_0;
end if;
end process;
-- axi_data_V_1_phi_fu_198_p4 assign process. --
axi_data_V_1_phi_fu_198_p4_assign_proc : process(axi_data_V_1_reg_195, p_Val2_s_reg_241, exitcond2_reg_431, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1))) then
axi_data_V_1_phi_fu_198_p4 <= p_Val2_s_reg_241;
else
axi_data_V_1_phi_fu_198_p4 <= axi_data_V_1_reg_195;
end if;
end process;
axi_last_V_1_mux_fu_356_p2 <= (eol_1_phi_fu_187_p4 or not_sof_2_fu_350_p2);
brmerge_fu_344_p2 <= (sof_1_fu_98 or eol_phi_fu_221_p4);
-- eol_1_phi_fu_187_p4 assign process. --
eol_1_phi_fu_187_p4_assign_proc : process(eol_1_reg_184, axi_last_V_2_reg_229, exitcond2_reg_431, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1))) then
eol_1_phi_fu_187_p4 <= axi_last_V_2_reg_229;
else
eol_1_phi_fu_187_p4 <= eol_1_reg_184;
end if;
end process;
-- eol_phi_fu_221_p4 assign process. --
eol_phi_fu_221_p4_assign_proc : process(eol_reg_217, eol_2_reg_253, exitcond2_reg_431, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1))) then
eol_phi_fu_221_p4 <= eol_2_reg_253;
else
eol_phi_fu_221_p4 <= eol_reg_217;
end if;
end process;
exitcond1_fu_319_p2 <= "1" when (p_s_reg_173 = img_rows_V_read) else "0";
exitcond2_fu_330_p2 <= "1" when (p_1_reg_206 = img_cols_V_read) else "0";
i_V_fu_324_p2 <= std_logic_vector(unsigned(p_s_reg_173) + unsigned(ap_const_lv12_1));
img_data_stream_0_V_din <= tmp_34_reg_444;
-- img_data_stream_0_V_write assign process. --
img_data_stream_0_V_write_assign_proc : process(exitcond2_reg_431, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_sig_bdd_120, ap_reg_ppiten_pp1_it0, ap_sig_bdd_133, ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
img_data_stream_0_V_write <= ap_const_logic_1;
else
img_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
img_data_stream_1_V_din <= tmp_6_reg_449;
-- img_data_stream_1_V_write assign process. --
img_data_stream_1_V_write_assign_proc : process(exitcond2_reg_431, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_sig_bdd_120, ap_reg_ppiten_pp1_it0, ap_sig_bdd_133, ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
img_data_stream_1_V_write <= ap_const_logic_1;
else
img_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
img_data_stream_2_V_din <= tmp_7_reg_454;
-- img_data_stream_2_V_write assign process. --
img_data_stream_2_V_write_assign_proc : process(exitcond2_reg_431, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_sig_bdd_120, ap_reg_ppiten_pp1_it0, ap_sig_bdd_133, ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
img_data_stream_2_V_write <= ap_const_logic_1;
else
img_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
j_V_fu_335_p2 <= std_logic_vector(unsigned(p_1_reg_206) + unsigned(ap_const_lv12_1));
not_sof_2_fu_350_p2 <= (sof_1_fu_98 xor ap_const_lv1_1);
-- p_Val2_s_phi_fu_245_p4 assign process. --
p_Val2_s_phi_fu_245_p4_assign_proc : process(INPUT_STREAM_TDATA, brmerge_fu_344_p2, axi_data_V_1_phi_fu_198_p4, ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0, ap_sig_bdd_229)
begin
if (ap_sig_bdd_229) then
if (not((ap_const_lv1_0 = brmerge_fu_344_p2))) then
p_Val2_s_phi_fu_245_p4 <= axi_data_V_1_phi_fu_198_p4;
elsif ((ap_const_lv1_0 = brmerge_fu_344_p2)) then
p_Val2_s_phi_fu_245_p4 <= INPUT_STREAM_TDATA;
else
p_Val2_s_phi_fu_245_p4 <= ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0;
end if;
else
p_Val2_s_phi_fu_245_p4 <= ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0;
end if;
end process;
tmp_34_fu_363_p1 <= p_Val2_s_phi_fu_245_p4(8 - 1 downto 0);
tmp_user_V_fu_310_p1 <= INPUT_STREAM_TUSER;
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity image_filter_AXIvideo2Mat is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
INPUT_STREAM_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
INPUT_STREAM_TVALID : IN STD_LOGIC;
INPUT_STREAM_TREADY : OUT STD_LOGIC;
INPUT_STREAM_TKEEP : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TSTRB : IN STD_LOGIC_VECTOR (3 downto 0);
INPUT_STREAM_TUSER : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TLAST : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TID : IN STD_LOGIC_VECTOR (0 downto 0);
INPUT_STREAM_TDEST : IN STD_LOGIC_VECTOR (0 downto 0);
img_rows_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_cols_V_read : IN STD_LOGIC_VECTOR (11 downto 0);
img_data_stream_0_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_0_V_full_n : IN STD_LOGIC;
img_data_stream_0_V_write : OUT STD_LOGIC;
img_data_stream_1_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_1_V_full_n : IN STD_LOGIC;
img_data_stream_1_V_write : OUT STD_LOGIC;
img_data_stream_2_V_din : OUT STD_LOGIC_VECTOR (7 downto 0);
img_data_stream_2_V_full_n : IN STD_LOGIC;
img_data_stream_2_V_write : OUT STD_LOGIC );
end;
architecture behav of image_filter_AXIvideo2Mat is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (6 downto 0) := "0000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (6 downto 0) := "0000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (6 downto 0) := "0001000";
constant ap_ST_pp1_stg0_fsm_4 : STD_LOGIC_VECTOR (6 downto 0) := "0010000";
constant ap_ST_st7_fsm_5 : STD_LOGIC_VECTOR (6 downto 0) := "0100000";
constant ap_ST_st8_fsm_6 : STD_LOGIC_VECTOR (6 downto 0) := "1000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv12_0 : STD_LOGIC_VECTOR (11 downto 0) := "000000000000";
constant ap_const_lv12_1 : STD_LOGIC_VECTOR (11 downto 0) := "000000000001";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_true : BOOLEAN := true;
signal ap_done_reg : STD_LOGIC := '0';
signal ap_CS_fsm : STD_LOGIC_VECTOR (6 downto 0) := "0000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_26 : BOOLEAN;
signal eol_1_reg_184 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_data_V_1_reg_195 : STD_LOGIC_VECTOR (31 downto 0);
signal p_1_reg_206 : STD_LOGIC_VECTOR (11 downto 0);
signal eol_reg_217 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_last_V_2_reg_229 : STD_LOGIC_VECTOR (0 downto 0);
signal p_Val2_s_reg_241 : STD_LOGIC_VECTOR (31 downto 0);
signal eol_2_reg_253 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_75 : BOOLEAN;
signal tmp_data_V_reg_402 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_87 : BOOLEAN;
signal tmp_last_V_reg_410 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond1_fu_319_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_101 : BOOLEAN;
signal i_V_fu_324_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal i_V_reg_426 : STD_LOGIC_VECTOR (11 downto 0);
signal exitcond2_fu_330_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond2_reg_431 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_pp1_stg0_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_112 : BOOLEAN;
signal brmerge_fu_344_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_bdd_120 : BOOLEAN;
signal ap_reg_ppiten_pp1_it0 : STD_LOGIC := '0';
signal ap_sig_bdd_133 : BOOLEAN;
signal ap_reg_ppiten_pp1_it1 : STD_LOGIC := '0';
signal j_V_fu_335_p2 : STD_LOGIC_VECTOR (11 downto 0);
signal tmp_34_fu_363_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_34_reg_444 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_6_reg_449 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_7_reg_454 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_sig_cseq_ST_st7_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_158 : BOOLEAN;
signal ap_sig_bdd_163 : BOOLEAN;
signal axi_last_V_3_reg_264 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_last_V1_reg_153 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st8_fsm_6 : STD_LOGIC;
signal ap_sig_bdd_181 : BOOLEAN;
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_188 : BOOLEAN;
signal axi_data_V_3_reg_276 : STD_LOGIC_VECTOR (31 downto 0);
signal axi_data_V1_reg_163 : STD_LOGIC_VECTOR (31 downto 0);
signal p_s_reg_173 : STD_LOGIC_VECTOR (11 downto 0);
signal eol_1_phi_fu_187_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_data_V_1_phi_fu_198_p4 : STD_LOGIC_VECTOR (31 downto 0);
signal eol_phi_fu_221_p4 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_phiprechg_axi_last_V_2_reg_229pp1_it0 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0 : STD_LOGIC_VECTOR (31 downto 0);
signal p_Val2_s_phi_fu_245_p4 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_phiprechg_eol_2_reg_253pp1_it0 : STD_LOGIC_VECTOR (0 downto 0);
signal axi_last_V_1_mux_fu_356_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal eol_3_reg_288 : STD_LOGIC_VECTOR (0 downto 0);
signal sof_1_fu_98 : STD_LOGIC_VECTOR (0 downto 0);
signal not_sof_2_fu_350_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_user_V_fu_310_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (6 downto 0);
signal ap_sig_bdd_119 : BOOLEAN;
signal ap_sig_bdd_211 : BOOLEAN;
signal ap_sig_bdd_144 : BOOLEAN;
signal ap_sig_bdd_229 : BOOLEAN;
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_done_reg assign process. --
ap_done_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_done_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_continue)) then
ap_done_reg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((exitcond1_fu_319_p2 = ap_const_lv1_0)))) then
ap_done_reg <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp1_it0 assign process. --
ap_reg_ppiten_pp1_it0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0)))) then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (exitcond1_fu_319_p2 = ap_const_lv1_0))) then
ap_reg_ppiten_pp1_it0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp1_it1 assign process. --
ap_reg_ppiten_pp1_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_1;
elsif ((((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (exitcond1_fu_319_p2 = ap_const_lv1_0)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0))))) then
ap_reg_ppiten_pp1_it1 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- axi_data_V1_reg_163 assign process. --
axi_data_V1_reg_163_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
axi_data_V1_reg_163 <= tmp_data_V_reg_402;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_6)) then
axi_data_V1_reg_163 <= axi_data_V_3_reg_276;
end if;
end if;
end process;
-- axi_data_V_1_reg_195 assign process. --
axi_data_V_1_reg_195_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
axi_data_V_1_reg_195 <= p_Val2_s_reg_241;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (exitcond1_fu_319_p2 = ap_const_lv1_0))) then
axi_data_V_1_reg_195 <= axi_data_V1_reg_163;
end if;
end if;
end process;
-- axi_data_V_3_reg_276 assign process. --
axi_data_V_3_reg_276_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0)))) then
axi_data_V_3_reg_276 <= axi_data_V_1_phi_fu_198_p4;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_5) and (ap_const_lv1_0 = eol_3_reg_288) and not(ap_sig_bdd_163))) then
axi_data_V_3_reg_276 <= INPUT_STREAM_TDATA;
end if;
end if;
end process;
-- axi_last_V1_reg_153 assign process. --
axi_last_V1_reg_153_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
axi_last_V1_reg_153 <= tmp_last_V_reg_410;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_6)) then
axi_last_V1_reg_153 <= axi_last_V_3_reg_264;
end if;
end if;
end process;
-- axi_last_V_2_reg_229 assign process. --
axi_last_V_2_reg_229_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_144) then
if (ap_sig_bdd_211) then
axi_last_V_2_reg_229 <= eol_1_phi_fu_187_p4;
elsif (ap_sig_bdd_119) then
axi_last_V_2_reg_229 <= INPUT_STREAM_TLAST;
elsif ((ap_true = ap_true)) then
axi_last_V_2_reg_229 <= ap_reg_phiprechg_axi_last_V_2_reg_229pp1_it0;
end if;
end if;
end if;
end process;
-- axi_last_V_3_reg_264 assign process. --
axi_last_V_3_reg_264_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0)))) then
axi_last_V_3_reg_264 <= eol_1_phi_fu_187_p4;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_5) and (ap_const_lv1_0 = eol_3_reg_288) and not(ap_sig_bdd_163))) then
axi_last_V_3_reg_264 <= INPUT_STREAM_TLAST;
end if;
end if;
end process;
-- eol_1_reg_184 assign process. --
eol_1_reg_184_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
eol_1_reg_184 <= axi_last_V_2_reg_229;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (exitcond1_fu_319_p2 = ap_const_lv1_0))) then
eol_1_reg_184 <= axi_last_V1_reg_153;
end if;
end if;
end process;
-- eol_2_reg_253 assign process. --
eol_2_reg_253_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_144) then
if (ap_sig_bdd_211) then
eol_2_reg_253 <= axi_last_V_1_mux_fu_356_p2;
elsif (ap_sig_bdd_119) then
eol_2_reg_253 <= INPUT_STREAM_TLAST;
elsif ((ap_true = ap_true)) then
eol_2_reg_253 <= ap_reg_phiprechg_eol_2_reg_253pp1_it0;
end if;
end if;
end if;
end process;
-- eol_3_reg_288 assign process. --
eol_3_reg_288_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0)))) then
eol_3_reg_288 <= eol_phi_fu_221_p4;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_5) and (ap_const_lv1_0 = eol_3_reg_288) and not(ap_sig_bdd_163))) then
eol_3_reg_288 <= INPUT_STREAM_TLAST;
end if;
end if;
end process;
-- eol_reg_217 assign process. --
eol_reg_217_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
eol_reg_217 <= eol_2_reg_253;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (exitcond1_fu_319_p2 = ap_const_lv1_0))) then
eol_reg_217 <= ap_const_lv1_0;
end if;
end if;
end process;
-- p_1_reg_206 assign process. --
p_1_reg_206_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
p_1_reg_206 <= j_V_fu_335_p2;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and (exitcond1_fu_319_p2 = ap_const_lv1_0))) then
p_1_reg_206 <= ap_const_lv12_0;
end if;
end if;
end process;
-- p_Val2_s_reg_241 assign process. --
p_Val2_s_reg_241_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_sig_bdd_144) then
if (ap_sig_bdd_211) then
p_Val2_s_reg_241 <= axi_data_V_1_phi_fu_198_p4;
elsif (ap_sig_bdd_119) then
p_Val2_s_reg_241 <= INPUT_STREAM_TDATA;
elsif ((ap_true = ap_true)) then
p_Val2_s_reg_241 <= ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0;
end if;
end if;
end if;
end process;
-- p_s_reg_173 assign process. --
p_s_reg_173_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
p_s_reg_173 <= ap_const_lv12_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_6)) then
p_s_reg_173 <= i_V_reg_426;
end if;
end if;
end process;
-- sof_1_fu_98 assign process. --
sof_1_fu_98_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
sof_1_fu_98 <= ap_const_lv1_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
sof_1_fu_98 <= ap_const_lv1_1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
exitcond2_reg_431 <= exitcond2_fu_330_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
i_V_reg_426 <= i_V_fu_324_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
tmp_34_reg_444 <= tmp_34_fu_363_p1;
tmp_6_reg_449 <= p_Val2_s_phi_fu_245_p4(15 downto 8);
tmp_7_reg_454 <= p_Val2_s_phi_fu_245_p4(23 downto 16);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((INPUT_STREAM_TVALID = ap_const_logic_0)))) then
tmp_data_V_reg_402 <= INPUT_STREAM_TDATA;
tmp_last_V_reg_410 <= INPUT_STREAM_TLAST;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_CS_fsm, INPUT_STREAM_TVALID, ap_sig_bdd_75, exitcond1_fu_319_p2, exitcond2_fu_330_p2, ap_sig_bdd_120, ap_reg_ppiten_pp1_it0, ap_sig_bdd_133, ap_reg_ppiten_pp1_it1, ap_sig_bdd_163, eol_3_reg_288, tmp_user_V_fu_310_p1)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not(ap_sig_bdd_75)) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if ((not((INPUT_STREAM_TVALID = ap_const_logic_0)) and (ap_const_lv1_0 = tmp_user_V_fu_310_p1))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif ((not((INPUT_STREAM_TVALID = ap_const_logic_0)) and not((ap_const_lv1_0 = tmp_user_V_fu_310_p1)))) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
if (not((exitcond1_fu_319_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_4;
end if;
when ap_ST_pp1_stg0_fsm_4 =>
if (not(((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0))))) then
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_4;
elsif (((ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))) and not((exitcond2_fu_330_p2 = ap_const_lv1_0)))) then
ap_NS_fsm <= ap_ST_st7_fsm_5;
else
ap_NS_fsm <= ap_ST_pp1_stg0_fsm_4;
end if;
when ap_ST_st7_fsm_5 =>
if (((ap_const_lv1_0 = eol_3_reg_288) and not(ap_sig_bdd_163))) then
ap_NS_fsm <= ap_ST_st7_fsm_5;
elsif ((not(ap_sig_bdd_163) and not((ap_const_lv1_0 = eol_3_reg_288)))) then
ap_NS_fsm <= ap_ST_st8_fsm_6;
else
ap_NS_fsm <= ap_ST_st7_fsm_5;
end if;
when ap_ST_st8_fsm_6 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when others =>
ap_NS_fsm <= "XXXXXXX";
end case;
end process;
-- INPUT_STREAM_TREADY assign process. --
INPUT_STREAM_TREADY_assign_proc : process(INPUT_STREAM_TVALID, ap_sig_cseq_ST_st2_fsm_1, exitcond2_fu_330_p2, ap_sig_cseq_ST_pp1_stg0_fsm_4, brmerge_fu_344_p2, ap_sig_bdd_120, ap_reg_ppiten_pp1_it0, ap_sig_bdd_133, ap_reg_ppiten_pp1_it1, ap_sig_cseq_ST_st7_fsm_5, ap_sig_bdd_163, eol_3_reg_288)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((INPUT_STREAM_TVALID = ap_const_logic_0))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_5) and (ap_const_lv1_0 = eol_3_reg_288) and not(ap_sig_bdd_163)) or ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = brmerge_fu_344_p2) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1))))))) then
INPUT_STREAM_TREADY <= ap_const_logic_1;
else
INPUT_STREAM_TREADY <= ap_const_logic_0;
end if;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_done_reg, exitcond1_fu_319_p2, ap_sig_cseq_ST_st4_fsm_3)
begin
if (((ap_const_logic_1 = ap_done_reg) or ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((exitcond1_fu_319_p2 = ap_const_lv1_0))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(exitcond1_fu_319_p2, ap_sig_cseq_ST_st4_fsm_3)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3) and not((exitcond1_fu_319_p2 = ap_const_lv1_0)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_phiprechg_axi_last_V_2_reg_229pp1_it0 <= "X";
ap_reg_phiprechg_eol_2_reg_253pp1_it0 <= "X";
ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
-- ap_sig_bdd_101 assign process. --
ap_sig_bdd_101_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_101 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_112 assign process. --
ap_sig_bdd_112_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_112 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_119 assign process. --
ap_sig_bdd_119_assign_proc : process(exitcond2_fu_330_p2, brmerge_fu_344_p2)
begin
ap_sig_bdd_119 <= ((exitcond2_fu_330_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = brmerge_fu_344_p2));
end process;
-- ap_sig_bdd_120 assign process. --
ap_sig_bdd_120_assign_proc : process(INPUT_STREAM_TVALID, exitcond2_fu_330_p2, brmerge_fu_344_p2)
begin
ap_sig_bdd_120 <= ((INPUT_STREAM_TVALID = ap_const_logic_0) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = brmerge_fu_344_p2));
end process;
-- ap_sig_bdd_133 assign process. --
ap_sig_bdd_133_assign_proc : process(img_data_stream_0_V_full_n, img_data_stream_1_V_full_n, img_data_stream_2_V_full_n, exitcond2_reg_431)
begin
ap_sig_bdd_133 <= (((img_data_stream_0_V_full_n = ap_const_logic_0) and (exitcond2_reg_431 = ap_const_lv1_0)) or ((exitcond2_reg_431 = ap_const_lv1_0) and (img_data_stream_1_V_full_n = ap_const_logic_0)) or ((exitcond2_reg_431 = ap_const_lv1_0) and (img_data_stream_2_V_full_n = ap_const_logic_0)));
end process;
-- ap_sig_bdd_144 assign process. --
ap_sig_bdd_144_assign_proc : process(ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_sig_bdd_120, ap_reg_ppiten_pp1_it0, ap_sig_bdd_133, ap_reg_ppiten_pp1_it1)
begin
ap_sig_bdd_144 <= ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))));
end process;
-- ap_sig_bdd_158 assign process. --
ap_sig_bdd_158_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_158 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_bdd_163 assign process. --
ap_sig_bdd_163_assign_proc : process(INPUT_STREAM_TVALID, eol_3_reg_288)
begin
ap_sig_bdd_163 <= ((INPUT_STREAM_TVALID = ap_const_logic_0) and (ap_const_lv1_0 = eol_3_reg_288));
end process;
-- ap_sig_bdd_181 assign process. --
ap_sig_bdd_181_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_181 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
-- ap_sig_bdd_188 assign process. --
ap_sig_bdd_188_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_188 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_211 assign process. --
ap_sig_bdd_211_assign_proc : process(exitcond2_fu_330_p2, brmerge_fu_344_p2)
begin
ap_sig_bdd_211 <= ((exitcond2_fu_330_p2 = ap_const_lv1_0) and not((ap_const_lv1_0 = brmerge_fu_344_p2)));
end process;
-- ap_sig_bdd_229 assign process. --
ap_sig_bdd_229_assign_proc : process(exitcond2_fu_330_p2, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_reg_ppiten_pp1_it0)
begin
ap_sig_bdd_229 <= ((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_fu_330_p2 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0));
end process;
-- ap_sig_bdd_26 assign process. --
ap_sig_bdd_26_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_26 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_75 assign process. --
ap_sig_bdd_75_assign_proc : process(ap_start, ap_done_reg)
begin
ap_sig_bdd_75 <= ((ap_start = ap_const_logic_0) or (ap_done_reg = ap_const_logic_1));
end process;
-- ap_sig_bdd_87 assign process. --
ap_sig_bdd_87_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_87 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_cseq_ST_pp1_stg0_fsm_4 assign process. --
ap_sig_cseq_ST_pp1_stg0_fsm_4_assign_proc : process(ap_sig_bdd_112)
begin
if (ap_sig_bdd_112) then
ap_sig_cseq_ST_pp1_stg0_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_pp1_stg0_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_26)
begin
if (ap_sig_bdd_26) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_87)
begin
if (ap_sig_bdd_87) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_188)
begin
if (ap_sig_bdd_188) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_101)
begin
if (ap_sig_bdd_101) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st7_fsm_5 assign process. --
ap_sig_cseq_ST_st7_fsm_5_assign_proc : process(ap_sig_bdd_158)
begin
if (ap_sig_bdd_158) then
ap_sig_cseq_ST_st7_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st8_fsm_6 assign process. --
ap_sig_cseq_ST_st8_fsm_6_assign_proc : process(ap_sig_bdd_181)
begin
if (ap_sig_bdd_181) then
ap_sig_cseq_ST_st8_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_6 <= ap_const_logic_0;
end if;
end process;
-- axi_data_V_1_phi_fu_198_p4 assign process. --
axi_data_V_1_phi_fu_198_p4_assign_proc : process(axi_data_V_1_reg_195, p_Val2_s_reg_241, exitcond2_reg_431, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1))) then
axi_data_V_1_phi_fu_198_p4 <= p_Val2_s_reg_241;
else
axi_data_V_1_phi_fu_198_p4 <= axi_data_V_1_reg_195;
end if;
end process;
axi_last_V_1_mux_fu_356_p2 <= (eol_1_phi_fu_187_p4 or not_sof_2_fu_350_p2);
brmerge_fu_344_p2 <= (sof_1_fu_98 or eol_phi_fu_221_p4);
-- eol_1_phi_fu_187_p4 assign process. --
eol_1_phi_fu_187_p4_assign_proc : process(eol_1_reg_184, axi_last_V_2_reg_229, exitcond2_reg_431, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1))) then
eol_1_phi_fu_187_p4 <= axi_last_V_2_reg_229;
else
eol_1_phi_fu_187_p4 <= eol_1_reg_184;
end if;
end process;
-- eol_phi_fu_221_p4 assign process. --
eol_phi_fu_221_p4_assign_proc : process(eol_reg_217, eol_2_reg_253, exitcond2_reg_431, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1))) then
eol_phi_fu_221_p4 <= eol_2_reg_253;
else
eol_phi_fu_221_p4 <= eol_reg_217;
end if;
end process;
exitcond1_fu_319_p2 <= "1" when (p_s_reg_173 = img_rows_V_read) else "0";
exitcond2_fu_330_p2 <= "1" when (p_1_reg_206 = img_cols_V_read) else "0";
i_V_fu_324_p2 <= std_logic_vector(unsigned(p_s_reg_173) + unsigned(ap_const_lv12_1));
img_data_stream_0_V_din <= tmp_34_reg_444;
-- img_data_stream_0_V_write assign process. --
img_data_stream_0_V_write_assign_proc : process(exitcond2_reg_431, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_sig_bdd_120, ap_reg_ppiten_pp1_it0, ap_sig_bdd_133, ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
img_data_stream_0_V_write <= ap_const_logic_1;
else
img_data_stream_0_V_write <= ap_const_logic_0;
end if;
end process;
img_data_stream_1_V_din <= tmp_6_reg_449;
-- img_data_stream_1_V_write assign process. --
img_data_stream_1_V_write_assign_proc : process(exitcond2_reg_431, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_sig_bdd_120, ap_reg_ppiten_pp1_it0, ap_sig_bdd_133, ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
img_data_stream_1_V_write <= ap_const_logic_1;
else
img_data_stream_1_V_write <= ap_const_logic_0;
end if;
end process;
img_data_stream_2_V_din <= tmp_7_reg_454;
-- img_data_stream_2_V_write assign process. --
img_data_stream_2_V_write_assign_proc : process(exitcond2_reg_431, ap_sig_cseq_ST_pp1_stg0_fsm_4, ap_sig_bdd_120, ap_reg_ppiten_pp1_it0, ap_sig_bdd_133, ap_reg_ppiten_pp1_it1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_pp1_stg0_fsm_4) and (exitcond2_reg_431 = ap_const_lv1_0) and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1) and not(((ap_sig_bdd_120 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it0)) or (ap_sig_bdd_133 and (ap_const_logic_1 = ap_reg_ppiten_pp1_it1)))))) then
img_data_stream_2_V_write <= ap_const_logic_1;
else
img_data_stream_2_V_write <= ap_const_logic_0;
end if;
end process;
j_V_fu_335_p2 <= std_logic_vector(unsigned(p_1_reg_206) + unsigned(ap_const_lv12_1));
not_sof_2_fu_350_p2 <= (sof_1_fu_98 xor ap_const_lv1_1);
-- p_Val2_s_phi_fu_245_p4 assign process. --
p_Val2_s_phi_fu_245_p4_assign_proc : process(INPUT_STREAM_TDATA, brmerge_fu_344_p2, axi_data_V_1_phi_fu_198_p4, ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0, ap_sig_bdd_229)
begin
if (ap_sig_bdd_229) then
if (not((ap_const_lv1_0 = brmerge_fu_344_p2))) then
p_Val2_s_phi_fu_245_p4 <= axi_data_V_1_phi_fu_198_p4;
elsif ((ap_const_lv1_0 = brmerge_fu_344_p2)) then
p_Val2_s_phi_fu_245_p4 <= INPUT_STREAM_TDATA;
else
p_Val2_s_phi_fu_245_p4 <= ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0;
end if;
else
p_Val2_s_phi_fu_245_p4 <= ap_reg_phiprechg_p_Val2_s_reg_241pp1_it0;
end if;
end process;
tmp_34_fu_363_p1 <= p_Val2_s_phi_fu_245_p4(8 - 1 downto 0);
tmp_user_V_fu_310_p1 <= INPUT_STREAM_TUSER;
end behav;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_xa_e
--
-- Generated
-- by: wig
-- on: Wed Apr 5 12:50:28 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_xa_e-e.vhd,v 1.1 2006/04/10 15:42:11 wig Exp $
-- $Date: 2006/04/10 15:42:11 $
-- $Log: inst_xa_e-e.vhd,v $
-- Revision 1.1 2006/04/10 15:42:11 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_xa_e
--
entity inst_xa_e is
HOOK: global hook in entity
-- Generics:
-- No Generated Generics for Entity inst_xa_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_xa_e
port_xa_i : in std_ulogic; -- signal test aa to ba
port_xa_o : out std_ulogic -- open signal to create port
-- End of Generated Port for Entity inst_xa_e
);
end inst_xa_e;
--
-- End of Generated Entity inst_xa_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lab4 is
port(CLOCK_50 : in std_logic;
KEY : in std_logic_vector(3 downto 0);
SW : in std_logic_vector(17 downto 0);
LEDG : out std_logic_vector(7 downto 0);
VGA_R, VGA_G, VGA_B : out std_logic_vector(9 downto 0); -- The outs go to VGA controller
VGA_HS : out std_logic;
VGA_VS : out std_logic;
VGA_BLANK : out std_logic;
VGA_SYNC : out std_logic;
VGA_CLK : out std_logic);
end lab4;
architecture rtl of lab4 is
-- Component from the Verilog file: vga_adapter.v
component vga_adapter
generic(RESOLUTION : string);
port (
resetn : in std_logic;
clock : in std_logic;
colour : in std_logic_vector(2 downto 0);
x : in std_logic_vector(7 downto 0);
y : in std_logic_vector(6 downto 0);
plot : in std_logic;
VGA_R, VGA_G, VGA_B : out std_logic_vector(9 downto 0);
VGA_HS, VGA_VS, VGA_BLANK, VGA_SYNC, VGA_CLK : out std_logic);
end component;
component fsm is
PORT (
clock : IN STD_LOGIC;
resetb : IN STD_LOGIC;
xdone, ydone, ldone : IN STD_LOGIC;
sw : IN STD_LOGIC_VECTOR(17 downto 0);
draw : IN STD_LOGIC;
resetx, resety, incr_y, incr_x, plot, initl, drawl : OUT STD_LOGIC;
colour : OUT STD_LOGIC_VECTOR(2 downto 0);
x : OUT STD_LOGIC_VECTOR(7 downto 0);
y : OUT STD_LOGIC_VECTOR(6 downto 0);
ledg : OUT STD_LOGIC_VECTOR(7 downto 0)
);
end component;
component datapath is
PORT (
clock : IN STD_LOGIC;
resetb : IN STD_LOGIC;
resetx, resety, incr_y, incr_x, initl, drawl : IN STD_LOGIC;
x : OUT STD_LOGIC_VECTOR(7 downto 0);
y : OUT STD_LOGIC_VECTOR(6 downto 0);
xin : IN STD_LOGIC_VECTOR(7 downto 0); -- x1
yin : IN STD_LOGIC_VECTOR(6 downto 0); -- y1
xdone, ydone, ldone : OUT STD_LOGIC
);
end component;
signal s_x : std_logic_vector(7 downto 0) := "00000000";
signal s_y : std_logic_vector(6 downto 0) := "0000000";
signal colour : std_logic_vector(2 downto 0);
signal plot : std_logic;
signal resety, resetx, initl : std_logic;
signal xdone, ydone, ldone : std_logic;
signal incr_y, incr_x, drawl : std_logic;
signal x_int : std_logic_vector(7 downto 0);
signal y_int : std_logic_vector(6 downto 0);
begin
vga_u0 : vga_adapter
generic map(RESOLUTION => "160x120")
port map(resetn => KEY(3),
clock => CLOCK_50,
colour => colour,
x => s_x,
y => s_y,
plot => plot,
VGA_R => VGA_R,
VGA_G => VGA_G,
VGA_B => VGA_B,
VGA_HS => VGA_HS,
VGA_VS => VGA_VS,
VGA_BLANK => VGA_BLANK,
VGA_SYNC => VGA_SYNC,
VGA_CLK => VGA_CLK
);
fsm0 : fsm PORT MAP(
clock => CLOCK_50,
resetb => KEY(3),
xdone => xdone,
ydone => ydone,
ldone => ldone,
sw => SW,
draw => KEY(0),
resetx => resetx,
resety => resety,
incr_y => incr_y,
incr_x => incr_x,
plot => plot,
initl => initl,
drawl => drawl,
colour => colour,
x => x_int,
y => y_int,
ledg => LEDG
);
datapath0 : datapath PORT MAP(
clock => CLOCK_50,
resetb => KEY(3),
resetx => resetx,
resety => resety,
initl => initl,
drawl => drawl,
x => s_x,
y => s_y,
xin => x_int,
yin => y_int,
xdone => xdone,
ydone => ydone,
ldone => ldone,
incr_y => incr_y,
incr_x => incr_x
);
end rtl;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.config.all;
library techmap;
use techmap.gencomp.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
scantest : integer := CFG_SCAN
);
port (
resetn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
clk : in std_ulogic;
lock : out std_ulogic;
errorn : inout std_ulogic;
wdogn : inout std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
cb : inout std_logic_vector(7 downto 0);
sdclk : out std_ulogic;
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
dsutx : out std_ulogic; -- DSU tx data / scanout
dsurx : in std_ulogic; -- DSU rx data / scanin
dsuen : in std_ulogic;
dsubre : in std_ulogic; -- DSU break / scanen
dsuact : out std_ulogic; -- DSU active / NT
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_ulogic;
bexcn : in std_ulogic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
i2c_scl : inout std_ulogic;
i2c_sda : inout std_ulogic;
spi_miso : in std_ulogic;
spi_mosi : out std_ulogic;
spi_sck : out std_ulogic;
spi_slvsel : out std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
prom32 : in std_ulogic;
spw_clksel : in std_logic_vector(1 downto 0);
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
gtx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
etx_clk : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
emdio : inout std_logic;
emdc : out std_ulogic;
testen : in std_ulogic;
trst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic
);
end;
architecture rtl of leon3mp is
signal lresetn : std_ulogic;
signal lclksel : std_logic_vector (1 downto 0);
signal lclk : std_ulogic;
signal llock : std_ulogic;
signal lerrorn : std_ulogic;
signal laddress : std_logic_vector(27 downto 0);
signal ldatain : std_logic_vector(31 downto 0);
signal ldataout : std_logic_vector(31 downto 0);
signal ldataen : std_logic_vector(31 downto 0);
signal lcbin : std_logic_vector(7 downto 0);
signal lcbout : std_logic_vector(7 downto 0);
signal lcben : std_logic_vector(7 downto 0);
signal lsdclk : std_ulogic;
signal lsdcsn : std_logic_vector (1 downto 0);
signal lsdwen : std_ulogic;
signal lsdrasn : std_ulogic;
signal lsdcasn : std_ulogic;
signal lsddqm : std_logic_vector (3 downto 0);
signal ldsutx : std_ulogic;
signal ldsurx : std_ulogic;
signal ldsuen : std_ulogic;
signal ldsubre : std_ulogic;
signal ldsuact : std_ulogic;
signal ltxd1 : std_ulogic;
signal lrxd1 : std_ulogic;
signal ltxd2 : std_ulogic;
signal lrxd2 : std_ulogic;
signal lramsn : std_logic_vector (4 downto 0);
signal lramoen : std_logic_vector (4 downto 0);
signal lrwen : std_logic_vector (3 downto 0);
signal loen : std_ulogic;
signal lwriten : std_ulogic;
signal lread : std_ulogic;
signal liosn : std_ulogic;
signal lromsn : std_logic_vector (1 downto 0);
signal lbrdyn : std_ulogic;
signal lbexcn : std_ulogic;
signal lwdogn : std_ulogic;
signal lgpioin : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal lgpioout : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal lgpioen : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal li2c_sclout : std_ulogic;
signal li2c_sclen : std_ulogic;
signal li2c_sclin : std_ulogic;
signal li2c_sdaout : std_ulogic;
signal li2c_sdaen : std_ulogic;
signal li2c_sdain : std_ulogic;
signal lspi_miso : std_ulogic;
signal lspi_mosi : std_ulogic;
signal lspi_sck : std_ulogic;
signal lspi_slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal lprom32 : std_ulogic;
signal lspw_clksel : std_logic_vector (1 downto 0);
signal lspw_clk : std_ulogic;
signal lspw_rxd : std_logic_vector(0 to CFG_SPW_NUM-1);
signal lspw_rxs : std_logic_vector(0 to CFG_SPW_NUM-1);
signal lspw_txd : std_logic_vector(0 to CFG_SPW_NUM-1);
signal lspw_txs : std_logic_vector(0 to CFG_SPW_NUM-1);
signal lgtx_clk : std_ulogic;
signal lerx_clk : std_ulogic;
signal lerxd : std_logic_vector(7 downto 0);
signal lerx_dv : std_ulogic;
signal letx_clk : std_ulogic;
signal letxd : std_logic_vector(7 downto 0);
signal letx_en : std_ulogic;
signal letx_er : std_ulogic;
signal lerx_er : std_ulogic;
signal lerx_col : std_ulogic;
signal lerx_crs : std_ulogic;
signal lemdint : std_ulogic;
signal lemdioin : std_logic;
signal lemdioout : std_logic;
signal lemdioen : std_logic;
signal lemdc : std_ulogic;
signal ltesten : std_ulogic;
signal ltrst : std_ulogic;
signal ltck : std_ulogic;
signal ltms : std_ulogic;
signal ltdi : std_ulogic;
signal ltdo : std_ulogic;
signal ltdoen : std_ulogic;
-- Use for ASIC
--constant padvoltage : integer := x33v;
--constant padlevel : integer := ttl;
-- Use for FPGA
constant padvoltage : integer := x18v;
constant padlevel : integer := cmos;
begin
-- TODO: Move PAD options to 'xconfig'
pads0 : entity work.pads
generic map (
padtech => CFG_PADTECH,
padlevel => padlevel,
padstrength => 4,
jtag_padfilter => pullup,
testen_padfilter => pulldown,
resetn_padfilter => schmitt,
clk_padfilter => 0,
spw_padstrength => 12,
jtag_padstrength => 4,
uart_padstrength => 4,
dsu_padstrength => 4,
padvoltage => padvoltage,
spw_input_type => CFG_SPW_INPUT,
oepol => padoen_polarity(CFG_PADTECH)
)
port map (
---------------------------
--to chip boundary
---------------------------
resetn => resetn ,
clksel => clksel ,
clk => clk ,
lock => lock ,
errorn => errorn ,
address => address ,
data => data ,
cb => cb ,
sdclk => sdclk ,
sdcsn => sdcsn ,
sdwen => sdwen ,
sdrasn => sdrasn ,
sdcasn => sdcasn ,
sddqm => sddqm ,
dsutx => dsutx ,
dsurx => dsurx ,
dsuen => dsuen ,
dsubre => dsubre ,
dsuact => dsuact ,
txd1 => txd1 ,
rxd1 => rxd1 ,
txd2 => txd2 ,
rxd2 => rxd2 ,
ramsn => ramsn ,
ramoen => ramoen ,
rwen => rwen ,
oen => oen ,
writen => writen ,
read => read ,
iosn => iosn ,
romsn => romsn ,
brdyn => brdyn ,
bexcn => bexcn ,
wdogn => wdogn ,
gpio => gpio ,
i2c_scl => i2c_scl ,
i2c_sda => i2c_sda ,
spi_miso => spi_miso ,
spi_mosi => spi_mosi ,
spi_sck => spi_sck ,
spi_slvsel => spi_slvsel,
prom32 => prom32 ,
spw_clksel => spw_clksel,
spw_clk => spw_clk ,
spw_rxd => spw_rxd ,
spw_rxs => spw_rxs ,
spw_txd => spw_txd ,
spw_txs => spw_txs ,
gtx_clk => gtx_clk ,
erx_clk => erx_clk ,
erxd => erxd ,
erx_dv => erx_dv ,
etx_clk => etx_clk ,
etxd => etxd ,
etx_en => etx_en ,
etx_er => etx_er ,
erx_er => erx_er ,
erx_col => erx_col ,
erx_crs => erx_crs ,
emdint => emdint ,
emdio => emdio ,
emdc => emdc ,
testen => testen ,
trst => trst ,
tck => tck ,
tms => tms ,
tdi => tdi ,
tdo => tdo ,
------------------------- ---
--to core
----------------------------
lresetn => lresetn ,
lclksel => lclksel ,
lclk => lclk ,
llock => llock ,
lerrorn => lerrorn ,
laddress => laddress ,
ldatain => ldatain ,
ldataout => ldataout ,
ldataen => ldataen ,
lcbin => lcbin ,
lcbout => lcbout ,
lcben => lcben ,
lsdclk => lsdclk ,
lsdcsn => lsdcsn ,
lsdwen => lsdwen ,
lsdrasn => lsdrasn ,
lsdcasn => lsdcasn ,
lsddqm => lsddqm ,
ldsutx => ldsutx ,
ldsurx => ldsurx ,
ldsuen => ldsuen ,
ldsubre => ldsubre ,
ldsuact => ldsuact ,
ltxd1 => ltxd1 ,
lrxd1 => lrxd1 ,
ltxd2 => ltxd2 ,
lrxd2 => lrxd2 ,
lramsn => lramsn ,
lramoen => lramoen ,
lrwen => lrwen ,
loen => loen ,
lwriten => lwriten ,
lread => lread ,
liosn => liosn ,
lromsn => lromsn ,
lbrdyn => lbrdyn ,
lbexcn => lbexcn ,
lwdogn => lwdogn ,
lgpioin => lgpioin ,
lgpioout => lgpioout ,
lgpioen => lgpioen ,
li2c_sclout => li2c_sclout,
li2c_sclen => li2c_sclen ,
li2c_sclin => li2c_sclin ,
li2c_sdaout => li2c_sdaout,
li2c_sdaen => li2c_sdaen ,
li2c_sdain => li2c_sdain ,
lspi_miso => lspi_miso ,
lspi_mosi => lspi_mosi ,
lspi_sck => lspi_sck ,
lspi_slvsel => lspi_slvsel,
lprom32 => lprom32 ,
lspw_clksel => lspw_clksel,
lspw_clk => lspw_clk ,
lspw_rxd => lspw_rxd ,
lspw_rxs => lspw_rxs ,
lspw_txd => lspw_txd ,
lspw_txs => lspw_txs ,
lgtx_clk => lgtx_clk ,
lerx_clk => lerx_clk ,
lerxd => lerxd ,
lerx_dv => lerx_dv ,
letx_clk => letx_clk ,
letxd => letxd ,
letx_en => letx_en ,
letx_er => letx_er ,
lerx_er => lerx_er ,
lerx_col => lerx_col ,
lerx_crs => lerx_crs ,
lemdint => lemdint ,
lemdioin => lemdioin ,
lemdioout => lemdioout ,
lemdioen => lemdioen ,
lemdc => lemdc ,
ltesten => ltesten ,
ltrst => ltrst ,
ltck => ltck ,
ltms => ltms ,
ltdi => ltdi ,
ltdo => ltdo ,
ltdoen => ltdoen
);
-- ASIC Core
core0 : entity work.core
generic map (
fabtech => CFG_FABTECH,
memtech => CFG_MEMTECH,
padtech => CFG_PADTECH,
clktech => CFG_CLKTECH,
disas => CFG_DISAS,
dbguart => CFG_DUART,
pclow => CFG_PCLOW,
scantest => CFG_SCAN,
bscanen => CFG_BOUNDSCAN_EN,
oepol => padoen_polarity(CFG_PADTECH)
)
port map (
----------------------------
-- ASIC Ports/Pads
----------------------------
resetn => lresetn ,
clksel => lclksel ,
clk => lclk ,
lock => llock ,
errorn => lerrorn ,
address => laddress ,
datain => ldatain ,
dataout => ldataout ,
dataen => ldataen ,
cbin => lcbin ,
cbout => lcbout ,
cben => lcben ,
sdclk => lsdclk ,
sdcsn => lsdcsn ,
sdwen => lsdwen ,
sdrasn => lsdrasn ,
sdcasn => lsdcasn ,
sddqm => lsddqm ,
dsutx => ldsutx ,
dsurx => ldsurx ,
dsuen => ldsuen ,
dsubre => ldsubre ,
dsuact => ldsuact ,
txd1 => ltxd1 ,
rxd1 => lrxd1 ,
txd2 => ltxd2 ,
rxd2 => lrxd2 ,
ramsn => lramsn ,
ramoen => lramoen ,
rwen => lrwen ,
oen => loen ,
writen => lwriten ,
read => lread ,
iosn => liosn ,
romsn => lromsn ,
brdyn => lbrdyn ,
bexcn => lbexcn ,
wdogn => lwdogn ,
gpioin => lgpioin ,
gpioout => lgpioout ,
gpioen => lgpioen ,
i2c_sclout => li2c_sclout,
i2c_sclen => li2c_sclen ,
i2c_sclin => li2c_sclin ,
i2c_sdaout => li2c_sdaout,
i2c_sdaen => li2c_sdaen ,
i2c_sdain => li2c_sdain ,
spi_miso => lspi_miso ,
spi_mosi => lspi_mosi ,
spi_sck => lspi_sck ,
spi_slvsel => lspi_slvsel,
prom32 => lprom32 ,
spw_clksel => lspw_clksel,
spw_clk => lspw_clk ,
spw_rxd => lspw_rxd ,
spw_rxs => lspw_rxs ,
spw_txd => lspw_txd ,
spw_txs => lspw_txs ,
gtx_clk => lgtx_clk ,
erx_clk => lerx_clk ,
erxd => lerxd ,
erx_dv => lerx_dv ,
etx_clk => letx_clk ,
etxd => letxd ,
etx_en => letx_en ,
etx_er => letx_er ,
erx_er => lerx_er ,
erx_col => lerx_col ,
erx_crs => lerx_crs ,
emdint => lemdint ,
emdioin => lemdioin ,
emdioout => lemdioout ,
emdioen => lemdioen ,
emdc => lemdc ,
testen => ltesten ,
trst => ltrst ,
tck => ltck ,
tms => ltms ,
tdi => ltdi ,
tdo => ltdo ,
tdoen => ltdoen ,
----------------------------
-- BSCAN
----------------------------
chain_tck => OPEN ,
chain_tckn => OPEN ,
chain_tdi => OPEN ,
chain_tdo => '0',
bsshft => OPEN ,
bscapt => OPEN ,
bsupdi => OPEN ,
bsupdo => OPEN ,
bsdrive => OPEN ,
bshighz => OPEN
);
-- BSCAN
-- TODO: ADD BSCAN
end;
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`protect begin_protected
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`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5728)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect begin_protected
`protect version = 1
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`protect key_block
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`protect data_block
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`protect begin_protected
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`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect key_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 22-02-2016
-- Module Name: register_t.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity n_register_t is
end entity;
architecture arch_n_register_t of n_register_t is
component n_register is
generic (N : integer := 8);
port (d : in std_logic_vector(N - 1 downto 0);
clk, s_sync, r_sync : in std_logic;
s_async, r_async : in std_logic;
q : out std_logic_vector(N - 1 downto 0));
end component n_register;
for all:n_register use entity work.n_register(beh_arch_n_register);
signal clk, s_sync, r_sync, s_async, r_async : std_logic;
signal d, q : std_logic_vector(0 downto 0);
begin
reg_1 : n_register generic map (1) port map (d, clk, s_sync, r_sync, s_async, r_async, q);
d <= "0", "1" after 100 ns, "0" after 200 ns;
end architecture arch_n_register_t;
|
package pkg is
type BIT is range 0 to 1;
end package;
library work;
use work.pkg;
entity clkgen is
port (CK: out pkg.BIT);
end;
architecture behav of clkgen is
begin
p_clkgen: process
begin
CK <= 0;
wait for 10 ns;
for I in 0 to 3 loop
CK <= 1;
wait for 5 ns;
CK <= 0;
wait for 5 ns;
end loop;
end process;
end;
|
architecture RTL of FIFO is
attribute coordinate of comp_1:component is (0.0, 17.5);
-- Violations below
attribute coordinate of comp_1:component is (0.0, 17.5);
begin
end architecture RTL;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ieee754_fp_adder_subtractor:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_ieee754_fp_adder_subtractor_0_0 IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END affine_block_ieee754_fp_adder_subtractor_0_0;
ARCHITECTURE affine_block_ieee754_fp_adder_subtractor_0_0_arch OF affine_block_ieee754_fp_adder_subtractor_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_ieee754_fp_adder_subtractor_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ieee754_fp_adder_subtractor IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT ieee754_fp_adder_subtractor;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF affine_block_ieee754_fp_adder_subtractor_0_0_arch: ARCHITECTURE IS "ieee754_fp_adder_subtractor,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF affine_block_ieee754_fp_adder_subtractor_0_0_arch : ARCHITECTURE IS "affine_block_ieee754_fp_adder_subtractor_0_0,ieee754_fp_adder_subtractor,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF affine_block_ieee754_fp_adder_subtractor_0_0_arch: ARCHITECTURE IS "affine_block_ieee754_fp_adder_subtractor_0_0,ieee754_fp_adder_subtractor,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ieee754_fp_adder_subtractor,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : ieee754_fp_adder_subtractor
PORT MAP (
x => x,
y => y,
z => z
);
END affine_block_ieee754_fp_adder_subtractor_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ieee754_fp_adder_subtractor:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_ieee754_fp_adder_subtractor_0_0 IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END affine_block_ieee754_fp_adder_subtractor_0_0;
ARCHITECTURE affine_block_ieee754_fp_adder_subtractor_0_0_arch OF affine_block_ieee754_fp_adder_subtractor_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_ieee754_fp_adder_subtractor_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ieee754_fp_adder_subtractor IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT ieee754_fp_adder_subtractor;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF affine_block_ieee754_fp_adder_subtractor_0_0_arch: ARCHITECTURE IS "ieee754_fp_adder_subtractor,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF affine_block_ieee754_fp_adder_subtractor_0_0_arch : ARCHITECTURE IS "affine_block_ieee754_fp_adder_subtractor_0_0,ieee754_fp_adder_subtractor,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF affine_block_ieee754_fp_adder_subtractor_0_0_arch: ARCHITECTURE IS "affine_block_ieee754_fp_adder_subtractor_0_0,ieee754_fp_adder_subtractor,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ieee754_fp_adder_subtractor,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : ieee754_fp_adder_subtractor
PORT MAP (
x => x,
y => y,
z => z
);
END affine_block_ieee754_fp_adder_subtractor_0_0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_dc_xhuff_tbl_huffval is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(9 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(9 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end p_jinfo_dc_xhuff_tbl_huffval;
architecture augh of p_jinfo_dc_xhuff_tbl_huffval is
-- Embedded RAM
type ram_type is array (0 to 1023) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_dc_xhuff_tbl_huffval is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(9 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(9 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end p_jinfo_dc_xhuff_tbl_huffval;
architecture augh of p_jinfo_dc_xhuff_tbl_huffval is
-- Embedded RAM
type ram_type is array (0 to 1023) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1327.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p03n02i01327ent IS
END c08s04b01x00p03n02i01327ent;
ARCHITECTURE c08s04b01x00p03n02i01327arch OF c08s04b01x00p03n02i01327ent IS
-- enumerated types.
type SWITCH_LEVEL is ('0', '1', 'X');
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
-- integer types.
type POSITIVE is range 0 to INTEGER'HIGH;
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
-- floating point types.
type POSITIVE_R is range 0.0 to REAL'HIGH;
-- array types.
type MEMORY is array(INTEGER range <>) of BIT;
type WORD is array(0 to 31) of BIT;
type BYTE is array(7 downto 0) of BIT;
-- record types.
type DATE is
record
DAY : INTEGER range 1 to 31;
MONTH : INTEGER range 1 to 12;
YEAR : INTEGER range -10000 to 1988;
end record;
-- Signals with no resolution function.
signal SWITCHSIG : SWITCH_LEVEL;
signal LOGICSIG : LOGIC_SWITCH;
signal CHARSIG : CHARACTER;
signal BOOLSIG : BOOLEAN;
signal SEVERSIG : SEVERITY_LEVEL;
signal INTSIG : INTEGER;
signal POSSIG : POSITIVE;
signal DISTSIG : DISTANCE;
signal TIMESIG : TIME;
signal REALSIG : REAL;
signal POSRSIG : POSITIVE_R;
signal BYTESIG : BYTE;
signal RECSIG : DATE;
-- Composite signals with resolution functions on the scalar subelements.
BEGIN
TESTING: PROCESS
-- local variables
variable ShouldBeTime : TIME := 0 ns;
variable k : integer := 0;
BEGIN
-- Test each signal assignment.
SWITCHSIG <= '1' after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on SWITCHSIG;
if (ShouldBeTime /= now or switchsig /= '1') then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (SWITCHSIG = '1');
LOGICSIG <= '1' after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on LOGICSIG;
if (ShouldBeTime /= now or logicsig /= '1') then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (LOGICSIG = '1');
CHARSIG <= '1' after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on CHARSIG;
if (ShouldBeTime /= now or charsig /= '1') then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (CHARSIG = '1');
BOOLSIG <= TRUE after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on BOOLSIG;
if (ShouldBeTime /= now or boolsig /= true) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (BOOLSIG = TRUE);
SEVERSIG <= ERROR after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on SEVERSIG;
if (ShouldBeTime /= now or seversig /= error) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (SEVERSIG = ERROR);
INTSIG <= 47 after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on INTSIG;
if (ShouldBeTime /= now or intsig /= 47) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (INTSIG = 47);
POSSIG <= 47 after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on POSSIG;
if (ShouldBeTime /= now or possig /= 47) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (POSSIG = 47);
DISTSIG <= 1 A after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on DISTSIG;
if (ShouldBeTime /= now or distsig /= 1 A) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (DISTSIG = 1 A);
TIMESIG <= 10 ns after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on TIMESIG;
if (ShouldBeTime /= now or timesig /= 10 ns) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (TIMESIG = 10 ns);
REALSIG <= 47.0 after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on REALSIG;
if (ShouldBeTime /= now or realsig /= 47.0) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (REALSIG = 47.0);
POSRSIG <= 47.0 after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on POSRSIG;
if (ShouldBeTime /= now or posrsig /= 47.0) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (POSRSIG = 47.0);
BYTESIG <= B"10101010" after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on BYTESIG;
if (ShouldBeTime /= now or bytesig /= B"10101010") then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (BYTESIG = B"10101010");
RECSIG <= ( DAY => 14, MONTH => 2, YEAR => 1988 ) after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on RECSIG;
if (ShouldBeTime /= now or recsig.day /= 14 or recsig.month /= 2 or recsig.year /= 1988) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (RECSIG.DAY = 14);
assert (RECSIG.MONTH = 2);
assert (RECSIG.YEAR = 1988);
assert NOT( k=0 )
report "***PASSED TEST: c08s04b01x00p03n02i01327"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s04b01x00p03n02i01327 - Evaluation of waveform elements is used to specify that driver is to assign a particular value to a target at the specified time."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p03n02i01327arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1327.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p03n02i01327ent IS
END c08s04b01x00p03n02i01327ent;
ARCHITECTURE c08s04b01x00p03n02i01327arch OF c08s04b01x00p03n02i01327ent IS
-- enumerated types.
type SWITCH_LEVEL is ('0', '1', 'X');
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
-- integer types.
type POSITIVE is range 0 to INTEGER'HIGH;
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
-- floating point types.
type POSITIVE_R is range 0.0 to REAL'HIGH;
-- array types.
type MEMORY is array(INTEGER range <>) of BIT;
type WORD is array(0 to 31) of BIT;
type BYTE is array(7 downto 0) of BIT;
-- record types.
type DATE is
record
DAY : INTEGER range 1 to 31;
MONTH : INTEGER range 1 to 12;
YEAR : INTEGER range -10000 to 1988;
end record;
-- Signals with no resolution function.
signal SWITCHSIG : SWITCH_LEVEL;
signal LOGICSIG : LOGIC_SWITCH;
signal CHARSIG : CHARACTER;
signal BOOLSIG : BOOLEAN;
signal SEVERSIG : SEVERITY_LEVEL;
signal INTSIG : INTEGER;
signal POSSIG : POSITIVE;
signal DISTSIG : DISTANCE;
signal TIMESIG : TIME;
signal REALSIG : REAL;
signal POSRSIG : POSITIVE_R;
signal BYTESIG : BYTE;
signal RECSIG : DATE;
-- Composite signals with resolution functions on the scalar subelements.
BEGIN
TESTING: PROCESS
-- local variables
variable ShouldBeTime : TIME := 0 ns;
variable k : integer := 0;
BEGIN
-- Test each signal assignment.
SWITCHSIG <= '1' after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on SWITCHSIG;
if (ShouldBeTime /= now or switchsig /= '1') then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (SWITCHSIG = '1');
LOGICSIG <= '1' after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on LOGICSIG;
if (ShouldBeTime /= now or logicsig /= '1') then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (LOGICSIG = '1');
CHARSIG <= '1' after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on CHARSIG;
if (ShouldBeTime /= now or charsig /= '1') then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (CHARSIG = '1');
BOOLSIG <= TRUE after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on BOOLSIG;
if (ShouldBeTime /= now or boolsig /= true) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (BOOLSIG = TRUE);
SEVERSIG <= ERROR after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on SEVERSIG;
if (ShouldBeTime /= now or seversig /= error) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (SEVERSIG = ERROR);
INTSIG <= 47 after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on INTSIG;
if (ShouldBeTime /= now or intsig /= 47) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (INTSIG = 47);
POSSIG <= 47 after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on POSSIG;
if (ShouldBeTime /= now or possig /= 47) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (POSSIG = 47);
DISTSIG <= 1 A after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on DISTSIG;
if (ShouldBeTime /= now or distsig /= 1 A) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (DISTSIG = 1 A);
TIMESIG <= 10 ns after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on TIMESIG;
if (ShouldBeTime /= now or timesig /= 10 ns) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (TIMESIG = 10 ns);
REALSIG <= 47.0 after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on REALSIG;
if (ShouldBeTime /= now or realsig /= 47.0) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (REALSIG = 47.0);
POSRSIG <= 47.0 after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on POSRSIG;
if (ShouldBeTime /= now or posrsig /= 47.0) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (POSRSIG = 47.0);
BYTESIG <= B"10101010" after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on BYTESIG;
if (ShouldBeTime /= now or bytesig /= B"10101010") then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (BYTESIG = B"10101010");
RECSIG <= ( DAY => 14, MONTH => 2, YEAR => 1988 ) after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on RECSIG;
if (ShouldBeTime /= now or recsig.day /= 14 or recsig.month /= 2 or recsig.year /= 1988) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (RECSIG.DAY = 14);
assert (RECSIG.MONTH = 2);
assert (RECSIG.YEAR = 1988);
assert NOT( k=0 )
report "***PASSED TEST: c08s04b01x00p03n02i01327"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s04b01x00p03n02i01327 - Evaluation of waveform elements is used to specify that driver is to assign a particular value to a target at the specified time."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p03n02i01327arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1327.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p03n02i01327ent IS
END c08s04b01x00p03n02i01327ent;
ARCHITECTURE c08s04b01x00p03n02i01327arch OF c08s04b01x00p03n02i01327ent IS
-- enumerated types.
type SWITCH_LEVEL is ('0', '1', 'X');
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
-- integer types.
type POSITIVE is range 0 to INTEGER'HIGH;
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
-- floating point types.
type POSITIVE_R is range 0.0 to REAL'HIGH;
-- array types.
type MEMORY is array(INTEGER range <>) of BIT;
type WORD is array(0 to 31) of BIT;
type BYTE is array(7 downto 0) of BIT;
-- record types.
type DATE is
record
DAY : INTEGER range 1 to 31;
MONTH : INTEGER range 1 to 12;
YEAR : INTEGER range -10000 to 1988;
end record;
-- Signals with no resolution function.
signal SWITCHSIG : SWITCH_LEVEL;
signal LOGICSIG : LOGIC_SWITCH;
signal CHARSIG : CHARACTER;
signal BOOLSIG : BOOLEAN;
signal SEVERSIG : SEVERITY_LEVEL;
signal INTSIG : INTEGER;
signal POSSIG : POSITIVE;
signal DISTSIG : DISTANCE;
signal TIMESIG : TIME;
signal REALSIG : REAL;
signal POSRSIG : POSITIVE_R;
signal BYTESIG : BYTE;
signal RECSIG : DATE;
-- Composite signals with resolution functions on the scalar subelements.
BEGIN
TESTING: PROCESS
-- local variables
variable ShouldBeTime : TIME := 0 ns;
variable k : integer := 0;
BEGIN
-- Test each signal assignment.
SWITCHSIG <= '1' after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on SWITCHSIG;
if (ShouldBeTime /= now or switchsig /= '1') then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (SWITCHSIG = '1');
LOGICSIG <= '1' after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on LOGICSIG;
if (ShouldBeTime /= now or logicsig /= '1') then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (LOGICSIG = '1');
CHARSIG <= '1' after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on CHARSIG;
if (ShouldBeTime /= now or charsig /= '1') then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (CHARSIG = '1');
BOOLSIG <= TRUE after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on BOOLSIG;
if (ShouldBeTime /= now or boolsig /= true) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (BOOLSIG = TRUE);
SEVERSIG <= ERROR after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on SEVERSIG;
if (ShouldBeTime /= now or seversig /= error) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (SEVERSIG = ERROR);
INTSIG <= 47 after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on INTSIG;
if (ShouldBeTime /= now or intsig /= 47) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (INTSIG = 47);
POSSIG <= 47 after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on POSSIG;
if (ShouldBeTime /= now or possig /= 47) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (POSSIG = 47);
DISTSIG <= 1 A after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on DISTSIG;
if (ShouldBeTime /= now or distsig /= 1 A) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (DISTSIG = 1 A);
TIMESIG <= 10 ns after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on TIMESIG;
if (ShouldBeTime /= now or timesig /= 10 ns) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (TIMESIG = 10 ns);
REALSIG <= 47.0 after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on REALSIG;
if (ShouldBeTime /= now or realsig /= 47.0) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (REALSIG = 47.0);
POSRSIG <= 47.0 after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on POSRSIG;
if (ShouldBeTime /= now or posrsig /= 47.0) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (POSRSIG = 47.0);
BYTESIG <= B"10101010" after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on BYTESIG;
if (ShouldBeTime /= now or bytesig /= B"10101010") then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (BYTESIG = B"10101010");
RECSIG <= ( DAY => 14, MONTH => 2, YEAR => 1988 ) after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on RECSIG;
if (ShouldBeTime /= now or recsig.day /= 14 or recsig.month /= 2 or recsig.year /= 1988) then
k := 1;
end if;
assert (ShouldBeTime = NOW);
assert (RECSIG.DAY = 14);
assert (RECSIG.MONTH = 2);
assert (RECSIG.YEAR = 1988);
assert NOT( k=0 )
report "***PASSED TEST: c08s04b01x00p03n02i01327"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s04b01x00p03n02i01327 - Evaluation of waveform elements is used to specify that driver is to assign a particular value to a target at the specified time."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p03n02i01327arch;
|
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
entity fullAdder is
-- Full, 1 bit adder
port(
a, b, c: in std_logic;
r, s : out std_logic
);
end entity fullAdder;
architecture rtl of fullAdder is
signal s1, c1, c2 : std_logic;
component halfAdder
port(
a, b : in std_logic;
s, c : out std_logic
);
end component halfAdder;
begin
i1: halfAdder port map(a=>a , b=>b, s=>s1, c=>c1);
i2: halfAdder port map(a=>s1, b=>c, s=>s , c=>c2 );
r <= c1 or c2;
end architecture rtl;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun May 28 19:58:38 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_clk_wiz_0_0 -prefix
-- system_clk_wiz_0_0_ system_clk_wiz_0_0_stub.vhdl
-- Design : system_clk_wiz_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_clk_wiz_0_0 is
Port (
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end system_clk_wiz_0_0;
architecture stub of system_clk_wiz_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_out1,locked,clk_in1";
begin
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun May 28 19:58:38 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_clk_wiz_0_0 -prefix
-- system_clk_wiz_0_0_ system_clk_wiz_0_0_stub.vhdl
-- Design : system_clk_wiz_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_clk_wiz_0_0 is
Port (
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end system_clk_wiz_0_0;
architecture stub of system_clk_wiz_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_out1,locked,clk_in1";
begin
end;
|
-------------------------------------------------------------------------------
-- Title : Song ROM and Duration Counter
-- Project :
-------------------------------------------------------------------------------
-- File : SongDB.vhd
-- Author : <Marco@JUDI-WIN10>
-- Company :
-- Created : 2016-07-28
-- Last update: 2016-07-29
-- Platform : Mentor Graphics ModelSim, Altera Quartus
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Implements the song ROM and the duration counter to release the
-- next key.
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-07-28 1.0 Marco Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.Helpers_Pkg.all;
entity SongDB is
port (
Clk_CI : in std_logic;
Reset_SI : in std_logic;
KeyTick_SI : in std_logic;
NewKeyData_DO : out std_logic_vector(6 downto 0);
NewKeyValid_SO : out std_logic);
end entity SongDB;
architecture RTL of SongDB is
-- ROM constants (adapt to Quartus IP and generated .mif file)
constant SONG_ROM_ADDR_WIDTH : integer := 11; -- adapt to song ROM address width
constant MAX_SONG_ADDR : integer := 1067; -- adapt to song ROM depth
-- duration counter
constant DURATION_COUNTER_WIDTH : integer := 10; -- fixed in MATLAB
signal DurCounter_S : unsigned(DURATION_COUNTER_WIDTH-1 downto 0) := (others => '0');
signal DurationZero_S : std_logic := '0';
signal LoadNextDuration_S : std_logic := '0';
-- address counter
signal GenNextAddr_S : std_logic := '0';
signal AddrCounter_S : unsigned(SONG_ROM_ADDR_WIDTH-1 downto 0) := (others => '0');
-- song rom output
signal ROMout_D : std_logic_vector(16 downto 0) := (others => '0');
signal CurKey_D : std_logic_vector(6 downto 0) := (others => '0');
signal CurDuration_D : std_logic_vector(9 downto 0) := (others => '0');
-- fsm
type states_t is (INIT, WAITZERO, ADDRLAT1, ROMLAT1, ROMLAT2);
signal State_SN, State_SP : states_t;
begin -- architecture RTL
-- instantiate song rom (latency 2)
SongROM_i : entity work.SongROM
port map (
address => std_logic_vector(AddrCounter_S),
clock => Clk_CI,
q => ROMout_D);
CurKey_D <= ROMout_D(6 downto 0);
CurDuration_D <= ROMout_D(16 downto 7);
-- address counter
addr_gen : process (Clk_CI) is
begin -- process addr_gen
if Clk_CI'event and Clk_CI = '1' then -- rising clock edge
if Reset_SI = '1' then -- synchronous reset (active high)
AddrCounter_S <= (others => '0');
else
if GenNextAddr_S = '1' then
if AddrCounter_S = MAX_SONG_ADDR then
AddrCounter_S <= (others => '0');
else
AddrCounter_S <= AddrCounter_S + 1;
end if;
end if;
end if;
end if;
end process addr_gen;
-- duration counter
dur_gen : process (Clk_CI) is
begin -- process addr_gen
if Clk_CI'event and Clk_CI = '1' then -- rising clock edge
if Reset_SI = '1' then -- synchronous reset (active high)
DurCounter_S <= (others => '0');
else
if KeyTick_SI = '1' then
DurCounter_S <= DurCounter_S - 1;
end if;
if LoadNextDuration_S = '1' then
DurCounter_S <= unsigned(CurDuration_D);
end if;
end if;
end if;
end process dur_gen;
DurationZero_S <= bool2sl(DurCounter_S = 0);
-- outputs
NewKeyData_DO <= CurKey_D;
NewKeyValid_SO <= LoadNextDuration_S;
-----------------------------------------------------------------------------
-- FSM
-----------------------------------------------------------------------------
fsm_comb : process (DurationZero_S, State_SP) is
begin -- process fsm_comb
-- default assignments
State_SN <= State_SP;
LoadNextDuration_S <= '0';
GenNextAddr_S <= '0';
case State_SP is
when INIT =>
-- init state, duration does not matter, just load address 0 data for
-- the first note
State_SN <= ADDRLAT1;
-------------------------------------------------------------------------
when WAITZERO =>
if DurationZero_S = '1' then
GenNextAddr_S <= '1';
State_SN <= ADDRLAT1;
end if;
-------------------------------------------------------------------------
when ADDRLAT1 =>
State_SN <= ROMLAT1;
-------------------------------------------------------------------------
when ROMLAT1 =>
State_SN <= ROMLAT2;
-------------------------------------------------------------------------
when ROMLAT2 =>
LoadNextDuration_S <= '1';
State_SN <= WAITZERO;
-----------------------------------------------------------------------
when others =>
State_SN <= INIT;
end case;
end process fsm_comb;
fsm_reg : process (Clk_CI) is
begin -- process fsm_reg
if Clk_CI'event and Clk_CI = '1' then -- rising clock edge
if Reset_SI = '1' then -- synchronous reset (active high)
State_SP <= INIT;
else
State_SP <= State_SN;
end if;
end if;
end process fsm_reg;
end architecture RTL;
|
use std.textio.all;
entity issue308 is
generic (TIME_WIDTH : integer := 13);
end issue308;
architecture MODEL of issue308 is
begin
process
variable text_line : LINE;
procedure p(T:in time;M:in string) is
begin
if (TIME_WIDTH > 0) then
WRITE(text_line, T, RIGHT, TIME_WIDTH);
elsif (TIME_WIDTH < 0) then
WRITE(text_line, T, LEFT , -TIME_WIDTH);
end if;
WRITE(text_line, string'(" ") & M);
WRITELINE(OUTPUT, text_line);
end procedure;
begin
p(Now, string'("Simulation Start."));
wait for 100 ns;
p(Now, string'("Simulation Phase 1."));
wait for 100 ns;
p(Now, string'("Simulation Phase 2."));
wait for 1947 ns;
p(Now, string'("Simulation Phase 3."));
wait for 1 ns;
p(Now, string'("Simulation Phase 4."));
wait for 1 ns;
p(Now, string'("Simulation Done."));
wait;
end process;
end MODEL;
|
use std.textio.all;
entity issue308 is
generic (TIME_WIDTH : integer := 13);
end issue308;
architecture MODEL of issue308 is
begin
process
variable text_line : LINE;
procedure p(T:in time;M:in string) is
begin
if (TIME_WIDTH > 0) then
WRITE(text_line, T, RIGHT, TIME_WIDTH);
elsif (TIME_WIDTH < 0) then
WRITE(text_line, T, LEFT , -TIME_WIDTH);
end if;
WRITE(text_line, string'(" ") & M);
WRITELINE(OUTPUT, text_line);
end procedure;
begin
p(Now, string'("Simulation Start."));
wait for 100 ns;
p(Now, string'("Simulation Phase 1."));
wait for 100 ns;
p(Now, string'("Simulation Phase 2."));
wait for 1947 ns;
p(Now, string'("Simulation Phase 3."));
wait for 1 ns;
p(Now, string'("Simulation Phase 4."));
wait for 1 ns;
p(Now, string'("Simulation Done."));
wait;
end process;
end MODEL;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/18/2015 11:10:22 PM
-- Design Name:
-- Module Name: Or8Bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Or8Bit is
Port
(
InputA : in BIT_VECTOR(7 downto 0); -- 1st 8-bit input value
InputB : in BIT_VECTOR(7 downto 0); -- 2nd 8-bit input value
Output : out BIT_VECTOR(7 downto 0) -- 8-bit output value
);
end Or8Bit;
architecture Behavioral of Or8Bit is
begin
Output(0) <= InputA(0) or InputB(0);
Output(1) <= InputA(1) or InputB(1);
Output(2) <= InputA(2) or InputB(2);
Output(3) <= InputA(3) or InputB(3);
Output(4) <= InputA(4) or InputB(4);
Output(5) <= InputA(5) or InputB(5);
Output(6) <= InputA(6) or InputB(6);
Output(7) <= InputA(7) or InputB(7);
end Behavioral;
|
library verilog;
use verilog.vl_types.all;
entity finalproject_mm_interconnect_0_router_001_default_decode is
generic(
DEFAULT_CHANNEL : integer := 2;
\DEFAULT_WR_CHANNEL\: integer := -1;
\DEFAULT_RD_CHANNEL\: integer := -1;
DEFAULT_DESTID : integer := 5
);
port(
default_destination_id: out vl_logic_vector(2 downto 0);
default_wr_channel: out vl_logic_vector(5 downto 0);
default_rd_channel: out vl_logic_vector(5 downto 0);
default_src_channel: out vl_logic_vector(5 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of DEFAULT_CHANNEL : constant is 1;
attribute mti_svvh_generic_type of \DEFAULT_WR_CHANNEL\ : constant is 1;
attribute mti_svvh_generic_type of \DEFAULT_RD_CHANNEL\ : constant is 1;
attribute mti_svvh_generic_type of DEFAULT_DESTID : constant is 1;
end finalproject_mm_interconnect_0_router_001_default_decode;
|
package pack1 is
generic (n : integer);
type pt is protected
procedure get_str (s : out string);
end protected;
end package ;
package body pack1 is
constant h : string := "hello";
type pt is protected body
procedure get_str (s : out string) is
begin
s := h;
end procedure;
end protected body;
end package body;
-------------------------------------------------------------------------------
package pack2 is
procedure test;
end package;
package body pack2 is
package inst is new work.pack1 generic map (n => 5) ;
use inst.all;
shared variable p : pt;
procedure test is
variable s : string(1 to 5);
begin
p.get_str(s);
assert s = "hello";
end procedure;
end package body ;
-------------------------------------------------------------------------------
entity genpack10 is
end entity;
use work.pack2.all;
architecture aa of genpack10 is
begin
test;
end architecture;
|
-- smlttion for AMI decoder.
entity smlt_ami_dec is
end smlt_ami_dec;
architecture behaviour of smlt_ami_dec is
--data type:
component ami_dec
port (
clr_bar,
e0, e1: in bit;
s : out bit);
end component;
--binding:
for a: ami_dec use entity work.ami_dec;
--declaring the signals present in this architecture:
signal CLK, S, E0, E1, clrb: bit;
signal input0, input1: bit_vector(0 to 26);
begin --architecture.
a: ami_dec port map
( clr_bar => clrb, e0 => E0, e1 => E1, s => S );
input0 <= "000100010000100100001000010";
input1 <= "000001001000001000100000101";
process begin
clrb <= '1';
for i in 0 to 26 loop
E0 <= input0(i);
E1 <= input1(i);
CLK <= '0';
wait for 9 ns;
CLK <= '1';
wait for 1 ns;
end loop;
wait;
end process;
end behaviour;
|
-- cb20_width_adapter.vhd
-- Generated using ACDS version 13.0sp1 232 at 2016.10.12.10:12:44
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cb20_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 34;
IN_PKT_ADDR_L : integer := 18;
IN_PKT_DATA_H : integer := 15;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 17;
IN_PKT_BYTEEN_L : integer := 16;
IN_PKT_BYTE_CNT_H : integer := 43;
IN_PKT_BYTE_CNT_L : integer := 41;
IN_PKT_TRANS_COMPRESSED_READ : integer := 35;
IN_PKT_BURSTWRAP_H : integer := 44;
IN_PKT_BURSTWRAP_L : integer := 44;
IN_PKT_BURST_SIZE_H : integer := 47;
IN_PKT_BURST_SIZE_L : integer := 45;
IN_PKT_RESPONSE_STATUS_H : integer := 69;
IN_PKT_RESPONSE_STATUS_L : integer := 68;
IN_PKT_TRANS_EXCLUSIVE : integer := 40;
IN_PKT_BURST_TYPE_H : integer := 49;
IN_PKT_BURST_TYPE_L : integer := 48;
IN_ST_DATA_W : integer := 70;
OUT_PKT_ADDR_H : integer := 52;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 61;
OUT_PKT_BYTE_CNT_L : integer := 59;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 53;
OUT_PKT_BURST_SIZE_H : integer := 65;
OUT_PKT_BURST_SIZE_L : integer := 63;
OUT_PKT_RESPONSE_STATUS_H : integer := 87;
OUT_PKT_RESPONSE_STATUS_L : integer := 86;
OUT_PKT_TRANS_EXCLUSIVE : integer := 58;
OUT_PKT_BURST_TYPE_H : integer := 67;
OUT_PKT_BURST_TYPE_L : integer := 66;
OUT_ST_DATA_W : integer := 88;
ST_CHANNEL_W : integer := 7;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- clk_reset.reset
in_valid : in std_logic := '0'; -- sink.valid
in_channel : in std_logic_vector(6 downto 0) := (others => '0'); -- .channel
in_startofpacket : in std_logic := '0'; -- .startofpacket
in_endofpacket : in std_logic := '0'; -- .endofpacket
in_ready : out std_logic; -- .ready
in_data : in std_logic_vector(69 downto 0) := (others => '0'); -- .data
out_endofpacket : out std_logic; -- src.endofpacket
out_data : out std_logic_vector(87 downto 0); -- .data
out_channel : out std_logic_vector(6 downto 0); -- .channel
out_valid : out std_logic; -- .valid
out_ready : in std_logic := '0'; -- .ready
out_startofpacket : out std_logic; -- .startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => '0')
);
end entity cb20_width_adapter;
architecture rtl of cb20_width_adapter is
component altera_merlin_width_adapter is
generic (
IN_PKT_ADDR_H : integer := 60;
IN_PKT_ADDR_L : integer := 36;
IN_PKT_DATA_H : integer := 31;
IN_PKT_DATA_L : integer := 0;
IN_PKT_BYTEEN_H : integer := 35;
IN_PKT_BYTEEN_L : integer := 32;
IN_PKT_BYTE_CNT_H : integer := 63;
IN_PKT_BYTE_CNT_L : integer := 61;
IN_PKT_TRANS_COMPRESSED_READ : integer := 65;
IN_PKT_BURSTWRAP_H : integer := 67;
IN_PKT_BURSTWRAP_L : integer := 66;
IN_PKT_BURST_SIZE_H : integer := 70;
IN_PKT_BURST_SIZE_L : integer := 68;
IN_PKT_RESPONSE_STATUS_H : integer := 72;
IN_PKT_RESPONSE_STATUS_L : integer := 71;
IN_PKT_TRANS_EXCLUSIVE : integer := 73;
IN_PKT_BURST_TYPE_H : integer := 75;
IN_PKT_BURST_TYPE_L : integer := 74;
IN_ST_DATA_W : integer := 76;
OUT_PKT_ADDR_H : integer := 60;
OUT_PKT_ADDR_L : integer := 36;
OUT_PKT_DATA_H : integer := 31;
OUT_PKT_DATA_L : integer := 0;
OUT_PKT_BYTEEN_H : integer := 35;
OUT_PKT_BYTEEN_L : integer := 32;
OUT_PKT_BYTE_CNT_H : integer := 63;
OUT_PKT_BYTE_CNT_L : integer := 61;
OUT_PKT_TRANS_COMPRESSED_READ : integer := 65;
OUT_PKT_BURST_SIZE_H : integer := 68;
OUT_PKT_BURST_SIZE_L : integer := 66;
OUT_PKT_RESPONSE_STATUS_H : integer := 70;
OUT_PKT_RESPONSE_STATUS_L : integer := 69;
OUT_PKT_TRANS_EXCLUSIVE : integer := 71;
OUT_PKT_BURST_TYPE_H : integer := 73;
OUT_PKT_BURST_TYPE_L : integer := 72;
OUT_ST_DATA_W : integer := 74;
ST_CHANNEL_W : integer := 32;
OPTIMIZE_FOR_RSP : integer := 0;
RESPONSE_PATH : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
in_valid : in std_logic := 'X'; -- valid
in_channel : in std_logic_vector(6 downto 0) := (others => 'X'); -- channel
in_startofpacket : in std_logic := 'X'; -- startofpacket
in_endofpacket : in std_logic := 'X'; -- endofpacket
in_ready : out std_logic; -- ready
in_data : in std_logic_vector(69 downto 0) := (others => 'X'); -- data
out_endofpacket : out std_logic; -- endofpacket
out_data : out std_logic_vector(87 downto 0); -- data
out_channel : out std_logic_vector(6 downto 0); -- channel
out_valid : out std_logic; -- valid
out_ready : in std_logic := 'X'; -- ready
out_startofpacket : out std_logic; -- startofpacket
in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data
);
end component altera_merlin_width_adapter;
begin
width_adapter : component altera_merlin_width_adapter
generic map (
IN_PKT_ADDR_H => IN_PKT_ADDR_H,
IN_PKT_ADDR_L => IN_PKT_ADDR_L,
IN_PKT_DATA_H => IN_PKT_DATA_H,
IN_PKT_DATA_L => IN_PKT_DATA_L,
IN_PKT_BYTEEN_H => IN_PKT_BYTEEN_H,
IN_PKT_BYTEEN_L => IN_PKT_BYTEEN_L,
IN_PKT_BYTE_CNT_H => IN_PKT_BYTE_CNT_H,
IN_PKT_BYTE_CNT_L => IN_PKT_BYTE_CNT_L,
IN_PKT_TRANS_COMPRESSED_READ => IN_PKT_TRANS_COMPRESSED_READ,
IN_PKT_BURSTWRAP_H => IN_PKT_BURSTWRAP_H,
IN_PKT_BURSTWRAP_L => IN_PKT_BURSTWRAP_L,
IN_PKT_BURST_SIZE_H => IN_PKT_BURST_SIZE_H,
IN_PKT_BURST_SIZE_L => IN_PKT_BURST_SIZE_L,
IN_PKT_RESPONSE_STATUS_H => IN_PKT_RESPONSE_STATUS_H,
IN_PKT_RESPONSE_STATUS_L => IN_PKT_RESPONSE_STATUS_L,
IN_PKT_TRANS_EXCLUSIVE => IN_PKT_TRANS_EXCLUSIVE,
IN_PKT_BURST_TYPE_H => IN_PKT_BURST_TYPE_H,
IN_PKT_BURST_TYPE_L => IN_PKT_BURST_TYPE_L,
IN_ST_DATA_W => IN_ST_DATA_W,
OUT_PKT_ADDR_H => OUT_PKT_ADDR_H,
OUT_PKT_ADDR_L => OUT_PKT_ADDR_L,
OUT_PKT_DATA_H => OUT_PKT_DATA_H,
OUT_PKT_DATA_L => OUT_PKT_DATA_L,
OUT_PKT_BYTEEN_H => OUT_PKT_BYTEEN_H,
OUT_PKT_BYTEEN_L => OUT_PKT_BYTEEN_L,
OUT_PKT_BYTE_CNT_H => OUT_PKT_BYTE_CNT_H,
OUT_PKT_BYTE_CNT_L => OUT_PKT_BYTE_CNT_L,
OUT_PKT_TRANS_COMPRESSED_READ => OUT_PKT_TRANS_COMPRESSED_READ,
OUT_PKT_BURST_SIZE_H => OUT_PKT_BURST_SIZE_H,
OUT_PKT_BURST_SIZE_L => OUT_PKT_BURST_SIZE_L,
OUT_PKT_RESPONSE_STATUS_H => OUT_PKT_RESPONSE_STATUS_H,
OUT_PKT_RESPONSE_STATUS_L => OUT_PKT_RESPONSE_STATUS_L,
OUT_PKT_TRANS_EXCLUSIVE => OUT_PKT_TRANS_EXCLUSIVE,
OUT_PKT_BURST_TYPE_H => OUT_PKT_BURST_TYPE_H,
OUT_PKT_BURST_TYPE_L => OUT_PKT_BURST_TYPE_L,
OUT_ST_DATA_W => OUT_ST_DATA_W,
ST_CHANNEL_W => ST_CHANNEL_W,
OPTIMIZE_FOR_RSP => OPTIMIZE_FOR_RSP,
RESPONSE_PATH => RESPONSE_PATH
)
port map (
clk => clk, -- clk.clk
reset => reset, -- clk_reset.reset
in_valid => in_valid, -- sink.valid
in_channel => in_channel, -- .channel
in_startofpacket => in_startofpacket, -- .startofpacket
in_endofpacket => in_endofpacket, -- .endofpacket
in_ready => in_ready, -- .ready
in_data => in_data, -- .data
out_endofpacket => out_endofpacket, -- src.endofpacket
out_data => out_data, -- .data
out_channel => out_channel, -- .channel
out_valid => out_valid, -- .valid
out_ready => out_ready, -- .ready
out_startofpacket => out_startofpacket, -- .startofpacket
in_command_size_data => "000" -- (terminated)
);
end architecture rtl; -- of cb20_width_adapter
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1064.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n02i01064ent IS
END c06s04b00x00p03n02i01064ent;
ARCHITECTURE c06s04b00x00p03n02i01064arch OF c06s04b00x00p03n02i01064ent IS
BEGIN
TESTING: PROCESS
type THREE is range 1 to 3;
type ENUM1 is (EN1, EN2, EN3);
type A11 is array (THREE) of BOOLEAN;
type A32 is array (ENUM1, ENUM1) of A11;
variable V1 : BOOLEAN;
variable V32: A32 ;
BEGIN
V1 := V32(EN3)(EN2, 1); -- ONE LESS AND ONE MORE
-- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
-- INDEX POSITIONS IN TYPE DECLARATION
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n02i01064 - The expresion should be the same type as the corresponding index."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n02i01064arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1064.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n02i01064ent IS
END c06s04b00x00p03n02i01064ent;
ARCHITECTURE c06s04b00x00p03n02i01064arch OF c06s04b00x00p03n02i01064ent IS
BEGIN
TESTING: PROCESS
type THREE is range 1 to 3;
type ENUM1 is (EN1, EN2, EN3);
type A11 is array (THREE) of BOOLEAN;
type A32 is array (ENUM1, ENUM1) of A11;
variable V1 : BOOLEAN;
variable V32: A32 ;
BEGIN
V1 := V32(EN3)(EN2, 1); -- ONE LESS AND ONE MORE
-- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
-- INDEX POSITIONS IN TYPE DECLARATION
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n02i01064 - The expresion should be the same type as the corresponding index."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n02i01064arch;
|
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