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`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16672)
`protect data_block
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16672)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16672)
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16672)
`protect data_block
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|
`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16672)
`protect data_block
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08NaenNvtN/WUzttt3SLh/Jo00f1mI8NrTXLwQ==
`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
entity xp is port
(
ri : in std_logic_vector(1 TO 32);
e : out std_logic_vector(1 TO 48));
end xp;
architecture behavior of xp is
begin
e(1)<=ri(32);e(2)<=ri(1); e(3)<=ri(2); e(4)<=ri(3); e(5)<=ri(4); e(6)<=ri(5);
e(7)<=ri(4); e(8)<=ri(5); e(9)<=ri(6); e(10)<=ri(7); e(11)<=ri(8);e(12)<=ri(9);
e(13)<=ri(8); e(14)<=ri(9);e(15)<=ri(10); e(16)<=ri(11); e(17)<=ri(12); e(18)<=ri(13);
e(19)<=ri(12); e(20)<=ri(13); e(21)<=ri(14); e(22)<=ri(15); e(23)<=ri(16); e(24)<=ri(17);
e(25)<=ri(16); e(26)<=ri(17); e(27)<=ri(18); e(28)<=ri(19); e(29)<=ri(20); e(30)<=ri(21);
e(31)<=ri(20); e(32)<=ri(21); e(33)<=ri(22); e(34)<=ri(23); e(35)<=ri(24); e(36)<=ri(25);
e(37)<=ri(24); e(38)<=ri(25); e(39)<=ri(26); e(40)<=ri(27); e(41)<=ri(28); e(42)<=ri(29);
e(43)<=ri(28); e(44)<=ri(29); e(45)<=ri(30); e(46)<=ri(31); e(47)<=ri(32); e(48)<=ri(1);
end behavior;
|
library ieee;
use ieee.std_logic_1164.all;
entity xp is port
(
ri : in std_logic_vector(1 TO 32);
e : out std_logic_vector(1 TO 48));
end xp;
architecture behavior of xp is
begin
e(1)<=ri(32);e(2)<=ri(1); e(3)<=ri(2); e(4)<=ri(3); e(5)<=ri(4); e(6)<=ri(5);
e(7)<=ri(4); e(8)<=ri(5); e(9)<=ri(6); e(10)<=ri(7); e(11)<=ri(8);e(12)<=ri(9);
e(13)<=ri(8); e(14)<=ri(9);e(15)<=ri(10); e(16)<=ri(11); e(17)<=ri(12); e(18)<=ri(13);
e(19)<=ri(12); e(20)<=ri(13); e(21)<=ri(14); e(22)<=ri(15); e(23)<=ri(16); e(24)<=ri(17);
e(25)<=ri(16); e(26)<=ri(17); e(27)<=ri(18); e(28)<=ri(19); e(29)<=ri(20); e(30)<=ri(21);
e(31)<=ri(20); e(32)<=ri(21); e(33)<=ri(22); e(34)<=ri(23); e(35)<=ri(24); e(36)<=ri(25);
e(37)<=ri(24); e(38)<=ri(25); e(39)<=ri(26); e(40)<=ri(27); e(41)<=ri(28); e(42)<=ri(29);
e(43)<=ri(28); e(44)<=ri(29); e(45)<=ri(30); e(46)<=ri(31); e(47)<=ri(32); e(48)<=ri(1);
end behavior;
|
-------------------------------------------------------------------
-- TITLE: NoC_Node
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 4/21/01
-- ORIGNAL FILENAME: tbench.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity provides a simple NoC node with plasma as its processor
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
use ieee.std_logic_unsigned.all;
entity NoC_Node is
generic( current_address : integer := 0;
stim_file: string :="code.txt";
mem_address_width : natural := 16;
log_file : string := "output.txt";
memory_type : string :=
"TRI_PORT_X"
-- "DUAL_PORT_"
-- "ALTERA_LPM"
-- "XILINX_16X"
);
port( reset : in std_logic;
clk : in std_logic;
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0)
);
end; --entity NoC_Node
architecture messed_up of NoC_Node is
signal interrupt : std_logic := '0';
signal mem_write : std_logic;
signal address : std_logic_vector(31 downto 2);
signal data_write : std_logic_vector(31 downto 0);
signal data_read : std_logic_vector(31 downto 0);
signal pause1 : std_logic := '0';
signal pause2 : std_logic := '0';
signal pause : std_logic;
signal no_ddr_start: std_logic;
signal no_ddr_stop : std_logic;
signal byte_we : std_logic_vector(3 downto 0);
signal uart_write : std_logic;
signal gpioA_in : std_logic_vector(31 downto 0) := (others => '0');
--signal credit_in, valid_in: std_logic := '0';
--signal credit_out, valid_out: std_logic := '0';
--signal RX: std_logic_vector(31 downto 0) := (others => '0');
--signal TX: std_logic_vector(31 downto 0) := (others => '0');
-- signal credit_counter_out_0: std_logic_vector (1 downto 0);
begin --architecture
--pause1 <= '1' after 700 ns when pause1 = '0' else '0' after 200 ns;
pause1 <= '0';
--pause2 <= '1' after 300 ns when pause2 = '0' else '0' after 200 ns;
pause2 <= '0';
pause <= pause1 or pause2;
--gpioA_in(20) <= not gpioA_in(20) after 200 ns; --E_RX_CLK
--gpioA_in(19) <= not gpioA_in(19) after 20 us; --E_RX_DV
--gpioA_in(18 downto 15) <= gpioA_in(18 downto 15) + 1 after 400 ns; --E_RX_RXD
--gpioA_in(14) <= not gpioA_in(14) after 200 ns; --E_TX_CLK
u1_plasma: plasma
generic map (memory_type => memory_type,
ethernet => '0',
use_cache => '0',
log_file => log_file,
current_address => current_address,
stim_file => stim_file)
PORT MAP (
clk => clk,
reset => reset,
uart_read => uart_write,
uart_write => uart_write,
address => address,
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
mem_pause_in => pause,
no_ddr_start => no_ddr_start,
no_ddr_stop => no_ddr_stop,
gpio0_out => open,
gpioA_in => gpioA_in,
credit_in => credit_in,
valid_out => valid_out,
TX => TX,
credit_out => credit_out,
valid_in => valid_in,
RX => RX
);
memory_impl: memory
generic map (address_width => mem_address_width)
port map (
clk => clk,
address => address,
data_write => data_write,
pause => pause,
byte_we => byte_we,
data_read => data_read
);
end; --architecture logic
|
-------------------------------------------------------------------
-- TITLE: NoC_Node
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 4/21/01
-- ORIGNAL FILENAME: tbench.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity provides a simple NoC node with plasma as its processor
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
use ieee.std_logic_unsigned.all;
entity NoC_Node is
generic( current_address : integer := 0;
stim_file: string :="code.txt";
mem_address_width : natural := 16;
log_file : string := "output.txt";
memory_type : string :=
"TRI_PORT_X"
-- "DUAL_PORT_"
-- "ALTERA_LPM"
-- "XILINX_16X"
);
port( reset : in std_logic;
clk : in std_logic;
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0)
);
end; --entity NoC_Node
architecture messed_up of NoC_Node is
signal interrupt : std_logic := '0';
signal mem_write : std_logic;
signal address : std_logic_vector(31 downto 2);
signal data_write : std_logic_vector(31 downto 0);
signal data_read : std_logic_vector(31 downto 0);
signal pause1 : std_logic := '0';
signal pause2 : std_logic := '0';
signal pause : std_logic;
signal no_ddr_start: std_logic;
signal no_ddr_stop : std_logic;
signal byte_we : std_logic_vector(3 downto 0);
signal uart_write : std_logic;
signal gpioA_in : std_logic_vector(31 downto 0) := (others => '0');
--signal credit_in, valid_in: std_logic := '0';
--signal credit_out, valid_out: std_logic := '0';
--signal RX: std_logic_vector(31 downto 0) := (others => '0');
--signal TX: std_logic_vector(31 downto 0) := (others => '0');
-- signal credit_counter_out_0: std_logic_vector (1 downto 0);
begin --architecture
--pause1 <= '1' after 700 ns when pause1 = '0' else '0' after 200 ns;
pause1 <= '0';
--pause2 <= '1' after 300 ns when pause2 = '0' else '0' after 200 ns;
pause2 <= '0';
pause <= pause1 or pause2;
--gpioA_in(20) <= not gpioA_in(20) after 200 ns; --E_RX_CLK
--gpioA_in(19) <= not gpioA_in(19) after 20 us; --E_RX_DV
--gpioA_in(18 downto 15) <= gpioA_in(18 downto 15) + 1 after 400 ns; --E_RX_RXD
--gpioA_in(14) <= not gpioA_in(14) after 200 ns; --E_TX_CLK
u1_plasma: plasma
generic map (memory_type => memory_type,
ethernet => '0',
use_cache => '0',
log_file => log_file,
current_address => current_address,
stim_file => stim_file)
PORT MAP (
clk => clk,
reset => reset,
uart_read => uart_write,
uart_write => uart_write,
address => address,
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
mem_pause_in => pause,
no_ddr_start => no_ddr_start,
no_ddr_stop => no_ddr_stop,
gpio0_out => open,
gpioA_in => gpioA_in,
credit_in => credit_in,
valid_out => valid_out,
TX => TX,
credit_out => credit_out,
valid_in => valid_in,
RX => RX
);
memory_impl: memory
generic map (address_width => mem_address_width)
port map (
clk => clk,
address => address,
data_write => data_write,
pause => pause,
byte_we => byte_we,
data_read => data_read
);
end; --architecture logic
|
-------------------------------------------------------------------
-- TITLE: NoC_Node
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 4/21/01
-- ORIGNAL FILENAME: tbench.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity provides a simple NoC node with plasma as its processor
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
use ieee.std_logic_unsigned.all;
entity NoC_Node is
generic( current_address : integer := 0;
stim_file: string :="code.txt";
mem_address_width : natural := 16;
log_file : string := "output.txt";
memory_type : string :=
"TRI_PORT_X"
-- "DUAL_PORT_"
-- "ALTERA_LPM"
-- "XILINX_16X"
);
port( reset : in std_logic;
clk : in std_logic;
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0)
);
end; --entity NoC_Node
architecture messed_up of NoC_Node is
signal interrupt : std_logic := '0';
signal mem_write : std_logic;
signal address : std_logic_vector(31 downto 2);
signal data_write : std_logic_vector(31 downto 0);
signal data_read : std_logic_vector(31 downto 0);
signal pause1 : std_logic := '0';
signal pause2 : std_logic := '0';
signal pause : std_logic;
signal no_ddr_start: std_logic;
signal no_ddr_stop : std_logic;
signal byte_we : std_logic_vector(3 downto 0);
signal uart_write : std_logic;
signal gpioA_in : std_logic_vector(31 downto 0) := (others => '0');
--signal credit_in, valid_in: std_logic := '0';
--signal credit_out, valid_out: std_logic := '0';
--signal RX: std_logic_vector(31 downto 0) := (others => '0');
--signal TX: std_logic_vector(31 downto 0) := (others => '0');
-- signal credit_counter_out_0: std_logic_vector (1 downto 0);
begin --architecture
--pause1 <= '1' after 700 ns when pause1 = '0' else '0' after 200 ns;
pause1 <= '0';
--pause2 <= '1' after 300 ns when pause2 = '0' else '0' after 200 ns;
pause2 <= '0';
pause <= pause1 or pause2;
--gpioA_in(20) <= not gpioA_in(20) after 200 ns; --E_RX_CLK
--gpioA_in(19) <= not gpioA_in(19) after 20 us; --E_RX_DV
--gpioA_in(18 downto 15) <= gpioA_in(18 downto 15) + 1 after 400 ns; --E_RX_RXD
--gpioA_in(14) <= not gpioA_in(14) after 200 ns; --E_TX_CLK
u1_plasma: plasma
generic map (memory_type => memory_type,
ethernet => '0',
use_cache => '0',
log_file => log_file,
current_address => current_address,
stim_file => stim_file)
PORT MAP (
clk => clk,
reset => reset,
uart_read => uart_write,
uart_write => uart_write,
address => address,
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
mem_pause_in => pause,
no_ddr_start => no_ddr_start,
no_ddr_stop => no_ddr_stop,
gpio0_out => open,
gpioA_in => gpioA_in,
credit_in => credit_in,
valid_out => valid_out,
TX => TX,
credit_out => credit_out,
valid_in => valid_in,
RX => RX
);
memory_impl: memory
generic map (address_width => mem_address_width)
port map (
clk => clk,
address => address,
data_write => data_write,
pause => pause,
byte_we => byte_we,
data_read => data_read
);
end; --architecture logic
|
-- $Id: sys_tst_serloop2_n3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_serloop2_n3 - syn
-- Description: Tester serial link for nexys3
--
-- Dependencies: vlib/xlib/dcm_sfs
-- genlib/clkdivce
-- bpgen/bp_rs232_2l4l_iob
-- bpgen/sn_humanio
-- tst_serloop_hiomap
-- vlib/serport/serport_2clock
-- tst_serloop
-- vlib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-11-27 433 13.1 O40d xc6slx16-2 486 652 59 237 t 6.3
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-11 438 1.0.2 add dcm monitor hack; use with ser=usr=100 MHz
-- 2011-12-09 437 1.0.1 rename serport stat->moni port
-- 2011-11-27 433 1.0 Initial version
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_serlooplib.all;
use work.serportlib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_serloop2_n3 is -- top level
-- implements nexys3_fusp_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end sys_tst_serloop2_n3;
architecture syn of sys_tst_serloop2_n3 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal RXD : slbit := '0';
signal TXD : slbit := '0';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal LED_OUT : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXHOLD : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal SER_MONI : serport_moni_type := serport_moni_init;
-- some signals for dcm monitor hack
signal LOCKED_DCMU : slbit := '0';
signal LOCKED_DCMS : slbit := '0';
signal R_MSECU_CNT : slv10 := (others=>'0');
signal R_MSECS_CNT : slv10 := (others=>'0');
begin
DCM_U : dcm_sfs
generic map (
CLKFX_DIVIDE => 1, -- was 2
CLKFX_MULTIPLY => 1, -- was 3
CLKIN_PERIOD => 10.0)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => LOCKED_DCMU
);
CLKDIV_U : clkdivce
generic map (
CDUWIDTH => 8,
USECDIV => sys_conf_clkudiv_usecdiv, -- syn: 150 sim: 30
MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
port map (
CLK => CLK,
CE_USEC => open,
CE_MSEC => CE_MSEC
);
DCM_S : dcm_sfs
generic map (
CLKFX_DIVIDE => 1, -- was 5
CLKFX_MULTIPLY => 1, -- was 3
CLKIN_PERIOD => 10.0)
port map (
CLKIN => I_CLK100,
CLKFX => CLKS,
LOCKED => LOCKED_DCMS
);
CLKDIV_S : clkdivce
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksdiv_usecdiv, -- syn: 60 sim: 12
MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5
port map (
CLK => CLKS,
CE_USEC => open,
CE_MSEC => CES_MSEC
);
HIO : sn_humanio
generic map (
BWIDTH => 5,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED_OUT,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_serloop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
SWI => SWI,
BTN => BTN(3 downto 0),
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
IOB_RS232 : bp_rs232_2l4l_iob
port map (
CLK => CLKS,
RESET => '0',
SEL => SWI(0), -- port selection
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD0 => I_RXD,
O_TXD0 => O_TXD,
I_RXD1 => I_FUSP_RXD,
O_TXD1 => O_FUSP_TXD,
I_CTS1_N => I_FUSP_CTS_N,
O_RTS1_N => O_FUSP_RTS_N
);
SERPORT : serport_2clock
generic map (
CDWIDTH => 15,
CDINIT => sys_conf_uart_cdinit,
RXFAWIDTH => 5,
TXFAWIDTH => 5)
port map (
CLKU => CLK,
RESET => RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => HIO_CNTL.enaxon,
ENAESC => HIO_CNTL.enaesc,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
MONI => SER_MONI,
RXSD => RXD,
TXSD => TXD,
RXRTS_N => RTS_N,
TXCTS_N => CTS_N
);
TESTER : tst_serloop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
SER_MONI => SER_MONI,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXHOLD => RXHOLD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
-- this is a hack to monitor the two dcm's
proc_msecu: process (CLK)
begin
if rising_edge(CLK) then
if CE_MSEC = '1' then
R_MSECU_CNT <= slv(unsigned(R_MSECU_CNT) + 1);
end if;
end if;
end process proc_msecu;
proc_msecs: process (CLKS)
begin
if rising_edge(CLKS) then
if CES_MSEC = '1' then
R_MSECS_CNT <= slv(unsigned(R_MSECS_CNT) + 1);
end if;
end if;
end process proc_msecs;
LED_OUT(7) <= R_MSECU_CNT(9) or (not LOCKED_DCMU);
LED_OUT(6) <= R_MSECS_CNT(9) or (not LOCKED_DCMS);
LED_OUT(5 downto 0) <= LED(5 downto 0);
end syn;
|
-- A RAM initialized with an external file
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use STD.textio.all;
entity ram is
port(
clk_i : in std_logic;
we_i : in std_logic;
addr_i : in std_logic_vector(5 downto 0);
data_i : in std_logic_vector(31 downto 0);
data_o : out std_logic_vector(31 downto 0)
);
end ram;
architecture RTL of ram is
type mem_t is array (0 to 63) of bit_vector(31 downto 0);
impure function init(filename : in string) return mem_t is
file fh : text is in filename;
variable l : line;
variable mem : mem_t;
begin
for i in mem_t'range loop
readline(fh, l);
read(l, mem(i));
end loop;
return mem;
end function;
signal ram : mem_t := init("data/memory.dat");
begin
memory:
process(clk_i)
begin
if rising_edge(clk_i) then
if we_i = '1' then
ram(to_integer(unsigned(addr_i))) <= to_bitvector(data_i);
end if;
data_o <= to_stdlogicvector(ram(to_integer(unsigned(addr_i))));
end if;
end process;
end architecture RTL;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:37:01 10/06/2010
-- Design Name:
-- Module Name: DecBCD7Seg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DecBCD7Seg is
port (
BCD : in STD_LOGIC_VECTOR (3 downto 0);
Seg : out STD_LOGIC_VECTOR (7 downto 0));
end DecBCD7Seg;
architecture Behavioral of DecBCD7Seg is
begin
--Implementacion de un decodificador Binario a 7 segmentos que tambien sirve como
--Decodificador BCD a 7 segmentos
--Los segmentos encienden con un 0 logico, se apagan con un 1 logico
with BCD select
-- .gfedcba
Seg <= X"C0" when X"0",
X"F9" when X"1",
X"A4" when X"2",
X"B0" when X"3",
X"99" when X"4",
X"92" when X"5",
X"82" when X"6",
X"F8" when X"7",
X"80" when X"8",
X"90" when X"9",
X"88" when X"A",
X"83" when X"B",
X"C6" when X"C",
X"A1" when X"D",
X"86" when X"E",
X"8E" when X"F",
X"FF" when others;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:37:01 10/06/2010
-- Design Name:
-- Module Name: DecBCD7Seg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DecBCD7Seg is
port (
BCD : in STD_LOGIC_VECTOR (3 downto 0);
Seg : out STD_LOGIC_VECTOR (7 downto 0));
end DecBCD7Seg;
architecture Behavioral of DecBCD7Seg is
begin
--Implementacion de un decodificador Binario a 7 segmentos que tambien sirve como
--Decodificador BCD a 7 segmentos
--Los segmentos encienden con un 0 logico, se apagan con un 1 logico
with BCD select
-- .gfedcba
Seg <= X"C0" when X"0",
X"F9" when X"1",
X"A4" when X"2",
X"B0" when X"3",
X"99" when X"4",
X"92" when X"5",
X"82" when X"6",
X"F8" when X"7",
X"80" when X"8",
X"90" when X"9",
X"88" when X"A",
X"83" when X"B",
X"C6" when X"C",
X"A1" when X"D",
X"86" when X"E",
X"8E" when X"F",
X"FF" when others;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:37:01 10/06/2010
-- Design Name:
-- Module Name: DecBCD7Seg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DecBCD7Seg is
port (
BCD : in STD_LOGIC_VECTOR (3 downto 0);
Seg : out STD_LOGIC_VECTOR (7 downto 0));
end DecBCD7Seg;
architecture Behavioral of DecBCD7Seg is
begin
--Implementacion de un decodificador Binario a 7 segmentos que tambien sirve como
--Decodificador BCD a 7 segmentos
--Los segmentos encienden con un 0 logico, se apagan con un 1 logico
with BCD select
-- .gfedcba
Seg <= X"C0" when X"0",
X"F9" when X"1",
X"A4" when X"2",
X"B0" when X"3",
X"99" when X"4",
X"92" when X"5",
X"82" when X"6",
X"F8" when X"7",
X"80" when X"8",
X"90" when X"9",
X"88" when X"A",
X"83" when X"B",
X"C6" when X"C",
X"A1" when X"D",
X"86" when X"E",
X"8E" when X"F",
X"FF" when others;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:37:01 10/06/2010
-- Design Name:
-- Module Name: DecBCD7Seg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DecBCD7Seg is
port (
BCD : in STD_LOGIC_VECTOR (3 downto 0);
Seg : out STD_LOGIC_VECTOR (7 downto 0));
end DecBCD7Seg;
architecture Behavioral of DecBCD7Seg is
begin
--Implementacion de un decodificador Binario a 7 segmentos que tambien sirve como
--Decodificador BCD a 7 segmentos
--Los segmentos encienden con un 0 logico, se apagan con un 1 logico
with BCD select
-- .gfedcba
Seg <= X"C0" when X"0",
X"F9" when X"1",
X"A4" when X"2",
X"B0" when X"3",
X"99" when X"4",
X"92" when X"5",
X"82" when X"6",
X"F8" when X"7",
X"80" when X"8",
X"90" when X"9",
X"88" when X"A",
X"83" when X"B",
X"C6" when X"C",
X"A1" when X"D",
X"86" when X"E",
X"8E" when X"F",
X"FF" when others;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:37:01 10/06/2010
-- Design Name:
-- Module Name: DecBCD7Seg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DecBCD7Seg is
port (
BCD : in STD_LOGIC_VECTOR (3 downto 0);
Seg : out STD_LOGIC_VECTOR (7 downto 0));
end DecBCD7Seg;
architecture Behavioral of DecBCD7Seg is
begin
--Implementacion de un decodificador Binario a 7 segmentos que tambien sirve como
--Decodificador BCD a 7 segmentos
--Los segmentos encienden con un 0 logico, se apagan con un 1 logico
with BCD select
-- .gfedcba
Seg <= X"C0" when X"0",
X"F9" when X"1",
X"A4" when X"2",
X"B0" when X"3",
X"99" when X"4",
X"92" when X"5",
X"82" when X"6",
X"F8" when X"7",
X"80" when X"8",
X"90" when X"9",
X"88" when X"A",
X"83" when X"B",
X"C6" when X"C",
X"A1" when X"D",
X"86" when X"E",
X"8E" when X"F",
X"FF" when others;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:37:01 10/06/2010
-- Design Name:
-- Module Name: DecBCD7Seg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DecBCD7Seg is
port (
BCD : in STD_LOGIC_VECTOR (3 downto 0);
Seg : out STD_LOGIC_VECTOR (7 downto 0));
end DecBCD7Seg;
architecture Behavioral of DecBCD7Seg is
begin
--Implementacion de un decodificador Binario a 7 segmentos que tambien sirve como
--Decodificador BCD a 7 segmentos
--Los segmentos encienden con un 0 logico, se apagan con un 1 logico
with BCD select
-- .gfedcba
Seg <= X"C0" when X"0",
X"F9" when X"1",
X"A4" when X"2",
X"B0" when X"3",
X"99" when X"4",
X"92" when X"5",
X"82" when X"6",
X"F8" when X"7",
X"80" when X"8",
X"90" when X"9",
X"88" when X"A",
X"83" when X"B",
X"C6" when X"C",
X"A1" when X"D",
X"86" when X"E",
X"8E" when X"F",
X"FF" when others;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:37:01 10/06/2010
-- Design Name:
-- Module Name: DecBCD7Seg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DecBCD7Seg is
port (
BCD : in STD_LOGIC_VECTOR (3 downto 0);
Seg : out STD_LOGIC_VECTOR (7 downto 0));
end DecBCD7Seg;
architecture Behavioral of DecBCD7Seg is
begin
--Implementacion de un decodificador Binario a 7 segmentos que tambien sirve como
--Decodificador BCD a 7 segmentos
--Los segmentos encienden con un 0 logico, se apagan con un 1 logico
with BCD select
-- .gfedcba
Seg <= X"C0" when X"0",
X"F9" when X"1",
X"A4" when X"2",
X"B0" when X"3",
X"99" when X"4",
X"92" when X"5",
X"82" when X"6",
X"F8" when X"7",
X"80" when X"8",
X"90" when X"9",
X"88" when X"A",
X"83" when X"B",
X"C6" when X"C",
X"A1" when X"D",
X"86" when X"E",
X"8E" when X"F",
X"FF" when others;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:37:01 10/06/2010
-- Design Name:
-- Module Name: DecBCD7Seg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DecBCD7Seg is
port (
BCD : in STD_LOGIC_VECTOR (3 downto 0);
Seg : out STD_LOGIC_VECTOR (7 downto 0));
end DecBCD7Seg;
architecture Behavioral of DecBCD7Seg is
begin
--Implementacion de un decodificador Binario a 7 segmentos que tambien sirve como
--Decodificador BCD a 7 segmentos
--Los segmentos encienden con un 0 logico, se apagan con un 1 logico
with BCD select
-- .gfedcba
Seg <= X"C0" when X"0",
X"F9" when X"1",
X"A4" when X"2",
X"B0" when X"3",
X"99" when X"4",
X"92" when X"5",
X"82" when X"6",
X"F8" when X"7",
X"80" when X"8",
X"90" when X"9",
X"88" when X"A",
X"83" when X"B",
X"C6" when X"C",
X"A1" when X"D",
X"86" when X"E",
X"8E" when X"F",
X"FF" when others;
end Behavioral;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal sys_clk : std_logic := '0';
signal sysace_clk : std_logic := '0';
signal sys_rst_in : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal errorn : std_logic;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(15 downto 0);
signal xdata : std_logic_vector(31 downto 0);
signal romsn : std_logic;
signal iosn : std_ulogic;
signal writen, read : std_ulogic;
signal oen : std_ulogic;
signal flash_rstn : std_logic;
signal ddr_clk : std_logic_vector(2 downto 0);
signal ddr_clkb : std_logic_vector(2 downto 0);
signal ddr_clk_fb : std_logic;
signal ddr_clk_fb_out : std_logic;
signal ddr_cke : std_logic_vector(1 downto 0);
signal ddr_csb : std_logic_vector(1 downto 0);
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (7 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (7 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (13 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (63 downto 0); -- ddr data
signal txd1 : std_logic; -- UART1 tx data
signal rxd1 : std_logic; -- UART1 rx data
signal gpio : std_logic_vector(31 downto 0); -- I/O port
signal flash_cex : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
signal emdc, emdio, eresetn : std_logic;
signal etx_slew : std_logic_vector(1 downto 0);
signal leds : std_logic_vector(1 downto 0);
signal vid_clock : std_ulogic;
signal vid_blankn : std_ulogic;
signal vid_syncn : std_ulogic;
signal vid_hsync : std_ulogic;
signal vid_vsync : std_ulogic;
signal vid_r : std_logic_vector(7 downto 0);
signal vid_g : std_logic_vector(7 downto 0);
signal vid_b : std_logic_vector(7 downto 0);
signal ps2clk : std_logic_vector(1 downto 0);
signal ps2data : std_logic_vector(1 downto 0);
signal cf_mpa : std_logic_vector(6 downto 0);
signal cf_mpd : std_logic_vector(15 downto 0);
signal cf_mp_ce_z : std_ulogic;
signal cf_mp_oe_z : std_ulogic;
signal cf_mp_we_z : std_ulogic;
signal cf_mpirq : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
constant lresp : boolean := false;
signal dsuen : std_ulogic;
signal dsubre : std_ulogic;
signal dsuact : std_ulogic;
begin
-- clock and reset
sys_clk <= not sys_clk after ct * 1 ns;
sysace_clk <= not sysace_clk after 15 ns;
sys_rst_in <= '0', '1' after 200 ns;
rxd1 <= 'H'; errorn <= 'H'; dsuen <= '0'; dsubre <= 'H';
ddr_clk_fb <= ddr_clk_fb_out; rxd1 <= txd1;
cf_mpd <= (others => 'H'); cf_mpirq <= 'L';
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, ncpu, disas, dbguart, pclow )
port map ( sys_rst_in, sys_clk, sysace_clk, errorn, dsuen, dsubre, dsuact,
ddr_clk, ddr_clkb, ddr_clk_fb, ddr_clk_fb_out, ddr_cke, ddr_csb,
ddr_web, ddr_rasb, ddr_casb, ddr_dm, ddr_dqs, ddr_ad, ddr_ba, ddr_dq,
rxd1, txd1, leds(0), leds(1),
-- gpio,
emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
etxd, etx_en, etx_er, emdc, eresetn, etx_slew, ps2clk, ps2data,
vid_clock, vid_blankn, vid_syncn, vid_hsync, vid_vsync,
vid_r, vid_g, vid_b,
cf_mpa, cf_mpd, cf_mp_ce_z, cf_mp_oe_z, cf_mp_we_z, cf_mpirq
);
ddrmem : for i in 0 to 1 generate
-- u3 : mt46v16m16
-- generic map (index => 3, fname => sdramfile, bbits => 64)
-- PORT MAP(
-- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i),
-- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(1 downto 0));
-- u2 : mt46v16m16
-- generic map (index => 2, fname => sdramfile, bbits => 64)
-- PORT MAP(
-- Dq => ddr_dq(31 downto 16), Dqs => ddr_dqs(3 downto 2), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i),
-- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(3 downto 2));
-- u1 : mt46v16m16
-- generic map (index => 1, fname => sdramfile, bbits => 64)
-- PORT MAP(
-- Dq => ddr_dq(47 downto 32), Dqs => ddr_dqs(5 downto 4), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i),
-- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(5 downto 4));
-- u0 : mt46v16m16
-- generic map (index => 0, fname => sdramfile, bbits => 64)
-- PORT MAP(
-- Dq => ddr_dq(63 downto 48), Dqs => ddr_dqs(7 downto 6), Addr => ddr_ad(12 downto 0),
-- Ba => ddr_ba, Clk => ddr_clk(i), Clk_n => ddr_clkb(i), Cke => ddr_cke(i),
-- Cs_n => ddr_csb(i), Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(7 downto 6));
ddr0 : ddrram
generic map(width => 64, abits => 14, colbits => 9, rowbits => 14,
implbanks => 1, fname => sdramfile, speedbin => 1, density => 1)
port map (ck => ddr_clk(i), cke => ddr_cke(i), csn => ddr_csb(i),
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq,
dqs => ddr_dqs);
end generate;
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data,
gnd, gnd, romsn, writen, oen);
iuerr : process
begin
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
xdata <= "0000000000000000" & data;
test0 : grtestmod
port map ( sys_rst_in, sys_clk, errorn, address(20 downto 1), xdata,
iosn, oen, writen, open);
data <= buskeep(data), (others => 'H') after 250 ns;
ddr_dq <= buskeep(ddr_dq), (others => 'H') after 250 ns;
end ;
|
-------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
-- Generic counter module
--
-- $Id: spi_counter.vhd,v 1.2 2007/02/25 18:24:12 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger ([email protected])
--
-- All rights reserved, see COPYING.
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity spi_counter is
generic (
cnt_width_g : integer := 4;
cnt_max_g : integer := 15
);
port (
clk_i : in std_logic;
reset_i : in boolean;
cnt_en_i : in boolean;
cnt_o : out std_logic_vector(cnt_width_g-1 downto 0);
cnt_ovfl_o : out boolean
);
end spi_counter;
library ieee;
use ieee.numeric_std.all;
use work.spi_boot_pack.all;
architecture rtl of spi_counter is
signal cnt_q : unsigned(cnt_width_g-1 downto 0);
signal cnt_ovfl_s : boolean;
begin
cnt: process (clk_i, reset_i)
begin
if reset_i then
cnt_q <= (others => '0');
elsif clk_i'event and clk_i = '1' then
if cnt_en_i then
if not cnt_ovfl_s then
cnt_q <= cnt_q + 1;
else
cnt_q <= (others => '0');
end if;
end if;
end if;
end process cnt;
cnt_ovfl_s <= cnt_q = cnt_max_g;
-----------------------------------------------------------------------------
-- Output Mapping
-----------------------------------------------------------------------------
cnt_ovfl_o <= cnt_ovfl_s;
cnt_o <= std_logic_vector(cnt_q);
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: spi_counter.vhd,v $
-- Revision 1.2 2007/02/25 18:24:12 arniml
-- fix type handling of resets
--
-- Revision 1.1 2005/02/08 20:41:33 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc398.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p07n01i00398ent IS
END c03s02b01x01p07n01i00398ent;
ARCHITECTURE c03s02b01x01p07n01i00398arch OF c03s02b01x01p07n01i00398ent IS
constant X : BIT_VECTOR := "0101";
BEGIN
TESTING: PROCESS
variable i : integer;
BEGIN
i := X'length;
assert NOT(i=4)
report "***PASSED TEST: c03s02b01x01p07n01i00398"
severity NOTE;
assert (i=4)
report "***FAILED TEST: c03s02b01x01p07n01i00398 - For a constant declared by an object declaration, the index ranges are defined by the initial value, if the subtype of the constant is unconstrained."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p07n01i00398arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc398.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p07n01i00398ent IS
END c03s02b01x01p07n01i00398ent;
ARCHITECTURE c03s02b01x01p07n01i00398arch OF c03s02b01x01p07n01i00398ent IS
constant X : BIT_VECTOR := "0101";
BEGIN
TESTING: PROCESS
variable i : integer;
BEGIN
i := X'length;
assert NOT(i=4)
report "***PASSED TEST: c03s02b01x01p07n01i00398"
severity NOTE;
assert (i=4)
report "***FAILED TEST: c03s02b01x01p07n01i00398 - For a constant declared by an object declaration, the index ranges are defined by the initial value, if the subtype of the constant is unconstrained."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p07n01i00398arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc398.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p07n01i00398ent IS
END c03s02b01x01p07n01i00398ent;
ARCHITECTURE c03s02b01x01p07n01i00398arch OF c03s02b01x01p07n01i00398ent IS
constant X : BIT_VECTOR := "0101";
BEGIN
TESTING: PROCESS
variable i : integer;
BEGIN
i := X'length;
assert NOT(i=4)
report "***PASSED TEST: c03s02b01x01p07n01i00398"
severity NOTE;
assert (i=4)
report "***FAILED TEST: c03s02b01x01p07n01i00398 - For a constant declared by an object declaration, the index ranges are defined by the initial value, if the subtype of the constant is unconstrained."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p07n01i00398arch;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Toplevel
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: ALU top level
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
entity ALU is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (7 downto 0);
RB : in STD_LOGIC_VECTOR (7 downto 0);
OPCODE : in STD_LOGIC_VECTOR (3 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
LDST_OUT : out STD_LOGIC_VECTOR (7 downto 0));
end ALU;
architecture Structural of ALU is
signal arith : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal logic : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal shift : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal memory : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal ccr_arith : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal ccr_logic : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
LDST_OUT <= memory;
Arith_Unit: entity work.Arith_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_arith,
RESULT => arith);
Logic_Unit: entity work.Logic_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_logic,
RESULT => logic);
shift_unit: entity work.alu_shift_unit
port map( A => RA,
COUNT => RB(2 downto 0),
OP => opcode(3),
RESULT => shift);
Load_Store_Unit: entity work.Load_Store_Unit
port map( CLK => CLK,
A => RA,
IMMED => RB,
OP => opcode,
RESULT => memory);
ALU_Mux: entity work.ALU_Mux
port map( OP => opcode,
ARITH => arith,
LOGIC => logic,
SHIFT => shift,
MEMORY => memory,
CCR_ARITH => ccr_arith,
CCR_LOGIC => ccr_logic,
ALU_OUT => ALU_OUT,
CCR_OUT => CCR);
end Structural;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Toplevel
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: ALU top level
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
entity ALU is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (7 downto 0);
RB : in STD_LOGIC_VECTOR (7 downto 0);
OPCODE : in STD_LOGIC_VECTOR (3 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
LDST_OUT : out STD_LOGIC_VECTOR (7 downto 0));
end ALU;
architecture Structural of ALU is
signal arith : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal logic : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal shift : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal memory : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal ccr_arith : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal ccr_logic : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
LDST_OUT <= memory;
Arith_Unit: entity work.Arith_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_arith,
RESULT => arith);
Logic_Unit: entity work.Logic_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_logic,
RESULT => logic);
shift_unit: entity work.alu_shift_unit
port map( A => RA,
COUNT => RB(2 downto 0),
OP => opcode(3),
RESULT => shift);
Load_Store_Unit: entity work.Load_Store_Unit
port map( CLK => CLK,
A => RA,
IMMED => RB,
OP => opcode,
RESULT => memory);
ALU_Mux: entity work.ALU_Mux
port map( OP => opcode,
ARITH => arith,
LOGIC => logic,
SHIFT => shift,
MEMORY => memory,
CCR_ARITH => ccr_arith,
CCR_LOGIC => ccr_logic,
ALU_OUT => ALU_OUT,
CCR_OUT => CCR);
end Structural;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Toplevel
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: ALU top level
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
entity ALU is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (7 downto 0);
RB : in STD_LOGIC_VECTOR (7 downto 0);
OPCODE : in STD_LOGIC_VECTOR (3 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
LDST_OUT : out STD_LOGIC_VECTOR (7 downto 0));
end ALU;
architecture Structural of ALU is
signal arith : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal logic : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal shift : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal memory : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal ccr_arith : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal ccr_logic : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
LDST_OUT <= memory;
Arith_Unit: entity work.Arith_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_arith,
RESULT => arith);
Logic_Unit: entity work.Logic_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_logic,
RESULT => logic);
shift_unit: entity work.alu_shift_unit
port map( A => RA,
COUNT => RB(2 downto 0),
OP => opcode(3),
RESULT => shift);
Load_Store_Unit: entity work.Load_Store_Unit
port map( CLK => CLK,
A => RA,
IMMED => RB,
OP => opcode,
RESULT => memory);
ALU_Mux: entity work.ALU_Mux
port map( OP => opcode,
ARITH => arith,
LOGIC => logic,
SHIFT => shift,
MEMORY => memory,
CCR_ARITH => ccr_arith,
CCR_LOGIC => ccr_logic,
ALU_OUT => ALU_OUT,
CCR_OUT => CCR);
end Structural;
|
--------------------------------------------------------------------------------
-- obj_code_pkg.vhdl -- Application object code in vhdl constant string format.
--------------------------------------------------------------------------------
-- Written by build_rom.py for project 'hello'.
--------------------------------------------------------------------------------
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Package with utility functions for handling SoC object code.
use work.mcu80_pkg.all;
package obj_code_pkg is
-- Object code initialization constant.
constant object_code : obj_code_t(0 to 248) := (
X"c3", X"60", X"00", X"00", X"00", X"00", X"00", X"00", -- 0000h : 0007h
X"c9", X"00", X"00", X"00", X"00", X"00", X"00", X"00", -- 0008h : 000fh
X"c9", X"00", X"00", X"00", X"00", X"00", X"00", X"00", -- 0010h : 0017h
X"c9", X"00", X"00", X"00", X"00", X"00", X"00", X"00", -- 0018h : 001fh
X"c9", X"00", X"00", X"00", X"00", X"00", X"00", X"00", -- 0020h : 0027h
X"c9", X"00", X"00", X"00", X"00", X"00", X"00", X"00", -- 0028h : 002fh
X"c9", X"00", X"00", X"00", X"00", X"00", X"00", X"00", -- 0030h : 0037h
X"c3", X"b0", X"00", X"00", X"00", X"00", X"00", X"00", -- 0038h : 003fh
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", -- 0040h : 0047h
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", -- 0048h : 004fh
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", -- 0050h : 0057h
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", -- 0058h : 005fh
X"31", X"5c", X"01", X"21", X"f7", X"00", X"22", X"f8", -- 0060h : 0067h
X"00", X"21", X"fc", X"00", X"22", X"fa", X"00", X"3e", -- 0068h : 006fh
X"14", X"d3", X"83", X"3e", X"58", X"d3", X"82", X"3e", -- 0070h : 0077h
X"00", X"d3", X"86", X"3e", X"08", X"d3", X"88", X"fb", -- 0078h : 007fh
X"21", X"9e", X"00", X"cd", X"e7", X"00", X"3e", X"55", -- 0080h : 0087h
X"d3", X"86", X"3e", X"04", X"d3", X"80", X"db", X"84", -- 0088h : 008fh
X"4f", X"07", X"07", X"81", X"d3", X"86", X"c3", X"8e", -- 0090h : 0097h
X"00", X"f3", X"76", X"c3", X"9b", X"00", X"0a", X"0d", -- 0098h : 009fh
X"0a", X"48", X"65", X"6c", X"6c", X"6f", X"20", X"57", -- 00a0h : 00a7h
X"6f", X"72", X"6c", X"64", X"21", X"0a", X"24", X"00", -- 00a8h : 00afh
X"e5", X"f5", X"db", X"81", X"e6", X"20", X"ca", X"c9", -- 00b0h : 00b7h
X"00", X"3e", X"20", X"d3", X"81", X"db", X"80", X"d3", -- 00b8h : 00bfh
X"86", X"2a", X"fa", X"00", X"77", X"23", X"22", X"fa", -- 00c0h : 00c7h
X"00", X"db", X"81", X"e6", X"10", X"ca", X"e3", X"00", -- 00c8h : 00cfh
X"3e", X"10", X"d3", X"81", X"2a", X"f8", X"00", X"7e", -- 00d0h : 00d7h
X"fe", X"24", X"ca", X"e3", X"00", X"23", X"22", X"f8", -- 00d8h : 00dfh
X"00", X"d3", X"80", X"f1", X"e1", X"fb", X"c9", X"7e", -- 00e0h : 00e7h
X"23", X"22", X"f8", X"00", X"fe", X"24", X"ca", X"f6", -- 00e8h : 00efh
X"00", X"d3", X"80", X"c3", X"e7", X"00", X"c9", X"24", -- 00f0h : 00f7h
X"00" -- 00f8h : 00f8h
);
end package obj_code_pkg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2488.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p02n01i02488ent IS
END c07s03b03x00p02n01i02488ent;
ARCHITECTURE c07s03b03x00p02n01i02488arch OF c07s03b03x00p02n01i02488ent IS
BEGIN
TESTING: PROCESS
function func1 (a2 : integer) return integer is
begin
return 5;
end func1;
variable x: integer := 1;
variable y: integer;
BEGIN
y := func1 ();
assert FALSE
report "***FAILED TEST: c07s03b03x00p02n01i02488 - Missing parameter list."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p02n01i02488arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2488.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p02n01i02488ent IS
END c07s03b03x00p02n01i02488ent;
ARCHITECTURE c07s03b03x00p02n01i02488arch OF c07s03b03x00p02n01i02488ent IS
BEGIN
TESTING: PROCESS
function func1 (a2 : integer) return integer is
begin
return 5;
end func1;
variable x: integer := 1;
variable y: integer;
BEGIN
y := func1 ();
assert FALSE
report "***FAILED TEST: c07s03b03x00p02n01i02488 - Missing parameter list."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p02n01i02488arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2488.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p02n01i02488ent IS
END c07s03b03x00p02n01i02488ent;
ARCHITECTURE c07s03b03x00p02n01i02488arch OF c07s03b03x00p02n01i02488ent IS
BEGIN
TESTING: PROCESS
function func1 (a2 : integer) return integer is
begin
return 5;
end func1;
variable x: integer := 1;
variable y: integer;
BEGIN
y := func1 ();
assert FALSE
report "***FAILED TEST: c07s03b03x00p02n01i02488 - Missing parameter list."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p02n01i02488arch;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity buttons_to_switches is
port(
adjust: out std_logic_vector(1 downto 0);
rotary_pulse: in std_logic;
rotary_direction: in std_logic;
buttons_in: in std_logic_vector(3 downto 0);
current_mode: out std_logic_vector(1 downto 0);
current_channel: out std_logic_vector(1 downto 0);
clk: in std_logic
);
end buttons_to_switches;
architecture behavioral of buttons_to_switches is
signal current_mode_sig: unsigned(1 downto 0);
signal current_channel_sig: unsigned(1 downto 0);
begin
rotary_handle: process(clk)
begin
if(rising_edge(clk)) then
adjust <= "00";
if(rotary_pulse = '1' and rotary_direction = '1') then
adjust <= "01";
elsif (rotary_pulse = '1') then
adjust <= "10";
end if;
end if;
end process;
button_handle: process(clk)
begin
if(rising_edge(clk)) then
if(buttons_in = "0001") then
current_mode_sig <= current_mode_sig + 1;
elsif(buttons_in = "0010") then
current_mode_sig <= current_mode_sig - 1;
elsif(buttons_in = "0100") then
current_channel_sig <= current_channel_sig + 1;
elsif(buttons_in = "1000") then
current_channel_sig <= current_channel_sig - 1;
end if;
end if;
end process;
current_channel <= std_logic_vector(current_channel_sig);
current_mode <= std_logic_vector(current_mode_sig);
end behavioral;
|
-------------------------------------------------------------------------------
--
-- SPI to AXI4-Lite Bridge, test controller entity declaration
--
-- Description:
-- SPI overrun testcase
--
-- Author(s):
-- Guy Eschemann, [email protected]
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2022 Guy Eschemann
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library OSVVM;
context OSVVM.OsvvmContext;
use osvvm.ScoreboardPkg_slv.all;
library osvvm_axi4;
use osvvm_axi4.Axi4OptionsPkg.all;
architecture overrun of tb_spi2axi_testctrl is
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant SPI_PACKET_LENGTH_BYTES : natural := 11;
-------------------------------------------------------------------------------
-- Aliases
-------------------------------------------------------------------------------
alias TxBurstFifo : ScoreboardIdType is SpiRec.BurstFifo;
alias RxBurstFifo : ScoreboardIdType is SpiRec.BurstFifo;
begin
------------------------------------------------------------
-- ControlProc
-- Set up AlertLog and wait for end of test
------------------------------------------------------------
ControlProc : process
procedure spi_process(tx_bytes : integer_vector; rx_bytes : out integer_vector) is
variable num_bytes : integer;
variable valid : boolean;
variable rx_byte : std_logic_vector(7 downto 0);
variable bytes_to_send : integer;
begin
-- Push TX bytes to SPI VC
PushBurst(TxBurstFifo, tx_bytes, 8);
SendBurst(SpiRec, tx_bytes'length);
-- Fetch RX bytes from SPI VC
GetBurst(SpiRec, num_bytes);
AlertIfNot(num_bytes = tx_bytes'length, "unexpected number of received bytes");
for i in 0 to num_bytes - 1 loop
PopWord(RxBurstFifo, valid, rx_byte, bytes_to_send);
AlertIfNot(valid, "invalid receive data");
Log("RX byte: " & to_string(rx_byte), DEBUG);
rx_bytes(i) := to_integer(unsigned(rx_byte));
end loop;
end procedure;
-- Write an AXI4 register over SPI
procedure spi_write(addr : unsigned(31 downto 0); data : std_logic_vector(31 downto 0); status : out std_logic_vector(7 downto 0)) is
variable tx_bytes : integer_vector(0 to SPI_PACKET_LENGTH_BYTES - 1);
variable rx_bytes : integer_vector(0 to SPI_PACKET_LENGTH_BYTES - 1);
variable tx_byte_idx : natural;
begin
Log("SPI Write: addr = 0x" & to_hxstring(addr) & ", data = 0x" & to_hxstring(data), DEBUG);
tx_byte_idx := 0;
tx_bytes(tx_byte_idx) := 0; -- write
tx_byte_idx := tx_byte_idx + 1;
for i in 3 downto 0 loop
tx_bytes(tx_byte_idx) := to_integer(addr(i * 8 + 7 downto i * 8));
tx_byte_idx := tx_byte_idx + 1;
end loop;
for i in 3 downto 0 loop
tx_bytes(tx_byte_idx) := to_integer(unsigned(data(i * 8 + 7 downto i * 8)));
tx_byte_idx := tx_byte_idx + 1;
end loop;
tx_bytes(tx_byte_idx) := 0; -- a dummy byte to allow writing the data word
tx_byte_idx := tx_byte_idx + 1;
tx_bytes(tx_byte_idx) := 0; -- AXI4 write response
tx_byte_idx := tx_byte_idx + 1;
assert tx_byte_idx = tx_bytes'length severity failure;
--
spi_process(tx_bytes, rx_bytes);
status := std_logic_vector(to_unsigned(rx_bytes(10), 8));
end procedure;
-- Read an AXI4 register over SPI
procedure spi_read(addr : unsigned(31 downto 0); data : out std_logic_vector(31 downto 0); status : out std_logic_vector(7 downto 0)) is
variable tx_bytes : integer_vector(0 to SPI_PACKET_LENGTH_BYTES - 1);
variable rx_bytes : integer_vector(0 to SPI_PACKET_LENGTH_BYTES - 1);
variable tx_byte_idx : natural;
begin
Log("SPI Write: addr = 0x" & to_hxstring(addr) & ", data = 0x" & to_hxstring(data), DEBUG);
tx_byte_idx := 0;
tx_bytes(tx_byte_idx) := 1; -- read
tx_byte_idx := tx_byte_idx + 1;
for i in 3 downto 0 loop
tx_bytes(tx_byte_idx) := to_integer(addr(i * 8 + 7 downto i * 8));
tx_byte_idx := tx_byte_idx + 1;
end loop;
for i in 0 to 5 loop
tx_bytes(tx_byte_idx) := 0; -- don't care
tx_byte_idx := tx_byte_idx + 1;
end loop;
assert tx_byte_idx = tx_bytes'length severity failure;
--
spi_process(tx_bytes, rx_bytes);
data(31 downto 24) := std_logic_vector(to_unsigned(rx_bytes(6), 8));
data(23 downto 16) := std_logic_vector(to_unsigned(rx_bytes(7), 8));
data(15 downto 8) := std_logic_vector(to_unsigned(rx_bytes(8), 8));
data(7 downto 0) := std_logic_vector(to_unsigned(rx_bytes(9), 8));
status := std_logic_vector(to_unsigned(rx_bytes(10), 8));
end procedure;
variable addr : unsigned(31 downto 0);
variable wdata : std_logic_vector(31 downto 0);
variable mem_reg : std_logic_vector(31 downto 0);
variable status : std_logic_vector(7 downto 0);
variable tx_bytes : integer_vector(0 to SPI_PACKET_LENGTH_BYTES);
variable rx_bytes : integer_vector(0 to SPI_PACKET_LENGTH_BYTES); -- @suppress "variable rx_bytes is never read"
begin
-- Initialization of test
SetAlertLogName("tb_spi2axi_overrun");
SetLogEnable(INFO, TRUE);
SetLogEnable(DEBUG, FALSE);
SetLogEnable(PASSED, FALSE);
SetLogEnable(FindAlertLogID("Axi4LiteMemory"), INFO, FALSE, TRUE);
-- Wait for testbench initialization
wait for 0 ns;
-- Wait for Design Reset
wait until nReset = '1';
ClearAlerts;
SetCPHA(SpiRec, SPI_CPHA);
SetCPOL(SpiRec, SPI_CPOL);
wait for 1 us;
Log("Testing 12-byte SPI write");
tx_bytes := (others => 0);
spi_process(tx_bytes, rx_bytes);
Log("Testing normal SPI write");
addr := x"76543210";
wdata := x"12345678";
spi_write(addr, wdata, status);
AlertIf(status(2) /= '0', "unexpected timeout");
AlertIf(status(1 downto 0) /= "00", "unexpected write response");
Read(Axi4MemRec, std_logic_vector(addr), mem_reg);
AffirmIfEqual(mem_reg, wdata, "Memory data word: ");
wait for 1 us;
EndOfTestReports;
std.env.stop;
wait;
end process ControlProc;
end architecture overrun;
configuration tb_spi2axi_overrun of tb_spi2axi is
for TestHarness
for testctrl_inst : tb_spi2axi_testctrl
use entity work.tb_spi2axi_testctrl(overrun);
end for;
end for;
end tb_spi2axi_overrun;
|
library ieee;
use ieee.std_logic_1164.all;
package fastfilter_types is
constant PIXEL_CONST : integer := 8;
type pixel_array is array ( integer range <> ) of std_logic_vector (PIXEL_CONST-1 downto 0);
end fastfilter_types;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/hdl_modulator/hdl_modulator_sincos_hdl.vhd
-- Created: 2018-02-27 13:25:15
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: hdl_modulator_sincos_hdl
-- Source Path: hdl_modulator/wave_generator/sincos hdl
-- Hierarchy Level: 3
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY hdl_modulator_sincos_hdl IS
PORT( In1 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
Out1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
Out2 : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14
);
END hdl_modulator_sincos_hdl;
ARCHITECTURE rtl OF hdl_modulator_sincos_hdl IS
-- Component Declarations
COMPONENT hdl_modulator_sin_hdl
PORT( In1 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
y : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14
);
END COMPONENT;
COMPONENT hdl_modulator_cos_hdl
PORT( In1 : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
x : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : hdl_modulator_sin_hdl
USE ENTITY work.hdl_modulator_sin_hdl(rtl);
FOR ALL : hdl_modulator_cos_hdl
USE ENTITY work.hdl_modulator_cos_hdl(rtl);
-- Signals
SIGNAL Sine : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL Cosine : std_logic_vector(15 DOWNTO 0); -- ufix16
BEGIN
u_sin_hdl : hdl_modulator_sin_hdl
PORT MAP( In1 => In1, -- sfix16_En14
y => Sine -- sfix16_En14
);
u_cos_hdl : hdl_modulator_cos_hdl
PORT MAP( In1 => In1, -- sfix16_En14
x => Cosine -- sfix16_En14
);
Out1 <= Sine;
Out2 <= Cosine;
END rtl;
|
-------------------------------------------------------------------------------
-- system_mb_plb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library plb_v46_v1_05_a;
use plb_v46_v1_05_a.all;
entity system_mb_plb_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 11);
MPLB_Rst : out std_logic_vector(0 to 5);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 191);
M_UABus : in std_logic_vector(0 to 191);
M_BE : in std_logic_vector(0 to 47);
M_RNW : in std_logic_vector(0 to 5);
M_abort : in std_logic_vector(0 to 5);
M_busLock : in std_logic_vector(0 to 5);
M_TAttribute : in std_logic_vector(0 to 95);
M_lockErr : in std_logic_vector(0 to 5);
M_MSize : in std_logic_vector(0 to 11);
M_priority : in std_logic_vector(0 to 11);
M_rdBurst : in std_logic_vector(0 to 5);
M_request : in std_logic_vector(0 to 5);
M_size : in std_logic_vector(0 to 23);
M_type : in std_logic_vector(0 to 17);
M_wrBurst : in std_logic_vector(0 to 5);
M_wrDBus : in std_logic_vector(0 to 383);
Sl_addrAck : in std_logic_vector(0 to 11);
Sl_MRdErr : in std_logic_vector(0 to 71);
Sl_MWrErr : in std_logic_vector(0 to 71);
Sl_MBusy : in std_logic_vector(0 to 71);
Sl_rdBTerm : in std_logic_vector(0 to 11);
Sl_rdComp : in std_logic_vector(0 to 11);
Sl_rdDAck : in std_logic_vector(0 to 11);
Sl_rdDBus : in std_logic_vector(0 to 767);
Sl_rdWdAddr : in std_logic_vector(0 to 47);
Sl_rearbitrate : in std_logic_vector(0 to 11);
Sl_SSize : in std_logic_vector(0 to 23);
Sl_wait : in std_logic_vector(0 to 11);
Sl_wrBTerm : in std_logic_vector(0 to 11);
Sl_wrComp : in std_logic_vector(0 to 11);
Sl_wrDAck : in std_logic_vector(0 to 11);
Sl_MIRQ : in std_logic_vector(0 to 71);
PLB_MIRQ : out std_logic_vector(0 to 5);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 7);
PLB_MAddrAck : out std_logic_vector(0 to 5);
PLB_MTimeout : out std_logic_vector(0 to 5);
PLB_MBusy : out std_logic_vector(0 to 5);
PLB_MRdErr : out std_logic_vector(0 to 5);
PLB_MWrErr : out std_logic_vector(0 to 5);
PLB_MRdBTerm : out std_logic_vector(0 to 5);
PLB_MRdDAck : out std_logic_vector(0 to 5);
PLB_MRdDBus : out std_logic_vector(0 to 383);
PLB_MRdWdAddr : out std_logic_vector(0 to 23);
PLB_MRearbitrate : out std_logic_vector(0 to 5);
PLB_MWrBTerm : out std_logic_vector(0 to 5);
PLB_MWrDAck : out std_logic_vector(0 to 5);
PLB_MSSize : out std_logic_vector(0 to 11);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 2);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 11);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 63);
PLB_wrPrim : out std_logic_vector(0 to 11);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 5);
PLB_SMWrErr : out std_logic_vector(0 to 5);
PLB_SMBusy : out std_logic_vector(0 to 5);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 63);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end system_mb_plb_wrapper;
architecture STRUCTURE of system_mb_plb_wrapper is
component plb_v46 is
generic (
C_PLBV46_NUM_MASTERS : integer;
C_PLBV46_NUM_SLAVES : integer;
C_PLBV46_MID_WIDTH : integer;
C_PLBV46_AWIDTH : integer;
C_PLBV46_DWIDTH : integer;
C_DCR_INTFCE : integer;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_DCR_AWIDTH : integer;
C_DCR_DWIDTH : integer;
C_EXT_RESET_HIGH : integer;
C_IRQ_ACTIVE : std_logic;
C_ADDR_PIPELINING_TYPE : integer;
C_FAMILY : string;
C_P2P : integer;
C_ARB_TYPE : integer
);
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
MPLB_Rst : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_ABus : in std_logic_vector(0 to C_DCR_AWIDTH-1);
DCR_DBus : in std_logic_vector(0 to C_DCR_DWIDTH-1);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_UABus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*32)-1);
M_BE : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*(C_PLBV46_DWIDTH/8))-1);
M_RNW : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_abort : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_busLock : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_TAttribute : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*16)-1);
M_lockErr : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_MSize : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_priority : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
M_rdBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_request : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_size : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
M_type : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*3)-1);
M_wrBurst : in std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
M_wrDBus : in std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
Sl_addrAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MRdErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MWrErr : in std_logic_vector(0 to (C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1);
Sl_MBusy : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 );
Sl_rdBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_rdDBus : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1);
Sl_rdWdAddr : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*4-1);
Sl_rearbitrate : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_SSize : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*2-1);
Sl_wait : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrBTerm : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrComp : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_wrDAck : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
Sl_MIRQ : in std_logic_vector(0 to C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1);
PLB_MIRQ : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to (C_PLBV46_DWIDTH/8)-1);
PLB_MAddrAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MTimeout : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MRdDBus : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1);
PLB_MRdWdAddr : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*4)-1);
PLB_MRearbitrate : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrBTerm : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MWrDAck : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_MSSize : out std_logic_vector(0 to (C_PLBV46_NUM_MASTERS*2)-1);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to C_PLBV46_MID_WIDTH-1);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_wrPrim : out std_logic_vector(0 to C_PLBV46_NUM_SLAVES-1);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMWrErr : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SMBusy : out std_logic_vector(0 to C_PLBV46_NUM_MASTERS-1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to C_PLBV46_DWIDTH-1);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
Bus_Error_Det : out std_logic
);
end component;
begin
mb_plb : plb_v46
generic map (
C_PLBV46_NUM_MASTERS => 6,
C_PLBV46_NUM_SLAVES => 12,
C_PLBV46_MID_WIDTH => 3,
C_PLBV46_AWIDTH => 32,
C_PLBV46_DWIDTH => 64,
C_DCR_INTFCE => 0,
C_BASEADDR => B"1111111111",
C_HIGHADDR => B"0000000000",
C_DCR_AWIDTH => 10,
C_DCR_DWIDTH => 32,
C_EXT_RESET_HIGH => 1,
C_IRQ_ACTIVE => '1',
C_ADDR_PIPELINING_TYPE => 1,
C_FAMILY => "virtex5",
C_P2P => 0,
C_ARB_TYPE => 0
)
port map (
PLB_Clk => PLB_Clk,
SYS_Rst => SYS_Rst,
PLB_Rst => PLB_Rst,
SPLB_Rst => SPLB_Rst,
MPLB_Rst => MPLB_Rst,
PLB_dcrAck => PLB_dcrAck,
PLB_dcrDBus => PLB_dcrDBus,
DCR_ABus => DCR_ABus,
DCR_DBus => DCR_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
M_ABus => M_ABus,
M_UABus => M_UABus,
M_BE => M_BE,
M_RNW => M_RNW,
M_abort => M_abort,
M_busLock => M_busLock,
M_TAttribute => M_TAttribute,
M_lockErr => M_lockErr,
M_MSize => M_MSize,
M_priority => M_priority,
M_rdBurst => M_rdBurst,
M_request => M_request,
M_size => M_size,
M_type => M_type,
M_wrBurst => M_wrBurst,
M_wrDBus => M_wrDBus,
Sl_addrAck => Sl_addrAck,
Sl_MRdErr => Sl_MRdErr,
Sl_MWrErr => Sl_MWrErr,
Sl_MBusy => Sl_MBusy,
Sl_rdBTerm => Sl_rdBTerm,
Sl_rdComp => Sl_rdComp,
Sl_rdDAck => Sl_rdDAck,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rearbitrate => Sl_rearbitrate,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_wrBTerm => Sl_wrBTerm,
Sl_wrComp => Sl_wrComp,
Sl_wrDAck => Sl_wrDAck,
Sl_MIRQ => Sl_MIRQ,
PLB_MIRQ => PLB_MIRQ,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_BE => PLB_BE,
PLB_MAddrAck => PLB_MAddrAck,
PLB_MTimeout => PLB_MTimeout,
PLB_MBusy => PLB_MBusy,
PLB_MRdErr => PLB_MRdErr,
PLB_MWrErr => PLB_MWrErr,
PLB_MRdBTerm => PLB_MRdBTerm,
PLB_MRdDAck => PLB_MRdDAck,
PLB_MRdDBus => PLB_MRdDBus,
PLB_MRdWdAddr => PLB_MRdWdAddr,
PLB_MRearbitrate => PLB_MRearbitrate,
PLB_MWrBTerm => PLB_MWrBTerm,
PLB_MWrDAck => PLB_MWrDAck,
PLB_MSSize => PLB_MSSize,
PLB_PAValid => PLB_PAValid,
PLB_RNW => PLB_RNW,
PLB_SAValid => PLB_SAValid,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_TAttribute => PLB_TAttribute,
PLB_lockErr => PLB_lockErr,
PLB_masterID => PLB_masterID,
PLB_MSize => PLB_MSize,
PLB_rdPendPri => PLB_rdPendPri,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdBurst => PLB_rdBurst,
PLB_rdPrim => PLB_rdPrim,
PLB_reqPri => PLB_reqPri,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrBurst => PLB_wrBurst,
PLB_wrDBus => PLB_wrDBus,
PLB_wrPrim => PLB_wrPrim,
PLB_SaddrAck => PLB_SaddrAck,
PLB_SMRdErr => PLB_SMRdErr,
PLB_SMWrErr => PLB_SMWrErr,
PLB_SMBusy => PLB_SMBusy,
PLB_SrdBTerm => PLB_SrdBTerm,
PLB_SrdComp => PLB_SrdComp,
PLB_SrdDAck => PLB_SrdDAck,
PLB_SrdDBus => PLB_SrdDBus,
PLB_SrdWdAddr => PLB_SrdWdAddr,
PLB_Srearbitrate => PLB_Srearbitrate,
PLB_Sssize => PLB_Sssize,
PLB_Swait => PLB_Swait,
PLB_SwrBTerm => PLB_SwrBTerm,
PLB_SwrComp => PLB_SwrComp,
PLB_SwrDAck => PLB_SwrDAck,
Bus_Error_Det => Bus_Error_Det
);
end architecture STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity add1 is
port(
in1 : in std_logic;
in0 : in std_logic;
cin : in std_logic;
cout : out std_logic;
sum : out std_logic
);
end add1;
architecture bhv of add1 is
begin
sum <= in1 xor in0 xor cin;
cout <= (in1 and in0) or (cin and in1) or (cin and in0);
end bhv;
|
entity proc6 is
end entity;
architecture test of proc6 is
procedure delay(signal x : out integer;
signal y : in integer;
constant d : in delay_length) is
begin
x <= y after d;
end procedure;
signal a, b : integer;
begin
foo: delay(a, b, 10 ns);
check: process is
begin
b <= 6;
wait for 11 ns;
assert a = 6;
b <= 7;
wait for 5 ns;
assert a = 6;
wait for 5 ns;
assert a = 7;
wait;
end process;
end architecture;
|
entity proc6 is
end entity;
architecture test of proc6 is
procedure delay(signal x : out integer;
signal y : in integer;
constant d : in delay_length) is
begin
x <= y after d;
end procedure;
signal a, b : integer;
begin
foo: delay(a, b, 10 ns);
check: process is
begin
b <= 6;
wait for 11 ns;
assert a = 6;
b <= 7;
wait for 5 ns;
assert a = 6;
wait for 5 ns;
assert a = 7;
wait;
end process;
end architecture;
|
entity proc6 is
end entity;
architecture test of proc6 is
procedure delay(signal x : out integer;
signal y : in integer;
constant d : in delay_length) is
begin
x <= y after d;
end procedure;
signal a, b : integer;
begin
foo: delay(a, b, 10 ns);
check: process is
begin
b <= 6;
wait for 11 ns;
assert a = 6;
b <= 7;
wait for 5 ns;
assert a = 6;
wait for 5 ns;
assert a = 7;
wait;
end process;
end architecture;
|
entity proc6 is
end entity;
architecture test of proc6 is
procedure delay(signal x : out integer;
signal y : in integer;
constant d : in delay_length) is
begin
x <= y after d;
end procedure;
signal a, b : integer;
begin
foo: delay(a, b, 10 ns);
check: process is
begin
b <= 6;
wait for 11 ns;
assert a = 6;
b <= 7;
wait for 5 ns;
assert a = 6;
wait for 5 ns;
assert a = 7;
wait;
end process;
end architecture;
|
entity proc6 is
end entity;
architecture test of proc6 is
procedure delay(signal x : out integer;
signal y : in integer;
constant d : in delay_length) is
begin
x <= y after d;
end procedure;
signal a, b : integer;
begin
foo: delay(a, b, 10 ns);
check: process is
begin
b <= 6;
wait for 11 ns;
assert a = 6;
b <= 7;
wait for 5 ns;
assert a = 6;
wait for 5 ns;
assert a = 7;
wait;
end process;
end architecture;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: timers
-- File: timers.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: This unit implemets two general-pupose timers and one watchdog.
-- All three timers are 24-bit wide down-counters clocked by a
-- common 10-bit pre-scaler. The pre-scaler is clocked by the
-- system clock. All three timers share the same decrementer
-- which means that the minimum pre-scaler division is three.
-- On reset, the scaler and watchdog are set to 'all-ones',
-- the two GP-timers disabled, and the remaining registers are
-- 'unknown'.
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned."+";
use work.target.all;
use work.config.all;
use work.iface.all;
use work.macro.all;
use work.amba.all;
entity timers is
port (
rst : in std_logic;
clk : in clk_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
timo : out timers_out_type
);
end;
architecture rtl of timers is
type timer_control_type is record
enable : std_logic; -- enable counter
load : std_logic; -- load counter
restart : std_logic; -- restart counter
irq : std_logic; -- interrupt
end record;
type timregs is record
t0value : std_logic_vector(23 downto 0);
t0load : std_logic_vector(23 downto 0);
t0ctrl : timer_control_type;
t1value : std_logic_vector(23 downto 0);
t1load : std_logic_vector(23 downto 0);
t1ctrl : timer_control_type;
scalerval : std_logic_vector(9 downto 0);
scalerpre : std_logic_vector(9 downto 0);
tick : std_logic;
tsel : std_logic_vector(1 downto 0);
end record;
type wdogregs is record
wdog : std_logic_vector(23 downto 0);
wdogtout : std_logic;
end record;
constant zero : std_logic_vector(23 downto 0) := (others => '0');
signal r, rin : timregs;
signal wr, wrin : wdogregs;
-- Main process
begin
timerop : process(rst, r, wr, apbi)
variable sval : std_logic_vector(10 downto 0);
variable rdata : std_logic_vector(31 downto 0);
variable res, addin : std_logic_vector(23 downto 0);
variable tv : timregs;
variable wv : wdogregs;
variable z : std_logic;
begin
tv := r; tv.t0ctrl.irq := '0'; tv.t1ctrl.irq := '0';
tv.t0ctrl.load := '0'; tv.t1ctrl.load := '0';
wv := wr;
-- scaler operation
-- pragma translate_off
if not is_x(r.scalerval) then
-- pragma translate_on
sval := ('0' & r.scalerval) - 1; -- decrement scaler
-- pragma translate_off
end if;
-- pragma translate_on
if sval(10) = '1' then
tv.scalerval := r.scalerpre; -- reload if carry-out
else
tv.scalerval := sval(9 downto 0);
end if;
tv.tick := sval(10);
-- timer operation
if (r.tick = '1') or (r.tsel /= "00") then
-- pragma translate_off
if not is_x(r.tsel) then
-- pragma translate_on
tv.tsel := r.tsel + 1;
-- pragma translate_off
end if;
-- pragma translate_on
end if;
addin := (others => '-');
case r.tsel is -- select which timer to operate on
when "01" => addin := r.t0value;
when "10" => addin := r.t1value;
when "11" => if WDOGEN then addin := wr.wdog; end if;
when others =>
end case;
-- pragma translate_off
if not is_x(addin) then
-- pragma translate_on
res := addin - 1; -- decrement timer
if addin = zero then z := '1'; else z := '0'; end if; -- zero detect
-- pragma translate_off
end if;
-- pragma translate_on
-- update corresponding register and generate irq/wdrst
case r.tsel is -- select which timer to operate on
when "01" =>
if r.t0ctrl.enable = '1' then
tv.t0ctrl.irq := z and not r.t0ctrl.load; -- no irq at load
if tv.t0ctrl.irq = '1' then
tv.t0ctrl.enable := r.t0ctrl.restart;
if r.t0ctrl.restart = '1' then tv.t0value := r.t0load; end if;
else tv.t0value := res; end if;
end if;
when "10" =>
if r.t1ctrl.enable = '1' then
tv.t1ctrl.irq := z and not r.t1ctrl.load; -- no irq at load
if tv.t1ctrl.irq = '1' then
tv.t1ctrl.enable := r.t1ctrl.restart;
if r.t1ctrl.restart = '1' then tv.t1value := r.t1load; end if;
else tv.t1value := res; end if;
end if;
when "11" =>
if WDOGEN then
wv.wdogtout := z;
if z = '0' then wv.wdog := res; end if;
end if;
when others =>
end case;
if r.t0ctrl.load = '1' then tv.t0value := r.t0load; end if;
if r.t1ctrl.load = '1' then tv.t1value := r.t1load; end if;
-- read/write registers
rdata := (others => '0');
case apbi.paddr(5 downto 2) is
when "0000" => rdata(23 downto 0) := r.t0value;
when "0001" => rdata(23 downto 0) := r.t0load;
when "0010" => rdata(1 downto 0) := r.t0ctrl.restart & r.t0ctrl.enable;
when "0011" => if WDOGEN then rdata(23 downto 0) := wr.wdog; end if;
when "0100" => rdata(23 downto 0) := r.t1value;
when "0101" => rdata(23 downto 0) := r.t1load;
when "0110" => rdata(1 downto 0) := r.t1ctrl.restart & r.t1ctrl.enable;
when "1000" => rdata(9 downto 0) := r.scalerval;
when "1001" => rdata(9 downto 0) := r.scalerpre;
when others => rdata(9 downto 0) := (others => '-');
end case;
if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(5 downto 2) is
when "0000" => tv.t0value := apbi.pwdata(23 downto 0);
when "0001" => tv.t0load := apbi.pwdata(23 downto 0);
when "0010" => tv.t0ctrl.load := apbi.pwdata(2);
tv.t0ctrl.restart := apbi.pwdata(1);
tv.t0ctrl.enable := apbi.pwdata(0);
when "0011" => if WDOGEN then wv.wdog := apbi.pwdata(23 downto 0); end if;
when "0100" => tv.t1value := apbi.pwdata(23 downto 0);
when "0101" => tv.t1load := apbi.pwdata(23 downto 0);
when "0110" => tv.t1ctrl.load := apbi.pwdata(2);
tv.t1ctrl.restart := apbi.pwdata(1);
tv.t1ctrl.enable := apbi.pwdata(0);
when "1000" => tv.scalerval := apbi.pwdata(9 downto 0);
when "1001" => tv.scalerpre := apbi.pwdata(9 downto 0);
when others => null;
end case;
end if;
-- reset operation
if rst = '0' then
tv.t0ctrl.enable := '0'; tv.t1ctrl.enable := '0';
if WDOGEN then wv.wdog := (others => '1'); wv.wdogtout := '0'; end if;
if BOOTOPT /= memory then
tv.scalerval := std_logic_vector(TPRESC(9 downto 0));
tv.scalerpre := std_logic_vector(TPRESC(9 downto 0));
else
tv.scalerval := (others => '0'); tv.scalerpre := (others => '0');
end if;
tv.tsel := "00";
end if;
rin <= tv; wrin <= wv; -- update registers
apbo.prdata <= rdata; -- drive data bus
end process;
-- Registers
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
wd : if WDOGEN generate
regs : process(clk)
begin
if rising_edge(clk) then
wr <= wrin;
end if;
end process;
end generate;
-- Drive outputs
timo.tick <= r.tick;
timo.irq <= r.t1ctrl.irq & r.t0ctrl.irq;
timo.wdog <= not wr.wdogtout when WDOGEN else '-';
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: timers
-- File: timers.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: This unit implemets two general-pupose timers and one watchdog.
-- All three timers are 24-bit wide down-counters clocked by a
-- common 10-bit pre-scaler. The pre-scaler is clocked by the
-- system clock. All three timers share the same decrementer
-- which means that the minimum pre-scaler division is three.
-- On reset, the scaler and watchdog are set to 'all-ones',
-- the two GP-timers disabled, and the remaining registers are
-- 'unknown'.
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."-";
use IEEE.std_logic_unsigned."+";
use work.target.all;
use work.config.all;
use work.iface.all;
use work.macro.all;
use work.amba.all;
entity timers is
port (
rst : in std_logic;
clk : in clk_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
timo : out timers_out_type
);
end;
architecture rtl of timers is
type timer_control_type is record
enable : std_logic; -- enable counter
load : std_logic; -- load counter
restart : std_logic; -- restart counter
irq : std_logic; -- interrupt
end record;
type timregs is record
t0value : std_logic_vector(23 downto 0);
t0load : std_logic_vector(23 downto 0);
t0ctrl : timer_control_type;
t1value : std_logic_vector(23 downto 0);
t1load : std_logic_vector(23 downto 0);
t1ctrl : timer_control_type;
scalerval : std_logic_vector(9 downto 0);
scalerpre : std_logic_vector(9 downto 0);
tick : std_logic;
tsel : std_logic_vector(1 downto 0);
end record;
type wdogregs is record
wdog : std_logic_vector(23 downto 0);
wdogtout : std_logic;
end record;
constant zero : std_logic_vector(23 downto 0) := (others => '0');
signal r, rin : timregs;
signal wr, wrin : wdogregs;
-- Main process
begin
timerop : process(rst, r, wr, apbi)
variable sval : std_logic_vector(10 downto 0);
variable rdata : std_logic_vector(31 downto 0);
variable res, addin : std_logic_vector(23 downto 0);
variable tv : timregs;
variable wv : wdogregs;
variable z : std_logic;
begin
tv := r; tv.t0ctrl.irq := '0'; tv.t1ctrl.irq := '0';
tv.t0ctrl.load := '0'; tv.t1ctrl.load := '0';
wv := wr;
-- scaler operation
-- pragma translate_off
if not is_x(r.scalerval) then
-- pragma translate_on
sval := ('0' & r.scalerval) - 1; -- decrement scaler
-- pragma translate_off
end if;
-- pragma translate_on
if sval(10) = '1' then
tv.scalerval := r.scalerpre; -- reload if carry-out
else
tv.scalerval := sval(9 downto 0);
end if;
tv.tick := sval(10);
-- timer operation
if (r.tick = '1') or (r.tsel /= "00") then
-- pragma translate_off
if not is_x(r.tsel) then
-- pragma translate_on
tv.tsel := r.tsel + 1;
-- pragma translate_off
end if;
-- pragma translate_on
end if;
addin := (others => '-');
case r.tsel is -- select which timer to operate on
when "01" => addin := r.t0value;
when "10" => addin := r.t1value;
when "11" => if WDOGEN then addin := wr.wdog; end if;
when others =>
end case;
-- pragma translate_off
if not is_x(addin) then
-- pragma translate_on
res := addin - 1; -- decrement timer
if addin = zero then z := '1'; else z := '0'; end if; -- zero detect
-- pragma translate_off
end if;
-- pragma translate_on
-- update corresponding register and generate irq/wdrst
case r.tsel is -- select which timer to operate on
when "01" =>
if r.t0ctrl.enable = '1' then
tv.t0ctrl.irq := z and not r.t0ctrl.load; -- no irq at load
if tv.t0ctrl.irq = '1' then
tv.t0ctrl.enable := r.t0ctrl.restart;
if r.t0ctrl.restart = '1' then tv.t0value := r.t0load; end if;
else tv.t0value := res; end if;
end if;
when "10" =>
if r.t1ctrl.enable = '1' then
tv.t1ctrl.irq := z and not r.t1ctrl.load; -- no irq at load
if tv.t1ctrl.irq = '1' then
tv.t1ctrl.enable := r.t1ctrl.restart;
if r.t1ctrl.restart = '1' then tv.t1value := r.t1load; end if;
else tv.t1value := res; end if;
end if;
when "11" =>
if WDOGEN then
wv.wdogtout := z;
if z = '0' then wv.wdog := res; end if;
end if;
when others =>
end case;
if r.t0ctrl.load = '1' then tv.t0value := r.t0load; end if;
if r.t1ctrl.load = '1' then tv.t1value := r.t1load; end if;
-- read/write registers
rdata := (others => '0');
case apbi.paddr(5 downto 2) is
when "0000" => rdata(23 downto 0) := r.t0value;
when "0001" => rdata(23 downto 0) := r.t0load;
when "0010" => rdata(1 downto 0) := r.t0ctrl.restart & r.t0ctrl.enable;
when "0011" => if WDOGEN then rdata(23 downto 0) := wr.wdog; end if;
when "0100" => rdata(23 downto 0) := r.t1value;
when "0101" => rdata(23 downto 0) := r.t1load;
when "0110" => rdata(1 downto 0) := r.t1ctrl.restart & r.t1ctrl.enable;
when "1000" => rdata(9 downto 0) := r.scalerval;
when "1001" => rdata(9 downto 0) := r.scalerpre;
when others => rdata(9 downto 0) := (others => '-');
end case;
if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(5 downto 2) is
when "0000" => tv.t0value := apbi.pwdata(23 downto 0);
when "0001" => tv.t0load := apbi.pwdata(23 downto 0);
when "0010" => tv.t0ctrl.load := apbi.pwdata(2);
tv.t0ctrl.restart := apbi.pwdata(1);
tv.t0ctrl.enable := apbi.pwdata(0);
when "0011" => if WDOGEN then wv.wdog := apbi.pwdata(23 downto 0); end if;
when "0100" => tv.t1value := apbi.pwdata(23 downto 0);
when "0101" => tv.t1load := apbi.pwdata(23 downto 0);
when "0110" => tv.t1ctrl.load := apbi.pwdata(2);
tv.t1ctrl.restart := apbi.pwdata(1);
tv.t1ctrl.enable := apbi.pwdata(0);
when "1000" => tv.scalerval := apbi.pwdata(9 downto 0);
when "1001" => tv.scalerpre := apbi.pwdata(9 downto 0);
when others => null;
end case;
end if;
-- reset operation
if rst = '0' then
tv.t0ctrl.enable := '0'; tv.t1ctrl.enable := '0';
if WDOGEN then wv.wdog := (others => '1'); wv.wdogtout := '0'; end if;
if BOOTOPT /= memory then
tv.scalerval := std_logic_vector(TPRESC(9 downto 0));
tv.scalerpre := std_logic_vector(TPRESC(9 downto 0));
else
tv.scalerval := (others => '0'); tv.scalerpre := (others => '0');
end if;
tv.tsel := "00";
end if;
rin <= tv; wrin <= wv; -- update registers
apbo.prdata <= rdata; -- drive data bus
end process;
-- Registers
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
wd : if WDOGEN generate
regs : process(clk)
begin
if rising_edge(clk) then
wr <= wrin;
end if;
end process;
end generate;
-- Drive outputs
timo.tick <= r.tick;
timo.irq <= r.t1ctrl.irq & r.t0ctrl.irq;
timo.wdog <= not wr.wdogtout when WDOGEN else '-';
end;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_147 is
port (
output : out std_logic_vector(63 downto 0);
sign : in std_logic;
ge : out std_logic;
in_a : in std_logic_vector(63 downto 0);
in_b : in std_logic_vector(63 downto 0)
);
end sub_147;
architecture augh of sub_147 is
signal carry_inA : std_logic_vector(65 downto 0);
signal carry_inB : std_logic_vector(65 downto 0);
signal carry_res : std_logic_vector(65 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
output <= carry_res(64 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= in_a(63) & in_b(63) & carry_res(64);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "001" or msb_abr = "111") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011" or msb_abr = "111") else
'0';
ge <= tmp_ge;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_147 is
port (
output : out std_logic_vector(63 downto 0);
sign : in std_logic;
ge : out std_logic;
in_a : in std_logic_vector(63 downto 0);
in_b : in std_logic_vector(63 downto 0)
);
end sub_147;
architecture augh of sub_147 is
signal carry_inA : std_logic_vector(65 downto 0);
signal carry_inB : std_logic_vector(65 downto 0);
signal carry_res : std_logic_vector(65 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
output <= carry_res(64 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= in_a(63) & in_b(63) & carry_res(64);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "001" or msb_abr = "111") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011" or msb_abr = "111") else
'0';
ge <= tmp_ge;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_147 is
port (
output : out std_logic_vector(63 downto 0);
sign : in std_logic;
ge : out std_logic;
in_a : in std_logic_vector(63 downto 0);
in_b : in std_logic_vector(63 downto 0)
);
end sub_147;
architecture augh of sub_147 is
signal carry_inA : std_logic_vector(65 downto 0);
signal carry_inB : std_logic_vector(65 downto 0);
signal carry_res : std_logic_vector(65 downto 0);
-- Signals to generate the comparison outputs
signal msb_abr : std_logic_vector(2 downto 0);
signal tmp_sign : std_logic;
signal tmp_eq : std_logic;
signal tmp_le : std_logic;
signal tmp_ge : std_logic;
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
output <= carry_res(64 downto 1);
-- Other comparison outputs
-- Temporary signals
msb_abr <= in_a(63) & in_b(63) & carry_res(64);
tmp_sign <= sign;
tmp_eq <= '1' when in_a = in_b else '0';
tmp_le <=
tmp_eq when msb_abr = "000" or msb_abr = "110" else
'1' when msb_abr = "001" else
'1' when tmp_sign = '0' and (msb_abr = "010" or msb_abr = "001" or msb_abr = "111") else
'1' when tmp_sign = '1' and (msb_abr = "100" or msb_abr = "101") else
'0';
tmp_ge <=
'1' when msb_abr = "000" or msb_abr = "110" else
'1' when tmp_sign = '0' and (msb_abr = "100" or msb_abr = "101") else
'1' when tmp_sign = '1' and (msb_abr = "010" or msb_abr = "011" or msb_abr = "111") else
'0';
ge <= tmp_ge;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1198.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p05n01i01198ent IS
END c08s01b00x00p05n01i01198ent;
ARCHITECTURE c08s01b00x00p05n01i01198arch OF c08s01b00x00p05n01i01198ent IS
signal k : integer := 0;
BEGIN
TESTING: PROCESS
BEGIN
k <= 5 after 5 ns;
wait until 5;
assert FALSE
report "***FAILED TEST: c08s01b00x00p05n01i01198 - Condition clause in wait statement must be boolean expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p05n01i01198arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1198.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p05n01i01198ent IS
END c08s01b00x00p05n01i01198ent;
ARCHITECTURE c08s01b00x00p05n01i01198arch OF c08s01b00x00p05n01i01198ent IS
signal k : integer := 0;
BEGIN
TESTING: PROCESS
BEGIN
k <= 5 after 5 ns;
wait until 5;
assert FALSE
report "***FAILED TEST: c08s01b00x00p05n01i01198 - Condition clause in wait statement must be boolean expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p05n01i01198arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1198.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p05n01i01198ent IS
END c08s01b00x00p05n01i01198ent;
ARCHITECTURE c08s01b00x00p05n01i01198arch OF c08s01b00x00p05n01i01198ent IS
signal k : integer := 0;
BEGIN
TESTING: PROCESS
BEGIN
k <= 5 after 5 ns;
wait until 5;
assert FALSE
report "***FAILED TEST: c08s01b00x00p05n01i01198 - Condition clause in wait statement must be boolean expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p05n01i01198arch;
|
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end architecture rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2953.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p24n01i02953ent IS
END c02s02b00x00p24n01i02953ent;
ARCHITECTURE c02s02b00x00p24n01i02953arch OF c02s02b00x00p24n01i02953ent IS
BEGIN
TESTING: PROCESS
variable a1 : integer := func1 (1); --Failure_here
function func1 (x: in integer) return integer is
begin
return 12;
end;
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p24n01i02953 - Subprogram declaration should appear before call of subprogram."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p24n01i02953arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2953.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p24n01i02953ent IS
END c02s02b00x00p24n01i02953ent;
ARCHITECTURE c02s02b00x00p24n01i02953arch OF c02s02b00x00p24n01i02953ent IS
BEGIN
TESTING: PROCESS
variable a1 : integer := func1 (1); --Failure_here
function func1 (x: in integer) return integer is
begin
return 12;
end;
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p24n01i02953 - Subprogram declaration should appear before call of subprogram."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p24n01i02953arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2953.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p24n01i02953ent IS
END c02s02b00x00p24n01i02953ent;
ARCHITECTURE c02s02b00x00p24n01i02953arch OF c02s02b00x00p24n01i02953ent IS
BEGIN
TESTING: PROCESS
variable a1 : integer := func1 (1); --Failure_here
function func1 (x: in integer) return integer is
begin
return 12;
end;
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p24n01i02953 - Subprogram declaration should appear before call of subprogram."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p24n01i02953arch;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc\CPU_Subsystem_8_bit_pkg.vhd
-- Created: 2014-03-05 16:19:14
--
-- Generated by MATLAB 7.12 and Simulink HDL Coder 2.1
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
PACKAGE CPU_Subsystem_8_bit_pkg IS
TYPE vector_of_unsigned12 IS ARRAY (NATURAL RANGE <>) OF unsigned(11 DOWNTO 0);
END CPU_Subsystem_8_bit_pkg;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/RADIX22FFT_SDNF2_4.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_4
-- Source Path: ifft_16_bit/IFFT HDL Optimized/RADIX22FFT_SDNF2_4
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_4 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
rotate_1 : IN std_logic; -- ufix1
dout_1_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_1_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_3_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_3_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_1_re_1 : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_1_im_1 : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_2_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_2_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_4_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_4;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_4 IS
-- Signals
SIGNAL dout_1_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_1_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_3_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_3_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL dout_1_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_1_im_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_2_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_2_im_tmp : signed(16 DOWNTO 0); -- sfix17
BEGIN
dout_1_re_signed <= signed(dout_1_re);
dout_1_im_signed <= signed(dout_1_im);
dout_3_re_signed <= signed(dout_3_re);
dout_3_im_signed <= signed(dout_3_im);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 18);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, dout_1_re_signed, dout_1_im_signed,
dout_3_re_signed, dout_3_im_signed, dout_1_vld, rotate_1)
VARIABLE sra_temp : signed(17 DOWNTO 0);
VARIABLE sra_temp_0 : signed(17 DOWNTO 0);
VARIABLE sra_temp_1 : signed(17 DOWNTO 0);
VARIABLE sra_temp_2 : signed(17 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_1 /= '0' THEN
IF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(dout_1_re_signed, 18) + resize(dout_3_im_signed, 18);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(dout_1_re_signed, 18) - resize(dout_3_im_signed, 18);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(dout_1_im_signed, 18) + resize(dout_3_re_signed, 18);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(dout_1_im_signed, 18) - resize(dout_3_re_signed, 18);
END IF;
ELSIF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(dout_1_re_signed, 18) + resize(dout_3_re_signed, 18);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(dout_1_re_signed, 18) - resize(dout_3_re_signed, 18);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(dout_1_im_signed, 18) + resize(dout_3_im_signed, 18);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(dout_1_im_signed, 18) - resize(dout_3_im_signed, 18);
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_re_reg, 1);
dout_1_re_tmp <= sra_temp(16 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_im_reg, 1);
dout_1_im_tmp <= sra_temp_0(16 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_re_reg, 1);
dout_2_re_tmp <= sra_temp_1(16 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_im_reg, 1);
dout_2_im_tmp <= sra_temp_2(16 DOWNTO 0);
dout_4_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_2_re <= std_logic_vector(dout_2_re_tmp);
dout_2_im <= std_logic_vector(dout_2_im_tmp);
dout_1_re_1 <= std_logic_vector(dout_1_re_tmp);
dout_1_im_1 <= std_logic_vector(dout_1_im_tmp);
END rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNNCFWNIJI is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000000000000100";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNNCFWNIJI is
Begin
-- Constant
output <= "0000000000000100";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNNCFWNIJI is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000000000000100";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNNCFWNIJI is
Begin
-- Constant
output <= "0000000000000100";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNNCFWNIJI is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000000000000100";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNNCFWNIJI is
Begin
-- Constant
output <= "0000000000000100";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNNCFWNIJI is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000000000000100";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNNCFWNIJI is
Begin
-- Constant
output <= "0000000000000100";
end architecture; |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias2,
S => net1
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => out1,
G => vbias2,
S => net2
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net3,
G => vbias3,
S => net5
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net3,
S => gnd
);
subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net6,
G => net3,
S => gnd
);
subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net6
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net7,
G => vbias4,
S => gnd
);
end simple;
|
-- Std.Textio package body. This file is part of GHDL.
-- Copyright (C) 2002, 2003, 2004, 2005 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING3. If not see
-- <http://www.gnu.org/licenses/>.
package body textio is
attribute foreign : string; --V87
--START-V08
-- LRM08 16.4
-- The JUSTIFY operation formats a string value within a field that is at
-- least at long as required to contain the value. Parameter FIELD
-- specifies the desired field width. Since the actual field width will
-- always be at least large enough to hold the string value, the default
-- value 0 for the FIELD parameter has the effect of causing the string
-- value to be contained in a field of exactly the right widteh (i.e., no
-- additional leading or tailing spaces). Parameter JUSTIFIED specified
-- whether the string value is to be right- or left-justified within the
-- field; the default is right-justified. If the FIELD parameter describes
-- a field width larger than the number of characters in the string value,
-- space characters are used to fill the remaining characters in the field.
--
-- TG: Note that the bounds of the result are not specified!
function Justify (Value: String;
Justified : Side := Right;
Field: Width := 0 ) return String
is
constant len : Width := Value'Length;
begin
if Field <= Len then
return Value;
else
case Justified is
when Right =>
return (1 to Field - Len => ' ') & Value;
when Left =>
return Value & (1 to Field - Len => ' ');
end case;
end if;
end Justify;
--END-V08
-- output routines for standard types
-- TIME_NAMES associates time units with textual names.
-- Textual names are in lower cases, since according to LRM93 14.3:
-- when written, the identifier is expressed in lowercase characters.
-- The length of the names are 3 characters, the last one may be a space
-- for 2 characters long names.
type time_unit is
record
val : time;
name : string (1 to 3);
end record;
type time_names_type is array (1 to 8) of time_unit;
constant time_names : time_names_type :=
((fs, "fs "), (ps, "ps "), (ns, "ns "), (us, "us "),
(ms, "ms "), (sec, "sec"), (min, "min"), (hr, "hr "));
-- Non breaking space character. --!V87
constant nbsp : character := character'val (160); --!V87
function is_whitespace (c : character) return Boolean is
begin
case c is
when ' '
| NBSP --!V87
| HT =>
return True;
when others =>
return False;
end case;
end is_Whitespace;
procedure writeline (variable f: out text; l: inout line) is --V87
procedure writeline (file f: text; l: inout line) is --!V87
begin
if l = null then
-- LRM93 14.3
-- If parameter L contains a null access value at the start of the call,
-- the a null string is written to the file.
null;
else
-- LRM93 14.3
-- Procedure WRITELINE causes the current line designated by parameter L
-- to be written to the file and returns with the value of parameter L
-- designating a null string.
write (f, l.all);
deallocate (l);
l := new string'("");
end if;
write (f, (1 => LF));
end writeline;
--START-V08
procedure Tee (file f : Text; L : inout LINE) is
begin
-- LRM08 16.4 Package TEXTIO
-- The procedure TEE additionally causes the current line to be written
-- to the file OUTPUT.
if l = null then
null;
else
write (f, l.all);
write (Output, l.all);
deallocate (l);
l := new string'("");
end if;
write (f, (1 => LF));
write (output, (1 => LF));
end Tee;
--END-V08
procedure write
(l: inout line; value: in string;
justified: in side := right; field: in width := 0)
is
variable length: natural;
variable nl: line;
begin
-- l can be null.
if l = null then
length := 0;
else
length := l.all'length;
end if;
if value'length < field then
nl := new string (1 to length + field);
if length /= 0 then
nl (1 to length) := l.all;
end if;
if justified = right then
nl (length + 1 to length + field - value'length) := (others => ' ');
nl (nl.all'high - value'length + 1 to nl.all'high) := value;
else
nl (length + 1 to length + value'length) := value;
nl (length + value'length + 1 to nl.all'high) := (others => ' ');
end if;
else
nl := new string (1 to length + value'length);
if length /= 0 then
nl (1 to length) := l.all;
end if;
nl (length + 1 to nl.all'high) := value;
end if;
deallocate (l);
l := nl;
end write;
procedure write
(l: inout line; value: in integer;
justified: in side := right; field: in width := 0)
is
variable str: string (11 downto 1);
variable val: integer := value;
variable digit: natural;
variable index: natural := 0;
begin
-- Note: the absolute value of VAL cannot be directly taken, since
-- it may be greather that the maximum value of an INTEGER.
loop
-- LRM93 7.2.6
-- (A rem B) has the sign of A and an absolute value less then
-- the absoulte value of B.
digit := abs (val rem 10);
val := val / 10;
index := index + 1;
str (index) := character'val(48 + digit);
exit when val = 0;
end loop;
if value < 0 then
index := index + 1;
str(index) := '-';
end if;
write (l, str (index downto 1), justified, field);
end write;
procedure write
(l: inout line; value: in boolean;
justified: in side := right; field: in width := 0)
is
begin
if value then
write (l, string'("TRUE"), justified, field);
else
write (l, string'("FALSE"), justified, field);
end if;
end write;
procedure write
(l: inout line; value: in character;
justified: in side := right; field: in width := 0)
is
variable str: string (1 to 1);
begin
str (1) := value;
write (l, str, justified, field);
end write;
function bit_to_char (value : in bit) return character is
begin
case value is
when '0' =>
return '0';
when '1' =>
return '1';
end case;
end bit_to_char;
procedure write
(l: inout line; value: in bit;
justified: in side := right; field: in width := 0)
is
variable str : string (1 to 1);
begin
str (1) := bit_to_char (value);
write (l, str, justified, field);
end write;
procedure write
(l: inout line; value: in bit_vector;
justified: in side := right; field: in width := 0)
is
constant length : natural := value'length;
alias n_value : bit_vector (1 to value'length) is value;
variable str : string (1 to length);
begin
for i in str'range loop
str (i) := bit_to_char (n_value (i));
end loop;
write (l, str, justified, field);
end write;
procedure write
(l: inout line; value : in time;
justified: in side := right; field: in width := 0; unit : in TIME := ns)
is
-- Copy of VALUE on which we are working.
variable val : time := value;
-- Copy of UNIT on which we are working.
variable un : time := unit;
-- Digit extract from VAL/UN.
variable d : integer; -- natural range 0 to 9;
-- Index for unit name.
variable n : integer;
-- Result.
variable str : string (1 to 28);
-- Current character in RES.
variable pos : natural := 1;
-- Add a character to STR.
procedure add_char (c : character) is
begin
str (pos) := c;
pos := pos + 1;
end add_char;
begin
-- Note:
-- Care is taken to avoid overflow. Time may be 64 bits while integer
-- may be only 32 bits.
-- Handle sign.
-- Note: VAL cannot be negated since its range may be not symetric
-- around 0.
if val < 0 ns then
add_char ('-');
end if;
-- Search for the first digit.
-- Note: we must start from unit, since all units are not a power of 10.
-- Note: UN can be multiplied only after we know it is possible. This
-- is a to avoid overflow.
if un <= 0 sec then
assert false report "UNIT argument is not positive" severity error;
un := ns;
end if;
while val / 10 >= un or val / 10 <= -un loop
un := un * 10;
end loop;
-- Extract digits one per one.
loop
d := val / un;
add_char (character'val (abs d + character'pos ('0')));
val := val - d * un;
exit when val = 0 ns and un <= unit;
if un = unit then
add_char ('.');
end if;
-- Stop as soon as precision will be lost.
-- This can happen only for hr and min.
-- FIXME: change the algorithm to display all the digits.
exit when (un / 10) * 10 /= un;
un := un / 10;
end loop;
add_char (' ');
-- Search the time unit name in the time table.
n := 0;
for i in time_names'range loop
if time_names (i).val = unit then
n := i;
exit;
end if;
end loop;
assert n /= 0 report "UNIT argument is not a unit name" severity error;
if n = 0 then
add_char ('?');
else
add_char (time_names (n).name (1));
add_char (time_names (n).name (2));
if time_names (n).name (3) /= ' ' then
add_char (time_names (n).name (3));
end if;
end if;
-- Write the result.
write (l, str (1 to pos - 1), justified, field);
end write;
procedure textio_write_real
(s : out string; len : out natural; value: real; ndigits : natural);
attribute foreign of textio_write_real : procedure is "GHDL intrinsic";
procedure textio_write_real
(s : out string; len : out natural; value: real; ndigits : natural) is
begin
assert false report "must not be called" severity failure;
end textio_write_real;
-- Parameter DIGITS specifies how many digits to the right of the decimal
-- point are to be output when writing a real number; the default value 0
-- indicates that the number should be output in standard form, consisting
-- of a normalized mantissa plus exponent (e.g., 1.079236E23). If DIGITS is
-- nonzero, then the real number is output as an integer part followed by
-- '.' followed by the fractional part, using the specified number of digits
-- (e.g., 3.14159).
-- Note: Nan, +Inf, -Inf are not to be considered, since these numbers are
-- not in the bounds defined by any real range.
procedure write (L: inout line; value: in real;
justified: in side := right; field: in width := 0;
digits: in natural := 0)
is
-- STR contains the result of the conversion.
variable str : string (1 to 320);
variable len : natural;
begin
textio_write_real (str, len, value, digits);
assert len <= str'length severity failure;
write (l, str (1 to len), justified, field);
end write;
--START-V08
procedure Owrite (L : inout line; value : in Bit_Vector;
Justified : in Side := Right; Field : in Width := 0) is
begin
write (l, to_ostring (value), justified, field);
end Owrite;
procedure Hwrite (L : inout line; value : in Bit_Vector;
Justified : in Side := Right; Field : in Width := 0) is
begin
write (l, to_hstring (value), justified, field);
end Hwrite;
--END-V08
procedure untruncated_text_read --V87
(variable f : text; str : out string; len : out natural); --V87
procedure untruncated_text_read --!V87
(file f : text; str : out string; len : out natural); --!V87
attribute foreign of untruncated_text_read : procedure is "GHDL intrinsic";
procedure untruncated_text_read
(variable f : text; str : out string; len : out natural) is --V87
(file f : text; str : out string; len : out natural) is --!V87
begin
assert false report "must not be called" severity failure;
end untruncated_text_read;
procedure readline (variable f: in text; l: inout line) --V87
procedure readline (file f: text; l: inout line) --!V87
is
variable len, nlen, posn : natural;
variable nl, old_l : line;
variable str : string (1 to 128);
variable is_eol : boolean;
begin
-- LRM93 14.3
-- If parameter L contains a non-null access value at the start of the
-- call, the object designated by that value is deallocated before the
-- new object is created.
if l /= null then
deallocate (l);
end if;
-- End of file is not expected. The user should check endfile before
-- calling readline.
assert not endfile (f)
report "eof in std.textio.readline" severity failure;
-- We read the input in 128-byte chunks.
-- We keep reading until we reach a newline or there is no more input.
-- The loop invariant is that old_l is allocated and contains the
-- previous chunks read, and posn = old_l.all'length.
posn := 0;
loop
untruncated_text_read (f, str, len);
exit when len = 0;
if str (len) = LF then
-- LRM 14.3
-- The representation of the line does not contain the representation
-- of the end of the line.
is_eol := true;
len := len - 1;
-- End of line is any of LF/CR/CR+LF. This is now handled
-- by untruncated_text_read because we need to do a look-ahead.
elsif endfile (f) then
is_eol := true;
else
is_eol := false;
end if;
l := new string (1 to posn + len);
if old_l /= null then
l (1 to posn) := old_l (1 to posn);
deallocate (old_l);
end if;
l (posn + 1 to posn + len) := str (1 to len);
exit when is_eol;
posn := posn + len;
old_l := l;
end loop;
end readline;
-- Replaces L with L (LEFT to/downto L'RIGHT)
procedure trim (l : inout line; left : natural)
is
variable nl : line;
begin
if l = null then
return;
end if;
if l'left < l'right then
-- Ascending.
if left > l'right then
nl := new string'("");
else
nl := new string (left to l'right);
-- nl := new string (1 to l'right + 1 - left);
nl.all := l (left to l'right);
end if;
else
-- Descending
if left < l'right then
nl := new string'("");
else
nl := new string (left downto l'right);
-- nl := new string (left - l'right + 1 downto 1);
nl.all := l (left downto l'right);
end if;
end if;
deallocate (l);
l := nl;
end trim;
-- Replaces L with L (LEFT + 1 to L'RIGHT or LEFT - 1 downto L'RIGHT)
procedure trim_next (l : inout line; left : natural)
is
variable nl : line;
begin
if l = null then
return;
end if;
if l'left < l'right then
-- Ascending.
trim (l, left + 1);
else
-- Descending
trim (l, left - 1);
end if;
end trim_next;
function to_lower (c : character) return character is
begin
if c >= 'A' and c <= 'Z' then
return character'val (character'pos (c) + 32);
else
return c;
end if;
end to_lower;
procedure read (l: inout line; value: out character; good: out boolean)
is
variable nl : line;
begin
if l = null or l'length = 0 then
good := false;
else
value := l (l'left);
trim_next (l, l'left);
good := true;
end if;
end read;
procedure read (l: inout line; value: out character)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "character read failure"
severity failure;
end read;
procedure read (l: inout line; value: out bit; good: out boolean)
is
begin
good := false;
for i in l'range loop
case l(i) is
when ' '
| NBSP --!V87
| HT =>
null;
when '1' =>
value := '1';
good := true;
trim_next (l, i);
return;
when '0' =>
value := '0';
good := true;
trim_next (l, i);
return;
when others =>
return;
end case;
end loop;
return;
end read;
procedure read (l: inout line; value: out bit)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "bit read failure"
severity failure;
end read;
procedure read (l: inout line; value: out bit_vector; good: out boolean)
is
-- Number of bit to parse.
variable len : natural;
variable pos, last : natural;
variable res : bit_vector (1 to value'length);
-- State of the previous byte:
-- LEADING: blank before the bit vector.
-- FOUND: bit of the vector.
type state_type is (leading, found);
variable state : state_type;
begin
-- Initialization.
len := value'length;
if len = 0 then
-- If VALUE is a nul array, return now.
-- L stay unchanged.
-- FIXME: should blanks be removed ?
good := true;
return;
end if;
good := false;
state := leading;
pos := res'left;
for i in l'range loop
case l(i) is
when ' '
| NBSP --!V87
| HT =>
case state is
when leading =>
null;
when found =>
return;
end case;
when '1' | '0' =>
case state is
when leading =>
state := found;
when found =>
null;
end case;
if l(i) = '0' then
res (pos) := '0';
else
res (pos) := '1';
end if;
pos := pos + 1;
len := len - 1;
last := i;
exit when len = 0;
when others =>
return;
end case;
end loop;
if len /= 0 then
-- Not enough bits.
return;
end if;
-- Note: if LEN = 0, then FIRST and LAST have been set.
good := true;
value := res;
trim_next (l, last);
return;
end read;
procedure read (l: inout line; value: out bit_vector)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "bit_vector read failure"
severity failure;
end read;
procedure read (l: inout line; value: out boolean; good: out boolean)
is
-- State:
-- BLANK: space are being scaned.
-- L_TF : T(rue) or F(alse) has been scanned.
-- L_RA : (t)R(ue) or (f)A(lse) has been scanned.
-- L_UL : (tr)U(e) or (fa)L(se) has been scanned.
-- L_ES : (tru)E or (fal)S(e) has been scanned.
type state_type is (blank, l_tf, l_ra, l_ul, l_es);
variable state : state_type;
-- Set to TRUE if T has been scanned, to FALSE if F has been scanned.
variable res : boolean;
variable c : character;
begin
-- By default, it is a failure.
good := false;
state := blank;
for i in l'range loop
c := l (i);
case state is
when blank =>
if is_whitespace (c) then
null;
elsif c = 'f' or c = 'T' then
res := true;
state := l_tf;
elsif c = 'f' or c = 'F' then
res := false;
state := l_tf;
else
return;
end if;
when l_tf =>
if res = true and (c = 'r' or c = 'R') then
state := l_ra;
elsif res = false and (c = 'a' or C = 'A') then
state := l_ra;
else
return;
end if;
when l_ra =>
if res = true and (c = 'u' or C = 'U') then
state := l_ul;
elsif res = false and (c = 'l' or c = 'L') then
state := l_ul;
else
return;
end if;
when l_ul =>
if res = true and (c = 'e' or c = 'E') then
trim_next (l, i);
good := true;
value := true;
return;
elsif res = false and (c = 's' or c = 'S') then
state := l_es;
else
return;
end if;
when l_es =>
if res = false and (c = 'e' or c = 'E') then
trim_next (l, i);
good := true;
value := false;
return;
else
return;
end if;
end case;
end loop;
return;
end read;
procedure read (l: inout line; value: out boolean)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "boolean read failure"
severity failure;
end read;
function char_to_nat (c : character) return natural
is
begin
return character'pos (c) - character'pos ('0');
end char_to_nat;
procedure read (l: inout line; value: out integer; good: out boolean)
is
variable val : integer;
variable d : natural;
type state_t is (leading, sign, digits);
variable cur_state : state_t := leading;
begin
val := 1;
for i in l'range loop
case cur_state is
when leading =>
case l(i) is
when ' '
| NBSP --!V87
| ht =>
null;
when '+' =>
cur_state := sign;
when '-' =>
val := -1;
cur_state := sign;
when '0' to '9' =>
val := char_to_nat (l(i));
cur_state := digits;
when others =>
good := false;
return;
end case;
when sign =>
case l(i) is
when '0' to '9' =>
val := val * char_to_nat (l(i));
cur_state := digits;
when others =>
good := false;
return;
end case;
when digits =>
case l(i) is
when '0' to '9' =>
d := char_to_nat (l(i));
val := val * 10;
if val < 0 then
val := val - d;
else
val := val + d;
end if;
when others =>
trim (l, i);
good := true;
value := val;
return;
end case;
end case;
end loop;
deallocate (l);
l := new string'("");
if cur_state /= leading then
good := true;
value := val;
else
good := false;
end if;
end read;
procedure read (l: inout line; value: out integer)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "integer read failure"
severity failure;
end read;
function textio_read_real (s : string) return real;
attribute foreign of textio_read_real : function is "GHDL intrinsic";
function textio_read_real (s : string) return real is
begin
assert false report "must not be called" severity failure;
return 0.0;
end textio_read_real;
procedure read (l: inout line; value: out real; good: out boolean)
is
-- The parsing is done with a state machine.
-- LEADING: leading blank suppression.
-- SIGN: a sign has been found.
-- DIGITS: integer parts
-- DECIMALS, DECIMALS2: digits after the dot.
-- EXPONENT_SIGN: sign after "E"
-- EXPONENT_1: first digit of the exponent.
-- EXPONENT: digits of the exponent.
type state_t is (leading, sign, digits, decimals, decimals2,
exponent_sign, exponent_1, exponent);
variable state : state_t := leading;
variable left : positive;
procedure set_value (right : positive; off : natural) is
begin
if right > left then
value := textio_read_real (l (left to right - off));
else
value := textio_read_real (l (left downto right + off));
end if;
good := True;
end set_value;
begin
-- By default, parsing has failed.
good := false;
-- Iterate over all characters of the string.
-- Return immediatly in case of parse error.
-- Trim L and call SET_VALUE and return in case of success.
for i in l'range loop
case state is
when leading =>
left := i;
case l (i) is
when ' '
| NBSP --!V87
| ht =>
null;
when '+' | '-' =>
state := sign;
when '0' to '9' =>
state := digits;
when others =>
return;
end case;
when sign =>
case l (i) is
when '0' to '9' =>
state := digits;
when others =>
return;
end case;
when digits =>
case l (i) is
when '0' to '9' =>
null;
when '.' =>
state := decimals;
when others =>
-- A "." (dot) is required in the string.
return;
end case;
when decimals | decimals2 =>
case l (i) is
when '0' to '9' =>
state := decimals2;
when 'e' | 'E' =>
-- "nnn.E" is erroneous.
if state = decimals then
return;
end if;
state := exponent_sign;
when others =>
-- "nnn.XX" is erroneous.
if state = decimals then
return;
end if;
set_value (i, 1);
trim (l, i);
return;
end case;
when exponent_sign =>
case l (i) is
when '+' | '-' =>
state := exponent_1;
when '0' to '9' =>
state := exponent;
when others =>
-- Error.
return;
end case;
when exponent_1 | exponent =>
case l (i) is
when '0' to '9' =>
state := exponent;
when others =>
set_value (i, 1);
trim (l, i);
return;
end case;
end case;
end loop;
-- End of string.
case state is
when leading | sign | digits =>
-- Erroneous.
return;
when decimals =>
-- "nnn.XX" is erroneous.
return;
when decimals2 =>
null;
when exponent_sign =>
-- Erroneous ("NNN.NNNE")
return;
when exponent_1 =>
-- "NNN.NNNE-"
return;
when exponent =>
null;
end case;
set_value (l'right, 0);
deallocate (l);
l := new string'("");
end read;
procedure read (l: inout line; value: out real)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "real read failure"
severity failure;
end read;
procedure read (l: inout line; value: out time; good: out boolean)
is
-- The result.
variable res : time;
-- UNIT is computed from the unit name, the exponent and the number of
-- digits before the dot. UNIT is the weight of the current digit.
variable unit : time;
-- Number of digits before the dot.
variable nbr_digits : integer;
-- True if a unit name has been found. Used temporaly to know the status
-- at the end of the search loop.
variable unit_found : boolean;
-- True if the number is negative.
variable is_neg : boolean;
-- Value of the exponent.
variable exp : integer;
-- True if the exponent is negative.
variable exp_neg : boolean;
-- Unit name extracted from the string.
variable unit_name : string (1 to 3);
-- state is the kind of the previous character parsed.
-- LEADING: leading blanks
-- SIGN: + or - as the first character of the number.
-- DIGITS: digit of the integer part of the number.
-- DOT: dot (.) after the integer part and before the decimal part.
-- DECIMALS: digit of the decimal part.
-- EXPONENT_MARK: e or E.
-- EXPONENT_SIGN: + or - just after the exponent mark (E).
-- EXPONENT: digit of the exponent.
-- UNIT_BLANK: blank after the exponent.
-- UNIT_1, UNIT_2, UNIT_3: first, second, third character of the unit.
type state_type is (leading, sign, digits, dot, decimals,
exponent_mark, exponent_sign, exponent,
unit_blank, unit_1, unit_2, unit_3);
variable state : state_type;
-- Used during the second scan of the string, TRUE is digits is being
-- scaned.
variable has_digits : boolean;
-- Position at the end of the string.
variable pos : integer;
-- Used to compute POS.
variable length : integer;
begin
-- Initialization.
-- Fail by default; therefore, in case of error, a return statement is
-- ok.
good := false;
nbr_digits := 0;
is_neg := false;
exp := 0;
exp_neg := false;
res := 0 sec;
-- Look for exponent and unit name.
-- Parse the string: this loop checks the correctness of the format, and
-- must return (GOOD has been set to FALSE) in case of error.
-- Set: NBR_DIGITS, IS_NEG, EXP, EXP_NEG.
state := leading;
for i in l'range loop
case l (i) is
when ' '
| NBSP --!V87
| HT =>
case state is
when leading | unit_blank =>
null;
when sign | dot | exponent_mark | exponent_sign =>
return;
when digits | decimals | exponent =>
state := unit_blank;
when unit_1 | unit_2 =>
exit;
when unit_3 =>
-- Cannot happen, since an exit is performed at unit_3.
assert false report "internal error" severity failure;
end case;
when '+' | '-' =>
case state is
when leading =>
if l(i) = '-' then
is_neg := true;
end if;
state := sign;
when exponent_mark =>
if l(i) = '-' then
exp_neg := true;
end if;
state := exponent_sign;
when others =>
return;
end case;
when '0' to '9' =>
case state is
when exponent_mark | exponent_sign | exponent =>
exp := exp * 10 + char_to_nat (l (i));
state := exponent;
when leading | sign | digits =>
-- Leading "0" are not significant.
if nbr_digits > 0 or l (i) /= '0' then
nbr_digits := nbr_digits + 1;
end if;
state := digits;
when decimals =>
null;
when dot =>
state := decimals;
when others =>
return;
end case;
when 'a' to 'z' | 'A' to 'Z' =>
case state is
when digits | decimals =>
-- "E" has exponent mark.
if l (i) = 'e' or l(i) = 'E' then
state := exponent_mark;
else
return;
end if;
when unit_blank =>
unit_name (1) := to_lower (l(i));
state := unit_1;
when unit_1 =>
unit_name (2) := to_lower (l(i));
state := unit_2;
pos := i;
when unit_2 =>
unit_name (3) := to_lower (l(i));
state := unit_3;
exit;
when others =>
return;
end case;
when '.' =>
case state is
when digits =>
state := decimals;
when others =>
exit;
end case;
when others =>
exit;
end case;
end loop;
-- A unit name (2 or 3 letters) must have been found.
-- The string may end anywhere.
if state /= unit_2 and state /= unit_3 then
return;
end if;
-- Compute EXP with the sign.
if exp_neg then
exp := -exp;
end if;
-- Search the unit name in the list of time names.
unit_found := false;
for i in time_names'range loop
-- The first two characters must match (case insensitive).
-- The third character must match if:
-- * the unit name is a three characters identifier (ie, not a blank).
-- * there is a third character in STR.
if time_names (i).name (1) = unit_name (1)
and time_names (i).name (2) = unit_name (2)
and (time_names (i).name (3) = ' '
or time_names (i).name (3) = unit_name (3))
then
unit := time_names (i).val;
unit_found := true;
-- POS is set to the position of the first invalid character.
if time_names (i).name (3) = ' ' then
length := 1;
else
length := 2;
end if;
if l'left < l'right then
pos := pos + length;
else
pos := pos - length;
end if;
exit;
end if;
end loop;
if not unit_found then
return;
end if;
-- Compute UNIT, the weight of the first non-significant character.
nbr_digits := nbr_digits + exp - 1;
if nbr_digits < 0 then
unit := unit / 10 ** (-nbr_digits);
else
unit := unit * 10 ** nbr_digits;
end if;
-- HAS_DIGITS will be set as soon as a digit is found.
-- No error is expected here (this has been checked during the first
-- pass).
has_digits := false;
for i in l'range loop
case l (i) is
when ' '
| NBSP --!V87
| HT =>
if has_digits then
exit;
end if;
when '+' | '-' =>
if not has_digits then
has_digits := true;
else
assert false report "internal error" severity failure;
return;
end if;
when '0' to '9' =>
-- Leading "0" are not significant.
if l (i) /= '0' or res /= 0 sec then
res := res + char_to_nat (l (i)) * unit;
unit := unit / 10;
end if;
has_digits := true;
when 'a' to 'z' | 'A' to 'Z' =>
if has_digits then
exit;
else
assert false report "internal error" severity failure;
return;
end if;
when '.' =>
if not has_digits then
assert false report "internal error" severity failure;
return;
end if;
when others =>
assert false report "internal error" severity failure;
return;
end case;
end loop;
-- Set VALUE.
if is_neg then
value := -res;
else
value := res;
end if;
good := true;
trim (l, pos);
return;
end read;
procedure read (l: inout line; value: out time)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "time read failure"
severity failure;
end read;
procedure read (l: inout line; value: out string; good: out boolean)
is
constant len : natural := value'length;
begin
if l'length < len then
good := false;
return;
end if;
good := true;
if len = 0 then
return;
end if;
if l'left < l'right then
-- Ascending (expected common case).
value := l (l'left to l'left + len - 1);
trim (l, l'left + len);
elsif l'left = l'right then
-- String of 1 character. We don't know the direction and therefore
-- can't use the code below which does a slice.
value := l.all;
deallocate (l);
l := new string'("");
else
-- Descending.
value := l (l'left downto l'left - len + 1);
trim (l, l'left - len);
end if;
end read;
procedure read (l: inout line; value: out string)
is
variable res : boolean;
begin
read (l, value, res);
assert res = true
report "string read failure"
severity failure;
end read;
--START-V08
procedure Sread (L : inout Line; Value : out String; Strlen : out Natural)
is
constant maxlen : natural := Value'Length;
alias value1 : string (1 to maxlen) is Value;
variable skipping : boolean := True;
variable f, len, nl_left : natural;
variable nl : line;
begin
-- Skip leading spaces. F designates the index of the first non-space
-- character, LEN the length of the extracted string.
len := 0;
for i in l'range loop
if skipping then
if not is_whitespace (l (i)) then
skipping := false;
f := i;
len := 1;
end if;
else
exit when is_whitespace (l (i));
len := len + 1;
exit when len = maxlen;
end if;
end loop;
-- Copy string.
if l'ascending then
value1 (1 to len) := l (f to f + len - 1);
else
value1 (1 to len) := l (f downto f - len + 1);
end if;
strlen := len;
if l'ascending then
if len = 0 then
f := l'right + 1;
end if;
nl_left := f + len;
nl := new string (nl_left to l'right);
nl.all := l (nl_left to l'right);
else
if len = 0 then
f := l'right - 1;
end if;
nl_left := f - len;
nl := new string (nl_left downto l'right);
nl.all := l (nl_left downto l'right);
end if;
deallocate (l);
l := nl;
end sread;
subtype bv4 is bit_vector (1 to 4);
function char_to_bv4 (c : character) return bv4 is
begin
case c is
when '0' => return "0000";
when '1' => return "0001";
when '2' => return "0010";
when '3' => return "0011";
when '4' => return "0100";
when '5' => return "0101";
when '6' => return "0110";
when '7' => return "0111";
when '8' => return "1000";
when '9' => return "1001";
when 'a' | 'A' => return "1010";
when 'b' | 'B' => return "1011";
when 'c' | 'C' => return "1100";
when 'd' | 'D' => return "1101";
when 'e' | 'E' => return "1110";
when 'f' | 'F' => return "1111";
when others =>
assert false report "bad hexa digit" severity failure;
end case;
end char_to_bv4;
procedure Oread (L : inout Line; Value : out Bit_Vector; Good : out Boolean)
is
-- Length of Value
constant vlen : natural := value'length;
-- Number of octal digits for Value
constant olen : natural := (vlen + 2) / 3;
variable res : bit_vector (1 to olen * 3);
-- Number of bit to parse.
variable len : natural;
variable pos : natural;
-- Last character from LEN to be removed
variable last : integer;
-- State of the previous byte:
-- SKIP: blank before the bit vector.
-- DIGIT: previous character was a digit
-- UNDERSCORE: was '_'
type state_type is (skip, digit, underscore);
variable state : state_type;
begin
-- Initialization.
if vlen = 0 then
-- If VALUE is a nul array, return now.
-- L stay unchanged.
-- FIXME: should blanks be removed ?
good := true;
return;
end if;
good := false;
state := skip;
pos := res'left;
if l'ascending then
last := l'left - 1;
else
last := l'left + 1;
end if;
for i in l'range loop
case l (i) is
when ' '
| NBSP
| HT =>
exit when state /= skip;
when '_' =>
exit when state /= digit;
state := underscore;
when '0' to '7' =>
res (pos to pos + 2) := char_to_bv4 (l (i)) (2 to 4);
last := i;
state := digit;
pos := pos + 3;
-- LRM08 16.4
-- Character removal and compostion also stops when the expected
-- number of digits have been removed.
exit when pos = res'right + 1;
when others =>
exit;
end case;
end loop;
-- LRM08 16.4
-- The OREAD or HEAD procedure does not succeed if less than the expected
-- number of digits are removed.
if pos /= res'right + 1 then
return;
end if;
-- LRM08 16.4
-- The rightmost value'length bits of the binary number are used to form
-- the result for the VALUE parameter, [with a '0' element corresponding
-- to a 0 bit and a '1' element corresponding to a 1 bit]. The OREAD or
-- HREAD procedure does not succeed if any unused bits are 1.
for i in 1 to res'right - vlen loop
if res (i) = '1' then
return;
end if;
end loop;
Value := res (res'right - vlen + 1 to res'right);
good := true;
trim_next (l, last);
end Oread;
procedure Oread (L : inout Line; Value : out Bit_Vector)
is
variable res : boolean;
begin
Oread (l, value, res);
assert res = true
report "octal bit_vector read failure"
severity failure;
end Oread;
procedure Hread (L : inout Line; Value : out Bit_Vector; Good : out Boolean)
is
-- Length of Value
constant vlen : natural := value'length;
-- Number of hexa digits for Value
constant hlen : natural := (vlen + 3) / 4;
variable res : bit_vector (1 to hlen * 4);
-- Number of bit to parse.
variable len : natural;
variable pos : natural;
-- Last character from LEN to be removed
variable last : integer;
-- State of the previous byte:
-- SKIP: blank before the bit vector.
-- DIGIT: previous character was a digit
-- UNDERSCORE: was '_'
type state_type is (skip, digit, underscore);
variable state : state_type;
begin
-- Initialization.
if vlen = 0 then
-- If VALUE is a nul array, return now.
-- L stay unchanged.
-- FIXME: should blanks be removed ?
good := true;
return;
end if;
good := false;
state := skip;
pos := res'left;
if l'ascending then
last := l'left - 1;
else
last := l'left + 1;
end if;
for i in l'range loop
case l (i) is
when ' '
| NBSP
| HT =>
exit when state /= skip;
when '_' =>
exit when state /= digit;
state := underscore;
when '0' to '9' | 'a' to 'f' | 'A' to 'F' =>
res (pos to pos + 3) := char_to_bv4 (l (i));
last := i;
state := digit;
pos := pos + 4;
-- LRM08 16.4
-- Character removal and compostion also stops when the expected
-- number of digits have been removed.
exit when pos = res'right + 1;
when others =>
exit;
end case;
end loop;
-- LRM08 16.4
-- The OREAD or HEAD procedure does not succeed if less than the expected
-- number of digits are removed.
if pos /= res'right + 1 then
return;
end if;
-- LRM08 16.4
-- The rightmost value'length bits of the binary number are used to form
-- the result for the VALUE parameter, [with a '0' element corresponding
-- to a 0 bit and a '1' element corresponding to a 1 bit]. The OREAD or
-- HREAD procedure does not succeed if any unused bits are 1.
for i in 1 to res'right - vlen loop
if res (i) = '1' then
return;
end if;
end loop;
Value := res (res'right - vlen + 1 to res'right);
good := true;
trim_next (l, last);
end Hread;
procedure Hread (L : inout Line; Value : out Bit_Vector)
is
variable res : boolean;
begin
Hread (l, value, res);
assert res = true
report "hexa bit_vector read failure"
severity failure;
end Hread;
--END-V08
end textio;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
-- Date : Sun Mar 13 07:43:23 2016
-- Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/SKL/Desktop/ECE532/project_work/integrated/test/project_2.srcs/sources_1/ip/dcfifo_32in_32out_8kb/dcfifo_32in_32out_8kb_funcsim.vhdl
-- Design : dcfifo_32in_32out_8kb
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end dcfifo_32in_32out_8kb_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of dcfifo_32in_32out_8kb_blk_mem_gen_prim_wrapper is
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35\ : STD_LOGIC;
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(13) => '0',
ADDRARDADDR(12 downto 5) => \gc0.count_d1_reg[7]\(7 downto 0),
ADDRARDADDR(4) => '0',
ADDRARDADDR(3) => '0',
ADDRARDADDR(2) => '0',
ADDRARDADDR(1) => '0',
ADDRARDADDR(0) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12 downto 5) => \gic0.gc0.count_d2_reg[7]\(7 downto 0),
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CLKARDCLK => rd_clk,
CLKBWRCLK => wr_clk,
DIADI(15 downto 0) => din(15 downto 0),
DIBDI(15 downto 0) => din(31 downto 16),
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(15 downto 0) => dout(15 downto 0),
DOBDO(15 downto 0) => dout(31 downto 16),
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_32\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_33\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_34\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_n_35\,
ENARDEN => tmp_ram_rd_en,
ENBWREN => WEBWE(0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => Q(0),
RSTRAMB => Q(0),
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(3) => WEBWE(0),
WEBWE(2) => WEBWE(0),
WEBWE(1) => WEBWE(0),
WEBWE(0) => WEBWE(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_rd_bin_cntr is
port (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
WR_PNTR_RD : in STD_LOGIC_VECTOR ( 7 downto 0 );
rd_en : in STD_LOGIC;
p_18_out : in STD_LOGIC;
\wr_pntr_bin_reg[6]\ : in STD_LOGIC;
\wr_pntr_bin_reg[5]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_rd_bin_cntr : entity is "rd_bin_cntr";
end dcfifo_32in_32out_8kb_rd_bin_cntr;
architecture STRUCTURE of dcfifo_32in_32out_8kb_rd_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.wide_prim18.ram\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \gc0.count[7]_i_2_n_0\ : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 7 downto 0 );
signal ram_empty_i_i_4_n_0 : STD_LOGIC;
signal ram_empty_i_i_5_n_0 : STD_LOGIC;
signal ram_empty_i_i_6_n_0 : STD_LOGIC;
signal ram_empty_i_i_7_n_0 : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gc0.count[7]_i_2\ : label is "soft_lutpair7";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(7 downto 0) <= \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rd_pntr_plus1(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => rd_pntr_plus1(0),
I1 => rd_pntr_plus1(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => rd_pntr_plus1(0),
I1 => rd_pntr_plus1(1),
I2 => rd_pntr_plus1(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => rd_pntr_plus1(0),
I2 => rd_pntr_plus1(1),
I3 => rd_pntr_plus1(2),
O => plusOp(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => rd_pntr_plus1(4),
I1 => rd_pntr_plus1(2),
I2 => rd_pntr_plus1(1),
I3 => rd_pntr_plus1(0),
I4 => rd_pntr_plus1(3),
O => plusOp(4)
);
\gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => rd_pntr_plus1(5),
I1 => rd_pntr_plus1(3),
I2 => rd_pntr_plus1(0),
I3 => rd_pntr_plus1(1),
I4 => rd_pntr_plus1(2),
I5 => rd_pntr_plus1(4),
O => plusOp(5)
);
\gc0.count[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => rd_pntr_plus1(6),
I1 => rd_pntr_plus1(4),
I2 => \gc0.count[7]_i_2_n_0\,
I3 => rd_pntr_plus1(3),
I4 => rd_pntr_plus1(5),
O => plusOp(6)
);
\gc0.count[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => rd_pntr_plus1(7),
I1 => rd_pntr_plus1(5),
I2 => rd_pntr_plus1(3),
I3 => \gc0.count[7]_i_2_n_0\,
I4 => rd_pntr_plus1(4),
I5 => rd_pntr_plus1(6),
O => plusOp(7)
);
\gc0.count[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => rd_pntr_plus1(2),
I1 => rd_pntr_plus1(1),
I2 => rd_pntr_plus1(0),
O => \gc0.count[7]_i_2_n_0\
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(0),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(1),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(2),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(3),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(4),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4)
);
\gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(5),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5)
);
\gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(6),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(6)
);
\gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => rd_pntr_plus1(7),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => plusOp(0),
PRE => Q(0),
Q => rd_pntr_plus1(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => plusOp(1),
Q => rd_pntr_plus1(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => plusOp(2),
Q => rd_pntr_plus1(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => plusOp(3),
Q => rd_pntr_plus1(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => plusOp(4),
Q => rd_pntr_plus1(4)
);
\gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => plusOp(5),
Q => rd_pntr_plus1(5)
);
\gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => plusOp(6),
Q => rd_pntr_plus1(6)
);
\gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => Q(0),
D => plusOp(7),
Q => rd_pntr_plus1(7)
);
ram_empty_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \wr_pntr_bin_reg[6]\,
I1 => \wr_pntr_bin_reg[5]\,
I2 => ram_empty_i_i_4_n_0,
I3 => ram_empty_i_i_5_n_0,
I4 => ram_empty_i_i_6_n_0,
I5 => ram_empty_i_i_7_n_0,
O => ram_empty_i_reg
);
ram_empty_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2),
I1 => WR_PNTR_RD(2),
I2 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3),
I3 => WR_PNTR_RD(3),
O => ram_empty_i_i_4_n_0
);
ram_empty_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => rd_pntr_plus1(6),
I1 => WR_PNTR_RD(6),
I2 => rd_pntr_plus1(7),
I3 => WR_PNTR_RD(7),
I4 => WR_PNTR_RD(2),
I5 => rd_pntr_plus1(2),
O => ram_empty_i_i_5_n_0
);
ram_empty_i_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"0090000000000090"
)
port map (
I0 => rd_pntr_plus1(5),
I1 => WR_PNTR_RD(5),
I2 => rd_en,
I3 => p_18_out,
I4 => WR_PNTR_RD(4),
I5 => rd_pntr_plus1(4),
O => ram_empty_i_i_6_n_0
);
ram_empty_i_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => WR_PNTR_RD(3),
I2 => rd_pntr_plus1(0),
I3 => WR_PNTR_RD(0),
I4 => WR_PNTR_RD(1),
I5 => rd_pntr_plus1(1),
O => ram_empty_i_i_7_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_rd_status_flags_as is
port (
empty : out STD_LOGIC;
p_18_out : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\wr_pntr_bin_reg[6]\ : in STD_LOGIC;
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_rd_status_flags_as : entity is "rd_status_flags_as";
end dcfifo_32in_32out_8kb_rd_status_flags_as;
architecture STRUCTURE of dcfifo_32in_32out_8kb_rd_status_flags_as is
signal \^p_18_out\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
p_18_out <= \^p_18_out\;
\gc0.count_d1[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => \^p_18_out\,
O => E(0)
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \wr_pntr_bin_reg[6]\,
PRE => Q(0),
Q => \^p_18_out\
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \wr_pntr_bin_reg[6]\,
PRE => Q(0),
Q => empty
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_reset_blk_ramfifo is
port (
rst_full_ff_i : out STD_LOGIC;
rst_full_gen_i : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_reg[0]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
p_18_out : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end dcfifo_32in_32out_8kb_reset_blk_ramfifo;
architecture STRUCTURE of dcfifo_32in_32out_8kb_reset_blk_ramfifo is
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\ : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_asreg_d1 : STD_LOGIC;
signal rd_rst_asreg_d2 : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
signal rst_d2 : STD_LOGIC;
signal rst_d3 : STD_LOGIC;
signal rst_rd_reg1 : STD_LOGIC;
signal rst_rd_reg2 : STD_LOGIC;
signal rst_wr_reg1 : STD_LOGIC;
signal rst_wr_reg2 : STD_LOGIC;
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_asreg_d1 : STD_LOGIC;
signal wr_rst_asreg_d2 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
begin
Q(2 downto 0) <= \^q\(2 downto 0);
rst_full_ff_i <= rst_d2;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => \^q\(0),
I1 => p_18_out,
I2 => rd_en,
O => tmp_ram_rd_en
);
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => rst,
D => rst_d3,
Q => rst_full_gen_i
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1,
PRE => rst,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d2,
PRE => rst,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rd_rst_asreg,
Q => rd_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rd_rst_asreg_d1,
Q => rd_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d1,
O => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => \^q\(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => \^q\(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0\,
Q => \^q\(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rst_rd_reg1,
PRE => rst,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => rst_wr_reg1,
PRE => rst,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => wr_rst_asreg,
Q => wr_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => wr_rst_asreg_d1,
Q => wr_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d1,
O => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d2,
O => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\,
Q => \gic0.gc0.count_reg[0]\(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0\,
Q => \gic0.gc0.count_reg[0]\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_synchronizer_ff is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_synchronizer_ff : entity is "synchronizer_ff";
end dcfifo_32in_32out_8kb_synchronizer_ff;
architecture STRUCTURE of dcfifo_32in_32out_8kb_synchronizer_ff is
signal Q_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
begin
D(7 downto 0) <= Q_reg(7 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(7),
Q => Q_reg(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_synchronizer_ff_0 is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_synchronizer_ff_0 : entity is "synchronizer_ff";
end dcfifo_32in_32out_8kb_synchronizer_ff_0;
architecture STRUCTURE of dcfifo_32in_32out_8kb_synchronizer_ff_0 is
signal Q_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
begin
D(7 downto 0) <= Q_reg(7 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => Q(7),
Q => Q_reg(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_synchronizer_ff_1 is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\wr_pntr_bin_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
D : in STD_LOGIC_VECTOR ( 7 downto 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_synchronizer_ff_1 : entity is "synchronizer_ff";
end dcfifo_32in_32out_8kb_synchronizer_ff_1;
architecture STRUCTURE of dcfifo_32in_32out_8kb_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^wr_pntr_bin_reg[6]\ : STD_LOGIC_VECTOR ( 6 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
begin
\out\(0) <= Q_reg(7);
\wr_pntr_bin_reg[6]\(6 downto 0) <= \^wr_pntr_bin_reg[6]\(6 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(7),
Q => Q_reg(7)
);
\wr_pntr_bin[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(1),
I2 => Q_reg(0),
I3 => \^wr_pntr_bin_reg[6]\(3),
O => \^wr_pntr_bin_reg[6]\(0)
);
\wr_pntr_bin[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(1),
I2 => \^wr_pntr_bin_reg[6]\(3),
O => \^wr_pntr_bin_reg[6]\(1)
);
\wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(3),
I1 => Q_reg(7),
I2 => Q_reg(5),
I3 => Q_reg(6),
I4 => Q_reg(4),
I5 => Q_reg(2),
O => \^wr_pntr_bin_reg[6]\(2)
);
\wr_pntr_bin[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(6),
I2 => Q_reg(5),
I3 => Q_reg(7),
I4 => Q_reg(3),
O => \^wr_pntr_bin_reg[6]\(3)
);
\wr_pntr_bin[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(5),
I2 => Q_reg(6),
I3 => Q_reg(4),
O => \^wr_pntr_bin_reg[6]\(4)
);
\wr_pntr_bin[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(5),
I2 => Q_reg(7),
O => \^wr_pntr_bin_reg[6]\(5)
);
\wr_pntr_bin[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(7),
O => \^wr_pntr_bin_reg[6]\(6)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_synchronizer_ff_2 is
port (
\out\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\rd_pntr_bin_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
D : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_synchronizer_ff_2 : entity is "synchronizer_ff";
end dcfifo_32in_32out_8kb_synchronizer_ff_2;
architecture STRUCTURE of dcfifo_32in_32out_8kb_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^rd_pntr_bin_reg[6]\ : STD_LOGIC_VECTOR ( 6 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[4]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[5]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[5]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[6]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[6]\ : label is "yes";
attribute ASYNC_REG of \Q_reg_reg[7]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[7]\ : label is "yes";
begin
\out\(0) <= Q_reg(7);
\rd_pntr_bin_reg[6]\(6 downto 0) <= \^rd_pntr_bin_reg[6]\(6 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(3),
Q => Q_reg(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(4),
Q => Q_reg(4)
);
\Q_reg_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(5),
Q => Q_reg(5)
);
\Q_reg_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(6),
Q => Q_reg(6)
);
\Q_reg_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => D(7),
Q => Q_reg(7)
);
\rd_pntr_bin[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(1),
I2 => Q_reg(0),
I3 => \^rd_pntr_bin_reg[6]\(3),
O => \^rd_pntr_bin_reg[6]\(0)
);
\rd_pntr_bin[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(1),
I2 => \^rd_pntr_bin_reg[6]\(3),
O => \^rd_pntr_bin_reg[6]\(1)
);
\rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => Q_reg(3),
I1 => Q_reg(7),
I2 => Q_reg(5),
I3 => Q_reg(6),
I4 => Q_reg(4),
I5 => Q_reg(2),
O => \^rd_pntr_bin_reg[6]\(2)
);
\rd_pntr_bin[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => Q_reg(4),
I1 => Q_reg(6),
I2 => Q_reg(5),
I3 => Q_reg(7),
I4 => Q_reg(3),
O => \^rd_pntr_bin_reg[6]\(3)
);
\rd_pntr_bin[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => Q_reg(7),
I1 => Q_reg(5),
I2 => Q_reg(6),
I3 => Q_reg(4),
O => \^rd_pntr_bin_reg[6]\(4)
);
\rd_pntr_bin[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(5),
I2 => Q_reg(7),
O => \^rd_pntr_bin_reg[6]\(5)
);
\rd_pntr_bin[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(6),
I1 => Q_reg(7),
O => \^rd_pntr_bin_reg[6]\(6)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_wr_bin_cntr is
port (
ram_full_fb_i_reg : out STD_LOGIC;
\wr_data_count_i_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
\gic0.gc0.count_d2_reg[7]_0\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_en : in STD_LOGIC;
p_1_out : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_wr_bin_cntr : entity is "wr_bin_cntr";
end dcfifo_32in_32out_8kb_wr_bin_cntr;
architecture STRUCTURE of dcfifo_32in_32out_8kb_wr_bin_cntr is
signal \^device_7series.no_bmm_info.sdp.wide_prim18.ram\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \gic0.gc0.count[7]_i_2_n_0\ : STD_LOGIC;
signal \^gic0.gc0.count_d2_reg[7]_0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[0]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gic0.gc0.count[4]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gic0.gc0.count[6]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gic0.gc0.count[7]_i_1\ : label is "soft_lutpair10";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(7 downto 0) <= \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7 downto 0);
Q(5 downto 0) <= \^q\(5 downto 0);
\gic0.gc0.count_d2_reg[7]_0\(7 downto 0) <= \^gic0.gc0.count_d2_reg[7]_0\(7 downto 0);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => wr_pntr_plus2(0),
O => \plusOp__0\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => wr_pntr_plus2(1),
O => \plusOp__0\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => wr_pntr_plus2(1),
I2 => \^q\(0),
O => \plusOp__0\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => wr_pntr_plus2(1),
I1 => wr_pntr_plus2(0),
I2 => \^q\(0),
I3 => \^q\(1),
O => \plusOp__0\(3)
);
\gic0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(0),
I1 => wr_pntr_plus2(0),
I2 => wr_pntr_plus2(1),
I3 => \^q\(1),
I4 => \^q\(2),
O => \plusOp__0\(4)
);
\gic0.gc0.count[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(1),
I1 => wr_pntr_plus2(1),
I2 => wr_pntr_plus2(0),
I3 => \^q\(0),
I4 => \^q\(2),
I5 => \^q\(3),
O => \plusOp__0\(5)
);
\gic0.gc0.count[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count[7]_i_2_n_0\,
I1 => \^q\(4),
O => \plusOp__0\(6)
);
\gic0.gc0.count[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \gic0.gc0.count[7]_i_2_n_0\,
I1 => \^q\(4),
I2 => \^q\(5),
O => \plusOp__0\(7)
);
\gic0.gc0.count[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => wr_pntr_plus2(1),
I3 => wr_pntr_plus2(0),
I4 => \^q\(0),
I5 => \^q\(2),
O => \gic0.gc0.count[7]_i_2_n_0\
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => wr_pntr_plus2(0),
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
Q => \^gic0.gc0.count_d2_reg[7]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => wr_pntr_plus2(1),
Q => \^gic0.gc0.count_d2_reg[7]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(0),
Q => \^gic0.gc0.count_d2_reg[7]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[7]_0\(3)
);
\gic0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[7]_0\(4)
);
\gic0.gc0.count_d1_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[7]_0\(5)
);
\gic0.gc0.count_d1_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(4),
Q => \^gic0.gc0.count_d2_reg[7]_0\(6)
);
\gic0.gc0.count_d1_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^q\(5),
Q => \^gic0.gc0.count_d2_reg[7]_0\(7)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(0),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(1),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(2),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(3),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3)
);
\gic0.gc0.count_d2_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(4),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4)
);
\gic0.gc0.count_d2_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(5),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5)
);
\gic0.gc0.count_d2_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(6),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(6)
);
\gic0.gc0.count_d2_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \^gic0.gc0.count_d2_reg[7]_0\(7),
Q => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(0),
Q => wr_pntr_plus2(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__0\(1),
PRE => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
Q => wr_pntr_plus2(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(2),
Q => \^q\(0)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(3),
Q => \^q\(1)
);
\gic0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(4),
Q => \^q\(2)
);
\gic0.gc0.count_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(5),
Q => \^q\(3)
);
\gic0.gc0.count_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(6),
Q => \^q\(4)
);
\gic0.gc0.count_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => \plusOp__0\(7),
Q => \^q\(5)
);
ram_full_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0090000000000090"
)
port map (
I0 => RD_PNTR_WR(0),
I1 => wr_pntr_plus2(0),
I2 => wr_en,
I3 => p_1_out,
I4 => wr_pntr_plus2(1),
I5 => RD_PNTR_WR(1),
O => ram_full_fb_i_reg
);
\wr_data_count_i[7]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(0),
I1 => RD_PNTR_WR(0),
O => S(0)
);
\wr_data_count_i[7]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7),
I1 => RD_PNTR_WR(7),
O => \wr_data_count_i_reg[7]\(3)
);
\wr_data_count_i[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(6),
I1 => RD_PNTR_WR(6),
O => \wr_data_count_i_reg[7]\(2)
);
\wr_data_count_i[7]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(5),
I1 => RD_PNTR_WR(5),
O => \wr_data_count_i_reg[7]\(1)
);
\wr_data_count_i[7]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(4),
I1 => RD_PNTR_WR(4),
O => \wr_data_count_i_reg[7]\(0)
);
\wr_data_count_i[7]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(3),
I1 => RD_PNTR_WR(3),
O => S(3)
);
\wr_data_count_i[7]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(2),
I1 => RD_PNTR_WR(2),
O => S(2)
);
\wr_data_count_i[7]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(1),
I1 => RD_PNTR_WR(1),
O => S(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_wr_dc_as is
port (
wr_data_count : out STD_LOGIC_VECTOR ( 1 downto 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gic0.gc0.count_d2_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_wr_dc_as : entity is "wr_dc_as";
end dcfifo_32in_32out_8kb_wr_dc_as;
architecture STRUCTURE of dcfifo_32in_32out_8kb_wr_dc_as is
signal minusOp : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \wr_data_count_i_reg[7]_i_1_n_1\ : STD_LOGIC;
signal \wr_data_count_i_reg[7]_i_1_n_2\ : STD_LOGIC;
signal \wr_data_count_i_reg[7]_i_1_n_3\ : STD_LOGIC;
signal \wr_data_count_i_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \wr_data_count_i_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \wr_data_count_i_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \wr_data_count_i_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \NLW_wr_data_count_i_reg[7]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
\wr_data_count_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => minusOp(6),
Q => wr_data_count(0)
);
\wr_data_count_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
D => minusOp(7),
Q => wr_data_count(1)
);
\wr_data_count_i_reg[7]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \wr_data_count_i_reg[7]_i_2_n_0\,
CO(3) => \NLW_wr_data_count_i_reg[7]_i_1_CO_UNCONNECTED\(3),
CO(2) => \wr_data_count_i_reg[7]_i_1_n_1\,
CO(1) => \wr_data_count_i_reg[7]_i_1_n_2\,
CO(0) => \wr_data_count_i_reg[7]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => \gic0.gc0.count_d2_reg[6]\(6 downto 4),
O(3 downto 0) => minusOp(7 downto 4),
S(3 downto 0) => \gic0.gc0.count_d2_reg[7]\(3 downto 0)
);
\wr_data_count_i_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \wr_data_count_i_reg[7]_i_2_n_0\,
CO(2) => \wr_data_count_i_reg[7]_i_2_n_1\,
CO(1) => \wr_data_count_i_reg[7]_i_2_n_2\,
CO(0) => \wr_data_count_i_reg[7]_i_2_n_3\,
CYINIT => '1',
DI(3 downto 0) => \gic0.gc0.count_d2_reg[6]\(3 downto 0),
O(3 downto 0) => minusOp(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_wr_status_flags_as is
port (
full : out STD_LOGIC;
p_1_out : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_i : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_wr_status_flags_as : entity is "wr_status_flags_as";
end dcfifo_32in_32out_8kb_wr_status_flags_as;
architecture STRUCTURE of dcfifo_32in_32out_8kb_wr_status_flags_as is
signal \^p_1_out\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
p_1_out <= \^p_1_out\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => \^p_1_out\,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_full_ff_i,
Q => \^p_1_out\
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_full_ff_i,
Q => full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end dcfifo_32in_32out_8kb_blk_mem_gen_prim_width;
architecture STRUCTURE of dcfifo_32in_32out_8kb_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.dcfifo_32in_32out_8kb_blk_mem_gen_prim_wrapper
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => \gic0.gc0.count_d2_reg[7]\(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_clk_x_pntrs is
port (
ram_empty_i_reg : out STD_LOGIC;
WR_PNTR_RD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ram_empty_i_reg_0 : out STD_LOGIC;
RD_PNTR_WR : out STD_LOGIC_VECTOR ( 7 downto 0 );
ram_full_i : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_reg[7]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\gic0.gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
rst_full_gen_i : in STD_LOGIC;
\rd_pntr_bin_reg[0]_0\ : in STD_LOGIC;
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_clk_x_pntrs : entity is "clk_x_pntrs";
end dcfifo_32in_32out_8kb_clk_x_pntrs;
architecture STRUCTURE of dcfifo_32in_32out_8kb_clk_x_pntrs is
signal \^rd_pntr_wr\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^wr_pntr_rd\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \gntv_or_sync_fifo.gl0.wr/gwas.wsts/comp1\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_1\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_2\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_3\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_5\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_6\ : STD_LOGIC;
signal \gsync_stage[2].wr_stg_inst_n_7\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 6 downto 0 );
signal p_0_in6_out : STD_LOGIC_VECTOR ( 6 downto 0 );
signal p_0_out : STD_LOGIC_VECTOR ( 7 to 7 );
signal p_1_out : STD_LOGIC_VECTOR ( 7 to 7 );
signal p_2_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal ram_full_i_i_2_n_0 : STD_LOGIC;
signal ram_full_i_i_4_n_0 : STD_LOGIC;
signal ram_full_i_i_6_n_0 : STD_LOGIC;
signal ram_full_i_i_7_n_0 : STD_LOGIC;
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \rd_pntr_gc[0]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[1]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[2]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[3]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[4]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[5]_i_1_n_0\ : STD_LOGIC;
signal \rd_pntr_gc[6]_i_1_n_0\ : STD_LOGIC;
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rd_pntr_gc[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rd_pntr_gc[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rd_pntr_gc[2]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rd_pntr_gc[3]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \rd_pntr_gc[4]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rd_pntr_gc[5]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \wr_pntr_gc[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_gc[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_gc[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wr_pntr_gc[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wr_pntr_gc[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wr_pntr_gc[5]_i_1\ : label is "soft_lutpair2";
begin
RD_PNTR_WR(7 downto 0) <= \^rd_pntr_wr\(7 downto 0);
WR_PNTR_RD(7 downto 0) <= \^wr_pntr_rd\(7 downto 0);
\gsync_stage[1].rd_stg_inst\: entity work.dcfifo_32in_32out_8kb_synchronizer_ff
port map (
D(7 downto 0) => p_3_out(7 downto 0),
Q(7 downto 0) => wr_pntr_gc(7 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
rd_clk => rd_clk
);
\gsync_stage[1].wr_stg_inst\: entity work.dcfifo_32in_32out_8kb_synchronizer_ff_0
port map (
D(7 downto 0) => p_2_out(7 downto 0),
Q(7 downto 0) => rd_pntr_gc(7 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
wr_clk => wr_clk
);
\gsync_stage[2].rd_stg_inst\: entity work.dcfifo_32in_32out_8kb_synchronizer_ff_1
port map (
D(7 downto 0) => p_3_out(7 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(0) => p_1_out(7),
rd_clk => rd_clk,
\wr_pntr_bin_reg[6]\(6 downto 0) => p_0_in(6 downto 0)
);
\gsync_stage[2].wr_stg_inst\: entity work.dcfifo_32in_32out_8kb_synchronizer_ff_2
port map (
D(7 downto 0) => p_2_out(7 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
\out\(0) => p_0_out(7),
\rd_pntr_bin_reg[6]\(6) => \gsync_stage[2].wr_stg_inst_n_1\,
\rd_pntr_bin_reg[6]\(5) => \gsync_stage[2].wr_stg_inst_n_2\,
\rd_pntr_bin_reg[6]\(4) => \gsync_stage[2].wr_stg_inst_n_3\,
\rd_pntr_bin_reg[6]\(3) => \gsync_stage[2].wr_stg_inst_n_4\,
\rd_pntr_bin_reg[6]\(2) => \gsync_stage[2].wr_stg_inst_n_5\,
\rd_pntr_bin_reg[6]\(1) => \gsync_stage[2].wr_stg_inst_n_6\,
\rd_pntr_bin_reg[6]\(0) => \gsync_stage[2].wr_stg_inst_n_7\,
wr_clk => wr_clk
);
ram_empty_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^wr_pntr_rd\(6),
I1 => Q(6),
I2 => \^wr_pntr_rd\(1),
I3 => Q(1),
I4 => Q(0),
I5 => \^wr_pntr_rd\(0),
O => ram_empty_i_reg_0
);
ram_empty_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^wr_pntr_rd\(5),
I1 => Q(5),
I2 => \^wr_pntr_rd\(4),
I3 => Q(4),
I4 => Q(7),
I5 => \^wr_pntr_rd\(7),
O => ram_empty_i_reg
);
ram_full_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"55554000"
)
port map (
I0 => rst_full_gen_i,
I1 => ram_full_i_i_2_n_0,
I2 => \rd_pntr_bin_reg[0]_0\,
I3 => ram_full_i_i_4_n_0,
I4 => \gntv_or_sync_fifo.gl0.wr/gwas.wsts/comp1\,
O => ram_full_i
);
ram_full_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^rd_pntr_wr\(5),
I1 => \gic0.gc0.count_reg[7]\(3),
I2 => \^rd_pntr_wr\(7),
I3 => \gic0.gc0.count_reg[7]\(5),
I4 => \gic0.gc0.count_reg[7]\(4),
I5 => \^rd_pntr_wr\(6),
O => ram_full_i_i_2_n_0
);
ram_full_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^rd_pntr_wr\(2),
I1 => \gic0.gc0.count_reg[7]\(0),
I2 => \^rd_pntr_wr\(3),
I3 => \gic0.gc0.count_reg[7]\(1),
I4 => \gic0.gc0.count_reg[7]\(2),
I5 => \^rd_pntr_wr\(4),
O => ram_full_i_i_4_n_0
);
ram_full_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000000000"
)
port map (
I0 => \^rd_pntr_wr\(7),
I1 => \gic0.gc0.count_d1_reg[7]\(7),
I2 => \^rd_pntr_wr\(6),
I3 => \gic0.gc0.count_d1_reg[7]\(6),
I4 => ram_full_i_i_6_n_0,
I5 => ram_full_i_i_7_n_0,
O => \gntv_or_sync_fifo.gl0.wr/gwas.wsts/comp1\
);
ram_full_i_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^rd_pntr_wr\(0),
I1 => \gic0.gc0.count_d1_reg[7]\(0),
I2 => \^rd_pntr_wr\(1),
I3 => \gic0.gc0.count_d1_reg[7]\(1),
I4 => \gic0.gc0.count_d1_reg[7]\(2),
I5 => \^rd_pntr_wr\(2),
O => ram_full_i_i_6_n_0
);
ram_full_i_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^rd_pntr_wr\(3),
I1 => \gic0.gc0.count_d1_reg[7]\(3),
I2 => \^rd_pntr_wr\(4),
I3 => \gic0.gc0.count_d1_reg[7]\(4),
I4 => \gic0.gc0.count_d1_reg[7]\(5),
I5 => \^rd_pntr_wr\(5),
O => ram_full_i_i_7_n_0
);
\rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_7\,
Q => \^rd_pntr_wr\(0)
);
\rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_6\,
Q => \^rd_pntr_wr\(1)
);
\rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_5\,
Q => \^rd_pntr_wr\(2)
);
\rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_4\,
Q => \^rd_pntr_wr\(3)
);
\rd_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_3\,
Q => \^rd_pntr_wr\(4)
);
\rd_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_2\,
Q => \^rd_pntr_wr\(5)
);
\rd_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gsync_stage[2].wr_stg_inst_n_1\,
Q => \^rd_pntr_wr\(6)
);
\rd_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_out(7),
Q => \^rd_pntr_wr\(7)
);
\rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(0),
I1 => Q(1),
O => \rd_pntr_gc[0]_i_1_n_0\
);
\rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(1),
I1 => Q(2),
O => \rd_pntr_gc[1]_i_1_n_0\
);
\rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(2),
I1 => Q(3),
O => \rd_pntr_gc[2]_i_1_n_0\
);
\rd_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(3),
I1 => Q(4),
O => \rd_pntr_gc[3]_i_1_n_0\
);
\rd_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(4),
I1 => Q(5),
O => \rd_pntr_gc[4]_i_1_n_0\
);
\rd_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(5),
I1 => Q(6),
O => \rd_pntr_gc[5]_i_1_n_0\
);
\rd_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q(6),
I1 => Q(7),
O => \rd_pntr_gc[6]_i_1_n_0\
);
\rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[0]_i_1_n_0\,
Q => rd_pntr_gc(0)
);
\rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[1]_i_1_n_0\,
Q => rd_pntr_gc(1)
);
\rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[2]_i_1_n_0\,
Q => rd_pntr_gc(2)
);
\rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[3]_i_1_n_0\,
Q => rd_pntr_gc(3)
);
\rd_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[4]_i_1_n_0\,
Q => rd_pntr_gc(4)
);
\rd_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[5]_i_1_n_0\,
Q => rd_pntr_gc(5)
);
\rd_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \rd_pntr_gc[6]_i_1_n_0\,
Q => rd_pntr_gc(6)
);
\rd_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(7),
Q => rd_pntr_gc(7)
);
\wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(0),
Q => \^wr_pntr_rd\(0)
);
\wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(1),
Q => \^wr_pntr_rd\(1)
);
\wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(2),
Q => \^wr_pntr_rd\(2)
);
\wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(3),
Q => \^wr_pntr_rd\(3)
);
\wr_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(4),
Q => \^wr_pntr_rd\(4)
);
\wr_pntr_bin_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(5),
Q => \^wr_pntr_rd\(5)
);
\wr_pntr_bin_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_in(6),
Q => \^wr_pntr_rd\(6)
);
\wr_pntr_bin_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_1_out(7),
Q => \^wr_pntr_rd\(7)
);
\wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[7]\(0),
I1 => \gic0.gc0.count_d2_reg[7]\(1),
O => p_0_in6_out(0)
);
\wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[7]\(1),
I1 => \gic0.gc0.count_d2_reg[7]\(2),
O => p_0_in6_out(1)
);
\wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[7]\(2),
I1 => \gic0.gc0.count_d2_reg[7]\(3),
O => p_0_in6_out(2)
);
\wr_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[7]\(3),
I1 => \gic0.gc0.count_d2_reg[7]\(4),
O => p_0_in6_out(3)
);
\wr_pntr_gc[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[7]\(4),
I1 => \gic0.gc0.count_d2_reg[7]\(5),
O => p_0_in6_out(4)
);
\wr_pntr_gc[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[7]\(5),
I1 => \gic0.gc0.count_d2_reg[7]\(6),
O => p_0_in6_out(5)
);
\wr_pntr_gc[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[7]\(6),
I1 => \gic0.gc0.count_d2_reg[7]\(7),
O => p_0_in6_out(6)
);
\wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in6_out(0),
Q => wr_pntr_gc(0)
);
\wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in6_out(1),
Q => wr_pntr_gc(1)
);
\wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in6_out(2),
Q => wr_pntr_gc(2)
);
\wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in6_out(3),
Q => wr_pntr_gc(3)
);
\wr_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in6_out(4),
Q => wr_pntr_gc(4)
);
\wr_pntr_gc_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in6_out(5),
Q => wr_pntr_gc(5)
);
\wr_pntr_gc_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => p_0_in6_out(6),
Q => wr_pntr_gc(6)
);
\wr_pntr_gc_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0),
D => \gic0.gc0.count_d2_reg[7]\(7),
Q => wr_pntr_gc(7)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_rd_logic is
port (
empty : out STD_LOGIC;
p_18_out : out STD_LOGIC;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
WR_PNTR_RD : in STD_LOGIC_VECTOR ( 7 downto 0 );
rd_en : in STD_LOGIC;
\wr_pntr_bin_reg[6]\ : in STD_LOGIC;
\wr_pntr_bin_reg[5]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_rd_logic : entity is "rd_logic";
end dcfifo_32in_32out_8kb_rd_logic;
architecture STRUCTURE of dcfifo_32in_32out_8kb_rd_logic is
signal p_14_out : STD_LOGIC;
signal \^p_18_out\ : STD_LOGIC;
signal rpntr_n_8 : STD_LOGIC;
begin
p_18_out <= \^p_18_out\;
\gras.rsts\: entity work.dcfifo_32in_32out_8kb_rd_status_flags_as
port map (
E(0) => p_14_out,
Q(0) => Q(0),
empty => empty,
p_18_out => \^p_18_out\,
rd_clk => rd_clk,
rd_en => rd_en,
\wr_pntr_bin_reg[6]\ => rpntr_n_8
);
rpntr: entity work.dcfifo_32in_32out_8kb_rd_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(7 downto 0) => \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(7 downto 0),
E(0) => p_14_out,
Q(0) => Q(0),
WR_PNTR_RD(7 downto 0) => WR_PNTR_RD(7 downto 0),
p_18_out => \^p_18_out\,
ram_empty_i_reg => rpntr_n_8,
rd_clk => rd_clk,
rd_en => rd_en,
\wr_pntr_bin_reg[5]\ => \wr_pntr_bin_reg[5]\,
\wr_pntr_bin_reg[6]\ => \wr_pntr_bin_reg[6]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_wr_logic is
port (
full : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
WEBWE : out STD_LOGIC_VECTOR ( 0 to 0 );
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 1 downto 0 );
ram_full_i : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst_full_ff_i : in STD_LOGIC;
RD_PNTR_WR : in STD_LOGIC_VECTOR ( 7 downto 0 );
wr_en : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_wr_logic : entity is "wr_logic";
end dcfifo_32in_32out_8kb_wr_logic;
architecture STRUCTURE of dcfifo_32in_32out_8kb_wr_logic is
signal \^device_7series.no_bmm_info.sdp.wide_prim18.ram\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^webwe\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_1_out : STD_LOGIC;
signal wpntr_n_1 : STD_LOGIC;
signal wpntr_n_13 : STD_LOGIC;
signal wpntr_n_14 : STD_LOGIC;
signal wpntr_n_15 : STD_LOGIC;
signal wpntr_n_16 : STD_LOGIC;
signal wpntr_n_2 : STD_LOGIC;
signal wpntr_n_3 : STD_LOGIC;
signal wpntr_n_4 : STD_LOGIC;
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(7 downto 0) <= \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7 downto 0);
WEBWE(0) <= \^webwe\(0);
\gwas.gwdc0.wdc\: entity work.dcfifo_32in_32out_8kb_wr_dc_as
port map (
S(3) => wpntr_n_13,
S(2) => wpntr_n_14,
S(1) => wpntr_n_15,
S(0) => wpntr_n_16,
\gic0.gc0.count_d2_reg[6]\(6 downto 0) => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(6 downto 0),
\gic0.gc0.count_d2_reg[7]\(3) => wpntr_n_1,
\gic0.gc0.count_d2_reg[7]\(2) => wpntr_n_2,
\gic0.gc0.count_d2_reg[7]\(1) => wpntr_n_3,
\gic0.gc0.count_d2_reg[7]\(0) => wpntr_n_4,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
wr_clk => wr_clk,
wr_data_count(1 downto 0) => wr_data_count(1 downto 0)
);
\gwas.wsts\: entity work.dcfifo_32in_32out_8kb_wr_status_flags_as
port map (
E(0) => \^webwe\(0),
full => full,
p_1_out => p_1_out,
ram_full_i => ram_full_i,
rst_full_ff_i => rst_full_ff_i,
wr_clk => wr_clk,
wr_en => wr_en
);
wpntr: entity work.dcfifo_32in_32out_8kb_wr_bin_cntr
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(7 downto 0) => \^device_7series.no_bmm_info.sdp.wide_prim18.ram\(7 downto 0),
E(0) => \^webwe\(0),
Q(5 downto 0) => Q(5 downto 0),
RD_PNTR_WR(7 downto 0) => RD_PNTR_WR(7 downto 0),
S(3) => wpntr_n_13,
S(2) => wpntr_n_14,
S(1) => wpntr_n_15,
S(0) => wpntr_n_16,
\gic0.gc0.count_d2_reg[7]_0\(7 downto 0) => \gic0.gc0.count_d2_reg[7]\(7 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0),
p_1_out => p_1_out,
ram_full_fb_i_reg => ram_full_fb_i_reg,
wr_clk => wr_clk,
\wr_data_count_i_reg[7]\(3) => wpntr_n_1,
\wr_data_count_i_reg[7]\(2) => wpntr_n_2,
\wr_data_count_i_reg[7]\(1) => wpntr_n_3,
\wr_data_count_i_reg[7]\(0) => wpntr_n_4,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end dcfifo_32in_32out_8kb_blk_mem_gen_generic_cstr;
architecture STRUCTURE of dcfifo_32in_32out_8kb_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.dcfifo_32in_32out_8kb_blk_mem_gen_prim_width
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => \gic0.gc0.count_d2_reg[7]\(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_blk_mem_gen_top : entity is "blk_mem_gen_top";
end dcfifo_32in_32out_8kb_blk_mem_gen_top;
architecture STRUCTURE of dcfifo_32in_32out_8kb_blk_mem_gen_top is
begin
\valid.cstr\: entity work.dcfifo_32in_32out_8kb_blk_mem_gen_generic_cstr
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => \gic0.gc0.count_d2_reg[7]\(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_blk_mem_gen_v8_2_synth is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end dcfifo_32in_32out_8kb_blk_mem_gen_v8_2_synth;
architecture STRUCTURE of dcfifo_32in_32out_8kb_blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.dcfifo_32in_32out_8kb_blk_mem_gen_top
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => \gic0.gc0.count_d2_reg[7]\(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_blk_mem_gen_v8_2 is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_blk_mem_gen_v8_2 : entity is "blk_mem_gen_v8_2";
end dcfifo_32in_32out_8kb_blk_mem_gen_v8_2;
architecture STRUCTURE of dcfifo_32in_32out_8kb_blk_mem_gen_v8_2 is
begin
inst_blk_mem_gen: entity work.dcfifo_32in_32out_8kb_blk_mem_gen_v8_2_synth
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => \gic0.gc0.count_d2_reg[7]\(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_memory is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
WEBWE : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\gic0.gc0.count_d2_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
din : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_memory : entity is "memory";
end dcfifo_32in_32out_8kb_memory;
architecture STRUCTURE of dcfifo_32in_32out_8kb_memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.dcfifo_32in_32out_8kb_blk_mem_gen_v8_2
port map (
Q(0) => Q(0),
WEBWE(0) => WEBWE(0),
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => \gc0.count_d1_reg[7]\(7 downto 0),
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => \gic0.gc0.count_d2_reg[7]\(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_data_count : out STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end dcfifo_32in_32out_8kb_fifo_generator_ramfifo;
architecture STRUCTURE of dcfifo_32in_32out_8kb_fifo_generator_ramfifo is
signal RD_RST : STD_LOGIC;
signal WR_RST : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_9\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_1\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_8\ : STD_LOGIC;
signal \gwas.wsts/ram_full_i\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_1_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_20_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_9_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal rst_full_gen_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 7 downto 2 );
signal wr_rst_i : STD_LOGIC_VECTOR ( 0 to 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.dcfifo_32in_32out_8kb_clk_x_pntrs
port map (
Q(7 downto 0) => p_20_out(7 downto 0),
RD_PNTR_WR(7 downto 0) => p_0_out(7 downto 0),
WR_PNTR_RD(7 downto 0) => p_1_out(7 downto 0),
\gic0.gc0.count_d1_reg[7]\(7 downto 0) => p_8_out(7 downto 0),
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => p_9_out(7 downto 0),
\gic0.gc0.count_reg[7]\(5 downto 0) => wr_pntr_plus2(7 downto 2),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\(0) => wr_rst_i(0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_0\,
ram_empty_i_reg_0 => \gntv_or_sync_fifo.gcx.clkx_n_9\,
ram_full_i => \gwas.wsts/ram_full_i\,
rd_clk => rd_clk,
\rd_pntr_bin_reg[0]_0\ => \gntv_or_sync_fifo.gl0.wr_n_1\,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk
);
\gntv_or_sync_fifo.gl0.rd\: entity work.dcfifo_32in_32out_8kb_rd_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(7 downto 0) => p_20_out(7 downto 0),
Q(0) => RD_RST,
WR_PNTR_RD(7 downto 0) => p_1_out(7 downto 0),
empty => empty,
p_18_out => p_18_out,
rd_clk => rd_clk,
rd_en => rd_en,
\wr_pntr_bin_reg[5]\ => \gntv_or_sync_fifo.gcx.clkx_n_0\,
\wr_pntr_bin_reg[6]\ => \gntv_or_sync_fifo.gcx.clkx_n_9\
);
\gntv_or_sync_fifo.gl0.wr\: entity work.dcfifo_32in_32out_8kb_wr_logic
port map (
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\(7 downto 0) => p_9_out(7 downto 0),
Q(5 downto 0) => wr_pntr_plus2(7 downto 2),
RD_PNTR_WR(7 downto 0) => p_0_out(7 downto 0),
WEBWE(0) => \gntv_or_sync_fifo.gl0.wr_n_8\,
full => full,
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => p_8_out(7 downto 0),
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\(0) => WR_RST,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_1\,
ram_full_i => \gwas.wsts/ram_full_i\,
rst_full_ff_i => rst_full_ff_i,
wr_clk => wr_clk,
wr_data_count(1 downto 0) => wr_data_count(1 downto 0),
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.dcfifo_32in_32out_8kb_memory
port map (
Q(0) => rd_rst_i(0),
WEBWE(0) => \gntv_or_sync_fifo.gl0.wr_n_8\,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
\gc0.count_d1_reg[7]\(7 downto 0) => p_20_out(7 downto 0),
\gic0.gc0.count_d2_reg[7]\(7 downto 0) => p_9_out(7 downto 0),
rd_clk => rd_clk,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
rstblk: entity work.dcfifo_32in_32out_8kb_reset_blk_ramfifo
port map (
Q(2) => RD_RST,
Q(1 downto 0) => rd_rst_i(1 downto 0),
\gic0.gc0.count_reg[0]\(1) => WR_RST,
\gic0.gc0.count_reg[0]\(0) => wr_rst_i(0),
p_18_out => p_18_out,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
rst_full_ff_i => rst_full_ff_i,
rst_full_gen_i => rst_full_gen_i,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_data_count : out STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_fifo_generator_top : entity is "fifo_generator_top";
end dcfifo_32in_32out_8kb_fifo_generator_top;
architecture STRUCTURE of dcfifo_32in_32out_8kb_fifo_generator_top is
begin
\grf.rf\: entity work.dcfifo_32in_32out_8kb_fifo_generator_ramfifo
port map (
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_data_count(1 downto 0) => wr_data_count(1 downto 0),
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_fifo_generator_v12_0_synth is
port (
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
wr_data_count : out STD_LOGIC_VECTOR ( 1 downto 0 );
rd_en : in STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_fifo_generator_v12_0_synth : entity is "fifo_generator_v12_0_synth";
end dcfifo_32in_32out_8kb_fifo_generator_v12_0_synth;
architecture STRUCTURE of dcfifo_32in_32out_8kb_fifo_generator_v12_0_synth is
begin
\gconvfifo.rf\: entity work.dcfifo_32in_32out_8kb_fifo_generator_top
port map (
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_data_count(1 downto 0) => wr_data_count(1 downto 0),
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb_fifo_generator_v12_0 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 7 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 7 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 7 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 7 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 7 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 7 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 7 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 7 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 1 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 8;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 32;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 253;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 252;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 8;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 256;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 8;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 2;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 256;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 8;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of dcfifo_32in_32out_8kb_fifo_generator_v12_0 : entity is "fifo_generator_v12_0";
end dcfifo_32in_32out_8kb_fifo_generator_v12_0;
architecture STRUCTURE of dcfifo_32in_32out_8kb_fifo_generator_v12_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.dcfifo_32in_32out_8kb_fifo_generator_v12_0_synth
port map (
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_data_count(1 downto 0) => wr_data_count(1 downto 0),
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dcfifo_32in_32out_8kb is
port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 31 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
wr_data_count : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of dcfifo_32in_32out_8kb : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of dcfifo_32in_32out_8kb : entity is "dcfifo_32in_32out_8kb,fifo_generator_v12_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of dcfifo_32in_32out_8kb : entity is "dcfifo_32in_32out_8kb,fifo_generator_v12_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=8,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=1,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=253,C_PROG_FULL_THRESH_NEGATE_VAL=252,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=8,C_RD_DEPTH=256,C_RD_FREQ=1,C_RD_PNTR_WIDTH=8,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=2,C_WR_DEPTH=256,C_WR_FREQ=1,C_WR_PNTR_WIDTH=8,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of dcfifo_32in_32out_8kb : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of dcfifo_32in_32out_8kb : entity is "fifo_generator_v12_0,Vivado 2015.1";
end dcfifo_32in_32out_8kb;
architecture STRUCTURE of dcfifo_32in_32out_8kb is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 8;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 32;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 32;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 1;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 253;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 252;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 8;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 256;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 8;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 2;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 256;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 8;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.dcfifo_32in_32out_8kb_fifo_generator_v12_0
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3) => '0',
axi_ar_prog_empty_thresh(2) => '0',
axi_ar_prog_empty_thresh(1) => '0',
axi_ar_prog_empty_thresh(0) => '0',
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3) => '0',
axi_ar_prog_full_thresh(2) => '0',
axi_ar_prog_full_thresh(1) => '0',
axi_ar_prog_full_thresh(0) => '0',
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3) => '0',
axi_aw_prog_empty_thresh(2) => '0',
axi_aw_prog_empty_thresh(1) => '0',
axi_aw_prog_empty_thresh(0) => '0',
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3) => '0',
axi_aw_prog_full_thresh(2) => '0',
axi_aw_prog_full_thresh(1) => '0',
axi_aw_prog_full_thresh(0) => '0',
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3) => '0',
axi_b_prog_empty_thresh(2) => '0',
axi_b_prog_empty_thresh(1) => '0',
axi_b_prog_empty_thresh(0) => '0',
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3) => '0',
axi_b_prog_full_thresh(2) => '0',
axi_b_prog_full_thresh(1) => '0',
axi_b_prog_full_thresh(0) => '0',
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9) => '0',
axi_r_prog_empty_thresh(8) => '0',
axi_r_prog_empty_thresh(7) => '0',
axi_r_prog_empty_thresh(6) => '0',
axi_r_prog_empty_thresh(5) => '0',
axi_r_prog_empty_thresh(4) => '0',
axi_r_prog_empty_thresh(3) => '0',
axi_r_prog_empty_thresh(2) => '0',
axi_r_prog_empty_thresh(1) => '0',
axi_r_prog_empty_thresh(0) => '0',
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9) => '0',
axi_r_prog_full_thresh(8) => '0',
axi_r_prog_full_thresh(7) => '0',
axi_r_prog_full_thresh(6) => '0',
axi_r_prog_full_thresh(5) => '0',
axi_r_prog_full_thresh(4) => '0',
axi_r_prog_full_thresh(3) => '0',
axi_r_prog_full_thresh(2) => '0',
axi_r_prog_full_thresh(1) => '0',
axi_r_prog_full_thresh(0) => '0',
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9) => '0',
axi_w_prog_empty_thresh(8) => '0',
axi_w_prog_empty_thresh(7) => '0',
axi_w_prog_empty_thresh(6) => '0',
axi_w_prog_empty_thresh(5) => '0',
axi_w_prog_empty_thresh(4) => '0',
axi_w_prog_empty_thresh(3) => '0',
axi_w_prog_empty_thresh(2) => '0',
axi_w_prog_empty_thresh(1) => '0',
axi_w_prog_empty_thresh(0) => '0',
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9) => '0',
axi_w_prog_full_thresh(8) => '0',
axi_w_prog_full_thresh(7) => '0',
axi_w_prog_full_thresh(6) => '0',
axi_w_prog_full_thresh(5) => '0',
axi_w_prog_full_thresh(4) => '0',
axi_w_prog_full_thresh(3) => '0',
axi_w_prog_full_thresh(2) => '0',
axi_w_prog_full_thresh(1) => '0',
axi_w_prog_full_thresh(0) => '0',
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9) => '0',
axis_prog_empty_thresh(8) => '0',
axis_prog_empty_thresh(7) => '0',
axis_prog_empty_thresh(6) => '0',
axis_prog_empty_thresh(5) => '0',
axis_prog_empty_thresh(4) => '0',
axis_prog_empty_thresh(3) => '0',
axis_prog_empty_thresh(2) => '0',
axis_prog_empty_thresh(1) => '0',
axis_prog_empty_thresh(0) => '0',
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9) => '0',
axis_prog_full_thresh(8) => '0',
axis_prog_full_thresh(7) => '0',
axis_prog_full_thresh(6) => '0',
axis_prog_full_thresh(5) => '0',
axis_prog_full_thresh(4) => '0',
axis_prog_full_thresh(3) => '0',
axis_prog_full_thresh(2) => '0',
axis_prog_full_thresh(1) => '0',
axis_prog_full_thresh(0) => '0',
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(7 downto 0) => NLW_U0_data_count_UNCONNECTED(7 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(31 downto 0) => din(31 downto 0),
dout(31 downto 0) => dout(31 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1) => '0',
m_axi_bresp(0) => '0',
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63) => '0',
m_axi_rdata(62) => '0',
m_axi_rdata(61) => '0',
m_axi_rdata(60) => '0',
m_axi_rdata(59) => '0',
m_axi_rdata(58) => '0',
m_axi_rdata(57) => '0',
m_axi_rdata(56) => '0',
m_axi_rdata(55) => '0',
m_axi_rdata(54) => '0',
m_axi_rdata(53) => '0',
m_axi_rdata(52) => '0',
m_axi_rdata(51) => '0',
m_axi_rdata(50) => '0',
m_axi_rdata(49) => '0',
m_axi_rdata(48) => '0',
m_axi_rdata(47) => '0',
m_axi_rdata(46) => '0',
m_axi_rdata(45) => '0',
m_axi_rdata(44) => '0',
m_axi_rdata(43) => '0',
m_axi_rdata(42) => '0',
m_axi_rdata(41) => '0',
m_axi_rdata(40) => '0',
m_axi_rdata(39) => '0',
m_axi_rdata(38) => '0',
m_axi_rdata(37) => '0',
m_axi_rdata(36) => '0',
m_axi_rdata(35) => '0',
m_axi_rdata(34) => '0',
m_axi_rdata(33) => '0',
m_axi_rdata(32) => '0',
m_axi_rdata(31) => '0',
m_axi_rdata(30) => '0',
m_axi_rdata(29) => '0',
m_axi_rdata(28) => '0',
m_axi_rdata(27) => '0',
m_axi_rdata(26) => '0',
m_axi_rdata(25) => '0',
m_axi_rdata(24) => '0',
m_axi_rdata(23) => '0',
m_axi_rdata(22) => '0',
m_axi_rdata(21) => '0',
m_axi_rdata(20) => '0',
m_axi_rdata(19) => '0',
m_axi_rdata(18) => '0',
m_axi_rdata(17) => '0',
m_axi_rdata(16) => '0',
m_axi_rdata(15) => '0',
m_axi_rdata(14) => '0',
m_axi_rdata(13) => '0',
m_axi_rdata(12) => '0',
m_axi_rdata(11) => '0',
m_axi_rdata(10) => '0',
m_axi_rdata(9) => '0',
m_axi_rdata(8) => '0',
m_axi_rdata(7) => '0',
m_axi_rdata(6) => '0',
m_axi_rdata(5) => '0',
m_axi_rdata(4) => '0',
m_axi_rdata(3) => '0',
m_axi_rdata(2) => '0',
m_axi_rdata(1) => '0',
m_axi_rdata(0) => '0',
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1) => '0',
m_axi_rresp(0) => '0',
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(7) => '0',
prog_empty_thresh(6) => '0',
prog_empty_thresh(5) => '0',
prog_empty_thresh(4) => '0',
prog_empty_thresh(3) => '0',
prog_empty_thresh(2) => '0',
prog_empty_thresh(1) => '0',
prog_empty_thresh(0) => '0',
prog_empty_thresh_assert(7) => '0',
prog_empty_thresh_assert(6) => '0',
prog_empty_thresh_assert(5) => '0',
prog_empty_thresh_assert(4) => '0',
prog_empty_thresh_assert(3) => '0',
prog_empty_thresh_assert(2) => '0',
prog_empty_thresh_assert(1) => '0',
prog_empty_thresh_assert(0) => '0',
prog_empty_thresh_negate(7) => '0',
prog_empty_thresh_negate(6) => '0',
prog_empty_thresh_negate(5) => '0',
prog_empty_thresh_negate(4) => '0',
prog_empty_thresh_negate(3) => '0',
prog_empty_thresh_negate(2) => '0',
prog_empty_thresh_negate(1) => '0',
prog_empty_thresh_negate(0) => '0',
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(7) => '0',
prog_full_thresh(6) => '0',
prog_full_thresh(5) => '0',
prog_full_thresh(4) => '0',
prog_full_thresh(3) => '0',
prog_full_thresh(2) => '0',
prog_full_thresh(1) => '0',
prog_full_thresh(0) => '0',
prog_full_thresh_assert(7) => '0',
prog_full_thresh_assert(6) => '0',
prog_full_thresh_assert(5) => '0',
prog_full_thresh_assert(4) => '0',
prog_full_thresh_assert(3) => '0',
prog_full_thresh_assert(2) => '0',
prog_full_thresh_assert(1) => '0',
prog_full_thresh_assert(0) => '0',
prog_full_thresh_negate(7) => '0',
prog_full_thresh_negate(6) => '0',
prog_full_thresh_negate(5) => '0',
prog_full_thresh_negate(4) => '0',
prog_full_thresh_negate(3) => '0',
prog_full_thresh_negate(2) => '0',
prog_full_thresh_negate(1) => '0',
prog_full_thresh_negate(0) => '0',
rd_clk => rd_clk,
rd_data_count(7 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(7 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arcache(3) => '0',
s_axi_arcache(2) => '0',
s_axi_arcache(1) => '0',
s_axi_arcache(0) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arlock(0) => '0',
s_axi_arprot(2) => '0',
s_axi_arprot(1) => '0',
s_axi_arprot(0) => '0',
s_axi_arqos(3) => '0',
s_axi_arqos(2) => '0',
s_axi_arqos(1) => '0',
s_axi_arqos(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3) => '0',
s_axi_arregion(2) => '0',
s_axi_arregion(1) => '0',
s_axi_arregion(0) => '0',
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awcache(3) => '0',
s_axi_awcache(2) => '0',
s_axi_awcache(1) => '0',
s_axi_awcache(0) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awlock(0) => '0',
s_axi_awprot(2) => '0',
s_axi_awprot(1) => '0',
s_axi_awprot(0) => '0',
s_axi_awqos(3) => '0',
s_axi_awqos(2) => '0',
s_axi_awqos(1) => '0',
s_axi_awqos(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3) => '0',
s_axi_awregion(2) => '0',
s_axi_awregion(1) => '0',
s_axi_awregion(0) => '0',
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63) => '0',
s_axi_wdata(62) => '0',
s_axi_wdata(61) => '0',
s_axi_wdata(60) => '0',
s_axi_wdata(59) => '0',
s_axi_wdata(58) => '0',
s_axi_wdata(57) => '0',
s_axi_wdata(56) => '0',
s_axi_wdata(55) => '0',
s_axi_wdata(54) => '0',
s_axi_wdata(53) => '0',
s_axi_wdata(52) => '0',
s_axi_wdata(51) => '0',
s_axi_wdata(50) => '0',
s_axi_wdata(49) => '0',
s_axi_wdata(48) => '0',
s_axi_wdata(47) => '0',
s_axi_wdata(46) => '0',
s_axi_wdata(45) => '0',
s_axi_wdata(44) => '0',
s_axi_wdata(43) => '0',
s_axi_wdata(42) => '0',
s_axi_wdata(41) => '0',
s_axi_wdata(40) => '0',
s_axi_wdata(39) => '0',
s_axi_wdata(38) => '0',
s_axi_wdata(37) => '0',
s_axi_wdata(36) => '0',
s_axi_wdata(35) => '0',
s_axi_wdata(34) => '0',
s_axi_wdata(33) => '0',
s_axi_wdata(32) => '0',
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7) => '0',
s_axi_wstrb(6) => '0',
s_axi_wstrb(5) => '0',
s_axi_wstrb(4) => '0',
s_axi_wstrb(3) => '0',
s_axi_wstrb(2) => '0',
s_axi_wstrb(1) => '0',
s_axi_wstrb(0) => '0',
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7) => '0',
s_axis_tdata(6) => '0',
s_axis_tdata(5) => '0',
s_axis_tdata(4) => '0',
s_axis_tdata(3) => '0',
s_axis_tdata(2) => '0',
s_axis_tdata(1) => '0',
s_axis_tdata(0) => '0',
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3) => '0',
s_axis_tuser(2) => '0',
s_axis_tuser(1) => '0',
s_axis_tuser(0) => '0',
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(1 downto 0) => wr_data_count(1 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
entity Axi_basic_slave is
generic(
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 4
);
port(
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH - 1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
--S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH / 8) - 1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH - 1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
--S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end Axi_basic_slave; |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
--USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.STD_LOGIC_UNSIGNED.ALL;
--USE IEEE.STD_LOGIC_SIGNED.ALL;
ENTITY compteur IS
GENERIC ( Nb_bascules : natural := 1
);
PORT ( AB : IN unsigned(1 DOWNTO 0);
cpt : OUT unsigned(7 DOWNTO 0);
clk : IN std_ulogic;
INV : IN std_ulogic
);
END compteur;
ARCHITECTURE Behavioral OF compteur IS
TYPE tableau IS ARRAY (Nb_bascules downto 0) OF unsigned(1 DOWNTO 0);
SIGNAL A_B : tableau;
SIGNAL tmp : unsigned(7 DOWNTO 0);
BEGIN
-- double latch des codeurs
copie : PROCESS
BEGIN
WAIT UNTIL rising_edge(clk) ;
A_B(0)<= AB(1) & (AB(0) XOR INV);
FOR i IN 1 TO Nb_bascules LOOP
A_B(i) <= A_B(i-1);
END LOOP;
END PROCESS copie;
-- decodage de la quadrature et comptage
comptage: PROCESS
BEGIN
WAIT UNTIL falling_edge(clk) ;
IF (A_B(Nb_bascules-1) = "00" and A_B(Nb_bascules) = "01") OR (A_B(Nb_bascules-1) = "01" AND A_B(Nb_bascules) = "11") OR (A_B(Nb_bascules-1) = "11" AND A_B(Nb_bascules) = "10") OR (A_B(Nb_bascules-1) = "10" AND A_B(Nb_bascules) = "00") THEN
tmp <= tmp - 1;
ELSIF (A_B(Nb_bascules) = "00" and A_B(Nb_bascules-1) = "01") OR (A_B(Nb_bascules) = "01" AND A_B(Nb_bascules-1) = "11") OR (A_B(Nb_bascules) = "11" AND A_B(Nb_bascules-1) = "10") OR (A_B(Nb_bascules) = "10" AND A_B(Nb_bascules-1) = "00") THEN
tmp <= tmp + 1;
END IF;
END PROCESS comptage;
cpt <= tmp;
END Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity sicxe_core is
Port (
clock_i : in std_logic;
reset_i : in std_logic;
enable_i : in std_logic;
error_o : out std_logic;
-- memory
memory_read_o : out std_logic;
memory_write_o : out std_logic;
memory_address_o : out std_logic_vector(19 downto 0);
memory_data_in_i : in std_logic_vector(7 downto 0);
memory_data_out_o : out std_logic_vector(7 downto 0);
memory_done_i : in std_logic;
-- device ports
port_id_o : out std_logic_vector(7 downto 0);
port_in_i : in std_logic_vector(7 downto 0);
port_out_o : out std_logic_vector(7 downto 0);
port_read_strobe_o : out std_logic;
port_write_strobe_o : out std_logic;
-- interrupt
interrupt_i : in std_logic;
interrupt_acknowledge_o : out std_logic;
interrupt_enabled_o : out std_logic
);
end sicxe_core;
architecture behavioral of sicxe_core is
-- opcodes
constant OPCODE_LONG_EINT : std_logic_vector := "11111000";
constant OPCODE_LONG_DINT : std_logic_vector := "11111001";
constant OPCODE_LONG_RINT : std_logic_vector := "11111010";
constant OPCODE_LONG_CLEAR : std_logic_vector := "10110100";
constant OPCODE_LONG_RMO : std_logic_vector := "10101100";
constant OPCODE_LONG_ADDR : std_logic_vector := "10010000";
constant OPCODE_LONG_SUBR : std_logic_vector := "10010100";
constant OPCODE_LONG_MULR : std_logic_vector := "10011000";
constant OPCODE_LONG_SHIFTL : std_logic_vector := "10100100";
constant OPCODE_LONG_SHIFTR : std_logic_vector := "10101000";
constant OPCODE_LONG_COMPR : std_logic_vector := "10100000";
constant OPCODE_LONG_TIXR : std_logic_vector := "10111000";
constant OPCODE_LONG_ANDR : std_logic_vector := "11110100";
constant OPCODE_LONG_ORR : std_logic_vector := "11110101";
constant OPCODE_LONG_XORR : std_logic_vector := "11110110";
constant OPCODE_LONG_NOT : std_logic_vector := "11110111";
constant OPCODE_SHORT_ADD : std_logic_vector := "000110";
constant OPCODE_SHORT_SUB : std_logic_vector := "000111";
constant OPCODE_SHORT_MUL : std_logic_vector := "001000";
constant OPCODE_SHORT_AND : std_logic_vector := "010000";
constant OPCODE_SHORT_OR : std_logic_vector := "010001";
constant OPCODE_SHORT_COMP : std_logic_vector := "001010";
constant OPCODE_SHORT_TIX : std_logic_vector := "001011";
constant OPCODE_SHORT_J : std_logic_vector := "001111";
constant OPCODE_SHORT_JEQ : std_logic_vector := "001100";
constant OPCODE_SHORT_JGT : std_logic_vector := "001101";
constant OPCODE_SHORT_JLT : std_logic_vector := "001110";
constant OPCODE_SHORT_JSUB : std_logic_vector := "010010";
constant OPCODE_SHORT_RSUB : std_logic_vector := "010011";
constant OPCODE_SHORT_LDCH : std_logic_vector := "010100";
constant OPCODE_SHORT_LDA : std_logic_vector := "000000";
constant OPCODE_SHORT_LDB : std_logic_vector := "011010";
constant OPCODE_SHORT_LDL : std_logic_vector := "000010";
constant OPCODE_SHORT_LDS : std_logic_vector := "011011";
constant OPCODE_SHORT_LDT : std_logic_vector := "011101";
constant OPCODE_SHORT_LDX : std_logic_vector := "000001";
constant OPCODE_SHORT_STCH : std_logic_vector := "010101";
constant OPCODE_SHORT_STSW : std_logic_vector := "111010";
constant OPCODE_SHORT_STA : std_logic_vector := "000011";
constant OPCODE_SHORT_STB : std_logic_vector := "011110";
constant OPCODE_SHORT_STL : std_logic_vector := "000101";
constant OPCODE_SHORT_STS : std_logic_vector := "011111";
constant OPCODE_SHORT_STT : std_logic_vector := "100001";
constant OPCODE_SHORT_STX : std_logic_vector := "000100";
constant OPCODE_SHORT_TD : std_logic_vector := "111000";
constant OPCODE_SHORT_RD : std_logic_vector := "110110";
constant OPCODE_SHORT_WD : std_logic_vector := "110111";
constant OPCODE_SHORT_XOR : std_logic_vector := "111100";
constant OPCODE_SHORT_STIL : std_logic_vector := "111111";
-- ALU
type alu_operation_type is (ALU_ZERO, ALU_PASS1, ALU_PASS2, ALU_ADD, ALU_SUB,
ALU_MUL, ALU_AND, ALU_OR, ALU_XOR, ALU_NOT,
ALU_SHIFTL, ALU_SHIFTR);
signal alu_operation : alu_operation_type;
signal alu_operand1 : std_logic_vector(23 downto 0);
signal alu_operand2 : std_logic_vector(23 downto 0);
signal alu_shift_bits : std_logic_vector(3 downto 0);
signal alu_result : std_logic_vector(23 downto 0);
signal alu_compare_result_left : std_logic_vector(1 downto 0);
signal alu_compare_result_right : std_logic_vector(1 downto 0);
-- general registers
signal reg_general_a : std_logic_vector(23 downto 0);
signal reg_general_x : std_logic_vector(23 downto 0);
signal reg_general_l : std_logic_vector(23 downto 0);
signal reg_general_b : std_logic_vector(23 downto 0);
signal reg_general_s : std_logic_vector(23 downto 0);
signal reg_general_t : std_logic_vector(23 downto 0);
signal reg_general_write : std_logic;
signal reg_general_select : std_logic_vector(3 downto 0);
signal reg_general_select_write : std_logic;
type select_general_type is (SELECT_GENERAL_A, SELECT_GENERAL_X, SELECT_GENERAL_L,
SELECT_GENERAL_R1, SELECT_GENERAL_R2,
SELECT_GENERAL_LOAD_INSN);
signal select_general : select_general_type;
-- operand registers
signal reg_operand1 : std_logic_vector(23 downto 0);
signal reg_operand2 : std_logic_vector(23 downto 0);
signal reg_operand3 : std_logic_vector(23 downto 0);
signal reg_operand1_write : std_logic;
signal reg_operand2_write : std_logic;
signal reg_operand3_write : std_logic;
-- result register
signal reg_result : std_logic_vector(23 downto 0);
signal reg_result_write : std_logic;
-- special registers
signal reg_special_target : std_logic_vector(23 downto 0);
signal reg_special_pc : std_logic_vector(19 downto 0);
signal reg_special_il : std_logic_vector(19 downto 0);
signal reg_special_cc : std_logic_vector(1 downto 0);
signal reg_special_icc : std_logic_vector(1 downto 0);
signal reg_special_target_write : std_logic;
signal reg_special_pc_write : std_logic;
signal reg_special_pc_write_cond : std_logic;
signal reg_special_il_write : std_logic;
signal reg_special_cc_clear : std_logic;
signal reg_special_cc_write_left : std_logic;
signal reg_special_cc_write_right : std_logic;
signal reg_special_cc_save : std_logic;
signal reg_special_cc_restore : std_logic;
-- conditional PC write
signal reg_special_pc_write_cond_lt : std_logic;
signal reg_special_pc_write_cond_eq : std_logic;
signal reg_special_pc_write_cond_gt : std_logic;
-- interrupt enable register
signal reg_interrupt : std_logic;
signal reg_interrupt_next : std_logic;
signal interrupt_disable : std_logic;
signal interrupt_enable : std_logic;
signal interrupt_move : std_logic;
-- memory data register
signal reg_memory_data : std_logic_vector(23 downto 0);
signal reg_memory_data_write_result : std_logic;
signal reg_memory_data_write_mem : std_logic_vector(2 downto 0);
-- device data register
signal reg_device_data : std_logic_vector(7 downto 0);
signal reg_device_data_write_result : std_logic;
signal reg_device_data_write_dev : std_logic;
-- instruction register
signal reg_instruction : std_logic_vector(31 downto 0);
signal reg_instruction_write : std_logic_vector(3 downto 0);
signal insn_opcode : std_logic_vector(7 downto 0);
signal insn_flag_n : std_logic;
signal insn_flag_i : std_logic;
signal insn_flag_x : std_logic;
signal insn_flag_b : std_logic;
signal insn_flag_p : std_logic;
signal insn_flag_e : std_logic;
signal insn_r1 : std_logic_vector(3 downto 0);
signal insn_r2 : std_logic_vector(3 downto 0);
signal insn_operand_f3_usgn : std_logic_vector(23 downto 0);
signal insn_operand_f3_sgn : std_logic_vector(23 downto 0);
signal insn_operand_f4_usgn : std_logic_vector(23 downto 0);
signal insn_operand_sic : std_logic_vector(23 downto 0);
signal insn_r1_valid : std_logic;
signal insn_r2_valid : std_logic;
-- operand select
type select_op1_type is (SELECT_OP1_ROP1, SELECT_OP1_X, SELECT_OP1_TARGET,
SELECT_OP1_PC, SELECT_OP1_IL, SELECT_OP1_MEM,
SELECT_OP1_MEM_BYTE, SELECT_OP1_DEV, SELECT_OP1_F3USGN,
SELECT_OP1_F3SGN, SELECT_OP1_F4USGN, SELECT_OP1_SIC);
signal select_op1 : select_op1_type;
type select_op2_type is (SELECT_OP2_CONE, SELECT_OP2_CIV, SELECT_OP2_ROP2,
SELECT_OP2_ROP3, SELECT_OP2_A, SELECT_OP2_X, SELECT_OP2_B,
SELECT_OP2_L, SELECT_OP2_PC, SELECT_OP2_SW);
signal select_op2 : select_op2_type;
-- memory address select
type select_addr_type is (SELECT_ADDR_PC, SELECT_ADDR_TARGET);
signal select_addr : select_addr_type;
-- memory out data select
type select_mem_type is (SELECT_MEM_BYTE0, SELECT_MEM_BYTE1, SELECT_MEM_BYTE2);
signal select_mem : select_mem_type;
-- control unit FSM
type ctl_state_type is (CTL_ERROR, CTL_DISABLED, CTL_INSN0, CTL_DECODE0,
CTL_F1_EINT, CTL_F1_DINT, CTL_F1_RINT,
CTL_F2_INSN1, CTL_F2_DECODE1, CTL_F2_ALU0, CTL_F2_ALU1,
CTL_F2_COMP, CTL_F2_TIX0, CTL_F2_TIX1, CTL_F2_TIX2,
CTL_F34_INSN1, CTL_F34_INSN2, CTL_F34_INSN3, CTL_F34_DECODE1,
CTL_F34_DECODE2, CTL_F34_INDEXED,
CTL_F34_INDIRECT0, CTL_F34_INDIRECT1, CTL_F34_INDIRECT2,
CTL_F34_INDIRECT3, CTL_F34_RSUB,
CTL_F34B_LOAD0, CTL_F34B_LOAD1, CTL_F34B_DECODE3, CTL_F34B_WD0,
CTL_F34B_WD1, CTL_F34B_WD2, CTL_F34B_TD, CTL_F34B_RD0,
CTL_F34B_RD1, CTL_F34B_RD2, CTL_F34B_RD3, CTL_F34B_LDCH0,
CTL_F34B_LDCH1,
CTL_F34B_STSW, CTL_F34B_STCH,
CTL_F34W_STR0, CTL_F34W_STR1, CTL_F34W_STIL,
CTL_F34_STORE0, CTL_F34_STORE1, CTL_F34_STORE2,
CTL_F34_JUMP, CTL_F34_JSUB0, CTL_F34_JSUB1,
CTL_F34W_LOAD0, CTL_F34W_LOAD1, CTL_F34W_LOAD2, CTL_F34W_LOAD3,
CTL_F34W_DECODE3, CTL_F34W_LDR0, CTL_F34W_LDR1,
CTL_F34W_COMP, CTL_F34W_TIX0, CTL_F34W_TIX1, CTL_F34W_TIX2,
CTL_F34W_ALU0, CTL_F34W_ALU1,
CTL_INT0, CTL_INT1, CTL_INT2, CTL_INT3, CTL_INT4, CTL_INT5);
signal ctl_state : ctl_state_type;
signal ctl_next_state : ctl_state_type;
begin
-- ALU
alu_proc : process(alu_operation, alu_operand1, alu_operand2, alu_shift_bits)
begin
alu_result <= (others => '0');
case (alu_operation) is
when ALU_ZERO =>
alu_result <= (others => '0');
when ALU_PASS1 =>
alu_result <= alu_operand1;
when ALU_PASS2 =>
alu_result <= alu_operand2;
when ALU_ADD =>
alu_result <= std_logic_vector(signed(alu_operand2) + signed(alu_operand1));
when ALU_SUB =>
alu_result <= std_logic_vector(signed(alu_operand2) - signed(alu_operand1));
when ALU_MUL =>
alu_result <= std_logic_vector(
resize(signed(alu_operand2) * signed(alu_operand1), 24));
when ALU_AND =>
alu_result <= std_logic_vector(signed(alu_operand2) and signed(alu_operand1));
when ALU_OR =>
alu_result <= std_logic_vector(signed(alu_operand2) or signed(alu_operand1));
when ALU_XOR =>
alu_result <= std_logic_vector(signed(alu_operand2) xor signed(alu_operand1));
when ALU_NOT =>
alu_result <= std_logic_vector(not signed(alu_operand1));
when ALU_SHIFTL =>
alu_result <= std_logic_vector(
signed(alu_operand1) sll to_integer(unsigned(alu_shift_bits)));
when ALU_SHIFTR =>
alu_result <= std_logic_vector(shift_right(signed(alu_operand1),
to_integer(unsigned(alu_shift_bits))));
when others =>
end case;
end process;
alu_compare_proc : process(alu_operand1, alu_operand2)
begin
if (signed(alu_operand1) < signed(alu_operand2)) then
alu_compare_result_left <= "00";
alu_compare_result_right <= "10";
elsif (signed(alu_operand1) = signed(alu_operand2)) then
alu_compare_result_left <= "01";
alu_compare_result_right <= "01";
else
alu_compare_result_left <= "10";
alu_compare_result_right <= "00";
end if;
end process;
-- general registers
reg_general_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
reg_general_a <= (others => '0');
reg_general_x <= (others => '0');
reg_general_l <= (others => '0');
reg_general_b <= (others => '0');
reg_general_s <= (others => '0');
reg_general_t <= (others => '0');
else
reg_general_a <= reg_general_a;
reg_general_x <= reg_general_x;
reg_general_l <= reg_general_l;
reg_general_b <= reg_general_b;
reg_general_s <= reg_general_s;
reg_general_t <= reg_general_t;
if (reg_general_write = '1') then
case (reg_general_select) is
when x"0" =>
reg_general_a <= reg_result;
when x"1" =>
reg_general_x <= reg_result;
when x"2" =>
reg_general_l <= reg_result;
when x"3" =>
reg_general_b <= reg_result;
when x"4" =>
reg_general_s <= reg_result;
when x"5" =>
reg_general_t <= reg_result;
when others =>
end case;
end if;
end if;
end if;
end process;
reg_general_select_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
reg_general_select <= x"0";
else
reg_general_select <= reg_general_select;
if (reg_general_select_write = '1') then
case (select_general) is
when SELECT_GENERAL_A =>
reg_general_select <= x"0";
when SELECT_GENERAL_X =>
reg_general_select <= x"1";
when SELECT_GENERAL_L =>
reg_general_select <= x"2";
when SELECT_GENERAL_R1 =>
reg_general_select <= insn_r1;
when SELECT_GENERAL_R2 =>
reg_general_select <= insn_r2;
when SELECT_GENERAL_LOAD_INSN =>
case (insn_opcode(7 downto 2)) is
when OPCODE_SHORT_LDA =>
reg_general_select <= x"0";
when OPCODE_SHORT_LDX =>
reg_general_select <= x"1";
when OPCODE_SHORT_LDL =>
reg_general_select <= x"2";
when OPCODE_SHORT_LDB =>
reg_general_select <= x"3";
when OPCODE_SHORT_LDS =>
reg_general_select <= x"4";
when OPCODE_SHORT_LDT =>
reg_general_select <= x"5";
when others =>
reg_general_select <= x"0";
end case;
when others =>
end case;
end if;
end if;
end if;
end process;
-- special registers
reg_special_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
reg_special_target <= (others => '0');
reg_special_pc <= (others => '0');
reg_special_il <= (others => '0');
reg_special_cc <= (others => '0');
reg_special_icc <= (others => '0');
else
reg_special_target <= reg_special_target;
reg_special_pc <= reg_special_pc;
reg_special_il <= reg_special_il;
reg_special_cc <= reg_special_cc;
reg_special_icc <= reg_special_icc;
if (reg_special_target_write = '1') then
reg_special_target <= alu_result;
end if;
if (reg_special_pc_write = '1' or reg_special_pc_write_cond = '1') then
reg_special_pc <= alu_result(19 downto 0);
end if;
if (reg_special_il_write = '1') then
reg_special_il <= alu_result(19 downto 0);
end if;
if (reg_special_cc_clear = '1') then
reg_special_cc <= (others => '0');
elsif (reg_special_cc_write_left = '1') then
reg_special_cc <= alu_compare_result_left;
elsif (reg_special_cc_write_right = '1') then
reg_special_cc <= alu_compare_result_right;
elsif (reg_special_cc_restore = '1') then
reg_special_cc <= reg_special_icc;
end if;
if (reg_special_cc_save = '1') then
reg_special_icc <= reg_special_cc;
end if;
end if;
end if;
end process;
-- conditional PC write
reg_special_pc_write_cond_proc : process(reg_special_cc,
reg_special_pc_write_cond_lt,
reg_special_pc_write_cond_eq,
reg_special_pc_write_cond_gt)
begin
reg_special_pc_write_cond <= '0';
case (reg_special_cc) is
when "00" =>
reg_special_pc_write_cond <= reg_special_pc_write_cond_lt;
when "01" =>
reg_special_pc_write_cond <= reg_special_pc_write_cond_eq;
when "10" =>
reg_special_pc_write_cond <= reg_special_pc_write_cond_gt;
when others =>
end case;
end process;
-- operand registers
reg_operand_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
reg_operand1 <= (others => '0');
reg_operand2 <= (others => '0');
reg_operand3 <= (others => '0');
else
reg_operand1 <= reg_operand1;
reg_operand2 <= reg_operand2;
reg_operand3 <= reg_operand3;
if (reg_operand1_write = '1') then
case (insn_r1) is
when x"0" =>
reg_operand1 <= reg_general_a;
when x"1" =>
reg_operand1 <= reg_general_x;
when x"2" =>
reg_operand1 <= reg_general_l;
when x"3" =>
reg_operand1 <= reg_general_b;
when x"4" =>
reg_operand1 <= reg_general_s;
when x"5" =>
reg_operand1 <= reg_general_t;
when others =>
end case;
end if;
if (reg_operand2_write = '1') then
case (insn_r2) is
when x"0" =>
reg_operand2 <= reg_general_a;
when x"1" =>
reg_operand2 <= reg_general_x;
when x"2" =>
reg_operand2 <= reg_general_l;
when x"3" =>
reg_operand2 <= reg_general_b;
when x"4" =>
reg_operand2 <= reg_general_s;
when x"5" =>
reg_operand2 <= reg_general_t;
when others =>
end case;
end if;
if (reg_operand3_write = '1') then
case (insn_opcode(7 downto 2)) is
when OPCODE_SHORT_STA =>
reg_operand3 <= reg_general_a;
when OPCODE_SHORT_STX =>
reg_operand3 <= reg_general_x;
when OPCODE_SHORT_STL =>
reg_operand3 <= reg_general_l;
when OPCODE_SHORT_STB =>
reg_operand3 <= reg_general_b;
when OPCODE_SHORT_STS =>
reg_operand3 <= reg_general_s;
when OPCODE_SHORT_STT =>
reg_operand3 <= reg_general_t;
when others =>
end case;
end if;
end if;
end if;
end process;
-- result register
reg_result_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
reg_result <= (others => '0');
else
if (reg_result_write = '1') then
reg_result <= alu_result;
else
reg_result <= reg_result;
end if;
end if;
end if;
end process;
-- interrupt enable register
reg_interrupt_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
reg_interrupt <= '0';
reg_interrupt_next <= '0';
else
if (interrupt_disable = '1') then
reg_interrupt <= '0';
reg_interrupt_next <= '0';
else
if (interrupt_move = '1') then
reg_interrupt <= reg_interrupt_next;
else
reg_interrupt <= reg_interrupt;
end if;
if (interrupt_enable = '1') then
reg_interrupt_next <= '1';
else
reg_interrupt_next <= reg_interrupt_next;
end if;
end if;
end if;
end if;
end process;
-- memory data register
reg_memory_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
reg_memory_data <= (others => '0');
else
if (reg_memory_data_write_result = '1') then
reg_memory_data <= alu_result;
else
reg_memory_data <= reg_memory_data;
if (reg_memory_data_write_mem(0) = '1') then
reg_memory_data(7 downto 0) <= memory_data_in_i;
end if;
if (reg_memory_data_write_mem(1) = '1') then
reg_memory_data(15 downto 8) <= memory_data_in_i;
end if;
if (reg_memory_data_write_mem(2) = '1') then
reg_memory_data(23 downto 16) <= memory_data_in_i;
end if;
end if;
end if;
end if;
end process;
-- device data register
reg_device_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
reg_device_data <= (others => '0');
else
if (reg_device_data_write_result = '1') then
reg_device_data <= alu_result(7 downto 0);
elsif (reg_device_data_write_dev = '1') then
reg_device_data <= port_in_i;
else
reg_device_data <= reg_device_data;
end if;
end if;
end if;
end process;
-- instruction register
reg_instruction_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
reg_instruction <= (others => '0');
else
reg_instruction <= reg_instruction;
if (reg_instruction_write(0) = '1') then
reg_instruction(7 downto 0) <= memory_data_in_i;
end if;
if (reg_instruction_write(1) = '1') then
reg_instruction(15 downto 8) <= memory_data_in_i;
end if;
if (reg_instruction_write(2) = '1') then
reg_instruction(23 downto 16) <= memory_data_in_i;
end if;
if (reg_instruction_write(3) = '1') then
reg_instruction(31 downto 24) <= memory_data_in_i;
end if;
end if;
end if;
end process;
insn_opcode <= reg_instruction(31 downto 24);
insn_flag_n <= reg_instruction(25);
insn_flag_i <= reg_instruction(24);
insn_flag_x <= reg_instruction(23);
insn_flag_b <= reg_instruction(22);
insn_flag_p <= reg_instruction(21);
insn_flag_e <= reg_instruction(20);
insn_r1 <= reg_instruction(23 downto 20);
insn_r2 <= reg_instruction(19 downto 16);
insn_operand_f3_usgn <= std_logic_vector(
resize(unsigned(reg_instruction(19 downto 8)), 24));
insn_operand_f3_sgn <= std_logic_vector(
resize(signed(reg_instruction(19 downto 8)), 24));
insn_operand_f4_usgn <= std_logic_vector(
resize(unsigned(reg_instruction(19 downto 0)), 24));
insn_operand_sic <= std_logic_vector(
resize(unsigned(reg_instruction(22 downto 8)), 24));
insn_r1_valid_proc : process(insn_r1)
begin
case (insn_r1) is
when x"0" | x"1" | x"2" | x"3" | x"4" | x"5" =>
insn_r1_valid <= '1';
when others =>
insn_r1_valid <= '0';
end case;
end process;
insn_r2_valid_proc : process(insn_r2)
begin
case (insn_r2) is
when x"0" | x"1" | x"2" | x"3" | x"4" | x"5" =>
insn_r2_valid <= '1';
when others =>
insn_r2_valid <= '0';
end case;
end process;
-- operand select
select_op1_proc : process(select_op1, reg_operand1, reg_general_x,
reg_special_target, reg_special_pc, reg_special_il,
reg_memory_data, reg_device_data, insn_operand_f3_usgn,
insn_operand_f3_sgn, insn_operand_f4_usgn, insn_operand_sic)
begin
case (select_op1) is
when SELECT_OP1_ROP1 =>
alu_operand1 <= reg_operand1;
when SELECT_OP1_X =>
alu_operand1 <= reg_general_x;
when SELECT_OP1_TARGET =>
alu_operand1 <= reg_special_target;
when SELECT_OP1_PC =>
alu_operand1 <= "0000" & reg_special_pc;
when SELECT_OP1_IL =>
alu_operand1 <= "0000" & reg_special_il;
when SELECT_OP1_MEM =>
alu_operand1 <= reg_memory_data;
when SELECT_OP1_MEM_BYTE =>
alu_operand1 <= x"0000" & reg_memory_data(7 downto 0);
when SELECT_OP1_DEV =>
alu_operand1 <= x"0000" & reg_device_data;
when SELECT_OP1_F3USGN =>
alu_operand1 <= insn_operand_f3_usgn;
when SELECT_OP1_F3SGN =>
alu_operand1 <= insn_operand_f3_sgn;
when SELECT_OP1_F4USGN =>
alu_operand1 <= insn_operand_f4_usgn;
when SELECT_OP1_SIC =>
alu_operand1 <= insn_operand_sic;
when others =>
alu_operand1 <= (others => '0');
end case;
end process;
select_op2_proc : process(select_op2, reg_operand2, reg_operand3, reg_general_a,
reg_general_x, reg_general_b, reg_general_l,
reg_special_pc, reg_interrupt, reg_special_icc,
reg_special_cc)
begin
case (select_op2) is
when SELECT_OP2_CONE =>
alu_operand2 <= x"000001";
when SELECT_OP2_CIV =>
alu_operand2 <= x"0ffffd";
when SELECT_OP2_ROP2 =>
alu_operand2 <= reg_operand2;
when SELECT_OP2_ROP3 =>
alu_operand2 <= reg_operand3;
when SELECT_OP2_A =>
alu_operand2 <= reg_general_a;
when SELECT_OP2_X =>
alu_operand2 <= reg_general_x;
when SELECT_OP2_B =>
alu_operand2 <= reg_general_b;
when SELECT_OP2_L =>
alu_operand2 <= reg_general_l;
when SELECT_OP2_PC =>
alu_operand2 <= "0000" & reg_special_pc;
when SELECT_OP2_SW =>
alu_operand2 <= x"0000" & "000" &
reg_interrupt & reg_special_icc & reg_special_cc;
when others =>
alu_operand2 <= (others => '0');
end case;
end process;
-- memory address select
select_addr_proc : process(select_addr, reg_special_target, reg_special_pc)
begin
case (select_addr) is
when SELECT_ADDR_PC =>
memory_address_o <= reg_special_pc;
when SELECT_ADDR_TARGET =>
memory_address_o <= reg_special_target(19 downto 0);
when others =>
memory_address_o <= (others => '0');
end case;
end process;
-- memory out data select
select_mem_proc : process(select_mem, reg_memory_data)
begin
case (select_mem) is
when SELECT_MEM_BYTE0 =>
memory_data_out_o <= reg_memory_data(7 downto 0);
when SELECT_MEM_BYTE1 =>
memory_data_out_o <= reg_memory_data(15 downto 8);
when SELECT_MEM_BYTE2 =>
memory_data_out_o <= reg_memory_data(23 downto 16);
when others =>
memory_data_out_o <= (others => '0');
end case;
end process;
-- other connections
port_id_o <= reg_special_target(7 downto 0);
port_out_o <= reg_device_data;
alu_shift_bits <= insn_r2;
interrupt_enabled_o <= reg_interrupt;
-- control unit FSM
ctl_sync_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
ctl_state <= CTL_DISABLED;
else
ctl_state <= ctl_next_state;
end if;
end if;
end process;
ctl_state_proc : process(ctl_state, enable_i, interrupt_i, reg_interrupt,
insn_opcode, insn_r1_valid, insn_r2_valid,
insn_flag_n, insn_flag_i, insn_flag_x, insn_flag_b,
insn_flag_p, insn_flag_e, memory_done_i)
begin
ctl_next_state <= ctl_state;
case (ctl_state) is
-- special states
when CTL_ERROR =>
when CTL_DISABLED =>
if (enable_i = '1') then
if (reg_interrupt = '1' and interrupt_i = '1') then
ctl_next_state <= CTL_INT0;
else
ctl_next_state <= CTL_INSN0;
end if;
end if;
-- instruction read & decode
when CTL_INSN0 =>
if (memory_done_i = '1') then
ctl_next_state <= CTL_DECODE0;
end if;
when CTL_DECODE0 =>
case (insn_opcode) is
when OPCODE_LONG_EINT =>
ctl_next_state <= CTL_F1_EINT;
when OPCODE_LONG_DINT =>
ctl_next_state <= CTL_F1_DINT;
when OPCODE_LONG_RINT =>
ctl_next_state <= CTL_F1_RINT;
when OPCODE_LONG_CLEAR | OPCODE_LONG_RMO | OPCODE_LONG_ADDR |
OPCODE_LONG_SUBR | OPCODE_LONG_MULR | OPCODE_LONG_SHIFTL |
OPCODE_LONG_SHIFTR | OPCODE_LONG_COMPR | OPCODE_LONG_TIXR |
OPCODE_LONG_ANDR | OPCODE_LONG_ORR | OPCODE_LONG_XORR |
OPCODE_LONG_NOT =>
ctl_next_state <= CTL_F2_INSN1;
when others =>
case (insn_opcode(7 downto 2)) is
when OPCODE_SHORT_ADD | OPCODE_SHORT_SUB |OPCODE_SHORT_MUL |
OPCODE_SHORT_AND |OPCODE_SHORT_OR | OPCODE_SHORT_COMP |
OPCODE_SHORT_TIX | OPCODE_SHORT_J | OPCODE_SHORT_JEQ |
OPCODE_SHORT_JGT | OPCODE_SHORT_JLT | OPCODE_SHORT_JSUB |
OPCODE_SHORT_RSUB | OPCODE_SHORT_LDCH | OPCODE_SHORT_LDA |
OPCODE_SHORT_LDB | OPCODE_SHORT_LDL | OPCODE_SHORT_LDS |
OPCODE_SHORT_LDT | OPCODE_SHORT_LDX | OPCODE_SHORT_STCH |
OPCODE_SHORT_STSW | OPCODE_SHORT_STA | OPCODE_SHORT_STB |
OPCODE_SHORT_STL | OPCODE_SHORT_STS | OPCODE_SHORT_STT |
OPCODE_SHORT_STX | OPCODE_SHORT_TD | OPCODE_SHORT_RD |
OPCODE_SHORT_WD | OPCODE_SHORT_XOR | OPCODE_SHORT_STIL =>
ctl_next_state <= CTL_F34_INSN1;
when others =>
ctl_next_state <= CTL_ERROR;
end case;
end case;
-- format 1 instructions
when CTL_F1_EINT | CTL_F1_DINT =>
if (enable_i = '1') then
ctl_next_state <= CTL_INSN0;
else
ctl_next_state <= CTL_DISABLED;
end if;
-- format 2 instructions
when CTL_F2_INSN1 =>
if (memory_done_i = '1') then
ctl_next_state <= CTL_F2_DECODE1;
end if;
when CTL_F2_DECODE1 =>
case (insn_opcode) is
when OPCODE_LONG_CLEAR | OPCODE_LONG_NOT |
OPCODE_LONG_SHIFTL | OPCODE_LONG_SHIFTR =>
if (insn_r1_valid = '1') then
ctl_next_state <= CTL_F2_ALU0;
else
ctl_next_state <= CTL_ERROR;
end if;
when OPCODE_LONG_COMPR =>
if (insn_r1_valid = '1' and insn_r2_valid = '1') then
ctl_next_state <= CTL_F2_COMP;
else
ctl_next_state <= CTL_ERROR;
end if;
when OPCODE_LONG_TIXR =>
if (insn_r1_valid = '1') then
ctl_next_state <= CTL_F2_TIX0;
else
ctl_next_state <= CTL_ERROR;
end if;
when others =>
if (insn_r1_valid = '1' and insn_r2_valid = '1') then
ctl_next_state <= CTL_F2_ALU0;
else
ctl_next_state <= CTL_ERROR;
end if;
end case;
when CTL_F2_ALU0 =>
ctl_next_state <= CTL_F2_ALU1;
when CTL_F2_TIX0 =>
ctl_next_state <= CTL_F2_TIX1;
when CTL_F2_TIX1 =>
ctl_next_state <= CTL_F2_TIX2;
-- format S34 instructions
when CTL_F34_INSN1 =>
if (memory_done_i = '1') then
ctl_next_state <= CTL_F34_INSN2;
end if;
when CTL_F34_INSN2 =>
if (memory_done_i = '1') then
if (insn_flag_e = '1') then
ctl_next_state <= CTL_F34_INSN3;
else
ctl_next_state <= CTL_F34_DECODE1;
end if;
end if;
when CTL_F34_INSN3 =>
if (memory_done_i = '1') then
ctl_next_state <= CTL_F34_DECODE1;
end if;
when CTL_F34_DECODE1 =>
if (insn_opcode(7 downto 2) = OPCODE_SHORT_RSUB) then
ctl_next_state <= CTL_F34_RSUB;
else
if (insn_flag_n = '0' and insn_flag_i = '0') then
-- simple addressing (SIC)
if (insn_flag_x = '1') then
ctl_next_state <= CTL_F34_INDEXED;
else
ctl_next_state <= CTL_F34_DECODE2;
end if;
else
if ((insn_flag_b = '1' and insn_flag_p = '1') or
(insn_flag_e = '1' and (insn_flag_b = '1' or insn_flag_p = '1'))) then
-- invalid addressing
ctl_next_state <= CTL_ERROR;
else
if (insn_flag_n = '1' and insn_flag_i = '1') then
-- simple addressing
if (insn_flag_x = '1') then
ctl_next_state <= CTL_F34_INDEXED;
else
ctl_next_state <= CTL_F34_DECODE2;
end if;
else
if (insn_flag_x = '1') then
-- invalid addressing
ctl_next_state <= CTL_ERROR;
else
if (insn_flag_n = '0' and insn_flag_i = '1') then
-- immediate addressing
ctl_next_state <= CTL_F34_DECODE2;
else
-- indirect addressing
ctl_next_state <= CTL_F34_INDIRECT0;
end if;
end if;
end if;
end if;
end if;
end if;
when CTL_F34_INDEXED =>
ctl_next_state <= CTL_F34_DECODE2;
when CTL_F34_INDIRECT0 =>
if (memory_done_i = '1') then
ctl_next_state <= CTL_F34_INDIRECT1;
end if;
when CTL_F34_INDIRECT1 =>
if (memory_done_i = '1') then
ctl_next_state <= CTL_F34_INDIRECT2;
end if;
when CTL_F34_INDIRECT2 =>
if (memory_done_i = '1') then
ctl_next_state <= CTL_F34_INDIRECT3;
end if;
when CTL_F34_INDIRECT3 =>
ctl_next_state <= CTL_F34_DECODE2;
when CTL_F34_DECODE2 =>
case (insn_opcode(7 downto 2)) is
when OPCODE_SHORT_LDCH | OPCODE_SHORT_TD | OPCODE_SHORT_RD |
OPCODE_SHORT_WD =>
if (insn_flag_n = '0' and insn_flag_i = '1') then
ctl_next_state <= CTL_F34B_DECODE3;
else
ctl_next_state <= CTL_F34B_LOAD0;
end if;
when OPCODE_SHORT_STSW =>
if (insn_flag_n = '0' and insn_flag_i = '1') then
ctl_next_state <= CTL_ERROR;
else
ctl_next_state <= CTL_F34B_STSW;
end if;
when OPCODE_SHORT_STCH =>
if (insn_flag_n = '0' and insn_flag_i = '1') then
ctl_next_state <= CTL_ERROR;
else
ctl_next_state <= CTL_F34B_STCH;
end if;
when OPCODE_SHORT_STIL =>
if (insn_flag_n = '0' and insn_flag_i = '1') then
ctl_next_state <= CTL_ERROR;
else
ctl_next_state <= CTL_F34W_STIL;
end if;
when OPCODE_SHORT_STA | OPCODE_SHORT_STB | OPCODE_SHORT_STL |
OPCODE_SHORT_STS | OPCODE_SHORT_STT | OPCODE_SHORT_STX =>
if (insn_flag_n = '0' and insn_flag_i = '1') then
ctl_next_state <= CTL_ERROR;
else
ctl_next_state <= CTL_F34W_STR0;
end if;
when OPCODE_SHORT_J | OPCODE_SHORT_JEQ | OPCODE_SHORT_JGT |
OPCODE_SHORT_JLT =>
ctl_next_state <= CTL_F34_JUMP;
when OPCODE_SHORT_JSUB =>
ctl_next_state <= CTL_F34_JSUB0;
when others =>
if (insn_flag_n = '0' and insn_flag_i = '1') then
ctl_next_state <= CTL_F34W_DECODE3;
else
ctl_next_state <= CTL_F34W_LOAD0;
end if;
end case;
-- format S34 instructions - device operations and load byte
when CTL_F34B_LOAD0 =>
if (memory_done_i = '1') then
ctl_next_state <= CTL_F34B_LOAD1;
end if;
when CTL_F34B_LOAD1 =>
ctl_next_state <= CTL_F34B_DECODE3;
when CTL_F34B_DECODE3 =>
case (insn_opcode(7 downto 2)) is
when OPCODE_SHORT_LDCH =>
ctl_next_state <= CTL_F34B_LDCH0;
when OPCODE_SHORT_TD =>
ctl_next_state <= CTL_F34B_TD;
when OPCODE_SHORT_RD =>
ctl_next_state <= CTL_F34B_RD0;
when OPCODE_SHORT_WD =>
ctl_next_state <= CTL_F34B_WD0;
when others =>
end case;
when CTL_F34B_RD0 =>
ctl_next_state <= CTL_F34B_RD1;
when CTL_F34B_RD1 =>
ctl_next_state <= CTL_F34B_RD2;
when CTL_F34B_RD2 =>
ctl_next_state <= CTL_F34B_RD3;
when CTL_F34B_WD0 =>
ctl_next_state <= CTL_F34B_WD1;
when CTL_F34B_WD1 =>
ctl_next_state <= CTL_F34B_WD2;
when CTL_F34B_LDCH0 =>
ctl_next_state <= CTL_F34B_LDCH1;
-- format S34 instructions - store
when CTL_F34B_STSW =>
ctl_next_state <= CTL_F34_STORE2;
when CTL_F34B_STCH =>
ctl_next_state <= CTL_F34_STORE2;
when CTL_F34W_STR0 =>
ctl_next_state <= CTL_F34W_STR1;
when CTL_F34W_STR1 =>
ctl_next_state <= CTL_F34_STORE0;
when CTL_F34W_STIL =>
ctl_next_state <= CTL_F34_STORE0;
when CTL_F34_STORE0 =>
if (memory_done_i = '1') then
ctl_next_state <= CTL_F34_STORE1;
end if;
when CTL_F34_STORE1 =>
if (memory_done_i = '1') then
ctl_next_state <= CTL_F34_STORE2;
end if;
when CTL_F34_STORE2 =>
if (memory_done_i = '1') then
if (enable_i = '1') then
if (reg_interrupt = '1' and interrupt_i = '1') then
ctl_next_state <= CTL_INT0;
else
ctl_next_state <= CTL_INSN0;
end if;
else
ctl_next_state <= CTL_DISABLED;
end if;
end if;
-- format S34 instructions - jump
when CTL_F34_JSUB0 =>
ctl_next_state <= CTL_F34_JSUB1;
-- format S34 instructions - load, ALU and others
when CTL_F34W_LOAD0 =>
if (memory_done_i = '1') then
ctl_next_state <= CTL_F34W_LOAD1;
end if;
when CTL_F34W_LOAD1 =>
if (memory_done_i = '1') then
ctl_next_state <= CTL_F34W_LOAD2;
end if;
when CTL_F34W_LOAD2 =>
if (memory_done_i = '1') then
ctl_next_state <= CTL_F34W_LOAD3;
end if;
when CTL_F34W_LOAD3 =>
ctl_next_state <= CTL_F34W_DECODE3;
when CTL_F34W_DECODE3 =>
case (insn_opcode(7 downto 2)) is
when OPCODE_SHORT_LDA | OPCODE_SHORT_LDB | OPCODE_SHORT_LDL |
OPCODE_SHORT_LDS | OPCODE_SHORT_LDT | OPCODE_SHORT_LDX =>
ctl_next_state <= CTL_F34W_LDR0;
when OPCODE_SHORT_COMP =>
ctl_next_state <= CTL_F34W_COMP;
when OPCODE_SHORT_TIX =>
ctl_next_state <= CTL_F34W_TIX0;
when OPCODE_SHORT_ADD | OPCODE_SHORT_SUB | OPCODE_SHORT_MUL |
OPCODE_SHORT_AND | OPCODE_SHORT_OR | OPCODE_SHORT_XOR =>
ctl_next_state <= CTL_F34W_ALU0;
when others =>
end case;
when CTL_F34W_LDR0 =>
ctl_next_state <= CTL_F34W_LDR1;
when CTL_F34W_TIX0 =>
ctl_next_state <= CTL_F34W_TIX1;
when CTL_F34W_TIX1 =>
ctl_next_state <= CTL_F34W_TIX2;
when CTL_F34W_ALU0 =>
ctl_next_state <= CTL_F34W_ALU1;
-- interrupt cycle
when CTL_INT0 =>
ctl_next_state <= CTL_INT1;
when CTL_INT1 =>
ctl_next_state <= CTL_INT2;
when CTL_INT2 =>
if (memory_done_i = '1') then
ctl_next_state <= CTL_INT3;
end if;
when CTL_INT3 =>
if (memory_done_i = '1') then
ctl_next_state <= CTL_INT4;
end if;
when CTL_INT4 =>
if (memory_done_i = '1') then
ctl_next_state <= CTL_INT5;
end if;
when CTL_INT5 =>
if (enable_i = '1') then
ctl_next_state <= CTL_INSN0;
else
ctl_next_state <= CTL_DISABLED;
end if;
-- shared logic for last state of many instructions
when CTL_F1_RINT | CTL_F2_ALU1 | CTL_F2_COMP | CTL_F2_TIX2 | CTL_F34_RSUB |
CTL_F34B_TD | CTL_F34B_RD3 | CTL_F34B_WD2 | CTL_F34B_LDCH1 |
CTL_F34_JUMP | CTL_F34_JSUB1 | CTL_F34W_LDR1 | CTL_F34W_COMP |
CTL_F34W_TIX2 | CTL_F34W_ALU1 =>
if (enable_i = '1') then
if (reg_interrupt = '1' and interrupt_i = '1') then
ctl_next_state <= CTL_INT0;
else
ctl_next_state <= CTL_INSN0;
end if;
else
ctl_next_state <= CTL_DISABLED;
end if;
when others =>
end case;
end process;
ctl_output_proc : process(ctl_state, insn_opcode, memory_done_i, insn_flag_n,
insn_flag_i, insn_flag_x, insn_flag_b, insn_flag_p,
insn_flag_e)
begin
error_o <= '0';
memory_read_o <= '0';
memory_write_o <= '0';
port_read_strobe_o <= '0';
port_write_strobe_o <= '0';
interrupt_acknowledge_o <= '0';
alu_operation <= ALU_ZERO;
reg_general_write <= '0';
reg_general_select_write <= '0';
select_general <= SELECT_GENERAL_A;
reg_operand1_write <= '0';
reg_operand2_write <= '0';
reg_operand3_write <= '0';
reg_result_write <= '0';
reg_special_target_write <= '0';
reg_special_pc_write <= '0';
reg_special_il_write <= '0';
reg_special_cc_clear <= '0';
reg_special_cc_write_left <= '0';
reg_special_cc_write_right <= '0';
reg_special_cc_save <= '0';
reg_special_cc_restore <= '0';
reg_special_pc_write_cond_lt <= '0';
reg_special_pc_write_cond_eq <= '0';
reg_special_pc_write_cond_gt <= '0';
interrupt_disable <= '0';
interrupt_enable <= '0';
interrupt_move <= '0';
reg_memory_data_write_result <= '0';
reg_memory_data_write_mem <= (others => '0');
reg_device_data_write_result <= '0';
reg_device_data_write_dev <= '0';
reg_instruction_write <= (others => '0');
select_op1 <= SELECT_OP1_ROP1;
select_op2 <= SELECT_OP2_CONE;
select_addr <= SELECT_ADDR_PC;
select_mem <= SELECT_MEM_BYTE0;
case (ctl_state) is
-- special state
when CTL_ERROR =>
error_o <= '1';
when CTL_DISABLED =>
-- instruction read & decode
when CTL_INSN0 =>
select_op1 <= SELECT_OP1_PC;
select_op2 <= SELECT_OP2_CONE;
alu_operation <= ALU_ADD;
select_addr <= SELECT_ADDR_PC;
memory_read_o <= '1';
if (memory_done_i = '1') then
reg_instruction_write(3) <= '1';
reg_special_pc_write <= '1';
interrupt_move <= '1';
end if;
when CTL_DECODE0 =>
-- format 1 instructions
when CTL_F1_EINT =>
interrupt_enable <= '1';
when CTL_F1_DINT =>
interrupt_disable <= '1';
when CTL_F1_RINT =>
select_op1 <= SELECT_OP1_IL;
alu_operation <= ALU_PASS1;
reg_special_pc_write <= '1';
reg_special_cc_restore <= '1';
-- format 2 instructions
when CTL_F2_INSN1 =>
select_op1 <= SELECT_OP1_PC;
select_op2 <= SELECT_OP2_CONE;
alu_operation <= ALU_ADD;
select_addr <= SELECT_ADDR_PC;
memory_read_o <= '1';
if (memory_done_i = '1') then
reg_instruction_write(2) <= '1';
reg_special_pc_write <= '1';
end if;
when CTL_F2_DECODE1 =>
reg_operand1_write <= '1';
reg_operand2_write <= '1';
when CTL_F2_ALU0 =>
select_op1 <= SELECT_OP1_ROP1;
select_op2 <= SELECT_OP2_ROP2;
reg_result_write <= '1';
reg_general_select_write <= '1';
case (insn_opcode) is
when OPCODE_LONG_CLEAR | OPCODE_LONG_NOT |
OPCODE_LONG_SHIFTL | OPCODE_LONG_SHIFTR =>
select_general <= SELECT_GENERAL_R1;
when others =>
select_general <= SELECT_GENERAL_R2;
end case;
case (insn_opcode) is
when OPCODE_LONG_CLEAR =>
alu_operation <= ALU_ZERO;
when OPCODE_LONG_RMO =>
alu_operation <= ALU_PASS1;
when OPCODE_LONG_ADDR =>
alu_operation <= ALU_ADD;
when OPCODE_LONG_SUBR =>
alu_operation <= ALU_SUB;
when OPCODE_LONG_MULR =>
alu_operation <= ALU_MUL;
when OPCODE_LONG_SHIFTL =>
alu_operation <= ALU_SHIFTL;
when OPCODE_LONG_SHIFTR =>
alu_operation <= ALU_SHIFTR;
when OPCODE_LONG_ANDR =>
alu_operation <= ALU_AND;
when OPCODE_LONG_ORR =>
alu_operation <= ALU_OR;
when OPCODE_LONG_XORR =>
alu_operation <= ALU_XOR;
when OPCODE_LONG_NOT =>
alu_operation <= ALU_NOT;
when others =>
end case;
when CTL_F2_ALU1 =>
reg_general_write <= '1';
when CTL_F2_COMP =>
select_op1 <= SELECT_OP1_ROP1;
select_op2 <= SELECT_OP2_ROP2;
reg_special_cc_write_left <= '1';
when CTL_F2_TIX0 =>
select_op1 <= SELECT_OP1_X;
select_op2 <= SELECT_OP2_CONE;
alu_operation <= ALU_ADD;
reg_result_write <= '1';
reg_general_select_write <= '1';
select_general <= SELECT_GENERAL_X;
when CTL_F2_TIX1 =>
reg_general_write <= '1';
when CTL_F2_TIX2 =>
select_op1 <= SELECT_OP1_ROP1;
select_op2 <= SELECT_OP2_X;
reg_special_cc_write_right <= '1';
-- format S34 instructions
when CTL_F34_INSN1 =>
select_op1 <= SELECT_OP1_PC;
select_op2 <= SELECT_OP2_CONE;
alu_operation <= ALU_ADD;
select_addr <= SELECT_ADDR_PC;
memory_read_o <= '1';
if (memory_done_i = '1') then
reg_instruction_write(2) <= '1';
reg_special_pc_write <= '1';
end if;
when CTL_F34_INSN2 =>
select_op1 <= SELECT_OP1_PC;
select_op2 <= SELECT_OP2_CONE;
alu_operation <= ALU_ADD;
select_addr <= SELECT_ADDR_PC;
memory_read_o <= '1';
if (memory_done_i = '1') then
reg_instruction_write(1) <= '1';
reg_special_pc_write <= '1';
end if;
when CTL_F34_INSN3 =>
select_op1 <= SELECT_OP1_PC;
select_op2 <= SELECT_OP2_CONE;
alu_operation <= ALU_ADD;
select_addr <= SELECT_ADDR_PC;
memory_read_o <= '1';
if (memory_done_i = '1') then
reg_instruction_write(0) <= '1';
reg_special_pc_write <= '1';
end if;
when CTL_F34_DECODE1 =>
if (insn_flag_n = '0' and insn_flag_i = '0') then
select_op1 <= SELECT_OP1_SIC;
else
if (insn_flag_e = '1') then
select_op1 <= SELECT_OP1_F4USGN;
else
if (insn_flag_p = '1') then
select_op1 <= SELECT_OP1_F3SGN;
else
select_op1 <= SELECT_OP1_F3USGN;
end if;
end if;
end if;
if (insn_flag_b = '1' and insn_flag_p = '0') then
select_op2 <= SELECT_OP2_B;
alu_operation <= ALU_ADD;
elsif (insn_flag_b = '0' and insn_flag_p = '1') then
select_op2 <= SELECT_OP2_PC;
alu_operation <= ALU_ADD;
else
alu_operation <= ALU_PASS1;
end if;
reg_special_target_write <= '1';
when CTL_F34_INDEXED =>
select_op1 <= SELECT_OP1_TARGET;
select_op2 <= SELECT_OP2_X;
alu_operation <= ALU_ADD;
reg_special_target_write <= '1';
when CTL_F34_INDIRECT0 =>
select_op1 <= SELECT_OP1_TARGET;
select_op2 <= SELECT_OP2_CONE;
alu_operation <= ALU_ADD;
select_addr <= SELECT_ADDR_TARGET;
memory_read_o <= '1';
if (memory_done_i = '1') then
reg_memory_data_write_mem(2) <= '1';
reg_special_target_write <= '1';
end if;
when CTL_F34_INDIRECT1 =>
select_op1 <= SELECT_OP1_TARGET;
select_op2 <= SELECT_OP2_CONE;
alu_operation <= ALU_ADD;
select_addr <= SELECT_ADDR_TARGET;
memory_read_o <= '1';
if (memory_done_i = '1') then
reg_memory_data_write_mem(1) <= '1';
reg_special_target_write <= '1';
end if;
when CTL_F34_INDIRECT2 =>
select_addr <= SELECT_ADDR_TARGET;
memory_read_o <= '1';
if (memory_done_i = '1') then
reg_memory_data_write_mem(0) <= '1';
end if;
when CTL_F34_INDIRECT3 =>
select_op1 <= SELECT_OP1_MEM;
alu_operation <= ALU_PASS1;
reg_special_target_write <= '1';
when CTL_F34_DECODE2 =>
-- format S34 instructions - rsub
when CTL_F34_RSUB =>
select_op2 <= SELECT_OP2_L;
alu_operation <= ALU_PASS2;
reg_special_pc_write <= '1';
-- format S34 instructions - device operations and load byte
when CTL_F34B_LOAD0 =>
select_addr <= SELECT_ADDR_TARGET;
memory_read_o <= '1';
if (memory_done_i = '1') then
reg_memory_data_write_mem(0) <= '1';
end if;
when CTL_F34B_LOAD1 =>
select_op1 <= SELECT_OP1_MEM_BYTE;
alu_operation <= ALU_PASS1;
reg_special_target_write <= '1';
when CTL_F34B_DECODE3 =>
select_general <= SELECT_GENERAL_A;
reg_general_select_write <= '1';
when CTL_F34B_TD =>
reg_special_cc_clear <= '1';
when CTL_F34B_RD0 =>
when CTL_F34B_RD1 =>
port_read_strobe_o <= '1';
reg_device_data_write_dev <= '1';
when CTL_F34B_RD2 =>
select_op1 <= SELECT_OP1_DEV;
alu_operation <= ALU_PASS1;
reg_result_write <= '1';
when CTL_F34B_RD3 =>
reg_general_write <= '1';
when CTL_F34B_WD0 =>
select_op2 <= SELECT_OP2_A;
alu_operation <= ALU_PASS2;
reg_device_data_write_result <= '1';
when CTL_F34B_WD1 =>
when CTL_F34B_WD2 =>
port_write_strobe_o <= '1';
when CTL_F34B_LDCH0 =>
select_op1 <= SELECT_OP1_TARGET;
alu_operation <= ALU_PASS1;
reg_result_write <= '1';
when CTL_F34B_LDCH1 =>
reg_general_write <= '1';
-- format S34 instructions - store
when CTL_F34B_STSW =>
select_op2 <= SELECT_OP2_SW;
alu_operation <= ALU_PASS2;
reg_memory_data_write_result <= '1';
when CTL_F34B_STCH =>
select_op2 <= SELECT_OP2_A;
alu_operation <= ALU_PASS2;
reg_memory_data_write_result <= '1';
when CTL_F34W_STR0 =>
reg_operand3_write <= '1';
when CTL_F34W_STR1 =>
select_op2 <= SELECT_OP2_ROP3;
alu_operation <= ALU_PASS2;
reg_memory_data_write_result <= '1';
when CTL_F34_STORE0 =>
select_op1 <= SELECT_OP1_TARGET;
select_op2 <= SELECT_OP2_CONE;
alu_operation <= ALU_ADD;
select_addr <= SELECT_ADDR_TARGET;
select_mem <= SELECT_MEM_BYTE2;
memory_write_o <= '1';
if (memory_done_i = '1') then
reg_special_target_write <= '1';
end if;
when CTL_F34_STORE1 =>
select_op1 <= SELECT_OP1_TARGET;
select_op2 <= SELECT_OP2_CONE;
alu_operation <= ALU_ADD;
select_addr <= SELECT_ADDR_TARGET;
select_mem <= SELECT_MEM_BYTE1;
memory_write_o <= '1';
if (memory_done_i = '1') then
reg_special_target_write <= '1';
end if;
when CTL_F34_STORE2 =>
select_addr <= SELECT_ADDR_TARGET;
select_mem <= SELECT_MEM_BYTE0;
memory_write_o <= '1';
-- format S34 instructions - jump
when CTL_F34_JUMP =>
select_op1 <= SELECT_OP1_TARGET;
alu_operation <= ALU_PASS1;
case (insn_opcode(7 downto 2)) is
when OPCODE_SHORT_J =>
reg_special_pc_write <= '1';
when OPCODE_SHORT_JLT =>
reg_special_pc_write_cond_lt <= '1';
when OPCODE_SHORT_JEQ =>
reg_special_pc_write_cond_eq <= '1';
when OPCODE_SHORT_JGT =>
reg_special_pc_write_cond_gt <= '1';
when others =>
end case;
when CTL_F34_JSUB0 =>
select_general <= SELECT_GENERAL_L;
reg_general_select_write <= '1';
select_op1 <= SELECT_OP1_PC;
alu_operation <= ALU_PASS1;
reg_result_write <= '1';
when CTL_F34_JSUB1 =>
reg_general_write <= '1';
select_op1 <= SELECT_OP1_TARGET;
alu_operation <= ALU_PASS1;
reg_special_pc_write <= '1';
-- format S34 instructions - load, ALU and others
when CTL_F34W_LOAD0 =>
select_op1 <= SELECT_OP1_TARGET;
select_op2 <= SELECT_OP2_CONE;
alu_operation <= ALU_ADD;
select_addr <= SELECT_ADDR_TARGET;
memory_read_o <= '1';
if (memory_done_i = '1') then
reg_memory_data_write_mem(2) <= '1';
reg_special_target_write <= '1';
end if;
when CTL_F34W_LOAD1 =>
select_op1 <= SELECT_OP1_TARGET;
select_op2 <= SELECT_OP2_CONE;
alu_operation <= ALU_ADD;
select_addr <= SELECT_ADDR_TARGET;
memory_read_o <= '1';
if (memory_done_i = '1') then
reg_memory_data_write_mem(1) <= '1';
reg_special_target_write <= '1';
end if;
when CTL_F34W_LOAD2 =>
select_addr <= SELECT_ADDR_TARGET;
memory_read_o <= '1';
if (memory_done_i = '1') then
reg_memory_data_write_mem(0) <= '1';
end if;
when CTL_F34W_LOAD3 =>
select_op1 <= SELECT_OP1_MEM;
alu_operation <= ALU_PASS1;
reg_special_target_write <= '1';
when CTL_F34W_DECODE3 =>
when CTL_F34W_LDR0 =>
select_general <= SELECT_GENERAL_LOAD_INSN;
reg_general_select_write <= '1';
select_op1 <= SELECT_OP1_TARGET;
alu_operation <= ALU_PASS1;
reg_result_write <= '1';
when CTL_F34W_LDR1 =>
reg_general_write <= '1';
when CTL_F34W_COMP =>
select_op1 <= SELECT_OP1_TARGET;
select_op2 <= SELECT_OP2_A;
reg_special_cc_write_right <= '1';
when CTL_F34W_TIX0 =>
select_op1 <= SELECT_OP1_X;
select_op2 <= SELECT_OP2_CONE;
alu_operation <= ALU_ADD;
reg_result_write <= '1';
reg_general_select_write <= '1';
select_general <= SELECT_GENERAL_X;
when CTL_F34W_TIX1 =>
reg_general_write <= '1';
when CTL_F34W_TIX2 =>
select_op1 <= SELECT_OP1_TARGET;
select_op2 <= SELECT_OP2_X;
reg_special_cc_write_right <= '1';
when CTL_F34W_ALU0 =>
select_general <= SELECT_GENERAL_A;
reg_general_select_write <= '1';
reg_result_write <= '1';
select_op1 <= SELECT_OP1_TARGET;
select_op2 <= SELECT_OP2_A;
case (insn_opcode(7 downto 2)) is
when OPCODE_SHORT_ADD =>
alu_operation <= ALU_ADD;
when OPCODE_SHORT_SUB =>
alu_operation <= ALU_SUB;
when OPCODE_SHORT_MUL =>
alu_operation <= ALU_MUL;
when OPCODE_SHORT_AND =>
alu_operation <= ALU_AND;
when OPCODE_SHORT_OR =>
alu_operation <= ALU_OR;
when OPCODE_SHORT_XOR =>
alu_operation <= ALU_XOR;
when others =>
end case;
when CTL_F34W_ALU1 =>
reg_general_write <= '1';
-- interrupt cycle
when CTL_INT0 =>
interrupt_acknowledge_o <= '1';
interrupt_disable <= '1';
select_op1 <= SELECT_OP1_PC;
alu_operation <= ALU_PASS1;
reg_special_il_write <= '1';
reg_special_cc_save <= '1';
when CTL_INT1 =>
select_op2 <= SELECT_OP2_CIV;
alu_operation <= ALU_PASS2;
reg_special_target_write <= '1';
when CTL_INT2 =>
select_op1 <= SELECT_OP1_TARGET;
select_op2 <= SELECT_OP2_CONE;
alu_operation <= ALU_ADD;
select_addr <= SELECT_ADDR_TARGET;
memory_read_o <= '1';
if (memory_done_i = '1') then
reg_memory_data_write_mem(2) <= '1';
reg_special_target_write <= '1';
end if;
when CTL_INT3 =>
select_op1 <= SELECT_OP1_TARGET;
select_op2 <= SELECT_OP2_CONE;
alu_operation <= ALU_ADD;
select_addr <= SELECT_ADDR_TARGET;
memory_read_o <= '1';
if (memory_done_i = '1') then
reg_memory_data_write_mem(1) <= '1';
reg_special_target_write <= '1';
end if;
when CTL_INT4 =>
select_addr <= SELECT_ADDR_TARGET;
memory_read_o <= '1';
if (memory_done_i = '1') then
reg_memory_data_write_mem(0) <= '1';
end if;
when CTL_INT5 =>
select_op1 <= SELECT_OP1_MEM;
alu_operation <= ALU_PASS1;
reg_special_pc_write <= '1';
when others =>
end case;
end process;
end behavioral;
|
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY selfOR IS
GENERIC
(
size : integer
);
PORT
(
input : IN std_logic_vector(size-1 downto 0);
output : OUT std_logic
);
END selfOR;
ARCHITECTURE behavior OF selfOR IS
SIGNAL tempres : std_logic_vector(size downto 0);
BEGIN
tempres(0) <= '0';
gen : FOR I IN 0 TO size-1 GENERATE
tempres(I+1) <= input(I) OR tempres(I);
END GENERATE gen;
output <= tempres(size);
END behavior; |
----------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hscale4 is
Port ( CLK : in STD_LOGIC;
D_HSYNC : in STD_LOGIC;
D_VSYNC : in STD_LOGIC;
D_DATAENABLE : in STD_LOGIC;
D_R : in STD_LOGIC_VECTOR (7 downto 0);
D_G : in STD_LOGIC_VECTOR (7 downto 0);
D_B : in STD_LOGIC_VECTOR (7 downto 0);
Q_HSYNC : out STD_LOGIC;
Q_VSYNC : out STD_LOGIC;
Q_DATAENABLE : out STD_LOGIC;
CE2 : out STD_LOGIC;
CE4 : out STD_LOGIC;
Q_R : out STD_LOGIC_VECTOR (7 downto 0);
Q_G : out STD_LOGIC_VECTOR (7 downto 0);
Q_B : out STD_LOGIC_VECTOR (7 downto 0));
end hscale4;
architecture Behavioral of hscale4 is
signal COUNT : std_logic_vector(1 downto 0);
signal DATAENABLE_LAST : std_logic;
signal R1 : std_logic_vector(7 downto 0);
signal R2 : std_logic_vector(7 downto 0);
signal R3 : std_logic_vector(7 downto 0);
signal RSUM1 : std_logic_vector(8 downto 0);
signal RSUM2 : std_logic_vector(8 downto 0);
signal RSUM3 : std_logic_vector(8 downto 0);
signal RAVG : std_logic_vector(7 downto 0);
signal G1 : std_logic_vector(7 downto 0);
signal G2 : std_logic_vector(7 downto 0);
signal G3 : std_logic_vector(7 downto 0);
signal GSUM1 : std_logic_vector(8 downto 0);
signal GSUM2 : std_logic_vector(8 downto 0);
signal GSUM3 : std_logic_vector(8 downto 0);
signal GAVG : std_logic_vector(7 downto 0);
signal B1 : std_logic_vector(7 downto 0);
signal B2 : std_logic_vector(7 downto 0);
signal B3 : std_logic_vector(7 downto 0);
signal BSUM1 : std_logic_vector(8 downto 0);
signal BSUM2 : std_logic_vector(8 downto 0);
signal BSUM3 : std_logic_vector(8 downto 0);
signal BAVG : std_logic_vector(7 downto 0);
signal HSYNC : std_logic_vector(6 downto 0);
signal VSYNC : std_logic_vector(6 downto 0);
signal DATAENABLE : std_logic_vector(6 downto 0);
begin
process(CLK)
begin
if(rising_edge(CLK)) then
if(D_DATAENABLE = '1' and DATAENABLE_LAST = '0') then
COUNT <= (others => '0');
else
COUNT <= std_logic_vector(unsigned(COUNT) + 1);
end if;
DATAENABLE_LAST <= D_DATAENABLE;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
R3 <= R2;
R2 <= R1;
R1 <= D_R;
RSUM1 <= std_logic_vector(unsigned('0' & D_R) + unsigned('0' & R1));
RSUM2 <= std_logic_vector(unsigned('0' & R2) + unsigned('0' & R3));
RSUM3 <= std_logic_vector(unsigned('0' & RSUM1(8 downto 1)) + unsigned('0' & RSUM2(8 downto 1)));
if(COUNT(1 downto 0) = "01") then
RAVG <= RSUM3(8 downto 1);
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
G3 <= G2;
G2 <= G1;
G1 <= D_G;
GSUM1 <= std_logic_vector(unsigned('0' & D_G) + unsigned('0' & G1));
GSUM2 <= std_logic_vector(unsigned('0' & G2) + unsigned('0' & G3));
GSUM3 <= std_logic_vector(unsigned('0' & GSUM1(8 downto 1)) + unsigned('0' & GSUM2(8 downto 1)));
if(COUNT(1 downto 0) = "11") then
GAVG <= GSUM3(8 downto 1);
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
B3 <= B2;
B2 <= B1;
B1 <= D_B;
BSUM1 <= std_logic_vector(unsigned('0' & D_B) + unsigned('0' & B1));
BSUM2 <= std_logic_vector(unsigned('0' & B2) + unsigned('0' & B3));
BSUM3 <= std_logic_vector(unsigned('0' & BSUM1(8 downto 1)) + unsigned('0' & BSUM2(8 downto 1)));
if(COUNT(1 downto 0) = "11") then
BAVG <= BSUM3(8 downto 1);
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
HSYNC <= HSYNC(5 downto 0) & D_HSYNC;
VSYNC <= VSYNC(5 downto 0) & D_VSYNC;
DATAENABLE <= DATAENABLE(5 downto 0) & D_DATAENABLE;
end if;
end process;
Q_HSYNC <= HSYNC(6);
Q_VSYNC <= VSYNC(6);
Q_DATAENABLE <= DATAENABLE(6);
Q_R <= RAVG;
Q_G <= GAVG;
Q_B <= BAVG;
CE2 <= COUNT(0);
CE4 <= COUNT(1);
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mem_we_segment_regfile is
port
(
mem_we_segment_regfile_clk: in std_logic;
mem_we_segment_regfile_write_in: in std_logic;
mem_we_segment_regfile_result_in: in std_logic_vector(15 downto 0);
mem_we_segment_regfile_result_out: out std_logic_vector(15 downto 0);
mem_we_segment_regfile_reg_we_in: in std_logic;
mem_we_segment_regfile_reg_we_out: out std_logic;
mem_we_segment_regfile_we_result_in: in std_logic_vector (1 downto 0);
mem_we_segment_regfile_we_result_out: out std_logic_vector (1 downto 0);
mem_we_segment_regfile_imm_in: in std_logic_vector(15 downto 0);
mem_we_segment_regfile_imm_out: out std_logic_vector(15 downto 0)
);
end mem_we_segment_regfile;
architecture Behavioral of mem_we_segment_regfile is
begin
process (mem_we_segment_regfile_clk, mem_we_segment_regfile_write_in)
begin
if (mem_we_segment_regfile_write_in = '1') then
mem_we_segment_regfile_result_out <= mem_we_segment_regfile_result_in;
mem_we_segment_regfile_reg_we_out <= mem_we_segment_regfile_reg_we_in;
mem_we_segment_regfile_imm_out <= mem_we_segment_regfile_imm_in;
end if;
end process;
end Behavioral; |
------------------------------------------------------------------------------
-- Configurable parameters for the ZIPPY architecture
--
-- Project :
-- File : zarchPkg.vhd
-- Authors : Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Last changed: $LastChangedDate: 2005-01-12 12:28:20 +0100 (Wed, 12 Jan 2005) $
------------------------------------------------------------------------------
-- This file declares the user configurable architecture parameters for the
-- zippy architecture.
-- These parameters can/shall be modified by the user for defining a Zippy
-- architecture variant that is suited for the application at hand.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.auxPkg.all;
package archConfigPkg is
----------------------------------------------------------------------------
-- User configurable architecture parameter
----------------------------------------------------------------------------
constant DATAWIDTH : integer := 24; -- data path width
constant FIFODEPTH : integer := 4096; -- FIFO depth
constant N_CONTEXTS : integer := 8; -- no. of contexts
constant CNTXTWIDTH : integer := log2(N_CONTEXTS);
constant N_COLS : integer := 7; -- no. of columns (cells per row)
constant N_ROWS : integer := 7; -- no. of rows
constant N_HBUSN : integer := 2; -- no. of horizontal north buses
constant N_HBUSS : integer := 2; -- no. of horizontal south buses
constant N_VBUSE : integer := 2; -- no. of vertical east buses
constant N_MEMADDRWIDTH : integer := 7;
constant N_MEMDEPTH : integer := 2**N_MEMADDRWIDTH;
end archConfigPkg;
package body archConfigPkg is
end archConfigPkg;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity color_maker is
port (
sldsw : in std_logic_vector(2 downto 0);
red : out std_logic;
green : out std_logic;
blue : out std_logic
);
end color_maker;
architecture rtl of color_maker is
--
begin
red <= sldsw(2);
green <= sldsw(1);
blue <= sldsw(0);
end rtl;
|
architecture rtl of fifo is
constant c_zeros : std_logic_vector(7 downto 0) := (others => '0');
constant c_one : std_logic_vector(7 downto 0) := (0 => '1', (others => '0'));
constant c_two : std_logic_vector(7 downto 0) := (1 => '1', (others => '0'));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"
),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
)
);
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"
),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
)
);
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"
),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
)
);
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"
),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
)
);
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"
),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
)
);
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"
),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
)
);
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"
),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
)
);
constant c_stimulus : t_stimulus_array :=
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00" -- Comment
);
begin
end architecture rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2940.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p07n03i02940ent IS
function func1 (i,l:integer) return boolean;
END c02s02b00x00p07n03i02940ent;
ARCHITECTURE c02s02b00x00p07n03i02940arch OF c02s02b00x00p07n03i02940ent IS
-- ERROR: non-existent body for function func1
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p07n03i02940 - Every subprogram declaration has to have a corresponding body."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n03i02940arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2940.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p07n03i02940ent IS
function func1 (i,l:integer) return boolean;
END c02s02b00x00p07n03i02940ent;
ARCHITECTURE c02s02b00x00p07n03i02940arch OF c02s02b00x00p07n03i02940ent IS
-- ERROR: non-existent body for function func1
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p07n03i02940 - Every subprogram declaration has to have a corresponding body."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n03i02940arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2940.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p07n03i02940ent IS
function func1 (i,l:integer) return boolean;
END c02s02b00x00p07n03i02940ent;
ARCHITECTURE c02s02b00x00p07n03i02940arch OF c02s02b00x00p07n03i02940ent IS
-- ERROR: non-existent body for function func1
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p07n03i02940 - Every subprogram declaration has to have a corresponding body."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n03i02940arch;
|
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package befunge_pkg is
constant word_size : integer := 8;
constant instruction_size : integer := 16;
constant stack_size : integer := 2048;
constant grid_width : integer := 8;
constant grid_height : integer := 8;
type grid_nibble is array (grid_height-1 downto 0) of std_logic_vector(word_size-1 downto 0);
type grid_stuff is array (grid_width-1 downto 0) of grid_nibble;
--
-- Declare constants
--
-- constant <constant_name> : time := <time_unit> ns;
-- constant <constant_name> : integer := <value;
--
-- Declare functions and procedure
--
-- function <function_name> (signal <signal_name> : in <type_declaration>) return <type_declaration>;
-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>);
--
end befunge_pkg;
package body befunge_pkg is
---- Example 1
-- function <function_name> (signal <signal_name> : in <type_declaration> ) return <type_declaration> is
-- variable <variable_name> : <type_declaration>;
-- begin
-- <variable_name> := <signal_name> xor <signal_name>;
-- return <variable_name>;
-- end <function_name>;
---- Example 2
-- function <function_name> (signal <signal_name> : in <type_declaration>;
-- signal <signal_name> : in <type_declaration> ) return <type_declaration> is
-- begin
-- if (<signal_name> = '1') then
-- return <signal_name>;
-- else
-- return 'Z';
-- end if;
-- end <function_name>;
---- Procedure Example
-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>) is
--
-- begin
--
-- end <procedure_name>;
end befunge_pkg;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_barrelshifter is
generic (
DISTANCE_WIDTH : natural := 3;
NDIRECTION : natural := 0;
SIGNED : integer := 1;
USE_DEDICATED_CIRCUITRY : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
user_aclr : in std_logic;
distance : in std_logic_vector(DISTANCE_WIDTH-1 downto 0);
r : out std_logic_vector(WIDTH-1 downto 0);
clock : in std_logic;
direction : in std_logic;
a : in std_logic_vector(WIDTH-1 downto 0);
aclr : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_barrelshifter;
architecture rtl of alt_dspbuilder_barrelshifter is
component alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic (
DISTANCE_WIDTH : natural := 4;
NDIRECTION : natural := 1;
SIGNED : integer := 0;
USE_DEDICATED_CIRCUITRY : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 18
);
port (
a : in std_logic_vector(18-1 downto 0);
aclr : in std_logic;
clock : in std_logic;
distance : in std_logic_vector(4-1 downto 0);
ena : in std_logic;
r : out std_logic_vector(18-1 downto 0);
user_aclr : in std_logic
);
end component alt_dspbuilder_barrelshifter_GNV5DVAGHT;
begin
alt_dspbuilder_barrelshifter_GNV5DVAGHT_0: if ((DISTANCE_WIDTH = 4) and (NDIRECTION = 1) and (SIGNED = 0) and (USE_DEDICATED_CIRCUITRY = "false") and (PIPELINE = 0) and (WIDTH = 18)) generate
inst_alt_dspbuilder_barrelshifter_GNV5DVAGHT_0: alt_dspbuilder_barrelshifter_GNV5DVAGHT
generic map(DISTANCE_WIDTH => 4, NDIRECTION => 1, SIGNED => 0, USE_DEDICATED_CIRCUITRY => "false", PIPELINE => 0, WIDTH => 18)
port map(a => a, aclr => aclr, clock => clock, distance => distance, ena => ena, r => r, user_aclr => user_aclr);
end generate;
assert not (((DISTANCE_WIDTH = 4) and (NDIRECTION = 1) and (SIGNED = 0) and (USE_DEDICATED_CIRCUITRY = "false") and (PIPELINE = 0) and (WIDTH = 18)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_barrelshifter is
generic (
DISTANCE_WIDTH : natural := 3;
NDIRECTION : natural := 0;
SIGNED : integer := 1;
USE_DEDICATED_CIRCUITRY : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
user_aclr : in std_logic;
distance : in std_logic_vector(DISTANCE_WIDTH-1 downto 0);
r : out std_logic_vector(WIDTH-1 downto 0);
clock : in std_logic;
direction : in std_logic;
a : in std_logic_vector(WIDTH-1 downto 0);
aclr : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_barrelshifter;
architecture rtl of alt_dspbuilder_barrelshifter is
component alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic (
DISTANCE_WIDTH : natural := 4;
NDIRECTION : natural := 1;
SIGNED : integer := 0;
USE_DEDICATED_CIRCUITRY : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 18
);
port (
a : in std_logic_vector(18-1 downto 0);
aclr : in std_logic;
clock : in std_logic;
distance : in std_logic_vector(4-1 downto 0);
ena : in std_logic;
r : out std_logic_vector(18-1 downto 0);
user_aclr : in std_logic
);
end component alt_dspbuilder_barrelshifter_GNV5DVAGHT;
begin
alt_dspbuilder_barrelshifter_GNV5DVAGHT_0: if ((DISTANCE_WIDTH = 4) and (NDIRECTION = 1) and (SIGNED = 0) and (USE_DEDICATED_CIRCUITRY = "false") and (PIPELINE = 0) and (WIDTH = 18)) generate
inst_alt_dspbuilder_barrelshifter_GNV5DVAGHT_0: alt_dspbuilder_barrelshifter_GNV5DVAGHT
generic map(DISTANCE_WIDTH => 4, NDIRECTION => 1, SIGNED => 0, USE_DEDICATED_CIRCUITRY => "false", PIPELINE => 0, WIDTH => 18)
port map(a => a, aclr => aclr, clock => clock, distance => distance, ena => ena, r => r, user_aclr => user_aclr);
end generate;
assert not (((DISTANCE_WIDTH = 4) and (NDIRECTION = 1) and (SIGNED = 0) and (USE_DEDICATED_CIRCUITRY = "false") and (PIPELINE = 0) and (WIDTH = 18)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_barrelshifter is
generic (
DISTANCE_WIDTH : natural := 3;
NDIRECTION : natural := 0;
SIGNED : integer := 1;
USE_DEDICATED_CIRCUITRY : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
user_aclr : in std_logic;
distance : in std_logic_vector(DISTANCE_WIDTH-1 downto 0);
r : out std_logic_vector(WIDTH-1 downto 0);
clock : in std_logic;
direction : in std_logic;
a : in std_logic_vector(WIDTH-1 downto 0);
aclr : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_barrelshifter;
architecture rtl of alt_dspbuilder_barrelshifter is
component alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic (
DISTANCE_WIDTH : natural := 4;
NDIRECTION : natural := 1;
SIGNED : integer := 0;
USE_DEDICATED_CIRCUITRY : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 18
);
port (
a : in std_logic_vector(18-1 downto 0);
aclr : in std_logic;
clock : in std_logic;
distance : in std_logic_vector(4-1 downto 0);
ena : in std_logic;
r : out std_logic_vector(18-1 downto 0);
user_aclr : in std_logic
);
end component alt_dspbuilder_barrelshifter_GNV5DVAGHT;
begin
alt_dspbuilder_barrelshifter_GNV5DVAGHT_0: if ((DISTANCE_WIDTH = 4) and (NDIRECTION = 1) and (SIGNED = 0) and (USE_DEDICATED_CIRCUITRY = "false") and (PIPELINE = 0) and (WIDTH = 18)) generate
inst_alt_dspbuilder_barrelshifter_GNV5DVAGHT_0: alt_dspbuilder_barrelshifter_GNV5DVAGHT
generic map(DISTANCE_WIDTH => 4, NDIRECTION => 1, SIGNED => 0, USE_DEDICATED_CIRCUITRY => "false", PIPELINE => 0, WIDTH => 18)
port map(a => a, aclr => aclr, clock => clock, distance => distance, ena => ena, r => r, user_aclr => user_aclr);
end generate;
assert not (((DISTANCE_WIDTH = 4) and (NDIRECTION = 1) and (SIGNED = 0) and (USE_DEDICATED_CIRCUITRY = "false") and (PIPELINE = 0) and (WIDTH = 18)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_barrelshifter is
generic (
DISTANCE_WIDTH : natural := 3;
NDIRECTION : natural := 0;
SIGNED : integer := 1;
USE_DEDICATED_CIRCUITRY : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
user_aclr : in std_logic;
distance : in std_logic_vector(DISTANCE_WIDTH-1 downto 0);
r : out std_logic_vector(WIDTH-1 downto 0);
clock : in std_logic;
direction : in std_logic;
a : in std_logic_vector(WIDTH-1 downto 0);
aclr : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_barrelshifter;
architecture rtl of alt_dspbuilder_barrelshifter is
component alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic (
DISTANCE_WIDTH : natural := 4;
NDIRECTION : natural := 1;
SIGNED : integer := 0;
USE_DEDICATED_CIRCUITRY : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 18
);
port (
a : in std_logic_vector(18-1 downto 0);
aclr : in std_logic;
clock : in std_logic;
distance : in std_logic_vector(4-1 downto 0);
ena : in std_logic;
r : out std_logic_vector(18-1 downto 0);
user_aclr : in std_logic
);
end component alt_dspbuilder_barrelshifter_GNV5DVAGHT;
begin
alt_dspbuilder_barrelshifter_GNV5DVAGHT_0: if ((DISTANCE_WIDTH = 4) and (NDIRECTION = 1) and (SIGNED = 0) and (USE_DEDICATED_CIRCUITRY = "false") and (PIPELINE = 0) and (WIDTH = 18)) generate
inst_alt_dspbuilder_barrelshifter_GNV5DVAGHT_0: alt_dspbuilder_barrelshifter_GNV5DVAGHT
generic map(DISTANCE_WIDTH => 4, NDIRECTION => 1, SIGNED => 0, USE_DEDICATED_CIRCUITRY => "false", PIPELINE => 0, WIDTH => 18)
port map(a => a, aclr => aclr, clock => clock, distance => distance, ena => ena, r => r, user_aclr => user_aclr);
end generate;
assert not (((DISTANCE_WIDTH = 4) and (NDIRECTION = 1) and (SIGNED = 0) and (USE_DEDICATED_CIRCUITRY = "false") and (PIPELINE = 0) and (WIDTH = 18)))
report "Please run generate again" severity error;
end architecture rtl;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11680)
`protect data_block
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`protect end_protected
|
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