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------------------------------------------------------------------------------- -- axi_datamover_s2mm_realign.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_s2mm_realign.vhd -- -- Description: -- This file implements the S2MM Data Realignment module. THe S2MM direction is -- more complex than the MM2S direction since the DRE needs to be upstream from -- the Write Data Controller. This requires the S2MM DRE to be running 2 to -- 3 clocks ahead of the Write Data controller to minimize/eliminate xfer -- bubble insertion. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1_10; use axi_datamover_v5_1_10.axi_datamover_fifo; use axi_datamover_v5_1_10.axi_datamover_s2mm_dre; use axi_datamover_v5_1_10.axi_datamover_s2mm_scatter; ------------------------------------------------------------------------------- entity axi_datamover_s2mm_realign is generic ( C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0; -- Specifies if the IBTT Indeterminate BTT Module is enabled -- for use (outside of this module) C_INCLUDE_DRE : Integer range 0 to 1 := 1; -- Includes/Omits the S2MM DRE -- 0 = Omit -- 1 = Include C_DRE_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 1; -- Specifies the depth of the internal command queue fifo C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2; -- Sets the width of the DRE alignment control ports C_SUPPORT_SCATTER : Integer range 0 to 1 := 1; -- Includes/Omits the Scatter functionality -- 0 = omit -- 1 = include C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1; C_BTT_USED : Integer range 8 to 23 := 16; -- Indicates the width of the input command BTT that is actually -- used C_STREAM_DWIDTH : Integer range 8 to 1024 := 32; -- Sets the width of the Input and Output Stream Data ports C_TAG_WIDTH : Integer range 1 to 8 := 4; -- Sets the width of the input command Tag port C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1 ; -- Sets the width of the Store and Forward Start offset ports C_FAMILY : String := "virtex7" -- specifies the target FPGA familiy ); port ( -- Clock and Reset Inputs ------------------------------------------- -- primary_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- mmap_reset : in std_logic; -- -- Reset used for the internal master logic -- --------------------------------------------------------------------- -- Write Data Controller or IBTT Indeterminate BTT I/O ------------------------- -- wdc2dre_wready : In std_logic; -- -- Write READY input from WDC or SF -- -- dre2wdc_wvalid : Out std_logic; -- -- Write VALID output to WDC or SF -- -- dre2wdc_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); -- -- Write DATA output to WDC or SF -- -- dre2wdc_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); -- -- Write DATA output to WDC or SF -- -- dre2wdc_wlast : Out std_logic; -- -- Write LAST output to WDC or SF -- -- dre2wdc_eop : Out std_logic; -- -- End of Packet indicator for the Stream input to WDC or SF -- -------------------------------------------------------------------------------- -- Starting offset output for the Store and Forward Modules ------------------- -- dre2sf_strt_offset : Out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);-- -- Outputs the starting offset of a transfer. This is used with Store -- -- and Forward Packer/Unpacker logic -- -------------------------------------------------------------------------------- -- AXI Slave Stream In ---------------------------------------------------------- -- s2mm_strm_wready : Out Std_logic; -- -- AXI Stream READY input -- -- s2mm_strm_wvalid : In std_logic; -- -- AXI Stream VALID Output -- -- s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); -- -- AXI Stream data output -- -- s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); -- -- AXI Stream STRB output -- -- s2mm_strm_wlast : In std_logic; -- -- AXI Stream LAST output -- -------------------------------------------------------------------------------- -- Command Calculator Interface --------------------------------------------------- -- dre2mstr_cmd_ready : Out std_logic ; -- -- Indication from the DRE that the command is being -- -- accepted from the Command Calculator -- -- mstr2dre_cmd_valid : In std_logic; -- -- The next command valid indication to the DRE -- -- from the Command Calculator -- -- mstr2dre_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2dre_dre_src_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); -- -- The source (input) alignment for the DRE -- -- mstr2dre_dre_dest_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); -- -- The destinstion (output) alignment for the DRE -- -- mstr2dre_btt : In std_logic_vector(C_BTT_USED-1 downto 0); -- -- The bytes to transfer value for the input command -- -- mstr2dre_drr : In std_logic; -- -- The starting tranfer of a sequence of transfers -- -- mstr2dre_eof : In std_logic; -- -- The endiing tranfer of a sequence of transfers -- -- mstr2dre_cmd_cmplt : In std_logic; -- -- The last tranfer command of a sequence of transfers -- -- spawned from a single parent command -- -- mstr2dre_calc_error : In std_logic; -- -- Indication if the next command in the calculation pipe -- -- has a calculation error -- -- mstr2dre_strt_offset : In std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);-- -- Outputs the starting offset of a transfer. This is used with Store -- -- and Forward Packer/Unpacker logic -- ----------------------------------------------------------------------------------- -- Premature TLAST assertion error flag ----------------------------- -- dre2all_tlast_error : Out std_logic; -- -- When asserted, this indicates the DRE detected -- -- a Early/Late TLAST assertion on the incoming data stream. -- --------------------------------------------------------------------- -- DRE Halted Status ------------------------------------------------ -- dre2all_halted : Out std_logic -- -- When asserted, this indicates the DRE has satisfied -- -- all pending transfers queued by the command calculator -- -- and is halted. -- --------------------------------------------------------------------- ); end entity axi_datamover_s2mm_realign; architecture implementation of axi_datamover_s2mm_realign is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Declarations -------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_size_realign_fifo -- -- Function Description: -- Assures that the Realigner cmd fifo depth is at least 4 deep else it -- is equal to the pipe depth. -- ------------------------------------------------------------------- function funct_size_realign_fifo (pipe_depth : integer) return integer is Variable temp_fifo_depth : Integer := 4; begin If (pipe_depth < 4) Then temp_fifo_depth := 4; Else temp_fifo_depth := pipe_depth; End if; Return (temp_fifo_depth); end function funct_size_realign_fifo; -- Constant Declarations -------------------------------------------- Constant BYTE_WIDTH : integer := 8; -- bits Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH; Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES; Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1; Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1; Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0'); Constant USE_SYNC_FIFO : integer := 0; Constant REG_FIFO_PRIM : integer := 0; Constant BRAM_FIFO_PRIM : integer := 1; Constant SRL_FIFO_PRIM : integer := 2; Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM; Constant TAG_WIDTH : integer := C_TAG_WIDTH; Constant SRC_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH; Constant DEST_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH; Constant BTT_WIDTH : integer := C_BTT_USED; Constant DRR_WIDTH : integer := 1; Constant EOF_WIDTH : integer := 1; Constant SEQUENTIAL_WIDTH : integer := 1; Constant CALC_ERR_WIDTH : integer := 1; Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH; Constant BTT_OF_ZERO : std_logic_vector(BTT_WIDTH-1 downto 0) := (others => '0'); Constant DRECTL_FIFO_DEPTH : integer := funct_size_realign_fifo(C_DRE_CNTL_FIFO_DEPTH); Constant DRECTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field SRC_ALIGN_WIDTH + -- Source align field width DEST_ALIGN_WIDTH + -- Dest align field width BTT_WIDTH + -- BTT field width DRR_WIDTH + -- DRE Re-alignment Request Flag Field EOF_WIDTH + -- EOF flag field SEQUENTIAL_WIDTH + -- Sequential command flag CALC_ERR_WIDTH + -- Calc error flag SF_OFFSET_WIDTH; -- Store and Forward Offset Constant TAG_STRT_INDEX : integer := 0; Constant SRC_ALIGN_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH; Constant DEST_ALIGN_STRT_INDEX : integer := SRC_ALIGN_STRT_INDEX + SRC_ALIGN_WIDTH; Constant BTT_STRT_INDEX : integer := DEST_ALIGN_STRT_INDEX + DEST_ALIGN_WIDTH; Constant DRR_STRT_INDEX : integer := BTT_STRT_INDEX + BTT_WIDTH; Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH; Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH; Constant CALC_ERR_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH; Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH; Constant INCLUDE_DRE : boolean := (C_INCLUDE_DRE = 1 and C_STREAM_DWIDTH <= 64 and C_STREAM_DWIDTH >= 16); Constant OMIT_DRE : boolean := not(INCLUDE_DRE); -- Type Declarations -------------------------------------------- type TYPE_CMD_CNTL_SM is ( INIT, LD_DRE_SCATTER_FIRST, CHK_POP_FIRST , LD_DRE_SCATTER_SECOND, CHK_POP_SECOND, ERROR_TRAP ); -- Signal Declarations -------------------------------------------- Signal sig_cmdcntl_sm_state : TYPE_CMD_CNTL_SM := INIT; Signal sig_cmdcntl_sm_state_ns : TYPE_CMD_CNTL_SM := INIT; signal sig_sm_ld_dre_cmd_ns : std_logic := '0'; signal sig_sm_ld_dre_cmd : std_logic := '0'; signal sig_sm_ld_scatter_cmd_ns : std_logic := '0'; signal sig_sm_ld_scatter_cmd : std_logic := '0'; signal sig_sm_pop_cmd_fifo_ns : std_logic := '0'; signal sig_sm_pop_cmd_fifo : std_logic := '0'; signal sig_cmd_fifo_data_in : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_fifo_data_out : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_fifo_wr_cmd_valid : std_logic := '0'; signal sig_fifo_wr_cmd_ready : std_logic := '0'; signal sig_curr_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_curr_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_curr_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_curr_btt_reg : std_logic_vector(BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_curr_drr_reg : std_logic := '0'; signal sig_curr_eof_reg : std_logic := '0'; signal sig_curr_cmd_cmplt_reg : std_logic := '0'; signal sig_curr_calc_error_reg : std_logic := '0'; signal sig_dre_align_ready : std_logic := '0'; signal sig_dre_use_autodest : std_logic := '0'; signal sig_dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_dre_dest_align : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_dre_flush : std_logic := '0'; signal sig_dre2wdc_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0'); signal sig_dre2wdc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0'); signal sig_dre2wdc_tlast : std_logic := '0'; signal sig_dre2wdc_tvalid : std_logic := '0'; signal sig_wdc2dre_tready : std_logic := '0'; signal sig_tlast_err0r : std_logic := '0'; signal sig_dre_halted : std_logic := '0'; signal sig_strm2scatter_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0'); signal sig_strm2scatter_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0'); signal sig_strm2scatter_tlast : std_logic := '0'; signal sig_strm2scatter_tvalid : std_logic := '0'; signal sig_scatter2strm_tready : std_logic := '0'; signal sig_scatter2dre_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0'); signal sig_scatter2dre_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0'); signal sig_scatter2dre_tlast : std_logic := '0'; signal sig_scatter2dre_tvalid : std_logic := '0'; signal sig_dre2scatter_tready : std_logic := '0'; signal sig_scatter2dre_flush : std_logic := '0'; signal sig_scatter2drc_eop : std_logic := '0'; signal sig_scatter2dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_scatter2drc_cmd_ready : std_logic := '0'; signal sig_drc2scatter_push_cmd : std_logic; signal sig_drc2scatter_btt : std_logic_vector(BTT_WIDTH-1 downto 0); signal sig_drc2scatter_eof : std_logic; signal sig_scatter2all_tlast_error : std_logic := '0'; signal sig_need_cmd_flush : std_logic := '0'; signal sig_fifo_rd_cmd_valid : std_logic := '0'; signal sig_curr_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_ld_strt_offset : std_logic := '0'; signal sig_output_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_dre2sf_strt_offset : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0'); begin --(architecture implementation) ------------------------------------------------------------- -- Port connections -- Input Stream Attachment s2mm_strm_wready <= sig_scatter2strm_tready ; sig_strm2scatter_tvalid <= s2mm_strm_wvalid ; sig_strm2scatter_tdata <= s2mm_strm_wdata ; sig_strm2scatter_tstrb <= s2mm_strm_wstrb ; sig_strm2scatter_tlast <= s2mm_strm_wlast ; -- Write Data Controller Stream Attachment sig_wdc2dre_tready <= wdc2dre_wready ; dre2wdc_wvalid <= sig_dre2wdc_tvalid ; dre2wdc_wdata <= sig_dre2wdc_tdata ; dre2wdc_wstrb <= sig_dre2wdc_tstrb ; dre2wdc_wlast <= sig_dre2wdc_tlast ; -- Status/Error flags dre2all_tlast_error <= sig_tlast_err0r ; dre2all_halted <= sig_dre_halted ; -- Store and Forward Starting Offset Output dre2sf_strt_offset <= sig_dre2sf_strt_offset ; ------------------------------------------------------------- -- Internal logic sig_dre_halted <= sig_dre_align_ready; ------------------------------------------------------------- -- DRE Handshake signals sig_dre_src_align <= sig_curr_src_align_reg ; sig_dre_dest_align <= sig_curr_dest_align_reg; sig_dre_use_autodest <= '0'; -- not used sig_dre_flush <= '0'; -- not used ------------------------------------------------------------------------- -------- Realigner Command FIFO and controls ------------------------------------------------------------------------- -- Command Calculator Handshake sig_fifo_wr_cmd_valid <= mstr2dre_cmd_valid ; dre2mstr_cmd_ready <= sig_fifo_wr_cmd_ready; -- Format the input fifo data word sig_cmd_fifo_data_in <= mstr2dre_strt_offset & mstr2dre_calc_error & mstr2dre_cmd_cmplt & mstr2dre_eof & mstr2dre_drr & mstr2dre_btt & mstr2dre_dre_dest_align & mstr2dre_dre_src_align & mstr2dre_tag ; -- Rip the output fifo data word sig_curr_tag_reg <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX); sig_curr_src_align_reg <= sig_cmd_fifo_data_out((SRC_ALIGN_STRT_INDEX+SRC_ALIGN_WIDTH)-1 downto SRC_ALIGN_STRT_INDEX); sig_curr_dest_align_reg <= sig_cmd_fifo_data_out((DEST_ALIGN_STRT_INDEX+DEST_ALIGN_WIDTH)-1 downto DEST_ALIGN_STRT_INDEX); sig_curr_btt_reg <= sig_cmd_fifo_data_out((BTT_STRT_INDEX+BTT_WIDTH)-1 downto BTT_STRT_INDEX); sig_curr_drr_reg <= sig_cmd_fifo_data_out(DRR_STRT_INDEX); sig_curr_eof_reg <= sig_cmd_fifo_data_out(EOF_STRT_INDEX); sig_curr_cmd_cmplt_reg <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX); sig_curr_calc_error_reg <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX); sig_curr_strt_offset_reg <= sig_cmd_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto SF_OFFSET_STRT_INDEX); ------------------------------------------------------------ -- Instance: I_DRE_CNTL_FIFO -- -- Description: -- Instance for the DRE Control FIFO -- ------------------------------------------------------------ I_DRE_CNTL_FIFO : entity axi_datamover_v5_1_10.axi_datamover_fifo generic map ( C_DWIDTH => DRECTL_FIFO_WIDTH , C_DEPTH => DRECTL_FIFO_DEPTH , C_IS_ASYNC => USE_SYNC_FIFO , C_PRIM_TYPE => FIFO_PRIM_TYPE , C_FAMILY => C_FAMILY ) port map ( -- Write Clock and reset fifo_wr_reset => mmap_reset , fifo_wr_clk => primary_aclk , -- Write Side fifo_wr_tvalid => sig_fifo_wr_cmd_valid , fifo_wr_tready => sig_fifo_wr_cmd_ready , fifo_wr_tdata => sig_cmd_fifo_data_in , fifo_wr_full => open , -- Read Clock and reset fifo_async_rd_reset => mmap_reset , fifo_async_rd_clk => primary_aclk , -- Read Side fifo_rd_tvalid => sig_fifo_rd_cmd_valid , fifo_rd_tready => sig_sm_pop_cmd_fifo , fifo_rd_tdata => sig_cmd_fifo_data_out , fifo_rd_empty => open ); ------------------------------------------------------------------------- -------- DRE and Scatter Command Loader State Machine ------------------------------------------------------------------------- ------------------------------------------------------------- -- Combinational Process -- -- Label: CMDCNTL_SM_COMBINATIONAL -- -- Process Description: -- Command Controller State Machine combinational implementation -- The design is based on the premise that for every parent -- command loaded into the S2MM, the Realigner can be loaded with -- 1 or 2 commands spawned from it. The first command is used to -- align ensuing transfers (in MMap space) to a max burst address -- boundary. Then, if the parent command's BTT value is not satisfied -- after the first command completes, a second command is generated -- and loaded in the Realigner for the remaining BTT value. The -- command complete bit in the Realigner command indicates if the -- first command the final command or the second command (if needed) -- is the final command, ------------------------------------------------------------- CMDCNTL_SM_COMBINATIONAL : process (sig_cmdcntl_sm_state , sig_fifo_rd_cmd_valid , sig_dre_align_ready , sig_scatter2drc_cmd_ready , sig_need_cmd_flush , sig_curr_cmd_cmplt_reg , sig_curr_calc_error_reg ) begin -- SM Defaults sig_cmdcntl_sm_state_ns <= INIT; sig_sm_ld_dre_cmd_ns <= '0'; sig_sm_ld_scatter_cmd_ns <= '0'; sig_sm_pop_cmd_fifo_ns <= '0'; case sig_cmdcntl_sm_state is -------------------------------------------- when INIT => sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST; -------------------------------------------- when LD_DRE_SCATTER_FIRST => If (sig_fifo_rd_cmd_valid = '1' and sig_curr_calc_error_reg = '1') Then sig_cmdcntl_sm_state_ns <= ERROR_TRAP; elsif (sig_fifo_rd_cmd_valid = '1' and sig_dre_align_ready = '1' and sig_scatter2drc_cmd_ready = '1') Then sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ; sig_sm_ld_dre_cmd_ns <= '1'; sig_sm_ld_scatter_cmd_ns <= '1'; sig_sm_pop_cmd_fifo_ns <= '1'; else sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST; End if; -------------------------------------------- when CHK_POP_FIRST => If (sig_curr_cmd_cmplt_reg = '1') Then sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST; Else sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND; End if; -------------------------------------------- when LD_DRE_SCATTER_SECOND => If (sig_fifo_rd_cmd_valid = '1' and sig_curr_calc_error_reg = '1') Then sig_cmdcntl_sm_state_ns <= ERROR_TRAP; elsif (sig_fifo_rd_cmd_valid = '1' and sig_need_cmd_flush = '1') Then sig_cmdcntl_sm_state_ns <= CHK_POP_SECOND ; sig_sm_pop_cmd_fifo_ns <= '1'; elsif (sig_fifo_rd_cmd_valid = '1' and sig_dre_align_ready = '1' and sig_scatter2drc_cmd_ready = '1') Then sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ; sig_sm_ld_dre_cmd_ns <= '1'; sig_sm_ld_scatter_cmd_ns <= '1'; sig_sm_pop_cmd_fifo_ns <= '1'; else sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND; End if; -------------------------------------------- when CHK_POP_SECOND => sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST ; -------------------------------------------- when ERROR_TRAP => sig_cmdcntl_sm_state_ns <= ERROR_TRAP ; -------------------------------------------- when others => sig_cmdcntl_sm_state_ns <= INIT; end case; end process CMDCNTL_SM_COMBINATIONAL; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: CMDCNTL_SM_REGISTERED -- -- Process Description: -- Command Controller State Machine registered implementation -- ------------------------------------------------------------- CMDCNTL_SM_REGISTERED : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_cmdcntl_sm_state <= INIT; sig_sm_ld_dre_cmd <= '0' ; sig_sm_ld_scatter_cmd <= '0' ; sig_sm_pop_cmd_fifo <= '0' ; else sig_cmdcntl_sm_state <= sig_cmdcntl_sm_state_ns ; sig_sm_ld_dre_cmd <= sig_sm_ld_dre_cmd_ns ; sig_sm_ld_scatter_cmd <= sig_sm_ld_scatter_cmd_ns ; sig_sm_pop_cmd_fifo <= sig_sm_pop_cmd_fifo_ns ; end if; end if; end process CMDCNTL_SM_REGISTERED; ------------------------------------------------------------------------- -------- DRE Instance and controls ------------------------------------------------------------------------- ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_DRE -- -- If Generate Description: -- Includes the instance for the DRE -- -- ------------------------------------------------------------ GEN_INCLUDE_DRE : if (INCLUDE_DRE) generate signal lsig_eop_reg : std_logic := '0'; signal lsig_dre_load_beat : std_logic := '0'; signal lsig_dre_tlast_output_beat : std_logic := '0'; signal lsig_set_eop : std_logic := '0'; signal lsig_tlast_err_reg1 : std_logic := '0'; signal lsig_tlast_err_reg2 : std_logic := '0'; signal lsig_push_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal lsig_pushreg_full : std_logic := '0'; signal lsig_pushreg_empty : std_logic := '0'; signal lsig_pull_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal lsig_pullreg_full : std_logic := '0'; signal lsig_pullreg_empty : std_logic := '0'; signal lsig_pull_new_offset : std_logic := '0'; signal lsig_push_new_offset : std_logic := '0'; begin ------------------------------------------------------------ -- Instance: I_S2MM_DRE_BLOCK -- -- Description: -- Instance for the S2MM Data Realignment Engine (DRE) -- ------------------------------------------------------------ I_S2MM_DRE_BLOCK : entity axi_datamover_v5_1_10.axi_datamover_s2mm_dre generic map ( C_DWIDTH => C_STREAM_DWIDTH , C_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH ) port map ( -- Clock and Reset dre_clk => primary_aclk , dre_rst => mmap_reset , -- Alignment Control (Independent from Stream Input timing) dre_align_ready => sig_dre_align_ready , dre_align_valid => sig_sm_ld_dre_cmd , dre_use_autodest => sig_dre_use_autodest , dre_src_align => sig_scatter2dre_src_align , dre_dest_align => sig_dre_dest_align , -- Flush Control (Aligned to input Stream timing) dre_flush => sig_scatter2dre_flush , -- Stream Inputs dre_in_tstrb => sig_scatter2dre_tstrb , dre_in_tdata => sig_scatter2dre_tdata , dre_in_tlast => sig_scatter2dre_tlast , dre_in_tvalid => sig_scatter2dre_tvalid , dre_in_tready => sig_dre2scatter_tready , -- Stream Outputs dre_out_tstrb => sig_dre2wdc_tstrb , dre_out_tdata => sig_dre2wdc_tdata , dre_out_tlast => sig_dre2wdc_tlast , dre_out_tvalid => sig_dre2wdc_tvalid , dre_out_tready => sig_wdc2dre_tready ); lsig_dre_load_beat <= sig_scatter2dre_tvalid and sig_dre2scatter_tready; lsig_set_eop <= sig_scatter2drc_eop and lsig_dre_load_beat ; lsig_dre_tlast_output_beat <= sig_dre2wdc_tvalid and sig_wdc2dre_tready and sig_dre2wdc_tlast; dre2wdc_eop <= lsig_dre_tlast_output_beat and lsig_eop_reg; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_EOP_REG -- -- Process Description: -- Implements a flop for holding the EOP from the Scatter -- Engine until the corresponding packet clears out of the DRE. -- THis is used to transfer the EOP marker to the DRE output -- stream without the need for the DRE to pass it through. -- ------------------------------------------------------------- IMP_EOP_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or (lsig_dre_tlast_output_beat = '1' and lsig_set_eop = '0')) then lsig_eop_reg <= '0'; elsif (lsig_set_eop = '1') then lsig_eop_reg <= '1'; else null; -- Hold current state end if; end if; end process IMP_EOP_REG; -- Delay TLAST Error by 2 clocks to compensate for DRE minimum -- delay of 2 clocks for the stream data. sig_tlast_err0r <= lsig_tlast_err_reg2; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_TLAST_ERR_DELAY -- -- Process Description: -- Implements a 2 clock delay to better align the TLAST -- error detection with the Stream output data to the WDC -- which has a minimum 2 clock delay through the DRE. -- ------------------------------------------------------------- IMP_TLAST_ERR_DELAY : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then lsig_tlast_err_reg1 <= '0'; lsig_tlast_err_reg2 <= '0'; else lsig_tlast_err_reg1 <= sig_scatter2all_tlast_error; lsig_tlast_err_reg2 <= lsig_tlast_err_reg1; end if; end if; end process IMP_TLAST_ERR_DELAY; ------------------------------------------------------------------------- -- Store and Forward Start Address Offset Registers Logic -- Push-pull register is used to to time align the starting address -- offset (ripped from the Realigner command via parsing) to DRE -- TLAST output timing. The offset output of the pull register must -- be valid on the first output databeat of the DRE to the Store and -- Forward module. ------------------------------------------------------------------------- sig_dre2sf_strt_offset <= lsig_pull_strt_offset_reg; -- lsig_push_new_offset <= sig_dre_align_ready and -- sig_gated_dre_align_valid ; lsig_push_new_offset <= sig_sm_ld_dre_cmd ; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_PUSH_STRT_OFFSET_REG -- -- Process Description: -- Implements the input register for holding the starting address -- offset sent to the external Store and Forward functions. -- ------------------------------------------------------------- IMP_PUSH_STRT_OFFSET_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then lsig_push_strt_offset_reg <= (others => '0'); lsig_pushreg_full <= '0'; lsig_pushreg_empty <= '1'; elsif (lsig_push_new_offset = '1') then lsig_push_strt_offset_reg <= sig_curr_strt_offset_reg; lsig_pushreg_full <= '1'; lsig_pushreg_empty <= '0'; elsif (lsig_pull_new_offset = '1') then lsig_push_strt_offset_reg <= (others => '0'); lsig_pushreg_full <= '0'; lsig_pushreg_empty <= '1'; else null; -- Hold Current State end if; end if; end process IMP_PUSH_STRT_OFFSET_REG; -- Pull the next offset (if one exists) into the pull register -- when the DRE outputs a TLAST. If the pull register is empty -- and the push register has an offset, then push the new value -- into the pull register. lsig_pull_new_offset <= (sig_dre2wdc_tlast and sig_dre2wdc_tvalid and sig_wdc2dre_tready) or (lsig_pushreg_full and lsig_pullreg_empty); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_PULL_STRT_OFFSET_REG -- -- Process Description: -- Implements the output register for holding the starting -- address offset sent to the Store and Forward modul's upsizer -- logic. -- ------------------------------------------------------------- IMP_PULL_STRT_OFFSET_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then lsig_pull_strt_offset_reg <= (others => '0'); lsig_pullreg_full <= '0'; lsig_pullreg_empty <= '1'; elsif (lsig_pull_new_offset = '1' and lsig_pushreg_full = '1') then lsig_pull_strt_offset_reg <= lsig_push_strt_offset_reg; lsig_pullreg_full <= '1'; lsig_pullreg_empty <= '0'; elsif (lsig_pull_new_offset = '1' and lsig_pushreg_full = '0') then lsig_pull_strt_offset_reg <= (others => '0'); lsig_pullreg_full <= '0'; lsig_pullreg_empty <= '1'; else null; -- Hold Current State end if; end if; end process IMP_PULL_STRT_OFFSET_REG; end generate GEN_INCLUDE_DRE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_OMIT_DRE -- -- If Generate Description: -- Omits the DRE from the Re-aligner. -- -- ------------------------------------------------------------ GEN_OMIT_DRE : if (OMIT_DRE) generate begin -- DRE always ready sig_dre_align_ready <= '1'; -- -- Let the Scatter engine control the Realigner command -- -- flow. -- sig_dre_align_ready <= sig_scatter2drc_cmd_ready; -- Pass through signal connections sig_dre2wdc_tstrb <= sig_scatter2dre_tstrb ; sig_dre2wdc_tdata <= sig_scatter2dre_tdata ; sig_dre2wdc_tlast <= sig_scatter2dre_tlast ; sig_dre2wdc_tvalid <= sig_scatter2dre_tvalid ; sig_dre2scatter_tready <= sig_wdc2dre_tready ; dre2wdc_eop <= sig_scatter2drc_eop ; -- Just pass TLAST Error through when no DRE is present sig_tlast_err0r <= sig_scatter2all_tlast_error; ------------------------------------------------------------------------- -------- Store and Forward Start Address Offset Register Logic ------------------------------------------------------------------------- sig_dre2sf_strt_offset <= sig_output_strt_offset_reg; sig_ld_strt_offset <= sig_sm_ld_dre_cmd; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_STRT_OFFSET_OUTPUT -- -- Process Description: -- Implements the register for holding the starting address -- offset sent to the S2MM Store and Forward module's upsizer -- logic. -- ------------------------------------------------------------- IMP_STRT_OFFSET_OUTPUT : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_output_strt_offset_reg <= (others => '0'); elsif (sig_ld_strt_offset = '1') then sig_output_strt_offset_reg <= sig_curr_strt_offset_reg; else null; -- Hold Current State end if; end if; end process IMP_STRT_OFFSET_OUTPUT; end generate GEN_OMIT_DRE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_SCATTER -- -- If Generate Description: -- This IfGen implements the Scatter function which is a pre- -- processor for the S2MM DRE. The scatter function breaks up -- a continous input stream of data into constituant parts -- as described by a set of loaded commands that together -- describe an entire input packet. -- ------------------------------------------------------------ GEN_INCLUDE_SCATTER : if (C_SUPPORT_SCATTER = 1) generate begin -- Load the Scatter Engine command when the DRE command -- is loaded -- sig_drc2scatter_push_cmd <= sig_dre_align_ready and -- sig_gated_dre_align_valid; sig_drc2scatter_push_cmd <= sig_sm_ld_scatter_cmd ; -- Assign the new Bytes to Transfer (BTT) qualifier for the -- Scatter Engine sig_drc2scatter_btt <= sig_curr_btt_reg; -- Assign the new End of Frame (EOF) qualifier for the -- Scatter Engine sig_drc2scatter_eof <= sig_curr_eof_reg; ------------------------------------------------------------ -- Instance: I_S2MM_SCATTER -- -- Description: -- Instance for the Scatter Engine. This block breaks up a -- input stream per commands loaded. -- ------------------------------------------------------------ I_S2MM_SCATTER : entity axi_datamover_v5_1_10.axi_datamover_s2mm_scatter generic map ( C_ENABLE_INDET_BTT => C_ENABLE_INDET_BTT , C_DRE_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH , C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP , C_BTT_USED => BTT_WIDTH , C_STREAM_DWIDTH => C_STREAM_DWIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock input & Reset input primary_aclk => primary_aclk , mmap_reset => mmap_reset , -- DRE Realign Controller I/O ---------------------------- scatter2drc_cmd_ready => sig_scatter2drc_cmd_ready , drc2scatter_push_cmd => sig_drc2scatter_push_cmd , drc2scatter_btt => sig_drc2scatter_btt , drc2scatter_eof => sig_drc2scatter_eof , -- DRE Source Alignment ----------------------------------- scatter2drc_src_align => sig_scatter2dre_src_align , -- AXI Slave Stream In ----------------------------------- s2mm_strm_tready => sig_scatter2strm_tready , s2mm_strm_tvalid => sig_strm2scatter_tvalid , s2mm_strm_tdata => sig_strm2scatter_tdata , s2mm_strm_tstrb => sig_strm2scatter_tstrb , s2mm_strm_tlast => sig_strm2scatter_tlast , -- Stream Out to S2MM DRE --------------------------------- drc2scatter_tready => sig_dre2scatter_tready , scatter2drc_tvalid => sig_scatter2dre_tvalid , scatter2drc_tdata => sig_scatter2dre_tdata , scatter2drc_tstrb => sig_scatter2dre_tstrb , scatter2drc_tlast => sig_scatter2dre_tlast , scatter2drc_flush => sig_scatter2dre_flush , scatter2drc_eop => sig_scatter2drc_eop , -- Premature TLAST assertion error flag scatter2drc_tlast_error => sig_scatter2all_tlast_error ); end generate GEN_INCLUDE_SCATTER; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_OMIT_SCATTER -- -- If Generate Description: -- This IfGen omits the Scatter pre-processor. -- -- ------------------------------------------------------------ GEN_OMIT_SCATTER : if (C_SUPPORT_SCATTER = 0) generate begin -- Just housekeep the signaling sig_scatter2drc_cmd_ready <= '1' ; sig_scatter2drc_eop <= sig_strm2scatter_tlast ; sig_scatter2dre_src_align <= sig_dre_src_align ; sig_scatter2all_tlast_error <= '0' ; sig_scatter2dre_flush <= sig_dre_flush ; sig_scatter2dre_tstrb <= sig_strm2scatter_tstrb ; sig_scatter2dre_tdata <= sig_strm2scatter_tdata ; sig_scatter2dre_tlast <= sig_strm2scatter_tlast ; sig_scatter2dre_tvalid <= sig_strm2scatter_tvalid ; sig_scatter2strm_tready <= sig_dre2scatter_tready ; end generate GEN_OMIT_SCATTER; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_OMIT_INDET_BTT -- -- If Generate Description: -- Omit and special logic for Indeterminate BTT support. -- -- ------------------------------------------------------------ GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate begin sig_need_cmd_flush <= '0' ; -- not needed without Indeterminate BTT end generate GEN_OMIT_INDET_BTT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ENABLE_INDET_BTT -- -- If Generate Description: -- Include logic for the case when Indeterminate BTT is -- included as part of the S2MM. In this mode, the actual -- length of input stream packets is not known when the S2MM -- is loaded with a transfer command. -- ------------------------------------------------------------ GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate signal lsig_clr_cmd_flush : std_logic := '0'; signal lsig_set_cmd_flush : std_logic := '0'; signal lsig_cmd_set_fetch_pause : std_logic := '0'; signal lsig_cmd_clr_fetch_pause : std_logic := '0'; signal lsig_cmd_fetch_pause : std_logic := '0'; begin lsig_cmd_set_fetch_pause <= sig_drc2scatter_push_cmd and not(sig_curr_cmd_cmplt_reg) and not(sig_need_cmd_flush); lsig_cmd_clr_fetch_pause <= sig_scatter2dre_tvalid and sig_dre2scatter_tready and sig_scatter2dre_tlast; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CMD_FETCH_PAUSE -- -- Process Description: -- Implements the flop for the flag that causes the command -- queue manager to pause fetching the next command if the -- current command does not have the command complete bit set. -- The pause remains set until the associated TLAST for the -- command is output from the Scatter Engine. If the Tlast is -- also accompanied by a EOP and the pause is set, then the -- ensuing command (which will have the cmd cmplt bit set) must -- be flushed from the queue and not loaded into the Scatter -- Engine or DRE, This is normally associated with indeterminate -- packets that are actually shorter than the intial align to -- max burst child command sent to the Realigner, The next loaded -- child command is to finish the remainder of the indeterminate -- packet up to the full BTT value in the original parent command. -- This child command becomes stranded in the Realigner command fifo -- and has to be flushed. -- ------------------------------------------------------------- IMP_CMD_FETCH_PAUSE : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or lsig_cmd_clr_fetch_pause = '1') then lsig_cmd_fetch_pause <= '0'; elsif (lsig_cmd_set_fetch_pause = '1') then lsig_cmd_fetch_pause <= '1'; else null; -- Hold current state end if; end if; end process IMP_CMD_FETCH_PAUSE; -- Clear the flush needed flag when the command with the command -- complete marker is popped off of the command queue. lsig_clr_cmd_flush <= sig_need_cmd_flush and sig_sm_pop_cmd_fifo; -- The command queue has to be flushed if the stream EOP marker -- is transfered out of the Scatter Engine when the corresponding -- command being executed does not have the command complete -- marker set. lsig_set_cmd_flush <= lsig_cmd_fetch_pause and sig_scatter2dre_tvalid and sig_dre2scatter_tready and sig_scatter2drc_eop; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CMD_FLUSH_FLOP -- -- Process Description: -- Implements the flop for holding the command flush flag. -- This is only needed in Indeterminate BTT mode. -- ------------------------------------------------------------- IMP_CMD_FLUSH_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or lsig_clr_cmd_flush = '1') then sig_need_cmd_flush <= '0'; elsif (lsig_set_cmd_flush = '1') then sig_need_cmd_flush <= '1'; else null; -- Hold current state end if; end if; end process IMP_CMD_FLUSH_FLOP; end generate GEN_ENABLE_INDET_BTT; end implementation;
------------------------------------------------------------------------------- -- axi_datamover_s2mm_realign.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_s2mm_realign.vhd -- -- Description: -- This file implements the S2MM Data Realignment module. THe S2MM direction is -- more complex than the MM2S direction since the DRE needs to be upstream from -- the Write Data Controller. This requires the S2MM DRE to be running 2 to -- 3 clocks ahead of the Write Data controller to minimize/eliminate xfer -- bubble insertion. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1_10; use axi_datamover_v5_1_10.axi_datamover_fifo; use axi_datamover_v5_1_10.axi_datamover_s2mm_dre; use axi_datamover_v5_1_10.axi_datamover_s2mm_scatter; ------------------------------------------------------------------------------- entity axi_datamover_s2mm_realign is generic ( C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0; -- Specifies if the IBTT Indeterminate BTT Module is enabled -- for use (outside of this module) C_INCLUDE_DRE : Integer range 0 to 1 := 1; -- Includes/Omits the S2MM DRE -- 0 = Omit -- 1 = Include C_DRE_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 1; -- Specifies the depth of the internal command queue fifo C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2; -- Sets the width of the DRE alignment control ports C_SUPPORT_SCATTER : Integer range 0 to 1 := 1; -- Includes/Omits the Scatter functionality -- 0 = omit -- 1 = include C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1; C_BTT_USED : Integer range 8 to 23 := 16; -- Indicates the width of the input command BTT that is actually -- used C_STREAM_DWIDTH : Integer range 8 to 1024 := 32; -- Sets the width of the Input and Output Stream Data ports C_TAG_WIDTH : Integer range 1 to 8 := 4; -- Sets the width of the input command Tag port C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1 ; -- Sets the width of the Store and Forward Start offset ports C_FAMILY : String := "virtex7" -- specifies the target FPGA familiy ); port ( -- Clock and Reset Inputs ------------------------------------------- -- primary_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- mmap_reset : in std_logic; -- -- Reset used for the internal master logic -- --------------------------------------------------------------------- -- Write Data Controller or IBTT Indeterminate BTT I/O ------------------------- -- wdc2dre_wready : In std_logic; -- -- Write READY input from WDC or SF -- -- dre2wdc_wvalid : Out std_logic; -- -- Write VALID output to WDC or SF -- -- dre2wdc_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); -- -- Write DATA output to WDC or SF -- -- dre2wdc_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); -- -- Write DATA output to WDC or SF -- -- dre2wdc_wlast : Out std_logic; -- -- Write LAST output to WDC or SF -- -- dre2wdc_eop : Out std_logic; -- -- End of Packet indicator for the Stream input to WDC or SF -- -------------------------------------------------------------------------------- -- Starting offset output for the Store and Forward Modules ------------------- -- dre2sf_strt_offset : Out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);-- -- Outputs the starting offset of a transfer. This is used with Store -- -- and Forward Packer/Unpacker logic -- -------------------------------------------------------------------------------- -- AXI Slave Stream In ---------------------------------------------------------- -- s2mm_strm_wready : Out Std_logic; -- -- AXI Stream READY input -- -- s2mm_strm_wvalid : In std_logic; -- -- AXI Stream VALID Output -- -- s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); -- -- AXI Stream data output -- -- s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); -- -- AXI Stream STRB output -- -- s2mm_strm_wlast : In std_logic; -- -- AXI Stream LAST output -- -------------------------------------------------------------------------------- -- Command Calculator Interface --------------------------------------------------- -- dre2mstr_cmd_ready : Out std_logic ; -- -- Indication from the DRE that the command is being -- -- accepted from the Command Calculator -- -- mstr2dre_cmd_valid : In std_logic; -- -- The next command valid indication to the DRE -- -- from the Command Calculator -- -- mstr2dre_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2dre_dre_src_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); -- -- The source (input) alignment for the DRE -- -- mstr2dre_dre_dest_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); -- -- The destinstion (output) alignment for the DRE -- -- mstr2dre_btt : In std_logic_vector(C_BTT_USED-1 downto 0); -- -- The bytes to transfer value for the input command -- -- mstr2dre_drr : In std_logic; -- -- The starting tranfer of a sequence of transfers -- -- mstr2dre_eof : In std_logic; -- -- The endiing tranfer of a sequence of transfers -- -- mstr2dre_cmd_cmplt : In std_logic; -- -- The last tranfer command of a sequence of transfers -- -- spawned from a single parent command -- -- mstr2dre_calc_error : In std_logic; -- -- Indication if the next command in the calculation pipe -- -- has a calculation error -- -- mstr2dre_strt_offset : In std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);-- -- Outputs the starting offset of a transfer. This is used with Store -- -- and Forward Packer/Unpacker logic -- ----------------------------------------------------------------------------------- -- Premature TLAST assertion error flag ----------------------------- -- dre2all_tlast_error : Out std_logic; -- -- When asserted, this indicates the DRE detected -- -- a Early/Late TLAST assertion on the incoming data stream. -- --------------------------------------------------------------------- -- DRE Halted Status ------------------------------------------------ -- dre2all_halted : Out std_logic -- -- When asserted, this indicates the DRE has satisfied -- -- all pending transfers queued by the command calculator -- -- and is halted. -- --------------------------------------------------------------------- ); end entity axi_datamover_s2mm_realign; architecture implementation of axi_datamover_s2mm_realign is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Declarations -------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_size_realign_fifo -- -- Function Description: -- Assures that the Realigner cmd fifo depth is at least 4 deep else it -- is equal to the pipe depth. -- ------------------------------------------------------------------- function funct_size_realign_fifo (pipe_depth : integer) return integer is Variable temp_fifo_depth : Integer := 4; begin If (pipe_depth < 4) Then temp_fifo_depth := 4; Else temp_fifo_depth := pipe_depth; End if; Return (temp_fifo_depth); end function funct_size_realign_fifo; -- Constant Declarations -------------------------------------------- Constant BYTE_WIDTH : integer := 8; -- bits Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH; Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES; Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1; Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1; Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0'); Constant USE_SYNC_FIFO : integer := 0; Constant REG_FIFO_PRIM : integer := 0; Constant BRAM_FIFO_PRIM : integer := 1; Constant SRL_FIFO_PRIM : integer := 2; Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM; Constant TAG_WIDTH : integer := C_TAG_WIDTH; Constant SRC_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH; Constant DEST_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH; Constant BTT_WIDTH : integer := C_BTT_USED; Constant DRR_WIDTH : integer := 1; Constant EOF_WIDTH : integer := 1; Constant SEQUENTIAL_WIDTH : integer := 1; Constant CALC_ERR_WIDTH : integer := 1; Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH; Constant BTT_OF_ZERO : std_logic_vector(BTT_WIDTH-1 downto 0) := (others => '0'); Constant DRECTL_FIFO_DEPTH : integer := funct_size_realign_fifo(C_DRE_CNTL_FIFO_DEPTH); Constant DRECTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field SRC_ALIGN_WIDTH + -- Source align field width DEST_ALIGN_WIDTH + -- Dest align field width BTT_WIDTH + -- BTT field width DRR_WIDTH + -- DRE Re-alignment Request Flag Field EOF_WIDTH + -- EOF flag field SEQUENTIAL_WIDTH + -- Sequential command flag CALC_ERR_WIDTH + -- Calc error flag SF_OFFSET_WIDTH; -- Store and Forward Offset Constant TAG_STRT_INDEX : integer := 0; Constant SRC_ALIGN_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH; Constant DEST_ALIGN_STRT_INDEX : integer := SRC_ALIGN_STRT_INDEX + SRC_ALIGN_WIDTH; Constant BTT_STRT_INDEX : integer := DEST_ALIGN_STRT_INDEX + DEST_ALIGN_WIDTH; Constant DRR_STRT_INDEX : integer := BTT_STRT_INDEX + BTT_WIDTH; Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH; Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH; Constant CALC_ERR_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH; Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH; Constant INCLUDE_DRE : boolean := (C_INCLUDE_DRE = 1 and C_STREAM_DWIDTH <= 64 and C_STREAM_DWIDTH >= 16); Constant OMIT_DRE : boolean := not(INCLUDE_DRE); -- Type Declarations -------------------------------------------- type TYPE_CMD_CNTL_SM is ( INIT, LD_DRE_SCATTER_FIRST, CHK_POP_FIRST , LD_DRE_SCATTER_SECOND, CHK_POP_SECOND, ERROR_TRAP ); -- Signal Declarations -------------------------------------------- Signal sig_cmdcntl_sm_state : TYPE_CMD_CNTL_SM := INIT; Signal sig_cmdcntl_sm_state_ns : TYPE_CMD_CNTL_SM := INIT; signal sig_sm_ld_dre_cmd_ns : std_logic := '0'; signal sig_sm_ld_dre_cmd : std_logic := '0'; signal sig_sm_ld_scatter_cmd_ns : std_logic := '0'; signal sig_sm_ld_scatter_cmd : std_logic := '0'; signal sig_sm_pop_cmd_fifo_ns : std_logic := '0'; signal sig_sm_pop_cmd_fifo : std_logic := '0'; signal sig_cmd_fifo_data_in : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_fifo_data_out : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_fifo_wr_cmd_valid : std_logic := '0'; signal sig_fifo_wr_cmd_ready : std_logic := '0'; signal sig_curr_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_curr_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_curr_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_curr_btt_reg : std_logic_vector(BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_curr_drr_reg : std_logic := '0'; signal sig_curr_eof_reg : std_logic := '0'; signal sig_curr_cmd_cmplt_reg : std_logic := '0'; signal sig_curr_calc_error_reg : std_logic := '0'; signal sig_dre_align_ready : std_logic := '0'; signal sig_dre_use_autodest : std_logic := '0'; signal sig_dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_dre_dest_align : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_dre_flush : std_logic := '0'; signal sig_dre2wdc_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0'); signal sig_dre2wdc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0'); signal sig_dre2wdc_tlast : std_logic := '0'; signal sig_dre2wdc_tvalid : std_logic := '0'; signal sig_wdc2dre_tready : std_logic := '0'; signal sig_tlast_err0r : std_logic := '0'; signal sig_dre_halted : std_logic := '0'; signal sig_strm2scatter_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0'); signal sig_strm2scatter_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0'); signal sig_strm2scatter_tlast : std_logic := '0'; signal sig_strm2scatter_tvalid : std_logic := '0'; signal sig_scatter2strm_tready : std_logic := '0'; signal sig_scatter2dre_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0'); signal sig_scatter2dre_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0'); signal sig_scatter2dre_tlast : std_logic := '0'; signal sig_scatter2dre_tvalid : std_logic := '0'; signal sig_dre2scatter_tready : std_logic := '0'; signal sig_scatter2dre_flush : std_logic := '0'; signal sig_scatter2drc_eop : std_logic := '0'; signal sig_scatter2dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_scatter2drc_cmd_ready : std_logic := '0'; signal sig_drc2scatter_push_cmd : std_logic; signal sig_drc2scatter_btt : std_logic_vector(BTT_WIDTH-1 downto 0); signal sig_drc2scatter_eof : std_logic; signal sig_scatter2all_tlast_error : std_logic := '0'; signal sig_need_cmd_flush : std_logic := '0'; signal sig_fifo_rd_cmd_valid : std_logic := '0'; signal sig_curr_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_ld_strt_offset : std_logic := '0'; signal sig_output_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_dre2sf_strt_offset : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0'); begin --(architecture implementation) ------------------------------------------------------------- -- Port connections -- Input Stream Attachment s2mm_strm_wready <= sig_scatter2strm_tready ; sig_strm2scatter_tvalid <= s2mm_strm_wvalid ; sig_strm2scatter_tdata <= s2mm_strm_wdata ; sig_strm2scatter_tstrb <= s2mm_strm_wstrb ; sig_strm2scatter_tlast <= s2mm_strm_wlast ; -- Write Data Controller Stream Attachment sig_wdc2dre_tready <= wdc2dre_wready ; dre2wdc_wvalid <= sig_dre2wdc_tvalid ; dre2wdc_wdata <= sig_dre2wdc_tdata ; dre2wdc_wstrb <= sig_dre2wdc_tstrb ; dre2wdc_wlast <= sig_dre2wdc_tlast ; -- Status/Error flags dre2all_tlast_error <= sig_tlast_err0r ; dre2all_halted <= sig_dre_halted ; -- Store and Forward Starting Offset Output dre2sf_strt_offset <= sig_dre2sf_strt_offset ; ------------------------------------------------------------- -- Internal logic sig_dre_halted <= sig_dre_align_ready; ------------------------------------------------------------- -- DRE Handshake signals sig_dre_src_align <= sig_curr_src_align_reg ; sig_dre_dest_align <= sig_curr_dest_align_reg; sig_dre_use_autodest <= '0'; -- not used sig_dre_flush <= '0'; -- not used ------------------------------------------------------------------------- -------- Realigner Command FIFO and controls ------------------------------------------------------------------------- -- Command Calculator Handshake sig_fifo_wr_cmd_valid <= mstr2dre_cmd_valid ; dre2mstr_cmd_ready <= sig_fifo_wr_cmd_ready; -- Format the input fifo data word sig_cmd_fifo_data_in <= mstr2dre_strt_offset & mstr2dre_calc_error & mstr2dre_cmd_cmplt & mstr2dre_eof & mstr2dre_drr & mstr2dre_btt & mstr2dre_dre_dest_align & mstr2dre_dre_src_align & mstr2dre_tag ; -- Rip the output fifo data word sig_curr_tag_reg <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX); sig_curr_src_align_reg <= sig_cmd_fifo_data_out((SRC_ALIGN_STRT_INDEX+SRC_ALIGN_WIDTH)-1 downto SRC_ALIGN_STRT_INDEX); sig_curr_dest_align_reg <= sig_cmd_fifo_data_out((DEST_ALIGN_STRT_INDEX+DEST_ALIGN_WIDTH)-1 downto DEST_ALIGN_STRT_INDEX); sig_curr_btt_reg <= sig_cmd_fifo_data_out((BTT_STRT_INDEX+BTT_WIDTH)-1 downto BTT_STRT_INDEX); sig_curr_drr_reg <= sig_cmd_fifo_data_out(DRR_STRT_INDEX); sig_curr_eof_reg <= sig_cmd_fifo_data_out(EOF_STRT_INDEX); sig_curr_cmd_cmplt_reg <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX); sig_curr_calc_error_reg <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX); sig_curr_strt_offset_reg <= sig_cmd_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto SF_OFFSET_STRT_INDEX); ------------------------------------------------------------ -- Instance: I_DRE_CNTL_FIFO -- -- Description: -- Instance for the DRE Control FIFO -- ------------------------------------------------------------ I_DRE_CNTL_FIFO : entity axi_datamover_v5_1_10.axi_datamover_fifo generic map ( C_DWIDTH => DRECTL_FIFO_WIDTH , C_DEPTH => DRECTL_FIFO_DEPTH , C_IS_ASYNC => USE_SYNC_FIFO , C_PRIM_TYPE => FIFO_PRIM_TYPE , C_FAMILY => C_FAMILY ) port map ( -- Write Clock and reset fifo_wr_reset => mmap_reset , fifo_wr_clk => primary_aclk , -- Write Side fifo_wr_tvalid => sig_fifo_wr_cmd_valid , fifo_wr_tready => sig_fifo_wr_cmd_ready , fifo_wr_tdata => sig_cmd_fifo_data_in , fifo_wr_full => open , -- Read Clock and reset fifo_async_rd_reset => mmap_reset , fifo_async_rd_clk => primary_aclk , -- Read Side fifo_rd_tvalid => sig_fifo_rd_cmd_valid , fifo_rd_tready => sig_sm_pop_cmd_fifo , fifo_rd_tdata => sig_cmd_fifo_data_out , fifo_rd_empty => open ); ------------------------------------------------------------------------- -------- DRE and Scatter Command Loader State Machine ------------------------------------------------------------------------- ------------------------------------------------------------- -- Combinational Process -- -- Label: CMDCNTL_SM_COMBINATIONAL -- -- Process Description: -- Command Controller State Machine combinational implementation -- The design is based on the premise that for every parent -- command loaded into the S2MM, the Realigner can be loaded with -- 1 or 2 commands spawned from it. The first command is used to -- align ensuing transfers (in MMap space) to a max burst address -- boundary. Then, if the parent command's BTT value is not satisfied -- after the first command completes, a second command is generated -- and loaded in the Realigner for the remaining BTT value. The -- command complete bit in the Realigner command indicates if the -- first command the final command or the second command (if needed) -- is the final command, ------------------------------------------------------------- CMDCNTL_SM_COMBINATIONAL : process (sig_cmdcntl_sm_state , sig_fifo_rd_cmd_valid , sig_dre_align_ready , sig_scatter2drc_cmd_ready , sig_need_cmd_flush , sig_curr_cmd_cmplt_reg , sig_curr_calc_error_reg ) begin -- SM Defaults sig_cmdcntl_sm_state_ns <= INIT; sig_sm_ld_dre_cmd_ns <= '0'; sig_sm_ld_scatter_cmd_ns <= '0'; sig_sm_pop_cmd_fifo_ns <= '0'; case sig_cmdcntl_sm_state is -------------------------------------------- when INIT => sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST; -------------------------------------------- when LD_DRE_SCATTER_FIRST => If (sig_fifo_rd_cmd_valid = '1' and sig_curr_calc_error_reg = '1') Then sig_cmdcntl_sm_state_ns <= ERROR_TRAP; elsif (sig_fifo_rd_cmd_valid = '1' and sig_dre_align_ready = '1' and sig_scatter2drc_cmd_ready = '1') Then sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ; sig_sm_ld_dre_cmd_ns <= '1'; sig_sm_ld_scatter_cmd_ns <= '1'; sig_sm_pop_cmd_fifo_ns <= '1'; else sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST; End if; -------------------------------------------- when CHK_POP_FIRST => If (sig_curr_cmd_cmplt_reg = '1') Then sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST; Else sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND; End if; -------------------------------------------- when LD_DRE_SCATTER_SECOND => If (sig_fifo_rd_cmd_valid = '1' and sig_curr_calc_error_reg = '1') Then sig_cmdcntl_sm_state_ns <= ERROR_TRAP; elsif (sig_fifo_rd_cmd_valid = '1' and sig_need_cmd_flush = '1') Then sig_cmdcntl_sm_state_ns <= CHK_POP_SECOND ; sig_sm_pop_cmd_fifo_ns <= '1'; elsif (sig_fifo_rd_cmd_valid = '1' and sig_dre_align_ready = '1' and sig_scatter2drc_cmd_ready = '1') Then sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ; sig_sm_ld_dre_cmd_ns <= '1'; sig_sm_ld_scatter_cmd_ns <= '1'; sig_sm_pop_cmd_fifo_ns <= '1'; else sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND; End if; -------------------------------------------- when CHK_POP_SECOND => sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST ; -------------------------------------------- when ERROR_TRAP => sig_cmdcntl_sm_state_ns <= ERROR_TRAP ; -------------------------------------------- when others => sig_cmdcntl_sm_state_ns <= INIT; end case; end process CMDCNTL_SM_COMBINATIONAL; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: CMDCNTL_SM_REGISTERED -- -- Process Description: -- Command Controller State Machine registered implementation -- ------------------------------------------------------------- CMDCNTL_SM_REGISTERED : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_cmdcntl_sm_state <= INIT; sig_sm_ld_dre_cmd <= '0' ; sig_sm_ld_scatter_cmd <= '0' ; sig_sm_pop_cmd_fifo <= '0' ; else sig_cmdcntl_sm_state <= sig_cmdcntl_sm_state_ns ; sig_sm_ld_dre_cmd <= sig_sm_ld_dre_cmd_ns ; sig_sm_ld_scatter_cmd <= sig_sm_ld_scatter_cmd_ns ; sig_sm_pop_cmd_fifo <= sig_sm_pop_cmd_fifo_ns ; end if; end if; end process CMDCNTL_SM_REGISTERED; ------------------------------------------------------------------------- -------- DRE Instance and controls ------------------------------------------------------------------------- ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_DRE -- -- If Generate Description: -- Includes the instance for the DRE -- -- ------------------------------------------------------------ GEN_INCLUDE_DRE : if (INCLUDE_DRE) generate signal lsig_eop_reg : std_logic := '0'; signal lsig_dre_load_beat : std_logic := '0'; signal lsig_dre_tlast_output_beat : std_logic := '0'; signal lsig_set_eop : std_logic := '0'; signal lsig_tlast_err_reg1 : std_logic := '0'; signal lsig_tlast_err_reg2 : std_logic := '0'; signal lsig_push_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal lsig_pushreg_full : std_logic := '0'; signal lsig_pushreg_empty : std_logic := '0'; signal lsig_pull_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal lsig_pullreg_full : std_logic := '0'; signal lsig_pullreg_empty : std_logic := '0'; signal lsig_pull_new_offset : std_logic := '0'; signal lsig_push_new_offset : std_logic := '0'; begin ------------------------------------------------------------ -- Instance: I_S2MM_DRE_BLOCK -- -- Description: -- Instance for the S2MM Data Realignment Engine (DRE) -- ------------------------------------------------------------ I_S2MM_DRE_BLOCK : entity axi_datamover_v5_1_10.axi_datamover_s2mm_dre generic map ( C_DWIDTH => C_STREAM_DWIDTH , C_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH ) port map ( -- Clock and Reset dre_clk => primary_aclk , dre_rst => mmap_reset , -- Alignment Control (Independent from Stream Input timing) dre_align_ready => sig_dre_align_ready , dre_align_valid => sig_sm_ld_dre_cmd , dre_use_autodest => sig_dre_use_autodest , dre_src_align => sig_scatter2dre_src_align , dre_dest_align => sig_dre_dest_align , -- Flush Control (Aligned to input Stream timing) dre_flush => sig_scatter2dre_flush , -- Stream Inputs dre_in_tstrb => sig_scatter2dre_tstrb , dre_in_tdata => sig_scatter2dre_tdata , dre_in_tlast => sig_scatter2dre_tlast , dre_in_tvalid => sig_scatter2dre_tvalid , dre_in_tready => sig_dre2scatter_tready , -- Stream Outputs dre_out_tstrb => sig_dre2wdc_tstrb , dre_out_tdata => sig_dre2wdc_tdata , dre_out_tlast => sig_dre2wdc_tlast , dre_out_tvalid => sig_dre2wdc_tvalid , dre_out_tready => sig_wdc2dre_tready ); lsig_dre_load_beat <= sig_scatter2dre_tvalid and sig_dre2scatter_tready; lsig_set_eop <= sig_scatter2drc_eop and lsig_dre_load_beat ; lsig_dre_tlast_output_beat <= sig_dre2wdc_tvalid and sig_wdc2dre_tready and sig_dre2wdc_tlast; dre2wdc_eop <= lsig_dre_tlast_output_beat and lsig_eop_reg; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_EOP_REG -- -- Process Description: -- Implements a flop for holding the EOP from the Scatter -- Engine until the corresponding packet clears out of the DRE. -- THis is used to transfer the EOP marker to the DRE output -- stream without the need for the DRE to pass it through. -- ------------------------------------------------------------- IMP_EOP_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or (lsig_dre_tlast_output_beat = '1' and lsig_set_eop = '0')) then lsig_eop_reg <= '0'; elsif (lsig_set_eop = '1') then lsig_eop_reg <= '1'; else null; -- Hold current state end if; end if; end process IMP_EOP_REG; -- Delay TLAST Error by 2 clocks to compensate for DRE minimum -- delay of 2 clocks for the stream data. sig_tlast_err0r <= lsig_tlast_err_reg2; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_TLAST_ERR_DELAY -- -- Process Description: -- Implements a 2 clock delay to better align the TLAST -- error detection with the Stream output data to the WDC -- which has a minimum 2 clock delay through the DRE. -- ------------------------------------------------------------- IMP_TLAST_ERR_DELAY : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then lsig_tlast_err_reg1 <= '0'; lsig_tlast_err_reg2 <= '0'; else lsig_tlast_err_reg1 <= sig_scatter2all_tlast_error; lsig_tlast_err_reg2 <= lsig_tlast_err_reg1; end if; end if; end process IMP_TLAST_ERR_DELAY; ------------------------------------------------------------------------- -- Store and Forward Start Address Offset Registers Logic -- Push-pull register is used to to time align the starting address -- offset (ripped from the Realigner command via parsing) to DRE -- TLAST output timing. The offset output of the pull register must -- be valid on the first output databeat of the DRE to the Store and -- Forward module. ------------------------------------------------------------------------- sig_dre2sf_strt_offset <= lsig_pull_strt_offset_reg; -- lsig_push_new_offset <= sig_dre_align_ready and -- sig_gated_dre_align_valid ; lsig_push_new_offset <= sig_sm_ld_dre_cmd ; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_PUSH_STRT_OFFSET_REG -- -- Process Description: -- Implements the input register for holding the starting address -- offset sent to the external Store and Forward functions. -- ------------------------------------------------------------- IMP_PUSH_STRT_OFFSET_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then lsig_push_strt_offset_reg <= (others => '0'); lsig_pushreg_full <= '0'; lsig_pushreg_empty <= '1'; elsif (lsig_push_new_offset = '1') then lsig_push_strt_offset_reg <= sig_curr_strt_offset_reg; lsig_pushreg_full <= '1'; lsig_pushreg_empty <= '0'; elsif (lsig_pull_new_offset = '1') then lsig_push_strt_offset_reg <= (others => '0'); lsig_pushreg_full <= '0'; lsig_pushreg_empty <= '1'; else null; -- Hold Current State end if; end if; end process IMP_PUSH_STRT_OFFSET_REG; -- Pull the next offset (if one exists) into the pull register -- when the DRE outputs a TLAST. If the pull register is empty -- and the push register has an offset, then push the new value -- into the pull register. lsig_pull_new_offset <= (sig_dre2wdc_tlast and sig_dre2wdc_tvalid and sig_wdc2dre_tready) or (lsig_pushreg_full and lsig_pullreg_empty); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_PULL_STRT_OFFSET_REG -- -- Process Description: -- Implements the output register for holding the starting -- address offset sent to the Store and Forward modul's upsizer -- logic. -- ------------------------------------------------------------- IMP_PULL_STRT_OFFSET_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then lsig_pull_strt_offset_reg <= (others => '0'); lsig_pullreg_full <= '0'; lsig_pullreg_empty <= '1'; elsif (lsig_pull_new_offset = '1' and lsig_pushreg_full = '1') then lsig_pull_strt_offset_reg <= lsig_push_strt_offset_reg; lsig_pullreg_full <= '1'; lsig_pullreg_empty <= '0'; elsif (lsig_pull_new_offset = '1' and lsig_pushreg_full = '0') then lsig_pull_strt_offset_reg <= (others => '0'); lsig_pullreg_full <= '0'; lsig_pullreg_empty <= '1'; else null; -- Hold Current State end if; end if; end process IMP_PULL_STRT_OFFSET_REG; end generate GEN_INCLUDE_DRE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_OMIT_DRE -- -- If Generate Description: -- Omits the DRE from the Re-aligner. -- -- ------------------------------------------------------------ GEN_OMIT_DRE : if (OMIT_DRE) generate begin -- DRE always ready sig_dre_align_ready <= '1'; -- -- Let the Scatter engine control the Realigner command -- -- flow. -- sig_dre_align_ready <= sig_scatter2drc_cmd_ready; -- Pass through signal connections sig_dre2wdc_tstrb <= sig_scatter2dre_tstrb ; sig_dre2wdc_tdata <= sig_scatter2dre_tdata ; sig_dre2wdc_tlast <= sig_scatter2dre_tlast ; sig_dre2wdc_tvalid <= sig_scatter2dre_tvalid ; sig_dre2scatter_tready <= sig_wdc2dre_tready ; dre2wdc_eop <= sig_scatter2drc_eop ; -- Just pass TLAST Error through when no DRE is present sig_tlast_err0r <= sig_scatter2all_tlast_error; ------------------------------------------------------------------------- -------- Store and Forward Start Address Offset Register Logic ------------------------------------------------------------------------- sig_dre2sf_strt_offset <= sig_output_strt_offset_reg; sig_ld_strt_offset <= sig_sm_ld_dre_cmd; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_STRT_OFFSET_OUTPUT -- -- Process Description: -- Implements the register for holding the starting address -- offset sent to the S2MM Store and Forward module's upsizer -- logic. -- ------------------------------------------------------------- IMP_STRT_OFFSET_OUTPUT : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_output_strt_offset_reg <= (others => '0'); elsif (sig_ld_strt_offset = '1') then sig_output_strt_offset_reg <= sig_curr_strt_offset_reg; else null; -- Hold Current State end if; end if; end process IMP_STRT_OFFSET_OUTPUT; end generate GEN_OMIT_DRE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_SCATTER -- -- If Generate Description: -- This IfGen implements the Scatter function which is a pre- -- processor for the S2MM DRE. The scatter function breaks up -- a continous input stream of data into constituant parts -- as described by a set of loaded commands that together -- describe an entire input packet. -- ------------------------------------------------------------ GEN_INCLUDE_SCATTER : if (C_SUPPORT_SCATTER = 1) generate begin -- Load the Scatter Engine command when the DRE command -- is loaded -- sig_drc2scatter_push_cmd <= sig_dre_align_ready and -- sig_gated_dre_align_valid; sig_drc2scatter_push_cmd <= sig_sm_ld_scatter_cmd ; -- Assign the new Bytes to Transfer (BTT) qualifier for the -- Scatter Engine sig_drc2scatter_btt <= sig_curr_btt_reg; -- Assign the new End of Frame (EOF) qualifier for the -- Scatter Engine sig_drc2scatter_eof <= sig_curr_eof_reg; ------------------------------------------------------------ -- Instance: I_S2MM_SCATTER -- -- Description: -- Instance for the Scatter Engine. This block breaks up a -- input stream per commands loaded. -- ------------------------------------------------------------ I_S2MM_SCATTER : entity axi_datamover_v5_1_10.axi_datamover_s2mm_scatter generic map ( C_ENABLE_INDET_BTT => C_ENABLE_INDET_BTT , C_DRE_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH , C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP , C_BTT_USED => BTT_WIDTH , C_STREAM_DWIDTH => C_STREAM_DWIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock input & Reset input primary_aclk => primary_aclk , mmap_reset => mmap_reset , -- DRE Realign Controller I/O ---------------------------- scatter2drc_cmd_ready => sig_scatter2drc_cmd_ready , drc2scatter_push_cmd => sig_drc2scatter_push_cmd , drc2scatter_btt => sig_drc2scatter_btt , drc2scatter_eof => sig_drc2scatter_eof , -- DRE Source Alignment ----------------------------------- scatter2drc_src_align => sig_scatter2dre_src_align , -- AXI Slave Stream In ----------------------------------- s2mm_strm_tready => sig_scatter2strm_tready , s2mm_strm_tvalid => sig_strm2scatter_tvalid , s2mm_strm_tdata => sig_strm2scatter_tdata , s2mm_strm_tstrb => sig_strm2scatter_tstrb , s2mm_strm_tlast => sig_strm2scatter_tlast , -- Stream Out to S2MM DRE --------------------------------- drc2scatter_tready => sig_dre2scatter_tready , scatter2drc_tvalid => sig_scatter2dre_tvalid , scatter2drc_tdata => sig_scatter2dre_tdata , scatter2drc_tstrb => sig_scatter2dre_tstrb , scatter2drc_tlast => sig_scatter2dre_tlast , scatter2drc_flush => sig_scatter2dre_flush , scatter2drc_eop => sig_scatter2drc_eop , -- Premature TLAST assertion error flag scatter2drc_tlast_error => sig_scatter2all_tlast_error ); end generate GEN_INCLUDE_SCATTER; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_OMIT_SCATTER -- -- If Generate Description: -- This IfGen omits the Scatter pre-processor. -- -- ------------------------------------------------------------ GEN_OMIT_SCATTER : if (C_SUPPORT_SCATTER = 0) generate begin -- Just housekeep the signaling sig_scatter2drc_cmd_ready <= '1' ; sig_scatter2drc_eop <= sig_strm2scatter_tlast ; sig_scatter2dre_src_align <= sig_dre_src_align ; sig_scatter2all_tlast_error <= '0' ; sig_scatter2dre_flush <= sig_dre_flush ; sig_scatter2dre_tstrb <= sig_strm2scatter_tstrb ; sig_scatter2dre_tdata <= sig_strm2scatter_tdata ; sig_scatter2dre_tlast <= sig_strm2scatter_tlast ; sig_scatter2dre_tvalid <= sig_strm2scatter_tvalid ; sig_scatter2strm_tready <= sig_dre2scatter_tready ; end generate GEN_OMIT_SCATTER; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_OMIT_INDET_BTT -- -- If Generate Description: -- Omit and special logic for Indeterminate BTT support. -- -- ------------------------------------------------------------ GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate begin sig_need_cmd_flush <= '0' ; -- not needed without Indeterminate BTT end generate GEN_OMIT_INDET_BTT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ENABLE_INDET_BTT -- -- If Generate Description: -- Include logic for the case when Indeterminate BTT is -- included as part of the S2MM. In this mode, the actual -- length of input stream packets is not known when the S2MM -- is loaded with a transfer command. -- ------------------------------------------------------------ GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate signal lsig_clr_cmd_flush : std_logic := '0'; signal lsig_set_cmd_flush : std_logic := '0'; signal lsig_cmd_set_fetch_pause : std_logic := '0'; signal lsig_cmd_clr_fetch_pause : std_logic := '0'; signal lsig_cmd_fetch_pause : std_logic := '0'; begin lsig_cmd_set_fetch_pause <= sig_drc2scatter_push_cmd and not(sig_curr_cmd_cmplt_reg) and not(sig_need_cmd_flush); lsig_cmd_clr_fetch_pause <= sig_scatter2dre_tvalid and sig_dre2scatter_tready and sig_scatter2dre_tlast; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CMD_FETCH_PAUSE -- -- Process Description: -- Implements the flop for the flag that causes the command -- queue manager to pause fetching the next command if the -- current command does not have the command complete bit set. -- The pause remains set until the associated TLAST for the -- command is output from the Scatter Engine. If the Tlast is -- also accompanied by a EOP and the pause is set, then the -- ensuing command (which will have the cmd cmplt bit set) must -- be flushed from the queue and not loaded into the Scatter -- Engine or DRE, This is normally associated with indeterminate -- packets that are actually shorter than the intial align to -- max burst child command sent to the Realigner, The next loaded -- child command is to finish the remainder of the indeterminate -- packet up to the full BTT value in the original parent command. -- This child command becomes stranded in the Realigner command fifo -- and has to be flushed. -- ------------------------------------------------------------- IMP_CMD_FETCH_PAUSE : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or lsig_cmd_clr_fetch_pause = '1') then lsig_cmd_fetch_pause <= '0'; elsif (lsig_cmd_set_fetch_pause = '1') then lsig_cmd_fetch_pause <= '1'; else null; -- Hold current state end if; end if; end process IMP_CMD_FETCH_PAUSE; -- Clear the flush needed flag when the command with the command -- complete marker is popped off of the command queue. lsig_clr_cmd_flush <= sig_need_cmd_flush and sig_sm_pop_cmd_fifo; -- The command queue has to be flushed if the stream EOP marker -- is transfered out of the Scatter Engine when the corresponding -- command being executed does not have the command complete -- marker set. lsig_set_cmd_flush <= lsig_cmd_fetch_pause and sig_scatter2dre_tvalid and sig_dre2scatter_tready and sig_scatter2drc_eop; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CMD_FLUSH_FLOP -- -- Process Description: -- Implements the flop for holding the command flush flag. -- This is only needed in Indeterminate BTT mode. -- ------------------------------------------------------------- IMP_CMD_FLUSH_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or lsig_clr_cmd_flush = '1') then sig_need_cmd_flush <= '0'; elsif (lsig_set_cmd_flush = '1') then sig_need_cmd_flush <= '1'; else null; -- Hold current state end if; end if; end process IMP_CMD_FLUSH_FLOP; end generate GEN_ENABLE_INDET_BTT; end implementation;
architecture RTl of FIFO is component fifo is end component fifo; -- Failures below component fifo is end component fifo; component fifo is end component fifo; begin end architecture RTL;
architecture RTl of FIFO is component fifo is end component fifo; -- Failures below component fifo is end component fifo; component fifo is end component fifo; begin end architecture RTL;
architecture RTl of FIFO is component fifo is end component fifo; -- Failures below component fifo is end component fifo; component fifo is end component fifo; begin end architecture RTL;
architecture RTl of FIFO is component fifo is end component fifo; -- Failures below component fifo is end component fifo; component fifo is end component fifo; begin end architecture RTL;
architecture RTl of FIFO is component fifo is end component fifo; -- Failures below component fifo is end component fifo; component fifo is end component fifo; begin end architecture RTL;
architecture RTl of FIFO is component fifo is end component fifo; -- Failures below component fifo is end component fifo; component fifo is end component fifo; begin end architecture RTL;
architecture RTl of FIFO is component fifo is end component fifo; -- Failures below component fifo is end component fifo; component fifo is end component fifo; begin end architecture RTL;
architecture RTl of FIFO is component fifo is end component fifo; -- Failures below component fifo is end component fifo; component fifo is end component fifo; begin end architecture RTL;
architecture RTl of FIFO is component fifo is end component fifo; -- Failures below component fifo is end component fifo; component fifo is end component fifo; begin end architecture RTL;
architecture RTl of FIFO is component fifo is end component fifo; -- Failures below component fifo is end component fifo; component fifo is end component fifo; begin end architecture RTL;
architecture RTl of FIFO is component fifo is end component fifo; -- Failures below component fifo is end component fifo; component fifo is end component fifo; begin end architecture RTL;
-- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_sg_updt_cmdsts_if.vhd -- Description: This entity is the descriptor update command and status inteface -- for the Scatter Gather Engine AXI DataMover. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_sg_v4_1_3; use axi_sg_v4_1_3.axi_sg_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_updt_cmdsts_if is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 -- Master AXI Memory Map Address Width for Scatter Gather R/W Port ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- Update command write interface from fetch sm -- updt_cmnd_wr : in std_logic ; -- updt_cmnd_data : in std_logic_vector -- ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); -- -- -- User Command Interface Ports (AXI Stream) -- s_axis_updt_cmd_tvalid : out std_logic ; -- s_axis_updt_cmd_tready : in std_logic ; -- s_axis_updt_cmd_tdata : out std_logic_vector -- ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); -- -- -- User Status Interface Ports (AXI Stream) -- m_axis_updt_sts_tvalid : in std_logic ; -- m_axis_updt_sts_tready : out std_logic ; -- m_axis_updt_sts_tdata : in std_logic_vector(7 downto 0) ; -- m_axis_updt_sts_tkeep : in std_logic_vector(0 downto 0) ; -- -- -- Scatter Gather Fetch Status -- s2mm_err : in std_logic ; -- updt_done : out std_logic ; -- updt_error : out std_logic ; -- updt_interr : out std_logic ; -- updt_slverr : out std_logic ; -- updt_decerr : out std_logic -- ); end axi_sg_updt_cmdsts_if; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_updt_cmdsts_if is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal updt_slverr_i : std_logic := '0'; signal updt_decerr_i : std_logic := '0'; signal updt_interr_i : std_logic := '0'; signal s2mm_error : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin updt_slverr <= updt_slverr_i; updt_decerr <= updt_decerr_i; updt_interr <= updt_interr_i; ------------------------------------------------------------------------------- -- DataMover Command Interface ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- When command by fetch sm, drive descriptor update command to data mover. -- Hold until data mover indicates ready. ------------------------------------------------------------------------------- GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s_axis_updt_cmd_tvalid <= '0'; -- s_axis_updt_cmd_tdata <= (others => '0'); elsif(updt_cmnd_wr = '1')then s_axis_updt_cmd_tvalid <= '1'; -- s_axis_updt_cmd_tdata <= updt_cmnd_data; elsif(s_axis_updt_cmd_tready = '1')then s_axis_updt_cmd_tvalid <= '0'; -- s_axis_updt_cmd_tdata <= (others => '0'); end if; end if; end process GEN_DATAMOVER_CMND; s_axis_updt_cmd_tdata <= updt_cmnd_data; ------------------------------------------------------------------------------- -- DataMover Status Interface ------------------------------------------------------------------------------- -- Drive ready low during reset to indicate not ready REG_STS_READY : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then m_axis_updt_sts_tready <= '0'; else m_axis_updt_sts_tready <= '1'; end if; end if; end process REG_STS_READY; ------------------------------------------------------------------------------- -- Log status bits out of data mover. ------------------------------------------------------------------------------- DATAMOVER_STS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_slverr_i <= '0'; updt_decerr_i <= '0'; updt_interr_i <= '0'; -- Status valid, therefore capture status elsif(m_axis_updt_sts_tvalid = '1')then updt_slverr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT); updt_decerr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT); updt_interr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT); -- Only assert when valid else updt_slverr_i <= '0'; updt_decerr_i <= '0'; updt_interr_i <= '0'; end if; end if; end process DATAMOVER_STS; ------------------------------------------------------------------------------- -- Transfer Done ------------------------------------------------------------------------------- XFER_DONE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_done <= '0'; -- Status valid, therefore capture status elsif(m_axis_updt_sts_tvalid = '1')then updt_done <= m_axis_updt_sts_tdata(DATAMOVER_STS_CMDDONE_BIT) or m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT) or m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT) or m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT); -- Only assert when valid else updt_done <= '0'; end if; end if; end process XFER_DONE; ------------------------------------------------------------------------------- -- Register global error from data mover. ------------------------------------------------------------------------------- s2mm_error <= updt_slverr_i or updt_decerr_i or updt_interr_i; -- Log errors into a global error output UPDATE_ERROR_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_error <= '0'; elsif(s2mm_error = '1')then updt_error <= '1'; end if; end if; end process UPDATE_ERROR_PROCESS; end implementation;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_05_ch_05_14.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity ch_05_14 is end entity ch_05_14; ---------------------------------------------------------------- architecture test of ch_05_14 is signal PC, functional_next_PC, equivalent_next_PC : integer := 0; begin block_05_3_p : block is port ( next_PC : out integer ); port map ( next_PC => functional_next_PC ); begin -- code from book: PC_incr : next_PC <= PC + 4 after 5 ns; -- end of code from book end block block_05_3_p; ---------------- block_05_3_q : block is port ( next_PC : out integer ); port map ( next_PC => equivalent_next_PC ); begin -- code from book: PC_incr : process is begin next_PC <= PC + 4 after 5 ns; wait on PC; end process PC_incr; -- end of code from book end block block_05_3_q; ---------------- stimulus : process is begin for i in 1 to 10 loop PC <= i after 20 ns; wait for 20 ns; end loop; wait; end process stimulus; verifier : assert functional_next_PC = equivalent_next_PC report "Functional and equivalent models give different results"; end architecture test;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_05_ch_05_14.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity ch_05_14 is end entity ch_05_14; ---------------------------------------------------------------- architecture test of ch_05_14 is signal PC, functional_next_PC, equivalent_next_PC : integer := 0; begin block_05_3_p : block is port ( next_PC : out integer ); port map ( next_PC => functional_next_PC ); begin -- code from book: PC_incr : next_PC <= PC + 4 after 5 ns; -- end of code from book end block block_05_3_p; ---------------- block_05_3_q : block is port ( next_PC : out integer ); port map ( next_PC => equivalent_next_PC ); begin -- code from book: PC_incr : process is begin next_PC <= PC + 4 after 5 ns; wait on PC; end process PC_incr; -- end of code from book end block block_05_3_q; ---------------- stimulus : process is begin for i in 1 to 10 loop PC <= i after 20 ns; wait for 20 ns; end loop; wait; end process stimulus; verifier : assert functional_next_PC = equivalent_next_PC report "Functional and equivalent models give different results"; end architecture test;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_05_ch_05_14.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity ch_05_14 is end entity ch_05_14; ---------------------------------------------------------------- architecture test of ch_05_14 is signal PC, functional_next_PC, equivalent_next_PC : integer := 0; begin block_05_3_p : block is port ( next_PC : out integer ); port map ( next_PC => functional_next_PC ); begin -- code from book: PC_incr : next_PC <= PC + 4 after 5 ns; -- end of code from book end block block_05_3_p; ---------------- block_05_3_q : block is port ( next_PC : out integer ); port map ( next_PC => equivalent_next_PC ); begin -- code from book: PC_incr : process is begin next_PC <= PC + 4 after 5 ns; wait on PC; end process PC_incr; -- end of code from book end block block_05_3_q; ---------------- stimulus : process is begin for i in 1 to 10 loop PC <= i after 20 ns; wait for 20 ns; end loop; wait; end process stimulus; verifier : assert functional_next_PC = equivalent_next_PC report "Functional and equivalent models give different results"; end architecture test;
------------------------------------------------------------------------------- -- File Name : AC_ROM.vhd -- -- Project : JPEG_ENC -- -- Module : AC_ROM -- -- Content : AC_ROM Luminance -- -- Description : -- -- Spec. : -- -- Author : Michal Krepa -- ------------------------------------------------------------------------------- -- History : -- 20090228: (MK): Initial Creation. ------------------------------------------------------------------------------- -- ////////////////////////////////////////////////////////////////////////////// -- /// Copyright (c) 2013, Jahanzeb Ahmad -- /// All rights reserved. -- /// -- /// Redistribution and use in source and binary forms, with or without modification, -- /// are permitted provided that the following conditions are met: -- /// -- /// * Redistributions of source code must retain the above copyright notice, -- /// this list of conditions and the following disclaimer. -- /// * Redistributions in binary form must reproduce the above copyright notice, -- /// this list of conditions and the following disclaimer in the documentation and/or -- /// other materials provided with the distribution. -- /// -- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY -- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT -- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- /// POSSIBILITY OF SUCH DAMAGE. -- /// -- /// -- /// * http://opensource.org/licenses/MIT -- /// * http://copyfree.org/licenses/mit/license.txt -- /// -- ////////////////////////////////////////////////////////////////////////////// ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ----------------------------------- LIBRARY/PACKAGE --------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- generic packages/libraries: ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------------------------- -- user packages/libraries: ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ----------------------------------- ENTITY ------------------------------------ ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- entity AC_ROM is port ( CLK : in std_logic; RST : in std_logic; runlength : in std_logic_vector(3 downto 0); VLI_size : in std_logic_vector(3 downto 0); VLC_AC_size : out unsigned(4 downto 0); VLC_AC : out unsigned(15 downto 0) ); end entity AC_ROM; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ----------------------------------- ARCHITECTURE ------------------------------ ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- architecture RTL of AC_ROM is signal rom_addr : std_logic_vector(7 downto 0); ------------------------------------------------------------------------------- -- Architecture: begin ------------------------------------------------------------------------------- begin rom_addr <= runlength & VLI_size; ------------------------------------------------------------------- -- AC-ROM ------------------------------------------------------------------- p_AC_ROM : process(CLK, RST) begin if RST = '1' then VLC_AC_size <= (others => '0'); VLC_AC <= (others => '0'); elsif CLK'event and CLK = '1' then case runlength is when X"0" => case VLI_size is when X"0" => VLC_AC_size <= to_unsigned(4, VLC_AC_size'length); VLC_AC <= resize("1010", VLC_AC'length); when X"1" => VLC_AC_size <= to_unsigned(2, VLC_AC_size'length); VLC_AC <= resize("00", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(2, VLC_AC_size'length); VLC_AC <= resize("01", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(3, VLC_AC_size'length); VLC_AC <= resize("100", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(4, VLC_AC_size'length); VLC_AC <= resize("1011", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(5, VLC_AC_size'length); VLC_AC <= resize("11010", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(7, VLC_AC_size'length); VLC_AC <= resize("1111000", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(8, VLC_AC_size'length); VLC_AC <= resize("11111000", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); VLC_AC <= resize("1111110110", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110000010", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110000011", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"1" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(4, VLC_AC_size'length); VLC_AC <= resize("1100", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(5, VLC_AC_size'length); VLC_AC <= resize("11011", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(7, VLC_AC_size'length); VLC_AC <= resize("1111001", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); VLC_AC <= resize("111110110", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); VLC_AC <= resize("11111110110", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110000100", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110000101", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110000110", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110000111", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001000", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"2" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(5, VLC_AC_size'length); VLC_AC <= resize("11100", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(8, VLC_AC_size'length); VLC_AC <= resize("11111001", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); VLC_AC <= resize("1111110111", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); VLC_AC <= resize("111111110100", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001001", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001010", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001011", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001100", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001101", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001110", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"3" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(6, VLC_AC_size'length); VLC_AC <= resize("111010", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); VLC_AC <= resize("111110111", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); VLC_AC <= resize("111111110101", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001111", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010000", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010001", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010010", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010011", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010100", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010101", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"4" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(6, VLC_AC_size'length); VLC_AC <= resize("111011", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); VLC_AC <= resize("1111111000", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010110", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010111", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011000", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011001", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011010", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011011", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011100", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011101", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"5" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(7, VLC_AC_size'length); VLC_AC <= resize("1111010", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); VLC_AC <= resize("11111110111", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011110", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011111", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100000", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100001", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100010", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100011", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100100", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100101", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"6" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(7, VLC_AC_size'length); VLC_AC <= resize("1111011", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); VLC_AC <= resize("111111110110", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100110", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100111", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101000", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101001", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101010", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101011", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101100", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101101", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"7" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(8, VLC_AC_size'length); VLC_AC <= resize("11111010", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); VLC_AC <= resize("111111110111", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101110", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101111", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110000", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110001", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110010", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110011", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110100", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110101", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"8" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); VLC_AC <= resize("111111000", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(15, VLC_AC_size'length); VLC_AC <= resize("111111111000000", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110110", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110111", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111000", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111001", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111010", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111011", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111100", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111101", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"9" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); VLC_AC <= resize("111111001", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111110", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111111", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000000", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000001", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000010", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000011", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000100", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000101", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000110", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"A" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); VLC_AC <= resize("111111010", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000111", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001000", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001001", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001010", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001011", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001100", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001101", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001110", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001111", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"B" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); VLC_AC <= resize("1111111001", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010000", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010001", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010010", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010011", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010100", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010101", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010110", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010111", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011000", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"C" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); VLC_AC <= resize("1111111010", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011001", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011010", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011011", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011100", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011101", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011110", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011111", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100000", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100001", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"D" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); VLC_AC <= resize("11111111000", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100010", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100011", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100100", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100101", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100110", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100111", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101000", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101001", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101010", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"E" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101011", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101100", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101101", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101110", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101111", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110000", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110001", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110010", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110011", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110100", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"F" => case VLI_size is when X"0" => VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); VLC_AC <= resize("11111111001", VLC_AC'length); when X"1" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110101", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110110", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110111", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111000", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111001", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111010", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111011", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111100", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111101", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111110", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when others => VLC_AC_size <= (others => '0'); VLC_AC <= (others => '0'); end case; end if; end process; end architecture RTL; ------------------------------------------------------------------------------- -- Architecture: end -------------------------------------------------------------------------------
------------------------------------------------------------------------------- -- File Name : AC_ROM.vhd -- -- Project : JPEG_ENC -- -- Module : AC_ROM -- -- Content : AC_ROM Luminance -- -- Description : -- -- Spec. : -- -- Author : Michal Krepa -- ------------------------------------------------------------------------------- -- History : -- 20090228: (MK): Initial Creation. ------------------------------------------------------------------------------- -- ////////////////////////////////////////////////////////////////////////////// -- /// Copyright (c) 2013, Jahanzeb Ahmad -- /// All rights reserved. -- /// -- /// Redistribution and use in source and binary forms, with or without modification, -- /// are permitted provided that the following conditions are met: -- /// -- /// * Redistributions of source code must retain the above copyright notice, -- /// this list of conditions and the following disclaimer. -- /// * Redistributions in binary form must reproduce the above copyright notice, -- /// this list of conditions and the following disclaimer in the documentation and/or -- /// other materials provided with the distribution. -- /// -- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY -- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT -- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- /// POSSIBILITY OF SUCH DAMAGE. -- /// -- /// -- /// * http://opensource.org/licenses/MIT -- /// * http://copyfree.org/licenses/mit/license.txt -- /// -- ////////////////////////////////////////////////////////////////////////////// ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ----------------------------------- LIBRARY/PACKAGE --------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- generic packages/libraries: ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------------------------- -- user packages/libraries: ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ----------------------------------- ENTITY ------------------------------------ ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- entity AC_ROM is port ( CLK : in std_logic; RST : in std_logic; runlength : in std_logic_vector(3 downto 0); VLI_size : in std_logic_vector(3 downto 0); VLC_AC_size : out unsigned(4 downto 0); VLC_AC : out unsigned(15 downto 0) ); end entity AC_ROM; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ----------------------------------- ARCHITECTURE ------------------------------ ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- architecture RTL of AC_ROM is signal rom_addr : std_logic_vector(7 downto 0); ------------------------------------------------------------------------------- -- Architecture: begin ------------------------------------------------------------------------------- begin rom_addr <= runlength & VLI_size; ------------------------------------------------------------------- -- AC-ROM ------------------------------------------------------------------- p_AC_ROM : process(CLK, RST) begin if RST = '1' then VLC_AC_size <= (others => '0'); VLC_AC <= (others => '0'); elsif CLK'event and CLK = '1' then case runlength is when X"0" => case VLI_size is when X"0" => VLC_AC_size <= to_unsigned(4, VLC_AC_size'length); VLC_AC <= resize("1010", VLC_AC'length); when X"1" => VLC_AC_size <= to_unsigned(2, VLC_AC_size'length); VLC_AC <= resize("00", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(2, VLC_AC_size'length); VLC_AC <= resize("01", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(3, VLC_AC_size'length); VLC_AC <= resize("100", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(4, VLC_AC_size'length); VLC_AC <= resize("1011", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(5, VLC_AC_size'length); VLC_AC <= resize("11010", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(7, VLC_AC_size'length); VLC_AC <= resize("1111000", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(8, VLC_AC_size'length); VLC_AC <= resize("11111000", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); VLC_AC <= resize("1111110110", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110000010", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110000011", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"1" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(4, VLC_AC_size'length); VLC_AC <= resize("1100", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(5, VLC_AC_size'length); VLC_AC <= resize("11011", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(7, VLC_AC_size'length); VLC_AC <= resize("1111001", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); VLC_AC <= resize("111110110", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); VLC_AC <= resize("11111110110", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110000100", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110000101", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110000110", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110000111", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001000", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"2" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(5, VLC_AC_size'length); VLC_AC <= resize("11100", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(8, VLC_AC_size'length); VLC_AC <= resize("11111001", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); VLC_AC <= resize("1111110111", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); VLC_AC <= resize("111111110100", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001001", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001010", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001011", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001100", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001101", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001110", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"3" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(6, VLC_AC_size'length); VLC_AC <= resize("111010", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); VLC_AC <= resize("111110111", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); VLC_AC <= resize("111111110101", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001111", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010000", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010001", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010010", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010011", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010100", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010101", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"4" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(6, VLC_AC_size'length); VLC_AC <= resize("111011", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); VLC_AC <= resize("1111111000", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010110", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010111", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011000", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011001", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011010", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011011", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011100", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011101", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"5" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(7, VLC_AC_size'length); VLC_AC <= resize("1111010", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); VLC_AC <= resize("11111110111", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011110", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011111", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100000", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100001", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100010", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100011", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100100", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100101", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"6" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(7, VLC_AC_size'length); VLC_AC <= resize("1111011", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); VLC_AC <= resize("111111110110", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100110", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100111", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101000", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101001", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101010", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101011", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101100", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101101", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"7" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(8, VLC_AC_size'length); VLC_AC <= resize("11111010", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); VLC_AC <= resize("111111110111", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101110", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101111", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110000", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110001", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110010", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110011", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110100", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110101", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"8" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); VLC_AC <= resize("111111000", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(15, VLC_AC_size'length); VLC_AC <= resize("111111111000000", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110110", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110111", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111000", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111001", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111010", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111011", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111100", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111101", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"9" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); VLC_AC <= resize("111111001", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111110", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111111", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000000", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000001", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000010", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000011", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000100", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000101", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000110", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"A" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); VLC_AC <= resize("111111010", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000111", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001000", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001001", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001010", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001011", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001100", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001101", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001110", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001111", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"B" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); VLC_AC <= resize("1111111001", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010000", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010001", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010010", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010011", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010100", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010101", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010110", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010111", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011000", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"C" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); VLC_AC <= resize("1111111010", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011001", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011010", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011011", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011100", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011101", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011110", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011111", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100000", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100001", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"D" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); VLC_AC <= resize("11111111000", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100010", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100011", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100100", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100101", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100110", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100111", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101000", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101001", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101010", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"E" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101011", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101100", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101101", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101110", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101111", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110000", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110001", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110010", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110011", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110100", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"F" => case VLI_size is when X"0" => VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); VLC_AC <= resize("11111111001", VLC_AC'length); when X"1" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110101", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110110", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110111", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111000", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111001", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111010", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111011", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111100", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111101", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111110", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when others => VLC_AC_size <= (others => '0'); VLC_AC <= (others => '0'); end case; end if; end process; end architecture RTL; ------------------------------------------------------------------------------- -- Architecture: end -------------------------------------------------------------------------------
------------------------------------------------------------------------------- -- File Name : AC_ROM.vhd -- -- Project : JPEG_ENC -- -- Module : AC_ROM -- -- Content : AC_ROM Luminance -- -- Description : -- -- Spec. : -- -- Author : Michal Krepa -- ------------------------------------------------------------------------------- -- History : -- 20090228: (MK): Initial Creation. ------------------------------------------------------------------------------- -- ////////////////////////////////////////////////////////////////////////////// -- /// Copyright (c) 2013, Jahanzeb Ahmad -- /// All rights reserved. -- /// -- /// Redistribution and use in source and binary forms, with or without modification, -- /// are permitted provided that the following conditions are met: -- /// -- /// * Redistributions of source code must retain the above copyright notice, -- /// this list of conditions and the following disclaimer. -- /// * Redistributions in binary form must reproduce the above copyright notice, -- /// this list of conditions and the following disclaimer in the documentation and/or -- /// other materials provided with the distribution. -- /// -- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY -- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT -- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- /// POSSIBILITY OF SUCH DAMAGE. -- /// -- /// -- /// * http://opensource.org/licenses/MIT -- /// * http://copyfree.org/licenses/mit/license.txt -- /// -- ////////////////////////////////////////////////////////////////////////////// ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ----------------------------------- LIBRARY/PACKAGE --------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- generic packages/libraries: ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------------------------- -- user packages/libraries: ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ----------------------------------- ENTITY ------------------------------------ ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- entity AC_ROM is port ( CLK : in std_logic; RST : in std_logic; runlength : in std_logic_vector(3 downto 0); VLI_size : in std_logic_vector(3 downto 0); VLC_AC_size : out unsigned(4 downto 0); VLC_AC : out unsigned(15 downto 0) ); end entity AC_ROM; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ----------------------------------- ARCHITECTURE ------------------------------ ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- architecture RTL of AC_ROM is signal rom_addr : std_logic_vector(7 downto 0); ------------------------------------------------------------------------------- -- Architecture: begin ------------------------------------------------------------------------------- begin rom_addr <= runlength & VLI_size; ------------------------------------------------------------------- -- AC-ROM ------------------------------------------------------------------- p_AC_ROM : process(CLK, RST) begin if RST = '1' then VLC_AC_size <= (others => '0'); VLC_AC <= (others => '0'); elsif CLK'event and CLK = '1' then case runlength is when X"0" => case VLI_size is when X"0" => VLC_AC_size <= to_unsigned(4, VLC_AC_size'length); VLC_AC <= resize("1010", VLC_AC'length); when X"1" => VLC_AC_size <= to_unsigned(2, VLC_AC_size'length); VLC_AC <= resize("00", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(2, VLC_AC_size'length); VLC_AC <= resize("01", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(3, VLC_AC_size'length); VLC_AC <= resize("100", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(4, VLC_AC_size'length); VLC_AC <= resize("1011", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(5, VLC_AC_size'length); VLC_AC <= resize("11010", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(7, VLC_AC_size'length); VLC_AC <= resize("1111000", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(8, VLC_AC_size'length); VLC_AC <= resize("11111000", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); VLC_AC <= resize("1111110110", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110000010", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110000011", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"1" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(4, VLC_AC_size'length); VLC_AC <= resize("1100", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(5, VLC_AC_size'length); VLC_AC <= resize("11011", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(7, VLC_AC_size'length); VLC_AC <= resize("1111001", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); VLC_AC <= resize("111110110", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); VLC_AC <= resize("11111110110", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110000100", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110000101", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110000110", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110000111", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001000", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"2" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(5, VLC_AC_size'length); VLC_AC <= resize("11100", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(8, VLC_AC_size'length); VLC_AC <= resize("11111001", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); VLC_AC <= resize("1111110111", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); VLC_AC <= resize("111111110100", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001001", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001010", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001011", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001100", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001101", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001110", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"3" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(6, VLC_AC_size'length); VLC_AC <= resize("111010", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); VLC_AC <= resize("111110111", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); VLC_AC <= resize("111111110101", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001111", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010000", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010001", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010010", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010011", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010100", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010101", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"4" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(6, VLC_AC_size'length); VLC_AC <= resize("111011", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); VLC_AC <= resize("1111111000", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010110", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010111", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011000", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011001", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011010", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011011", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011100", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011101", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"5" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(7, VLC_AC_size'length); VLC_AC <= resize("1111010", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); VLC_AC <= resize("11111110111", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011110", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011111", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100000", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100001", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100010", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100011", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100100", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100101", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"6" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(7, VLC_AC_size'length); VLC_AC <= resize("1111011", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); VLC_AC <= resize("111111110110", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100110", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100111", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101000", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101001", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101010", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101011", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101100", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101101", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"7" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(8, VLC_AC_size'length); VLC_AC <= resize("11111010", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); VLC_AC <= resize("111111110111", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101110", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101111", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110000", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110001", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110010", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110011", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110100", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110101", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"8" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); VLC_AC <= resize("111111000", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(15, VLC_AC_size'length); VLC_AC <= resize("111111111000000", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110110", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110111", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111000", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111001", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111010", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111011", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111100", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111101", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"9" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); VLC_AC <= resize("111111001", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111110", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111111", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000000", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000001", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000010", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000011", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000100", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000101", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000110", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"A" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); VLC_AC <= resize("111111010", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000111", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001000", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001001", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001010", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001011", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001100", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001101", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001110", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001111", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"B" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); VLC_AC <= resize("1111111001", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010000", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010001", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010010", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010011", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010100", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010101", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010110", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010111", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011000", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"C" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); VLC_AC <= resize("1111111010", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011001", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011010", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011011", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011100", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011101", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011110", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011111", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100000", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100001", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"D" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); VLC_AC <= resize("11111111000", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100010", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100011", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100100", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100101", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100110", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100111", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101000", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101001", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101010", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"E" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101011", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101100", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101101", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101110", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101111", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110000", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110001", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110010", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110011", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110100", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"F" => case VLI_size is when X"0" => VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); VLC_AC <= resize("11111111001", VLC_AC'length); when X"1" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110101", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110110", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110111", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111000", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111001", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111010", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111011", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111100", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111101", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111110", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when others => VLC_AC_size <= (others => '0'); VLC_AC <= (others => '0'); end case; end if; end process; end architecture RTL; ------------------------------------------------------------------------------- -- Architecture: end -------------------------------------------------------------------------------
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017 -- Date : Tue Oct 17 15:44:51 2017 -- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS -- Command : write_vhdl -force -mode synth_stub -- /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/led_controller/led_controller.srcs/sources_1/bd/led_controller_design/ip/led_controller_design_led_controller_0_0/led_controller_design_led_controller_0_0_stub.vhdl -- Design : led_controller_design_led_controller_0_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity led_controller_design_led_controller_0_0 is Port ( LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 ); s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s00_axi_awvalid : in STD_LOGIC; s00_axi_awready : out STD_LOGIC; s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s00_axi_wvalid : in STD_LOGIC; s00_axi_wready : out STD_LOGIC; s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s00_axi_bvalid : out STD_LOGIC; s00_axi_bready : in STD_LOGIC; s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 ); s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s00_axi_arvalid : in STD_LOGIC; s00_axi_arready : out STD_LOGIC; s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s00_axi_rvalid : out STD_LOGIC; s00_axi_rready : in STD_LOGIC; s00_axi_aclk : in STD_LOGIC; s00_axi_aresetn : in STD_LOGIC ); end led_controller_design_led_controller_0_0; architecture stub of led_controller_design_led_controller_0_0 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "LEDs_out[7:0],s00_axi_awaddr[3:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[3:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "led_controller_v1_0,Vivado 2017.3"; begin end;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_05_tb_05_07.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $ -- $Revision: 1.1.1.1 $ -- -- --------------------------------------------------------------------- architecture functional of S_R_flipflop is begin q <= '1' when s = '1' else '0' when r = '1'; q_n <= '0' when s = '1' else '1' when r = '1'; end architecture functional; entity tb_05_07 is end entity tb_05_07; architecture test of tb_05_07 is signal s, r : bit := '0'; signal q, q_n : bit; begin dut : entity work.S_R_flipflop(functional) port map ( s => s, r => r, q => q, q_n => q_n ); stimulus : process is begin wait for 10 ns; s <= '1'; wait for 10 ns; s <= '0'; wait for 10 ns; r <= '1'; wait for 10 ns; r <= '0'; wait for 10 ns; s <= '1'; wait for 10 ns; r <= '1'; wait for 10 ns; s <= '0'; wait for 10 ns; r <= '0'; wait for 10 ns; wait; end process stimulus; end architecture test;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_05_tb_05_07.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $ -- $Revision: 1.1.1.1 $ -- -- --------------------------------------------------------------------- architecture functional of S_R_flipflop is begin q <= '1' when s = '1' else '0' when r = '1'; q_n <= '0' when s = '1' else '1' when r = '1'; end architecture functional; entity tb_05_07 is end entity tb_05_07; architecture test of tb_05_07 is signal s, r : bit := '0'; signal q, q_n : bit; begin dut : entity work.S_R_flipflop(functional) port map ( s => s, r => r, q => q, q_n => q_n ); stimulus : process is begin wait for 10 ns; s <= '1'; wait for 10 ns; s <= '0'; wait for 10 ns; r <= '1'; wait for 10 ns; r <= '0'; wait for 10 ns; s <= '1'; wait for 10 ns; r <= '1'; wait for 10 ns; s <= '0'; wait for 10 ns; r <= '0'; wait for 10 ns; wait; end process stimulus; end architecture test;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_05_tb_05_07.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $ -- $Revision: 1.1.1.1 $ -- -- --------------------------------------------------------------------- architecture functional of S_R_flipflop is begin q <= '1' when s = '1' else '0' when r = '1'; q_n <= '0' when s = '1' else '1' when r = '1'; end architecture functional; entity tb_05_07 is end entity tb_05_07; architecture test of tb_05_07 is signal s, r : bit := '0'; signal q, q_n : bit; begin dut : entity work.S_R_flipflop(functional) port map ( s => s, r => r, q => q, q_n => q_n ); stimulus : process is begin wait for 10 ns; s <= '1'; wait for 10 ns; s <= '0'; wait for 10 ns; r <= '1'; wait for 10 ns; r <= '0'; wait for 10 ns; s <= '1'; wait for 10 ns; r <= '1'; wait for 10 ns; s <= '0'; wait for 10 ns; r <= '0'; wait for 10 ns; wait; end process stimulus; end architecture test;
------------------------------------------------------------------------------- -- axi_datamover_wr_status_cntl.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_wr_status_cntl.vhd -- -- Description: -- This file implements the DataMover Master Write Status Controller. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_datamover_wr_status_cntl.vhd -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- -- History: -- DET 04/19/2011 Initial Version for EDK 13.3 -- -- DET 7/11/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- -- Per CR616212 -- - Changed logic to force a coesc register push when a TLAST error is -- reported by the Write Data Controller. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_fifo; ------------------------------------------------------------------------------- entity axi_datamover_wr_status_cntl is generic ( C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0; -- Specifies if the Indeterminate BTT Module is enabled -- for use (outside of this module) C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1; -- Sets the width of the data2wsc_bytes_rcvd port used for -- relaying the actual number of bytes received when Idet BTT is -- enabled (C_ENABLE_INDET_BTT = 1) C_STS_FIFO_DEPTH : Integer range 1 to 32 := 8; -- Specifies the depth of the internal status queue fifo C_STS_WIDTH : Integer range 8 to 32 := 8; -- sets the width of the Status ports C_TAG_WIDTH : Integer range 1 to 8 := 4; -- Sets the width of the Tag field in the Status reply C_FAMILY : String := "virtex7" -- Specifies the target FPGA device family ); port ( -- Clock and Reset inputs ------------------------------------------ -- primary_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- mmap_reset : in std_logic; -- -- Reset used for the internal master logic -- -------------------------------------------------------------------- -- Soft Shutdown Control interface -------------------------------- -- rst2wsc_stop_request : in std_logic; -- -- Active high soft stop request to modules -- -- wsc2rst_stop_cmplt : Out std_logic; -- -- Active high indication that the Write status Controller -- -- has completed any pending transfers committed by the -- -- Address Controller after a stop has been requested by -- -- the Reset module. -- -- addr2wsc_addr_posted : In std_logic ; -- -- Indication from the Address Channel Controller to the -- -- write Status Controller that an address has been posted -- -- to the AXI Address Channel -- -------------------------------------------------------------------- -- Write Response Channel Interface ------------------------------- -- s2mm_bresp : In std_logic_vector(1 downto 0); -- -- The Write response value -- -- s2mm_bvalid : In std_logic ; -- -- Indication from the Write Response Channel that a new -- -- write status input is valid -- -- s2mm_bready : out std_logic ; -- -- Indication to the Write Response Channel that the -- -- Status module is ready for a new status input -- -------------------------------------------------------------------- -- Command Calculator Interface ------------------------------------- -- calc2wsc_calc_error : in std_logic ; -- -- Indication from the Command Calculator that a calculation -- -- error has occured. -- --------------------------------------------------------------------- -- Address Controller Status ---------------------------------------- -- addr2wsc_calc_error : In std_logic ; -- -- Indication from the Address Channel Controller that it -- -- has encountered a calculation error from the command -- -- Calculator -- -- addr2wsc_fifo_empty : In std_logic ; -- -- Indication from the Address Controller FIFO that it -- -- is empty (no commands pending) -- --------------------------------------------------------------------- -- Data Controller Status --------------------------------------------------------- -- data2wsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The command tag -- -- data2wsc_calc_error : In std_logic ; -- -- Indication from the Data Channel Controller FIFO that it -- -- has encountered a Calculation error in the command pipe -- -- data2wsc_last_error : In std_logic ; -- -- Indication from the Write Data Channel Controller that a -- -- premature TLAST assertion was encountered on the incoming -- -- Stream Channel -- -- data2wsc_cmd_cmplt : In std_logic ; -- -- Indication from the Data Channel Controller that the -- -- corresponding status is the final status for a parent -- -- command fetched from the command FIFO -- -- data2wsc_valid : In std_logic ; -- -- Indication from the Data Channel Controller FIFO that it -- -- has a new tag/error status to transfer -- -- wsc2data_ready : out std_logic ; -- -- Indication to the Data Channel Controller FIFO that the -- -- Status module is ready for a new tag/error status input -- -- -- data2wsc_eop : In std_logic; -- -- Input from the Write Data Controller indicating that the -- -- associated command status also corresponds to a End of Packet -- -- marker for the input Stream. This is only used when Store and -- -- Forward is enabled in the S2MM. -- -- data2wsc_bytes_rcvd : In std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); -- -- Input from the Write Data Controller indicating the actual -- -- number of bytes received from the Stream input for the -- -- corresponding command status. This is only used when Store and -- -- Forward is enabled in the S2MM. -- ------------------------------------------------------------------------------------ -- Command/Status Interface -------------------------------------------------------- -- wsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); -- -- Read Status value collected during a Read Data transfer -- -- Output to the Command/Status Module -- -- stat2wsc_status_ready : In std_logic; -- -- Input from the Command/Status Module indicating that the -- -- Status Reg/FIFO is Full and cannot accept more staus writes -- -- wsc2stat_status_valid : Out std_logic ; -- -- Control Signal to Write the Status value to the Status -- -- Reg/FIFO -- ------------------------------------------------------------------------------------ -- Address and Data Controller Pipe halt -------------------------------- -- wsc2mstr_halt_pipe : Out std_logic -- -- Indication to Halt the Data and Address Command pipeline due -- -- to the Status pipe getting full at some point -- ------------------------------------------------------------------------- ); end entity axi_datamover_wr_status_cntl; architecture implementation of axi_datamover_wr_status_cntl is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_set_cnt_width -- -- Function Description: -- Sets a count width based on a fifo depth. A depth of 4 or less -- is a special case which requires a minimum count width of 3 bits. -- ------------------------------------------------------------------- function funct_set_cnt_width (fifo_depth : integer) return integer is Variable temp_cnt_width : Integer := 4; begin if (fifo_depth <= 4) then temp_cnt_width := 3; elsif (fifo_depth <= 8) then temp_cnt_width := 4; elsif (fifo_depth <= 16) then temp_cnt_width := 5; elsif (fifo_depth <= 32) then temp_cnt_width := 6; else -- fifo depth <= 64 temp_cnt_width := 7; end if; Return (temp_cnt_width); end function funct_set_cnt_width; -- Constant Declarations -------------------------------------------- Constant OKAY : std_logic_vector(1 downto 0) := "00"; Constant EXOKAY : std_logic_vector(1 downto 0) := "01"; Constant SLVERR : std_logic_vector(1 downto 0) := "10"; Constant DECERR : std_logic_vector(1 downto 0) := "11"; Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000"; Constant TAG_WIDTH : integer := C_TAG_WIDTH; Constant STAT_REG_TAG_WIDTH : integer := 4; Constant SYNC_FIFO_SELECT : integer := 0; Constant SRL_FIFO_TYPE : integer := 2; Constant DCNTL_SFIFO_DEPTH : integer := C_STS_FIFO_DEPTH; Constant DCNTL_STATCNT_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits Constant DCNTL_HALT_THRES : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := TO_UNSIGNED(DCNTL_SFIFO_DEPTH-2,DCNTL_STATCNT_WIDTH); Constant DCNTL_STATCNT_ZERO : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0'); Constant DCNTL_STATCNT_MAX : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := TO_UNSIGNED(DCNTL_SFIFO_DEPTH,DCNTL_STATCNT_WIDTH); Constant DCNTL_STATCNT_ONE : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := TO_UNSIGNED(1, DCNTL_STATCNT_WIDTH); Constant WRESP_WIDTH : integer := 2; Constant WRESP_SFIFO_WIDTH : integer := WRESP_WIDTH; Constant WRESP_SFIFO_DEPTH : integer := DCNTL_SFIFO_DEPTH; Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0'); Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH); Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '1'); -- Signal Declarations -------------------------------------------- signal sig_valid_status_rdy : std_logic := '0'; signal sig_decerr : std_logic := '0'; signal sig_slverr : std_logic := '0'; signal sig_coelsc_okay_reg : std_logic := '0'; signal sig_coelsc_interr_reg : std_logic := '0'; signal sig_coelsc_decerr_reg : std_logic := '0'; signal sig_coelsc_slverr_reg : std_logic := '0'; signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_pop_coelsc_reg : std_logic := '0'; signal sig_push_coelsc_reg : std_logic := '0'; signal sig_coelsc_reg_empty : std_logic := '0'; signal sig_coelsc_reg_full : std_logic := '0'; signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_data_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_data_err_reg : std_logic := '0'; signal sig_data_last_err_reg : std_logic := '0'; signal sig_data_cmd_cmplt_reg : std_logic := '0'; signal sig_bresp_reg : std_logic_vector(1 downto 0) := (others => '0'); signal sig_push_status : std_logic := '0'; Signal sig_status_push_ok : std_logic := '0'; signal sig_status_valid : std_logic := '0'; signal sig_wsc2data_ready : std_logic := '0'; signal sig_s2mm_bready : std_logic := '0'; signal sig_wresp_sfifo_in : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_wresp_sfifo_out : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_wresp_sfifo_wr_valid : std_logic := '0'; signal sig_wresp_sfifo_wr_ready : std_logic := '0'; signal sig_wresp_sfifo_wr_full : std_logic := '0'; signal sig_wresp_sfifo_rd_valid : std_logic := '0'; signal sig_wresp_sfifo_rd_ready : std_logic := '0'; signal sig_wresp_sfifo_rd_empty : std_logic := '0'; signal sig_halt_reg : std_logic := '0'; signal sig_halt_reg_dly1 : std_logic := '0'; signal sig_halt_reg_dly2 : std_logic := '0'; signal sig_halt_reg_dly3 : std_logic := '0'; signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_posted_cntr_eq_0 : std_logic := '0'; signal sig_addr_posted_cntr_eq_1 : std_logic := '0'; signal sig_addr_posted_cntr_max : std_logic := '0'; signal sig_decr_addr_posted_cntr : std_logic := '0'; signal sig_incr_addr_posted_cntr : std_logic := '0'; signal sig_no_posted_cmds : std_logic := '0'; signal sig_addr_posted : std_logic := '0'; signal sig_all_cmds_done : std_logic := '0'; signal sig_wsc2stat_status : std_logic_vector(C_STS_WIDTH-1 downto 0) := (others => '0'); signal sig_dcntl_sfifo_wr_valid : std_logic := '0'; signal sig_dcntl_sfifo_wr_ready : std_logic := '0'; signal sig_dcntl_sfifo_wr_full : std_logic := '0'; signal sig_dcntl_sfifo_rd_valid : std_logic := '0'; signal sig_dcntl_sfifo_rd_ready : std_logic := '0'; signal sig_dcntl_sfifo_rd_empty : std_logic := '0'; signal sig_wdc_statcnt : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0'); signal sig_incr_statcnt : std_logic := '0'; signal sig_decr_statcnt : std_logic := '0'; signal sig_statcnt_eq_max : std_logic := '0'; signal sig_statcnt_eq_0 : std_logic := '0'; signal sig_statcnt_gt_eq_thres : std_logic := '0'; signal sig_wdc_status_going_full : std_logic := '0'; begin --(architecture implementation) -- Assign the ready output to the AXI Write Response Channel s2mm_bready <= sig_s2mm_bready or sig_halt_reg; -- force bready if a Halt is requested -- Assign the ready output to the Data Controller status interface wsc2data_ready <= sig_wsc2data_ready; -- Assign the status valid output control to the Status FIFO wsc2stat_status_valid <= sig_status_valid ; -- Formulate the status output value to the Status FIFO wsc2stat_status <= sig_wsc2stat_status; -- Formulate the status write request signal sig_status_valid <= sig_push_status; -- Indicate the desire to push a coelesced status word -- to the Status FIFO sig_push_status <= sig_coelsc_reg_full; -- Detect that a push of a new status word is completing sig_status_push_ok <= sig_status_valid and stat2wsc_status_ready; sig_pop_coelsc_reg <= sig_status_push_ok; -- Signal a halt to the execution pipe if new status -- is valid but the Status FIFO is not accepting it or -- the WDC Status FIFO is going full wsc2mstr_halt_pipe <= (sig_status_valid and not(stat2wsc_status_ready)) or sig_wdc_status_going_full; -- Monitor the Status capture registers to detect a -- qualified Status set and push to the coelescing register -- when available to do so sig_push_coelsc_reg <= sig_valid_status_rdy and sig_coelsc_reg_empty; -- pre CR616212 sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and -- pre CR616212 sig_dcntl_sfifo_rd_valid) or -- pre CR616212 (sig_data_err_reg and -- pre CR616212 sig_dcntl_sfifo_rd_valid); sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and sig_dcntl_sfifo_rd_valid) or (sig_data_err_reg and sig_dcntl_sfifo_rd_valid) or -- or Added for CR616212 (sig_data_last_err_reg and -- Added for CR616212 sig_dcntl_sfifo_rd_valid); -- Added for CR616212 -- Decode the AXI MMap Read Respose sig_decerr <= '1' When sig_bresp_reg = DECERR Else '0'; sig_slverr <= '1' When sig_bresp_reg = SLVERR Else '0'; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_TAG_LE_STAT -- -- If Generate Description: -- Populates the TAG bits into the availble Status bits when -- the TAG width is less than or equal to the available number -- of bits in the Status word. -- ------------------------------------------------------------ GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate -- local signals signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0'); begin sig_tag2status <= lsig_temp_tag_small; ------------------------------------------------------------- -- Combinational Process -- -- Label: POPULATE_SMALL_TAG -- -- Process Description: -- -- ------------------------------------------------------------- POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg) begin -- Set default value lsig_temp_tag_small <= (others => '0'); -- Now overload actual TAG bits lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_coelsc_tag_reg; end process POPULATE_SMALL_TAG; end generate GEN_TAG_LE_STAT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_TAG_GT_STAT -- -- If Generate Description: -- Populates the TAG bits into the availble Status bits when -- the TAG width is greater than the available number of -- bits in the Status word. The upper bits of the TAG are -- clipped off (discarded). -- ------------------------------------------------------------ GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate -- local signals signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0'); begin sig_tag2status <= lsig_temp_tag_big; ------------------------------------------------------------- -- Combinational Process -- -- Label: POPULATE_BIG_TAG -- -- Process Description: -- -- ------------------------------------------------------------- POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg) begin -- Set default value lsig_temp_tag_big <= (others => '0'); -- Now overload actual TAG bits lsig_temp_tag_big <= sig_coelsc_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0); end process POPULATE_SMALL_TAG; end generate GEN_TAG_GT_STAT; ------------------------------------------------------------------------- -- Write Response Channel input FIFO and logic -- BRESP is the only fifo data sig_wresp_sfifo_in <= s2mm_bresp; -- The fifo output is already in the right format sig_bresp_reg <= sig_wresp_sfifo_out; -- Write Side assignments sig_wresp_sfifo_wr_valid <= s2mm_bvalid; sig_s2mm_bready <= sig_wresp_sfifo_wr_ready; -- read Side ready assignment sig_wresp_sfifo_rd_ready <= sig_push_coelsc_reg; ------------------------------------------------------------ -- Instance: I_WRESP_STATUS_FIFO -- -- Description: -- Instance for the AXI Write Response FIFO -- ------------------------------------------------------------ I_WRESP_STATUS_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo generic map ( C_DWIDTH => WRESP_SFIFO_WIDTH , C_DEPTH => WRESP_SFIFO_DEPTH , C_IS_ASYNC => SYNC_FIFO_SELECT , C_PRIM_TYPE => SRL_FIFO_TYPE , C_FAMILY => C_FAMILY ) port map ( -- Write Clock and reset fifo_wr_reset => mmap_reset , fifo_wr_clk => primary_aclk , -- Write Side fifo_wr_tvalid => sig_wresp_sfifo_wr_valid , fifo_wr_tready => sig_wresp_sfifo_wr_ready , fifo_wr_tdata => sig_wresp_sfifo_in , fifo_wr_full => sig_wresp_sfifo_wr_full , -- Read Clock and reset (not used in Sync mode) fifo_async_rd_reset => mmap_reset , fifo_async_rd_clk => primary_aclk , -- Read Side fifo_rd_tvalid => sig_wresp_sfifo_rd_valid , fifo_rd_tready => sig_wresp_sfifo_rd_ready , fifo_rd_tdata => sig_wresp_sfifo_out , fifo_rd_empty => sig_wresp_sfifo_rd_empty ); -------- Write Data Controller Status FIFO Going Full Logic ------------- sig_incr_statcnt <= sig_dcntl_sfifo_wr_valid and sig_dcntl_sfifo_wr_ready; sig_decr_statcnt <= sig_dcntl_sfifo_rd_valid and sig_dcntl_sfifo_rd_ready; sig_statcnt_eq_max <= '1' when (sig_wdc_statcnt = DCNTL_STATCNT_MAX) Else '0'; sig_statcnt_eq_0 <= '1' when (sig_wdc_statcnt = DCNTL_STATCNT_ZERO) Else '0'; sig_statcnt_gt_eq_thres <= '1' when (sig_wdc_statcnt >= DCNTL_HALT_THRES) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WDC_GOING_FULL_FLOP -- -- Process Description: -- Implements a flop for the WDC Status FIFO going full flag. -- ------------------------------------------------------------- IMP_WDC_GOING_FULL_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_wdc_status_going_full <= '0'; else sig_wdc_status_going_full <= sig_statcnt_gt_eq_thres; end if; end if; end process IMP_WDC_GOING_FULL_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_DCNTL_FIFO_CNTR -- -- Process Description: -- Implements a simple counter keeping track of the number -- of entries in the WDC Status FIFO. If the Status FIFO gets -- too full, the S2MM Data Pipe has to be halted. -- ------------------------------------------------------------- IMP_DCNTL_FIFO_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_wdc_statcnt <= (others => '0'); elsif (sig_incr_statcnt = '1' and sig_decr_statcnt = '0' and sig_statcnt_eq_max = '0') then sig_wdc_statcnt <= sig_wdc_statcnt + DCNTL_STATCNT_ONE; elsif (sig_incr_statcnt = '0' and sig_decr_statcnt = '1' and sig_statcnt_eq_0 = '0') then sig_wdc_statcnt <= sig_wdc_statcnt - DCNTL_STATCNT_ONE; else null; -- Hold current count value end if; end if; end process IMP_DCNTL_FIFO_CNTR; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_OMIT_INDET_BTT -- -- If Generate Description: -- Implements the logic needed when Indeterminate BTT is -- not enabled in the S2MM function. -- ------------------------------------------------------------ GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate -- Local Constants Constant DCNTL_SFIFO_WIDTH : integer := STAT_REG_TAG_WIDTH+3; Constant DCNTL_SFIFO_CMD_CMPLT_INDEX : integer := 0; Constant DCNTL_SFIFO_TLAST_ERR_INDEX : integer := 1; Constant DCNTL_SFIFO_CALC_ERR_INDEX : integer := 2; Constant DCNTL_SFIFO_TAG_INDEX : integer := DCNTL_SFIFO_CALC_ERR_INDEX+1; -- local signals signal sig_dcntl_sfifo_in : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_dcntl_sfifo_out : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0'); begin sig_wsc2stat_status <= sig_coelsc_okay_reg & sig_coelsc_slverr_reg & sig_coelsc_decerr_reg & sig_coelsc_interr_reg & sig_tag2status; ----------------------------------------------------------------------------- -- Data Controller Status FIFO and Logic -- Concatonate Input bits to build Dcntl fifo data word sig_dcntl_sfifo_in <= data2wsc_tag & -- bit 3 to tag Width+2 data2wsc_calc_error & -- bit 2 data2wsc_last_error & -- bit 1 data2wsc_cmd_cmplt ; -- bit 0 -- Rip the DCntl fifo outputs back to constituant pieces sig_data_tag_reg <= sig_dcntl_sfifo_out((DCNTL_SFIFO_TAG_INDEX+STAT_REG_TAG_WIDTH)-1 downto DCNTL_SFIFO_TAG_INDEX); sig_data_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CALC_ERR_INDEX) ; sig_data_last_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_TLAST_ERR_INDEX); sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CMD_CMPLT_INDEX); -- Data Control Valid/Ready assignments sig_dcntl_sfifo_wr_valid <= data2wsc_valid ; sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready; -- read side ready assignment sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg; ------------------------------------------------------------ -- Instance: I_DATA_CNTL_STATUS_FIFO -- -- Description: -- Instance for the Command Qualifier FIFO -- ------------------------------------------------------------ I_DATA_CNTL_STATUS_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo generic map ( C_DWIDTH => DCNTL_SFIFO_WIDTH , C_DEPTH => DCNTL_SFIFO_DEPTH , C_IS_ASYNC => SYNC_FIFO_SELECT , C_PRIM_TYPE => SRL_FIFO_TYPE , C_FAMILY => C_FAMILY ) port map ( -- Write Clock and reset fifo_wr_reset => mmap_reset , fifo_wr_clk => primary_aclk , -- Write Side fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid , fifo_wr_tready => sig_dcntl_sfifo_wr_ready , fifo_wr_tdata => sig_dcntl_sfifo_in , fifo_wr_full => sig_dcntl_sfifo_wr_full , -- Read Clock and reset (not used in Sync mode) fifo_async_rd_reset => mmap_reset , fifo_async_rd_clk => primary_aclk , -- Read Side fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid , fifo_rd_tready => sig_dcntl_sfifo_rd_ready , fifo_rd_tdata => sig_dcntl_sfifo_out , fifo_rd_empty => sig_dcntl_sfifo_rd_empty ); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: STATUS_COELESC_REG -- -- Process Description: -- Implement error status coelescing register. -- Once a bit is set it will remain set until the overall -- status is written to the Status FIFO. -- Tag bits are just registered at each valid dbeat. -- ------------------------------------------------------------- STATUS_COELESC_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_pop_coelsc_reg = '1') then sig_coelsc_tag_reg <= (others => '0'); sig_coelsc_interr_reg <= '0'; sig_coelsc_decerr_reg <= '0'; sig_coelsc_slverr_reg <= '0'; sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY" sig_coelsc_reg_full <= '0'; sig_coelsc_reg_empty <= '1'; Elsif (sig_push_coelsc_reg = '1') Then sig_coelsc_tag_reg <= sig_data_tag_reg; sig_coelsc_interr_reg <= sig_data_err_reg or sig_data_last_err_reg or sig_coelsc_interr_reg; sig_coelsc_decerr_reg <= not(sig_data_err_reg) and (sig_decerr or sig_coelsc_decerr_reg); sig_coelsc_slverr_reg <= not(sig_data_err_reg) and (sig_slverr or sig_coelsc_slverr_reg); sig_coelsc_okay_reg <= not(sig_decerr or sig_coelsc_decerr_reg or sig_slverr or sig_coelsc_slverr_reg or sig_data_err_reg or sig_data_last_err_reg or sig_coelsc_interr_reg ); sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg; sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg); else null; -- hold current state end if; end if; end process STATUS_COELESC_REG; end generate GEN_OMIT_INDET_BTT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ENABLE_INDET_BTT -- -- If Generate Description: -- Implements the logic needed when Indeterminate BTT is -- enabled in the S2MM function. Primary difference is the -- addition to the reported status of the End of Packet -- marker (EOP) and the received byte count for the parent -- command. -- ------------------------------------------------------------ GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate -- Local Constants Constant SF_DCNTL_SFIFO_WIDTH : integer := TAG_WIDTH + C_SF_BYTES_RCVD_WIDTH + 3; Constant SF_SFIFO_LS_TAG_INDEX : integer := 0; Constant SF_SFIFO_MS_TAG_INDEX : integer := SF_SFIFO_LS_TAG_INDEX + (TAG_WIDTH-1); Constant SF_SFIFO_CALC_ERR_INDEX : integer := SF_SFIFO_MS_TAG_INDEX+1; Constant SF_SFIFO_CMD_CMPLT_INDEX : integer := SF_SFIFO_CALC_ERR_INDEX+1; Constant SF_SFIFO_LS_BYTES_RCVD_INDEX : integer := SF_SFIFO_CMD_CMPLT_INDEX+1; Constant SF_SFIFO_MS_BYTES_RCVD_INDEX : integer := SF_SFIFO_LS_BYTES_RCVD_INDEX+ (C_SF_BYTES_RCVD_WIDTH-1); Constant SF_SFIFO_EOP_INDEX : integer := SF_SFIFO_MS_BYTES_RCVD_INDEX+1; Constant BYTES_RCVD_FIELD_WIDTH : integer := 23; -- local signals signal sig_dcntl_sfifo_in : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_dcntl_sfifo_out : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_data_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0'); signal sig_data_eop : std_logic := '0'; signal sig_coelsc_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0'); signal sig_coelsc_eop : std_logic := '0'; signal sig_coelsc_bytes_rcvd_pad : std_logic_vector(BYTES_RCVD_FIELD_WIDTH-1 downto 0) := (others => '0'); begin sig_wsc2stat_status <= sig_coelsc_eop & sig_coelsc_bytes_rcvd_pad & sig_coelsc_okay_reg & sig_coelsc_slverr_reg & sig_coelsc_decerr_reg & sig_coelsc_interr_reg & sig_tag2status; ----------------------------------------------------------------------------- -- Data Controller Status FIFO and Logic -- Concatonate Input bits to build Dcntl fifo input data word sig_dcntl_sfifo_in <= data2wsc_eop & -- ms bit data2wsc_bytes_rcvd & -- bit 7 to C_SF_BYTES_RCVD_WIDTH+7 data2wsc_cmd_cmplt & -- bit 6 data2wsc_calc_error & -- bit 4 data2wsc_tag; -- bits 0 to 3 -- Rip the DCntl fifo outputs back to constituant pieces sig_data_eop <= sig_dcntl_sfifo_out(SF_SFIFO_EOP_INDEX); sig_data_bytes_rcvd <= sig_dcntl_sfifo_out(SF_SFIFO_MS_BYTES_RCVD_INDEX downto SF_SFIFO_LS_BYTES_RCVD_INDEX); sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CMD_CMPLT_INDEX); sig_data_err_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CALC_ERR_INDEX); sig_data_tag_reg <= sig_dcntl_sfifo_out(SF_SFIFO_MS_TAG_INDEX downto SF_SFIFO_LS_TAG_INDEX) ; -- Data Control Valid/Ready assignments sig_dcntl_sfifo_wr_valid <= data2wsc_valid ; sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready; -- read side ready assignment sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg; ------------------------------------------------------------ -- Instance: I_SF_DATA_CNTL_STATUS_FIFO -- -- Description: -- Instance for the Command Qualifier FIFO when Store and -- Forward is included. -- ------------------------------------------------------------ I_SF_DATA_CNTL_STATUS_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo generic map ( C_DWIDTH => SF_DCNTL_SFIFO_WIDTH , C_DEPTH => DCNTL_SFIFO_DEPTH , C_IS_ASYNC => SYNC_FIFO_SELECT , C_PRIM_TYPE => SRL_FIFO_TYPE , C_FAMILY => C_FAMILY ) port map ( -- Write Clock and reset fifo_wr_reset => mmap_reset , fifo_wr_clk => primary_aclk , -- Write Side fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid , fifo_wr_tready => sig_dcntl_sfifo_wr_ready , fifo_wr_tdata => sig_dcntl_sfifo_in , fifo_wr_full => sig_dcntl_sfifo_wr_full , -- Read Clock and reset (not used in Sync mode) fifo_async_rd_reset => mmap_reset , fifo_async_rd_clk => primary_aclk , -- Read Side fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid , fifo_rd_tready => sig_dcntl_sfifo_rd_ready , fifo_rd_tdata => sig_dcntl_sfifo_out , fifo_rd_empty => sig_dcntl_sfifo_rd_empty ); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SF_STATUS_COELESC_REG -- -- Process Description: -- Implement error status coelescing register. -- Once a bit is set it will remain set until the overall -- status is written to the Status FIFO. -- Tag bits are just registered at each valid dbeat. -- ------------------------------------------------------------- SF_STATUS_COELESC_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_pop_coelsc_reg = '1') then sig_coelsc_tag_reg <= (others => '0'); sig_coelsc_interr_reg <= '0'; sig_coelsc_decerr_reg <= '0'; sig_coelsc_slverr_reg <= '0'; sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY" sig_coelsc_bytes_rcvd <= (others => '0'); sig_coelsc_eop <= '0'; sig_coelsc_reg_full <= '0'; sig_coelsc_reg_empty <= '1'; Elsif (sig_push_coelsc_reg = '1') Then sig_coelsc_tag_reg <= sig_data_tag_reg; sig_coelsc_interr_reg <= sig_data_err_reg or sig_coelsc_interr_reg; sig_coelsc_decerr_reg <= not(sig_data_err_reg) and (sig_decerr or sig_coelsc_decerr_reg); sig_coelsc_slverr_reg <= not(sig_data_err_reg) and (sig_slverr or sig_coelsc_slverr_reg); sig_coelsc_okay_reg <= not(sig_decerr or sig_coelsc_decerr_reg or sig_slverr or sig_coelsc_slverr_reg or sig_data_err_reg or sig_coelsc_interr_reg ); sig_coelsc_bytes_rcvd <= sig_data_bytes_rcvd; sig_coelsc_eop <= sig_data_eop; sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg; sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg); else null; -- hold current state end if; end if; end process SF_STATUS_COELESC_REG; ------------------------------------------------------------ -- If Generate -- -- Label: SF_GEN_PAD_BYTES_RCVD -- -- If Generate Description: -- Pad the bytes received value with zeros to fill in the -- status field width. -- -- ------------------------------------------------------------ SF_GEN_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH < BYTES_RCVD_FIELD_WIDTH) generate begin sig_coelsc_bytes_rcvd_pad(BYTES_RCVD_FIELD_WIDTH-1 downto C_SF_BYTES_RCVD_WIDTH) <= (others => '0'); sig_coelsc_bytes_rcvd_pad(C_SF_BYTES_RCVD_WIDTH-1 downto 0) <= sig_coelsc_bytes_rcvd; end generate SF_GEN_PAD_BYTES_RCVD; ------------------------------------------------------------ -- If Generate -- -- Label: SF_GEN_NO_PAD_BYTES_RCVD -- -- If Generate Description: -- No padding required for the bytes received value. -- -- ------------------------------------------------------------ SF_GEN_NO_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH = BYTES_RCVD_FIELD_WIDTH) generate begin sig_coelsc_bytes_rcvd_pad <= sig_coelsc_bytes_rcvd; -- no pad required end generate SF_GEN_NO_PAD_BYTES_RCVD; end generate GEN_ENABLE_INDET_BTT; ------- Soft Shutdown Logic ------------------------------- -- Address Posted Counter Logic ---------------------t----------------- -- Supports soft shutdown by tracking when all commited Write -- transfers to the AXI Bus have had corresponding Write Status -- Reponses Received. sig_addr_posted <= addr2wsc_addr_posted ; sig_incr_addr_posted_cntr <= sig_addr_posted ; sig_decr_addr_posted_cntr <= sig_s2mm_bready and s2mm_bvalid ; sig_addr_posted_cntr_eq_0 <= '1' when (sig_addr_posted_cntr = ADDR_POSTED_ZERO) Else '0'; sig_addr_posted_cntr_eq_1 <= '1' when (sig_addr_posted_cntr = ADDR_POSTED_ONE) Else '0'; sig_addr_posted_cntr_max <= '1' when (sig_addr_posted_cntr = ADDR_POSTED_MAX) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_ADDR_POSTED_FIFO_CNTR -- -- Process Description: -- This process implements a counter for the tracking -- if an Address has been posted on the AXI address channel. -- The counter is used to track flushing operations where all -- transfers committed on the AXI Address Channel have to -- be completed before a halt can occur. ------------------------------------------------------------- IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_addr_posted_cntr <= ADDR_POSTED_ZERO; elsif (sig_incr_addr_posted_cntr = '1' and sig_decr_addr_posted_cntr = '0' and sig_addr_posted_cntr_max = '0') then sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ; elsif (sig_incr_addr_posted_cntr = '0' and sig_decr_addr_posted_cntr = '1' and sig_addr_posted_cntr_eq_0 = '0') then sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ; else null; -- don't change state end if; end if; end process IMP_ADDR_POSTED_FIFO_CNTR; wsc2rst_stop_cmplt <= sig_all_cmds_done; sig_no_posted_cmds <= (sig_addr_posted_cntr_eq_0 and not(addr2wsc_calc_error)) or (sig_addr_posted_cntr_eq_1 and addr2wsc_calc_error); sig_all_cmds_done <= sig_no_posted_cmds and sig_halt_reg_dly3; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_HALT_REQ_REG -- -- Process Description: -- Implements the flop for capturing the Halt request from -- the Reset module. -- ------------------------------------------------------------- IMP_HALT_REQ_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_halt_reg <= '0'; elsif (rst2wsc_stop_request = '1') then sig_halt_reg <= '1'; else null; -- Hold current State end if; end if; end process IMP_HALT_REQ_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_HALT_REQ_REG_DLY -- -- Process Description: -- Implements the flops for delaying the halt request by 3 -- clocks to allow the Address Controller to halt before the -- Data Contoller can safely indicate it has exhausted all -- transfers committed to the AXI Address Channel by the Address -- Controller. -- ------------------------------------------------------------- IMP_HALT_REQ_REG_DLY : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_halt_reg_dly1 <= '0'; sig_halt_reg_dly2 <= '0'; sig_halt_reg_dly3 <= '0'; else sig_halt_reg_dly1 <= sig_halt_reg; sig_halt_reg_dly2 <= sig_halt_reg_dly1; sig_halt_reg_dly3 <= sig_halt_reg_dly2; end if; end if; end process IMP_HALT_REQ_REG_DLY; end implementation;
-- ------------------------------------------------------------- -- -- Entity Declaration for inst_ok_2_e -- -- Generated -- by: wig -- on: Fri Jul 15 13:54:30 2005 -- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_ok_2_e-e.vhd,v 1.2 2005/07/15 16:20:00 wig Exp $ -- $Date: 2005/07/15 16:20:00 $ -- $Log: inst_ok_2_e-e.vhd,v $ -- Revision 1.2 2005/07/15 16:20:00 wig -- Update all testcases; still problems though -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.36 , [email protected] -- (C) 2003 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/enty -- -- -- Start of Generated Entity inst_ok_2_e -- entity inst_ok_2_e is -- Generics: -- No Generated Generics for Entity inst_ok_2_e -- Generated Port Declaration: -- No Generated Port for Entity inst_ok_2_e end inst_ok_2_e; -- -- End of Generated Entity inst_ok_2_e -- -- --!End of Entity/ies -- --------------------------------------------------------------
----------------------------------------------------------------------------------------------------------------------- -- Author: Jonny Doin, [email protected], [email protected] -- -- Create Date: 09:56:30 07/06/2011 -- Module Name: grp_debouncer - RTL -- Project Name: basic functions -- Target Devices: Spartan-6 -- Tool versions: ISE 13.1 -- Description: -- -- This block is a generic multiple input debouncing circuit. -- It handles multiple inputs, like mechanical switch inputs, and outputs a debounced, stable registered version of the inputs. -- A 'new_data' one-cycle strobe is also available, to sync downstream logic. -- -- CONCEPTUAL CIRCUIT -- ================== -- -- W -- /----------------/----------------\ -- \| \| -- \| \| -- \| ______ ______ \| _____ -- \| W \| \| W \|fdr \| W \| W \|cmp \ -- \----/---\| +1 \|---/----\| \|--/--+----/----\| \ -- \| \| \| \| \| \ -- ------ \| \| \ \| -- \| \| \| = \|-----\ -- \|> R \| / \| \| -- ---+-- \| / \| -- \| CNT_VAL---\| / \| -- \| \|____/ \| -- \| \| -- \------------\ \| -- \| \| -- N ____ \| \| -- /-------/---)) \ ____ \| \| -- \| ))XOR \|-----) \ \| \| -- \| /------))___/ )OR \|-----/ \| -- \| \| /---)___/ \| -- \| \| \| \| -- \| \| \----------\ \| -- \| \| N \| \| -- \| \--------/-----------\ +----------------------+---------\ -- \| \| \| \| -- \---\ \| \| \| -- ______ \| ______ \| \| ______ \| -- \| fd \| \| \| fd \| \| \| \|fde \| \| -- [data_i]----/-----\| \|---/---+---/----\| \|---/---+----)---\| \|---/---+---/-----------)------------------------[data_o] -- N \| \| N N \| \| N \| \| \| \| N \| N \| -- \| \| \| \| \| \---\|CE \| \| \| -- \| \| \| \| \| \| \| \| \| -- [clk_i]----> \|> \| \|> \| \| \|> \| \| \| ____ ______ -- ------ ------ \| ------ \| N ____ \---\| \ \| fd \| -- \| \---/---)) \ \|AND \|-----\| \|----[strb_o] -- \| ))XOR \|-----\|___/ \| \| -- \-------------------------/---))___/ \| \| -- N \| \| -- \|> \| -- ------ -- -- -- PIPELINE LOGIC -- ============== -- -- This debouncer circuit detects edges in an input signal, and waits the signal to stabilize for the designated time -- before transferring the stable signal to the registered output. -- A one-clock-cyle strobe is pulsed at the output to signalize a new data available. -- The core clock should be the system clock, to optimize use of global clock resources. -- -- GROUP DEBOUNCING -- ================ -- -- A change in state in any bit in the input word causes reload of the delay counter, and the output word is updated only -- when all bits are stable for the specified period. Therefore, the grouping of signals and delay selection should match -- behaviour of the selected signals. -- -- RESOURCES USED -- ============== -- -- The number of registers inferred is: 3N + (LOG(CNT_VAL)/LOG(2)) + 1 registers. -- The number of LUTs inferred is roughly: ((4N+2)/6)+2. -- The slice distribution will vary, and depends on the control set restrictions and LUT-FF pairs resulting from map+p&r. -- -- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints. -- Verification in silicon was done on a Digilent Atlys board with a Spartan-6 FPGA @100MHz clock. -- The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools. -- ------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- -- -- -- Author(s): Jonny Doin, [email protected], [email protected] -- -- Copyright (C) 2011 Jonny Doin -- ----------------------------- -- -- This source file may be used and distributed without restriction provided that this copyright statement is not -- removed from the file and that any derivative work contains the original copyright notice and the associated -- disclaimer. -- -- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser -- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or -- (at your option) any later version. -- -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied -- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more -- details. -- -- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download -- it from http://www.gnu.org/licenses/lgpl.txt -- ------------------------------ REVISION HISTORY ----------------------------------------------------------------------- -- -- 2011/07/06 v0.01.0010 [JD] started development. verification of synthesis circuit inference. -- 2011/07/07 v1.00.0020 [JD] verification in silicon. operation at 100MHz, tested on the Atlys board (Spartan-6 LX45). -- 2011/08/10 v1.01.0025 [JD] added one pipeline delay to new data strobe output. -- 2011/09/19 v1.01.0030 [JD] changed range for internal counter (cnt_reg, cnt_next) to avoid adder flipover (Altera/ModelSim). -- ----------------------------------------------------------------------------------------------------------------------- -- TODO -- ==== -- -- The circuit can easily be extended to have a signature of which inputs changed at the data out port. -- ----------------------------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity GRP_DEBOUNCER is generic ( N : positive := 8; -- input bus width CNT_VAL : positive := 10000 -- clock counts for debounce period ); port ( CLK_I : in std_logic := 'X'; -- system clock DATA_I : in std_logic_vector(N - 1 downto 0) := (others => 'X'); -- noisy input data DATA_O : out std_logic_vector(N - 1 downto 0); -- registered stable output data STRB_O : out std_logic -- strobe for new data available ); end entity GRP_DEBOUNCER; architecture RTL of GRP_DEBOUNCER is -- datapath pipeline signal reg_a, reg_b : std_logic_vector(N - 1 downto 0) := (others => '0'); -- debounce edge detectors signal reg_out : std_logic_vector(N - 1 downto 0) := (others => '0'); -- registered output signal dat_strb : std_logic := '0'; -- data transfer strobe signal strb_reg : std_logic := '0'; -- registered strobe signal strb_next : std_logic := '0'; -- lookahead strobe signal dat_diff : std_logic := '0'; -- edge detector -- debounce counter signal cnt_reg : integer range CNT_VAL + 1 downto 0 := 0; -- debounce period counter signal cnt_next : integer range CNT_VAL + 1 downto 0 := 0; -- combinatorial signal begin --============================================================================================= -- DEBOUNCE COUNTER LOGIC --============================================================================================= -- This counter is implemented as a up-counter with reset and final count detection via compare, -- instead of a down-counter with preset and final count detection via nonzero detection. -- This is better for Spartan-6 and Virtex-6 CLB architecture, because it uses less control sets. -- -- cnt_reg register transfer logic CNT_REG_PROC : process (CLK_I) is begin if (CLK_I'event and CLK_I = '1') then cnt_reg <= cnt_next; end if; end process CNT_REG_PROC; -- cnt_next combinatorial logic cnt_next <= 0 when dat_diff = '1' or dat_strb = '1' else cnt_reg + 1; -- final count combinatorial logic dat_strb <= '1' when cnt_reg = CNT_VAL else '0'; --============================================================================================= -- DATAPATH SIGNAL PIPELINE --============================================================================================= -- input pipeline logic PIPELINE_PROC : process (CLK_I) is begin if (CLK_I'event and CLK_I = '1') then -- edge detection pipeline reg_a <= DATA_I; reg_b <= reg_a; -- new data strobe pipeline delay strb_reg <= strb_next; end if; -- output data pipeline if (CLK_I'event and CLK_I = '1') then if (dat_strb = '1') then reg_out <= reg_b; end if; end if; end process PIPELINE_PROC; -- edge detector dat_diff <= '1' when reg_a /= reg_b else '0'; -- lookahead new data strobe strb_next <= '1' when ((reg_out /= reg_b) and dat_strb = '1') else '0'; --============================================================================================= -- OUTPUT LOGIC --============================================================================================= -- connect output ports DATA_O <= reg_out; STRB_O <= strb_reg; end architecture RTL;
-------------------------------------------------------------------------------- -- -- Title : ctrl_leds.vhd -- Design : Example -- Author : Kapitanov -- Company : InSys -- -- Version : 1.0 -------------------------------------------------------------------------------- -- -- Description : Controller LEDs 8x8 -- -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity ctrl_leds is port( -- system signals: clk : in std_logic; --! clock clk_dv : in std_logic; --! clock/2 reset : in std_logic; --! system reset pwm_ena : in std_logic; --! enable PWM -- buttons: cbut : in std_logic_vector(5 downto 1); --! buttons -- leds vectors: led_x : out std_logic_vector(7 downto 0); --! LED X led_y : out std_logic_vector(7 downto 0) --! LED y ); end ctrl_leds; architecture ctrl_leds of ctrl_leds is component ctrl_led8x8_heart is port ( clk : in std_logic; -- Clock rst : in std_logic; -- Reset rst_reg : in std_logic; -- Count reset ch_freq : in std_logic; -- Change frequency led_y : out std_logic_vector(7 downto 0); -- LED Y led_x : out std_logic_vector(7 downto 0) -- LED X ); end component; component ctrl_pwm is port ( clk : in std_logic; -- Clock rst : in std_logic; -- Reset rst_reg : in std_logic; -- Count reset zoom_reg : in std_logic; -- Switch change zoom_cnt : in std_logic; -- Switch counter log_led : out std_logic -- Pulsed LED enable ); end component; component ctrl_jazz is port( clk : in std_logic; -- Clock button : in std_logic; -- Button in reset : in std_logic; -- Reset clrbutton : out std_logic -- Button out ); end component; signal clbutton : std_logic_vector(5 downto 1); signal log_led : std_logic; signal log_hearty : std_logic_vector(7 downto 0); signal log_heartx : std_logic_vector(7 downto 0); begin x_GEN_LEDX : for ii in 0 to 7 generate led_x(ii) <= log_led or log_heartx(ii) when pwm_ena = '0' else log_heartx(ii); end generate; x_GEN_LEDY : for ii in 0 to 7 generate led_y(ii) <= (log_led or log_hearty(ii)) when pwm_ena = '0' else log_hearty(ii); end generate; ---------------- PULSE-WITDH MODULO ---------------- xCTRL_PWM : ctrl_pwm port map ( clk => clk_dv, rst => reset, rst_reg => clbutton(1), zoom_reg => clbutton(2), zoom_cnt => clbutton(3), log_led => log_led ); ---------------- CTRL MATRIX 8X8 ---------------- xCTRL_LED : ctrl_led8x8_heart port map ( clk => clk_dv, rst => reset, rst_reg => clbutton(1), ch_freq => clbutton(2), led_y => log_hearty, led_x => log_heartx ); ---------------- DEBOUNCE ---------------- xDEBOUNCE: for ii in 1 to 5 generate x_buttons: ctrl_jazz port map ( clk => clk, button => cbut(ii), reset => reset, clrbutton => clbutton(ii) ); end generate; end ctrl_leds;
-- $Id: sys_w11a_n3.vhd 1181 2019-07-08 17:00:50Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2011-2019 by Walter F.J. Mueller <[email protected]> -- ------------------------------------------------------------------------------ -- Module Name: sys_w11a_n3 - syn -- Description: w11a test design for nexys3 -- -- Dependencies: vlib/xlib/s6_cmt_sfs -- vlib/genlib/clkdivce -- bplib/bpgen/bp_rs232_2l4l_iob -- bplib/fx2rlink/rlink_sp1c_fx2 -- w11a/pdp11_sys70 -- ibus/ibdr_maxisys -- bplib/nxcramlib/nx_cram_memctl_as -- bplib/fx2rlink/ioleds_sp1c_fx2 -- w11a/pdp11_hio70 -- bplib/bpgen/sn_humanio_rbus -- vlib/rbus/rb_sres_or_2 -- -- Test bench: tb/tb_sys_w11a_n3 -- -- Target Devices: generic -- Tool versions: xst 13.1-14.7; ghdl 0.29-0.35 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri -- 2019-05-19 1150 14.7 131013 xc6slx16-2 3167 6052 248 2130 ok: +dz11 93% -- 2019-05-01 1143 14.7 131013 xc6slx16-2 3062 5761 232 2057 ok: +m9312 90% -- 2019-04-27 1140 14.7 131013 xc6slx16-2 3053 5742 232 2050 ok: +dlbuf 89% -- 2019-04-24 1137 14.7 131013 xc6slx16-2 3049 5727 223 2045 ok: +pcbuf 89% -- 2019-03-17 1123 14.7 131013 xc6slx16-2 3059 5722 212 2041 ok: +lpbuf 89% -- 2019-03-02 1116 14.7 131013 xc6slx16-2 3048 5741 212 2030 ok: +ibtst 89% -- 2019-01-27 1108 14.7 131013 xc6slx16-2 2979 5542 201 2018 ok: -iist 88% -- 2018-10-13 1055 14.7 131013 xc6slx16-2 3057 5822 201 2064 ok: +dmpcnt 90% -- 2018-09-15 1045 14.7 131013 xc6slx16-2 2851 5453 177 1932 ok: +KW11P 84% -- 2017-03-30 888 14.7 131013 xc6slx16-2 2790 5352 177 1943 ok: +fx2dbg 85% -- 2017-03-04 858 14.7 131013 xc6slx16-2 2717 5273 177 1885 ok: +deuna 82% -- 2017-01-29 846 14.7 131013 xc6slx16-2 2680 5208 177 1860 ok: +int24 81% -- 2015-07-05 698 14.7 131013 xc6slx16-2 2500 4852 161 1782 ok: +dmhbpt 78% -- 2015-07-05 697 14.7 131013 xc6slx16-2 2428 4786 161 1756 ok: +dmcmon 77% -- 2015-06-27 695 14.7 131013 xc6slx16-2 2281 4638 161 1714 ok: +dmscnt 75% -- 2015-06-21 692 14.7 131013 xc6slx16-2 2192 4518 161 1584 ok: rhrp fixes -- 2015-06-04 686 14.7 131013 xc6slx16-2 2189 4492 161 1543 ok: +TM11 67% -- 2015-05-14 680 14.7 131013 xc6slx16-2 2120 4443 161 1546 ok: +ibmon 67% -- 2015-04-06 664 14.7 131013 xc6slx16-2 1991 4350 167 1489 ok: +RHRP 65% -- 2015-02-21 649 14.7 131013 xc6slx16-2 1819 3905 160 1380 ok: +RL11 61% -- 2014-12-22 619 14.7 131013 xc6slx16-2 1742 3767 150 1350 ok: +rbmon -- 2014-12-20 614 14.7 131013 xc6slx16-2 1640 3692 150 1297 ok: -RL11,rlv4 -- 2014-06-08 561 14.7 131013 xc6slx16-2 1531 3500 142 1165 ok: +RL11 -- 2014-05-29 556 14.7 131013 xc6slx16-2 1459 3342 128 1154 ok: 51% -- 2013-04-21 509 13.3 O76d xc6slx16-2 1516 3274 140 1184 ok: now + FX2 ! -- 2011-12-18 440 13.1 O40d xc6slx16-2 1441 3161 96 1084 ok: LP+PC+DL+II -- 2011-11-20 430 13.1 O40d xc6slx16-2 1412 3206 84 1063 ok: LP+PC+DL+II -- -- Revision History: -- Date Rev Version Comment -- 2018-10-13 1055 2.3 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT -- 2017-04-30 888 2.2 use SWI(7:6) to allow fx2 debug via LEDs -- 2016-03-19 748 2.1.1 define rlink SYSID -- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul -- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70 -- 2015-04-24 668 1.8.3 added ibd_ibmon -- 2015-04-11 666 1.8.2 rearrange XON handling -- 2015-02-21 649 1.8.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux) -- 2015-02-15 647 1.8 drop bram and minisys options -- 2014-12-24 620 1.7.2 relocate ibus window and hio rbus address -- 2014-12-22 619 1.7.1 add rbus monitor rbd_rbmon -- 2014-08-28 588 1.7 use new rlink v4 iface generics and 4 bit STAT -- 2014-08-15 583 1.6 rb_mreq addr now 16 bit -- 2013-10-06 538 1.5 pll support, use clksys_vcodivide ect -- 2013-04-21 509 1.4 added fx2 (cuff) support -- 2011-12-18 440 1.0.4 use rlink_sp1c -- 2011-12-04 435 1.0.3 increase ATOWIDTH 6->7 (saw i/o timeouts on wblks) -- 2011-11-26 433 1.0.2 use nx_cram_(dummy\|memctl_as) now -- 2011-11-23 432 1.0.1 fixup PPCM handling -- 2011-11-20 430 1.0 Initial version (derived from sys_w11a_n2) ------------------------------------------------------------------------------ -- -- w11a test design for nexys3 -- w11a + rlink + serport -- -- Usage of Nexys 3 Switches, Buttons, LEDs: -- -- SWI(7:6): select LED display mode -- 0x w11 sys70 LED display (further controlled by SWI(3)) -- 10 FX2 debug: fx2 fifo states -- 11 FX2 debug: fx2 fsm states -- (5:4): select DSP -- 00 abclkdiv & abclkdiv_f -- 01 PC -- 10 DISPREG -- 11 DR emulation -- (3): select LED display -- 0 overall status -- 1 DR emulation -- (2) 0 -> int/ext RS242 port for rlink -- 1 -> use USB interface for rlink -- (1): 1 enable XON -- (0): 0 -> main board RS232 port -- 1 -> Pmod B/top RS232 port -- -- LEDs if SWI(7) = 0 and SWI(3) = 1 -- (7:0) DR emulation; shows R0(lower 8 bits) during wait like 11/45+70 -- -- LEDs if SWI(7) = 0 and SWI(3) = 0 -- (7) MEM_ACT_W -- (6) MEM_ACT_R -- (5) cmdbusy (all rlink access, mostly rdma) -- (4:0) if cpugo=1 show cpu mode activity -- (4) kernel mode, pri>0 -- (3) kernel mode, pri=0 -- (2) kernel mode, wait -- (1) supervisor mode -- (0) user mode -- if cpugo=0 shows cpurust -- (4) '1' -- (3:0) cpurust code -- -- LEDs if SWI(7) = 1 -- (7) fifo_ep4 -- (6) fifo_ep6 -- (5) fsm_rx -- (4) fsm_tx -- LEDs if SWI(7) = 1 and SWI(6) = 0 -- (3) flag_ep4_empty -- (2) flag_ep4_almost -- (1) flag_ep6_full -- (0) flag_ep6_almost -- LEDs if SWI(7) = 1 and SWI(6) = 1 -- (3) fsm_idle -- (2) fsm_prep -- (1) fsm_disp -- (0) fsm_pipe -- -- DP(3:0) shows IO activity -- if SWI(2)=0 (serport) -- (3): not SER_MONI.txok (shows tx back pressure) -- (2): SER_MONI.txact (shows tx activity) -- (1): not SER_MONI.rxok (shows rx back pressure) -- (0): SER_MONI.rxact (shows rx activity) -- if SWI(2)=1 (fx2-usb) -- (3): RB_SRES.busy (shows rbus back pressure) -- (2): RLB_TXBUSY (shows tx back pressure) -- (1): RLB_TXENA (shows tx activity) -- (0): RLB_RXVAL (shows rx activity) -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; use work.xlib.all; use work.genlib.all; use work.serportlib.all; use work.rblib.all; use work.rlinklib.all; use work.fx2lib.all; use work.fx2rlinklib.all; use work.bpgenlib.all; use work.bpgenrbuslib.all; use work.nxcramlib.all; use work.iblib.all; use work.ibdlib.all; use work.pdp11.all; use work.sys_conf.all; -- ---------------------------------------------------------------------------- entity sys_w11a_n3 is -- top level -- implements nexys3_fusp_cuff_aif port ( I_CLK100 : in slbit; -- 100 MHz clock I_RXD : in slbit; -- receive data (board view) O_TXD : out slbit; -- transmit data (board view) I_SWI : in slv8; -- n3 switches I_BTN : in slv5; -- n3 buttons O_LED : out slv8; -- n3 leds O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) O_MEM_WE_N : out slbit; -- cram: write enable (act.low) O_MEM_OE_N : out slbit; -- cram: output enable (act.low) O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) O_MEM_CLK : out slbit; -- cram: clock O_MEM_CRE : out slbit; -- cram: command register enable I_MEM_WAIT : in slbit; -- cram: mem wait O_MEM_ADDR : out slv23; -- cram: address lines IO_MEM_DATA : inout slv16; -- cram: data lines O_PPCM_CE_N : out slbit; -- ppcm: ... O_PPCM_RST_N : out slbit; -- ppcm: ... O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n I_FUSP_RXD : in slbit; -- fusp: rs232 rx O_FUSP_TXD : out slbit; -- fusp: rs232 tx I_FX2_IFCLK : in slbit; -- fx2: interface clock O_FX2_FIFO : out slv2; -- fx2: fifo address I_FX2_FLAG : in slv4; -- fx2: fifo flags O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) IO_FX2_DATA : inout slv8 -- fx2: data lines ); end sys_w11a_n3; architecture syn of sys_w11a_n3 is signal CLK : slbit := '0'; signal RESET : slbit := '0'; signal CE_USEC : slbit := '0'; signal CE_MSEC : slbit := '0'; signal RXD : slbit := '1'; signal TXD : slbit := '0'; signal RTS_N : slbit := '0'; signal CTS_N : slbit := '0'; signal RB_MREQ : rb_mreq_type := rb_mreq_init; signal RB_SRES : rb_sres_type := rb_sres_init; signal RB_SRES_CPU : rb_sres_type := rb_sres_init; signal RB_SRES_HIO : rb_sres_type := rb_sres_init; signal RB_LAM : slv16 := (others=>'0'); signal RB_STAT : slv4 := (others=>'0'); signal RLB_MONI : rlb_moni_type := rlb_moni_init; signal SER_MONI : serport_moni_type := serport_moni_init; signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init; signal GRESET : slbit := '0'; -- general reset (from rbus) signal CRESET : slbit := '0'; -- cpu reset (from cp) signal BRESET : slbit := '0'; -- bus reset (from cp or cpu) signal PERFEXT : slv8 := (others=>'0'); signal EI_PRI : slv3 := (others=>'0'); signal EI_VECT : slv9_2 := (others=>'0'); signal EI_ACKM : slbit := '0'; signal CP_STAT : cp_stat_type := cp_stat_init; signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init; signal MEM_REQ : slbit := '0'; signal MEM_WE : slbit := '0'; signal MEM_BUSY : slbit := '0'; signal MEM_ACK_R : slbit := '0'; signal MEM_ACT_R : slbit := '0'; signal MEM_ACT_W : slbit := '0'; signal MEM_ADDR : slv20 := (others=>'0'); signal MEM_BE : slv4 := (others=>'0'); signal MEM_DI : slv32 := (others=>'0'); signal MEM_DO : slv32 := (others=>'0'); signal MEM_ADDR_EXT : slv22 := (others=>'0'); signal IB_MREQ : ib_mreq_type := ib_mreq_init; signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; signal DISPREG : slv16 := (others=>'0'); signal ABCLKDIV : slv16 := (others=>'0'); signal LED70 : slv8 := (others=>'0'); signal SWI : slv8 := (others=>'0'); signal BTN : slv5 := (others=>'0'); signal LED : slv8 := (others=>'0'); signal DSP_DAT : slv16 := (others=>'0'); signal DSP_DP : slv4 := (others=>'0'); constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx constant sysid_proj : slv16 := x"0201"; -- w11a constant sysid_board : slv8 := x"03"; -- nexys3 constant sysid_vers : slv8 := x"00"; begin assert (sys_conf_clksys mod 1000000) = 0 report "assert sys_conf_clksys on MHz grid" severity failure; GEN_CLKSYS : s6_cmt_sfs -- clock generator ------------------- generic map ( VCO_DIVIDE => sys_conf_clksys_vcodivide, VCO_MULTIPLY => sys_conf_clksys_vcomultiply, OUT_DIVIDE => sys_conf_clksys_outdivide, CLKIN_PERIOD => 10.0, CLKIN_JITTER => 0.01, STARTUP_WAIT => false, GEN_TYPE => sys_conf_clksys_gentype) port map ( CLKIN => I_CLK100, CLKFX => CLK, LOCKED => open ); CLKDIV : clkdivce -- usec/msec clock divider ----------- generic map ( CDUWIDTH => 7, USECDIV => sys_conf_clksys_mhz, MSECDIV => 1000) port map ( CLK => CLK, CE_USEC => CE_USEC, CE_MSEC => CE_MSEC ); IOB_RS232 : bp_rs232_2l4l_iob -- serport iob/switch ---------------- port map ( CLK => CLK, RESET => '0', SEL => SWI(0), RXD => RXD, TXD => TXD, CTS_N => CTS_N, RTS_N => RTS_N, I_RXD0 => I_RXD, O_TXD0 => O_TXD, I_RXD1 => I_FUSP_RXD, O_TXD1 => O_FUSP_TXD, I_CTS1_N => I_FUSP_CTS_N, O_RTS1_N => O_FUSP_RTS_N ); RLINK : rlink_sp1c_fx2 -- rlink for serport + fx2 ----------- generic map ( BTOWIDTH => 7, -- 128 cycles access timeout RTAWIDTH => 12, SYSID => (others=>'0'), IFAWIDTH => 5, -- 32 word input fifo OFAWIDTH => 5, -- 32 word output fifo PETOWIDTH => sys_conf_fx2_petowidth, CCWIDTH => sys_conf_fx2_ccwidth, ENAPIN_RLMON => sbcntl_sbf_rlmon, ENAPIN_RBMON => sbcntl_sbf_rbmon, CDWIDTH => 13, CDINIT => sys_conf_ser2rri_cdinit, RBMON_AWIDTH => sys_conf_rbmon_awidth, RBMON_RBADDR => rbaddr_rbmon) port map ( CLK => CLK, CE_USEC => CE_USEC, CE_MSEC => CE_MSEC, CE_INT => CE_MSEC, RESET => RESET, ENAXON => SWI(1), ENAFX2 => SWI(2), RXSD => RXD, TXSD => TXD, CTS_N => CTS_N, RTS_N => RTS_N, RB_MREQ => RB_MREQ, RB_SRES => RB_SRES, RB_LAM => RB_LAM, RB_STAT => RB_STAT, RL_MONI => open, RLB_MONI => RLB_MONI, SER_MONI => SER_MONI, FX2_MONI => FX2_MONI, I_FX2_IFCLK => I_FX2_IFCLK, O_FX2_FIFO => O_FX2_FIFO, I_FX2_FLAG => I_FX2_FLAG, O_FX2_SLRD_N => O_FX2_SLRD_N, O_FX2_SLWR_N => O_FX2_SLWR_N, O_FX2_SLOE_N => O_FX2_SLOE_N, O_FX2_PKTEND_N => O_FX2_PKTEND_N, IO_FX2_DATA => IO_FX2_DATA ); PERFEXT(0) <= '0'; -- unused (ext_rdrhit) PERFEXT(1) <= '0'; -- unused (ext_wrrhit) PERFEXT(2) <= '0'; -- unused (ext_wrflush) PERFEXT(3) <= RLB_MONI.rxval and not RLB_MONI.rxhold; -- ext_rlrxact PERFEXT(4) <= RLB_MONI.rxhold; -- ext_rlrxback PERFEXT(5) <= RLB_MONI.txena and not RLB_MONI.txbusy; -- ext_rltxact PERFEXT(6) <= RLB_MONI.txbusy; -- ext_rltxback PERFEXT(7) <= CE_USEC; -- ext_usec SYS70 : pdp11_sys70 -- 1 cpu system ---------------------- port map ( CLK => CLK, RESET => RESET, RB_MREQ => RB_MREQ, RB_SRES => RB_SRES_CPU, RB_STAT => RB_STAT, RB_LAM_CPU => RB_LAM(0), GRESET => GRESET, CRESET => CRESET, BRESET => BRESET, CP_STAT => CP_STAT, EI_PRI => EI_PRI, EI_VECT => EI_VECT, EI_ACKM => EI_ACKM, PERFEXT => PERFEXT, IB_MREQ => IB_MREQ, IB_SRES => IB_SRES_IBDR, MEM_REQ => MEM_REQ, MEM_WE => MEM_WE, MEM_BUSY => MEM_BUSY, MEM_ACK_R => MEM_ACK_R, MEM_ADDR => MEM_ADDR, MEM_BE => MEM_BE, MEM_DI => MEM_DI, MEM_DO => MEM_DO, DM_STAT_EXP => DM_STAT_EXP ); IBDR_SYS : ibdr_maxisys -- IO system ------------------------- port map ( CLK => CLK, CE_USEC => CE_USEC, CE_MSEC => CE_MSEC, RESET => GRESET, BRESET => BRESET, ITIMER => DM_STAT_EXP.se_itimer, IDEC => DM_STAT_EXP.se_idec, CPUSUSP => CP_STAT.cpususp, RB_LAM => RB_LAM(15 downto 1), IB_MREQ => IB_MREQ, IB_SRES => IB_SRES_IBDR, EI_ACKM => EI_ACKM, EI_PRI => EI_PRI, EI_VECT => EI_VECT, DISPREG => DISPREG ); MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB) CRAMCTL: nx_cram_memctl_as -- memory controller ----------------- generic map ( READ0DELAY => sys_conf_memctl_read0delay, READ1DELAY => sys_conf_memctl_read1delay, WRITEDELAY => sys_conf_memctl_writedelay) port map ( CLK => CLK, RESET => GRESET, REQ => MEM_REQ, WE => MEM_WE, BUSY => MEM_BUSY, ACK_R => MEM_ACK_R, ACK_W => open, ACT_R => MEM_ACT_R, ACT_W => MEM_ACT_W, ADDR => MEM_ADDR_EXT, BE => MEM_BE, DI => MEM_DI, DO => MEM_DO, O_MEM_CE_N => O_MEM_CE_N, O_MEM_BE_N => O_MEM_BE_N, O_MEM_WE_N => O_MEM_WE_N, O_MEM_OE_N => O_MEM_OE_N, O_MEM_ADV_N => O_MEM_ADV_N, O_MEM_CLK => O_MEM_CLK, O_MEM_CRE => O_MEM_CRE, I_MEM_WAIT => I_MEM_WAIT, O_MEM_ADDR => O_MEM_ADDR, IO_MEM_DATA => IO_MEM_DATA ); O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled O_PPCM_RST_N <= '1'; -- LED_IO : ioleds_sp1c_fx2 -- hio leds from serport or fx2 ------ port map ( CLK => CLK, CE_USEC => CE_USEC, RESET => GRESET, ENAFX2 => SWI(2), RB_SRES => RB_SRES, RLB_MONI => RLB_MONI, SER_MONI => SER_MONI, IOLEDS => DSP_DP ); ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; HIO70 : pdp11_hio70 -- hio from sys70 -------------------- generic map ( LWIDTH => LED'length, DCWIDTH => 2) port map ( SEL_LED => SWI(3), SEL_DSP => SWI(5 downto 4), MEM_ACT_R => MEM_ACT_R, MEM_ACT_W => MEM_ACT_W, CP_STAT => CP_STAT, DM_STAT_EXP => DM_STAT_EXP, ABCLKDIV => ABCLKDIV, DISPREG => DISPREG, LED => LED70, DSP_DAT => DSP_DAT ); proc_fx2leds: process (SWI, LED70, FX2_MONI) -- hio LED handler ------------ variable iled : slv8 := (others=>'0'); begin iled := (others=>'0'); if SWI(7) = '0' then iled := LED70; else iled(7) := FX2_MONI.fifo_ep4; iled(6) := FX2_MONI.fifo_ep6; iled(5) := FX2_MONI.fsm_rx; iled(4) := FX2_MONI.fsm_tx; if SWI(6) = '0' then iled(3) := FX2_MONI.flag_ep4_empty; iled(2) := FX2_MONI.flag_ep4_almost; iled(1) := FX2_MONI.flag_ep6_full; iled(0) := FX2_MONI.flag_ep6_almost; else iled(3) := FX2_MONI.fsm_idle; iled(2) := FX2_MONI.fsm_prep; iled(1) := FX2_MONI.fsm_disp; iled(0) := FX2_MONI.fsm_pipe; end if; end if; LED <= iled; end process proc_fx2leds; HIO : sn_humanio_rbus -- hio manager ----------------------- generic map ( BWIDTH => 5, DEBOUNCE => sys_conf_hio_debounce, RB_ADDR => rbaddr_hio) port map ( CLK => CLK, RESET => RESET, CE_MSEC => CE_MSEC, RB_MREQ => RB_MREQ, RB_SRES => RB_SRES_HIO, SWI => SWI, BTN => BTN, LED => LED, DSP_DAT => DSP_DAT, DSP_DP => DSP_DP, I_SWI => I_SWI, I_BTN => I_BTN, O_LED => O_LED, O_ANO_N => O_ANO_N, O_SEG_N => O_SEG_N ); RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- port map ( RB_SRES_1 => RB_SRES_CPU, RB_SRES_2 => RB_SRES_HIO, RB_SRES_OR => RB_SRES ); end syn;
-- ------------------------------------------------------------- -- -- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF1_3_block2.vhd -- Created: 2017-03-27 23:13:58 -- -- Generated by MATLAB 9.1 and HDL Coder 3.9 -- -- ------------------------------------------------------------- -- ------------------------------------------------------------- -- -- Module: RADIX22FFT_SDNF1_3_block2 -- Source Path: fft_16_bit/FFT HDL Optimized/RADIX22FFT_SDNF1_3 -- Hierarchy Level: 2 -- -- ------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; ENTITY RADIX22FFT_SDNF1_3_block2 IS PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_6_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_6_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_8_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_8_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_7_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_7_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_8_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_8_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_7_vld : OUT std_logic ); END RADIX22FFT_SDNF1_3_block2; ARCHITECTURE rtl OF RADIX22FFT_SDNF1_3_block2 IS -- Signals SIGNAL twdlXdin_6_re_signed : signed(19 DOWNTO 0); -- sfix20 SIGNAL twdlXdin_6_im_signed : signed(19 DOWNTO 0); -- sfix20 SIGNAL twdlXdin_8_re_signed : signed(19 DOWNTO 0); -- sfix20 SIGNAL twdlXdin_8_im_signed : signed(19 DOWNTO 0); -- sfix20 SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(20 DOWNTO 0); -- sfix21 SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(20 DOWNTO 0); -- sfix21 SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(20 DOWNTO 0); -- sfix21 SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(20 DOWNTO 0); -- sfix21 SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic; SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(20 DOWNTO 0); -- sfix21 SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(20 DOWNTO 0); -- sfix21 SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(20 DOWNTO 0); -- sfix21 SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(20 DOWNTO 0); -- sfix21 SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic; SIGNAL dout_7_re_tmp : signed(19 DOWNTO 0); -- sfix20 SIGNAL dout_7_im_tmp : signed(19 DOWNTO 0); -- sfix20 SIGNAL dout_8_re_tmp : signed(19 DOWNTO 0); -- sfix20 SIGNAL dout_8_im_tmp : signed(19 DOWNTO 0); -- sfix20 BEGIN twdlXdin_6_re_signed <= signed(twdlXdin_6_re); twdlXdin_6_im_signed <= signed(twdlXdin_6_im); twdlXdin_8_re_signed <= signed(twdlXdin_8_re); twdlXdin_8_im_signed <= signed(twdlXdin_8_im); -- Radix22ButterflyG1_NF Radix22ButterflyG1_NF_process : PROCESS (clk, reset) BEGIN IF reset = '1' THEN Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#000000#, 21); Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#000000#, 21); Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#000000#, 21); Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#000000#, 21); Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0'; ELSIF clk'EVENT AND clk = '1' THEN IF enb = '1' THEN Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next; Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next; Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next; Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next; Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next; END IF; END IF; END PROCESS Radix22ButterflyG1_NF_process; Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg, Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg, Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_6_re_signed, twdlXdin_6_im_signed, twdlXdin_8_re_signed, twdlXdin_8_im_signed, twdlXdin_1_vld) BEGIN Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg; Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg; Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg; Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg; Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld; IF twdlXdin_1_vld = '1' THEN Radix22ButterflyG1_NF_btf1_re_reg_next <= resize(twdlXdin_6_re_signed, 21) + resize(twdlXdin_8_re_signed, 21); Radix22ButterflyG1_NF_btf2_re_reg_next <= resize(twdlXdin_6_re_signed, 21) - resize(twdlXdin_8_re_signed, 21); Radix22ButterflyG1_NF_btf1_im_reg_next <= resize(twdlXdin_6_im_signed, 21) + resize(twdlXdin_8_im_signed, 21); Radix22ButterflyG1_NF_btf2_im_reg_next <= resize(twdlXdin_6_im_signed, 21) - resize(twdlXdin_8_im_signed, 21); END IF; dout_7_re_tmp <= Radix22ButterflyG1_NF_btf1_re_reg(19 DOWNTO 0); dout_7_im_tmp <= Radix22ButterflyG1_NF_btf1_im_reg(19 DOWNTO 0); dout_8_re_tmp <= Radix22ButterflyG1_NF_btf2_re_reg(19 DOWNTO 0); dout_8_im_tmp <= Radix22ButterflyG1_NF_btf2_im_reg(19 DOWNTO 0); dout_7_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1; END PROCESS Radix22ButterflyG1_NF_output; dout_7_re <= std_logic_vector(dout_7_re_tmp); dout_7_im <= std_logic_vector(dout_7_im_tmp); dout_8_re <= std_logic_vector(dout_8_re_tmp); dout_8_im <= std_logic_vector(dout_8_im_tmp); END rtl;
--! --! Copyright (C) 2012 - 2014 Creonic GmbH --! --! This file is part of the Creonic Viterbi Decoder, which is distributed --! under the terms of the GNU General Public License version 2. --! --! @file --! @brief AXI4-Stream buffer that allows to buffer the accept-signal. --! @author Matthias Alles --! @date 2012/04/18 --! --! @details --! One problem when concatenating multiple AXI4-Stream builind blocks is that --! the accept signal has to pass from the very last component to the input --! of the very first component. Only then it is possible to have an interruption --! free data processing within the whole chain. The drawback of this approach is --! that the accept signal has a long path and high fanouts. --! This entity allows to use registers on the accept signals by introducing buffers --! for storing the input values. It should improve timing of bigger building blocks. --! library ieee; use ieee.std_logic_1164.all; entity axi4s_buffer is generic ( DATA_WIDTH : natural := 1 ); port ( clk : in std_logic; rst : in std_logic; -- Input data handling ---------------------- input : in std_logic_vector(DATA_WIDTH - 1 downto 0); input_valid : in std_logic; input_last : in std_logic; input_accept : out std_logic; -- Output data handling ----------------------- output : out std_logic_vector(DATA_WIDTH - 1 downto 0); output_valid : out std_logic; output_last : out std_logic; output_accept : in std_logic ); end entity axi4s_buffer; architecture rtl of axi4s_buffer is signal input_accept_int : std_logic; signal output_reg : std_logic_vector(DATA_WIDTH - 1 downto 0); signal output_last_reg : std_logic; signal output_valid_reg : std_logic; signal buffer_full : std_logic; signal buffer_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal buffer_last : std_logic; begin input_accept <= input_accept_int; output <= output_reg; output_last <= output_last_reg; output_valid <= output_valid_reg; -- -- This process registers all signals. -- No combinatorial logic is bypassed from input to output and vice versa. -- pr_reg: process(clk) is begin if rising_edge(clk) then if rst = '1' then output_reg <= (others => '0'); output_last_reg <= '0'; output_valid_reg <= '0'; input_accept_int <= '1'; buffer_full <= '0'; buffer_data <= (others => '0'); buffer_last <= '0'; else -- -- Data is coming, buf output data can't be sent => Store input data in buffer -- and remove input_accept signal! -- if input_valid = '1' and input_accept_int = '1' and output_valid_reg = '1' and output_accept = '0' then buffer_data <= input; buffer_last <= input_last; buffer_full <= '1'; input_accept_int <= '0'; end if; -- -- Output data is being read but there is data in the buffer waiting for being sent -- => Use the buffer data! -- if output_accept = '1' and output_valid_reg = '1' and buffer_full = '1' then output_reg <= buffer_data; output_last_reg <= buffer_last; output_valid_reg <= '1'; buffer_full <= '0'; input_accept_int <= '1'; -- -- Data is being read and buffer is empty => Use input data directly! -- Output register is empty => Use input data directly! -- elsif (output_accept = '1' and output_valid_reg = '1') or output_valid_reg = '0' then output_reg <= input; output_last_reg <= input_last; output_valid_reg <= input_valid; end if; end if; end if; end process pr_reg; end architecture rtl;
--! --! Copyright (C) 2012 - 2014 Creonic GmbH --! --! This file is part of the Creonic Viterbi Decoder, which is distributed --! under the terms of the GNU General Public License version 2. --! --! @file --! @brief AXI4-Stream buffer that allows to buffer the accept-signal. --! @author Matthias Alles --! @date 2012/04/18 --! --! @details --! One problem when concatenating multiple AXI4-Stream builind blocks is that --! the accept signal has to pass from the very last component to the input --! of the very first component. Only then it is possible to have an interruption --! free data processing within the whole chain. The drawback of this approach is --! that the accept signal has a long path and high fanouts. --! This entity allows to use registers on the accept signals by introducing buffers --! for storing the input values. It should improve timing of bigger building blocks. --! library ieee; use ieee.std_logic_1164.all; entity axi4s_buffer is generic ( DATA_WIDTH : natural := 1 ); port ( clk : in std_logic; rst : in std_logic; -- Input data handling ---------------------- input : in std_logic_vector(DATA_WIDTH - 1 downto 0); input_valid : in std_logic; input_last : in std_logic; input_accept : out std_logic; -- Output data handling ----------------------- output : out std_logic_vector(DATA_WIDTH - 1 downto 0); output_valid : out std_logic; output_last : out std_logic; output_accept : in std_logic ); end entity axi4s_buffer; architecture rtl of axi4s_buffer is signal input_accept_int : std_logic; signal output_reg : std_logic_vector(DATA_WIDTH - 1 downto 0); signal output_last_reg : std_logic; signal output_valid_reg : std_logic; signal buffer_full : std_logic; signal buffer_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal buffer_last : std_logic; begin input_accept <= input_accept_int; output <= output_reg; output_last <= output_last_reg; output_valid <= output_valid_reg; -- -- This process registers all signals. -- No combinatorial logic is bypassed from input to output and vice versa. -- pr_reg: process(clk) is begin if rising_edge(clk) then if rst = '1' then output_reg <= (others => '0'); output_last_reg <= '0'; output_valid_reg <= '0'; input_accept_int <= '1'; buffer_full <= '0'; buffer_data <= (others => '0'); buffer_last <= '0'; else -- -- Data is coming, buf output data can't be sent => Store input data in buffer -- and remove input_accept signal! -- if input_valid = '1' and input_accept_int = '1' and output_valid_reg = '1' and output_accept = '0' then buffer_data <= input; buffer_last <= input_last; buffer_full <= '1'; input_accept_int <= '0'; end if; -- -- Output data is being read but there is data in the buffer waiting for being sent -- => Use the buffer data! -- if output_accept = '1' and output_valid_reg = '1' and buffer_full = '1' then output_reg <= buffer_data; output_last_reg <= buffer_last; output_valid_reg <= '1'; buffer_full <= '0'; input_accept_int <= '1'; -- -- Data is being read and buffer is empty => Use input data directly! -- Output register is empty => Use input data directly! -- elsif (output_accept = '1' and output_valid_reg = '1') or output_valid_reg = '0' then output_reg <= input; output_last_reg <= input_last; output_valid_reg <= input_valid; end if; end if; end if; end process pr_reg; end architecture rtl;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_06_tofpt.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $ -- $Revision: 1.1.1.1 $ -- -- --------------------------------------------------------------------- entity to_fp_test is end entity to_fp_test;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_06_tofpt.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $ -- $Revision: 1.1.1.1 $ -- -- --------------------------------------------------------------------- entity to_fp_test is end entity to_fp_test;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_06_tofpt.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $ -- $Revision: 1.1.1.1 $ -- -- --------------------------------------------------------------------- entity to_fp_test is end entity to_fp_test;
Library ieee; Use ieee.std_logic_1164.all; Use ieee.numeric_std.all; Entity System is Port(door: IN std_logic_vector(3 downto 0); ARM, clock : IN std_logic; ready, delay, SysArm, AlrOn: OUT std_logic); end System; Architecture Basic of System is Type StateName is (sysoff, syson, alr); signal Prest,NxtSt,sysoffnext,sysonnext,alrnext: StateName; begin sysoffnext <=syson when arm ='1' else sysoff; sysonnext <= sysoff when arm ='1' else alr when door /="0000" else syson; alrnext <= sysoff when arm ='1' else alr; NxtSt <= sysoffnext when prest = sysoff else sysonnext when prest = syson else alrnext; Prest <= NxtSt when Rising_edge(clock); ready <= '1' when door = "0000" else '0'; SysArm <= '1' when NxtSt = syson OR NxtSt = alr else '0'; AlrOn <= '1' when nxtSt = alr else '0' when NxtSt = sysoff OR nxtSt = syson; end Basic; Architecture thelayed of System is Component TenSecDelay is Port (load, clock: in std_logic; TC: out std_logic); End Component TenSecDelay; Type StateName is (sysoff, syson, alr); signal Prest,NxtSt,sysoffnext,sysonnext,alrnext: StateName; signal sload, sTC: std_logic; begin sysoffnext <=syson when arm ='1' else sysoff; sysonnext <= sysoff when arm ='1' else alr when (door /="0000" AND sTC ='0') else syson; alrnext <= sysoff when arm ='1' else alr; NxtSt <= sysoffnext when prest = sysoff else sysonnext when prest = syson else alrnext; Prest <= NxtSt when Rising_edge(clock); ready <= '1' when door = "0000" else '0'; SysArm <= '1' when NxtSt = syson OR NxtSt = alr else '0'; AlrOn <= '1' when (prest = alr AND sTC ='0') else '0'; --when NxtSt = sysoff OR nxtSt = syson; delay <= stc; sload<= '1' when (prest = sysoff and nxtst = syson) OR (prest = syson AND door /="0000") else '0'; stage0: entity work.tensecdelay port map(load=>sload, clock=> clock, TC=>sTC); end thelayed;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:51:25 10/20/2017 -- Design Name: -- Module Name: MuxRF - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity MuxRF is Port ( Rd : in STD_LOGIC_VECTOR (5 downto 0); O7 : in STD_LOGIC_VECTOR (5 downto 0); RFDEST : in STD_LOGIC; nRD : out STD_LOGIC_VECTOR (5 downto 0)); end MuxRF; architecture Behavioral of MuxRF is begin process (Rd,O7,RFDEST) begin case (RFDEST) is when '0' => nRD <= Rd; when '1' => nRD <= O7; when others => nRD <= Rd; end case; end process; end Behavioral;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:51:25 10/20/2017 -- Design Name: -- Module Name: MuxRF - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity MuxRF is Port ( Rd : in STD_LOGIC_VECTOR (5 downto 0); O7 : in STD_LOGIC_VECTOR (5 downto 0); RFDEST : in STD_LOGIC; nRD : out STD_LOGIC_VECTOR (5 downto 0)); end MuxRF; architecture Behavioral of MuxRF is begin process (Rd,O7,RFDEST) begin case (RFDEST) is when '0' => nRD <= Rd; when '1' => nRD <= O7; when others => nRD <= Rd; end case; end process; end Behavioral;
------------------------------------------------------------------------------- -- gpio_core - entity/architecture pair ------------------------------------------------------------------------------- -- ************************************************************************* -- DISCLAIMER OF LIABILITY -- -- This file contains proprietary and confidential information of -- Xilinx, Inc. ("Xilinx"), that is distributed under a license -- from Xilinx, and may be used, copied and/or disclosed only -- pursuant to the terms of a valid license agreement with Xilinx. -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx -- does not warrant that functions included in the Materials will -- meet the requirements of Licensee, or that the operation of the -- Materials will be uninterrupted or error-free, or that defects -- in the Materials will be corrected. Furthermore, Xilinx does -- not warrant or make any representations regarding use, or the -- results of the use, of the Materials in terms of correctness, -- accuracy, reliability or otherwise. -- -- Xilinx products are not designed or intended to be fail-safe, -- or for use in any application requiring fail-safe performance, -- such as life-support or safety devices or systems, Class III -- medical devices, nuclear facilities, applications related to -- the deployment of airbags, or any other applications that could -- lead to death, personal injury or severe property or -- environmental damage (individually and collectively, "critical -- applications"). Customer assumes the sole risk and liability -- of any use of Xilinx products in critical applications, -- subject only to applicable laws and regulations governing -- limitations on product liability. -- -- Copyright 2009 Xilinx, Inc. -- All rights reserved. -- -- This disclaimer and copyright notice must be retained as part -- of this file at all times. -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: gpio_core.vhd -- Version: v1.01a -- Description: General Purpose I/O for AXI Interface -- ------------------------------------------------------------------------------- -- Structure: -- axi_gpio.vhd -- -- axi_lite_ipif.vhd -- -- interrupt_control.vhd -- -- gpio_core.vhd -- ------------------------------------------------------------------------------- -- -- Author: KSB -- History: -- ~~~~~~~~~~~~~~ -- KSB 09/15/09 -- ^^^^^^^^^^^^^^ -- ~~~~~~~~~~~~~~ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; library lib_cdc_v1_0_2; ------------------------------------------------------------------------------- -- Definition of Generics : -- ------------------------------------------------------------------------------- -- C_DW -- Data width of PLB BUS. -- C_AW -- Address width of PLB BUS. -- C_GPIO_WIDTH -- GPIO Data Bus width. -- C_GPIO2_WIDTH -- GPIO2 Data Bus width. -- C_INTERRUPT_PRESENT -- GPIO Interrupt. -- C_DOUT_DEFAULT -- GPIO_DATA Register reset value. -- C_TRI_DEFAULT -- GPIO_TRI Register reset value. -- C_IS_DUAL -- Dual Channel GPIO. -- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value. -- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value. -- C_FAMILY -- XILINX FPGA family ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Definition of Ports -- ------------------------------------------------------------------------------- -- Clk -- Input clock -- Rst -- Reset -- ABus_Reg -- Bus to IP address -- BE_Reg -- Bus to IP byte enables -- DBus_Reg -- Bus to IP data bus -- RNW_Reg -- Bus to IP read write control -- GPIO_DBus -- IP to Bus data bus -- GPIO_xferAck -- GPIO transfer acknowledge -- GPIO_intr -- GPIO channel 1 interrupt to IPIC -- GPIO2_intr -- GPIO channel 2 interrupt to IPIC -- GPIO_Select -- GPIO select -- -- GPIO_IO_I -- Channel 1 General purpose I/O in port -- GPIO_IO_O -- Channel 1 General purpose I/O out port -- GPIO_IO_T -- Channel 1 General purpose I/O TRI-STATE control port -- GPIO2_IO_I -- Channel 2 General purpose I/O in port -- GPIO2_IO_O -- Channel 2 General purpose I/O out port -- GPIO2_IO_T -- Channel 2 General purpose I/O TRI-STATE control port ------------------------------------------------------------------------------- entity GPIO_Core is generic ( C_DW : integer := 32; C_AW : integer := 32; C_GPIO_WIDTH : integer := 32; C_GPIO2_WIDTH : integer := 32; C_MAX_GPIO_WIDTH : integer := 32; C_INTERRUPT_PRESENT : integer := 0; C_DOUT_DEFAULT : std_logic_vector (0 to 31) := X"0000_0000"; C_TRI_DEFAULT : std_logic_vector (0 to 31) := X"FFFF_FFFF"; C_IS_DUAL : integer := 0; C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013 C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013 C_ALL_INPUTS : integer range 0 to 1 := 0; C_ALL_INPUTS_2 : integer range 0 to 1 := 0; C_DOUT_DEFAULT_2 : std_logic_vector (0 to 31) := X"0000_0000"; C_TRI_DEFAULT_2 : std_logic_vector (0 to 31) := X"FFFF_FFFF"; C_FAMILY : string := "virtex7" ); port ( Clk : in std_logic; Rst : in std_logic; ABus_Reg : in std_logic_vector(0 to C_AW-1); BE_Reg : in std_logic_vector(0 to C_DW/8-1); DBus_Reg : in std_logic_vector(0 to C_MAX_GPIO_WIDTH-1); RNW_Reg : in std_logic; GPIO_DBus : out std_logic_vector(0 to C_DW-1); GPIO_xferAck : out std_logic; GPIO_intr : out std_logic; GPIO2_intr : out std_logic; GPIO_Select : in std_logic; GPIO_IO_I : in std_logic_vector(0 to C_GPIO_WIDTH-1); GPIO_IO_O : out std_logic_vector(0 to C_GPIO_WIDTH-1); GPIO_IO_T : out std_logic_vector(0 to C_GPIO_WIDTH-1); GPIO2_IO_I : in std_logic_vector(0 to C_GPIO2_WIDTH-1); GPIO2_IO_O : out std_logic_vector(0 to C_GPIO2_WIDTH-1); GPIO2_IO_T : out std_logic_vector(0 to C_GPIO2_WIDTH-1) ); end entity GPIO_Core; ------------------------------------------------------------------------------- -- Architecture section ------------------------------------------------------------------------------- architecture IMP of GPIO_Core is -- Pragma Added to supress synth warnings attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes"; ---------------------------------------------------------------------- -- Function for Reduction OR ---------------------------------------------------------------------- function or_reduce(l : std_logic_vector) return std_logic is variable v : std_logic := '0'; begin for i in l'range loop v := v or l(i); end loop; return v; end; --------------------------------------------------------------------- -- End of Function ------------------------------------------------------------------- --constant GPIO_G_W : integer = C_GPIO_WIDTH when (C_GPIO_WIDTH > C_GPIO2_WIDTH) else C_GPIO2_; signal gpio_Data_Select : std_logic_vector(0 to C_IS_DUAL); signal gpio_OE_Select : std_logic_vector(0 to C_IS_DUAL); signal Read_Reg_Rst : STD_LOGIC; signal Read_Reg_In : std_logic_vector(0 to C_GPIO_WIDTH-1); signal Read_Reg_CE : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_Data_Out : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_DOUT_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1); signal gpio_Data_In : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_in_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_in_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_io_i_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_io_i_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_OE : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_TRI_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1); signal GPIO_DBus_i : std_logic_vector(0 to C_DW-1); signal gpio_data_in_xor : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_data_in_xor_reg : std_logic_vector(0 to C_GPIO_WIDTH-1); signal or_ints : std_logic_vector(0 to 0); signal or_ints2 : std_logic_vector(0 to 0); signal iGPIO_xferAck : STD_LOGIC; signal gpio_xferAck_Reg : STD_LOGIC; signal dout_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1); signal tri_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1); signal reset_zeros : std_logic_vector(0 to C_GPIO_WIDTH-1); signal dout2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal tri2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal reset2_zeros : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio_reg_en : std_logic; begin -- architecture IMP reset_zeros <= (others => '0'); reset2_zeros <= (others => '0'); TIE_DEFAULTS_GENERATE : if C_DW >= C_GPIO_WIDTH generate SELECT_BITS_GENERATE : for i in 0 to C_GPIO_WIDTH-1 generate dout_default_i(i) <= C_DOUT_DEFAULT(i-C_GPIO_WIDTH+C_DW); tri_default_i(i) <= C_TRI_DEFAULT(i-C_GPIO_WIDTH+C_DW); end generate SELECT_BITS_GENERATE; end generate TIE_DEFAULTS_GENERATE; TIE_DEFAULTS_2_GENERATE : if C_DW >= C_GPIO2_WIDTH generate SELECT_BITS_2_GENERATE : for i in 0 to C_GPIO2_WIDTH-1 generate dout2_default_i(i) <= C_DOUT_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW); tri2_default_i(i) <= C_TRI_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW); end generate SELECT_BITS_2_GENERATE; end generate TIE_DEFAULTS_2_GENERATE; Read_Reg_Rst <= iGPIO_xferAck or gpio_xferAck_Reg or (not GPIO_Select) or (GPIO_Select and not RNW_Reg); gpio_reg_en <= GPIO_Select when (ABus_Reg(0) = '0') else '0'; ----------------------------------------------------------------------------- -- XFER_ACK_PROCESS ----------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ----------------------------------------------------------------------------- XFER_ACK_PROCESS : process (Clk) is begin if (Clk'EVENT and Clk = '1') then if (Rst = '1') then iGPIO_xferAck <= '0'; else iGPIO_xferAck <= GPIO_Select and not gpio_xferAck_Reg; if iGPIO_xferAck = '1' then iGPIO_xferAck <= '0'; end if; end if; end if; end process XFER_ACK_PROCESS; ----------------------------------------------------------------------------- -- DELAYED_XFER_ACK_PROCESS ----------------------------------------------------------------------------- -- Single Reg stage to make Transfer Ack period one clock pulse wide ----------------------------------------------------------------------------- DELAYED_XFER_ACK_PROCESS : process (Clk) is begin if (Clk'EVENT and Clk = '1') then if (Rst = '1') then gpio_xferAck_Reg <= '0'; else gpio_xferAck_Reg <= iGPIO_xferAck; end if; end if; end process DELAYED_XFER_ACK_PROCESS; GPIO_xferAck <= iGPIO_xferAck; ----------------------------------------------------------------------------- -- Drive GPIO interrupts to '0' when interrupt not present ----------------------------------------------------------------------------- DONT_GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate gpio_intr <= '0'; gpio2_intr <= '0'; end generate DONT_GEN_INTERRUPT; ---------------------------------------------------------------------------- -- When only one channel is used, the additional logic for the second -- channel ports is not present ----------------------------------------------------------------------------- Not_Dual : if (C_IS_DUAL = 0) generate GPIO2_IO_O <= C_DOUT_DEFAULT(0 to C_GPIO2_WIDTH-1); GPIO2_IO_T <= C_TRI_DEFAULT_2(0 to C_GPIO2_WIDTH-1); ALLOUT_ND : if (C_ALL_OUTPUTS = 1) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLOUT_ND; ALLIN1_ND : if (C_ALL_INPUTS = 1) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLIN1_ND; ALLOUT0_ND : if (C_ALL_OUTPUTS = 0 and C_ALL_INPUTS = 0) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else if (gpio_OE(i) = '0' and gpio_OE_Select(0) = '0')then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); end if; --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLOUT0_ND; TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0'); end generate TIE_DBUS_GENERATE; ----------------------------------------------------------------------------- -- GPIO_DBUS_PROCESS ----------------------------------------------------------------------------- -- This process generates the GPIO DATA BUS from the GPIO_DBUS_I based on -- the channel select signals ----------------------------------------------------------------------------- GPIO_DBus <= GPIO_DBus_i; ----------------------------------------------------------------------------- -- REG_SELECT_PROCESS ----------------------------------------------------------------------------- -- GPIO REGISTER selection decoder for single channel configuration ----------------------------------------------------------------------------- --REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is begin gpio_Data_Select(0) <= '0'; gpio_OE_Select(0) <= '0'; --if GPIO_Select = '1' then if gpio_reg_en = '1' then if (ABus_Reg(5) = '0') then case ABus_Reg(6) is -- bit A29 when '0' => gpio_Data_Select(0) <= '1'; when '1' => gpio_OE_Select(0) <= '1'; -- coverage off when others => null; -- coverage on end case; end if; end if; end process REG_SELECT_PROCESS; INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 0, C_VECTOR_WIDTH => C_GPIO_WIDTH, C_MTBF_STAGES => 4 ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => '0', prmry_vect_in => GPIO_IO_I, scndry_aclk => Clk, scndry_resetn => '0', scndry_out => open, scndry_vect_out => gpio_io_i_d2 ); --------------------------------------------------------------------------- -- GPIO_INDATA_BIRDIR_PROCESS --------------------------------------------------------------------------- -- Reading of channel 1 data from Bidirectional GPIO port -- to GPIO_DATA REGISTER --------------------------------------------------------------------------- GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then -- gpio_io_i_d1 <= GPIO_IO_I; -- gpio_io_i_d2 <= gpio_io_i_d1; gpio_Data_In <= gpio_io_i_d2; end if; end process GPIO_INDATA_BIRDIR_PROCESS; --------------------------------------------------------------------------- -- GPIO_OUTDATA_PROCESS --------------------------------------------------------------------------- -- Writing to Channel 1 GPIO_DATA REGISTER --------------------------------------------------------------------------- GPIO_OUTDATA_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio_Data_Out <= dout_default_i; elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO_WIDTH-1 loop gpio_Data_Out(i) <= DBus_Reg(i); end loop; end if; end if; end process GPIO_OUTDATA_PROCESS; --------------------------------------------------------------------------- -- READ_MUX_PROCESS --------------------------------------------------------------------------- -- Selects GPIO_TRI control or GPIO_DATA Register to be read --------------------------------------------------------------------------- READ_MUX_PROCESS : process (gpio_Data_In, gpio_Data_Select, gpio_OE, gpio_OE_Select,gpio_Data_Out) is begin Read_Reg_In <= (others => '0'); if gpio_Data_Select(0) = '1' then Read_Reg_In <= gpio_Data_In; --Read_Reg_In <= gpio_Data_In; elsif gpio_OE_Select(0) = '1' then Read_Reg_In <= gpio_OE; end if; end process READ_MUX_PROCESS; --------------------------------------------------------------------------- -- GPIO_OE_PROCESS --------------------------------------------------------------------------- -- Writing to Channel 1 GPIO_TRI Control REGISTER --------------------------------------------------------------------------- GPIO_OE_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio_OE <= tri_default_i; elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO_WIDTH-1 loop gpio_OE(i) <= DBus_Reg(i); end loop; end if; end if; end process GPIO_OE_PROCESS; GPIO_IO_O <= gpio_Data_Out; GPIO_IO_T <= gpio_OE; ---------------------------------------------------------------------------- -- INTERRUPT IS PRESENT ---------------------------------------------------------------------------- -- When the C_INTERRUPT_PRESENT=1, the interrupt is driven based on whether -- there is a change in the data coming in at the GPIO_IO_I port or GPIO_In -- port ---------------------------------------------------------------------------- GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 1) generate gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2; ------------------------------------------------------------------------- -- An interrupt conditon exists if there is a change on any bit. ------------------------------------------------------------------------- or_ints(0) <= or_reduce(gpio_data_in_xor_reg); ------------------------------------------------------------------------- -- Registering Interrupt condition ------------------------------------------------------------------------- REGISTER_XOR_INTR : process (Clk) is begin if (Clk'EVENT and Clk = '1') then if (Rst = '1') then gpio_data_in_xor_reg <= reset_zeros; GPIO_intr <= '0'; else gpio_data_in_xor_reg <= gpio_data_in_xor; GPIO_intr <= or_ints(0); end if; end if; end process REGISTER_XOR_INTR; gpio2_intr <= '0'; -- Channel 2 interrupt is driven low end generate GEN_INTERRUPT; end generate Not_Dual; ---)(------------------------------------------------------------------------ -- When both the channels are used, the additional logic for the second -- channel ports ----------------------------------------------------------------------------- Dual : if (C_IS_DUAL = 1) generate signal gpio2_Data_In : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_in_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_in_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_io_i_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_io_i_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_data_in_xor : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_data_in_xor_reg : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_Data_Out : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_DOUT_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1); signal gpio2_OE : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_TRI_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1); signal Read_Reg2_In : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal Read_Reg2_CE : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal GPIO2_DBus_i : std_logic_vector(0 to C_DW-1); begin ALLOUT0_ND_G0 : if (C_ALL_OUTPUTS = 0 and C_ALL_INPUTS = 0) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else if (gpio_OE(i) = '0' and gpio_OE_Select(0) = '0') then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); end if; --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLOUT0_ND_G0; ALLIN0_ND_G0 : if (C_ALL_INPUTS = 1) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLIN0_ND_G0; ALLOUT0_ND_G1 : if (C_ALL_OUTPUTS = 1) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate begin -------------------------------------------------------------------------- -- GPIO_DBUS_I_PROCESS -------------------------------------------------------------------------- -- This process generates the GPIO CHANNEL1 DATA BUS -------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLOUT0_ND_G1; TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0'); end generate TIE_DBUS_GENERATE; ALLIN0_ND_G2 : if (C_ALL_OUTPUTS_2 = 0 and C_ALL_INPUTS_2 = 1) generate READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate -------------------------------------------------------------------------- -- GPIO2_DBUS_I_PROCESS -------------------------------------------------------------------------- -- This process generates the GPIO CHANNEL2 DATA BUS -------------------------------------------------------------------------- GPIO2_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0'; else GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i); --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); end if; end if; end process; end generate READ_REG2_GEN; end generate ALLIN0_ND_G2; ALLOUT0_ND_G2 : if (C_ALL_OUTPUTS_2 = 0 and C_ALL_INPUTS_2 = 0) generate READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate -------------------------------------------------------------------------- -- GPIO2_DBUS_I_PROCESS -------------------------------------------------------------------------- -- This process generates the GPIO CHANNEL2 DATA BUS -------------------------------------------------------------------------- GPIO2_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0'; else if (gpio2_OE(i) = '0' and gpio_OE_Select(1) = '0') then GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i); else GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i); end if; -- GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i) when (gpio2_OE(i) = '1') else Read_Reg2_In(i); --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); end if; end if; end process; end generate READ_REG2_GEN; end generate ALLOUT0_ND_G2; ALLOUT1_ND_G2 : if (C_ALL_OUTPUTS_2 = 1) generate READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate -------------------------------------------------------------------------- -- GPIO2_DBUS_I_PROCESS -------------------------------------------------------------------------- -- This process generates the GPIO CHANNEL2 DATA BUS -------------------------------------------------------------------------- GPIO2_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0'; else GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i); end if; end if; end process; end generate READ_REG2_GEN; end generate ALLOUT1_ND_G2; TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0'); end generate TIE_DBUS2_GENERATE; --------------------------------------------------------------------------- -- GPIO_DBUS_PROCESS --------------------------------------------------------------------------- -- This process generates the GPIO DATA BUS from the GPIO_DBUS_I and -- GPIO2_DBUS_I based on which channel is selected --------------------------------------------------------------------------- GPIO_DBus <= GPIO_DBus_i when (((gpio_Data_Select(0) = '1') or (gpio_OE_Select(0) = '1')) and (RNW_Reg = '1')) else GPIO2_DBus_i; ----------------------------------------------------------------------------- -- DUAL_REG_SELECT_PROCESS ----------------------------------------------------------------------------- -- GPIO REGISTER selection decoder for Dual channel configuration ----------------------------------------------------------------------------- --DUAL_REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is DUAL_REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is variable ABus_reg_select : std_logic_vector(0 to 1); begin ABus_reg_select := ABus_Reg(5 to 6); gpio_Data_Select <= (others => '0'); gpio_OE_Select <= (others => '0'); --if GPIO_Select = '1' then if gpio_reg_en = '1' then -- case ABus_Reg(28 to 29) is -- bit A28,A29 for dual case ABus_reg_select is -- bit A28,A29 for dual when "00" => gpio_Data_Select(0) <= '1'; when "01" => gpio_OE_Select(0) <= '1'; when "10" => gpio_Data_Select(1) <= '1'; when "11" => gpio_OE_Select(1) <= '1'; -- coverage off when others => null; -- coverage on end case; end if; end process DUAL_REG_SELECT_PROCESS; --------------------------------------------------------------------------- -- GPIO_INDATA_BIRDIR_PROCESS --------------------------------------------------------------------------- -- Reading of channel 1 data from Bidirectional GPIO port -- to GPIO_DATA REGISTER --------------------------------------------------------------------------- INPUT_DOUBLE_REGS4 : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 0, C_VECTOR_WIDTH => C_GPIO_WIDTH, C_MTBF_STAGES => 4 ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => '0', prmry_vect_in => GPIO_IO_I, scndry_aclk => Clk, scndry_resetn => '0', scndry_out => open, scndry_vect_out => gpio_io_i_d2 ); GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then -- gpio_io_i_d1 <= GPIO_IO_I; -- gpio_io_i_d2 <= gpio_io_i_d1; --if (C_ALL_OUTPUTS = '1') then -- gpio_Data_In <= gpio_Data_Out; -- else gpio_Data_In <= gpio_io_i_d2; -- end if; end if; end process GPIO_INDATA_BIRDIR_PROCESS; INPUT_DOUBLE_REGS5 : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 0, C_VECTOR_WIDTH => C_GPIO2_WIDTH, C_MTBF_STAGES => 4 ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => '0', prmry_vect_in => GPIO2_IO_I, scndry_aclk => Clk, scndry_resetn => '0', scndry_out => open, scndry_vect_out => gpio2_io_i_d2 ); --------------------------------------------------------------------------- -- GPIO2_INDATA_BIRDIR_PROCESS --------------------------------------------------------------------------- -- Reading of channel 2 data from Bidirectional GPIO2 port -- to GPIO2_DATA REGISTER --------------------------------------------------------------------------- GPIO2_INDATA_BIRDIR_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then -- gpio2_io_i_d1 <= GPIO2_IO_I; -- gpio2_io_i_d2 <= gpio2_io_i_d1; -- if (C_ALL_OUTPUTS = '1') then -- gpio2_Data_In <= gpio2_Data_Out; -- else gpio2_Data_In <= gpio2_io_i_d2; -- end if; end if; end process GPIO2_INDATA_BIRDIR_PROCESS; --------------------------------------------------------------------------- -- GPIO_OUTDATA_PROCESS_0_0 --------------------------------------------------------------------------- -- Writing to Channel 1 GPIO_DATA REGISTER --------------------------------------------------------------------------- GPIO_OUTDATA_PROCESS_0_0 : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio_Data_Out <= dout_default_i; elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO_WIDTH-1 loop gpio_Data_Out(i) <= DBus_Reg(i); end loop; end if; end if; end process GPIO_OUTDATA_PROCESS_0_0; --------------------------------------------------------------------------- -- GPIO_OE_PROCESS_0_0 --------------------------------------------------------------------------- -- Writing to Channel 1 GPIO_TRI Control REGISTER --------------------------------------------------------------------------- GPIO_OE_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio_OE <= tri_default_i; elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO_WIDTH-1 loop gpio_OE(i) <= DBus_Reg(i); -- end if; end loop; end if; end if; end process GPIO_OE_PROCESS; --------------------------------------------------------------------------- -- GPIO2_OUTDATA_PROCESS_0_0 --------------------------------------------------------------------------- -- Writing to Channel 2 GPIO2_DATA REGISTER --------------------------------------------------------------------------- GPIO2_OUTDATA_PROCESS_0_0 : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio2_Data_Out <= dout2_default_i; elsif gpio_Data_Select(1) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO2_WIDTH-1 loop gpio2_Data_Out(i) <= DBus_Reg(i); -- end if; end loop; end if; end if; end process GPIO2_OUTDATA_PROCESS_0_0; --------------------------------------------------------------------------- -- GPIO2_OE_PROCESS_0_0 --------------------------------------------------------------------------- -- Writing to Channel 2 GPIO2_TRI Control REGISTER --------------------------------------------------------------------------- GPIO2_OE_PROCESS_0_0 : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio2_OE <= tri2_default_i; elsif gpio_OE_Select(1) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO2_WIDTH-1 loop gpio2_OE(i) <= DBus_Reg(i); end loop; end if; end if; end process GPIO2_OE_PROCESS_0_0; GPIO_IO_O <= gpio_Data_Out; GPIO_IO_T <= gpio_OE; GPIO2_IO_O <= gpio2_Data_Out; GPIO2_IO_T <= gpio2_OE; --------------------------------------------------------------------------- -- READ_MUX_PROCESS_0_0 --------------------------------------------------------------------------- -- Selects among Channel 1 GPIO_DATA ,GPIO_TRI and Channel 2 GPIO2_DATA -- GPIO2_TRI REGISTERS for reading --------------------------------------------------------------------------- READ_MUX_PROCESS_0_0 : process (gpio2_Data_In, gpio2_OE, gpio_Data_In, gpio_Data_Select, gpio_OE, gpio_OE_Select,gpio_Data_Out,gpio2_Data_Out) is begin Read_Reg_In <= (others => '0'); Read_Reg2_In <= (others => '0'); if gpio_Data_Select(0) = '1' then Read_Reg_In <= gpio_Data_In; --Read_Reg_In <= gpio_Data_In; elsif gpio_OE_Select(0) = '1' then Read_Reg_In <= gpio_OE; elsif gpio_Data_Select(1) = '1' then Read_Reg2_In <= gpio2_Data_In; --Read_Reg2_In <= gpio2_Data_In; --Read_Reg2_In<= gpio2_Data_In; elsif gpio_OE_Select(1) = '1' then Read_Reg2_In <= gpio2_OE; end if; end process READ_MUX_PROCESS_0_0; --------------------------------------------------------------------------- -- INTERRUPT IS PRESENT --------------------------------------------------------------------------- gen_interrupt_dual : if (C_INTERRUPT_PRESENT = 1) generate gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2; gpio2_data_in_xor <= gpio2_Data_In xor gpio2_io_i_d2; ------------------------------------------------------------------------- -- An interrupt conditon exists if there is a change any bit. ------------------------------------------------------------------------- or_ints(0) <= or_reduce(gpio_data_in_xor_reg); or_ints2(0) <= or_reduce(gpio2_data_in_xor_reg); ------------------------------------------------------------------------- -- Registering Interrupt condition ------------------------------------------------------------------------- REGISTER_XORs_INTRs : process (Clk) is begin if (Clk'EVENT and Clk = '1') then if (Rst = '1') then gpio_data_in_xor_reg <= reset_zeros; gpio2_data_in_xor_reg <= reset2_zeros; GPIO_intr <= '0'; GPIO2_intr <= '0'; else gpio_data_in_xor_reg <= gpio_data_in_xor; gpio2_data_in_xor_reg <= gpio2_data_in_xor; GPIO_intr <= or_ints(0); GPIO2_intr <= or_ints2(0); end if; end if; end process REGISTER_XORs_INTRs; end generate gen_interrupt_dual; end generate Dual; end architecture IMP; ------------------------------------------------------------------------------- -- AXI_GPIO - entity/architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************ -- DISCLAIMER OF LIABILITY -- -- This file contains proprietary and confidential information of -- Xilinx, Inc. ("Xilinx"), that is distributed under a license -- from Xilinx, and may be used, copied and/or disclosed only -- pursuant to the terms of a valid license agreement with Xilinx. -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx -- does not warrant that functions included in the Materials will -- meet the requirements of Licensee, or that the operation of the -- Materials will be uninterrupted or error-free, or that defects -- in the Materials will be corrected. Furthermore, Xilinx does -- not warrant or make any representations regarding use, or the -- results of the use, of the Materials in terms of correctness, -- accuracy, reliability or otherwise. -- -- Xilinx products are not designed or intended to be fail-safe, -- or for use in any application requiring fail-safe performance, -- such as life-support or safety devices or systems, Class III -- medical devices, nuclear facilities, applications related to -- the deployment of airbags, or any other applications that could -- lead to death, personal injury or severe property or -- environmental damage (individually and collectively, "critical -- applications"). Customer assumes the sole risk and liability -- of any use of Xilinx products in critical applications, -- subject only to applicable laws and regulations governing -- limitations on product liability. -- -- Copyright 2009 Xilinx, Inc. -- All rights reserved. -- -- This disclaimer and copyright notice must be retained as part -- of this file at all times. -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_gpio.vhd -- Version: v2.0 -- Description: General Purpose I/O for AXI Interface -- ------------------------------------------------------------------------------- -- Structure: -- axi_gpio.vhd -- -- axi_lite_ipif.vhd -- -- interrupt_control.vhd -- -- gpio_core.vhd ------------------------------------------------------------------------------- -- Author: KSB -- History: -- ~~~~~~~~~~~~~~ -- KSB 07/28/09 -- ^^^^^^^^^^^^^^ -- First version of axi_gpio. Based on xps_gpio 2.00a -- -- KSB 05/20/10 -- ^^^^^^^^^^^^^^ -- Updated for holes in address range -- ~~~~~~~~~~~~~~ -- VB 09/23/10 -- ^^^^^^^^^^^^^^ -- Updated for axi_lite_ipfi_v1_01_a -- ~~~~~~~~~~~~~~ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; use std.textio.all; ------------------------------------------------------------------------------- -- AXI common package of the proc common library is used for different -- function declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- axi_gpio_v2_0_15 library is used for axi4 component declarations ------------------------------------------------------------------------------- library axi_lite_ipif_v3_0_4; use axi_lite_ipif_v3_0_4.ipif_pkg.calc_num_ce; use axi_lite_ipif_v3_0_4.ipif_pkg.INTEGER_ARRAY_TYPE; use axi_lite_ipif_v3_0_4.ipif_pkg.SLV64_ARRAY_TYPE; ------------------------------------------------------------------------------- -- axi_gpio_v2_0_15 library is used for interrupt controller component -- declarations ------------------------------------------------------------------------------- library interrupt_control_v3_1_4; ------------------------------------------------------------------------------- -- axi_gpio_v2_0_15 library is used for axi_gpio component declarations ------------------------------------------------------------------------------- library axi_gpio_v2_0_15; ------------------------------------------------------------------------------- -- Defination of Generics : -- ------------------------------------------------------------------------------- -- AXI generics -- C_BASEADDR -- Base address of the core -- C_HIGHADDR -- Permits alias of address space -- by making greater than xFFF -- C_S_AXI_ADDR_WIDTH -- Width of AXI Address interface (in bits) -- C_S_AXI_DATA_WIDTH -- Width of the AXI Data interface (in bits) -- C_FAMILY -- XILINX FPGA family -- C_INSTANCE -- Instance name ot the core in the EDK system -- C_GPIO_WIDTH -- GPIO Data Bus width. -- C_ALL_INPUTS -- Inputs Only. -- C_INTERRUPT_PRESENT -- GPIO Interrupt. -- C_IS_BIDIR -- Selects gpio_io_i as input. -- C_DOUT_DEFAULT -- GPIO_DATA Register reset value. -- C_TRI_DEFAULT -- GPIO_TRI Register reset value. -- C_IS_DUAL -- Dual Channel GPIO. -- C_ALL_INPUTS_2 -- Channel2 Inputs only. -- C_IS_BIDIR_2 -- Selects gpio2_io_i as input. -- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value. -- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value. ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Defination of Ports -- ------------------------------------------------------------------------------- -- AXI signals -- s_axi_awaddr -- AXI Write address -- s_axi_awvalid -- Write address valid -- s_axi_awready -- Write address ready -- s_axi_wdata -- Write data -- s_axi_wstrb -- Write strobes -- s_axi_wvalid -- Write valid -- s_axi_wready -- Write ready -- s_axi_bresp -- Write response -- s_axi_bvalid -- Write response valid -- s_axi_bready -- Response ready -- s_axi_araddr -- Read address -- s_axi_arvalid -- Read address valid -- s_axi_arready -- Read address ready -- s_axi_rdata -- Read data -- s_axi_rresp -- Read response -- s_axi_rvalid -- Read valid -- s_axi_rready -- Read ready -- GPIO Signals -- gpio_io_i -- Channel 1 General purpose I/O in port -- gpio_io_o -- Channel 1 General purpose I/O out port -- gpio_io_t -- Channel 1 General purpose I/O -- TRI-STATE control port -- gpio2_io_i -- Channel 2 General purpose I/O in port -- gpio2_io_o -- Channel 2 General purpose I/O out port -- gpio2_io_t -- Channel 2 General purpose I/O -- TRI-STATE control port -- System Signals -- s_axi_aclk -- AXI Clock -- s_axi_aresetn -- AXI Reset -- ip2intc_irpt -- AXI GPIO Interrupt ------------------------------------------------------------------------------- entity axi_gpio is generic ( -- -- System Parameter C_FAMILY : string := "virtex7"; -- -- AXI Parameters C_S_AXI_ADDR_WIDTH : integer range 9 to 9 := 9; C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32; -- -- GPIO Parameter C_GPIO_WIDTH : integer range 1 to 32 := 32; C_GPIO2_WIDTH : integer range 1 to 32 := 32; C_ALL_INPUTS : integer range 0 to 1 := 0; C_ALL_INPUTS_2 : integer range 0 to 1 := 0; C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013 C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013 C_INTERRUPT_PRESENT : integer range 0 to 1 := 0; C_DOUT_DEFAULT : std_logic_vector (31 downto 0) := X"0000_0000"; C_TRI_DEFAULT : std_logic_vector (31 downto 0) := X"FFFF_FFFF"; C_IS_DUAL : integer range 0 to 1 := 0; C_DOUT_DEFAULT_2 : std_logic_vector (31 downto 0) := X"0000_0000"; C_TRI_DEFAULT_2 : std_logic_vector (31 downto 0) := X"FFFF_FFFF" ); port ( -- AXI interface Signals -------------------------------------------------- s_axi_aclk : in std_logic; s_axi_aresetn : in std_logic; s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); s_axi_wvalid : in std_logic; s_axi_wready : out std_logic; s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_arvalid : in std_logic; s_axi_arready : out std_logic; s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rvalid : out std_logic; s_axi_rready : in std_logic; -- Interrupt--------------------------------------------------------------- ip2intc_irpt : out std_logic; -- GPIO Signals------------------------------------------------------------ gpio_io_i : in std_logic_vector(C_GPIO_WIDTH-1 downto 0); gpio_io_o : out std_logic_vector(C_GPIO_WIDTH-1 downto 0); gpio_io_t : out std_logic_vector(C_GPIO_WIDTH-1 downto 0); gpio2_io_i : in std_logic_vector(C_GPIO2_WIDTH-1 downto 0); gpio2_io_o : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0); gpio2_io_t : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0) ); ------------------------------------------------------------------------------- -- fan-out attributes for XST ------------------------------------------------------------------------------- attribute MAX_FANOUT : string; attribute MAX_FANOUT of s_axi_aclk : signal is "10000"; attribute MAX_FANOUT of s_axi_aresetn : signal is "10000"; ------------------------------------------------------------------------------- -- Attributes for MPD file ------------------------------------------------------------------------------- attribute IP_GROUP : string ; attribute IP_GROUP of axi_gpio : entity is "LOGICORE"; attribute SIGIS : string ; attribute SIGIS of s_axi_aclk : signal is "Clk"; attribute SIGIS of s_axi_aresetn : signal is "Rst"; attribute SIGIS of ip2intc_irpt : signal is "INTR_LEVEL_HIGH"; end entity axi_gpio; ------------------------------------------------------------------------------- -- Architecture Section ------------------------------------------------------------------------------- architecture imp of axi_gpio is -- Pragma Added to supress synth warnings attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; ------------------------------------------------------------------------------- -- constant added for webtalk information ------------------------------------------------------------------------------- --function chr(sl: std_logic) return character is -- variable c: character; -- begin -- case sl is -- when '0' => c:= '0'; -- when '1' => c:= '1'; -- when 'Z' => c:= 'Z'; -- when 'U' => c:= 'U'; -- when 'X' => c:= 'X'; -- when 'W' => c:= 'W'; -- when 'L' => c:= 'L'; -- when 'H' => c:= 'H'; -- when '-' => c:= '-'; -- end case; -- return c; -- end chr; -- --function str(slv: std_logic_vector) return string is -- variable result : string (1 to slv'length); -- variable r : integer; -- begin -- r := 1; -- for i in slv'range loop -- result(r) := chr(slv(i)); -- r := r + 1; -- end loop; -- return result; -- end str; type bo2na_type is array (boolean) of natural; -- boolean to --natural conversion constant bo2na : bo2na_type := (false => 0, true => 1); ------------------------------------------------------------------------------- -- Function Declarations ------------------------------------------------------------------------------- type BOOLEAN_ARRAY_TYPE is array(natural range <>) of boolean; ---------------------------------------------------------------------------- -- This function returns the number of elements that are true in -- a boolean array. ---------------------------------------------------------------------------- function num_set( ba : BOOLEAN_ARRAY_TYPE ) return natural is variable n : natural := 0; begin for i in ba'range loop n := n + bo2na(ba(i)); end loop; return n; end; ---------------------------------------------------------------------------- -- This function returns a num_ce integer array that is constructed by -- taking only those elements of superset num_ce integer array -- that will be defined by the current case. -- The superset num_ce array is given by parameter num_ce_by_ard. -- The current case the ard elements that will be used is given -- by parameter defined_ards. ---------------------------------------------------------------------------- function qual_ard_num_ce_array( defined_ards : BOOLEAN_ARRAY_TYPE; num_ce_by_ard : INTEGER_ARRAY_TYPE ) return INTEGER_ARRAY_TYPE is variable res : INTEGER_ARRAY_TYPE(num_set(defined_ards)-1 downto 0); variable i : natural := 0; variable j : natural := defined_ards'left; begin while i /= res'length loop -- coverage off while defined_ards(j) = false loop j := j+1; end loop; -- coverage on res(i) := num_ce_by_ard(j); i := i+1; j := j+1; end loop; return res; end; ---------------------------------------------------------------------------- -- This function returns a addr_range array that is constructed by -- taking only those elements of superset addr_range array -- that will be defined by the current case. -- The superset addr_range array is given by parameter addr_range_by_ard. -- The current case the ard elements that will be used is given -- by parameter defined_ards. ---------------------------------------------------------------------------- function qual_ard_addr_range_array( defined_ards : BOOLEAN_ARRAY_TYPE; addr_range_by_ard : SLV64_ARRAY_TYPE ) return SLV64_ARRAY_TYPE is variable res : SLV64_ARRAY_TYPE(0 to 2num_set(defined_ards)-1); variable i : natural := 0; variable j : natural := defined_ards'left; begin while i /= res'length loop -- coverage off while defined_ards(j) = false loop j := j+1; end loop; -- coverage on res(i) := addr_range_by_ard(2j); res(i+1) := addr_range_by_ard((2j)+1); i := i+2; j := j+1; end loop; return res; end; function qual_ard_ce_valid( defined_ards : BOOLEAN_ARRAY_TYPE ) return std_logic_vector is variable res : std_logic_vector(0 to 31); begin res := (others => '0'); if defined_ards(defined_ards'right) then res(0 to 3) := "1111"; res(12) := '1'; res(13) := '1'; res(15) := '1'; else res(0 to 3) := "1111"; end if; return res; end; ---------------------------------------------------------------------------- -- This function returns the maximum width amongst the two GPIO Channels -- and if there is only one channel, it returns just the width of that -- channel. ---------------------------------------------------------------------------- function max_width( dual_channel : INTEGER; channel1_width : INTEGER; channel2_width : INTEGER ) return INTEGER is begin if (dual_channel = 0) then return channel1_width; else if (channel1_width > channel2_width) then return channel1_width; else return channel2_width; end if; end if; end; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- constant C_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF"; constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0'); constant INTR_TYPE : integer := 5; constant INTR_BASEADDR : std_logic_vector(0 to 31):= X"00000100"; constant INTR_HIGHADDR : std_logic_vector(0 to 31):= X"000001FF"; constant GPIO_HIGHADDR : std_logic_vector(0 to 31):= X"0000000F"; constant MAX_GPIO_WIDTH : integer := max_width (C_IS_DUAL,C_GPIO_WIDTH,C_GPIO2_WIDTH); constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := qual_ard_addr_range_array( (true,C_INTERRUPT_PRESENT=1), (ZERO_ADDR_PAD & X"00000000", ZERO_ADDR_PAD & GPIO_HIGHADDR, ZERO_ADDR_PAD & INTR_BASEADDR, ZERO_ADDR_PAD & INTR_HIGHADDR ) ); constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := qual_ard_num_ce_array( (true,C_INTERRUPT_PRESENT=1), (4,16) ); constant ARD_CE_VALID : std_logic_vector(0 to 31) := qual_ard_ce_valid( (true,C_INTERRUPT_PRESENT=1) ); constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to 0+bo2na(C_IS_DUAL=1)) := (others => 5); constant C_USE_WSTRB : integer := 0; constant C_DPHASE_TIMEOUT : integer := 8; ------------------------------------------------------------------------------- -- Signal and Type Declarations ------------------------------------------------------------------------------- signal ip2bus_intrevent : std_logic_vector(0 to 1); signal GPIO_xferAck_i : std_logic; signal Bus2IP_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal Bus2IP1_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal Bus2IP2_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); -- IPIC Used Signals signal ip2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal bus2ip_addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1); signal bus2ip_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal bus2ip_rnw : std_logic; signal bus2ip_cs : std_logic_vector(0 to 0 + bo2na (C_INTERRUPT_PRESENT=1)); signal bus2ip_rdce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); signal bus2ip_wrce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); signal Intrpt_bus2ip_rdce : std_logic_vector(0 to 15); signal Intrpt_bus2ip_wrce : std_logic_vector(0 to 15); signal intr_wr_ce_or_reduce : std_logic; signal intr_rd_ce_or_reduce : std_logic; signal ip2Bus_RdAck_intr_reg_hole : std_logic; signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic; signal ip2Bus_WrAck_intr_reg_hole : std_logic; signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic; signal bus2ip_be : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH / 8) - 1); signal bus2ip_clk : std_logic; signal bus2ip_reset : std_logic; signal bus2ip_resetn : std_logic; signal intr2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal intr2bus_wrack : std_logic; signal intr2bus_rdack : std_logic; signal intr2bus_error : std_logic; signal ip2bus_data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal ip2bus_data_i_D1 : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal ip2bus_wrack_i : std_logic; signal ip2bus_wrack_i_D1 : std_logic; signal ip2bus_rdack_i : std_logic; signal ip2bus_rdack_i_D1 : std_logic; signal ip2bus_error_i : std_logic; signal IP2INTC_Irpt_i : std_logic; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- begin -- architecture IMP AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif generic map ( C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, C_S_AXI_MIN_SIZE => C_AXI_MIN_SIZE, C_USE_WSTRB => C_USE_WSTRB, C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY, C_FAMILY => C_FAMILY ) port map ( S_AXI_ACLK => s_axi_aclk, S_AXI_ARESETN => s_axi_aresetn, S_AXI_AWADDR => s_axi_awaddr, S_AXI_AWVALID => s_axi_awvalid, S_AXI_AWREADY => s_axi_awready, S_AXI_WDATA => s_axi_wdata, S_AXI_WSTRB => s_axi_wstrb, S_AXI_WVALID => s_axi_wvalid, S_AXI_WREADY => s_axi_wready, S_AXI_BRESP => s_axi_bresp, S_AXI_BVALID => s_axi_bvalid, S_AXI_BREADY => s_axi_bready, S_AXI_ARADDR => s_axi_araddr, S_AXI_ARVALID => s_axi_arvalid, S_AXI_ARREADY => s_axi_arready, S_AXI_RDATA => s_axi_rdata, S_AXI_RRESP => s_axi_rresp, S_AXI_RVALID => s_axi_rvalid, S_AXI_RREADY => s_axi_rready, -- IP Interconnect (IPIC) port signals Bus2IP_Clk => bus2ip_clk, Bus2IP_Resetn => bus2ip_resetn, IP2Bus_Data => ip2bus_data_i_D1, IP2Bus_WrAck => ip2bus_wrack_i_D1, IP2Bus_RdAck => ip2bus_rdack_i_D1, --IP2Bus_WrAck => ip2bus_wrack_i, --IP2Bus_RdAck => ip2bus_rdack_i, IP2Bus_Error => ip2bus_error_i, Bus2IP_Addr => bus2ip_addr, Bus2IP_Data => bus2ip_data, Bus2IP_RNW => bus2ip_rnw, Bus2IP_BE => bus2ip_be, Bus2IP_CS => bus2ip_cs, Bus2IP_RdCE => bus2ip_rdce, Bus2IP_WrCE => bus2ip_wrce ); ip2bus_data_i <= intr2bus_data or ip2bus_data; ip2bus_wrack_i <= intr2bus_wrack or (GPIO_xferAck_i and not(bus2ip_rnw)) or ip2Bus_WrAck_intr_reg_hole;-- Holes in Address range ip2bus_rdack_i <= intr2bus_rdack or (GPIO_xferAck_i and bus2ip_rnw) or ip2Bus_RdAck_intr_reg_hole; -- Holes in Address range I_WRACK_RDACK_DELAYS: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2bus_wrack_i_D1 <= '0'; ip2bus_rdack_i_D1 <= '0'; ip2bus_data_i_D1 <= (others => '0'); else ip2bus_wrack_i_D1 <= ip2bus_wrack_i; ip2bus_rdack_i_D1 <= ip2bus_rdack_i; ip2bus_data_i_D1 <= ip2bus_data_i; end if; end if; end process I_WRACK_RDACK_DELAYS; ip2bus_error_i <= intr2bus_error; ---------------------- --REG_RESET_FROM_IPIF: convert active low to active hig reset to rest of -- the core. ---------------------- REG_RESET_FROM_IPIF: process (s_axi_aclk) is begin if(s_axi_aclk'event and s_axi_aclk = '1') then bus2ip_reset <= not(bus2ip_resetn); end if; end process REG_RESET_FROM_IPIF; --------------------------------------------------------------------------- -- Interrupts --------------------------------------------------------------------------- INTR_CTRLR_GEN : if (C_INTERRUPT_PRESENT = 1) generate constant NUM_IPIF_IRPT_SRC : natural := 1; constant NUM_CE : integer := 16; signal errack_reserved : std_logic_vector(0 to 1); signal ipif_lvl_interrupts : std_logic_vector(0 to NUM_IPIF_IRPT_SRC-1); begin ipif_lvl_interrupts <= (others => '0'); errack_reserved <= (others => '0'); --- Addr 0X11c, 0X120, 0X128 valid addresses, remaining are holes Intrpt_bus2ip_rdce <= "0000000" & bus2ip_rdce(11) & bus2ip_rdce(12) & '0' & bus2ip_rdce(14) & "00000"; Intrpt_bus2ip_wrce <= "0000000" & bus2ip_wrce(11) & bus2ip_wrce(12) & '0' & bus2ip_wrce(14) & "00000"; intr_rd_ce_or_reduce <= or_reduce(bus2ip_rdce(4 to 10)) or Bus2IP_RdCE(13) or or_reduce(Bus2IP_RdCE(15 to 19)); intr_wr_ce_or_reduce <= or_reduce(bus2ip_wrce(4 to 10)) or bus2ip_wrce(13) or or_reduce(bus2ip_wrce(15 to 19)); I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2Bus_RdAck_intr_reg_hole <= '0'; ip2Bus_RdAck_intr_reg_hole_d1 <= '0'; else ip2Bus_RdAck_intr_reg_hole_d1 <= intr_rd_ce_or_reduce; ip2Bus_RdAck_intr_reg_hole <= intr_rd_ce_or_reduce and (not ip2Bus_RdAck_intr_reg_hole_d1); end if; end if; end process I_READ_ACK_INTR_HOLES; I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2Bus_WrAck_intr_reg_hole <= '0'; ip2Bus_WrAck_intr_reg_hole_d1 <= '0'; else ip2Bus_WrAck_intr_reg_hole_d1 <= intr_wr_ce_or_reduce; ip2Bus_WrAck_intr_reg_hole <= intr_wr_ce_or_reduce and (not ip2Bus_WrAck_intr_reg_hole_d1); end if; end if; end process I_WRITE_ACK_INTR_HOLES; INTERRUPT_CONTROL_I : entity interrupt_control_v3_1_4.interrupt_control generic map ( C_NUM_CE => NUM_CE, C_NUM_IPIF_IRPT_SRC => NUM_IPIF_IRPT_SRC, C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY, C_INCLUDE_DEV_PENCODER => false, C_INCLUDE_DEV_ISC => false, C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH ) port map ( -- Inputs From the IPIF Bus Bus2IP_Clk => Bus2IP_Clk, Bus2IP_Reset => bus2ip_reset, Bus2IP_Data => bus2ip_data, Bus2IP_BE => bus2ip_be, Interrupt_RdCE => Intrpt_bus2ip_rdce, Interrupt_WrCE => Intrpt_bus2ip_wrce, -- Interrupt inputs from the IPIF sources that will -- get registered in this design IPIF_Reg_Interrupts => errack_reserved, -- Level Interrupt inputs from the IPIF sources IPIF_Lvl_Interrupts => ipif_lvl_interrupts, -- Inputs from the IP Interface IP2Bus_IntrEvent => ip2bus_intrevent(IP_INTR_MODE_ARRAY'range), -- Final Device Interrupt Output Intr2Bus_DevIntr => IP2INTC_Irpt_i, -- Status Reply Outputs to the Bus Intr2Bus_DBus => intr2bus_data, Intr2Bus_WrAck => intr2bus_wrack, Intr2Bus_RdAck => intr2bus_rdack, Intr2Bus_Error => intr2bus_error, Intr2Bus_Retry => open, Intr2Bus_ToutSup => open ); -- registering interrupt I_INTR_DELAY: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2intc_irpt <= '0'; else ip2intc_irpt <= IP2INTC_Irpt_i; end if; end if; end process I_INTR_DELAY; end generate INTR_CTRLR_GEN; ----------------------------------------------------------------------- -- Assigning the intr2bus signal to zero's when interrupt is not -- present ----------------------------------------------------------------------- REMOVE_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate intr2bus_data <= (others => '0'); ip2intc_irpt <= '0'; intr2bus_error <= '0'; intr2bus_rdack <= '0'; intr2bus_wrack <= '0'; ip2Bus_WrAck_intr_reg_hole <= '0'; ip2Bus_RdAck_intr_reg_hole <= '0'; end generate REMOVE_INTERRUPT; gpio_core_1 : entity axi_gpio_v2_0_15.gpio_core generic map ( C_DW => C_S_AXI_DATA_WIDTH, C_AW => C_S_AXI_ADDR_WIDTH, C_GPIO_WIDTH => C_GPIO_WIDTH, C_GPIO2_WIDTH => C_GPIO2_WIDTH, C_MAX_GPIO_WIDTH => MAX_GPIO_WIDTH, C_INTERRUPT_PRESENT => C_INTERRUPT_PRESENT, C_DOUT_DEFAULT => C_DOUT_DEFAULT, C_TRI_DEFAULT => C_TRI_DEFAULT, C_IS_DUAL => C_IS_DUAL, C_ALL_OUTPUTS => C_ALL_OUTPUTS, C_ALL_INPUTS => C_ALL_INPUTS, C_ALL_INPUTS_2 => C_ALL_INPUTS_2, C_ALL_OUTPUTS_2 => C_ALL_OUTPUTS_2, C_DOUT_DEFAULT_2 => C_DOUT_DEFAULT_2, C_TRI_DEFAULT_2 => C_TRI_DEFAULT_2, C_FAMILY => C_FAMILY ) port map ( Clk => Bus2IP_Clk, Rst => bus2ip_reset, ABus_Reg => Bus2IP_Addr, BE_Reg => Bus2IP_BE(0 to C_S_AXI_DATA_WIDTH/8-1), DBus_Reg => Bus2IP_Data_i(0 to MAX_GPIO_WIDTH-1), RNW_Reg => Bus2IP_RNW, GPIO_DBus => IP2Bus_Data(0 to C_S_AXI_DATA_WIDTH-1), GPIO_xferAck => GPIO_xferAck_i, GPIO_Select => bus2ip_cs(0), GPIO_intr => ip2bus_intrevent(0), GPIO2_intr => ip2bus_intrevent(1), GPIO_IO_I => gpio_io_i, GPIO_IO_O => gpio_io_o, GPIO_IO_T => gpio_io_t, GPIO2_IO_I => gpio2_io_i, GPIO2_IO_O => gpio2_io_o, GPIO2_IO_T => gpio2_io_t ); Bus2IP_Data_i <= Bus2IP1_Data_i when bus2ip_cs(0) = '1' and bus2ip_addr (5) = '0'else Bus2IP2_Data_i; BUS_CONV_ch1 : for i in 0 to C_GPIO_WIDTH-1 generate Bus2IP1_Data_i(i) <= Bus2IP_Data(i+ C_S_AXI_DATA_WIDTH-C_GPIO_WIDTH); end generate BUS_CONV_ch1; BUS_CONV_ch2 : for i in 0 to C_GPIO2_WIDTH-1 generate Bus2IP2_Data_i(i) <= Bus2IP_Data(i+ C_S_AXI_DATA_WIDTH-C_GPIO2_WIDTH); end generate BUS_CONV_ch2; end architecture imp;
------------------------------------------------------------------------------- -- gpio_core - entity/architecture pair ------------------------------------------------------------------------------- -- ************************************************************************* -- DISCLAIMER OF LIABILITY -- -- This file contains proprietary and confidential information of -- Xilinx, Inc. ("Xilinx"), that is distributed under a license -- from Xilinx, and may be used, copied and/or disclosed only -- pursuant to the terms of a valid license agreement with Xilinx. -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx -- does not warrant that functions included in the Materials will -- meet the requirements of Licensee, or that the operation of the -- Materials will be uninterrupted or error-free, or that defects -- in the Materials will be corrected. Furthermore, Xilinx does -- not warrant or make any representations regarding use, or the -- results of the use, of the Materials in terms of correctness, -- accuracy, reliability or otherwise. -- -- Xilinx products are not designed or intended to be fail-safe, -- or for use in any application requiring fail-safe performance, -- such as life-support or safety devices or systems, Class III -- medical devices, nuclear facilities, applications related to -- the deployment of airbags, or any other applications that could -- lead to death, personal injury or severe property or -- environmental damage (individually and collectively, "critical -- applications"). Customer assumes the sole risk and liability -- of any use of Xilinx products in critical applications, -- subject only to applicable laws and regulations governing -- limitations on product liability. -- -- Copyright 2009 Xilinx, Inc. -- All rights reserved. -- -- This disclaimer and copyright notice must be retained as part -- of this file at all times. -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: gpio_core.vhd -- Version: v1.01a -- Description: General Purpose I/O for AXI Interface -- ------------------------------------------------------------------------------- -- Structure: -- axi_gpio.vhd -- -- axi_lite_ipif.vhd -- -- interrupt_control.vhd -- -- gpio_core.vhd -- ------------------------------------------------------------------------------- -- -- Author: KSB -- History: -- ~~~~~~~~~~~~~~ -- KSB 09/15/09 -- ^^^^^^^^^^^^^^ -- ~~~~~~~~~~~~~~ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; library lib_cdc_v1_0_2; ------------------------------------------------------------------------------- -- Definition of Generics : -- ------------------------------------------------------------------------------- -- C_DW -- Data width of PLB BUS. -- C_AW -- Address width of PLB BUS. -- C_GPIO_WIDTH -- GPIO Data Bus width. -- C_GPIO2_WIDTH -- GPIO2 Data Bus width. -- C_INTERRUPT_PRESENT -- GPIO Interrupt. -- C_DOUT_DEFAULT -- GPIO_DATA Register reset value. -- C_TRI_DEFAULT -- GPIO_TRI Register reset value. -- C_IS_DUAL -- Dual Channel GPIO. -- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value. -- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value. -- C_FAMILY -- XILINX FPGA family ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Definition of Ports -- ------------------------------------------------------------------------------- -- Clk -- Input clock -- Rst -- Reset -- ABus_Reg -- Bus to IP address -- BE_Reg -- Bus to IP byte enables -- DBus_Reg -- Bus to IP data bus -- RNW_Reg -- Bus to IP read write control -- GPIO_DBus -- IP to Bus data bus -- GPIO_xferAck -- GPIO transfer acknowledge -- GPIO_intr -- GPIO channel 1 interrupt to IPIC -- GPIO2_intr -- GPIO channel 2 interrupt to IPIC -- GPIO_Select -- GPIO select -- -- GPIO_IO_I -- Channel 1 General purpose I/O in port -- GPIO_IO_O -- Channel 1 General purpose I/O out port -- GPIO_IO_T -- Channel 1 General purpose I/O TRI-STATE control port -- GPIO2_IO_I -- Channel 2 General purpose I/O in port -- GPIO2_IO_O -- Channel 2 General purpose I/O out port -- GPIO2_IO_T -- Channel 2 General purpose I/O TRI-STATE control port ------------------------------------------------------------------------------- entity GPIO_Core is generic ( C_DW : integer := 32; C_AW : integer := 32; C_GPIO_WIDTH : integer := 32; C_GPIO2_WIDTH : integer := 32; C_MAX_GPIO_WIDTH : integer := 32; C_INTERRUPT_PRESENT : integer := 0; C_DOUT_DEFAULT : std_logic_vector (0 to 31) := X"0000_0000"; C_TRI_DEFAULT : std_logic_vector (0 to 31) := X"FFFF_FFFF"; C_IS_DUAL : integer := 0; C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013 C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013 C_ALL_INPUTS : integer range 0 to 1 := 0; C_ALL_INPUTS_2 : integer range 0 to 1 := 0; C_DOUT_DEFAULT_2 : std_logic_vector (0 to 31) := X"0000_0000"; C_TRI_DEFAULT_2 : std_logic_vector (0 to 31) := X"FFFF_FFFF"; C_FAMILY : string := "virtex7" ); port ( Clk : in std_logic; Rst : in std_logic; ABus_Reg : in std_logic_vector(0 to C_AW-1); BE_Reg : in std_logic_vector(0 to C_DW/8-1); DBus_Reg : in std_logic_vector(0 to C_MAX_GPIO_WIDTH-1); RNW_Reg : in std_logic; GPIO_DBus : out std_logic_vector(0 to C_DW-1); GPIO_xferAck : out std_logic; GPIO_intr : out std_logic; GPIO2_intr : out std_logic; GPIO_Select : in std_logic; GPIO_IO_I : in std_logic_vector(0 to C_GPIO_WIDTH-1); GPIO_IO_O : out std_logic_vector(0 to C_GPIO_WIDTH-1); GPIO_IO_T : out std_logic_vector(0 to C_GPIO_WIDTH-1); GPIO2_IO_I : in std_logic_vector(0 to C_GPIO2_WIDTH-1); GPIO2_IO_O : out std_logic_vector(0 to C_GPIO2_WIDTH-1); GPIO2_IO_T : out std_logic_vector(0 to C_GPIO2_WIDTH-1) ); end entity GPIO_Core; ------------------------------------------------------------------------------- -- Architecture section ------------------------------------------------------------------------------- architecture IMP of GPIO_Core is -- Pragma Added to supress synth warnings attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes"; ---------------------------------------------------------------------- -- Function for Reduction OR ---------------------------------------------------------------------- function or_reduce(l : std_logic_vector) return std_logic is variable v : std_logic := '0'; begin for i in l'range loop v := v or l(i); end loop; return v; end; --------------------------------------------------------------------- -- End of Function ------------------------------------------------------------------- --constant GPIO_G_W : integer = C_GPIO_WIDTH when (C_GPIO_WIDTH > C_GPIO2_WIDTH) else C_GPIO2_; signal gpio_Data_Select : std_logic_vector(0 to C_IS_DUAL); signal gpio_OE_Select : std_logic_vector(0 to C_IS_DUAL); signal Read_Reg_Rst : STD_LOGIC; signal Read_Reg_In : std_logic_vector(0 to C_GPIO_WIDTH-1); signal Read_Reg_CE : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_Data_Out : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_DOUT_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1); signal gpio_Data_In : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_in_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_in_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_io_i_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_io_i_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_OE : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_TRI_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1); signal GPIO_DBus_i : std_logic_vector(0 to C_DW-1); signal gpio_data_in_xor : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_data_in_xor_reg : std_logic_vector(0 to C_GPIO_WIDTH-1); signal or_ints : std_logic_vector(0 to 0); signal or_ints2 : std_logic_vector(0 to 0); signal iGPIO_xferAck : STD_LOGIC; signal gpio_xferAck_Reg : STD_LOGIC; signal dout_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1); signal tri_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1); signal reset_zeros : std_logic_vector(0 to C_GPIO_WIDTH-1); signal dout2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal tri2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal reset2_zeros : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio_reg_en : std_logic; begin -- architecture IMP reset_zeros <= (others => '0'); reset2_zeros <= (others => '0'); TIE_DEFAULTS_GENERATE : if C_DW >= C_GPIO_WIDTH generate SELECT_BITS_GENERATE : for i in 0 to C_GPIO_WIDTH-1 generate dout_default_i(i) <= C_DOUT_DEFAULT(i-C_GPIO_WIDTH+C_DW); tri_default_i(i) <= C_TRI_DEFAULT(i-C_GPIO_WIDTH+C_DW); end generate SELECT_BITS_GENERATE; end generate TIE_DEFAULTS_GENERATE; TIE_DEFAULTS_2_GENERATE : if C_DW >= C_GPIO2_WIDTH generate SELECT_BITS_2_GENERATE : for i in 0 to C_GPIO2_WIDTH-1 generate dout2_default_i(i) <= C_DOUT_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW); tri2_default_i(i) <= C_TRI_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW); end generate SELECT_BITS_2_GENERATE; end generate TIE_DEFAULTS_2_GENERATE; Read_Reg_Rst <= iGPIO_xferAck or gpio_xferAck_Reg or (not GPIO_Select) or (GPIO_Select and not RNW_Reg); gpio_reg_en <= GPIO_Select when (ABus_Reg(0) = '0') else '0'; ----------------------------------------------------------------------------- -- XFER_ACK_PROCESS ----------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ----------------------------------------------------------------------------- XFER_ACK_PROCESS : process (Clk) is begin if (Clk'EVENT and Clk = '1') then if (Rst = '1') then iGPIO_xferAck <= '0'; else iGPIO_xferAck <= GPIO_Select and not gpio_xferAck_Reg; if iGPIO_xferAck = '1' then iGPIO_xferAck <= '0'; end if; end if; end if; end process XFER_ACK_PROCESS; ----------------------------------------------------------------------------- -- DELAYED_XFER_ACK_PROCESS ----------------------------------------------------------------------------- -- Single Reg stage to make Transfer Ack period one clock pulse wide ----------------------------------------------------------------------------- DELAYED_XFER_ACK_PROCESS : process (Clk) is begin if (Clk'EVENT and Clk = '1') then if (Rst = '1') then gpio_xferAck_Reg <= '0'; else gpio_xferAck_Reg <= iGPIO_xferAck; end if; end if; end process DELAYED_XFER_ACK_PROCESS; GPIO_xferAck <= iGPIO_xferAck; ----------------------------------------------------------------------------- -- Drive GPIO interrupts to '0' when interrupt not present ----------------------------------------------------------------------------- DONT_GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate gpio_intr <= '0'; gpio2_intr <= '0'; end generate DONT_GEN_INTERRUPT; ---------------------------------------------------------------------------- -- When only one channel is used, the additional logic for the second -- channel ports is not present ----------------------------------------------------------------------------- Not_Dual : if (C_IS_DUAL = 0) generate GPIO2_IO_O <= C_DOUT_DEFAULT(0 to C_GPIO2_WIDTH-1); GPIO2_IO_T <= C_TRI_DEFAULT_2(0 to C_GPIO2_WIDTH-1); ALLOUT_ND : if (C_ALL_OUTPUTS = 1) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLOUT_ND; ALLIN1_ND : if (C_ALL_INPUTS = 1) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLIN1_ND; ALLOUT0_ND : if (C_ALL_OUTPUTS = 0 and C_ALL_INPUTS = 0) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else if (gpio_OE(i) = '0' and gpio_OE_Select(0) = '0')then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); end if; --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLOUT0_ND; TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0'); end generate TIE_DBUS_GENERATE; ----------------------------------------------------------------------------- -- GPIO_DBUS_PROCESS ----------------------------------------------------------------------------- -- This process generates the GPIO DATA BUS from the GPIO_DBUS_I based on -- the channel select signals ----------------------------------------------------------------------------- GPIO_DBus <= GPIO_DBus_i; ----------------------------------------------------------------------------- -- REG_SELECT_PROCESS ----------------------------------------------------------------------------- -- GPIO REGISTER selection decoder for single channel configuration ----------------------------------------------------------------------------- --REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is begin gpio_Data_Select(0) <= '0'; gpio_OE_Select(0) <= '0'; --if GPIO_Select = '1' then if gpio_reg_en = '1' then if (ABus_Reg(5) = '0') then case ABus_Reg(6) is -- bit A29 when '0' => gpio_Data_Select(0) <= '1'; when '1' => gpio_OE_Select(0) <= '1'; -- coverage off when others => null; -- coverage on end case; end if; end if; end process REG_SELECT_PROCESS; INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 0, C_VECTOR_WIDTH => C_GPIO_WIDTH, C_MTBF_STAGES => 4 ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => '0', prmry_vect_in => GPIO_IO_I, scndry_aclk => Clk, scndry_resetn => '0', scndry_out => open, scndry_vect_out => gpio_io_i_d2 ); --------------------------------------------------------------------------- -- GPIO_INDATA_BIRDIR_PROCESS --------------------------------------------------------------------------- -- Reading of channel 1 data from Bidirectional GPIO port -- to GPIO_DATA REGISTER --------------------------------------------------------------------------- GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then -- gpio_io_i_d1 <= GPIO_IO_I; -- gpio_io_i_d2 <= gpio_io_i_d1; gpio_Data_In <= gpio_io_i_d2; end if; end process GPIO_INDATA_BIRDIR_PROCESS; --------------------------------------------------------------------------- -- GPIO_OUTDATA_PROCESS --------------------------------------------------------------------------- -- Writing to Channel 1 GPIO_DATA REGISTER --------------------------------------------------------------------------- GPIO_OUTDATA_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio_Data_Out <= dout_default_i; elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO_WIDTH-1 loop gpio_Data_Out(i) <= DBus_Reg(i); end loop; end if; end if; end process GPIO_OUTDATA_PROCESS; --------------------------------------------------------------------------- -- READ_MUX_PROCESS --------------------------------------------------------------------------- -- Selects GPIO_TRI control or GPIO_DATA Register to be read --------------------------------------------------------------------------- READ_MUX_PROCESS : process (gpio_Data_In, gpio_Data_Select, gpio_OE, gpio_OE_Select,gpio_Data_Out) is begin Read_Reg_In <= (others => '0'); if gpio_Data_Select(0) = '1' then Read_Reg_In <= gpio_Data_In; --Read_Reg_In <= gpio_Data_In; elsif gpio_OE_Select(0) = '1' then Read_Reg_In <= gpio_OE; end if; end process READ_MUX_PROCESS; --------------------------------------------------------------------------- -- GPIO_OE_PROCESS --------------------------------------------------------------------------- -- Writing to Channel 1 GPIO_TRI Control REGISTER --------------------------------------------------------------------------- GPIO_OE_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio_OE <= tri_default_i; elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO_WIDTH-1 loop gpio_OE(i) <= DBus_Reg(i); end loop; end if; end if; end process GPIO_OE_PROCESS; GPIO_IO_O <= gpio_Data_Out; GPIO_IO_T <= gpio_OE; ---------------------------------------------------------------------------- -- INTERRUPT IS PRESENT ---------------------------------------------------------------------------- -- When the C_INTERRUPT_PRESENT=1, the interrupt is driven based on whether -- there is a change in the data coming in at the GPIO_IO_I port or GPIO_In -- port ---------------------------------------------------------------------------- GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 1) generate gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2; ------------------------------------------------------------------------- -- An interrupt conditon exists if there is a change on any bit. ------------------------------------------------------------------------- or_ints(0) <= or_reduce(gpio_data_in_xor_reg); ------------------------------------------------------------------------- -- Registering Interrupt condition ------------------------------------------------------------------------- REGISTER_XOR_INTR : process (Clk) is begin if (Clk'EVENT and Clk = '1') then if (Rst = '1') then gpio_data_in_xor_reg <= reset_zeros; GPIO_intr <= '0'; else gpio_data_in_xor_reg <= gpio_data_in_xor; GPIO_intr <= or_ints(0); end if; end if; end process REGISTER_XOR_INTR; gpio2_intr <= '0'; -- Channel 2 interrupt is driven low end generate GEN_INTERRUPT; end generate Not_Dual; ---)(------------------------------------------------------------------------ -- When both the channels are used, the additional logic for the second -- channel ports ----------------------------------------------------------------------------- Dual : if (C_IS_DUAL = 1) generate signal gpio2_Data_In : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_in_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_in_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_io_i_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_io_i_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_data_in_xor : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_data_in_xor_reg : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_Data_Out : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_DOUT_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1); signal gpio2_OE : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_TRI_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1); signal Read_Reg2_In : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal Read_Reg2_CE : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal GPIO2_DBus_i : std_logic_vector(0 to C_DW-1); begin ALLOUT0_ND_G0 : if (C_ALL_OUTPUTS = 0 and C_ALL_INPUTS = 0) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else if (gpio_OE(i) = '0' and gpio_OE_Select(0) = '0') then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); end if; --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLOUT0_ND_G0; ALLIN0_ND_G0 : if (C_ALL_INPUTS = 1) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLIN0_ND_G0; ALLOUT0_ND_G1 : if (C_ALL_OUTPUTS = 1) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate begin -------------------------------------------------------------------------- -- GPIO_DBUS_I_PROCESS -------------------------------------------------------------------------- -- This process generates the GPIO CHANNEL1 DATA BUS -------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLOUT0_ND_G1; TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0'); end generate TIE_DBUS_GENERATE; ALLIN0_ND_G2 : if (C_ALL_OUTPUTS_2 = 0 and C_ALL_INPUTS_2 = 1) generate READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate -------------------------------------------------------------------------- -- GPIO2_DBUS_I_PROCESS -------------------------------------------------------------------------- -- This process generates the GPIO CHANNEL2 DATA BUS -------------------------------------------------------------------------- GPIO2_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0'; else GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i); --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); end if; end if; end process; end generate READ_REG2_GEN; end generate ALLIN0_ND_G2; ALLOUT0_ND_G2 : if (C_ALL_OUTPUTS_2 = 0 and C_ALL_INPUTS_2 = 0) generate READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate -------------------------------------------------------------------------- -- GPIO2_DBUS_I_PROCESS -------------------------------------------------------------------------- -- This process generates the GPIO CHANNEL2 DATA BUS -------------------------------------------------------------------------- GPIO2_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0'; else if (gpio2_OE(i) = '0' and gpio_OE_Select(1) = '0') then GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i); else GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i); end if; -- GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i) when (gpio2_OE(i) = '1') else Read_Reg2_In(i); --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); end if; end if; end process; end generate READ_REG2_GEN; end generate ALLOUT0_ND_G2; ALLOUT1_ND_G2 : if (C_ALL_OUTPUTS_2 = 1) generate READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate -------------------------------------------------------------------------- -- GPIO2_DBUS_I_PROCESS -------------------------------------------------------------------------- -- This process generates the GPIO CHANNEL2 DATA BUS -------------------------------------------------------------------------- GPIO2_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0'; else GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i); end if; end if; end process; end generate READ_REG2_GEN; end generate ALLOUT1_ND_G2; TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0'); end generate TIE_DBUS2_GENERATE; --------------------------------------------------------------------------- -- GPIO_DBUS_PROCESS --------------------------------------------------------------------------- -- This process generates the GPIO DATA BUS from the GPIO_DBUS_I and -- GPIO2_DBUS_I based on which channel is selected --------------------------------------------------------------------------- GPIO_DBus <= GPIO_DBus_i when (((gpio_Data_Select(0) = '1') or (gpio_OE_Select(0) = '1')) and (RNW_Reg = '1')) else GPIO2_DBus_i; ----------------------------------------------------------------------------- -- DUAL_REG_SELECT_PROCESS ----------------------------------------------------------------------------- -- GPIO REGISTER selection decoder for Dual channel configuration ----------------------------------------------------------------------------- --DUAL_REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is DUAL_REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is variable ABus_reg_select : std_logic_vector(0 to 1); begin ABus_reg_select := ABus_Reg(5 to 6); gpio_Data_Select <= (others => '0'); gpio_OE_Select <= (others => '0'); --if GPIO_Select = '1' then if gpio_reg_en = '1' then -- case ABus_Reg(28 to 29) is -- bit A28,A29 for dual case ABus_reg_select is -- bit A28,A29 for dual when "00" => gpio_Data_Select(0) <= '1'; when "01" => gpio_OE_Select(0) <= '1'; when "10" => gpio_Data_Select(1) <= '1'; when "11" => gpio_OE_Select(1) <= '1'; -- coverage off when others => null; -- coverage on end case; end if; end process DUAL_REG_SELECT_PROCESS; --------------------------------------------------------------------------- -- GPIO_INDATA_BIRDIR_PROCESS --------------------------------------------------------------------------- -- Reading of channel 1 data from Bidirectional GPIO port -- to GPIO_DATA REGISTER --------------------------------------------------------------------------- INPUT_DOUBLE_REGS4 : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 0, C_VECTOR_WIDTH => C_GPIO_WIDTH, C_MTBF_STAGES => 4 ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => '0', prmry_vect_in => GPIO_IO_I, scndry_aclk => Clk, scndry_resetn => '0', scndry_out => open, scndry_vect_out => gpio_io_i_d2 ); GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then -- gpio_io_i_d1 <= GPIO_IO_I; -- gpio_io_i_d2 <= gpio_io_i_d1; --if (C_ALL_OUTPUTS = '1') then -- gpio_Data_In <= gpio_Data_Out; -- else gpio_Data_In <= gpio_io_i_d2; -- end if; end if; end process GPIO_INDATA_BIRDIR_PROCESS; INPUT_DOUBLE_REGS5 : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 0, C_VECTOR_WIDTH => C_GPIO2_WIDTH, C_MTBF_STAGES => 4 ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => '0', prmry_vect_in => GPIO2_IO_I, scndry_aclk => Clk, scndry_resetn => '0', scndry_out => open, scndry_vect_out => gpio2_io_i_d2 ); --------------------------------------------------------------------------- -- GPIO2_INDATA_BIRDIR_PROCESS --------------------------------------------------------------------------- -- Reading of channel 2 data from Bidirectional GPIO2 port -- to GPIO2_DATA REGISTER --------------------------------------------------------------------------- GPIO2_INDATA_BIRDIR_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then -- gpio2_io_i_d1 <= GPIO2_IO_I; -- gpio2_io_i_d2 <= gpio2_io_i_d1; -- if (C_ALL_OUTPUTS = '1') then -- gpio2_Data_In <= gpio2_Data_Out; -- else gpio2_Data_In <= gpio2_io_i_d2; -- end if; end if; end process GPIO2_INDATA_BIRDIR_PROCESS; --------------------------------------------------------------------------- -- GPIO_OUTDATA_PROCESS_0_0 --------------------------------------------------------------------------- -- Writing to Channel 1 GPIO_DATA REGISTER --------------------------------------------------------------------------- GPIO_OUTDATA_PROCESS_0_0 : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio_Data_Out <= dout_default_i; elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO_WIDTH-1 loop gpio_Data_Out(i) <= DBus_Reg(i); end loop; end if; end if; end process GPIO_OUTDATA_PROCESS_0_0; --------------------------------------------------------------------------- -- GPIO_OE_PROCESS_0_0 --------------------------------------------------------------------------- -- Writing to Channel 1 GPIO_TRI Control REGISTER --------------------------------------------------------------------------- GPIO_OE_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio_OE <= tri_default_i; elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO_WIDTH-1 loop gpio_OE(i) <= DBus_Reg(i); -- end if; end loop; end if; end if; end process GPIO_OE_PROCESS; --------------------------------------------------------------------------- -- GPIO2_OUTDATA_PROCESS_0_0 --------------------------------------------------------------------------- -- Writing to Channel 2 GPIO2_DATA REGISTER --------------------------------------------------------------------------- GPIO2_OUTDATA_PROCESS_0_0 : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio2_Data_Out <= dout2_default_i; elsif gpio_Data_Select(1) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO2_WIDTH-1 loop gpio2_Data_Out(i) <= DBus_Reg(i); -- end if; end loop; end if; end if; end process GPIO2_OUTDATA_PROCESS_0_0; --------------------------------------------------------------------------- -- GPIO2_OE_PROCESS_0_0 --------------------------------------------------------------------------- -- Writing to Channel 2 GPIO2_TRI Control REGISTER --------------------------------------------------------------------------- GPIO2_OE_PROCESS_0_0 : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio2_OE <= tri2_default_i; elsif gpio_OE_Select(1) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO2_WIDTH-1 loop gpio2_OE(i) <= DBus_Reg(i); end loop; end if; end if; end process GPIO2_OE_PROCESS_0_0; GPIO_IO_O <= gpio_Data_Out; GPIO_IO_T <= gpio_OE; GPIO2_IO_O <= gpio2_Data_Out; GPIO2_IO_T <= gpio2_OE; --------------------------------------------------------------------------- -- READ_MUX_PROCESS_0_0 --------------------------------------------------------------------------- -- Selects among Channel 1 GPIO_DATA ,GPIO_TRI and Channel 2 GPIO2_DATA -- GPIO2_TRI REGISTERS for reading --------------------------------------------------------------------------- READ_MUX_PROCESS_0_0 : process (gpio2_Data_In, gpio2_OE, gpio_Data_In, gpio_Data_Select, gpio_OE, gpio_OE_Select,gpio_Data_Out,gpio2_Data_Out) is begin Read_Reg_In <= (others => '0'); Read_Reg2_In <= (others => '0'); if gpio_Data_Select(0) = '1' then Read_Reg_In <= gpio_Data_In; --Read_Reg_In <= gpio_Data_In; elsif gpio_OE_Select(0) = '1' then Read_Reg_In <= gpio_OE; elsif gpio_Data_Select(1) = '1' then Read_Reg2_In <= gpio2_Data_In; --Read_Reg2_In <= gpio2_Data_In; --Read_Reg2_In<= gpio2_Data_In; elsif gpio_OE_Select(1) = '1' then Read_Reg2_In <= gpio2_OE; end if; end process READ_MUX_PROCESS_0_0; --------------------------------------------------------------------------- -- INTERRUPT IS PRESENT --------------------------------------------------------------------------- gen_interrupt_dual : if (C_INTERRUPT_PRESENT = 1) generate gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2; gpio2_data_in_xor <= gpio2_Data_In xor gpio2_io_i_d2; ------------------------------------------------------------------------- -- An interrupt conditon exists if there is a change any bit. ------------------------------------------------------------------------- or_ints(0) <= or_reduce(gpio_data_in_xor_reg); or_ints2(0) <= or_reduce(gpio2_data_in_xor_reg); ------------------------------------------------------------------------- -- Registering Interrupt condition ------------------------------------------------------------------------- REGISTER_XORs_INTRs : process (Clk) is begin if (Clk'EVENT and Clk = '1') then if (Rst = '1') then gpio_data_in_xor_reg <= reset_zeros; gpio2_data_in_xor_reg <= reset2_zeros; GPIO_intr <= '0'; GPIO2_intr <= '0'; else gpio_data_in_xor_reg <= gpio_data_in_xor; gpio2_data_in_xor_reg <= gpio2_data_in_xor; GPIO_intr <= or_ints(0); GPIO2_intr <= or_ints2(0); end if; end if; end process REGISTER_XORs_INTRs; end generate gen_interrupt_dual; end generate Dual; end architecture IMP; ------------------------------------------------------------------------------- -- AXI_GPIO - entity/architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************ -- DISCLAIMER OF LIABILITY -- -- This file contains proprietary and confidential information of -- Xilinx, Inc. ("Xilinx"), that is distributed under a license -- from Xilinx, and may be used, copied and/or disclosed only -- pursuant to the terms of a valid license agreement with Xilinx. -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx -- does not warrant that functions included in the Materials will -- meet the requirements of Licensee, or that the operation of the -- Materials will be uninterrupted or error-free, or that defects -- in the Materials will be corrected. Furthermore, Xilinx does -- not warrant or make any representations regarding use, or the -- results of the use, of the Materials in terms of correctness, -- accuracy, reliability or otherwise. -- -- Xilinx products are not designed or intended to be fail-safe, -- or for use in any application requiring fail-safe performance, -- such as life-support or safety devices or systems, Class III -- medical devices, nuclear facilities, applications related to -- the deployment of airbags, or any other applications that could -- lead to death, personal injury or severe property or -- environmental damage (individually and collectively, "critical -- applications"). Customer assumes the sole risk and liability -- of any use of Xilinx products in critical applications, -- subject only to applicable laws and regulations governing -- limitations on product liability. -- -- Copyright 2009 Xilinx, Inc. -- All rights reserved. -- -- This disclaimer and copyright notice must be retained as part -- of this file at all times. -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_gpio.vhd -- Version: v2.0 -- Description: General Purpose I/O for AXI Interface -- ------------------------------------------------------------------------------- -- Structure: -- axi_gpio.vhd -- -- axi_lite_ipif.vhd -- -- interrupt_control.vhd -- -- gpio_core.vhd ------------------------------------------------------------------------------- -- Author: KSB -- History: -- ~~~~~~~~~~~~~~ -- KSB 07/28/09 -- ^^^^^^^^^^^^^^ -- First version of axi_gpio. Based on xps_gpio 2.00a -- -- KSB 05/20/10 -- ^^^^^^^^^^^^^^ -- Updated for holes in address range -- ~~~~~~~~~~~~~~ -- VB 09/23/10 -- ^^^^^^^^^^^^^^ -- Updated for axi_lite_ipfi_v1_01_a -- ~~~~~~~~~~~~~~ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; use std.textio.all; ------------------------------------------------------------------------------- -- AXI common package of the proc common library is used for different -- function declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- axi_gpio_v2_0_15 library is used for axi4 component declarations ------------------------------------------------------------------------------- library axi_lite_ipif_v3_0_4; use axi_lite_ipif_v3_0_4.ipif_pkg.calc_num_ce; use axi_lite_ipif_v3_0_4.ipif_pkg.INTEGER_ARRAY_TYPE; use axi_lite_ipif_v3_0_4.ipif_pkg.SLV64_ARRAY_TYPE; ------------------------------------------------------------------------------- -- axi_gpio_v2_0_15 library is used for interrupt controller component -- declarations ------------------------------------------------------------------------------- library interrupt_control_v3_1_4; ------------------------------------------------------------------------------- -- axi_gpio_v2_0_15 library is used for axi_gpio component declarations ------------------------------------------------------------------------------- library axi_gpio_v2_0_15; ------------------------------------------------------------------------------- -- Defination of Generics : -- ------------------------------------------------------------------------------- -- AXI generics -- C_BASEADDR -- Base address of the core -- C_HIGHADDR -- Permits alias of address space -- by making greater than xFFF -- C_S_AXI_ADDR_WIDTH -- Width of AXI Address interface (in bits) -- C_S_AXI_DATA_WIDTH -- Width of the AXI Data interface (in bits) -- C_FAMILY -- XILINX FPGA family -- C_INSTANCE -- Instance name ot the core in the EDK system -- C_GPIO_WIDTH -- GPIO Data Bus width. -- C_ALL_INPUTS -- Inputs Only. -- C_INTERRUPT_PRESENT -- GPIO Interrupt. -- C_IS_BIDIR -- Selects gpio_io_i as input. -- C_DOUT_DEFAULT -- GPIO_DATA Register reset value. -- C_TRI_DEFAULT -- GPIO_TRI Register reset value. -- C_IS_DUAL -- Dual Channel GPIO. -- C_ALL_INPUTS_2 -- Channel2 Inputs only. -- C_IS_BIDIR_2 -- Selects gpio2_io_i as input. -- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value. -- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value. ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Defination of Ports -- ------------------------------------------------------------------------------- -- AXI signals -- s_axi_awaddr -- AXI Write address -- s_axi_awvalid -- Write address valid -- s_axi_awready -- Write address ready -- s_axi_wdata -- Write data -- s_axi_wstrb -- Write strobes -- s_axi_wvalid -- Write valid -- s_axi_wready -- Write ready -- s_axi_bresp -- Write response -- s_axi_bvalid -- Write response valid -- s_axi_bready -- Response ready -- s_axi_araddr -- Read address -- s_axi_arvalid -- Read address valid -- s_axi_arready -- Read address ready -- s_axi_rdata -- Read data -- s_axi_rresp -- Read response -- s_axi_rvalid -- Read valid -- s_axi_rready -- Read ready -- GPIO Signals -- gpio_io_i -- Channel 1 General purpose I/O in port -- gpio_io_o -- Channel 1 General purpose I/O out port -- gpio_io_t -- Channel 1 General purpose I/O -- TRI-STATE control port -- gpio2_io_i -- Channel 2 General purpose I/O in port -- gpio2_io_o -- Channel 2 General purpose I/O out port -- gpio2_io_t -- Channel 2 General purpose I/O -- TRI-STATE control port -- System Signals -- s_axi_aclk -- AXI Clock -- s_axi_aresetn -- AXI Reset -- ip2intc_irpt -- AXI GPIO Interrupt ------------------------------------------------------------------------------- entity axi_gpio is generic ( -- -- System Parameter C_FAMILY : string := "virtex7"; -- -- AXI Parameters C_S_AXI_ADDR_WIDTH : integer range 9 to 9 := 9; C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32; -- -- GPIO Parameter C_GPIO_WIDTH : integer range 1 to 32 := 32; C_GPIO2_WIDTH : integer range 1 to 32 := 32; C_ALL_INPUTS : integer range 0 to 1 := 0; C_ALL_INPUTS_2 : integer range 0 to 1 := 0; C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013 C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013 C_INTERRUPT_PRESENT : integer range 0 to 1 := 0; C_DOUT_DEFAULT : std_logic_vector (31 downto 0) := X"0000_0000"; C_TRI_DEFAULT : std_logic_vector (31 downto 0) := X"FFFF_FFFF"; C_IS_DUAL : integer range 0 to 1 := 0; C_DOUT_DEFAULT_2 : std_logic_vector (31 downto 0) := X"0000_0000"; C_TRI_DEFAULT_2 : std_logic_vector (31 downto 0) := X"FFFF_FFFF" ); port ( -- AXI interface Signals -------------------------------------------------- s_axi_aclk : in std_logic; s_axi_aresetn : in std_logic; s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); s_axi_wvalid : in std_logic; s_axi_wready : out std_logic; s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_arvalid : in std_logic; s_axi_arready : out std_logic; s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rvalid : out std_logic; s_axi_rready : in std_logic; -- Interrupt--------------------------------------------------------------- ip2intc_irpt : out std_logic; -- GPIO Signals------------------------------------------------------------ gpio_io_i : in std_logic_vector(C_GPIO_WIDTH-1 downto 0); gpio_io_o : out std_logic_vector(C_GPIO_WIDTH-1 downto 0); gpio_io_t : out std_logic_vector(C_GPIO_WIDTH-1 downto 0); gpio2_io_i : in std_logic_vector(C_GPIO2_WIDTH-1 downto 0); gpio2_io_o : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0); gpio2_io_t : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0) ); ------------------------------------------------------------------------------- -- fan-out attributes for XST ------------------------------------------------------------------------------- attribute MAX_FANOUT : string; attribute MAX_FANOUT of s_axi_aclk : signal is "10000"; attribute MAX_FANOUT of s_axi_aresetn : signal is "10000"; ------------------------------------------------------------------------------- -- Attributes for MPD file ------------------------------------------------------------------------------- attribute IP_GROUP : string ; attribute IP_GROUP of axi_gpio : entity is "LOGICORE"; attribute SIGIS : string ; attribute SIGIS of s_axi_aclk : signal is "Clk"; attribute SIGIS of s_axi_aresetn : signal is "Rst"; attribute SIGIS of ip2intc_irpt : signal is "INTR_LEVEL_HIGH"; end entity axi_gpio; ------------------------------------------------------------------------------- -- Architecture Section ------------------------------------------------------------------------------- architecture imp of axi_gpio is -- Pragma Added to supress synth warnings attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; ------------------------------------------------------------------------------- -- constant added for webtalk information ------------------------------------------------------------------------------- --function chr(sl: std_logic) return character is -- variable c: character; -- begin -- case sl is -- when '0' => c:= '0'; -- when '1' => c:= '1'; -- when 'Z' => c:= 'Z'; -- when 'U' => c:= 'U'; -- when 'X' => c:= 'X'; -- when 'W' => c:= 'W'; -- when 'L' => c:= 'L'; -- when 'H' => c:= 'H'; -- when '-' => c:= '-'; -- end case; -- return c; -- end chr; -- --function str(slv: std_logic_vector) return string is -- variable result : string (1 to slv'length); -- variable r : integer; -- begin -- r := 1; -- for i in slv'range loop -- result(r) := chr(slv(i)); -- r := r + 1; -- end loop; -- return result; -- end str; type bo2na_type is array (boolean) of natural; -- boolean to --natural conversion constant bo2na : bo2na_type := (false => 0, true => 1); ------------------------------------------------------------------------------- -- Function Declarations ------------------------------------------------------------------------------- type BOOLEAN_ARRAY_TYPE is array(natural range <>) of boolean; ---------------------------------------------------------------------------- -- This function returns the number of elements that are true in -- a boolean array. ---------------------------------------------------------------------------- function num_set( ba : BOOLEAN_ARRAY_TYPE ) return natural is variable n : natural := 0; begin for i in ba'range loop n := n + bo2na(ba(i)); end loop; return n; end; ---------------------------------------------------------------------------- -- This function returns a num_ce integer array that is constructed by -- taking only those elements of superset num_ce integer array -- that will be defined by the current case. -- The superset num_ce array is given by parameter num_ce_by_ard. -- The current case the ard elements that will be used is given -- by parameter defined_ards. ---------------------------------------------------------------------------- function qual_ard_num_ce_array( defined_ards : BOOLEAN_ARRAY_TYPE; num_ce_by_ard : INTEGER_ARRAY_TYPE ) return INTEGER_ARRAY_TYPE is variable res : INTEGER_ARRAY_TYPE(num_set(defined_ards)-1 downto 0); variable i : natural := 0; variable j : natural := defined_ards'left; begin while i /= res'length loop -- coverage off while defined_ards(j) = false loop j := j+1; end loop; -- coverage on res(i) := num_ce_by_ard(j); i := i+1; j := j+1; end loop; return res; end; ---------------------------------------------------------------------------- -- This function returns a addr_range array that is constructed by -- taking only those elements of superset addr_range array -- that will be defined by the current case. -- The superset addr_range array is given by parameter addr_range_by_ard. -- The current case the ard elements that will be used is given -- by parameter defined_ards. ---------------------------------------------------------------------------- function qual_ard_addr_range_array( defined_ards : BOOLEAN_ARRAY_TYPE; addr_range_by_ard : SLV64_ARRAY_TYPE ) return SLV64_ARRAY_TYPE is variable res : SLV64_ARRAY_TYPE(0 to 2num_set(defined_ards)-1); variable i : natural := 0; variable j : natural := defined_ards'left; begin while i /= res'length loop -- coverage off while defined_ards(j) = false loop j := j+1; end loop; -- coverage on res(i) := addr_range_by_ard(2j); res(i+1) := addr_range_by_ard((2j)+1); i := i+2; j := j+1; end loop; return res; end; function qual_ard_ce_valid( defined_ards : BOOLEAN_ARRAY_TYPE ) return std_logic_vector is variable res : std_logic_vector(0 to 31); begin res := (others => '0'); if defined_ards(defined_ards'right) then res(0 to 3) := "1111"; res(12) := '1'; res(13) := '1'; res(15) := '1'; else res(0 to 3) := "1111"; end if; return res; end; ---------------------------------------------------------------------------- -- This function returns the maximum width amongst the two GPIO Channels -- and if there is only one channel, it returns just the width of that -- channel. ---------------------------------------------------------------------------- function max_width( dual_channel : INTEGER; channel1_width : INTEGER; channel2_width : INTEGER ) return INTEGER is begin if (dual_channel = 0) then return channel1_width; else if (channel1_width > channel2_width) then return channel1_width; else return channel2_width; end if; end if; end; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- constant C_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF"; constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0'); constant INTR_TYPE : integer := 5; constant INTR_BASEADDR : std_logic_vector(0 to 31):= X"00000100"; constant INTR_HIGHADDR : std_logic_vector(0 to 31):= X"000001FF"; constant GPIO_HIGHADDR : std_logic_vector(0 to 31):= X"0000000F"; constant MAX_GPIO_WIDTH : integer := max_width (C_IS_DUAL,C_GPIO_WIDTH,C_GPIO2_WIDTH); constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := qual_ard_addr_range_array( (true,C_INTERRUPT_PRESENT=1), (ZERO_ADDR_PAD & X"00000000", ZERO_ADDR_PAD & GPIO_HIGHADDR, ZERO_ADDR_PAD & INTR_BASEADDR, ZERO_ADDR_PAD & INTR_HIGHADDR ) ); constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := qual_ard_num_ce_array( (true,C_INTERRUPT_PRESENT=1), (4,16) ); constant ARD_CE_VALID : std_logic_vector(0 to 31) := qual_ard_ce_valid( (true,C_INTERRUPT_PRESENT=1) ); constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to 0+bo2na(C_IS_DUAL=1)) := (others => 5); constant C_USE_WSTRB : integer := 0; constant C_DPHASE_TIMEOUT : integer := 8; ------------------------------------------------------------------------------- -- Signal and Type Declarations ------------------------------------------------------------------------------- signal ip2bus_intrevent : std_logic_vector(0 to 1); signal GPIO_xferAck_i : std_logic; signal Bus2IP_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal Bus2IP1_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal Bus2IP2_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); -- IPIC Used Signals signal ip2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal bus2ip_addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1); signal bus2ip_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal bus2ip_rnw : std_logic; signal bus2ip_cs : std_logic_vector(0 to 0 + bo2na (C_INTERRUPT_PRESENT=1)); signal bus2ip_rdce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); signal bus2ip_wrce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); signal Intrpt_bus2ip_rdce : std_logic_vector(0 to 15); signal Intrpt_bus2ip_wrce : std_logic_vector(0 to 15); signal intr_wr_ce_or_reduce : std_logic; signal intr_rd_ce_or_reduce : std_logic; signal ip2Bus_RdAck_intr_reg_hole : std_logic; signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic; signal ip2Bus_WrAck_intr_reg_hole : std_logic; signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic; signal bus2ip_be : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH / 8) - 1); signal bus2ip_clk : std_logic; signal bus2ip_reset : std_logic; signal bus2ip_resetn : std_logic; signal intr2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal intr2bus_wrack : std_logic; signal intr2bus_rdack : std_logic; signal intr2bus_error : std_logic; signal ip2bus_data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal ip2bus_data_i_D1 : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal ip2bus_wrack_i : std_logic; signal ip2bus_wrack_i_D1 : std_logic; signal ip2bus_rdack_i : std_logic; signal ip2bus_rdack_i_D1 : std_logic; signal ip2bus_error_i : std_logic; signal IP2INTC_Irpt_i : std_logic; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- begin -- architecture IMP AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif generic map ( C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, C_S_AXI_MIN_SIZE => C_AXI_MIN_SIZE, C_USE_WSTRB => C_USE_WSTRB, C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY, C_FAMILY => C_FAMILY ) port map ( S_AXI_ACLK => s_axi_aclk, S_AXI_ARESETN => s_axi_aresetn, S_AXI_AWADDR => s_axi_awaddr, S_AXI_AWVALID => s_axi_awvalid, S_AXI_AWREADY => s_axi_awready, S_AXI_WDATA => s_axi_wdata, S_AXI_WSTRB => s_axi_wstrb, S_AXI_WVALID => s_axi_wvalid, S_AXI_WREADY => s_axi_wready, S_AXI_BRESP => s_axi_bresp, S_AXI_BVALID => s_axi_bvalid, S_AXI_BREADY => s_axi_bready, S_AXI_ARADDR => s_axi_araddr, S_AXI_ARVALID => s_axi_arvalid, S_AXI_ARREADY => s_axi_arready, S_AXI_RDATA => s_axi_rdata, S_AXI_RRESP => s_axi_rresp, S_AXI_RVALID => s_axi_rvalid, S_AXI_RREADY => s_axi_rready, -- IP Interconnect (IPIC) port signals Bus2IP_Clk => bus2ip_clk, Bus2IP_Resetn => bus2ip_resetn, IP2Bus_Data => ip2bus_data_i_D1, IP2Bus_WrAck => ip2bus_wrack_i_D1, IP2Bus_RdAck => ip2bus_rdack_i_D1, --IP2Bus_WrAck => ip2bus_wrack_i, --IP2Bus_RdAck => ip2bus_rdack_i, IP2Bus_Error => ip2bus_error_i, Bus2IP_Addr => bus2ip_addr, Bus2IP_Data => bus2ip_data, Bus2IP_RNW => bus2ip_rnw, Bus2IP_BE => bus2ip_be, Bus2IP_CS => bus2ip_cs, Bus2IP_RdCE => bus2ip_rdce, Bus2IP_WrCE => bus2ip_wrce ); ip2bus_data_i <= intr2bus_data or ip2bus_data; ip2bus_wrack_i <= intr2bus_wrack or (GPIO_xferAck_i and not(bus2ip_rnw)) or ip2Bus_WrAck_intr_reg_hole;-- Holes in Address range ip2bus_rdack_i <= intr2bus_rdack or (GPIO_xferAck_i and bus2ip_rnw) or ip2Bus_RdAck_intr_reg_hole; -- Holes in Address range I_WRACK_RDACK_DELAYS: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2bus_wrack_i_D1 <= '0'; ip2bus_rdack_i_D1 <= '0'; ip2bus_data_i_D1 <= (others => '0'); else ip2bus_wrack_i_D1 <= ip2bus_wrack_i; ip2bus_rdack_i_D1 <= ip2bus_rdack_i; ip2bus_data_i_D1 <= ip2bus_data_i; end if; end if; end process I_WRACK_RDACK_DELAYS; ip2bus_error_i <= intr2bus_error; ---------------------- --REG_RESET_FROM_IPIF: convert active low to active hig reset to rest of -- the core. ---------------------- REG_RESET_FROM_IPIF: process (s_axi_aclk) is begin if(s_axi_aclk'event and s_axi_aclk = '1') then bus2ip_reset <= not(bus2ip_resetn); end if; end process REG_RESET_FROM_IPIF; --------------------------------------------------------------------------- -- Interrupts --------------------------------------------------------------------------- INTR_CTRLR_GEN : if (C_INTERRUPT_PRESENT = 1) generate constant NUM_IPIF_IRPT_SRC : natural := 1; constant NUM_CE : integer := 16; signal errack_reserved : std_logic_vector(0 to 1); signal ipif_lvl_interrupts : std_logic_vector(0 to NUM_IPIF_IRPT_SRC-1); begin ipif_lvl_interrupts <= (others => '0'); errack_reserved <= (others => '0'); --- Addr 0X11c, 0X120, 0X128 valid addresses, remaining are holes Intrpt_bus2ip_rdce <= "0000000" & bus2ip_rdce(11) & bus2ip_rdce(12) & '0' & bus2ip_rdce(14) & "00000"; Intrpt_bus2ip_wrce <= "0000000" & bus2ip_wrce(11) & bus2ip_wrce(12) & '0' & bus2ip_wrce(14) & "00000"; intr_rd_ce_or_reduce <= or_reduce(bus2ip_rdce(4 to 10)) or Bus2IP_RdCE(13) or or_reduce(Bus2IP_RdCE(15 to 19)); intr_wr_ce_or_reduce <= or_reduce(bus2ip_wrce(4 to 10)) or bus2ip_wrce(13) or or_reduce(bus2ip_wrce(15 to 19)); I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2Bus_RdAck_intr_reg_hole <= '0'; ip2Bus_RdAck_intr_reg_hole_d1 <= '0'; else ip2Bus_RdAck_intr_reg_hole_d1 <= intr_rd_ce_or_reduce; ip2Bus_RdAck_intr_reg_hole <= intr_rd_ce_or_reduce and (not ip2Bus_RdAck_intr_reg_hole_d1); end if; end if; end process I_READ_ACK_INTR_HOLES; I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2Bus_WrAck_intr_reg_hole <= '0'; ip2Bus_WrAck_intr_reg_hole_d1 <= '0'; else ip2Bus_WrAck_intr_reg_hole_d1 <= intr_wr_ce_or_reduce; ip2Bus_WrAck_intr_reg_hole <= intr_wr_ce_or_reduce and (not ip2Bus_WrAck_intr_reg_hole_d1); end if; end if; end process I_WRITE_ACK_INTR_HOLES; INTERRUPT_CONTROL_I : entity interrupt_control_v3_1_4.interrupt_control generic map ( C_NUM_CE => NUM_CE, C_NUM_IPIF_IRPT_SRC => NUM_IPIF_IRPT_SRC, C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY, C_INCLUDE_DEV_PENCODER => false, C_INCLUDE_DEV_ISC => false, C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH ) port map ( -- Inputs From the IPIF Bus Bus2IP_Clk => Bus2IP_Clk, Bus2IP_Reset => bus2ip_reset, Bus2IP_Data => bus2ip_data, Bus2IP_BE => bus2ip_be, Interrupt_RdCE => Intrpt_bus2ip_rdce, Interrupt_WrCE => Intrpt_bus2ip_wrce, -- Interrupt inputs from the IPIF sources that will -- get registered in this design IPIF_Reg_Interrupts => errack_reserved, -- Level Interrupt inputs from the IPIF sources IPIF_Lvl_Interrupts => ipif_lvl_interrupts, -- Inputs from the IP Interface IP2Bus_IntrEvent => ip2bus_intrevent(IP_INTR_MODE_ARRAY'range), -- Final Device Interrupt Output Intr2Bus_DevIntr => IP2INTC_Irpt_i, -- Status Reply Outputs to the Bus Intr2Bus_DBus => intr2bus_data, Intr2Bus_WrAck => intr2bus_wrack, Intr2Bus_RdAck => intr2bus_rdack, Intr2Bus_Error => intr2bus_error, Intr2Bus_Retry => open, Intr2Bus_ToutSup => open ); -- registering interrupt I_INTR_DELAY: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2intc_irpt <= '0'; else ip2intc_irpt <= IP2INTC_Irpt_i; end if; end if; end process I_INTR_DELAY; end generate INTR_CTRLR_GEN; ----------------------------------------------------------------------- -- Assigning the intr2bus signal to zero's when interrupt is not -- present ----------------------------------------------------------------------- REMOVE_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate intr2bus_data <= (others => '0'); ip2intc_irpt <= '0'; intr2bus_error <= '0'; intr2bus_rdack <= '0'; intr2bus_wrack <= '0'; ip2Bus_WrAck_intr_reg_hole <= '0'; ip2Bus_RdAck_intr_reg_hole <= '0'; end generate REMOVE_INTERRUPT; gpio_core_1 : entity axi_gpio_v2_0_15.gpio_core generic map ( C_DW => C_S_AXI_DATA_WIDTH, C_AW => C_S_AXI_ADDR_WIDTH, C_GPIO_WIDTH => C_GPIO_WIDTH, C_GPIO2_WIDTH => C_GPIO2_WIDTH, C_MAX_GPIO_WIDTH => MAX_GPIO_WIDTH, C_INTERRUPT_PRESENT => C_INTERRUPT_PRESENT, C_DOUT_DEFAULT => C_DOUT_DEFAULT, C_TRI_DEFAULT => C_TRI_DEFAULT, C_IS_DUAL => C_IS_DUAL, C_ALL_OUTPUTS => C_ALL_OUTPUTS, C_ALL_INPUTS => C_ALL_INPUTS, C_ALL_INPUTS_2 => C_ALL_INPUTS_2, C_ALL_OUTPUTS_2 => C_ALL_OUTPUTS_2, C_DOUT_DEFAULT_2 => C_DOUT_DEFAULT_2, C_TRI_DEFAULT_2 => C_TRI_DEFAULT_2, C_FAMILY => C_FAMILY ) port map ( Clk => Bus2IP_Clk, Rst => bus2ip_reset, ABus_Reg => Bus2IP_Addr, BE_Reg => Bus2IP_BE(0 to C_S_AXI_DATA_WIDTH/8-1), DBus_Reg => Bus2IP_Data_i(0 to MAX_GPIO_WIDTH-1), RNW_Reg => Bus2IP_RNW, GPIO_DBus => IP2Bus_Data(0 to C_S_AXI_DATA_WIDTH-1), GPIO_xferAck => GPIO_xferAck_i, GPIO_Select => bus2ip_cs(0), GPIO_intr => ip2bus_intrevent(0), GPIO2_intr => ip2bus_intrevent(1), GPIO_IO_I => gpio_io_i, GPIO_IO_O => gpio_io_o, GPIO_IO_T => gpio_io_t, GPIO2_IO_I => gpio2_io_i, GPIO2_IO_O => gpio2_io_o, GPIO2_IO_T => gpio2_io_t ); Bus2IP_Data_i <= Bus2IP1_Data_i when bus2ip_cs(0) = '1' and bus2ip_addr (5) = '0'else Bus2IP2_Data_i; BUS_CONV_ch1 : for i in 0 to C_GPIO_WIDTH-1 generate Bus2IP1_Data_i(i) <= Bus2IP_Data(i+ C_S_AXI_DATA_WIDTH-C_GPIO_WIDTH); end generate BUS_CONV_ch1; BUS_CONV_ch2 : for i in 0 to C_GPIO2_WIDTH-1 generate Bus2IP2_Data_i(i) <= Bus2IP_Data(i+ C_S_AXI_DATA_WIDTH-C_GPIO2_WIDTH); end generate BUS_CONV_ch2; end architecture imp;
------------------------------------------------------------------------------- -- gpio_core - entity/architecture pair ------------------------------------------------------------------------------- -- ************************************************************************* -- DISCLAIMER OF LIABILITY -- -- This file contains proprietary and confidential information of -- Xilinx, Inc. ("Xilinx"), that is distributed under a license -- from Xilinx, and may be used, copied and/or disclosed only -- pursuant to the terms of a valid license agreement with Xilinx. -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx -- does not warrant that functions included in the Materials will -- meet the requirements of Licensee, or that the operation of the -- Materials will be uninterrupted or error-free, or that defects -- in the Materials will be corrected. Furthermore, Xilinx does -- not warrant or make any representations regarding use, or the -- results of the use, of the Materials in terms of correctness, -- accuracy, reliability or otherwise. -- -- Xilinx products are not designed or intended to be fail-safe, -- or for use in any application requiring fail-safe performance, -- such as life-support or safety devices or systems, Class III -- medical devices, nuclear facilities, applications related to -- the deployment of airbags, or any other applications that could -- lead to death, personal injury or severe property or -- environmental damage (individually and collectively, "critical -- applications"). Customer assumes the sole risk and liability -- of any use of Xilinx products in critical applications, -- subject only to applicable laws and regulations governing -- limitations on product liability. -- -- Copyright 2009 Xilinx, Inc. -- All rights reserved. -- -- This disclaimer and copyright notice must be retained as part -- of this file at all times. -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: gpio_core.vhd -- Version: v1.01a -- Description: General Purpose I/O for AXI Interface -- ------------------------------------------------------------------------------- -- Structure: -- axi_gpio.vhd -- -- axi_lite_ipif.vhd -- -- interrupt_control.vhd -- -- gpio_core.vhd -- ------------------------------------------------------------------------------- -- -- Author: KSB -- History: -- ~~~~~~~~~~~~~~ -- KSB 09/15/09 -- ^^^^^^^^^^^^^^ -- ~~~~~~~~~~~~~~ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; library lib_cdc_v1_0_2; ------------------------------------------------------------------------------- -- Definition of Generics : -- ------------------------------------------------------------------------------- -- C_DW -- Data width of PLB BUS. -- C_AW -- Address width of PLB BUS. -- C_GPIO_WIDTH -- GPIO Data Bus width. -- C_GPIO2_WIDTH -- GPIO2 Data Bus width. -- C_INTERRUPT_PRESENT -- GPIO Interrupt. -- C_DOUT_DEFAULT -- GPIO_DATA Register reset value. -- C_TRI_DEFAULT -- GPIO_TRI Register reset value. -- C_IS_DUAL -- Dual Channel GPIO. -- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value. -- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value. -- C_FAMILY -- XILINX FPGA family ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Definition of Ports -- ------------------------------------------------------------------------------- -- Clk -- Input clock -- Rst -- Reset -- ABus_Reg -- Bus to IP address -- BE_Reg -- Bus to IP byte enables -- DBus_Reg -- Bus to IP data bus -- RNW_Reg -- Bus to IP read write control -- GPIO_DBus -- IP to Bus data bus -- GPIO_xferAck -- GPIO transfer acknowledge -- GPIO_intr -- GPIO channel 1 interrupt to IPIC -- GPIO2_intr -- GPIO channel 2 interrupt to IPIC -- GPIO_Select -- GPIO select -- -- GPIO_IO_I -- Channel 1 General purpose I/O in port -- GPIO_IO_O -- Channel 1 General purpose I/O out port -- GPIO_IO_T -- Channel 1 General purpose I/O TRI-STATE control port -- GPIO2_IO_I -- Channel 2 General purpose I/O in port -- GPIO2_IO_O -- Channel 2 General purpose I/O out port -- GPIO2_IO_T -- Channel 2 General purpose I/O TRI-STATE control port ------------------------------------------------------------------------------- entity GPIO_Core is generic ( C_DW : integer := 32; C_AW : integer := 32; C_GPIO_WIDTH : integer := 32; C_GPIO2_WIDTH : integer := 32; C_MAX_GPIO_WIDTH : integer := 32; C_INTERRUPT_PRESENT : integer := 0; C_DOUT_DEFAULT : std_logic_vector (0 to 31) := X"0000_0000"; C_TRI_DEFAULT : std_logic_vector (0 to 31) := X"FFFF_FFFF"; C_IS_DUAL : integer := 0; C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013 C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013 C_ALL_INPUTS : integer range 0 to 1 := 0; C_ALL_INPUTS_2 : integer range 0 to 1 := 0; C_DOUT_DEFAULT_2 : std_logic_vector (0 to 31) := X"0000_0000"; C_TRI_DEFAULT_2 : std_logic_vector (0 to 31) := X"FFFF_FFFF"; C_FAMILY : string := "virtex7" ); port ( Clk : in std_logic; Rst : in std_logic; ABus_Reg : in std_logic_vector(0 to C_AW-1); BE_Reg : in std_logic_vector(0 to C_DW/8-1); DBus_Reg : in std_logic_vector(0 to C_MAX_GPIO_WIDTH-1); RNW_Reg : in std_logic; GPIO_DBus : out std_logic_vector(0 to C_DW-1); GPIO_xferAck : out std_logic; GPIO_intr : out std_logic; GPIO2_intr : out std_logic; GPIO_Select : in std_logic; GPIO_IO_I : in std_logic_vector(0 to C_GPIO_WIDTH-1); GPIO_IO_O : out std_logic_vector(0 to C_GPIO_WIDTH-1); GPIO_IO_T : out std_logic_vector(0 to C_GPIO_WIDTH-1); GPIO2_IO_I : in std_logic_vector(0 to C_GPIO2_WIDTH-1); GPIO2_IO_O : out std_logic_vector(0 to C_GPIO2_WIDTH-1); GPIO2_IO_T : out std_logic_vector(0 to C_GPIO2_WIDTH-1) ); end entity GPIO_Core; ------------------------------------------------------------------------------- -- Architecture section ------------------------------------------------------------------------------- architecture IMP of GPIO_Core is -- Pragma Added to supress synth warnings attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes"; ---------------------------------------------------------------------- -- Function for Reduction OR ---------------------------------------------------------------------- function or_reduce(l : std_logic_vector) return std_logic is variable v : std_logic := '0'; begin for i in l'range loop v := v or l(i); end loop; return v; end; --------------------------------------------------------------------- -- End of Function ------------------------------------------------------------------- --constant GPIO_G_W : integer = C_GPIO_WIDTH when (C_GPIO_WIDTH > C_GPIO2_WIDTH) else C_GPIO2_; signal gpio_Data_Select : std_logic_vector(0 to C_IS_DUAL); signal gpio_OE_Select : std_logic_vector(0 to C_IS_DUAL); signal Read_Reg_Rst : STD_LOGIC; signal Read_Reg_In : std_logic_vector(0 to C_GPIO_WIDTH-1); signal Read_Reg_CE : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_Data_Out : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_DOUT_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1); signal gpio_Data_In : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_in_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_in_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_io_i_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_io_i_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_OE : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_TRI_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1); signal GPIO_DBus_i : std_logic_vector(0 to C_DW-1); signal gpio_data_in_xor : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_data_in_xor_reg : std_logic_vector(0 to C_GPIO_WIDTH-1); signal or_ints : std_logic_vector(0 to 0); signal or_ints2 : std_logic_vector(0 to 0); signal iGPIO_xferAck : STD_LOGIC; signal gpio_xferAck_Reg : STD_LOGIC; signal dout_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1); signal tri_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1); signal reset_zeros : std_logic_vector(0 to C_GPIO_WIDTH-1); signal dout2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal tri2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal reset2_zeros : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio_reg_en : std_logic; begin -- architecture IMP reset_zeros <= (others => '0'); reset2_zeros <= (others => '0'); TIE_DEFAULTS_GENERATE : if C_DW >= C_GPIO_WIDTH generate SELECT_BITS_GENERATE : for i in 0 to C_GPIO_WIDTH-1 generate dout_default_i(i) <= C_DOUT_DEFAULT(i-C_GPIO_WIDTH+C_DW); tri_default_i(i) <= C_TRI_DEFAULT(i-C_GPIO_WIDTH+C_DW); end generate SELECT_BITS_GENERATE; end generate TIE_DEFAULTS_GENERATE; TIE_DEFAULTS_2_GENERATE : if C_DW >= C_GPIO2_WIDTH generate SELECT_BITS_2_GENERATE : for i in 0 to C_GPIO2_WIDTH-1 generate dout2_default_i(i) <= C_DOUT_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW); tri2_default_i(i) <= C_TRI_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW); end generate SELECT_BITS_2_GENERATE; end generate TIE_DEFAULTS_2_GENERATE; Read_Reg_Rst <= iGPIO_xferAck or gpio_xferAck_Reg or (not GPIO_Select) or (GPIO_Select and not RNW_Reg); gpio_reg_en <= GPIO_Select when (ABus_Reg(0) = '0') else '0'; ----------------------------------------------------------------------------- -- XFER_ACK_PROCESS ----------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ----------------------------------------------------------------------------- XFER_ACK_PROCESS : process (Clk) is begin if (Clk'EVENT and Clk = '1') then if (Rst = '1') then iGPIO_xferAck <= '0'; else iGPIO_xferAck <= GPIO_Select and not gpio_xferAck_Reg; if iGPIO_xferAck = '1' then iGPIO_xferAck <= '0'; end if; end if; end if; end process XFER_ACK_PROCESS; ----------------------------------------------------------------------------- -- DELAYED_XFER_ACK_PROCESS ----------------------------------------------------------------------------- -- Single Reg stage to make Transfer Ack period one clock pulse wide ----------------------------------------------------------------------------- DELAYED_XFER_ACK_PROCESS : process (Clk) is begin if (Clk'EVENT and Clk = '1') then if (Rst = '1') then gpio_xferAck_Reg <= '0'; else gpio_xferAck_Reg <= iGPIO_xferAck; end if; end if; end process DELAYED_XFER_ACK_PROCESS; GPIO_xferAck <= iGPIO_xferAck; ----------------------------------------------------------------------------- -- Drive GPIO interrupts to '0' when interrupt not present ----------------------------------------------------------------------------- DONT_GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate gpio_intr <= '0'; gpio2_intr <= '0'; end generate DONT_GEN_INTERRUPT; ---------------------------------------------------------------------------- -- When only one channel is used, the additional logic for the second -- channel ports is not present ----------------------------------------------------------------------------- Not_Dual : if (C_IS_DUAL = 0) generate GPIO2_IO_O <= C_DOUT_DEFAULT(0 to C_GPIO2_WIDTH-1); GPIO2_IO_T <= C_TRI_DEFAULT_2(0 to C_GPIO2_WIDTH-1); ALLOUT_ND : if (C_ALL_OUTPUTS = 1) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLOUT_ND; ALLIN1_ND : if (C_ALL_INPUTS = 1) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLIN1_ND; ALLOUT0_ND : if (C_ALL_OUTPUTS = 0 and C_ALL_INPUTS = 0) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else if (gpio_OE(i) = '0' and gpio_OE_Select(0) = '0')then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); end if; --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLOUT0_ND; TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0'); end generate TIE_DBUS_GENERATE; ----------------------------------------------------------------------------- -- GPIO_DBUS_PROCESS ----------------------------------------------------------------------------- -- This process generates the GPIO DATA BUS from the GPIO_DBUS_I based on -- the channel select signals ----------------------------------------------------------------------------- GPIO_DBus <= GPIO_DBus_i; ----------------------------------------------------------------------------- -- REG_SELECT_PROCESS ----------------------------------------------------------------------------- -- GPIO REGISTER selection decoder for single channel configuration ----------------------------------------------------------------------------- --REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is begin gpio_Data_Select(0) <= '0'; gpio_OE_Select(0) <= '0'; --if GPIO_Select = '1' then if gpio_reg_en = '1' then if (ABus_Reg(5) = '0') then case ABus_Reg(6) is -- bit A29 when '0' => gpio_Data_Select(0) <= '1'; when '1' => gpio_OE_Select(0) <= '1'; -- coverage off when others => null; -- coverage on end case; end if; end if; end process REG_SELECT_PROCESS; INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 0, C_VECTOR_WIDTH => C_GPIO_WIDTH, C_MTBF_STAGES => 4 ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => '0', prmry_vect_in => GPIO_IO_I, scndry_aclk => Clk, scndry_resetn => '0', scndry_out => open, scndry_vect_out => gpio_io_i_d2 ); --------------------------------------------------------------------------- -- GPIO_INDATA_BIRDIR_PROCESS --------------------------------------------------------------------------- -- Reading of channel 1 data from Bidirectional GPIO port -- to GPIO_DATA REGISTER --------------------------------------------------------------------------- GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then -- gpio_io_i_d1 <= GPIO_IO_I; -- gpio_io_i_d2 <= gpio_io_i_d1; gpio_Data_In <= gpio_io_i_d2; end if; end process GPIO_INDATA_BIRDIR_PROCESS; --------------------------------------------------------------------------- -- GPIO_OUTDATA_PROCESS --------------------------------------------------------------------------- -- Writing to Channel 1 GPIO_DATA REGISTER --------------------------------------------------------------------------- GPIO_OUTDATA_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio_Data_Out <= dout_default_i; elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO_WIDTH-1 loop gpio_Data_Out(i) <= DBus_Reg(i); end loop; end if; end if; end process GPIO_OUTDATA_PROCESS; --------------------------------------------------------------------------- -- READ_MUX_PROCESS --------------------------------------------------------------------------- -- Selects GPIO_TRI control or GPIO_DATA Register to be read --------------------------------------------------------------------------- READ_MUX_PROCESS : process (gpio_Data_In, gpio_Data_Select, gpio_OE, gpio_OE_Select,gpio_Data_Out) is begin Read_Reg_In <= (others => '0'); if gpio_Data_Select(0) = '1' then Read_Reg_In <= gpio_Data_In; --Read_Reg_In <= gpio_Data_In; elsif gpio_OE_Select(0) = '1' then Read_Reg_In <= gpio_OE; end if; end process READ_MUX_PROCESS; --------------------------------------------------------------------------- -- GPIO_OE_PROCESS --------------------------------------------------------------------------- -- Writing to Channel 1 GPIO_TRI Control REGISTER --------------------------------------------------------------------------- GPIO_OE_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio_OE <= tri_default_i; elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO_WIDTH-1 loop gpio_OE(i) <= DBus_Reg(i); end loop; end if; end if; end process GPIO_OE_PROCESS; GPIO_IO_O <= gpio_Data_Out; GPIO_IO_T <= gpio_OE; ---------------------------------------------------------------------------- -- INTERRUPT IS PRESENT ---------------------------------------------------------------------------- -- When the C_INTERRUPT_PRESENT=1, the interrupt is driven based on whether -- there is a change in the data coming in at the GPIO_IO_I port or GPIO_In -- port ---------------------------------------------------------------------------- GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 1) generate gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2; ------------------------------------------------------------------------- -- An interrupt conditon exists if there is a change on any bit. ------------------------------------------------------------------------- or_ints(0) <= or_reduce(gpio_data_in_xor_reg); ------------------------------------------------------------------------- -- Registering Interrupt condition ------------------------------------------------------------------------- REGISTER_XOR_INTR : process (Clk) is begin if (Clk'EVENT and Clk = '1') then if (Rst = '1') then gpio_data_in_xor_reg <= reset_zeros; GPIO_intr <= '0'; else gpio_data_in_xor_reg <= gpio_data_in_xor; GPIO_intr <= or_ints(0); end if; end if; end process REGISTER_XOR_INTR; gpio2_intr <= '0'; -- Channel 2 interrupt is driven low end generate GEN_INTERRUPT; end generate Not_Dual; ---)(------------------------------------------------------------------------ -- When both the channels are used, the additional logic for the second -- channel ports ----------------------------------------------------------------------------- Dual : if (C_IS_DUAL = 1) generate signal gpio2_Data_In : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_in_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_in_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_io_i_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_io_i_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_data_in_xor : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_data_in_xor_reg : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_Data_Out : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_DOUT_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1); signal gpio2_OE : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_TRI_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1); signal Read_Reg2_In : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal Read_Reg2_CE : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal GPIO2_DBus_i : std_logic_vector(0 to C_DW-1); begin ALLOUT0_ND_G0 : if (C_ALL_OUTPUTS = 0 and C_ALL_INPUTS = 0) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else if (gpio_OE(i) = '0' and gpio_OE_Select(0) = '0') then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); end if; --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLOUT0_ND_G0; ALLIN0_ND_G0 : if (C_ALL_INPUTS = 1) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLIN0_ND_G0; ALLOUT0_ND_G1 : if (C_ALL_OUTPUTS = 1) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate begin -------------------------------------------------------------------------- -- GPIO_DBUS_I_PROCESS -------------------------------------------------------------------------- -- This process generates the GPIO CHANNEL1 DATA BUS -------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLOUT0_ND_G1; TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0'); end generate TIE_DBUS_GENERATE; ALLIN0_ND_G2 : if (C_ALL_OUTPUTS_2 = 0 and C_ALL_INPUTS_2 = 1) generate READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate -------------------------------------------------------------------------- -- GPIO2_DBUS_I_PROCESS -------------------------------------------------------------------------- -- This process generates the GPIO CHANNEL2 DATA BUS -------------------------------------------------------------------------- GPIO2_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0'; else GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i); --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); end if; end if; end process; end generate READ_REG2_GEN; end generate ALLIN0_ND_G2; ALLOUT0_ND_G2 : if (C_ALL_OUTPUTS_2 = 0 and C_ALL_INPUTS_2 = 0) generate READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate -------------------------------------------------------------------------- -- GPIO2_DBUS_I_PROCESS -------------------------------------------------------------------------- -- This process generates the GPIO CHANNEL2 DATA BUS -------------------------------------------------------------------------- GPIO2_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0'; else if (gpio2_OE(i) = '0' and gpio_OE_Select(1) = '0') then GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i); else GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i); end if; -- GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i) when (gpio2_OE(i) = '1') else Read_Reg2_In(i); --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); end if; end if; end process; end generate READ_REG2_GEN; end generate ALLOUT0_ND_G2; ALLOUT1_ND_G2 : if (C_ALL_OUTPUTS_2 = 1) generate READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate -------------------------------------------------------------------------- -- GPIO2_DBUS_I_PROCESS -------------------------------------------------------------------------- -- This process generates the GPIO CHANNEL2 DATA BUS -------------------------------------------------------------------------- GPIO2_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0'; else GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i); end if; end if; end process; end generate READ_REG2_GEN; end generate ALLOUT1_ND_G2; TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0'); end generate TIE_DBUS2_GENERATE; --------------------------------------------------------------------------- -- GPIO_DBUS_PROCESS --------------------------------------------------------------------------- -- This process generates the GPIO DATA BUS from the GPIO_DBUS_I and -- GPIO2_DBUS_I based on which channel is selected --------------------------------------------------------------------------- GPIO_DBus <= GPIO_DBus_i when (((gpio_Data_Select(0) = '1') or (gpio_OE_Select(0) = '1')) and (RNW_Reg = '1')) else GPIO2_DBus_i; ----------------------------------------------------------------------------- -- DUAL_REG_SELECT_PROCESS ----------------------------------------------------------------------------- -- GPIO REGISTER selection decoder for Dual channel configuration ----------------------------------------------------------------------------- --DUAL_REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is DUAL_REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is variable ABus_reg_select : std_logic_vector(0 to 1); begin ABus_reg_select := ABus_Reg(5 to 6); gpio_Data_Select <= (others => '0'); gpio_OE_Select <= (others => '0'); --if GPIO_Select = '1' then if gpio_reg_en = '1' then -- case ABus_Reg(28 to 29) is -- bit A28,A29 for dual case ABus_reg_select is -- bit A28,A29 for dual when "00" => gpio_Data_Select(0) <= '1'; when "01" => gpio_OE_Select(0) <= '1'; when "10" => gpio_Data_Select(1) <= '1'; when "11" => gpio_OE_Select(1) <= '1'; -- coverage off when others => null; -- coverage on end case; end if; end process DUAL_REG_SELECT_PROCESS; --------------------------------------------------------------------------- -- GPIO_INDATA_BIRDIR_PROCESS --------------------------------------------------------------------------- -- Reading of channel 1 data from Bidirectional GPIO port -- to GPIO_DATA REGISTER --------------------------------------------------------------------------- INPUT_DOUBLE_REGS4 : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 0, C_VECTOR_WIDTH => C_GPIO_WIDTH, C_MTBF_STAGES => 4 ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => '0', prmry_vect_in => GPIO_IO_I, scndry_aclk => Clk, scndry_resetn => '0', scndry_out => open, scndry_vect_out => gpio_io_i_d2 ); GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then -- gpio_io_i_d1 <= GPIO_IO_I; -- gpio_io_i_d2 <= gpio_io_i_d1; --if (C_ALL_OUTPUTS = '1') then -- gpio_Data_In <= gpio_Data_Out; -- else gpio_Data_In <= gpio_io_i_d2; -- end if; end if; end process GPIO_INDATA_BIRDIR_PROCESS; INPUT_DOUBLE_REGS5 : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 0, C_VECTOR_WIDTH => C_GPIO2_WIDTH, C_MTBF_STAGES => 4 ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => '0', prmry_vect_in => GPIO2_IO_I, scndry_aclk => Clk, scndry_resetn => '0', scndry_out => open, scndry_vect_out => gpio2_io_i_d2 ); --------------------------------------------------------------------------- -- GPIO2_INDATA_BIRDIR_PROCESS --------------------------------------------------------------------------- -- Reading of channel 2 data from Bidirectional GPIO2 port -- to GPIO2_DATA REGISTER --------------------------------------------------------------------------- GPIO2_INDATA_BIRDIR_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then -- gpio2_io_i_d1 <= GPIO2_IO_I; -- gpio2_io_i_d2 <= gpio2_io_i_d1; -- if (C_ALL_OUTPUTS = '1') then -- gpio2_Data_In <= gpio2_Data_Out; -- else gpio2_Data_In <= gpio2_io_i_d2; -- end if; end if; end process GPIO2_INDATA_BIRDIR_PROCESS; --------------------------------------------------------------------------- -- GPIO_OUTDATA_PROCESS_0_0 --------------------------------------------------------------------------- -- Writing to Channel 1 GPIO_DATA REGISTER --------------------------------------------------------------------------- GPIO_OUTDATA_PROCESS_0_0 : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio_Data_Out <= dout_default_i; elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO_WIDTH-1 loop gpio_Data_Out(i) <= DBus_Reg(i); end loop; end if; end if; end process GPIO_OUTDATA_PROCESS_0_0; --------------------------------------------------------------------------- -- GPIO_OE_PROCESS_0_0 --------------------------------------------------------------------------- -- Writing to Channel 1 GPIO_TRI Control REGISTER --------------------------------------------------------------------------- GPIO_OE_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio_OE <= tri_default_i; elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO_WIDTH-1 loop gpio_OE(i) <= DBus_Reg(i); -- end if; end loop; end if; end if; end process GPIO_OE_PROCESS; --------------------------------------------------------------------------- -- GPIO2_OUTDATA_PROCESS_0_0 --------------------------------------------------------------------------- -- Writing to Channel 2 GPIO2_DATA REGISTER --------------------------------------------------------------------------- GPIO2_OUTDATA_PROCESS_0_0 : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio2_Data_Out <= dout2_default_i; elsif gpio_Data_Select(1) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO2_WIDTH-1 loop gpio2_Data_Out(i) <= DBus_Reg(i); -- end if; end loop; end if; end if; end process GPIO2_OUTDATA_PROCESS_0_0; --------------------------------------------------------------------------- -- GPIO2_OE_PROCESS_0_0 --------------------------------------------------------------------------- -- Writing to Channel 2 GPIO2_TRI Control REGISTER --------------------------------------------------------------------------- GPIO2_OE_PROCESS_0_0 : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio2_OE <= tri2_default_i; elsif gpio_OE_Select(1) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO2_WIDTH-1 loop gpio2_OE(i) <= DBus_Reg(i); end loop; end if; end if; end process GPIO2_OE_PROCESS_0_0; GPIO_IO_O <= gpio_Data_Out; GPIO_IO_T <= gpio_OE; GPIO2_IO_O <= gpio2_Data_Out; GPIO2_IO_T <= gpio2_OE; --------------------------------------------------------------------------- -- READ_MUX_PROCESS_0_0 --------------------------------------------------------------------------- -- Selects among Channel 1 GPIO_DATA ,GPIO_TRI and Channel 2 GPIO2_DATA -- GPIO2_TRI REGISTERS for reading --------------------------------------------------------------------------- READ_MUX_PROCESS_0_0 : process (gpio2_Data_In, gpio2_OE, gpio_Data_In, gpio_Data_Select, gpio_OE, gpio_OE_Select,gpio_Data_Out,gpio2_Data_Out) is begin Read_Reg_In <= (others => '0'); Read_Reg2_In <= (others => '0'); if gpio_Data_Select(0) = '1' then Read_Reg_In <= gpio_Data_In; --Read_Reg_In <= gpio_Data_In; elsif gpio_OE_Select(0) = '1' then Read_Reg_In <= gpio_OE; elsif gpio_Data_Select(1) = '1' then Read_Reg2_In <= gpio2_Data_In; --Read_Reg2_In <= gpio2_Data_In; --Read_Reg2_In<= gpio2_Data_In; elsif gpio_OE_Select(1) = '1' then Read_Reg2_In <= gpio2_OE; end if; end process READ_MUX_PROCESS_0_0; --------------------------------------------------------------------------- -- INTERRUPT IS PRESENT --------------------------------------------------------------------------- gen_interrupt_dual : if (C_INTERRUPT_PRESENT = 1) generate gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2; gpio2_data_in_xor <= gpio2_Data_In xor gpio2_io_i_d2; ------------------------------------------------------------------------- -- An interrupt conditon exists if there is a change any bit. ------------------------------------------------------------------------- or_ints(0) <= or_reduce(gpio_data_in_xor_reg); or_ints2(0) <= or_reduce(gpio2_data_in_xor_reg); ------------------------------------------------------------------------- -- Registering Interrupt condition ------------------------------------------------------------------------- REGISTER_XORs_INTRs : process (Clk) is begin if (Clk'EVENT and Clk = '1') then if (Rst = '1') then gpio_data_in_xor_reg <= reset_zeros; gpio2_data_in_xor_reg <= reset2_zeros; GPIO_intr <= '0'; GPIO2_intr <= '0'; else gpio_data_in_xor_reg <= gpio_data_in_xor; gpio2_data_in_xor_reg <= gpio2_data_in_xor; GPIO_intr <= or_ints(0); GPIO2_intr <= or_ints2(0); end if; end if; end process REGISTER_XORs_INTRs; end generate gen_interrupt_dual; end generate Dual; end architecture IMP; ------------------------------------------------------------------------------- -- AXI_GPIO - entity/architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************ -- DISCLAIMER OF LIABILITY -- -- This file contains proprietary and confidential information of -- Xilinx, Inc. ("Xilinx"), that is distributed under a license -- from Xilinx, and may be used, copied and/or disclosed only -- pursuant to the terms of a valid license agreement with Xilinx. -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx -- does not warrant that functions included in the Materials will -- meet the requirements of Licensee, or that the operation of the -- Materials will be uninterrupted or error-free, or that defects -- in the Materials will be corrected. Furthermore, Xilinx does -- not warrant or make any representations regarding use, or the -- results of the use, of the Materials in terms of correctness, -- accuracy, reliability or otherwise. -- -- Xilinx products are not designed or intended to be fail-safe, -- or for use in any application requiring fail-safe performance, -- such as life-support or safety devices or systems, Class III -- medical devices, nuclear facilities, applications related to -- the deployment of airbags, or any other applications that could -- lead to death, personal injury or severe property or -- environmental damage (individually and collectively, "critical -- applications"). Customer assumes the sole risk and liability -- of any use of Xilinx products in critical applications, -- subject only to applicable laws and regulations governing -- limitations on product liability. -- -- Copyright 2009 Xilinx, Inc. -- All rights reserved. -- -- This disclaimer and copyright notice must be retained as part -- of this file at all times. -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_gpio.vhd -- Version: v2.0 -- Description: General Purpose I/O for AXI Interface -- ------------------------------------------------------------------------------- -- Structure: -- axi_gpio.vhd -- -- axi_lite_ipif.vhd -- -- interrupt_control.vhd -- -- gpio_core.vhd ------------------------------------------------------------------------------- -- Author: KSB -- History: -- ~~~~~~~~~~~~~~ -- KSB 07/28/09 -- ^^^^^^^^^^^^^^ -- First version of axi_gpio. Based on xps_gpio 2.00a -- -- KSB 05/20/10 -- ^^^^^^^^^^^^^^ -- Updated for holes in address range -- ~~~~~~~~~~~~~~ -- VB 09/23/10 -- ^^^^^^^^^^^^^^ -- Updated for axi_lite_ipfi_v1_01_a -- ~~~~~~~~~~~~~~ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; use std.textio.all; ------------------------------------------------------------------------------- -- AXI common package of the proc common library is used for different -- function declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- axi_gpio_v2_0_15 library is used for axi4 component declarations ------------------------------------------------------------------------------- library axi_lite_ipif_v3_0_4; use axi_lite_ipif_v3_0_4.ipif_pkg.calc_num_ce; use axi_lite_ipif_v3_0_4.ipif_pkg.INTEGER_ARRAY_TYPE; use axi_lite_ipif_v3_0_4.ipif_pkg.SLV64_ARRAY_TYPE; ------------------------------------------------------------------------------- -- axi_gpio_v2_0_15 library is used for interrupt controller component -- declarations ------------------------------------------------------------------------------- library interrupt_control_v3_1_4; ------------------------------------------------------------------------------- -- axi_gpio_v2_0_15 library is used for axi_gpio component declarations ------------------------------------------------------------------------------- library axi_gpio_v2_0_15; ------------------------------------------------------------------------------- -- Defination of Generics : -- ------------------------------------------------------------------------------- -- AXI generics -- C_BASEADDR -- Base address of the core -- C_HIGHADDR -- Permits alias of address space -- by making greater than xFFF -- C_S_AXI_ADDR_WIDTH -- Width of AXI Address interface (in bits) -- C_S_AXI_DATA_WIDTH -- Width of the AXI Data interface (in bits) -- C_FAMILY -- XILINX FPGA family -- C_INSTANCE -- Instance name ot the core in the EDK system -- C_GPIO_WIDTH -- GPIO Data Bus width. -- C_ALL_INPUTS -- Inputs Only. -- C_INTERRUPT_PRESENT -- GPIO Interrupt. -- C_IS_BIDIR -- Selects gpio_io_i as input. -- C_DOUT_DEFAULT -- GPIO_DATA Register reset value. -- C_TRI_DEFAULT -- GPIO_TRI Register reset value. -- C_IS_DUAL -- Dual Channel GPIO. -- C_ALL_INPUTS_2 -- Channel2 Inputs only. -- C_IS_BIDIR_2 -- Selects gpio2_io_i as input. -- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value. -- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value. ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Defination of Ports -- ------------------------------------------------------------------------------- -- AXI signals -- s_axi_awaddr -- AXI Write address -- s_axi_awvalid -- Write address valid -- s_axi_awready -- Write address ready -- s_axi_wdata -- Write data -- s_axi_wstrb -- Write strobes -- s_axi_wvalid -- Write valid -- s_axi_wready -- Write ready -- s_axi_bresp -- Write response -- s_axi_bvalid -- Write response valid -- s_axi_bready -- Response ready -- s_axi_araddr -- Read address -- s_axi_arvalid -- Read address valid -- s_axi_arready -- Read address ready -- s_axi_rdata -- Read data -- s_axi_rresp -- Read response -- s_axi_rvalid -- Read valid -- s_axi_rready -- Read ready -- GPIO Signals -- gpio_io_i -- Channel 1 General purpose I/O in port -- gpio_io_o -- Channel 1 General purpose I/O out port -- gpio_io_t -- Channel 1 General purpose I/O -- TRI-STATE control port -- gpio2_io_i -- Channel 2 General purpose I/O in port -- gpio2_io_o -- Channel 2 General purpose I/O out port -- gpio2_io_t -- Channel 2 General purpose I/O -- TRI-STATE control port -- System Signals -- s_axi_aclk -- AXI Clock -- s_axi_aresetn -- AXI Reset -- ip2intc_irpt -- AXI GPIO Interrupt ------------------------------------------------------------------------------- entity axi_gpio is generic ( -- -- System Parameter C_FAMILY : string := "virtex7"; -- -- AXI Parameters C_S_AXI_ADDR_WIDTH : integer range 9 to 9 := 9; C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32; -- -- GPIO Parameter C_GPIO_WIDTH : integer range 1 to 32 := 32; C_GPIO2_WIDTH : integer range 1 to 32 := 32; C_ALL_INPUTS : integer range 0 to 1 := 0; C_ALL_INPUTS_2 : integer range 0 to 1 := 0; C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013 C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013 C_INTERRUPT_PRESENT : integer range 0 to 1 := 0; C_DOUT_DEFAULT : std_logic_vector (31 downto 0) := X"0000_0000"; C_TRI_DEFAULT : std_logic_vector (31 downto 0) := X"FFFF_FFFF"; C_IS_DUAL : integer range 0 to 1 := 0; C_DOUT_DEFAULT_2 : std_logic_vector (31 downto 0) := X"0000_0000"; C_TRI_DEFAULT_2 : std_logic_vector (31 downto 0) := X"FFFF_FFFF" ); port ( -- AXI interface Signals -------------------------------------------------- s_axi_aclk : in std_logic; s_axi_aresetn : in std_logic; s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); s_axi_wvalid : in std_logic; s_axi_wready : out std_logic; s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_arvalid : in std_logic; s_axi_arready : out std_logic; s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rvalid : out std_logic; s_axi_rready : in std_logic; -- Interrupt--------------------------------------------------------------- ip2intc_irpt : out std_logic; -- GPIO Signals------------------------------------------------------------ gpio_io_i : in std_logic_vector(C_GPIO_WIDTH-1 downto 0); gpio_io_o : out std_logic_vector(C_GPIO_WIDTH-1 downto 0); gpio_io_t : out std_logic_vector(C_GPIO_WIDTH-1 downto 0); gpio2_io_i : in std_logic_vector(C_GPIO2_WIDTH-1 downto 0); gpio2_io_o : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0); gpio2_io_t : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0) ); ------------------------------------------------------------------------------- -- fan-out attributes for XST ------------------------------------------------------------------------------- attribute MAX_FANOUT : string; attribute MAX_FANOUT of s_axi_aclk : signal is "10000"; attribute MAX_FANOUT of s_axi_aresetn : signal is "10000"; ------------------------------------------------------------------------------- -- Attributes for MPD file ------------------------------------------------------------------------------- attribute IP_GROUP : string ; attribute IP_GROUP of axi_gpio : entity is "LOGICORE"; attribute SIGIS : string ; attribute SIGIS of s_axi_aclk : signal is "Clk"; attribute SIGIS of s_axi_aresetn : signal is "Rst"; attribute SIGIS of ip2intc_irpt : signal is "INTR_LEVEL_HIGH"; end entity axi_gpio; ------------------------------------------------------------------------------- -- Architecture Section ------------------------------------------------------------------------------- architecture imp of axi_gpio is -- Pragma Added to supress synth warnings attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; ------------------------------------------------------------------------------- -- constant added for webtalk information ------------------------------------------------------------------------------- --function chr(sl: std_logic) return character is -- variable c: character; -- begin -- case sl is -- when '0' => c:= '0'; -- when '1' => c:= '1'; -- when 'Z' => c:= 'Z'; -- when 'U' => c:= 'U'; -- when 'X' => c:= 'X'; -- when 'W' => c:= 'W'; -- when 'L' => c:= 'L'; -- when 'H' => c:= 'H'; -- when '-' => c:= '-'; -- end case; -- return c; -- end chr; -- --function str(slv: std_logic_vector) return string is -- variable result : string (1 to slv'length); -- variable r : integer; -- begin -- r := 1; -- for i in slv'range loop -- result(r) := chr(slv(i)); -- r := r + 1; -- end loop; -- return result; -- end str; type bo2na_type is array (boolean) of natural; -- boolean to --natural conversion constant bo2na : bo2na_type := (false => 0, true => 1); ------------------------------------------------------------------------------- -- Function Declarations ------------------------------------------------------------------------------- type BOOLEAN_ARRAY_TYPE is array(natural range <>) of boolean; ---------------------------------------------------------------------------- -- This function returns the number of elements that are true in -- a boolean array. ---------------------------------------------------------------------------- function num_set( ba : BOOLEAN_ARRAY_TYPE ) return natural is variable n : natural := 0; begin for i in ba'range loop n := n + bo2na(ba(i)); end loop; return n; end; ---------------------------------------------------------------------------- -- This function returns a num_ce integer array that is constructed by -- taking only those elements of superset num_ce integer array -- that will be defined by the current case. -- The superset num_ce array is given by parameter num_ce_by_ard. -- The current case the ard elements that will be used is given -- by parameter defined_ards. ---------------------------------------------------------------------------- function qual_ard_num_ce_array( defined_ards : BOOLEAN_ARRAY_TYPE; num_ce_by_ard : INTEGER_ARRAY_TYPE ) return INTEGER_ARRAY_TYPE is variable res : INTEGER_ARRAY_TYPE(num_set(defined_ards)-1 downto 0); variable i : natural := 0; variable j : natural := defined_ards'left; begin while i /= res'length loop -- coverage off while defined_ards(j) = false loop j := j+1; end loop; -- coverage on res(i) := num_ce_by_ard(j); i := i+1; j := j+1; end loop; return res; end; ---------------------------------------------------------------------------- -- This function returns a addr_range array that is constructed by -- taking only those elements of superset addr_range array -- that will be defined by the current case. -- The superset addr_range array is given by parameter addr_range_by_ard. -- The current case the ard elements that will be used is given -- by parameter defined_ards. ---------------------------------------------------------------------------- function qual_ard_addr_range_array( defined_ards : BOOLEAN_ARRAY_TYPE; addr_range_by_ard : SLV64_ARRAY_TYPE ) return SLV64_ARRAY_TYPE is variable res : SLV64_ARRAY_TYPE(0 to 2num_set(defined_ards)-1); variable i : natural := 0; variable j : natural := defined_ards'left; begin while i /= res'length loop -- coverage off while defined_ards(j) = false loop j := j+1; end loop; -- coverage on res(i) := addr_range_by_ard(2j); res(i+1) := addr_range_by_ard((2j)+1); i := i+2; j := j+1; end loop; return res; end; function qual_ard_ce_valid( defined_ards : BOOLEAN_ARRAY_TYPE ) return std_logic_vector is variable res : std_logic_vector(0 to 31); begin res := (others => '0'); if defined_ards(defined_ards'right) then res(0 to 3) := "1111"; res(12) := '1'; res(13) := '1'; res(15) := '1'; else res(0 to 3) := "1111"; end if; return res; end; ---------------------------------------------------------------------------- -- This function returns the maximum width amongst the two GPIO Channels -- and if there is only one channel, it returns just the width of that -- channel. ---------------------------------------------------------------------------- function max_width( dual_channel : INTEGER; channel1_width : INTEGER; channel2_width : INTEGER ) return INTEGER is begin if (dual_channel = 0) then return channel1_width; else if (channel1_width > channel2_width) then return channel1_width; else return channel2_width; end if; end if; end; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- constant C_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF"; constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0'); constant INTR_TYPE : integer := 5; constant INTR_BASEADDR : std_logic_vector(0 to 31):= X"00000100"; constant INTR_HIGHADDR : std_logic_vector(0 to 31):= X"000001FF"; constant GPIO_HIGHADDR : std_logic_vector(0 to 31):= X"0000000F"; constant MAX_GPIO_WIDTH : integer := max_width (C_IS_DUAL,C_GPIO_WIDTH,C_GPIO2_WIDTH); constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := qual_ard_addr_range_array( (true,C_INTERRUPT_PRESENT=1), (ZERO_ADDR_PAD & X"00000000", ZERO_ADDR_PAD & GPIO_HIGHADDR, ZERO_ADDR_PAD & INTR_BASEADDR, ZERO_ADDR_PAD & INTR_HIGHADDR ) ); constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := qual_ard_num_ce_array( (true,C_INTERRUPT_PRESENT=1), (4,16) ); constant ARD_CE_VALID : std_logic_vector(0 to 31) := qual_ard_ce_valid( (true,C_INTERRUPT_PRESENT=1) ); constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to 0+bo2na(C_IS_DUAL=1)) := (others => 5); constant C_USE_WSTRB : integer := 0; constant C_DPHASE_TIMEOUT : integer := 8; ------------------------------------------------------------------------------- -- Signal and Type Declarations ------------------------------------------------------------------------------- signal ip2bus_intrevent : std_logic_vector(0 to 1); signal GPIO_xferAck_i : std_logic; signal Bus2IP_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal Bus2IP1_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal Bus2IP2_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); -- IPIC Used Signals signal ip2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal bus2ip_addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1); signal bus2ip_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal bus2ip_rnw : std_logic; signal bus2ip_cs : std_logic_vector(0 to 0 + bo2na (C_INTERRUPT_PRESENT=1)); signal bus2ip_rdce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); signal bus2ip_wrce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); signal Intrpt_bus2ip_rdce : std_logic_vector(0 to 15); signal Intrpt_bus2ip_wrce : std_logic_vector(0 to 15); signal intr_wr_ce_or_reduce : std_logic; signal intr_rd_ce_or_reduce : std_logic; signal ip2Bus_RdAck_intr_reg_hole : std_logic; signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic; signal ip2Bus_WrAck_intr_reg_hole : std_logic; signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic; signal bus2ip_be : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH / 8) - 1); signal bus2ip_clk : std_logic; signal bus2ip_reset : std_logic; signal bus2ip_resetn : std_logic; signal intr2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal intr2bus_wrack : std_logic; signal intr2bus_rdack : std_logic; signal intr2bus_error : std_logic; signal ip2bus_data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal ip2bus_data_i_D1 : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal ip2bus_wrack_i : std_logic; signal ip2bus_wrack_i_D1 : std_logic; signal ip2bus_rdack_i : std_logic; signal ip2bus_rdack_i_D1 : std_logic; signal ip2bus_error_i : std_logic; signal IP2INTC_Irpt_i : std_logic; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- begin -- architecture IMP AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif generic map ( C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, C_S_AXI_MIN_SIZE => C_AXI_MIN_SIZE, C_USE_WSTRB => C_USE_WSTRB, C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY, C_FAMILY => C_FAMILY ) port map ( S_AXI_ACLK => s_axi_aclk, S_AXI_ARESETN => s_axi_aresetn, S_AXI_AWADDR => s_axi_awaddr, S_AXI_AWVALID => s_axi_awvalid, S_AXI_AWREADY => s_axi_awready, S_AXI_WDATA => s_axi_wdata, S_AXI_WSTRB => s_axi_wstrb, S_AXI_WVALID => s_axi_wvalid, S_AXI_WREADY => s_axi_wready, S_AXI_BRESP => s_axi_bresp, S_AXI_BVALID => s_axi_bvalid, S_AXI_BREADY => s_axi_bready, S_AXI_ARADDR => s_axi_araddr, S_AXI_ARVALID => s_axi_arvalid, S_AXI_ARREADY => s_axi_arready, S_AXI_RDATA => s_axi_rdata, S_AXI_RRESP => s_axi_rresp, S_AXI_RVALID => s_axi_rvalid, S_AXI_RREADY => s_axi_rready, -- IP Interconnect (IPIC) port signals Bus2IP_Clk => bus2ip_clk, Bus2IP_Resetn => bus2ip_resetn, IP2Bus_Data => ip2bus_data_i_D1, IP2Bus_WrAck => ip2bus_wrack_i_D1, IP2Bus_RdAck => ip2bus_rdack_i_D1, --IP2Bus_WrAck => ip2bus_wrack_i, --IP2Bus_RdAck => ip2bus_rdack_i, IP2Bus_Error => ip2bus_error_i, Bus2IP_Addr => bus2ip_addr, Bus2IP_Data => bus2ip_data, Bus2IP_RNW => bus2ip_rnw, Bus2IP_BE => bus2ip_be, Bus2IP_CS => bus2ip_cs, Bus2IP_RdCE => bus2ip_rdce, Bus2IP_WrCE => bus2ip_wrce ); ip2bus_data_i <= intr2bus_data or ip2bus_data; ip2bus_wrack_i <= intr2bus_wrack or (GPIO_xferAck_i and not(bus2ip_rnw)) or ip2Bus_WrAck_intr_reg_hole;-- Holes in Address range ip2bus_rdack_i <= intr2bus_rdack or (GPIO_xferAck_i and bus2ip_rnw) or ip2Bus_RdAck_intr_reg_hole; -- Holes in Address range I_WRACK_RDACK_DELAYS: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2bus_wrack_i_D1 <= '0'; ip2bus_rdack_i_D1 <= '0'; ip2bus_data_i_D1 <= (others => '0'); else ip2bus_wrack_i_D1 <= ip2bus_wrack_i; ip2bus_rdack_i_D1 <= ip2bus_rdack_i; ip2bus_data_i_D1 <= ip2bus_data_i; end if; end if; end process I_WRACK_RDACK_DELAYS; ip2bus_error_i <= intr2bus_error; ---------------------- --REG_RESET_FROM_IPIF: convert active low to active hig reset to rest of -- the core. ---------------------- REG_RESET_FROM_IPIF: process (s_axi_aclk) is begin if(s_axi_aclk'event and s_axi_aclk = '1') then bus2ip_reset <= not(bus2ip_resetn); end if; end process REG_RESET_FROM_IPIF; --------------------------------------------------------------------------- -- Interrupts --------------------------------------------------------------------------- INTR_CTRLR_GEN : if (C_INTERRUPT_PRESENT = 1) generate constant NUM_IPIF_IRPT_SRC : natural := 1; constant NUM_CE : integer := 16; signal errack_reserved : std_logic_vector(0 to 1); signal ipif_lvl_interrupts : std_logic_vector(0 to NUM_IPIF_IRPT_SRC-1); begin ipif_lvl_interrupts <= (others => '0'); errack_reserved <= (others => '0'); --- Addr 0X11c, 0X120, 0X128 valid addresses, remaining are holes Intrpt_bus2ip_rdce <= "0000000" & bus2ip_rdce(11) & bus2ip_rdce(12) & '0' & bus2ip_rdce(14) & "00000"; Intrpt_bus2ip_wrce <= "0000000" & bus2ip_wrce(11) & bus2ip_wrce(12) & '0' & bus2ip_wrce(14) & "00000"; intr_rd_ce_or_reduce <= or_reduce(bus2ip_rdce(4 to 10)) or Bus2IP_RdCE(13) or or_reduce(Bus2IP_RdCE(15 to 19)); intr_wr_ce_or_reduce <= or_reduce(bus2ip_wrce(4 to 10)) or bus2ip_wrce(13) or or_reduce(bus2ip_wrce(15 to 19)); I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2Bus_RdAck_intr_reg_hole <= '0'; ip2Bus_RdAck_intr_reg_hole_d1 <= '0'; else ip2Bus_RdAck_intr_reg_hole_d1 <= intr_rd_ce_or_reduce; ip2Bus_RdAck_intr_reg_hole <= intr_rd_ce_or_reduce and (not ip2Bus_RdAck_intr_reg_hole_d1); end if; end if; end process I_READ_ACK_INTR_HOLES; I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2Bus_WrAck_intr_reg_hole <= '0'; ip2Bus_WrAck_intr_reg_hole_d1 <= '0'; else ip2Bus_WrAck_intr_reg_hole_d1 <= intr_wr_ce_or_reduce; ip2Bus_WrAck_intr_reg_hole <= intr_wr_ce_or_reduce and (not ip2Bus_WrAck_intr_reg_hole_d1); end if; end if; end process I_WRITE_ACK_INTR_HOLES; INTERRUPT_CONTROL_I : entity interrupt_control_v3_1_4.interrupt_control generic map ( C_NUM_CE => NUM_CE, C_NUM_IPIF_IRPT_SRC => NUM_IPIF_IRPT_SRC, C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY, C_INCLUDE_DEV_PENCODER => false, C_INCLUDE_DEV_ISC => false, C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH ) port map ( -- Inputs From the IPIF Bus Bus2IP_Clk => Bus2IP_Clk, Bus2IP_Reset => bus2ip_reset, Bus2IP_Data => bus2ip_data, Bus2IP_BE => bus2ip_be, Interrupt_RdCE => Intrpt_bus2ip_rdce, Interrupt_WrCE => Intrpt_bus2ip_wrce, -- Interrupt inputs from the IPIF sources that will -- get registered in this design IPIF_Reg_Interrupts => errack_reserved, -- Level Interrupt inputs from the IPIF sources IPIF_Lvl_Interrupts => ipif_lvl_interrupts, -- Inputs from the IP Interface IP2Bus_IntrEvent => ip2bus_intrevent(IP_INTR_MODE_ARRAY'range), -- Final Device Interrupt Output Intr2Bus_DevIntr => IP2INTC_Irpt_i, -- Status Reply Outputs to the Bus Intr2Bus_DBus => intr2bus_data, Intr2Bus_WrAck => intr2bus_wrack, Intr2Bus_RdAck => intr2bus_rdack, Intr2Bus_Error => intr2bus_error, Intr2Bus_Retry => open, Intr2Bus_ToutSup => open ); -- registering interrupt I_INTR_DELAY: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2intc_irpt <= '0'; else ip2intc_irpt <= IP2INTC_Irpt_i; end if; end if; end process I_INTR_DELAY; end generate INTR_CTRLR_GEN; ----------------------------------------------------------------------- -- Assigning the intr2bus signal to zero's when interrupt is not -- present ----------------------------------------------------------------------- REMOVE_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate intr2bus_data <= (others => '0'); ip2intc_irpt <= '0'; intr2bus_error <= '0'; intr2bus_rdack <= '0'; intr2bus_wrack <= '0'; ip2Bus_WrAck_intr_reg_hole <= '0'; ip2Bus_RdAck_intr_reg_hole <= '0'; end generate REMOVE_INTERRUPT; gpio_core_1 : entity axi_gpio_v2_0_15.gpio_core generic map ( C_DW => C_S_AXI_DATA_WIDTH, C_AW => C_S_AXI_ADDR_WIDTH, C_GPIO_WIDTH => C_GPIO_WIDTH, C_GPIO2_WIDTH => C_GPIO2_WIDTH, C_MAX_GPIO_WIDTH => MAX_GPIO_WIDTH, C_INTERRUPT_PRESENT => C_INTERRUPT_PRESENT, C_DOUT_DEFAULT => C_DOUT_DEFAULT, C_TRI_DEFAULT => C_TRI_DEFAULT, C_IS_DUAL => C_IS_DUAL, C_ALL_OUTPUTS => C_ALL_OUTPUTS, C_ALL_INPUTS => C_ALL_INPUTS, C_ALL_INPUTS_2 => C_ALL_INPUTS_2, C_ALL_OUTPUTS_2 => C_ALL_OUTPUTS_2, C_DOUT_DEFAULT_2 => C_DOUT_DEFAULT_2, C_TRI_DEFAULT_2 => C_TRI_DEFAULT_2, C_FAMILY => C_FAMILY ) port map ( Clk => Bus2IP_Clk, Rst => bus2ip_reset, ABus_Reg => Bus2IP_Addr, BE_Reg => Bus2IP_BE(0 to C_S_AXI_DATA_WIDTH/8-1), DBus_Reg => Bus2IP_Data_i(0 to MAX_GPIO_WIDTH-1), RNW_Reg => Bus2IP_RNW, GPIO_DBus => IP2Bus_Data(0 to C_S_AXI_DATA_WIDTH-1), GPIO_xferAck => GPIO_xferAck_i, GPIO_Select => bus2ip_cs(0), GPIO_intr => ip2bus_intrevent(0), GPIO2_intr => ip2bus_intrevent(1), GPIO_IO_I => gpio_io_i, GPIO_IO_O => gpio_io_o, GPIO_IO_T => gpio_io_t, GPIO2_IO_I => gpio2_io_i, GPIO2_IO_O => gpio2_io_o, GPIO2_IO_T => gpio2_io_t ); Bus2IP_Data_i <= Bus2IP1_Data_i when bus2ip_cs(0) = '1' and bus2ip_addr (5) = '0'else Bus2IP2_Data_i; BUS_CONV_ch1 : for i in 0 to C_GPIO_WIDTH-1 generate Bus2IP1_Data_i(i) <= Bus2IP_Data(i+ C_S_AXI_DATA_WIDTH-C_GPIO_WIDTH); end generate BUS_CONV_ch1; BUS_CONV_ch2 : for i in 0 to C_GPIO2_WIDTH-1 generate Bus2IP2_Data_i(i) <= Bus2IP_Data(i+ C_S_AXI_DATA_WIDTH-C_GPIO2_WIDTH); end generate BUS_CONV_ch2; end architecture imp;
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block dPI2Kuf4xz7CemPH/QlaD7hcYqKhcR3NrIcD8v0oKrpOlL+W1YPz0HzOs6fITkhHPw6GpiNmP1w0 YZaKH/vuQw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block LKBMBPM2d4xR6GBUOC+BvDP5wZzXqqQ9m1OpIG5zDdhNfLoiwTXATh3DCuN3aa/Dayo8pfS08DWr aASYjAENp3kVaM5l4J30ay8/s6VsyQ5q+TLsgX3YbPs0REJKOp9L7P+uikKwGIdh8jywuE4A7peh 5WSRnykewDaNFp6V0D4= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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------------------------------------------------------------------------------- -- -- Title : req_ack -- Design : plk_mn -- ------------------------------------------------------------------------------- -- -- File : C:\my_designs\PLK_MN\plk_mn\src\lib\req_ack.vhd -- Generated : Mon Aug 1 15:58:57 2011 -- From : interface description file -- By : Itf2Vhdl ver. 1.22 -- ------------------------------------------------------------------------------- -- -- (c) B&R, 2011 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- -- -- 2011-08-01 V0.01 zelenkaj First version -- 2011-11-30 V0.02 zelenkaj removed enable at ack output -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; USE ieee.math_real.log2; USE ieee.math_real.ceil; entity req_ack is generic( ack_delay_g : integer := 1; zero_delay_g : boolean := false ); port( clk : in std_logic; rst : in std_logic; enable : in std_logic; ack : out std_logic ); end req_ack; architecture rtl of req_ack is constant iMaxCnt : integer := ack_delay_g; constant iMaxCntLog2 : integer := integer(ceil(log2(real(iMaxCnt)))); signal cnt, cnt_next : std_logic_vector(iMaxCntLog2 downto 0); signal cnt_tc : std_logic; begin genDelay : if zero_delay_g = false generate theCnter : process(clk, rst) begin if rst = '1' then cnt <= (others => '0'); elsif clk = '1' and clk'event then cnt <= cnt_next; end if; end process; cnt_next <= cnt + 1 when enable = '1' and cnt_tc /= '1' else (others => '0'); cnt_tc <= '1' when cnt = iMaxCnt else '0'; ack <= cnt_tc; end generate; genNoDelay : if zero_delay_g = true generate ack <= enable; end generate; end rtl;
------------------------------------------------------------------------------- -- -- Title : req_ack -- Design : plk_mn -- ------------------------------------------------------------------------------- -- -- File : C:\my_designs\PLK_MN\plk_mn\src\lib\req_ack.vhd -- Generated : Mon Aug 1 15:58:57 2011 -- From : interface description file -- By : Itf2Vhdl ver. 1.22 -- ------------------------------------------------------------------------------- -- -- (c) B&R, 2011 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- -- -- 2011-08-01 V0.01 zelenkaj First version -- 2011-11-30 V0.02 zelenkaj removed enable at ack output -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; USE ieee.math_real.log2; USE ieee.math_real.ceil; entity req_ack is generic( ack_delay_g : integer := 1; zero_delay_g : boolean := false ); port( clk : in std_logic; rst : in std_logic; enable : in std_logic; ack : out std_logic ); end req_ack; architecture rtl of req_ack is constant iMaxCnt : integer := ack_delay_g; constant iMaxCntLog2 : integer := integer(ceil(log2(real(iMaxCnt)))); signal cnt, cnt_next : std_logic_vector(iMaxCntLog2 downto 0); signal cnt_tc : std_logic; begin genDelay : if zero_delay_g = false generate theCnter : process(clk, rst) begin if rst = '1' then cnt <= (others => '0'); elsif clk = '1' and clk'event then cnt <= cnt_next; end if; end process; cnt_next <= cnt + 1 when enable = '1' and cnt_tc /= '1' else (others => '0'); cnt_tc <= '1' when cnt = iMaxCnt else '0'; ack <= cnt_tc; end generate; genNoDelay : if zero_delay_g = true generate ack <= enable; end generate; end rtl;
------------------------------------------------------------------------------- -- -- Title : req_ack -- Design : plk_mn -- ------------------------------------------------------------------------------- -- -- File : C:\my_designs\PLK_MN\plk_mn\src\lib\req_ack.vhd -- Generated : Mon Aug 1 15:58:57 2011 -- From : interface description file -- By : Itf2Vhdl ver. 1.22 -- ------------------------------------------------------------------------------- -- -- (c) B&R, 2011 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- -- -- 2011-08-01 V0.01 zelenkaj First version -- 2011-11-30 V0.02 zelenkaj removed enable at ack output -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; USE ieee.math_real.log2; USE ieee.math_real.ceil; entity req_ack is generic( ack_delay_g : integer := 1; zero_delay_g : boolean := false ); port( clk : in std_logic; rst : in std_logic; enable : in std_logic; ack : out std_logic ); end req_ack; architecture rtl of req_ack is constant iMaxCnt : integer := ack_delay_g; constant iMaxCntLog2 : integer := integer(ceil(log2(real(iMaxCnt)))); signal cnt, cnt_next : std_logic_vector(iMaxCntLog2 downto 0); signal cnt_tc : std_logic; begin genDelay : if zero_delay_g = false generate theCnter : process(clk, rst) begin if rst = '1' then cnt <= (others => '0'); elsif clk = '1' and clk'event then cnt <= cnt_next; end if; end process; cnt_next <= cnt + 1 when enable = '1' and cnt_tc /= '1' else (others => '0'); cnt_tc <= '1' when cnt = iMaxCnt else '0'; ack <= cnt_tc; end generate; genNoDelay : if zero_delay_g = true generate ack <= enable; end generate; end rtl;
library IEEE; use IEEE.std_logic_1164.all; entity com1_pkg1_lib2 is generic ( WITH_GENERIC: boolean:=TRUE ); port ( data_i : in std_logic; data_o : out std_logic ); end entity com1_pkg1_lib2; architecture RTL of com1_pkg1_lib2 is begin data_o <= data_i; end architecture RTL;
-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net> -- This software is distributed under the terms of the MIT License shown below. -- -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to -- deal in the Software without restriction, including without limitation the -- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or -- sell copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- -- The above copyright notice and this permission notice shall be included in -- all copies or substantial portions of the Software. -- -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -- IN THE SOFTWARE. -- Implements a synchronous register of a given width. library ieee; use ieee.std_logic_1164.all; entity reg is generic ( WIDTH : positive := 1 ); port ( clk : in std_logic; rst : in std_logic; d : in std_logic_vector(WIDTH-1 downto 0); q : out std_logic_vector(WIDTH-1 downto 0) ); end reg; architecture BHV of reg is begin process(clk, rst) begin if(rst = '1') then q <= (others => '0'); elsif(rising_edge(clk)) then q <= d; end if; end process; end BHV;
entity \test \ is end;
-- $Id: sys_tst_serloop1_n3.vhd 476 2013-01-26 22:23:53Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller <[email protected]> -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free -- Software Foundation, either version 2, or at your option any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY -- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for complete details. -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_serloop1_n3 - syn -- Description: Tester serial link for nexys3 (serport_1clock case) -- -- Dependencies: genlib/clkdivce -- bpgen/bp_rs232_2l4l_iob -- bpgen/sn_humanio -- tst_serloop_hiomap -- vlib/serport/serport_1clock -- tst_serloop -- vlib/nxcramlib/nx_cram_dummy -- -- Test bench: - -- -- Target Devices: generic -- Tool versions: xst 13.1; ghdl 0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri -- 2011-12-11 438 13.1 O40d xc6slx16-2 419 650 32 221 t 7.7 -- -- Revision History: -- Date Rev Version Comment -- 2011-12-11 438 1.0 Initial version (derived from sys_tst_serloop_n3) ------------------------------------------------------------------------------ -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; use work.xlib.all; use work.genlib.all; use work.bpgenlib.all; use work.tst_serlooplib.all; use work.serportlib.all; use work.nxcramlib.all; use work.sys_conf.all; -- ---------------------------------------------------------------------------- entity sys_tst_serloop1_n3 is -- top level -- implements nexys3_fusp_aif port ( I_CLK100 : in slbit; -- 100 MHz clock I_RXD : in slbit; -- receive data (board view) O_TXD : out slbit; -- transmit data (board view) I_SWI : in slv8; -- n3 switches I_BTN : in slv5; -- n3 buttons O_LED : out slv8; -- n3 leds O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) O_MEM_WE_N : out slbit; -- cram: write enable (act.low) O_MEM_OE_N : out slbit; -- cram: output enable (act.low) O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) O_MEM_CLK : out slbit; -- cram: clock O_MEM_CRE : out slbit; -- cram: command register enable I_MEM_WAIT : in slbit; -- cram: mem wait O_MEM_ADDR : out slv23; -- cram: address lines IO_MEM_DATA : inout slv16; -- cram: data lines O_PPCM_CE_N : out slbit; -- ppcm: ... O_PPCM_RST_N : out slbit; -- ppcm: ... O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n I_FUSP_RXD : in slbit; -- fusp: rs232 rx O_FUSP_TXD : out slbit -- fusp: rs232 tx ); end sys_tst_serloop1_n3; architecture syn of sys_tst_serloop1_n3 is signal CLK : slbit := '0'; signal RESET : slbit := '0'; signal CE_USEC : slbit := '0'; signal CE_MSEC : slbit := '0'; signal RXD : slbit := '0'; signal TXD : slbit := '0'; signal CTS_N : slbit := '0'; signal RTS_N : slbit := '0'; signal SWI : slv8 := (others=>'0'); signal BTN : slv5 := (others=>'0'); signal LED : slv8 := (others=>'0'); signal DSP_DAT : slv16 := (others=>'0'); signal DSP_DP : slv4 := (others=>'0'); signal HIO_CNTL : hio_cntl_type := hio_cntl_init; signal HIO_STAT : hio_stat_type := hio_stat_init; signal RXDATA : slv8 := (others=>'0'); signal RXVAL : slbit := '0'; signal RXHOLD : slbit := '0'; signal TXDATA : slv8 := (others=>'0'); signal TXENA : slbit := '0'; signal TXBUSY : slbit := '0'; signal SER_MONI : serport_moni_type := serport_moni_init; begin CLK <= I_CLK100; CLKDIV : clkdivce generic map ( CDUWIDTH => 8, USECDIV => sys_conf_clkdiv_usecdiv, -- syn: 100 sim: 20 MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5 port map ( CLK => CLK, CE_USEC => open, CE_MSEC => CE_MSEC ); HIO : sn_humanio generic map ( BWIDTH => 5, DEBOUNCE => sys_conf_hio_debounce) port map ( CLK => CLK, RESET => '0', CE_MSEC => CE_MSEC, SWI => SWI, BTN => BTN, LED => LED, DSP_DAT => DSP_DAT, DSP_DP => DSP_DP, I_SWI => I_SWI, I_BTN => I_BTN, O_LED => O_LED, O_ANO_N => O_ANO_N, O_SEG_N => O_SEG_N ); RESET <= BTN(0); -- BTN(0) will reset tester !! HIOMAP : tst_serloop_hiomap port map ( CLK => CLK, RESET => RESET, HIO_CNTL => HIO_CNTL, HIO_STAT => HIO_STAT, SER_MONI => SER_MONI, SWI => SWI, BTN => BTN(3 downto 0), LED => LED, DSP_DAT => DSP_DAT, DSP_DP => DSP_DP ); IOB_RS232 : bp_rs232_2l4l_iob port map ( CLK => CLK, RESET => '0', SEL => SWI(0), -- port selection RXD => RXD, TXD => TXD, CTS_N => CTS_N, RTS_N => RTS_N, I_RXD0 => I_RXD, O_TXD0 => O_TXD, I_RXD1 => I_FUSP_RXD, O_TXD1 => O_FUSP_TXD, I_CTS1_N => I_FUSP_CTS_N, O_RTS1_N => O_FUSP_RTS_N ); SERPORT : serport_1clock generic map ( CDWIDTH => 15, CDINIT => sys_conf_uart_cdinit, RXFAWIDTH => 5, TXFAWIDTH => 5) port map ( CLK => CLK, CE_MSEC => CE_MSEC, RESET => RESET, ENAXON => HIO_CNTL.enaxon, ENAESC => HIO_CNTL.enaesc, RXDATA => RXDATA, RXVAL => RXVAL, RXHOLD => RXHOLD, TXDATA => TXDATA, TXENA => TXENA, TXBUSY => TXBUSY, MONI => SER_MONI, RXSD => RXD, TXSD => TXD, RXRTS_N => RTS_N, TXCTS_N => CTS_N ); TESTER : tst_serloop port map ( CLK => CLK, RESET => RESET, CE_MSEC => CE_MSEC, HIO_CNTL => HIO_CNTL, HIO_STAT => HIO_STAT, SER_MONI => SER_MONI, RXDATA => RXDATA, RXVAL => RXVAL, RXHOLD => RXHOLD, TXDATA => TXDATA, TXENA => TXENA, TXBUSY => TXBUSY ); SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy port map ( O_MEM_CE_N => O_MEM_CE_N, O_MEM_BE_N => O_MEM_BE_N, O_MEM_WE_N => O_MEM_WE_N, O_MEM_OE_N => O_MEM_OE_N, O_MEM_ADV_N => O_MEM_ADV_N, O_MEM_CLK => O_MEM_CLK, O_MEM_CRE => O_MEM_CRE, I_MEM_WAIT => I_MEM_WAIT, O_MEM_ADDR => O_MEM_ADDR, IO_MEM_DATA => IO_MEM_DATA ); O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled O_PPCM_RST_N <= '1'; -- end syn;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v3_00_a; use proc_common_v3_00_a.proc_common_pkg.all; use proc_common_v3_00_a.ipif_pkg.all; library plbv46_slave_single_v1_01_a; use plbv46_slave_single_v1_01_a.plbv46_slave_single; library simple_timebase_v1_00_a; use simple_timebase_v1_00_a.user_logic; entity simple_timebase is generic ( C_BASEADDR : std_logic_vector := X"FFFFFFFF"; C_HIGHADDR : std_logic_vector := X"00000000"; C_SPLB_AWIDTH : integer := 32; C_SPLB_DWIDTH : integer := 128; C_SPLB_NUM_MASTERS : integer := 8; C_SPLB_MID_WIDTH : integer := 3; C_SPLB_NATIVE_DWIDTH : integer := 32; C_SPLB_P2P : integer := 0; C_SPLB_SUPPORT_BURSTS : integer := 0; C_SPLB_SMALLEST_MASTER : integer := 32; C_SPLB_CLK_PERIOD_PS : integer := 10000; C_INCLUDE_DPHASE_TIMER : integer := 0; C_FAMILY : string := "virtex5" ); port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1) ); attribute SIGIS : string; attribute SIGIS of SPLB_Clk : signal is "CLK"; attribute SIGIS of SPLB_Rst : signal is "RST"; end entity simple_timebase; architecture IMP of simple_timebase is constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0'); constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR; constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR; constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := ( ZERO_ADDR_PAD & USER_SLV_BASEADDR, ZERO_ADDR_PAD & USER_SLV_HIGHADDR ); constant USER_SLV_NUM_REG : integer := 1; constant USER_NUM_REG : integer := USER_SLV_NUM_REG; constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => pad_power2(USER_SLV_NUM_REG) ); constant IPIF_BUS2CORE_CLK_RATIO : integer := 1; constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH; constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH; constant USER_SLV_CS_INDEX : integer := 0; constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX); constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX; signal ipif_Bus2IP_Clk : std_logic; signal ipif_Bus2IP_Reset : std_logic; signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1); signal ipif_IP2Bus_WrAck : std_logic; signal ipif_IP2Bus_RdAck : std_logic; signal ipif_IP2Bus_Error : std_logic; signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1); signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1); signal ipif_Bus2IP_RNW : std_logic; signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1); signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1); signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1); signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1); signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1); signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1); signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1); signal user_IP2Bus_RdAck : std_logic; signal user_IP2Bus_WrAck : std_logic; signal user_IP2Bus_Error : std_logic; begin PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single generic map ( C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY, C_SPLB_P2P => C_SPLB_P2P, C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO, C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH, C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS, C_SPLB_AWIDTH => C_SPLB_AWIDTH, C_SPLB_DWIDTH => C_SPLB_DWIDTH, C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH, C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER, C_FAMILY => C_FAMILY ) port map ( SPLB_Clk => SPLB_Clk, SPLB_Rst => SPLB_Rst, PLB_ABus => PLB_ABus, PLB_UABus => PLB_UABus, PLB_PAValid => PLB_PAValid, PLB_SAValid => PLB_SAValid, PLB_rdPrim => PLB_rdPrim, PLB_wrPrim => PLB_wrPrim, PLB_masterID => PLB_masterID, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_RNW => PLB_RNW, PLB_BE => PLB_BE, PLB_MSize => PLB_MSize, PLB_size => PLB_size, PLB_type => PLB_type, PLB_lockErr => PLB_lockErr, PLB_wrDBus => PLB_wrDBus, PLB_wrBurst => PLB_wrBurst, PLB_rdBurst => PLB_rdBurst, PLB_wrPendReq => PLB_wrPendReq, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendPri => PLB_rdPendPri, PLB_reqPri => PLB_reqPri, PLB_TAttribute => PLB_TAttribute, Sl_addrAck => Sl_addrAck, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_rearbitrate => Sl_rearbitrate, Sl_wrDAck => Sl_wrDAck, Sl_wrComp => Sl_wrComp, Sl_wrBTerm => Sl_wrBTerm, Sl_rdDBus => Sl_rdDBus, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rdDAck => Sl_rdDAck, Sl_rdComp => Sl_rdComp, Sl_rdBTerm => Sl_rdBTerm, Sl_MBusy => Sl_MBusy, Sl_MWrErr => Sl_MWrErr, Sl_MRdErr => Sl_MRdErr, Sl_MIRQ => Sl_MIRQ, Bus2IP_Clk => ipif_Bus2IP_Clk, Bus2IP_Reset => ipif_Bus2IP_Reset, IP2Bus_Data => ipif_IP2Bus_Data, IP2Bus_WrAck => ipif_IP2Bus_WrAck, IP2Bus_RdAck => ipif_IP2Bus_RdAck, IP2Bus_Error => ipif_IP2Bus_Error, Bus2IP_Addr => ipif_Bus2IP_Addr, Bus2IP_Data => ipif_Bus2IP_Data, Bus2IP_RNW => ipif_Bus2IP_RNW, Bus2IP_BE => ipif_Bus2IP_BE, Bus2IP_CS => ipif_Bus2IP_CS, Bus2IP_RdCE => ipif_Bus2IP_RdCE, Bus2IP_WrCE => ipif_Bus2IP_WrCE ); USER_LOGIC_I : entity simple_timebase_v1_00_a.user_logic generic map ( C_SLV_DWIDTH => USER_SLV_DWIDTH, C_NUM_REG => USER_NUM_REG ) port map ( Bus2IP_Clk => ipif_Bus2IP_Clk, Bus2IP_Reset => ipif_Bus2IP_Reset, Bus2IP_Data => ipif_Bus2IP_Data, Bus2IP_BE => ipif_Bus2IP_BE, Bus2IP_RdCE => user_Bus2IP_RdCE, Bus2IP_WrCE => user_Bus2IP_WrCE, IP2Bus_Data => user_IP2Bus_Data, IP2Bus_RdAck => user_IP2Bus_RdAck, IP2Bus_WrAck => user_IP2Bus_WrAck, IP2Bus_Error => user_IP2Bus_Error ); ipif_IP2Bus_Data <= user_IP2Bus_Data; ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck; ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck; ipif_IP2Bus_Error <= user_IP2Bus_Error; user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1); user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1); end IMP;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2209.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b06x00p01n01i02209ent IS END c07s02b06x00p01n01i02209ent; ARCHITECTURE c07s02b06x00p01n01i02209arch OF c07s02b06x00p01n01i02209ent IS BEGIN TESTING: PROCESS -- All different non-numeric type declarations. -- enumerated types. type SWITCH_LEVEL is ('0', '1', 'X'); -- Local declarations. variable SWITCHV : SWITCH_LEVEL := '0'; variable k : integer; BEGIN k := SWITCHV mod '1'; assert FALSE report "***FAILED TEST: c07s02b06x00p01n01i02209 - Operators mod and rem are predefined for any integer type only." severity ERROR; wait; END PROCESS TESTING; END c07s02b06x00p01n01i02209arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2209.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b06x00p01n01i02209ent IS END c07s02b06x00p01n01i02209ent; ARCHITECTURE c07s02b06x00p01n01i02209arch OF c07s02b06x00p01n01i02209ent IS BEGIN TESTING: PROCESS -- All different non-numeric type declarations. -- enumerated types. type SWITCH_LEVEL is ('0', '1', 'X'); -- Local declarations. variable SWITCHV : SWITCH_LEVEL := '0'; variable k : integer; BEGIN k := SWITCHV mod '1'; assert FALSE report "***FAILED TEST: c07s02b06x00p01n01i02209 - Operators mod and rem are predefined for any integer type only." severity ERROR; wait; END PROCESS TESTING; END c07s02b06x00p01n01i02209arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2209.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b06x00p01n01i02209ent IS END c07s02b06x00p01n01i02209ent; ARCHITECTURE c07s02b06x00p01n01i02209arch OF c07s02b06x00p01n01i02209ent IS BEGIN TESTING: PROCESS -- All different non-numeric type declarations. -- enumerated types. type SWITCH_LEVEL is ('0', '1', 'X'); -- Local declarations. variable SWITCHV : SWITCH_LEVEL := '0'; variable k : integer; BEGIN k := SWITCHV mod '1'; assert FALSE report "***FAILED TEST: c07s02b06x00p01n01i02209 - Operators mod and rem are predefined for any integer type only." severity ERROR; wait; END PROCESS TESTING; END c07s02b06x00p01n01i02209arch;
SIGNAL I_BUFFERED : std_logic_vector(0 TO %%I_MAX); SIGNAL C_SIG : std_logic_vector(0 TO %%C_MAX); SIGNAL STATE, NEXTSTATE : std_logic_vector(%%STATEWIDTH_M1 DOWNTO 0);
SIGNAL I_BUFFERED : std_logic_vector(0 TO %%I_MAX); SIGNAL C_SIG : std_logic_vector(0 TO %%C_MAX); SIGNAL STATE, NEXTSTATE : std_logic_vector(%%STATEWIDTH_M1 DOWNTO 0);
SIGNAL I_BUFFERED : std_logic_vector(0 TO %%I_MAX); SIGNAL C_SIG : std_logic_vector(0 TO %%C_MAX); SIGNAL STATE, NEXTSTATE : std_logic_vector(%%STATEWIDTH_M1 DOWNTO 0);
-------------------------------------------------------------------------------- -- Copyright (c) 1995-2003 Xilinx, Inc. -- All Right Reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 7.1.04i -- \ \ Application : sch2vhdl -- / / Filename : ISAintfc.vhf -- /___/ /\ Timestamp : 01/05/2006 10:51:23 -- \ \ / \ -- \___\/\___\ -- --Command: C:/Xilinx/bin/nt/sch2vhdl.exe -intstyle ise -family xc9500 -flat -suppress -w ISAintfc.sch ISAintfc.vhf --Design Name: ISAintfc --Device: xc9500 --Purpose: -- This vhdl netlist is translated from an ECS schematic. It can be -- synthesis and simulted, but it should not be modified. -- library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; -- synopsys translate_off library UNISIM; use UNISIM.Vcomponents.ALL; -- synopsys translate_on entity FD_MXILINX_ISAintfc is port ( C : in std_logic; D : in std_logic; Q : out std_logic); end FD_MXILINX_ISAintfc; architecture BEHAVIORAL of FD_MXILINX_ISAintfc is attribute BOX_TYPE : string ; signal XLXN_4 : std_logic; component GND port ( G : out std_logic); end component; attribute BOX_TYPE of GND : component is "BLACK_BOX"; component FDCP port ( C : in std_logic; CLR : in std_logic; D : in std_logic; PRE : in std_logic; Q : out std_logic); end component; attribute BOX_TYPE of FDCP : component is "BLACK_BOX"; begin I_36_43 : GND port map (G=>XLXN_4); U0 : FDCP port map (C=>C, CLR=>XLXN_4, D=>D, PRE=>XLXN_4, Q=>Q); end BEHAVIORAL; library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; -- synopsys translate_off library UNISIM; use UNISIM.Vcomponents.ALL; -- synopsys translate_on entity D3_8E_MXILINX_ISAintfc is port ( A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; E : in std_logic; D0 : out std_logic; D1 : out std_logic; D2 : out std_logic; D3 : out std_logic; D4 : out std_logic; D5 : out std_logic; D6 : out std_logic; D7 : out std_logic); end D3_8E_MXILINX_ISAintfc; architecture BEHAVIORAL of D3_8E_MXILINX_ISAintfc is attribute BOX_TYPE : string ; component AND4 port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND4 : component is "BLACK_BOX"; component AND4B1 port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND4B1 : component is "BLACK_BOX"; component AND4B2 port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND4B2 : component is "BLACK_BOX"; component AND4B3 port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND4B3 : component is "BLACK_BOX"; begin I_36_30 : AND4 port map (I0=>A2, I1=>A1, I2=>A0, I3=>E, O=>D7); I_36_31 : AND4B1 port map (I0=>A0, I1=>A2, I2=>A1, I3=>E, O=>D6); I_36_32 : AND4B1 port map (I0=>A1, I1=>A2, I2=>A0, I3=>E, O=>D5); I_36_33 : AND4B2 port map (I0=>A1, I1=>A0, I2=>A2, I3=>E, O=>D4); I_36_34 : AND4B1 port map (I0=>A2, I1=>A0, I2=>A1, I3=>E, O=>D3); I_36_35 : AND4B2 port map (I0=>A2, I1=>A0, I2=>A1, I3=>E, O=>D2); I_36_36 : AND4B2 port map (I0=>A2, I1=>A1, I2=>A0, I3=>E, O=>D1); I_36_37 : AND4B3 port map (I0=>A2, I1=>A1, I2=>A0, I3=>E, O=>D0); end BEHAVIORAL; library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; -- synopsys translate_off library UNISIM; use UNISIM.Vcomponents.ALL; -- synopsys translate_on entity FD4CE_MXILINX_ISAintfc is port ( C : in std_logic; CE : in std_logic; CLR : in std_logic; D0 : in std_logic; D1 : in std_logic; D2 : in std_logic; D3 : in std_logic; Q0 : out std_logic; Q1 : out std_logic; Q2 : out std_logic; Q3 : out std_logic); end FD4CE_MXILINX_ISAintfc; architecture BEHAVIORAL of FD4CE_MXILINX_ISAintfc is attribute BOX_TYPE : string ; component FDCE port ( C : in std_logic; CE : in std_logic; CLR : in std_logic; D : in std_logic; Q : out std_logic); end component; attribute BOX_TYPE of FDCE : component is "BLACK_BOX"; begin U0 : FDCE port map (C=>C, CE=>CE, CLR=>CLR, D=>D0, Q=>Q0); U1 : FDCE port map (C=>C, CE=>CE, CLR=>CLR, D=>D1, Q=>Q1); U2 : FDCE port map (C=>C, CE=>CE, CLR=>CLR, D=>D2, Q=>Q2); U3 : FDCE port map (C=>C, CE=>CE, CLR=>CLR, D=>D3, Q=>Q3); end BEHAVIORAL; library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; -- synopsys translate_off library UNISIM; use UNISIM.Vcomponents.ALL; -- synopsys translate_on entity ISAintfc is port ( BRDSELO : in std_logic; FIFOCTL : in std_logic_vector (7 downto 0); IORN : in std_logic; IOWN : in std_logic; SA0 : in std_logic; SA1 : in std_logic; SA2 : in std_logic; SA3 : in std_logic; SA4 : in std_logic; PLLOUT : in std_logic; A2DDATA : out std_logic; A2DSTAT : out std_logic; D2A0 : out std_logic; D2A1 : out std_logic; D2A2 : out std_logic; FIFO : out std_logic; FIFOSTAT : out std_logic; IOCS16N : out std_logic; I2CSCL : out std_logic; LBSD3 : out std_logic; SIOR : out std_logic; SIORN : out std_logic; SIORW : out std_logic; SIOW : out std_logic; SIOWN : out std_logic; SYSCTL : out std_logic; BSD : inout std_logic_vector (15 downto 0); I2CSDA : inout std_logic); end ISAintfc; architecture BEHAVIORAL of ISAintfc is attribute BOX_TYPE : string ; attribute HU_SET : string ; signal BRDSELI : std_logic; signal FSEL : std_logic; signal XLXN_157 : std_logic; signal XLXN_158 : std_logic; signal XLXN_159 : std_logic; signal XLXN_161 : std_logic; signal XLXN_206 : std_logic; signal XLXN_210 : std_logic; signal XLXN_212 : std_logic; signal XLXN_214 : std_logic; signal XLXN_216 : std_logic; signal XLXN_221 : std_logic; signal XLXN_222 : std_logic; signal XLXN_370 : std_logic; -- signal XLXN_223a : std_logic; -- signal XLXN_223b : std_logic; -- signal XLXN_223c : std_logic; -- signal XLXN_223d : std_logic; -- signal XLXN_223e : std_logic; -- signal XLXN_223f : std_logic; signal XLXN_225 : std_logic; signal XLXN_229 : std_logic; signal XLXN_230 : std_logic; signal A2DSTAT_DUMMY : std_logic; signal SIOWN_DUMMY : std_logic; signal SIOR_DUMMY : std_logic; signal SIORN_DUMMY : std_logic; signal SIOW_DUMMY : std_logic; signal SIORW_DUMMY : std_logic; signal D2A2_DUMMY : std_logic; -- signal MY_SIORW : std_logic; -- signal cnt : std_logic_vector(1 downto 0):="00"; component INV port ( I : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of INV : component is "BLACK_BOX"; component FD4CE_MXILINX_ISAintfc port ( C : in std_logic; CE : in std_logic; CLR : in std_logic; D0 : in std_logic; D1 : in std_logic; D2 : in std_logic; D3 : in std_logic; Q0 : out std_logic; Q1 : out std_logic; Q2 : out std_logic; Q3 : out std_logic); end component; component D3_8E_MXILINX_ISAintfc port ( A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; E : in std_logic; D0 : out std_logic; D1 : out std_logic; D2 : out std_logic; D3 : out std_logic; D4 : out std_logic; D5 : out std_logic; D6 : out std_logic; D7 : out std_logic); end component; component GND port ( G : out std_logic); end component; attribute BOX_TYPE of GND : component is "BLACK_BOX"; component VCC port ( P : out std_logic); end component; attribute BOX_TYPE of VCC : component is "BLACK_BOX"; component NAND2 port ( I0 : in std_logic; I1 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of NAND2 : component is "BLACK_BOX"; component NOR2 port ( I0 : in std_logic; I1 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of NOR2 : component is "BLACK_BOX"; component BUFE port ( E : in std_logic; I : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of BUFE : component is "BLACK_BOX"; component AND5 port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; I4 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND5 : component is "BLACK_BOX"; component AND2 port ( I0 : in std_logic; I1 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND2 : component is "BLACK_BOX"; component FD_MXILINX_ISAintfc port ( C : in std_logic; D : in std_logic; Q : out std_logic); end component; attribute HU_SET of XLXI_60 : label is "XLXI_60_0"; attribute HU_SET of XLXI_61 : label is "XLXI_61_1"; attribute HU_SET of XLXI_102 : label is "XLXI_102_2"; attribute HU_SET of XLXI_103 : label is "XLXI_103_3"; begin A2DSTAT <= A2DSTAT_DUMMY; SIOR <= SIOR_DUMMY; SIORN <= SIORN_DUMMY; SIOW <= SIOW_DUMMY; SIOWN <= SIOWN_DUMMY; D2A2 <= D2A2_DUMMY; XLXI_30 : INV port map (I=>SIOW_DUMMY, O=>SIOWN_DUMMY); XLXI_143 : VCC port map (P=>XLXN_370); XLXI_60 : FD4CE_MXILINX_ISAintfc port map (C=>SIOWN_DUMMY, CE=>FSEL, CLR=>XLXN_210, D0=>BSD(0), D1=>BSD(1), D2=>BSD(2), D3=>BSD(3), Q0=>XLXN_157, Q1=>XLXN_158, Q2=>XLXN_159, Q3=>LBSD3); XLXI_61 : D3_8E_MXILINX_ISAintfc port map (A0=>XLXN_157, A1=>XLXN_158, A2=>XLXN_159, E=>XLXN_206, D0=>FIFO, D1=>A2DSTAT_DUMMY, D2=>A2DDATA, D3=>D2A0, D4=>D2A1, D5=>D2A2_DUMMY, D6=>SYSCTL, D7=>FIFOSTAT); XLXI_63 : GND port map (G=>XLXN_210); XLXI_66 : NAND2 port map (I0=>SIORN_DUMMY, I1=>SIOWN_DUMMY, O=>SIORW); XLXI_69 : INV port map (I=>SIOR_DUMMY, O=>SIORN_DUMMY); XLXI_75 : NOR2 port map (I0=>IOWN, I1=>BRDSELO, O=>SIOW_DUMMY); XLXI_76 : NOR2 port map (I0=>IORN, I1=>BRDSELO, O=>SIOR_DUMMY); XLXI_80 : BUFE port map (E=>BRDSELI, I=>XLXN_161, O=>IOCS16N); XLXI_81 : INV port map (I=>BRDSELO, O=>BRDSELI); XLXI_82 : GND port map (G=>XLXN_161); XLXI_90 : INV port map (I=>FSEL, O=>XLXN_206); XLXI_92 : AND5 port map (I0=>BRDSELI, I1=>SA3, I2=>SA2, I3=>SA1, -- I4=>SA0, I4=>XLXN_370, O=>FSEL); XLXI_93 : AND2 -- port map (I0=>FIFOCTL(1), -- I1=>A2DSTAT_DUMMY, port map (I0=>FIFOCTL(7), I1=>D2A2_DUMMY, O=>XLXN_230); XLXI_94 : AND2 port map (I0=>SIOR_DUMMY, I1=>XLXN_230, O=>XLXN_229); XLXI_95 : NAND2 port map (I0=>SIOW_DUMMY, I1=>XLXN_230, O=>XLXN_216); XLXI_96 : INV port map (I=>BSD(0), O=>XLXN_212); XLXI_97 : INV port map (I=>BSD(1), O=>XLXN_214); XLXI_98 : INV port map (I=>XLXN_221, O=>XLXN_222); XLXI_99 : INV port map (I=>XLXN_225, O=>I2CSCL); XLXI_100 : BUFE port map (E=>XLXN_229, I=>I2CSDA, O=>BSD(0)); XLXI_101 : BUFE port map (E=>XLXN_221, I=>XLXN_222, O=>I2CSDA); XLXI_102 : FD_MXILINX_ISAintfc port map (C=>XLXN_216, D=>XLXN_212, Q=>XLXN_221); XLXI_103 : FD_MXILINX_ISAintfc port map (C=>XLXN_216, D=>XLXN_214, Q=>XLXN_225); -- delay: process(pllout,FSEL) -- begin -- if FSEL = '1' then -- cnt <= "00"; -- elsif cnt = "00" and FSEL = '0' then -- cnt <= "01"; -- elsif cnt = "01" and FSEL = '0' then -- cnt <= "10"; -- else -- cnt <= cnt; -- end if; -- end process delay; end BEHAVIORAL;
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use std.textio.all; entity test_typecasts is end test_typecasts; architecture behavioural of test_typecasts is constant natural_value : natural range 255 downto 0 := 164; constant slv_value : std_logic_vector(7 downto 0) := "10100100"; function chr(sl: std_logic) return character is variable c: character; begin case sl is when 'U' => c:= 'U'; when 'X' => c:= 'X'; when '0' => c:= '0'; when '1' => c:= '1'; when 'Z' => c:= 'Z'; when 'W' => c:= 'W'; when 'L' => c:= 'L'; when 'H' => c:= 'H'; when '-' => c:= '-'; end case; return c; end chr; function str(slv: std_logic_vector) return string is variable result : string (1 to slv'length); variable r : integer; begin r := 1; for i in slv'range loop result(r) := chr(slv(i)); r := r + 1; end loop; return result; end str; begin process variable natural_holder : natural range 255 downto 0; variable slv_holder : std_logic_vector(7 downto 0); variable oline: line; begin natural_holder := to_integer(unsigned(slv_value)); assert natural_holder = natural_value report "1 natural and slv should match" severity error; slv_holder := std_logic_vector(to_unsigned(natural_value, slv_holder'length)); assert slv_holder = slv_value report "2 slv and natural should match" severity error; write(oline, str(slv_holder)); write(oline, '='); write(oline, str(slv_value)); writeline(output, oline); wait; end process; end behavioural;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity speccy is Port ( CLK50 : in std_logic; MCU_READY : in std_logic; KEYB_CLK : in std_logic; KEYB_DATA : in std_logic; SD_MOSI : out std_logic; SD_MISO : in std_logic; SD_SCK : out std_logic; SD_CS : out std_logic; SOUND_L : out std_logic; SOUND_R : out std_logic; SRAM_A : out std_logic_vector(17 downto 0); SRAM_D : inout std_logic_vector(15 downto 0); SRAM_WE : out std_logic; SRAM_OE : out std_logic; SRAM_UB : out std_logic; SRAM_LB : out std_logic; SRAM_CE0 : out std_logic; SRAM_CE1 : out std_logic; VGA_R : out std_logic_vector(3 downto 0); VGA_G : out std_logic_vector(3 downto 0); VGA_B : out std_logic_vector(3 downto 0); VGA_HSYNC : out std_logic; VGA_VSYNC : out std_logic ); end speccy; architecture rtl of speccy is signal CLK : std_logic; signal VGA_CLK : std_logic; signal LOCKED : std_logic; signal RESET : std_logic; signal TICK : unsigned(3 downto 0); signal CLC_TICK : std_logic; signal CPU_CLK : std_logic; signal CPU_RESET : std_logic; signal CPU_INT : std_logic; signal CPU_NMI : std_logic; signal CPU_MREQ : std_logic; signal CPU_IORQ : std_logic; signal CPU_M1 : std_logic; signal CPU_RD : std_logic; signal CPU_WR : std_logic; signal CPU_A : std_logic_vector(15 downto 0); signal CPU_DI : std_logic_vector(7 downto 0); signal CPU_DO : std_logic_vector(7 downto 0); signal ROM_DO : std_logic_vector(7 downto 0); signal DIVROM_DO : std_logic_vector(7 downto 0); signal RAM_A : std_logic_vector(19 downto 0); signal RAM_DO : std_logic_vector(7 downto 0); signal RAM_RW : std_logic; signal RAM_REQ : std_logic; signal VRAM_WR : std_logic_vector(0 downto 0); signal VRAM_A : std_logic_vector(13 downto 0); signal VRAM_VA : std_logic_vector(12 downto 0); signal VRAM_VD : std_logic_vector(7 downto 0); signal BORDERCOLOR : std_logic_vector(2 downto 0); signal KEYB_DO : std_logic_vector(4 downto 0); signal RESET_TICK : std_logic; signal RESET_ONESHOT: std_logic; signal NMI_TICK : std_logic; signal NMI_ONESHOT : std_logic; signal BEEPER : std_logic; signal CLC : std_logic; signal AY_CS : std_logic; signal AY_DO : std_logic_vector(7 downto 0); signal AY_A : std_logic_vector(7 downto 0); signal AY_B : std_logic_vector(7 downto 0); signal AY_C : std_logic_vector(7 downto 0); signal AUDIO_L : std_logic_vector(9 downto 0); signal AUDIO_R : std_logic_vector(9 downto 0); ------------------------- 128K ------------------------- signal PAGE : std_logic_vector(2 downto 0) := "000"; signal SCREEN : std_logic := '0'; signal ROMSEL : std_logic := '0'; signal DISABLE : std_logic := '0'; ------------------------ DIVMMC ------------------------ signal BANK : std_logic_vector(5 downto 0) := "000000"; signal CONMEM : std_logic := '0'; signal MAPRAM : std_logic := '0'; signal MAPCOND : std_logic := '0'; signal AUTOMAP : std_logic := '0'; signal counter : unsigned(3 downto 0); -- Shift register has an extra bit because we write on the -- falling edge and read on the rising edge signal shift_reg : std_logic_vector(8 downto 0); signal in_reg : std_logic_vector(7 downto 0); begin u_CLOCK : entity work.clock port map( CLK50 => CLK50, CLK => CLK, VGA_CLK => VGA_CLK, LOCKED => LOCKED ); u_VIDEO : entity work.video port map( VGA_CLK => VGA_CLK, RESET => '0', BORDERCOLOR => BORDERCOLOR, INT => CPU_INT, VA => VRAM_VA, VD => VRAM_VD, VGA_R => VGA_R, VGA_G => VGA_G, VGA_B => VGA_B, VGA_HSYNC => VGA_HSYNC, VGA_VSYNC => VGA_VSYNC ); u_ROM : entity work.rom port map( clka => CLK, addra => ROMSEL & CPU_A(13 downto 0), douta => ROM_DO ); u_DIVROM : entity work.divrom port map( clka => CLK, addra => CPU_A(12 downto 0), douta => DIVROM_DO ); u_VRAM : entity work.vram port map( clka => CLK, wea => VRAM_WR, addra => VRAM_A, dina => CPU_DO, clkb => VGA_CLK, addrb => SCREEN & VRAM_VA, doutb => VRAM_VD ); u_CPU : entity work.T80se port map( RESET_n => CPU_RESET, --not RESET, CLK_n => CLK, CLKEN => CPU_CLK, WAIT_n => '1', INT_n => CPU_INT, NMI_n => CPU_NMI, BUSRQ_n => '1', M1_n => CPU_M1, MREQ_n => CPU_MREQ, IORQ_n => CPU_IORQ, RD_n => CPU_RD, WR_n => CPU_WR, RFSH_n => OPEN, HALT_n => OPEN, BUSAK_n => OPEN, A => CPU_A, DI => CPU_DI, DO => CPU_DO ); u_RAM : entity work.memctrl port map( CLK => CLK, RESET => RESET, MEM_A => RAM_A, MEM_DI => CPU_DO, MEM_DO => RAM_DO, MEM_RW => RAM_RW, MEM_REQ => RAM_REQ, MEM_ACK => open, SRAM_A => SRAM_A, SRAM_D => SRAM_D, SRAM_CE0 => SRAM_CE0, SRAM_CE1 => SRAM_CE1, SRAM_OE => SRAM_OE, SRAM_WE => SRAM_WE, SRAM_UB => SRAM_UB, SRAM_LB => SRAM_LB ); u_KEYBOARD: entity work.keyboard port map( CLK => CLK, RESET => RESET, PS2_CLK => KEYB_CLK, PS2_DATA => KEYB_DATA, KEYB_ADDR => CPU_A(15 downto 8), KEYB_DATA => KEYB_DO, RESET_TICK => RESET_TICK, NMI_TICK => NMI_TICK ); u_ONESHOT_RESET : entity work.oneshot port map( CLK => CLK, RESET => RESET, ONESHOT_IN => RESET_TICK, ONESHOT_OUT => RESET_ONESHOT ); u_ONESHOT_NMI : entity work.oneshot port map( CLK => CLK, RESET => RESET, ONESHOT_IN => NMI_TICK, ONESHOT_OUT => NMI_ONESHOT ); u_AY8910 : entity work.ay8910 port map( CLK => CLK, CLC => CLC, RESET => CPU_RESET, BDIR => not CPU_WR, CS => AY_CS, BC => CPU_A(14), DI => CPU_DO, DO => AY_DO, OUT_A => AY_A, OUT_B => AY_B, OUT_C => AY_C ); u_DAC_L : entity work.dac port map( clk_i => CLK, res_n_i => CPU_RESET, dac_i => AUDIO_L, dac_o => SOUND_L ); u_DAC_R : entity work.dac port map( clk_i => CLK, res_n_i => CPU_RESET, dac_i => AUDIO_R, dac_o => SOUND_R ); AUDIO_L <= std_logic_vector(unsigned('0' & AY_A & '0') + unsigned('0' & BEEPER & AY_B)); AUDIO_R <= std_logic_vector(unsigned('0' & AY_C & '0') + unsigned('0' & BEEPER & AY_B)); CPU_RESET <= not RESET_ONESHOT; reset_and_clock : process(CLK) begin if rising_edge(CLK) then if LOCKED = '0' or MCU_READY = '0' then TICK <= "0000"; RESET <= '1'; CPU_CLK <= '0'; CLC <= '0'; CLC_TICK <= '0'; else CPU_CLK <= '0'; CLC <= '0'; TICK <= TICK + 1; if TICK = "1111" then CPU_CLK <= '1'; RESET <= '0'; CLC_TICK <= not CLC_TICK; if CLC_TICK = '1' then CLC <= '1'; end if; end if; end if; end if; end process; CPU_DI <= ROM_DO when CPU_A(15 downto 14) = "00" and CPU_MREQ = '0' and AUTOMAP = '0' and CONMEM = '0' else DIVROM_DO when CPU_A(15 downto 13) = "000" and CPU_MREQ = '0' and (AUTOMAP = '1' or CONMEM = '1') else RAM_DO when CPU_A(15 downto 13) = "001" and CPU_MREQ = '0' and (AUTOMAP = '1' or CONMEM = '1') else RAM_DO when CPU_A(15 downto 14) /= "00" and CPU_MREQ = '0' else AY_DO when AY_CS = '0' else in_reg when CPU_A(7 downto 0) = X"EB" and CPU_IORQ = '0' else "111" & KEYB_DO when CPU_A(0) = '0' and CPU_IORQ = '0' else "11111111"; VRAM_WR <= "1" when ((CPU_A(15 downto 13) = "010") or (CPU_A(15 downto 13) = "110" and PAGE(2) = '1' and PAGE(0) = '1')) and CPU_MREQ = '0' and CPU_WR = '0' else "0"; VRAM_A <= '0' & CPU_A(12 downto 0) when CPU_A(15 downto 13) = "010" else PAGE(1) & CPU_A(12 downto 0); RAM_A <= '1' & BANK & CPU_A(12 downto 0) when CPU_A(15 downto 13) = "001" and (AUTOMAP = '1' or CONMEM = '1') else "000" & PAGE & CPU_A(13 downto 0) when CPU_A(15 downto 14) = "11" else "000" & CPU_A(14) & CPU_A; RAM_RW <= '1' when CPU_MREQ = '0' and CPU_WR = '0' and (CPU_A(15 downto 14) /= "00" or (CPU_A(15 downto 13) = "001" and (AUTOMAP = '1' or CONMEM = '1'))) else '0'; RAM_REQ <= '1' when TICK = "0100" else '0'; AY_CS <= '0' when CPU_A(15) = '1' and CPU_A(13) = '1' and CPU_A(1) = '0' and CPU_M1 = '1' and CPU_IORQ = '0' else '1'; process(CLK) begin if rising_edge(CLK) then if CPU_RESET = '0' then SD_CS <= '1'; PAGE <= "000"; SCREEN <= '0'; ROMSEL <= '0'; DISABLE <= '0'; elsif TICK = "0011" then if CPU_MREQ = '0' then if CPU_M1 = '0' and CPU_A(15 downto 3) = "0001111111111" then MAPCOND <= '0'; elsif (CPU_M1 = '0' and (CPU_A = X"0000" or CPU_A = X"0008" or CPU_A = X"0038" or CPU_A = X"0066" or CPU_A = X"04C6" or CPU_A = X"0562")) or (CPU_M1 = '0' and CPU_A(15 downto 8) = X"3D") then MAPCOND <= '1'; end if; if MAPCOND = '1' or (CPU_M1 = '0' and CPU_A(15 downto 8) = X"3D") then AUTOMAP <= '1'; else AUTOMAP <= '0'; end if; end if; if CPU_IORQ = '0' and CPU_WR = '0' then if CPU_A(7 downto 0) = X"E7" then -- Port #E7 SD_CS <= CPU_DO(0); elsif CPU_A(7 downto 0) = X"E3" then -- Port #E3 BANK <= CPU_DO(5 downto 0); CONMEM <= CPU_DO(7); MAPRAM <= CPU_DO(6) or MAPRAM; elsif CPU_A(15) = '0' and CPU_A(1) = '0' then -- Port #7FFD if DISABLE = '0' then -- not locked in 48K-mode PAGE <= CPU_DO(2 downto 0); SCREEN <= CPU_DO(3); ROMSEL <= CPU_DO(4); DISABLE <= CPU_DO(5); end if; elsif CPU_A(0) = '0' then -- Port #FE BORDERCOLOR <= CPU_DO(2 downto 0); BEEPER <= CPU_DO(4); end if; end if; end if; end if; end process; CPU_NMI <= '0' when NMI_ONESHOT = '1' and MAPCOND = '0' else '1'; sd_card : process(CLK) begin if rising_edge(CLK) then if CPU_RESET = '0' then shift_reg <= (others => '1'); in_reg <= (others => '1'); counter <= "1111"; -- Idle elsif TICK = "0011" then if counter = "1111" then in_reg <= shift_reg(7 downto 0); if CPU_IORQ = '0' and CPU_A(7 downto 0) = X"EB" then if CPU_WR = '1' then shift_reg <= (others => '1'); else shift_reg <= CPU_DO & '1'; end if; counter <= "0000"; end if; else counter <= counter + 1; if counter(0) = '0' then shift_reg(0) <= SD_MISO; else shift_reg <= shift_reg(7 downto 0) & '1'; end if; end if; end if; end if; end process; SD_SCK <= counter(0); SD_MOSI <= shift_reg(8); end rtl;
entity tb_cnt01 is end tb_cnt01; library ieee; use ieee.std_logic_1164.all; architecture behav of tb_cnt01 is signal clk : std_logic; signal rst : std_logic; signal clr : std_logic; signal en : std_logic; signal cnt : std_logic_vector (9 downto 0); begin dut: entity work.cnt01 port map (clock => clk, reset => rst, clear_count => clr, enable => en, counter_out => cnt); process procedure pulse is begin clk <= '0'; wait for 1 ns; clk <= '1'; wait for 1 ns; end pulse; begin clk <= '0'; clr <= '0'; en <= '0'; rst <= '1'; wait for 1 ns; assert cnt = "0000000000" severity failure; rst <= '0'; pulse; assert cnt = "0000000000" severity failure; en <= '1'; pulse; assert cnt = "0000000001" severity failure; en <= '0'; pulse; assert cnt = "0000000001" severity failure; en <= '1'; pulse; assert cnt = "0000000010" severity failure; en <= '1'; pulse; assert cnt = "0000000011" severity failure; en <= '1'; clr <= '1'; pulse; assert cnt = "0000000000" severity failure; en <= '1'; clr <= '0'; pulse; assert cnt = "0000000001" severity failure; wait; end process; end behav;
-- ------------------------------------------------------------- -- -- File Name: hdlsrc\hdlcodercpu_eml\SinglePortRAM_Inst0.vhd -- Created: 2014-08-26 11:41:14 -- -- Generated by MATLAB 8.3 and HDL Coder 3.4 -- -- ------------------------------------------------------------- -- ------------------------------------------------------------- -- -- Module: SinglePortRAM_Inst0 -- Source Path: hdlcodercpu_eml/CPU_Subsystem_8_bit/SinglePortRAM_Inst0 -- Hierarchy Level: 1 -- -- ------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; ENTITY SinglePortRAM_Inst0 IS PORT( clk : IN std_logic; enb : IN std_logic; din : IN std_logic_vector(7 DOWNTO 0); -- int8 addr : IN std_logic_vector(7 DOWNTO 0); -- uint8 we : IN std_logic; -- ufix1 dout : OUT std_logic_vector(7 DOWNTO 0) -- int8 ); END SinglePortRAM_Inst0; ARCHITECTURE rtl OF SinglePortRAM_Inst0 IS -- Component Declarations COMPONENT SinglePortRAM_256x8b PORT( clk : IN std_logic; enb : IN std_logic; din : IN std_logic_vector(7 DOWNTO 0); -- int8 addr : IN std_logic_vector(7 DOWNTO 0); -- uint8 we : IN std_logic; -- ufix1 dout : OUT std_logic_vector(7 DOWNTO 0) -- int8 ); END COMPONENT; -- Component Configuration Statements FOR ALL : SinglePortRAM_256x8b USE ENTITY work.SinglePortRAM_256x8b(rtl); -- Signals SIGNAL dout_tmp : std_logic_vector(7 DOWNTO 0); -- ufix8 BEGIN u_SinglePortRAM_256x8b : SinglePortRAM_256x8b PORT MAP( clk => clk, enb => enb, din => din, -- int8 addr => addr, -- uint8 we => we, -- ufix1 dout => dout_tmp -- int8 ); dout <= dout_tmp; END rtl;
-------------------------------------------------------------------------------- -- -- FIFO Generator Core Demo Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: fg_tb_pkg.vhd -- -- Description: -- This is the demo testbench package file for fifo_generator_v8.4 core. -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE ieee.std_logic_arith.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; PACKAGE fg_tb_pkg IS FUNCTION divroundup ( data_value : INTEGER; divisor : INTEGER) RETURN INTEGER; ------------------------ FUNCTION if_then_else ( condition : BOOLEAN; true_case : INTEGER; false_case : INTEGER) RETURN INTEGER; ------------------------ FUNCTION if_then_else ( condition : BOOLEAN; true_case : STD_LOGIC; false_case : STD_LOGIC) RETURN STD_LOGIC; ------------------------ FUNCTION if_then_else ( condition : BOOLEAN; true_case : TIME; false_case : TIME) RETURN TIME; ------------------------ FUNCTION log2roundup ( data_value : INTEGER) RETURN INTEGER; ------------------------ FUNCTION hexstr_to_std_logic_vec( arg1 : string; size : integer ) RETURN std_logic_vector; ------------------------ COMPONENT fg_tb_rng IS GENERIC (WIDTH : integer := 8; SEED : integer := 3); PORT ( CLK : IN STD_LOGIC; RESET : IN STD_LOGIC; ENABLE : IN STD_LOGIC; RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) ); END COMPONENT; ------------------------ COMPONENT fg_tb_dgen IS GENERIC ( C_DIN_WIDTH : INTEGER := 32; C_DOUT_WIDTH : INTEGER := 32; C_CH_TYPE : INTEGER := 0; TB_SEED : INTEGER := 2 ); PORT ( RESET : IN STD_LOGIC; WR_CLK : IN STD_LOGIC; PRC_WR_EN : IN STD_LOGIC; FULL : IN STD_LOGIC; WR_EN : OUT STD_LOGIC; WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) ); END COMPONENT; ------------------------ COMPONENT fg_tb_dverif IS GENERIC( C_DIN_WIDTH : INTEGER := 0; C_DOUT_WIDTH : INTEGER := 0; C_USE_EMBEDDED_REG : INTEGER := 0; C_CH_TYPE : INTEGER := 0; TB_SEED : INTEGER := 2 ); PORT( RESET : IN STD_LOGIC; RD_CLK : IN STD_LOGIC; PRC_RD_EN : IN STD_LOGIC; EMPTY : IN STD_LOGIC; DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); RD_EN : OUT STD_LOGIC; DOUT_CHK : OUT STD_LOGIC ); END COMPONENT; ------------------------ COMPONENT fg_tb_pctrl IS GENERIC( AXI_CHANNEL : STRING := "NONE"; C_APPLICATION_TYPE : INTEGER := 0; C_DIN_WIDTH : INTEGER := 0; C_DOUT_WIDTH : INTEGER := 0; C_WR_PNTR_WIDTH : INTEGER := 0; C_RD_PNTR_WIDTH : INTEGER := 0; C_CH_TYPE : INTEGER := 0; FREEZEON_ERROR : INTEGER := 0; TB_STOP_CNT : INTEGER := 2; TB_SEED : INTEGER := 2 ); PORT( RESET_WR : IN STD_LOGIC; RESET_RD : IN STD_LOGIC; WR_CLK : IN STD_LOGIC; RD_CLK : IN STD_LOGIC; FULL : IN STD_LOGIC; EMPTY : IN STD_LOGIC; ALMOST_FULL : IN STD_LOGIC; ALMOST_EMPTY : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); DOUT_CHK : IN STD_LOGIC; PRC_WR_EN : OUT STD_LOGIC; PRC_RD_EN : OUT STD_LOGIC; RESET_EN : OUT STD_LOGIC; SIM_DONE : OUT STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; ------------------------ COMPONENT fg_tb_synth IS GENERIC( FREEZEON_ERROR : INTEGER := 0; TB_STOP_CNT : INTEGER := 0; TB_SEED : INTEGER := 1 ); PORT( CLK : IN STD_LOGIC; RESET : IN STD_LOGIC; SIM_DONE : OUT STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; ------------------------ COMPONENT gc_command_fifo_top IS PORT ( CLK : IN std_logic; DATA_COUNT : OUT std_logic_vector(5-1 DOWNTO 0); RST : IN std_logic; PROG_FULL : OUT std_logic; WR_EN : IN std_logic; RD_EN : IN std_logic; DIN : IN std_logic_vector(29-1 DOWNTO 0); DOUT : OUT std_logic_vector(29-1 DOWNTO 0); FULL : OUT std_logic; EMPTY : OUT std_logic); END COMPONENT; ------------------------ END fg_tb_pkg; PACKAGE BODY fg_tb_pkg IS FUNCTION divroundup ( data_value : INTEGER; divisor : INTEGER) RETURN INTEGER IS VARIABLE div : INTEGER; BEGIN div := data_value/divisor; IF ( (data_value MOD divisor) /= 0) THEN div := div+1; END IF; RETURN div; END divroundup; --------------------------------- FUNCTION if_then_else ( condition : BOOLEAN; true_case : INTEGER; false_case : INTEGER) RETURN INTEGER IS VARIABLE retval : INTEGER := 0; BEGIN IF condition=false THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; --------------------------------- FUNCTION if_then_else ( condition : BOOLEAN; true_case : STD_LOGIC; false_case : STD_LOGIC) RETURN STD_LOGIC IS VARIABLE retval : STD_LOGIC := '0'; BEGIN IF condition=false THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; --------------------------------- FUNCTION if_then_else ( condition : BOOLEAN; true_case : TIME; false_case : TIME) RETURN TIME IS VARIABLE retval : TIME := 0 ps; BEGIN IF condition=false THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; ------------------------------- FUNCTION log2roundup ( data_value : INTEGER) RETURN INTEGER IS VARIABLE width : INTEGER := 0; VARIABLE cnt : INTEGER := 1; BEGIN IF (data_value <= 1) THEN width := 1; ELSE WHILE (cnt < data_value) LOOP width := width + 1; cnt := cnt 2; END LOOP; END IF; RETURN width; END log2roundup; ------------------------------------------------------------------------------ -- hexstr_to_std_logic_vec -- This function converts a hex string to a std_logic_vector ------------------------------------------------------------------------------ FUNCTION hexstr_to_std_logic_vec( arg1 : string; size : integer ) RETURN std_logic_vector IS VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0'); VARIABLE bin : std_logic_vector(3 DOWNTO 0); VARIABLE index : integer := 0; BEGIN FOR i IN arg1'reverse_range LOOP CASE arg1(i) IS WHEN '0' => bin := (OTHERS => '0'); WHEN '1' => bin := (0 => '1', OTHERS => '0'); WHEN '2' => bin := (1 => '1', OTHERS => '0'); WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0'); WHEN '4' => bin := (2 => '1', OTHERS => '0'); WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0'); WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0'); WHEN '7' => bin := (3 => '0', OTHERS => '1'); WHEN '8' => bin := (3 => '1', OTHERS => '0'); WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0'); WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1'); WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1'); WHEN 'B' => bin := (2 => '0', OTHERS => '1'); WHEN 'b' => bin := (2 => '0', OTHERS => '1'); WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1'); WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1'); WHEN 'D' => bin := (1 => '0', OTHERS => '1'); WHEN 'd' => bin := (1 => '0', OTHERS => '1'); WHEN 'E' => bin := (0 => '0', OTHERS => '1'); WHEN 'e' => bin := (0 => '0', OTHERS => '1'); WHEN 'F' => bin := (OTHERS => '1'); WHEN 'f' => bin := (OTHERS => '1'); WHEN OTHERS => FOR j IN 0 TO 3 LOOP bin(j) := 'X'; END LOOP; END CASE; FOR j IN 0 TO 3 LOOP IF (index4)+j < size THEN result((index*4)+j) := bin(j); END IF; END LOOP; index := index + 1; END LOOP; RETURN result; END hexstr_to_std_logic_vec; END fg_tb_pkg;
architecture RTL of BLOCK_EXAMPLE is begin -- correct block format BLK : block is begin BLK2 : block is begin BLK3 : block is begin end block BLK3; end block BLK2; BLK4 : block is begin BLK5 : block is begin BLK6 : block is begin end block BLK6; end block BLK5; end block BLK4; end block BLK; b1 : block begin end block; process begin end process; b1 : block begin process begin end process; end block; assert true report "something" severity failure; end architecture RTL;
------------------------------------------------------------------------------- -- Title : Onewire Master Testbench - Reset Operation ------------------------------------------------------------------------------- -- Author : [email protected] ------------------------------------------------------------------------------- -- Created : 2014-12-13 ------------------------------------------------------------------------------- -- Copyright (c) 2014, Carl Treudler -- All Rights Reserved. -- -- The file is part for the Loa project and is released under the -- 3-clause BSD license. See the file `LICENSE` for the full license -- governing this code. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; use work.onewire_pkg.all; use work.onewire_cfg_pkg.all; ------------------------------------------------------------------------------- entity onewire_reset_tb is end onewire_reset_tb; ------------------------------------------------------------------------------- architecture tb of onewire_reset_tb is component onewire port ( onewire_in : in onewire_in_type; onewire_out : out onewire_out_type; onewire_bus_in : in onewire_bus_in_type; onewire_bus_out : out onewire_bus_out_type; clk : in std_logic); end component; -- component ports signal onewire_in : onewire_in_type; signal onewire_out : onewire_out_type; signal onewire_bus_in : onewire_bus_in_type; signal onewire_bus_out : onewire_bus_out_type; -- clock signal Clk : std_logic := '1'; begin -- tb -- component instantiation DUT : onewire port map ( onewire_in => onewire_in, onewire_out => onewire_out, onewire_bus_in => onewire_bus_in, onewire_bus_out => onewire_bus_out, clk => clk); -- clock generation Clk <= not Clk after 10 ns; -- 50MHz Clock -- waveform generation WaveGen_Proc : process begin onewire_in.d <= (others => '0'); onewire_in.re <= '0'; onewire_in.we <= '0'; onewire_in.reset_bus <= '0'; wait until Clk = '1'; wait until Clk = '1'; wait until Clk = '1'; onewire_in.reset_bus <= '1'; wait until Clk = '1'; onewire_in.reset_bus <= '0'; wait for 2.5 ms; end process WaveGen_Proc; WaveGen_onewire_device : process variable device_response : std_logic := '0'; begin onewire_bus_in.d <= '1'; wait until onewire_bus_out.en_driver = '1'; wait for 480 us; wait for 60 us; onewire_bus_in.d <= device_response; device_response := not device_response; -- Bus reset will fail every second -- time. wait for 240 us; end process WaveGen_onewire_device; end tb;
library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity add_393 is port ( result : out std_logic_vector(31 downto 0); in_a : in std_logic_vector(31 downto 0); in_b : in std_logic_vector(31 downto 0) ); end add_393; architecture augh of add_393 is signal carry_inA : std_logic_vector(33 downto 0); signal carry_inB : std_logic_vector(33 downto 0); signal carry_res : std_logic_vector(33 downto 0); begin -- To handle the CI input, the operation is '1' + CI -- If CI is not present, the operation is '1' + '0' carry_inA <= '0' & in_a & '1'; carry_inB <= '0' & in_b & '0'; -- Compute the result carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB)); -- Set the outputs result <= carry_res(32 downto 1); end architecture;
library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity add_393 is port ( result : out std_logic_vector(31 downto 0); in_a : in std_logic_vector(31 downto 0); in_b : in std_logic_vector(31 downto 0) ); end add_393; architecture augh of add_393 is signal carry_inA : std_logic_vector(33 downto 0); signal carry_inB : std_logic_vector(33 downto 0); signal carry_res : std_logic_vector(33 downto 0); begin -- To handle the CI input, the operation is '1' + CI -- If CI is not present, the operation is '1' + '0' carry_inA <= '0' & in_a & '1'; carry_inB <= '0' & in_b & '0'; -- Compute the result carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB)); -- Set the outputs result <= carry_res(32 downto 1); end architecture;
architecture RTL of FIFO is function func1 return integer is begin END function func1; function func1 return integer is begin END function func1; function func1 return integer is begin END function func1; procedure proc1 is begin End procedure proc1; begin end architecture RTL;
entity tb_revrng01 is end tb_revrng01; library ieee; use ieee.std_logic_1164.all; architecture behav of tb_revrng01 is signal a, z : std_logic_vector (7 downto 0); begin dut: entity work.revrng01 port map (a, z); process begin a <= x"a1"; wait for 1 ns; assert z = x"85" severity failure; wait; end process; end behav;
library verilog; use verilog.vl_types.all; entity dummy_hub is generic( sld_node_ir_width: integer := 16 ); port( jtag_tck : in vl_logic; jtag_tdi : in vl_logic; jtag_tms : in vl_logic; jtag_usr1 : in vl_logic; jtag_state_tlr : in vl_logic; jtag_state_rti : in vl_logic; jtag_state_drs : in vl_logic; jtag_state_cdr : in vl_logic; jtag_state_sdr : in vl_logic; jtag_state_e1dr : in vl_logic; jtag_state_pdr : in vl_logic; jtag_state_e2dr : in vl_logic; jtag_state_udr : in vl_logic; jtag_state_irs : in vl_logic; jtag_state_cir : in vl_logic; jtag_state_sir : in vl_logic; jtag_state_e1ir : in vl_logic; jtag_state_pir : in vl_logic; jtag_state_e2ir : in vl_logic; jtag_state_uir : in vl_logic; dummy_tdo : in vl_logic; virtual_ir_out : in vl_logic_vector; jtag_tdo : out vl_logic; dummy_tck : out vl_logic; dummy_tdi : out vl_logic; dummy_tms : out vl_logic; dummy_state_tlr : out vl_logic; dummy_state_rti : out vl_logic; dummy_state_drs : out vl_logic; dummy_state_cdr : out vl_logic; dummy_state_sdr : out vl_logic; dummy_state_e1dr: out vl_logic; dummy_state_pdr : out vl_logic; dummy_state_e2dr: out vl_logic; dummy_state_udr : out vl_logic; dummy_state_irs : out vl_logic; dummy_state_cir : out vl_logic; dummy_state_sir : out vl_logic; dummy_state_e1ir: out vl_logic; dummy_state_pir : out vl_logic; dummy_state_e2ir: out vl_logic; dummy_state_uir : out vl_logic; virtual_state_cdr: out vl_logic; virtual_state_sdr: out vl_logic; virtual_state_e1dr: out vl_logic; virtual_state_pdr: out vl_logic; virtual_state_e2dr: out vl_logic; virtual_state_udr: out vl_logic; virtual_state_cir: out vl_logic; virtual_state_uir: out vl_logic; virtual_ir_in : out vl_logic_vector ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of sld_node_ir_width : constant is 1; end dummy_hub;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity CU is Port ( OP : in STD_LOGIC_VECTOR (1 downto 0); OP3 : in STD_LOGIC_VECTOR (5 downto 0); icc : in STD_LOGIC_VECTOR (3 downto 0); Cond : in STD_LOGIC_VECTOR (3 downto 0); wren : out STD_LOGIC; PCsource : out STD_LOGIC_VECTOR (1 downto 0); ALUOP : out STD_LOGIC_VECTOR (5 downto 0); RdEnMem : out STD_LOGIC; WrEnMem : out STD_LOGIC; RFsource : out STD_LOGIC_VECTOR (1 downto 0); RFdest : out STD_LOGIC ); end CU; architecture Behavioral of CU is signal calcicc : std_logic := '0'; begin process(op, op3, icc, cond) begin --valores for defecto PCsource <= "11"; RFsource <= "01"; wren <= '0'; RdEnMem <= '0'; WrEnMem <= '0'; RFdest <= '0'; if(op = "10") then --formato3 wren <= '1'; case op3 is when "000000" => --Add aluop <= "000000"; --0 when "000100" => --Sub aluop <= "000001"; --1 when "000001" => -- And aluop <= "000010"; --2 when "000101" => --Andn aluop <= "000011"; --3 when "000010" => --or aluop <= "000100"; --4 when "000110" => --orn aluop <= "000101"; --5 when "000011" => --xor aluop <= "000110"; --6 when "000111" => --xnor aluop <= "000111"; --7 when "010100" => --SUBcc aluop <= "001000"; --8 when "001100" => --SUBx aluop <= "001001"; --9 when "011100" => --SUBxcc aluop <= "001010"; --10 when "010001" => --ANDcc aluop <= "001011"; --11 when "010101" => --ANDNcc aluop <= "001100"; --12 when "010010" => --ORcc aluop <= "001101"; --13 when "010110" => --ORNcc aluop <= "001110"; --14 when "010011" => --XORcc aluop <= "001111"; --15 when "010111" => --XNORcc aluop <= "010000"; --16 when "001000" => --ADDx aluop <= "010001"; --17 when "011000" => --ADDxcc aluop <= "010010"; --18 when "010000" => --ADDcc aluop <= "010011"; --19 when "100101" => AluOp <= "100101";--SLL Shift Left Logical 37 when "100110" => AluOp <= "100110";--SRL Shift Right Logical 38 when "111100" => AluOp <= "111100";--Save 60 when "111101" => AluOp <= "111101";--RESTORE 61 when "111000" => ALUOP <= "010100"; RFsource <= "10";--selecciona PC como datatoreg PCsource <= "00";--operacion de la alu RFdest <= '0';--seleccion nRD when others => aluop <= (others=>'1'); --error end case; elsif (op = "11") then case OP3 is when "000000" =>--load word ALUOP <= "010101"; --21 RdEnMem <= '1';--activa lectura en memoria WrEnMem <= '0'; RFsource <= "00";--selecciona dato de memoria como datatoreg wren <= '1'; when "000100" =>--store word ALUOP <= "010110"; --22 WrEnMem <= '1';--activa escritura en memoria RdEnMem <= '0'; when others => ALUOP <= "000000"; end case; elsif(OP = "01") then ALUOP <= "000000"; wren <='0'; RFsource <= "10";--selecciona PC como datatoreg RFdest <= '1';--selecciona no7 como registro de destino PCsource <= "01";--selecciona disp30 como source del PC WrEnMem <= '0'; RdEnMem <= '1'; elsif(OP = "00") then --NZCV wren <= '0'; ALUOP <= "000000"; case cond is when "1000" => PCsource <= "10";--BA escoge disp22 como source when "1001" =>--BNE calcicc <= not icc(2); if(calcicc = '1') then PCsource <= "10"; end if; when "0001" =>--BE calcicc <= icc(2); if(calcicc='1') then PCsource <= "10"; end if; when "1010" =>--BG calcicc <= not (icc(2) or (icc(3) xor icc(0))); if(calcicc = '1') then PCsource <= "10"; end if; when "0010" =>--BLE calcicc <= icc(2) or (icc(3) xor icc(0)); if(calcicc='1') then PCsource <= "10"; end if; when "1011" =>--BGE calcicc <= not(icc(3) xor icc(0)); if(calcicc='1') then PCsource <= "10"; end if; when "0011" =>--BL calcicc <= (icc(3) xor icc(0)); if(calcicc='1') then PCsource <= "10"; end if; when "1100" =>--BGU calcicc <= not(icc(1) or icc(2)); if(calcicc='1') then PCsource <= "10"; end if; when "0100" =>--BLEU calcicc <= (icc(1) or icc(2)); if(calcicc='1') then PCsource <= "10"; end if; when "1101" =>--BCC calcicc <= not icc(1); if(calcicc='1') then PCsource <= "10"; end if; when "0101" =>--BCS calcicc <= icc(1); if(calcicc='1') then PCsource <= "10"; end if; when "1110" =>--BPOS calcicc <= not icc(3); if(calcicc='1') then PCsource <= "10"; end if; when "0110" =>--BNEG calcicc <= icc(3); if(calcicc='1') then PCsource <= "10"; end if; when "1111" =>--BVC calcicc <= not icc(0); if(calcicc='1') then PCsource <= "10"; end if; when "0111" =>--BVS calcicc <= icc(0); if(calcicc='1') then PCsource <= "10"; end if; when others => PCsource <="00"; end case; end if; end process; end Behavioral;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 12:12:44 08/17/2014 -- Design Name: -- Module Name: vga_tx_display - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity vga_tx_display is Port ( clk : in STD_LOGIC; E_TX_CLK : in STD_LOGIC; E_TXD : in STD_LOGIC_VECTOR (3 downto 0); E_TX_EN : in std_logic; Char_DI : out STD_LOGIC_VECTOR (7 downto 0); Char_WE : out STD_LOGIC; reset : in std_logic); end vga_tx_display; architecture Behavioral of vga_tx_display is type state_type is (IDLE, START_RISING_EDGE, KEEP_RISING_EDGE, START_FALLING_EDGE, WAIT_FOR_DOWN); signal state, next_state : state_type; signal latched_data : std_logic_vector(3 downto 0) := (others=>'0'); begin process (E_TX_CLK) begin if rising_edge(E_TX_CLK) then if(E_TX_EN = '1') then latched_data <= E_TXD(3 downto 0); end if; end if; end process; SYNC_PROC: process (clk) begin if rising_edge(clk) then if (reset = '1') then state <= IDLE; else state <= next_state; end if; end if; end process; OUTPUT_DECODE: process (state) begin if state = IDLE then Char_DI <= (others=>'0'); Char_WE <= '0'; elsif state = START_RISING_EDGE then Char_DI <= "0011" & latched_data; Char_WE <= '1'; elsif state = START_FALLING_EDGE then Char_DI <= (others=>'0'); Char_WE <= '0'; else Char_DI <= (others=>'0'); Char_WE <= '0'; end if; end process; NEXT_STATE_DECODE: process (state, E_TX_CLK) begin next_state <= state; case (state) is when IDLE => if E_TX_EN = '1' and E_TX_CLK = '1' then next_state <= START_RISING_EDGE; end if; when START_RISING_EDGE => next_state <= START_FALLING_EDGE; when START_FALLING_EDGE => next_state <= WAIT_FOR_DOWN; when WAIT_FOR_DOWN => if E_TX_CLK = '0' then next_state <= IDLE; end if; when others => next_state <= IDLE; end case; end process; end Behavioral;
entity FIFO is generic ( G_GEN1 : integer; G_GEN2 : std_logic; G_GENA : t_user2; G_GEN3 : std_logic_vector(3 downto 0); G_GEN4 : signed(15 downto 0); G_GEN5 : unsigned(7 downto 0); G_GEN6 : std_ulogic; G_GEN7 : t_user1 ); end entity FIFO; -- Violation below entity FIFO is generic ( G_GEN1 : integer; G_GEN2 : std_logic; G_GENA : T_USER2; G_GEN3 : std_logic_vector(3 downto 0); G_GEN4 : signed(15 downto 0); G_GEN5 : unsigned(7 downto 0); G_GEN6 : std_ulogic; G_GEN7 : T_USER1 ); end entity FIFO;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_13_fg_13_25.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- entity nand3 is generic ( Tpd : delay_length ); port ( a, b, c : in bit; y : out bit ); end entity nand3; architecture basic of nand3 is begin y <= not (a and b and c) after Tpd; end architecture basic; library project_lib; library stimulus; use stimulus.stimulus_generators.all; entity misc_logic is end entity misc_logic; -- code from book architecture gate_level of misc_logic is component nand3 is generic ( Tpd : delay_length ); port ( a, b, c : in bit; y : out bit ); end component nand3; for all : nand3 use entity project_lib.nand3(basic); -- . . . -- not in book signal sig1, sig2, sig3, out_sig : bit; signal test_vector : bit_vector(1 to 3); -- end not in book begin gate1 : component nand3 generic map ( Tpd => 2 ns ) port map ( a => sig1, b => sig2, c => sig3, y => out_sig ); -- . . . -- not in book all_possible_values(test_vector, 10 ns); (sig1, sig2, sig3) <= test_vector; -- end not in book end architecture gate_level; -- end code from book
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_13_fg_13_25.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- entity nand3 is generic ( Tpd : delay_length ); port ( a, b, c : in bit; y : out bit ); end entity nand3; architecture basic of nand3 is begin y <= not (a and b and c) after Tpd; end architecture basic; library project_lib; library stimulus; use stimulus.stimulus_generators.all; entity misc_logic is end entity misc_logic; -- code from book architecture gate_level of misc_logic is component nand3 is generic ( Tpd : delay_length ); port ( a, b, c : in bit; y : out bit ); end component nand3; for all : nand3 use entity project_lib.nand3(basic); -- . . . -- not in book signal sig1, sig2, sig3, out_sig : bit; signal test_vector : bit_vector(1 to 3); -- end not in book begin gate1 : component nand3 generic map ( Tpd => 2 ns ) port map ( a => sig1, b => sig2, c => sig3, y => out_sig ); -- . . . -- not in book all_possible_values(test_vector, 10 ns); (sig1, sig2, sig3) <= test_vector; -- end not in book end architecture gate_level; -- end code from book
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_13_fg_13_25.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- entity nand3 is generic ( Tpd : delay_length ); port ( a, b, c : in bit; y : out bit ); end entity nand3; architecture basic of nand3 is begin y <= not (a and b and c) after Tpd; end architecture basic; library project_lib; library stimulus; use stimulus.stimulus_generators.all; entity misc_logic is end entity misc_logic; -- code from book architecture gate_level of misc_logic is component nand3 is generic ( Tpd : delay_length ); port ( a, b, c : in bit; y : out bit ); end component nand3; for all : nand3 use entity project_lib.nand3(basic); -- . . . -- not in book signal sig1, sig2, sig3, out_sig : bit; signal test_vector : bit_vector(1 to 3); -- end not in book begin gate1 : component nand3 generic map ( Tpd => 2 ns ) port map ( a => sig1, b => sig2, c => sig3, y => out_sig ); -- . . . -- not in book all_possible_values(test_vector, 10 ns); (sig1, sig2, sig3) <= test_vector; -- end not in book end architecture gate_level; -- end code from book
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; use work.HammingPack16.all; use work.PhoenixPackage.all; entity HAM_ENC is port ( data_in : in regflit; -- data input data_out : out reghamm -- data output ); end HAM_ENC; architecture HAM_ENC of HAM_ENC is signal P : Std_logic_vector(5 downto 1); --Hamming bits begin P(1) <= xor_reduce(data_in and MaskP1); P(2) <= xor_reduce(data_in and MaskP2); P(3) <= xor_reduce(data_in and MaskP4); P(4) <= xor_reduce(data_in and MaskP8); P(5) <= xor_reduce(data_in and MaskP16); data_out <= P & xor_reduce(P & data_in); end HAM_ENC;
------------------------------------------------------------------------------- -- axi_cdma_sg_cntlr ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_cdma_sg_cntlr.vhd -- Description: This entity is reset module entity for the AXI DMA core. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library lib_pkg_v1_0; use lib_pkg_v1_0.lib_pkg.all; library axi_cdma_v4_1; use axi_cdma_v4_1.axi_cdma_pulse_gen; ------------------------------------------------------------------------------- entity axi_cdma_sg_cntlr is Generic ( C_SG_ADDR_WIDTH : integer := 32; C_SG_FETCH_DWIDTH : integer := 32; C_SG_PTR_UPDATE_DWIDTH : integer := 32; C_SG_STS_UPDATE_DWIDTH : integer := 33; C_DM_CMD_WIDTH : integer := 72; C_DM_DATA_WIDTH : integer := 32; C_DM_MM2S_STATUS_WIDTH : integer := 8; C_DM_S2MM_STATUS_WIDTH : integer := 8; C_FAMILY : String := "virtex7" ); port ( -- Clock Input axi_aclk : in std_logic ; -- Reset Input (active high) axi_reset : in std_logic ; -- Halt request from the Reset module rst2sgcntl_halt : in std_logic ; -- Halt complete status to the Reset module sgcntl2rst_halt_cmplt : out std_logic ; -- SG Queue Flush Request sgcntlr2sg_desc_flush : out std_logic ; -- Register Module SG Mode Control reg2sgcntl_sg_mode : in std_logic ; -- MM2S Type of Burst, 1 is increment, 0 is fixed burst_type_read : in std_logic; -- S2MM Type of Burst, 1 is increment, 0 is fixed burst_type_write : in std_logic; -- Register Module Tail pointer updated flag reg2sgcntl_tailpntr_updated : in std_logic ; -- Register Module Current Desciptor pointer updated flag reg2sgcntl_currdesc_updated : in std_logic ; -- Run/Stop Control to SG sgcntlr2sg_run_stop : out std_logic ; -- Idle bit set to Register Module Status Register sgcntl2reg_idle_set : out std_logic ; -- Idle bit clear to Register Module Status Register sgcntl2reg_idle_clr : out std_logic ; -- SOF control to SG sgcntl2sg_pkt_sof : out std_logic ; -- EOF control to SG sgcntl2sg_pkt_eof : out std_logic ; -- Interrupt on complete status bit set from SG sg2sgcntl_ioc_irq_set : in std_logic ; -- Delay Interrupt status bit set from SG sg2sgcntl_dly_irq_set : in std_logic ; -- Interrupt on complete status bit set to Register Module sgcntl2reg_ioc_irq_set : out std_logic ; -- Delay Interrupt status bit set to Register Module sgcntl2reg_dly_irq_set : out std_logic ; -- Descriptor Fetch Stream Interface from SG sgcntl2sg_ftch_tready : out std_logic ; -- Axi4-Stream sg2sgcntlr_ftch_tvalid : in std_logic ; -- Axi4-Stream sg2sgcntlr_ftch_tvalid_new : in std_logic ; -- Axi4-Stream sg2sgcntlr_ftch_tdata : in std_logic_vector(C_SG_FETCH_DWIDTH-1 downto 0) ; -- Axi4-Stream sg2sgcntlr_ftch_tdata_new : in std_logic_vector(127 downto 0) ; -- Axi4-Stream sg2sgcntlr_ftch_tlast : in std_logic ; -- Axi4-Stream sig_sg2sgcntlr_ftch_desc_available : in std_logic; -- Descriptor Pointer Update Stream to SG sg2sgcntlr_updptr_tready : in std_logic ; -- Axi4-Stream sgcntl2sg_updptr_tvalid : out std_logic ; -- Axi4-Stream sgcntl2sg_updptr_tdata : out std_logic_vector(C_SG_PTR_UPDATE_DWIDTH-1 downto 0) ;-- Axi4-Stream sgcntl2sg_updptr_tlast : out std_logic ; -- Axi4-Stream -- Descriptor Status Update Stream to SG sg2sgcntlr_updsts_tready : in std_logic ; -- Axi4-Stream sgcntl2sg_updsts_tvalid : out std_logic ; -- Axi4-Stream sgcntl2sg_updsts_tdata : out std_logic_vector(C_SG_STS_UPDATE_DWIDTH-1 downto 0) ;-- Axi4-Stream sgcntl2sg_updsts_tlast : out std_logic ; -- Axi4-Stream -- Descriptor Fetch Idle status from SG sg2sgcntlr_ftch_idle : in std_logic ; -- Descriptor Fetch error early from SG sg2sgcntlr_ftch_err_early : in std_logic ; -- Descriptor Fetch stale descriptor error from SG sg2sgcntlr_ftch_stale_desc : in std_logic ; -- Descriptor Fetch error from SG sg2sgcntlr_ftch_error : in std_logic ; -- Descriptor update Idle status from SG sg2sgcntlr_updt_idle : in std_logic ; -- Descriptor interrupt on complete bit set from SG sg2sgcntlr_updt_ioc_irq_set : in std_logic ; -- Descriptor Update error from SG sg2sgcntlr_updt_error : in std_logic ; -- Echo of Main DataMover internal error from SG sg2sgcntlr_dma_interr_set : in std_logic ; -- Echo of Main DataMover Slave error from SG sg2sgcntlr_dma_slverr_set : in std_logic ; -- Echo of Main DataMover Decode error from SG sg2sgcntlr_dma_decerr_set : in std_logic ; -- Echo of Main DataMover internal error to the Register Module sgcntlr2reg_dma_interr_set : out std_logic ; -- Echo of Main DataMover Slave error to the Register Module sgcntlr2reg_dma_slverr_set : out std_logic ; -- Echo of Main DataMover Decode error to the Register Module sgcntlr2reg_dma_decerr_set : out std_logic ; -- Current Descriptor write control to Register Module sgcntlr2reg_new_curdesc_wren : out std_logic ; -- Current Descriptor to Register Module sgcntlr2reg_new_curdesc : out std_logic_vector(C_SG_ADDR_WIDTH-1 downto 0) ; -- DataMover MM2S Command Interface Ports (AXI Stream) mm2s2sgcntl_cmd_tready : in std_logic ; -- DM MM2S CMD IF sgcntl2mm2s_cmd_tvalid : out std_logic ; -- DM MM2S CMD IF sgcntl2mm2s_cmd_tdata : out std_logic_vector(C_DM_CMD_WIDTH-1 downto 0); -- DM MM2S CMD IF -- DataMover MM2S Status Interface Ports (AXI Stream) sgcntl2mm2s_sts_tready : out std_logic ; -- DM MM2S Status IF mm2s2sgcntl_sts_tvalid : in std_logic ; -- DM MM2S Status IF mm2s2sgcntl_sts_tdata : in std_logic_vector(C_DM_MM2S_STATUS_WIDTH-1 downto 0); -- DM MM2S Status IF mm2s2sgcntl_sts_tstrb : in std_logic_vector((C_DM_MM2S_STATUS_WIDTH/8)-1 downto 0); -- DM MM2S Status IF -- DataMover MM2S error discrete mm2s2sgcntl_err : in std_logic ; -- DataMover MM2S Halt request input sgcntl2mm2s_halt : Out std_logic ; -- DataMover MM2S Halt complete flag mm2s2sgcntl_halt_cmplt : In std_logic ; -- DataMover S2MM Command Interface Ports (AXI Stream) s2mm2sgcntl_cmd_tready : in std_logic ; -- DM S2MM CMD IF sgcntl2s2mm_cmd_tvalid : out std_logic ; -- DM S2MM CMD IF sgcntl2s2mm_cmd_tdata : out std_logic_vector(C_DM_CMD_WIDTH-1 downto 0); -- DM S2MM CMD IF -- DataMover S2MM Status Interface Ports (AXI Stream) sgcntl2s2mm_sts_tready : out std_logic ; -- DM S2MM Status IF s2mm2sgcntl_sts_tvalid : in std_logic ; -- DM S2MM Status IF s2mm2sgcntl_sts_tdata : in std_logic_vector(C_DM_S2MM_STATUS_WIDTH-1 downto 0); -- DM S2MM Status IF s2mm2sgcntl_sts_tstrb : in std_logic_vector((C_DM_S2MM_STATUS_WIDTH/8)-1 downto 0);-- DM S2MM Status IF -- DataMover S2MM error discrete s2mm2sgcntl_err : in std_logic ; -- DataMover S2MM Halt request input sgcntl2s2mm_halt : Out std_logic ; -- DataMover S2MM Halt complete flag s2mm2sgcntl_halt_cmplt : In std_logic ); end axi_cdma_sg_cntlr; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_cdma_sg_cntlr is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_calc_offset_bits -- -- Function Description: -- Calculates the width of the destination address offset bits -- needed for populating the MM2S Command DSA field. -- ------------------------------------------------------------------- function funct_calc_offset_bits (data_width : integer) return integer is Variable lvar_bits_needed : Integer := 0; begin case data_width is when 32 => lvar_bits_needed := 2; when 64 => lvar_bits_needed := 3; when 128 => lvar_bits_needed := 4; when others => -- 256 bits lvar_bits_needed := 5; end case; Return (lvar_bits_needed); end function funct_calc_offset_bits; attribute mark_debug : string; ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- Constant DM_CMD_PEND_WIDTH : integer := 5; -- bits Constant DM_CMD_PEND_ONE : unsigned(DM_CMD_PEND_WIDTH-1 downto 0) := TO_UNSIGNED(1,DM_CMD_PEND_WIDTH); Constant DM_CMD_PEND_ZERO : unsigned(DM_CMD_PEND_WIDTH-1 downto 0) := TO_UNSIGNED(0,DM_CMD_PEND_WIDTH); Constant NO_SYNCHRONIZERS : integer := 0; Constant POSITIVE_EDGE_TRIGGER : integer := 1; Constant NEGATIVE_EDGE_TRIGGER : integer := 0; Constant TWO_CLKS : integer := 2; Constant ONE_CLK : integer := 1; Constant CMD_TAG_WIDTH : integer := 4; Constant CMD_DSA_WIDTH : integer := 6; Constant DSA_ADDR_OFFSET_WIDTH : integer := funct_calc_offset_bits(C_DM_DATA_WIDTH); Constant CMD_RSVD : std_logic_vector(3 downto 0) := (others => '0'); Constant CMD_DSA_ZEROED : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0'); Constant STS_TAG_MS_INDEX : integer := CMD_TAG_WIDTH-1; Constant STS_INTERR_INDEX : integer := STS_TAG_MS_INDEX+1; Constant STS_DECERR_INDEX : integer := STS_INTERR_INDEX+1; Constant STS_SLVERR_INDEX : integer := STS_DECERR_INDEX+1; Constant STS_OK_INDEX : integer := STS_SLVERR_INDEX+1; Constant DM_ADDR_FIELD_WIDTH : integer := 32; Constant DM_BTT_FIELD_WIDTH : integer := 23; Constant BTT_ZERO : std_logic_vector(DM_BTT_FIELD_WIDTH-1 downto 0) := (others => '0'); Constant TAG_CNT_ONE : unsigned(CMD_TAG_WIDTH-1 downto 0) := TO_UNSIGNED(1,CMD_TAG_WIDTH); Constant DESCR_DBEAT_CNT_WIDTH : integer := 3; -- bits Constant DESCR_DBEAT_CNT_ONE : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(1,DESCR_DBEAT_CNT_WIDTH); -- Descriptor Load databeat positions Constant CDA_LS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(0,DESCR_DBEAT_CNT_WIDTH); Constant CDA_MS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(1,DESCR_DBEAT_CNT_WIDTH); -- Constant SA_LS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(2,DESCR_DBEAT_CNT_WIDTH); Constant SA_LS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(1,DESCR_DBEAT_CNT_WIDTH); Constant SA_MS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(3,DESCR_DBEAT_CNT_WIDTH); -- Constant DA_LS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(4,DESCR_DBEAT_CNT_WIDTH); Constant DA_LS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(2,DESCR_DBEAT_CNT_WIDTH); Constant DA_MS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(5,DESCR_DBEAT_CNT_WIDTH); -- Constant BTT : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(6,DESCR_DBEAT_CNT_WIDTH); Constant BTT : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(3,DESCR_DBEAT_CNT_WIDTH); Constant STATUS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(7,DESCR_DBEAT_CNT_WIDTH); -- Status update word reserved field Constant STATUS_USED_WIDTH : integer := 1 -- Update IOC bit + 1 -- Cmplt bit + 1 -- DMADecErr bit + 1 -- DMASlvErr bit + 1 ; -- DMAIntErr bit Constant STATUS_RSVD_WIDTH : integer := C_SG_STS_UPDATE_DWIDTH - STATUS_USED_WIDTH; Constant STATUS_RSVD : std_logic_vector(STATUS_RSVD_WIDTH-1 downto 0) := (others => '0'); Constant FTCH_UPDT_CNTR_WIDTH : integer := 5; -- 5 bits wide Constant FTCH_UPDT_ZERO : unsigned(FTCH_UPDT_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(0, FTCH_UPDT_CNTR_WIDTH); Constant FTCH_UPDT_ONE : unsigned(FTCH_UPDT_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(1, FTCH_UPDT_CNTR_WIDTH); Constant UPDT_FLTR_WIDTH : integer := 8; -- 8 clocks Constant UPDT_FLTR_CNTR_WIDTH : integer := 4; -- 4 bits wide Constant UPDT_FLTR_CNTR_LD_VALUE : unsigned(UPDT_FLTR_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(UPDT_FLTR_WIDTH, UPDT_FLTR_CNTR_WIDTH); Constant UPDT_FLTR_CNTR_ZERO : unsigned(UPDT_FLTR_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(0, UPDT_FLTR_CNTR_WIDTH); Constant UPDT_FLTR_CNTR_ONE : unsigned(UPDT_FLTR_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(1, UPDT_FLTR_CNTR_WIDTH); Constant FETCH_LIMIT : integer := 4; -- limit of allowed prefetches for DM Cmds Constant FTCH_LIMITER_CNTR_WIDTH : integer := 4; -- 4 bits wide (16 values) Constant FTCH_LIMIT_VALUE : unsigned(UPDT_FLTR_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(FETCH_LIMIT, FTCH_LIMITER_CNTR_WIDTH); Constant FTCH_LIMITER_CNTR_ZERO : unsigned(UPDT_FLTR_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(0, FTCH_LIMITER_CNTR_WIDTH); Constant FTCH_LIMITER_CNTR_ONE : unsigned(UPDT_FLTR_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(1, FTCH_LIMITER_CNTR_WIDTH); ------------------------------------------------------------------------------- -- Type Declarations ------------------------------------------------------------------------------- -- Define the Fetch State Machine type and states type sg_fetch_sm_type is (FTCH_IDLE , CHK_SG_DM_RDY , LOAD_DESC , XFER_DONE ); -- Define the Status State Machine type and states type sg_status_sm_type is (STS_IDLE , GET_MM2S_STATUS , GET_S2MM_STATUS , DO_UPDATE ); -- Update Stream arbiter type type update_arb_type is (ARB_IDLE , ARB_GRANT_FETCH , ARB_GRANT_STATUS ); -- shutdown sequencer type type shtdwn_type is (SHTDWN_IDLE , HALT_FTCH_DM , WAIT_FTCH_IDLE , WAIT_FTCH_UPDATE , WAIT_DM_HALT_CMPLT , WAIT_STS_IDLE , WAIT_STS_UPDATE , WAIT_SG_UPDATE , SHTDWN_CMPLT ); ------------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------------- -- Fetch State machine signal sig_ftch_sm_state : sg_fetch_sm_type := FTCH_IDLE; signal sig_ftch_sm_state_ns : sg_fetch_sm_type := FTCH_IDLE; signal sig_ftch_sm_set_getdesc : std_logic := '0'; signal sig_ftch_sm_set_getdesc_ns : std_logic := '0'; signal sig_ftch_sm_ld_dm_cmd : std_logic := '0'; signal sig_ftch_sm_ld_dm_cmd_ns : std_logic := '0'; signal sig_ftch_sm_push_updt : std_logic := '0'; signal sig_ftch_sm_push_updt_ns : std_logic := '0'; signal sig_ftch_sm_done : std_logic := '0'; signal sig_ftch_sm_done_ns : std_logic := '0'; -- Status State machine signal sig_sts_sm_state : sg_status_sm_type := STS_IDLE; signal sig_sts_sm_state_ns : sg_status_sm_type := STS_IDLE; signal sig_sts_sm_pop_mm2s_sts : std_logic := '0'; signal sig_sts_sm_pop_mm2s_sts_ns : std_logic := '0'; signal sig_sts_sm_pop_s2mm_sts : std_logic := '0'; signal sig_sts_sm_pop_s2mm_sts_ns : std_logic := '0'; signal sig_sts_sm_push_updt : std_logic := '0'; signal sig_sts_sm_push_updt_ns : std_logic := '0'; -- High level control signal sig_sg_active : std_logic := '1'; signal sig_sg_run : std_logic := '0'; attribute mark_debug of sig_sg_run : signal is "true"; signal sig_idle_clr : std_logic := '0'; signal sig_idle_set : std_logic := '0'; attribute mark_debug of sig_idle_set : signal is "true"; signal sig_dm_cmd_pend_cntr : unsigned(DM_CMD_PEND_WIDTH-1 downto 0) := (others => '0'); signal sig_inc_cmd_pending : std_logic := '0'; signal sig_decr_cmd_pending : std_logic := '0'; signal sig_dm_cmd_pend_eq0 : std_logic := '0'; signal sig_composite_idle : std_logic := '0'; -- Soft shutdown support signal sig_halt_request : std_logic := '0'; signal sig_halt_cmplt_reg : std_logic := '0'; -- DataMover Cmd/Status IF signal sig_cmd_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_tag_cntr : unsigned(CMD_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mm2s_dsa_offset : std_logic_vector(DSA_ADDR_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_mm2s_dsa_field : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0'); signal sig_btt_dm_slice : std_logic_vector(DM_BTT_FIELD_WIDTH-1 downto 0) := (others => '0'); signal sig_mm2s_s2mm_cmd_rdy : std_logic := '0'; signal sig_mm2s_cmd : std_logic_vector(C_DM_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_mm2s_cmd_valid : std_logic := '0'; attribute mark_debug of sig_mm2s_cmd_valid : signal is "true"; attribute mark_debug of sig_mm2s_cmd : signal is "true"; signal sig_mm2s_cmd_ready : std_logic := '0'; signal sig_mm2s_sts_tready : std_logic ; signal sig_mm2s_sts_tvalid : std_logic ; signal sig_mm2s_sts_tdata : std_logic_vector(C_DM_MM2S_STATUS_WIDTH-1 downto 0); signal sig_s2mm_cmd : std_logic_vector(C_DM_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_s2mm_cmd_valid : std_logic := '0'; attribute mark_debug of sig_s2mm_cmd_valid : signal is "true"; attribute mark_debug of sig_s2mm_cmd : signal is "true"; signal sig_s2mm_cmd_ready : std_logic := '0'; signal sig_s2mm_sts_tready : std_logic ; signal sig_s2mm_sts_tvalid : std_logic ; signal sig_s2mm_sts_tdata : std_logic_vector(C_DM_MM2S_STATUS_WIDTH-1 downto 0); -- DataMover Status Scoring and Update signal sig_mm2s_status_reg : std_logic_vector(C_DM_MM2S_STATUS_WIDTH-1 downto 0) := (others => '0'); signal sig_s2mm_status_reg : std_logic_vector(C_DM_MM2S_STATUS_WIDTH-1 downto 0) := (others => '0'); signal sig_mm2s_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mm2s_slverr : std_logic := '0'; signal sig_mm2s_decerr : std_logic := '0'; signal sig_mm2s_interr : std_logic := '0'; attribute mark_debug of sig_mm2s_slverr : signal is "true"; attribute mark_debug of sig_mm2s_decerr : signal is "true"; attribute mark_debug of sig_mm2s_interr : signal is "true"; signal sig_s2mm_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_s2mm_slverr : std_logic := '0'; signal sig_s2mm_decerr : std_logic := '0'; signal sig_s2mm_interr : std_logic := '0'; attribute mark_debug of sig_s2mm_slverr : signal is "true"; attribute mark_debug of sig_s2mm_decerr : signal is "true"; attribute mark_debug of sig_s2mm_interr : signal is "true"; signal sig_mm2s2cntl_err : std_logic := '0'; signal sig_s2mm2cntl_err : std_logic := '0'; signal sig_composite_interr : std_logic := '0'; signal sig_composite_slverr : std_logic := '0'; signal sig_composite_decerr : std_logic := '0'; signal sig_tag_error : std_logic := '0'; -- SG Update Ready signals signal sig_fetch_updptr_tready : std_logic := '0'; signal sig_status_updsts_tready : std_logic := '0'; -- Descriptor Fetch support signal sig_fetch_dbeat_cnt : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := (others => '0'); signal sig_good_fetch_dbeat : std_logic := '0'; signal sig_fetch_go : std_logic := '0'; signal sig_fetch_done : std_logic := '0'; signal sig_fetch_last : std_logic := '0'; -- Descriptor fetch holding registers signal sig_curr_desc_pntr_reg : std_logic_vector(C_SG_FETCH_DWIDTH-1 downto 0) := (others => '0'); signal sig_src_addr_reg : std_logic_vector(C_SG_FETCH_DWIDTH-1 downto 0) := (others => '0'); signal sig_dest_addr_reg : std_logic_vector(C_SG_FETCH_DWIDTH-1 downto 0) := (others => '0'); signal sig_btt_reg : std_logic_vector(C_SG_FETCH_DWIDTH-1 downto 0) := (others => '0'); -- Descriptor fetch SG update support signal sig_ld_fetch_update_reg : std_logic := '0'; signal sig_pop_fetch_update_reg : std_logic := '0'; signal sig_fetch_update_reg : std_logic_vector(C_SG_PTR_UPDATE_DWIDTH-1 downto 0) := (others => '0'); signal sig_fetch_update_full_1 : std_logic := '0'; signal sig_fetch_update_empty_1 : std_logic := '0'; signal sig_fetch_update_full : std_logic := '0'; signal sig_fetch_update_empty : std_logic := '0'; signal sig_fetch_update_last : std_logic := '0'; -- Status SG Update support signal sig_ld_dm_status_reg : std_logic := '0'; signal sig_pop_dm_status_reg : std_logic := '0'; signal sig_dm_status_reg : std_logic_vector(C_SG_STS_UPDATE_DWIDTH-1 downto 0) := (others => '0'); signal sig_dm_status_full : std_logic := '0'; signal sig_dm_status_empty : std_logic := '0'; -- Controlled Shutdown support Signal sig_shtdwn_sm_state : shtdwn_type := SHTDWN_IDLE; Signal sig_shtdwn_sm_state_ns : shtdwn_type := SHTDWN_IDLE; signal sig_shtdwn_sm_flush_sg : std_logic := '0'; signal sig_shtdwn_sm_flush_sg_ns : std_logic := '0'; signal sig_shtdwn_sm_set_ftch_halt : std_logic := '0'; signal sig_shtdwn_sm_set_ftch_halt_ns : std_logic := '0'; signal sig_shtdwn_sm_set_dm_halt : std_logic := '0'; signal sig_shtdwn_sm_set_dm_halt_ns : std_logic := '0'; signal sig_shtdwn_sm_set_sts_halt : std_logic := '0'; signal sig_shtdwn_sm_set_sts_halt_ns : std_logic := '0'; signal sig_shtdwn_sm_set_cmplt : std_logic := '0'; signal sig_shtdwn_sm_set_cmplt_ns : std_logic := '0'; signal sig_do_shutdown : std_logic := '0'; signal sig_sg_error : std_logic := '0'; signal sig_halt_fetch : std_logic := '0'; signal sig_halt_status : std_logic := '0'; signal sig_halt_dm : std_logic := '0'; signal sig_dmhalt_cmplt : std_logic := '0'; signal sig_flush_sg : std_logic := '0'; signal sig_ftchsm_idle : std_logic := '0'; signal sig_stssm_idle : std_logic := '0'; -- SG Idle detection enhancement signal sig_ftch_updt_cntr : unsigned(FTCH_UPDT_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_incr_ftch_updt_cntr : std_logic := '0'; signal sig_decr_ftch_updt_cntr : std_logic := '0'; signal sig_ftch_updt_cntr_eq0 : std_logic := '0'; signal sig_final_updt_idle : std_logic := '0'; signal sig_update_idle_rising : std_logic := '0'; signal sig_shutdown_idle : std_logic := '0'; signal sig_shutdown_idle_rising : std_logic := '0'; signal sig_updt_filter_cntr : unsigned(UPDT_FLTR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_updt_filter_cntr_eq0 : std_logic := '0'; signal sig_ld_updt_filter_cntr : std_logic := '0'; -- SG Fetch Limiter (lock up avoidance) signal sig_ftch_limit_cntr : unsigned(FTCH_LIMITER_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_incr_ftch_limit_cntr : std_logic := '0'; signal sig_decr_ftch_limit_cntr : std_logic := '0'; signal sig_ftch_limit_cntr_eq0 : std_logic := '0'; signal sig_ftch_limit_cntr_eqlimit : std_logic := '0'; signal type_of_burst_write : std_logic; signal type_of_burst : std_logic; signal ZERO_WORD : std_logic_vector (31 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin ------------------------------------------------------------------------------- -- SG Run/Stop ------------------------------------------------------------------------------- sgcntlr2sg_run_stop <= sig_sg_run ; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SG_RUN_FLOP -- -- Process Description: -- Implements the flop for the SG Run control. The Run/Stop -- control is set when SG Mode is enabled and the Current -- Descriptor Register is updated by SW (in the Reg Module). -- ------------------------------------------------------------- IMP_SG_RUN_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or reg2sgcntl_sg_mode = '0') then sig_sg_run <= '0'; elsif (reg2sgcntl_currdesc_updated = '1') then sig_sg_run <= '1'; else null; -- Hold Current State end if; end if; end process IMP_SG_RUN_FLOP; ------------------------------------------------------------------------------- -- SG Xfer "Really" Done Detection ------------------------------------------------------------------------------- sig_idle_set <= (not(sig_do_shutdown) and -- not in a shutdown sequence sig_update_idle_rising and -- update engine done sig_ftch_updt_cntr_eq0 and -- the last update queued sig_updt_filter_cntr_eq0 and sg2sgcntlr_ftch_idle) or -- not in update filter period sig_shutdown_idle_rising; -- in shutdown and complete sig_incr_ftch_updt_cntr <= sig_ftch_sm_set_getdesc ; sig_decr_ftch_updt_cntr <= sig_pop_dm_status_reg ; sig_ftch_updt_cntr_eq0 <= '1' when sig_ftch_updt_cntr = FTCH_UPDT_ZERO Else '0'; sig_final_updt_idle <= sig_ftch_updt_cntr_eq0 and -- all fetches have corresponding updates sg2sgcntlr_updt_idle ; -- and the SG Update engine is idle ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FTCH_UPDT_CNTR -- -- Process Description: -- Implements a counter to keep track of the number of -- descriptor fetches and updates. This is used to detirmine -- when SG operation are really completed. -- ------------------------------------------------------------- IMP_FTCH_UPDT_CNTR : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_ftch_updt_cntr <= FTCH_UPDT_ZERO; elsif (sig_incr_ftch_updt_cntr = '1' and sig_decr_ftch_updt_cntr = '0') then sig_ftch_updt_cntr <= sig_ftch_updt_cntr + FTCH_UPDT_ONE; Elsif (sig_ftch_updt_cntr_eq0 = '0' and sig_decr_ftch_updt_cntr = '1' and sig_incr_ftch_updt_cntr = '0') Then sig_ftch_updt_cntr <= sig_ftch_updt_cntr - FTCH_UPDT_ONE; else null; -- Hold Current State end if; end if; end process IMP_FTCH_UPDT_CNTR; ------------------------------------------------------------ -- Instance: I_GEN_SG_IDLE_RISE -- -- Description: -- Generates a pulse signaling the last SG update -- operation has completed. -- ------------------------------------------------------------ I_GEN_SG_IDLE_RISE : entity axi_cdma_v4_1.axi_cdma_pulse_gen generic map ( C_INCLUDE_SYNCHRO => NO_SYNCHRONIZERS , C_POS_EDGE_TRIG => POSITIVE_EDGE_TRIGGER , C_PULSE_WIDTH_CLKS => ONE_CLK ) port map ( Clk_In => axi_aclk , Rst_In => axi_reset , Sig_in => sg2sgcntlr_updt_idle , Pulse_Out => sig_update_idle_rising ); ------------------------------------------------------------------------------- -- Update Filter Counter -- -- Used to filter the lag between the acceptance of an update by the SG -- and the Update Idle flag being reset by the SG (going to not idle). -- ------------------------------------------------------------------------------- -- Start the filter counter when a status update is accepted -- by the SG Update interface sig_ld_updt_filter_cntr <= sig_pop_dm_status_reg; sig_updt_filter_cntr_eq0 <= '1' when (sig_updt_filter_cntr = UPDT_FLTR_CNTR_ZERO) else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_UPDT_FILTER_CNTR -- -- Process Description: -- Implements a counter to filter the time lag between an update -- being accepted by the SG and the Update Idle Flag being reset -- by the SG. -- ------------------------------------------------------------- IMP_UPDT_FILTER_CNTR : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_updt_filter_cntr <= UPDT_FLTR_CNTR_ZERO; Elsif (sig_ld_updt_filter_cntr = '1') Then sig_updt_filter_cntr <= UPDT_FLTR_CNTR_LD_VALUE; Elsif (sig_updt_filter_cntr_eq0 = '0') Then sig_updt_filter_cntr <= sig_updt_filter_cntr - UPDT_FLTR_CNTR_ONE; else null; -- Hold Current State end if; end if; end process IMP_UPDT_FILTER_CNTR; ------------------------------------------------------------------------------- -- Idle Set and Clear logic ------------------------------------------------------------------------------- -- The SG operation starts when the Tail Pointer is written by SW in the -- Register Module sgcntl2reg_idle_set <= sig_idle_set ; sgcntl2reg_idle_clr <= sig_idle_clr ; ------------------------------------------------------------ -- Instance: I_GEN_IDLE_CLR -- -- Description: -- Generates the Idle Clear pulse of 1 clock width. -- ------------------------------------------------------------ I_GEN_IDLE_CLR : entity axi_cdma_v4_1.axi_cdma_pulse_gen generic map ( C_INCLUDE_SYNCHRO => NO_SYNCHRONIZERS , C_POS_EDGE_TRIG => POSITIVE_EDGE_TRIGGER , C_PULSE_WIDTH_CLKS => ONE_CLK ) port map ( Clk_In => axi_aclk , Rst_In => axi_reset , Sig_in => reg2sgcntl_tailpntr_updated, Pulse_Out => sig_idle_clr ); sig_shutdown_idle <= (sig_do_shutdown and -- In a shutdown sequence and sig_halt_cmplt_reg ); -- shutdown complete ------------------------------------------------------------ -- Instance: I_GEN_IDLE_SET -- -- Description: -- Generates the Idle Set pulse of 1 clock width. -- ------------------------------------------------------------ I_GEN_IDLE_SET : entity axi_cdma_v4_1.axi_cdma_pulse_gen generic map ( C_INCLUDE_SYNCHRO => NO_SYNCHRONIZERS , C_POS_EDGE_TRIG => POSITIVE_EDGE_TRIGGER , C_PULSE_WIDTH_CLKS => ONE_CLK ) port map ( Clk_In => axi_aclk , Rst_In => axi_reset , Sig_in => sig_shutdown_idle , Pulse_Out => sig_shutdown_idle_rising ); -- Controls for the DataMover Command pending counter sig_inc_cmd_pending <= sig_ftch_sm_ld_dm_cmd; sig_decr_cmd_pending <= sig_sts_sm_push_updt ; sig_dm_cmd_pend_eq0 <= '1' when (sig_dm_cmd_pend_cntr = DM_CMD_PEND_ZERO) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_DM_CMD_PEND_CNTR -- -- Process Description: -- -- ------------------------------------------------------------- IMP_DM_CMD_PEND_CNTR : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_dm_cmd_pend_cntr <= DM_CMD_PEND_ZERO; elsif (sig_inc_cmd_pending = '1' and sig_decr_cmd_pending = '0') then sig_dm_cmd_pend_cntr <= sig_dm_cmd_pend_cntr + DM_CMD_PEND_ONE; elsif (sig_inc_cmd_pending = '0' and sig_decr_cmd_pending = '1' and sig_dm_cmd_pend_eq0 = '0') then sig_dm_cmd_pend_cntr <= sig_dm_cmd_pend_cntr - DM_CMD_PEND_ONE; else null; -- Hold Current State end if; end if; end process IMP_DM_CMD_PEND_CNTR; ------------------------------------------------------------------------------- -- SOF/EOF control logic ------------------------------------------------------------------------------- -- Since CDMA does not need to support SOF/EOF concept (no Stream IF) then -- every descriptor processed is by definition a EOF/SOF case (from the -- viewpoint of the DataMover and the SG engine). sgcntl2sg_pkt_sof <= sig_idle_clr or -- Used to stop Delay Timer when a descr is ready or sig_shtdwn_sm_set_cmplt ; -- Stop delay timer on shutdown completion sgcntl2sg_pkt_eof <= sig_idle_set ; -- Used to start Delay timer ------------------------------------------------------------------------------- -- IOC and Delay Interrupt set control logic ------------------------------------------------------------------------------- -- Just pass these through the SG Controller for now. These were -- brought through the SG Controller just in case the need arose -- for some protection from the register module during simple DMA -- mode. sgcntl2reg_ioc_irq_set <= sg2sgcntl_ioc_irq_set; sgcntl2reg_dly_irq_set <= sg2sgcntl_dly_irq_set; ------------------------------------------------------------------------------- -- Current Descriptor Update to Register module control logic ------------------------------------------------------------------------------- -- Update the Register module with the latest Descriptor's Current -- DEscriptor Address when the SG Fetch Update occurs. sgcntlr2reg_new_curdesc_wren <= sig_ftch_sm_push_updt ; sgcntlr2reg_new_curdesc <= sig_curr_desc_pntr_reg ; ------------------------------------------------------------------------------- -- SG DMA Error set control logic ------------------------------------------------------------------------------- -- Just pass these through the SG Controller for now. These were -- brought through the SG Controller just in case the need arose -- for some protection from the register module during simple DMA -- mode. sgcntlr2reg_dma_interr_set <= sg2sgcntlr_dma_interr_set ; sgcntlr2reg_dma_slverr_set <= sg2sgcntlr_dma_slverr_set ; sgcntlr2reg_dma_decerr_set <= sg2sgcntlr_dma_decerr_set ; ------------------------------------------------------------------------------- -- Misc logic ------------------------------------------------------------------------------- -- See if DataMover is ready for next command sig_mm2s_s2mm_cmd_rdy <= sig_mm2s_cmd_ready and sig_s2mm_cmd_ready; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SG_ACTIVE_FLAG -- -- Process Description: -- Internal flag for enable and disable of state machines. -- ------------------------------------------------------------- IMP_SG_ACTIVE_FLAG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_idle_set = '1') then -- sig_sg_active <= '0'; elsif (sig_idle_clr = '1') then -- sig_sg_active <= '1'; else null; -- Hold Current State end if; end if; end process IMP_SG_ACTIVE_FLAG; ------------------------------------------------------------------------------- -- FETCH Prefetch Limiter Logic ------------------------------------------------------------------------------- sig_incr_ftch_limit_cntr <= sig_ftch_sm_set_getdesc ; sig_decr_ftch_limit_cntr <= sig_pop_dm_status_reg ; sig_ftch_limit_cntr_eq0 <= '1' when sig_ftch_limit_cntr = FTCH_LIMITER_CNTR_ZERO Else '0'; sig_ftch_limit_cntr_eqlimit <= '1' when sig_ftch_limit_cntr = FTCH_LIMIT_VALUE Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FTCH_LIMIT_CNTR -- -- Process Description: -- Implements a counter to keep track of the number of -- descriptor fetches and updates. This is used to limit the -- difference to a fixed value to keep the SG Update Queue from -- going full. The SG Update Queue full can lead to SG lockup. -- ------------------------------------------------------------- IMP_FTCH_LIMIT_CNTR : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_ftch_limit_cntr <= FTCH_LIMITER_CNTR_ZERO; elsif (sig_incr_ftch_limit_cntr = '1' and sig_decr_ftch_limit_cntr = '0') then sig_ftch_limit_cntr <= sig_ftch_limit_cntr + FTCH_LIMITER_CNTR_ONE; Elsif (sig_ftch_limit_cntr_eq0 = '0' and sig_decr_ftch_limit_cntr = '1' and sig_incr_ftch_limit_cntr = '0') Then sig_ftch_limit_cntr <= sig_ftch_limit_cntr - FTCH_LIMITER_CNTR_ONE; else null; -- Hold Current State end if; end if; end process IMP_FTCH_LIMIT_CNTR; ------------------------------------------------------------------------------- -- Descriptor Fetch Logic ------------------------------------------------------------------------------- sgcntl2sg_ftch_tready <= sig_fetch_go or sig_halt_fetch ; -- force tready high on a shutdown -- sig_fetch_last <= sg2sgcntlr_ftch_tlast; sig_fetch_last <= '1'; --sg2sgcntlr_ftch_tlast; -- sig_good_fetch_dbeat <= sig_fetch_go and sig_good_fetch_dbeat <= sg2sgcntlr_ftch_tvalid_new; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FETCH_GO_FLOP -- -- Process Description: -- Implements the fetch go and done flags -- ------------------------------------------------------------- IMP_FETCH_GO_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_ftch_sm_done = '1') then -- sig_fetch_go <= '0'; -- sig_fetch_done <= '0'; elsif (sig_ftch_sm_set_getdesc_ns = '1') then -- sig_fetch_go <= '1'; -- sig_fetch_done <= '0'; Elsif (sig_good_fetch_dbeat = '1' and sig_fetch_last = '1') Then -- sig_fetch_go <= '0'; -- sig_fetch_done <= '1'; else null; -- hold current state end if; end if; end process IMP_FETCH_GO_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FETCH_DB_CNTR -- -- Process Description: -- Implements the descriptor fetch data beat counter -- ------------------------------------------------------------- IMP_FETCH_DB_CNTR : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_ftch_sm_set_getdesc_ns = '1') then sig_fetch_dbeat_cnt <= (others => '0'); elsif (sig_good_fetch_dbeat = '1' and sig_fetch_done = '0' and sig_fetch_last = '0') then sig_fetch_dbeat_cnt <= sig_fetch_dbeat_cnt + DESCR_DBEAT_CNT_ONE ; else null; -- Hold Current State end if; end if; end process IMP_FETCH_DB_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CURR_DESC_PNTR_REG -- -- Process Description: -- Implements the Next descriptor pointer reg. It is -- cleared when the fetch process is complete. -- ------------------------------------------------------------- -- IMP_CURR_DESC_PNTR_REG : process (axi_aclk) -- begin -- if (axi_aclk'event and axi_aclk = '1') then -- if (axi_reset = '1' or -- sig_ftch_sm_done = '1') then -- sig_curr_desc_pntr_reg <= (others => '0'); -- elsif (sig_good_fetch_dbeat = '1' and -- sig_fetch_dbeat_cnt = CDA_LS) then sig_curr_desc_pntr_reg <= sg2sgcntlr_ftch_tdata_new (127 downto 96); -- else -- null; -- Hold Current State -- end if; -- end if; -- end process IMP_CURR_DESC_PNTR_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SRC_ADDR_REG -- -- Process Description: -- Implements the Source Address register. It is -- cleared when the fetch process is complete. -- ------------------------------------------------------------- -- IMP_SRC_ADDR_REG : process (axi_aclk) -- begin -- if (axi_aclk'event and axi_aclk = '1') then -- if (axi_reset = '1' or -- sig_ftch_sm_done = '1') then -- sig_src_addr_reg <= (others => '0'); -- elsif (sig_good_fetch_dbeat = '1' and -- sig_fetch_dbeat_cnt = SA_LS) then sig_src_addr_reg <= sg2sgcntlr_ftch_tdata_new (31 downto 0); -- else -- null; -- Hold Current State -- end if; -- end if; -- end process IMP_SRC_ADDR_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_DEST_ADDR_REG -- -- Process Description: -- Implements the Destination Address register. It is -- cleared when the fetch process is complete. -- ------------------------------------------------------------- -- IMP_DEST_ADDR_REG : process (axi_aclk) -- begin -- if (axi_aclk'event and axi_aclk = '1') then -- if (axi_reset = '1' or -- sig_ftch_sm_done = '1') then -- sig_dest_addr_reg <= (others => '0'); -- elsif (sig_good_fetch_dbeat = '1' and -- sig_fetch_dbeat_cnt = DA_LS) then sig_dest_addr_reg <= sg2sgcntlr_ftch_tdata_new (63 downto 32); -- else -- null; -- Hold Current State -- end if; -- end if; -- end process IMP_DEST_ADDR_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_BTT_REG -- -- Process Description: -- Implements the BTT register. It is -- cleared when the fetch process is complete. -- ------------------------------------------------------------- -- IMP_BTT_REG : process (axi_aclk) -- begin -- if (axi_aclk'event and axi_aclk = '1') then -- if (axi_reset = '1' or -- sig_ftch_sm_done = '1') then -- sig_btt_reg <= (others => '0'); -- elsif (sig_good_fetch_dbeat = '1' and -- sig_fetch_dbeat_cnt = BTT) then sig_btt_reg <= sg2sgcntlr_ftch_tdata_new (95 downto 64); -- else -- null; -- Hold Current State -- end if; -- end if; -- end process IMP_BTT_REG; ------------------------------------------------------------------------------- -- Rip the needed BTT bits for the DataMover from the descriptor BTT register ------------------------------------------------------------------------------- sig_btt_dm_slice <= sig_btt_reg(DM_BTT_FIELD_WIDTH-1 downto 0); ------------------------------------------------------------------------------- -- Command TAG Generator (just an incrementing counter) -- The Command tag is used for test and debug to track command execution flow -- through the DataMover. ------------------------------------------------------------------------------- sig_cmd_tag <= STD_LOGIC_VECTOR(sig_cmd_tag_cntr); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: DM_TAG_CNTR -- -- Process Description: -- Command tag generator. This is just a simple counter -- that increments every time a command is loaded into the -- DataMover. Counter rollover is ok. -- ------------------------------------------------------------- DM_TAG_CNTR : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or reg2sgcntl_sg_mode = '0') then sig_cmd_tag_cntr <= (others => '0'); elsif (sig_ftch_sm_ld_dm_cmd = '1') then sig_cmd_tag_cntr <= sig_cmd_tag_cntr + TAG_CNT_ONE; else null; -- hold current state end if; end if; end process DM_TAG_CNTR; ------------------------------------------------------------------------------- -- MM2S Command Generation ------------------------------------------------------------------------------- sgcntl2mm2s_cmd_tdata <= sig_mm2s_cmd ; sgcntl2mm2s_cmd_tvalid <= sig_mm2s_cmd_valid ; sig_mm2s_cmd_ready <= mm2s2sgcntl_cmd_tready ; sig_mm2s_cmd_valid <= sig_ftch_sm_ld_dm_cmd ; type_of_burst <= '1' and (not burst_type_read); -- Formulate the MM2S Command sig_mm2s_cmd <= CMD_RSVD & -- reserved sig_cmd_tag & -- Tag sig_src_addr_reg & -- Address '1' & -- DRR bit '1' & -- EOF bit sig_mm2s_dsa_field & -- DSA Field Assignment type_of_burst & -- '1' & -- Incrementing burst type sig_btt_dm_slice ; -- BTT -- Rip the Destnation address offset bits sig_mm2s_dsa_offset <= sig_dest_addr_reg(DSA_ADDR_OFFSET_WIDTH-1 downto 0); -- Size the dest addr offset to the DSA field width sig_mm2s_dsa_field <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(sig_mm2s_dsa_offset), CMD_DSA_WIDTH)); ------------------------------------------------------------------------------- -- MM2S Status Reg and logic ------------------------------------------------------------------------------- sgcntl2mm2s_sts_tready <= sig_sts_sm_pop_mm2s_sts or sig_halt_dm ; -- allow status to flush on shutdown sig_mm2s_sts_tvalid <= mm2s2sgcntl_sts_tvalid ; sig_mm2s_sts_tdata <= mm2s2sgcntl_sts_tdata ; -- DataMover MM2S Error discrete sig_mm2s2cntl_err <= mm2s2sgcntl_err ; -- Rip the status bits from the status register sig_mm2s_tag <= sig_mm2s_status_reg(STS_TAG_MS_INDEX downto 0); sig_mm2s_interr <= sig_mm2s_status_reg(STS_INTERR_INDEX); sig_mm2s_decerr <= sig_mm2s_status_reg(STS_DECERR_INDEX); sig_mm2s_slverr <= sig_mm2s_status_reg(STS_SLVERR_INDEX); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_MM2S_STATUS_REG -- -- Process Description: -- Implements the MM2S status reply holding register. -- ------------------------------------------------------------- IMP_MM2S_STATUS_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_sts_sm_push_updt = '1') then sig_mm2s_status_reg <= (others => '0'); elsif (sig_sts_sm_pop_mm2s_sts = '1') then sig_mm2s_status_reg <= sig_mm2s_sts_tdata; else null; -- hold current state end if; end if; end process IMP_MM2S_STATUS_REG; ------------------------------------------------------------------------------- -- S2MM Command Generation ------------------------------------------------------------------------------- sgcntl2s2mm_cmd_tdata <= sig_s2mm_cmd ; sgcntl2s2mm_cmd_tvalid <= sig_s2mm_cmd_valid ; sig_s2mm_cmd_ready <= s2mm2sgcntl_cmd_tready ; sig_s2mm_cmd_valid <= sig_ftch_sm_ld_dm_cmd ; type_of_burst_write <= '1' and (not burst_type_write); -- Formulate the S2MM Command sig_s2mm_cmd <= CMD_RSVD & -- reserved sig_cmd_tag & -- Tag sig_dest_addr_reg & -- Address '1' & -- DRR bit '1' & -- EOF bit CMD_DSA_ZEROED & -- DSA Field Assignment type_of_burst_write & -- '1' & -- Incrementing burst type sig_btt_dm_slice ; -- BTT ------------------------------------------------------------------------------- -- S2MM Status Reg and logic ------------------------------------------------------------------------------- sgcntl2s2mm_sts_tready <= sig_sts_sm_pop_s2mm_sts or sig_halt_dm ; -- allow status to flush on shutdown; sig_s2mm_sts_tvalid <= s2mm2sgcntl_sts_tvalid ; sig_s2mm_sts_tdata <= s2mm2sgcntl_sts_tdata ; -- DataMover S2MM Error discrete sig_s2mm2cntl_err <= s2mm2sgcntl_err ; -- Rip the status bits from the status register sig_s2mm_tag <= sig_s2mm_status_reg(STS_TAG_MS_INDEX downto 0); sig_s2mm_interr <= sig_s2mm_status_reg(STS_INTERR_INDEX); sig_s2mm_decerr <= sig_s2mm_status_reg(STS_DECERR_INDEX); sig_s2mm_slverr <= sig_s2mm_status_reg(STS_SLVERR_INDEX); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_S2MM_STATUS_REG -- -- Process Description: -- Implements the MM2S status reply holding register. -- ------------------------------------------------------------- IMP_S2MM_STATUS_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_sts_sm_push_updt = '1') then sig_s2mm_status_reg <= (others => '0'); elsif (sig_sts_sm_pop_s2mm_sts = '1') then sig_s2mm_status_reg <= sig_s2mm_sts_tdata; else null; -- hold current state end if; end if; end process IMP_S2MM_STATUS_REG; ------------------------------------------------------------------------------- -- Fetch Update words formulation ------------------------------------------------------------------------------- -- Assign the Fetch update outputs to the SG Fetch Update port sgcntl2sg_updptr_tvalid <= sig_fetch_update_full ; sgcntl2sg_updptr_tdata <= sig_fetch_update_reg ; sgcntl2sg_updptr_tlast <= sig_fetch_update_last ; sig_fetch_updptr_tready <= sg2sgcntlr_updptr_tready ; sig_fetch_update_last <= sig_fetch_update_full;-- and -- not(sig_fetch_update_full_1); sig_ld_fetch_update_reg <= sig_ftch_sm_push_updt and sig_fetch_update_empty ; sig_pop_fetch_update_reg <= sig_fetch_update_full and sig_fetch_updptr_tready ; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FETCH_UPDATE_FLAGS -- -- Process Description: -- Implements the Fetch Update Register status flags. -- Note that this simulates a 2-deep register requiring -- 2 pops to become empty (not full). -- ------------------------------------------------------------- IMP_FETCH_UPDATE_FLAGS : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_pop_fetch_update_reg = '1' or sig_halt_fetch = '1') then -- sig_fetch_update_full_1 <= '0'; sig_fetch_update_full <= '0'; -- sig_fetch_update_empty_1 <= '1'; sig_fetch_update_empty <= '1'; elsif (sig_ld_fetch_update_reg = '1') then -- sig_fetch_update_full_1 <= '1'; sig_fetch_update_full <= '1'; -- sig_fetch_update_empty_1 <= '0'; sig_fetch_update_empty <= '0'; -- elsif (sig_pop_fetch_update_reg = '1') then -- sig_fetch_update_full_1 <= '0'; -- sig_fetch_update_full <= sig_fetch_update_full_1; -- sig_fetch_update_empty_1 <= '1'; -- sig_fetch_update_empty <= sig_fetch_update_empty_1; else null; -- Hold Current State end if; end if; end process IMP_FETCH_UPDATE_FLAGS; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FETCH_UPDATE_REG -- -- Process Description: -- Implements the fetch update register for the current -- descriptor address write to the SG Update port. -- ------------------------------------------------------------- IMP_FETCH_UPDATE_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_pop_fetch_update_reg = '1') then sig_fetch_update_reg <= (others => '0'); elsif (sig_ld_fetch_update_reg = '1') then sig_fetch_update_reg <= sig_curr_desc_pntr_reg; -- Curr Descr Pointer LS else null; -- Hold Current State end if; end if; end process IMP_FETCH_UPDATE_REG; ------------------------------------------------------------------------------- -- Status DM Error merging ------------------------------------------------------------------------------- -- If the MM2S Status tag does not match the S2MM Status tag, -- this is a nasty internal error where a status reply has been -- dropped by the DataMover. This is a unique condition for the -- CDMA application. sig_tag_error <= '0' When (sig_halt_dm = '1') else '1' when (sig_s2mm_tag /= sig_mm2s_tag) Else '0'; sig_composite_interr <= (sig_s2mm_interr or sig_mm2s_interr or sig_tag_error) and not(sig_halt_dm) ; sig_composite_slverr <= (sig_s2mm_slverr or sig_mm2s_slverr) and not(sig_halt_dm) ; sig_composite_decerr <= (sig_s2mm_decerr or sig_mm2s_decerr) and not(sig_halt_dm) ; ------------------------------------------------------------------------------- -- Status Update Register Logic ------------------------------------------------------------------------------- -- Assign Output Stream port to SG Status Update interface sgcntl2sg_updsts_tvalid <= sig_dm_status_full; sgcntl2sg_updsts_tdata <= sig_dm_status_reg ; sgcntl2sg_updsts_tlast <= '1' ; sig_status_updsts_tready <= sg2sgcntlr_updsts_tready ; sig_ld_dm_status_reg <= sig_sts_sm_push_updt and sig_dm_status_empty; sig_pop_dm_status_reg <= sig_dm_status_full and sig_status_updsts_tready ; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_DM_STATUS_REG -- -- Process Description: -- Implements the composite transfer status register for the -- descriptor. -- ------------------------------------------------------------- IMP_DM_STATUS_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_pop_dm_status_reg = '1' or sig_halt_status = '1') then sig_dm_status_reg <= (others => '0'); sig_dm_status_full <= '0'; sig_dm_status_empty <= '1'; elsif (sig_ld_dm_status_reg = '1') then sig_dm_status_reg <= '1' & -- SG Update IOC bit '1' & -- Descriptor Cmplt bit sig_composite_decerr & -- DM Decode Error sig_composite_slverr & -- DM Slave Error sig_composite_interr & -- DM Internal Error STATUS_RSVD ; -- Unused (zeros) sig_dm_status_full <= '1'; sig_dm_status_empty <= '0'; else null; -- Hold Current State end if; end if; end process IMP_DM_STATUS_REG; ------------------------------------------------------------------------------- -- Descriptor Fetch State Machine ------------------------------------------------------------------------------- ------------------------------------------------------------- -- Combinational Process -- -- Label: IMP_FETCH_SM_COMB -- -- Process Description: -- Implements the combinatorial portion of the Descriptor -- Fetch from SG state machine. -- ------------------------------------------------------------- IMP_FETCH_SM_COMB : process (sig_ftch_sm_state , sig_halt_fetch , sig_sg_active , sig_sg2sgcntlr_ftch_desc_available , sig_mm2s_s2mm_cmd_rdy , sig_fetch_update_empty , -- sig_fetch_done , sig_ftch_limit_cntr_eqlimit ) begin -- assign the default values sig_ftch_sm_state_ns <= FTCH_IDLE ; sig_ftch_sm_set_getdesc_ns <= '0' ; sig_ftch_sm_ld_dm_cmd_ns <= '0' ; sig_ftch_sm_push_updt_ns <= '0' ; sig_ftch_sm_done_ns <= '0' ; case sig_ftch_sm_state is --------------------------------- when FTCH_IDLE => If (sig_sg_active = '1' and sig_halt_fetch = '0') Then -- Start operations sig_ftch_sm_state_ns <= CHK_SG_DM_RDY ; Else -- wait here sig_ftch_sm_state_ns <= FTCH_IDLE ; End if; --------------------------------- when CHK_SG_DM_RDY => if (sig_halt_fetch = '1') then sig_ftch_sm_state_ns <= XFER_DONE ; elsif (sig_ftch_limit_cntr_eqlimit = '0' and sig_sg2sgcntlr_ftch_desc_available = '1' and sig_mm2s_s2mm_cmd_rdy = '1' and sig_fetch_update_empty = '1') then sig_ftch_sm_state_ns <= LOAD_DESC ; sig_ftch_sm_set_getdesc_ns <= '1' ; sig_ftch_sm_ld_dm_cmd_ns <= '1' ; sig_ftch_sm_push_updt_ns <= '1' ; else sig_ftch_sm_state_ns <= CHK_SG_DM_RDY ; end if; --------------------------------- when LOAD_DESC => sig_ftch_sm_set_getdesc_ns <= '0' ; if (sig_halt_fetch = '1') then sig_ftch_sm_state_ns <= XFER_DONE ; else --if (sig_fetch_done = '1') then sig_ftch_sm_state_ns <= XFER_DONE ; -- sig_ftch_sm_ld_dm_cmd_ns <= '1' ; -- sig_ftch_sm_push_updt_ns <= '1' ; -- else -- sig_ftch_sm_state_ns <= LOAD_DESC ; end if; --------------------------------- when XFER_DONE => sig_ftch_sm_state_ns <= FTCH_IDLE ; sig_ftch_sm_done_ns <= '1' ; --------------------------------- when others => sig_ftch_sm_state_ns <= FTCH_IDLE ; end case; end process IMP_FETCH_SM_COMB; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FETCH_SM_REG -- -- Process Description: -- Implements the registered portion of the descriptor Fetch -- State Machine. -- ------------------------------------------------------------- IMP_FETCH_SM_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_ftch_sm_state <= FTCH_IDLE ; sig_ftch_sm_set_getdesc <= '0' ; sig_ftch_sm_ld_dm_cmd <= '0' ; sig_ftch_sm_push_updt <= '0' ; sig_ftch_sm_done <= '0' ; -- sig_fetch_go <= '0' ; sig_fetch_done <= '0' ; else sig_ftch_sm_state <= sig_ftch_sm_state_ns ; sig_ftch_sm_set_getdesc <= sig_ftch_sm_set_getdesc_ns ; -- sig_fetch_go <= sig_ftch_sm_set_getdesc_ns ; sig_fetch_done <= sig_fetch_go; sig_ftch_sm_ld_dm_cmd <= sig_ftch_sm_ld_dm_cmd_ns ; sig_ftch_sm_push_updt <= sig_ftch_sm_push_updt_ns ; sig_ftch_sm_done <= sig_ftch_sm_done_ns ; end if; end if; end process IMP_FETCH_SM_REG; sig_fetch_go <= sig_ftch_sm_set_getdesc_ns ; ------------------------------------------------------------------------------- -- Status Update State Machine ------------------------------------------------------------------------------- ------------------------------------------------------------- -- Combinational Process -- -- Label: IMP_STATUS_SM_COMB -- -- Process Description: -- Implements the combinatorial portion of the Status Update -- State Machine. -- ------------------------------------------------------------- IMP_STATUS_SM_COMB : process (sig_sts_sm_state , sig_halt_status , sig_sg_active , sig_dm_cmd_pend_eq0 , sig_mm2s_sts_tvalid , sig_s2mm_sts_tvalid , sig_dm_status_empty ) begin -- assign the default values sig_sts_sm_state_ns <= STS_IDLE ; sig_sts_sm_pop_mm2s_sts_ns <= '0' ; sig_sts_sm_pop_s2mm_sts_ns <= '0' ; sig_sts_sm_push_updt_ns <= '0' ; case sig_sts_sm_state is --------------------------------- when STS_IDLE => If (sig_sg_active = '1' and sig_halt_status = '0') Then -- Start operations sig_sts_sm_state_ns <= GET_MM2S_STATUS ; Else -- wait here sig_sts_sm_state_ns <= STS_IDLE ; End if; --------------------------------- when GET_MM2S_STATUS => if (sig_halt_status = '1') then sig_sts_sm_state_ns <= STS_IDLE ; elsif (sig_mm2s_sts_tvalid = '1') then sig_sts_sm_state_ns <= GET_S2MM_STATUS ; sig_sts_sm_pop_mm2s_sts_ns <= '1' ; else sig_sts_sm_state_ns <= GET_MM2S_STATUS ; end if; --------------------------------- when GET_S2MM_STATUS => if (sig_halt_status = '1') then sig_sts_sm_state_ns <= STS_IDLE ; elsif (sig_s2mm_sts_tvalid = '1') then sig_sts_sm_state_ns <= DO_UPDATE ; sig_sts_sm_pop_s2mm_sts_ns <= '1' ; else sig_sts_sm_state_ns <= GET_S2MM_STATUS ; end if; --------------------------------- when DO_UPDATE => If (sig_dm_status_empty = '1') Then sig_sts_sm_state_ns <= STS_IDLE ; sig_sts_sm_push_updt_ns <= '1' ; Else sig_sts_sm_state_ns <= DO_UPDATE ; End if; --------------------------------- when others => -- shouldn't ever get here sig_sts_sm_state_ns <= STS_IDLE ; end case; end process IMP_STATUS_SM_COMB; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_STATUS_SM_REG -- -- Process Description: -- Implements the registered portion of the Status Update -- State Machine. -- ------------------------------------------------------------- IMP_STATUS_SM_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_sts_sm_state <= STS_IDLE ; sig_sts_sm_pop_mm2s_sts <= '0' ; sig_sts_sm_pop_s2mm_sts <= '0' ; sig_sts_sm_push_updt <= '0' ; else sig_sts_sm_state <= sig_sts_sm_state_ns ; sig_sts_sm_pop_mm2s_sts <= sig_sts_sm_pop_mm2s_sts_ns ; sig_sts_sm_pop_s2mm_sts <= sig_sts_sm_pop_s2mm_sts_ns ; sig_sts_sm_push_updt <= sig_sts_sm_push_updt_ns ; end if; end if; end process IMP_STATUS_SM_REG; ------------------------------------------------------------------------------- -- controlled Shutdown State Machine and related logic ------------------------------------------------------------------------------- -- Reset Module HALT request and complete reply sig_halt_request <= rst2sgcntl_halt ; sgcntl2rst_halt_cmplt <= sig_halt_cmplt_reg; -- SG Descriptor Queue flush request sgcntlr2sg_desc_flush <= sig_flush_sg ; -- DataMover Halt requests sgcntl2mm2s_halt <= sig_halt_dm ; sgcntl2s2mm_halt <= sig_halt_dm ; -- Composite DataMover halt complete flag sig_dmhalt_cmplt <= mm2s2sgcntl_halt_cmplt and s2mm2sgcntl_halt_cmplt ; -- Fetch State Machine Idle flag sig_ftchsm_idle <= '1' when (sig_ftch_sm_state = FTCH_IDLE) Else '0'; -- Status State Machine Idle flag sig_stssm_idle <= '1' when (sig_sts_sm_state = STS_IDLE) Else '0'; -- Composite error flag indicating that an error occured -- during a descriptor fetch or update operation sig_sg_error <= sg2sgcntlr_ftch_error or sg2sgcntlr_updt_error ; -- Formulate the shutdown request decision logic sig_do_shutdown <= sig_halt_request or sig_sg_error or sg2sgcntlr_ftch_stale_desc or sg2sgcntlr_dma_interr_set or sg2sgcntlr_dma_slverr_set or sg2sgcntlr_dma_decerr_set ; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_HALT_CMPLT_REG -- -- Process Description: -- Implements the Halt Complete register. -- This is sticky and is only cleared by a reset. -- ------------------------------------------------------------- IMP_HALT_CMPLT_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_halt_cmplt_reg <= '0'; elsif (sig_shtdwn_sm_set_cmplt_ns = '1') then sig_halt_cmplt_reg <= '1'; else null; -- hold current state end if; end if; end process IMP_HALT_CMPLT_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_DM_HALT_FLOP -- -- Process Description: -- Implements the sticky flag that requests a DataMover -- HALT. -- This is sticky and is only cleared by a reset. -- ------------------------------------------------------------- IMP_DM_HALT_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_halt_dm <= '0'; elsif (sig_shtdwn_sm_set_dm_halt_ns = '1') then sig_halt_dm <= '1'; else null; -- Hold Current State end if; end if; end process IMP_DM_HALT_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FTCH_HALT_FLOP -- -- Process Description: -- Implements the sticky flag that requests a DataMover -- HALT. -- This is sticky and is only cleared by a reset. -- ------------------------------------------------------------- IMP_FTCH_HALT_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_halt_fetch <= '0'; elsif (sig_shtdwn_sm_set_ftch_halt_ns = '1') then sig_halt_fetch <= '1'; else null; -- Hold Current State end if; end if; end process IMP_FTCH_HALT_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_DM_SG_FLUSH -- -- Process Description: -- Implements the sticky flag that requests a SG -- Queue flush. The Shutdown state Machine controls -- when it is set. -- This is sticky and is only cleared by a reset. -- ------------------------------------------------------------- IMP_DM_SG_FLUSH : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_flush_sg <= '0'; elsif (sig_shtdwn_sm_flush_sg_ns = '1') then sig_flush_sg <= '1'; else null; -- Hold Current State end if; end if; end process IMP_DM_SG_FLUSH; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_STS_HALT_FLOP -- -- Process Description: -- Implements the sticky flag that requests a Status State -- Machine halt. -- This is sticky and is only cleared by a reset. -- ------------------------------------------------------------- IMP_STS_HALT_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_halt_status <= '0'; elsif (sig_shtdwn_sm_set_sts_halt_ns = '1') then sig_halt_status <= '1'; else null; -- Hold Current State end if; end if; end process IMP_STS_HALT_FLOP; ------------------------------------------------------------- -- Combinational Process -- -- Label: IMP_SHTDWN_SM_COMB -- -- Process Description: -- Implements the combinatorial portion of the Shutdown -- State Machine. The shutdown sequence is activated by -- either a soft reset request from the reset module or -- by a detected error condition. -- ------------------------------------------------------------- IMP_SHTDWN_SM_COMB : process (sig_shtdwn_sm_state , sig_do_shutdown , sg2sgcntlr_ftch_idle , sg2sgcntlr_updt_idle , sig_ftchsm_idle , sig_stssm_idle , sig_dm_status_empty , sig_fetch_update_empty , sig_dmhalt_cmplt , sig_sg_error ) begin -- assign the default values sig_shtdwn_sm_state_ns <= SHTDWN_IDLE ; sig_shtdwn_sm_flush_sg_ns <= '0'; sig_shtdwn_sm_set_ftch_halt_ns <= '0'; sig_shtdwn_sm_set_dm_halt_ns <= '0'; sig_shtdwn_sm_set_sts_halt_ns <= '0'; sig_shtdwn_sm_set_cmplt_ns <= '0'; case sig_shtdwn_sm_state is --------------------------------- when SHTDWN_IDLE => if (sig_do_shutdown = '1') then -- start shutdown sequence sig_shtdwn_sm_state_ns <= HALT_FTCH_DM; sig_shtdwn_sm_set_ftch_halt_ns <= '1'; sig_shtdwn_sm_set_dm_halt_ns <= '1'; else -- Stay here sig_shtdwn_sm_state_ns <= SHTDWN_IDLE ; end if; --------------------------------- when HALT_FTCH_DM => sig_shtdwn_sm_state_ns <= WAIT_FTCH_IDLE ; sig_shtdwn_sm_flush_sg_ns <= '1' ; --------------------------------- when WAIT_FTCH_IDLE => if (sig_ftchsm_idle = '1') then sig_shtdwn_sm_state_ns <= WAIT_FTCH_UPDATE ; else sig_shtdwn_sm_state_ns <= WAIT_FTCH_IDLE ; end if; --------------------------------- when WAIT_FTCH_UPDATE => if (sg2sgcntlr_ftch_idle = '1' and sig_ftchsm_idle = '1') then sig_shtdwn_sm_state_ns <= WAIT_DM_HALT_CMPLT ; else sig_shtdwn_sm_state_ns <= WAIT_FTCH_UPDATE ; end if; --------------------------------- when WAIT_DM_HALT_CMPLT => if (sig_dmhalt_cmplt = '1') then sig_shtdwn_sm_state_ns <= WAIT_STS_IDLE ; sig_shtdwn_sm_set_sts_halt_ns <= '1' ; else sig_shtdwn_sm_state_ns <= WAIT_DM_HALT_CMPLT ; end if; --------------------------------- when WAIT_STS_IDLE => if (sig_stssm_idle = '1') then sig_shtdwn_sm_state_ns <= WAIT_STS_UPDATE ; else sig_shtdwn_sm_state_ns <= WAIT_STS_IDLE ; end if; --------------------------------- when WAIT_STS_UPDATE => if (sig_dm_status_empty = '1') then sig_shtdwn_sm_state_ns <= WAIT_SG_UPDATE ; else sig_shtdwn_sm_state_ns <= WAIT_STS_UPDATE ; end if; --------------------------------- when WAIT_SG_UPDATE => if (sg2sgcntlr_updt_idle = '1') then sig_shtdwn_sm_state_ns <= SHTDWN_CMPLT ; sig_shtdwn_sm_set_cmplt_ns <= '1'; else sig_shtdwn_sm_state_ns <= WAIT_SG_UPDATE ; end if; --------------------------------- when SHTDWN_CMPLT => sig_shtdwn_sm_state_ns <= SHTDWN_CMPLT ; sig_shtdwn_sm_set_cmplt_ns <= '1'; --------------------------------- when others => -- shouldn't ever get here sig_shtdwn_sm_state_ns <= SHTDWN_IDLE ; end case; end process IMP_SHTDWN_SM_COMB; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SHTDWN_SM_REG -- -- Process Description: -- Implements the registered portion of the shutdown -- State Machine. -- ------------------------------------------------------------- IMP_SHTDWN_SM_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_shtdwn_sm_state <= SHTDWN_IDLE ; sig_shtdwn_sm_flush_sg <= '0' ; sig_shtdwn_sm_set_ftch_halt <= '0' ; sig_shtdwn_sm_set_dm_halt <= '0' ; sig_shtdwn_sm_set_sts_halt <= '0' ; sig_shtdwn_sm_set_cmplt <= '0' ; else sig_shtdwn_sm_state <= sig_shtdwn_sm_state_ns ; sig_shtdwn_sm_flush_sg <= sig_shtdwn_sm_flush_sg_ns ; sig_shtdwn_sm_set_ftch_halt <= sig_shtdwn_sm_set_ftch_halt_ns ; sig_shtdwn_sm_set_dm_halt <= sig_shtdwn_sm_set_dm_halt_ns ; sig_shtdwn_sm_set_sts_halt <= sig_shtdwn_sm_set_sts_halt_ns ; sig_shtdwn_sm_set_cmplt <= sig_shtdwn_sm_set_cmplt_ns ; end if; end if; end process IMP_SHTDWN_SM_REG; end implementation;
------------------------------------------------------------------------------- -- $Id: cntr_incr_decr_addn_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- cntr_incr_decr_addn_f - entity / architecture pair ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2005 - 2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: cntr_incr_decr_addn_f.vhd -- -- Description: This counter can increment, decrement or skip ahead -- by an arbitrary amount. -- -- If Reset is active, the value Cnt synchronously resets -- to all ones. (This reset value, different than the -- customary reset value of zero, caters to the original -- application of cntr_incr_decr_addn_f as the address -- counter for srl_fifo_rbu_f.) -- -- Otherwise, on each Clk, one is added to Cnt if Incr is -- asserted and one is subtracted if Decr is asserted. (If -- both are asserted, then there is no change to Cnt.) -- -- If Decr is not asserted, then the input value, -- Nm_to_add, is added. (Simultaneous assertion of Incr -- would add one more.) If Decr is asserted, then -- N_to_add, is ignored, i.e., it is possible to decrement -- by one or add N, but not both, and Decr overrides. -- -- The value that Cnt will take on at the next clock -- is available as Cnt_p1. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- cntr_incr_decr_addn_f.vhd -- ------------------------------------------------------------------------------- -- -- History: -- FLO 12/30/05 First Version. -- -- ~~~~~~ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_com" -- pipelined or register delay signals: "_d#" -- predecessor value by # clks: "_p#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- entity cntr_incr_decr_addn_f is generic ( C_SIZE : natural; C_FAMILY : string := "nofamily" ); port ( Clk : in std_logic; Reset : in std_logic; -- Note: the counter resets to all ones! Incr : in std_logic; Decr : in std_logic; N_to_add : in std_logic_vector(C_SIZE-1 downto 0); Cnt : out std_logic_vector(C_SIZE-1 downto 0); Cnt_p1 : out std_logic_vector(C_SIZE-1 downto 0) ); end entity cntr_incr_decr_addn_f; ---( library proc_common_v3_00_a; library ieee; use ieee.numeric_std.UNSIGNED; use ieee.numeric_std."+"; library unisim; use unisim.all; -- Make unisim entities available for default binding. -- architecture imp of cntr_incr_decr_addn_f is use proc_common_v3_00_a.family_support; use family_support.all; -- primitives_type, primitive_array_type, supported constant COUNTER_PRIMS_AVAIL : boolean := supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDS)); signal cnt_i : std_logic_vector(Cnt'range); signal cnt_i_p1 : std_logic_vector(Cnt'range); ---------------------------------------------------------------------------- -- Unisim components declared locally for maximum avoidance of default -- binding and vcomponents version issues. ---------------------------------------------------------------------------- component MUXCY_L port ( LO : out std_ulogic; CI : in std_ulogic; DI : in std_ulogic; S : in std_ulogic ); end component; component XORCY port ( O : out std_ulogic; CI : in std_ulogic; LI : in std_ulogic ); end component; component FDS generic ( INIT : bit := '1' ); port ( Q : out std_ulogic; C : in std_ulogic; D : in std_ulogic; S : in std_ulogic ); end component; begin -- architecture imp ---( STRUCTURAL_A_GEN : if COUNTER_PRIMS_AVAIL = true generate signal hsum_A : std_logic_vector(Cnt'range); signal cry : std_logic_vector(Cnt'length downto 0); begin ---( cry(0) <= Incr; Addr_Counters : for I in cnt_i'range generate hsum_A(I) <= ((Decr or N_to_add(i)) xor cnt_i(I)); MUXCY_L_I : component MUXCY_L port map ( DI => cnt_i(I), CI => cry(I), S => hsum_A(I), LO => cry(I+1)); XORCY_I : component XORCY port map ( LI => hsum_A(I), CI => cry(I), O => cnt_i_p1(I)); FDS_I : component FDS port map ( Q => cnt_i(I), C => Clk, D => cnt_i_p1(I), S => Reset); end generate Addr_Counters; ---) end generate STRUCTURAL_A_GEN; ---) ---( INFERRED_GEN : if COUNTER_PRIMS_AVAIL = false generate -- CNT_I_P1_PROC : process( cnt_i, N_to_add, Decr, Incr ) is -- function qual_n_to_add(N_to_add : std_logic_vector; Decr : std_logic ) return UNSIGNED is variable r: UNSIGNED(N_to_add'range); begin for i in r'range loop r(i) := N_to_add(i) or Decr; end loop; return r; end; -- function to_singleton_unsigned(s : std_logic) return unsigned is variable r : unsigned(0 to 0) := (others => s); begin return r; end; -- begin cnt_i_p1 <= std_logic_vector( UNSIGNED(cnt_i) + qual_n_to_add(N_to_add, Decr) + to_singleton_unsigned(Incr) ); end process; -- CNT_I_PROC : process(Clk) is begin if Clk'event and Clk = '1' then if Reset = '1' then cnt_i <= (others => '1'); else cnt_i <= cnt_i_p1; end if; end if; end process; -- end generate INFERRED_GEN; ---) Cnt <= cnt_i; Cnt_p1 <= cnt_i_p1; end architecture imp; ---)
---------------------------------------------------------------------------------- -- Engineer: Mike Field <[email protected]> -- -- Description: Top level for the OV7670 camera project. ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; Library UNISIM; use UNISIM.vcomponents.all; entity ov7670_top is Port ( clk100 : in STD_LOGIC; OV7670_SIOC : out STD_LOGIC; OV7670_SIOD : inout STD_LOGIC; OV7670_RESET : out STD_LOGIC; OV7670_PWDN : out STD_LOGIC; OV7670_VSYNC : in STD_LOGIC; OV7670_HREF : in STD_LOGIC; OV7670_PCLK : in STD_LOGIC; OV7670_XCLK : out STD_LOGIC; OV7670_D : in STD_LOGIC_VECTOR(7 downto 0); LED : out STD_LOGIC_VECTOR(7 downto 0); vga_red : out STD_LOGIC_VECTOR(3 downto 0); vga_green : out STD_LOGIC_VECTOR(3 downto 0); vga_blue : out STD_LOGIC_VECTOR(3 downto 0); vga_hsync : out STD_LOGIC; vga_vsync : out STD_LOGIC; btn : in STD_LOGIC ); end ov7670_top; architecture Behavioral of ov7670_top is COMPONENT debounce PORT( clk : IN std_logic; i : IN std_logic; o : OUT std_logic ); END COMPONENT; component clocking port (-- Clock in ports CLK_100 : in std_logic; -- Clock out ports CLK_50 : out std_logic; CLK_25 : out std_logic ); end component; COMPONENT ov7670_controller PORT( clk : IN std_logic; resend: IN std_logic; config_finished : out std_logic; siod : INOUT std_logic; sioc : OUT std_logic; reset : OUT std_logic; pwdn : OUT std_logic; xclk : OUT std_logic ); END COMPONENT; COMPONENT frame_buffer PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(18 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0); clkb : IN STD_LOGIC; addrb : IN STD_LOGIC_VECTOR(18 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) ); END COMPONENT; COMPONENT ov7670_capture PORT( pclk : IN std_logic; vsync : IN std_logic; href : IN std_logic; d : IN std_logic_vector(7 downto 0); addr : OUT std_logic_vector(18 downto 0); dout : OUT std_logic_vector(11 downto 0); we : OUT std_logic ); END COMPONENT; COMPONENT vga PORT( clk25 : IN std_logic; vga_red : OUT std_logic_vector(3 downto 0); vga_green : OUT std_logic_vector(3 downto 0); vga_blue : OUT std_logic_vector(3 downto 0); vga_hsync : OUT std_logic; vga_vsync : OUT std_logic; frame_addr : OUT std_logic_vector(18 downto 0); frame_pixel : IN std_logic_vector(11 downto 0) ); END COMPONENT; signal frame_addr : std_logic_vector(18 downto 0); signal frame_pixel : std_logic_vector(11 downto 0); signal capture_addr : std_logic_vector(18 downto 0); signal capture_data : std_logic_vector(11 downto 0); signal capture_we : std_logic_vector(0 downto 0); signal resend : std_logic; signal config_finished : std_logic; signal clk_feedback : std_logic; signal clk50u : std_logic; signal clk50 : std_logic; signal clk25u : std_logic; signal clk25 : std_logic; signal buffered_pclk : std_logic; begin btn_debounce: debounce PORT MAP( clk => clk50, i => btn, o => resend ); Inst_vga: vga PORT MAP( clk25 => clk25, vga_red => vga_red, vga_green => vga_green, vga_blue => vga_blue, vga_hsync => vga_hsync, vga_vsync => vga_vsync, frame_addr => frame_addr, frame_pixel => frame_pixel ); fb : frame_buffer PORT MAP ( clka => OV7670_PCLK, wea => capture_we, addra => capture_addr, dina => capture_data, clkb => clk50, addrb => frame_addr, doutb => frame_pixel ); led <= "0000000" & config_finished; capture: ov7670_capture PORT MAP( pclk => OV7670_PCLK, vsync => OV7670_VSYNC, href => OV7670_HREF, d => OV7670_D, addr => capture_addr, dout => capture_data, we => capture_we(0) ); controller: ov7670_controller PORT MAP( clk => clk50, sioc => ov7670_sioc, resend => resend, config_finished => config_finished, siod => ov7670_siod, pwdn => OV7670_PWDN, reset => OV7670_RESET, xclk => OV7670_XCLK ); your_instance_name : clocking port map (-- Clock in ports CLK_100 => CLK100, -- Clock out ports CLK_50 => CLK50, CLK_25 => CLK25); end Behavioral;
package pkg1 is type my_int1 is range 1 to 10; type my_int2 is range 1 to 10; type my_int3 is range 1 to 10; end package; ------------------------------------------------------------------------------- package pkg2 is use work.pkg1.my_int2; -- OK function func return my_int2; end package; package body pkg2 is use work.pkg1.my_int1; -- OK constant x : my_int1 := 2; -- OK function func return my_int2 is -- OK use work.pkg1.my_int3; -- OK variable y : my_int3; -- OK begin return 0; end function; constant y : my_int3; -- Error end package body; ------------------------------------------------------------------------------- entity ent is use work.pkg1.my_int1; -- OK constant c : my_int1 := 2; -- OK end entity;
package pkg1 is type my_int1 is range 1 to 10; type my_int2 is range 1 to 10; type my_int3 is range 1 to 10; end package; ------------------------------------------------------------------------------- package pkg2 is use work.pkg1.my_int2; -- OK function func return my_int2; end package; package body pkg2 is use work.pkg1.my_int1; -- OK constant x : my_int1 := 2; -- OK function func return my_int2 is -- OK use work.pkg1.my_int3; -- OK variable y : my_int3; -- OK begin return 0; end function; constant y : my_int3; -- Error end package body; ------------------------------------------------------------------------------- entity ent is use work.pkg1.my_int1; -- OK constant c : my_int1 := 2; -- OK end entity;
package pkg1 is type my_int1 is range 1 to 10; type my_int2 is range 1 to 10; type my_int3 is range 1 to 10; end package; ------------------------------------------------------------------------------- package pkg2 is use work.pkg1.my_int2; -- OK function func return my_int2; end package; package body pkg2 is use work.pkg1.my_int1; -- OK constant x : my_int1 := 2; -- OK function func return my_int2 is -- OK use work.pkg1.my_int3; -- OK variable y : my_int3; -- OK begin return 0; end function; constant y : my_int3; -- Error end package body; ------------------------------------------------------------------------------- entity ent is use work.pkg1.my_int1; -- OK constant c : my_int1 := 2; -- OK end entity;
package pkg1 is type my_int1 is range 1 to 10; type my_int2 is range 1 to 10; type my_int3 is range 1 to 10; end package; ------------------------------------------------------------------------------- package pkg2 is use work.pkg1.my_int2; -- OK function func return my_int2; end package; package body pkg2 is use work.pkg1.my_int1; -- OK constant x : my_int1 := 2; -- OK function func return my_int2 is -- OK use work.pkg1.my_int3; -- OK variable y : my_int3; -- OK begin return 0; end function; constant y : my_int3; -- Error end package body; ------------------------------------------------------------------------------- entity ent is use work.pkg1.my_int1; -- OK constant c : my_int1 := 2; -- OK end entity;
package pkg1 is type my_int1 is range 1 to 10; type my_int2 is range 1 to 10; type my_int3 is range 1 to 10; end package; ------------------------------------------------------------------------------- package pkg2 is use work.pkg1.my_int2; -- OK function func return my_int2; end package; package body pkg2 is use work.pkg1.my_int1; -- OK constant x : my_int1 := 2; -- OK function func return my_int2 is -- OK use work.pkg1.my_int3; -- OK variable y : my_int3; -- OK begin return 0; end function; constant y : my_int3; -- Error end package body; ------------------------------------------------------------------------------- entity ent is use work.pkg1.my_int1; -- OK constant c : my_int1 := 2; -- OK end entity;
library verilog; use verilog.vl_types.all; entity finalproject_mm_interconnect_0_cmd_demux_001 is port( sink_valid : in vl_logic_vector(0 downto 0); sink_data : in vl_logic_vector(104 downto 0); sink_channel : in vl_logic_vector(5 downto 0); sink_startofpacket: in vl_logic; sink_endofpacket: in vl_logic; sink_ready : out vl_logic; src0_valid : out vl_logic; src0_data : out vl_logic_vector(104 downto 0); src0_channel : out vl_logic_vector(5 downto 0); src0_startofpacket: out vl_logic; src0_endofpacket: out vl_logic; src0_ready : in vl_logic; src1_valid : out vl_logic; src1_data : out vl_logic_vector(104 downto 0); src1_channel : out vl_logic_vector(5 downto 0); src1_startofpacket: out vl_logic; src1_endofpacket: out vl_logic; src1_ready : in vl_logic; src2_valid : out vl_logic; src2_data : out vl_logic_vector(104 downto 0); src2_channel : out vl_logic_vector(5 downto 0); src2_startofpacket: out vl_logic; src2_endofpacket: out vl_logic; src2_ready : in vl_logic; clk : in vl_logic; reset : in vl_logic ); end finalproject_mm_interconnect_0_cmd_demux_001;
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; use work.PhoenixPackage.regNport; use work.HammingPack16.all; entity FPPM is port ( clock : in std_logic; reset_in : in std_logic; -- reset geral da NoC rx : in regHamm_Nport; -- rx (sinal que indica que estou recebendo transmissao) statusHamming : in array_statusHamming; -- status (sem erro, erro corrigido, erro detectado) das 4 portas (EAST,WEST,NORTH,SOUTH) write_FaultTable : out regHamm_Nport; -- sinal para indicar escrita na tabela de falhas row_FaultTablePorts_out : out row_FaultTable_Ports -- linha a ser escrita na tabela de falhas ); end FPPM; architecture FPPM of FPPM is -- CUIDADO! Os contadores tem apenas COUNTERS_SIZE bits! constant N: integer range 1 to 31 := 8; constant M: integer range 1 to 31 := 4; constant P: integer range 1 to 31 := 30; constant COUNTER_UPDATE_TABLE: integer := 1; -- numero de flits recebidos necessarios para atualizar a tabela begin FPPM_generate: for i in 0 to (HAMM_NPORT-1) generate begin process(clock, reset_in) variable counter_write: integer range 0 to COUNTER_UPDATE_TABLE; variable reset: std_logic := '0'; variable counter_N, counter_M, counter_P: std_logic_vector((COUNTERS_SIZE-1) downto 0); variable link_status: std_logic_vector(1 downto 0) := "00"; begin if (reset_in='1') then reset := '0'; counter_N := (others=>'0'); counter_M := (others=>'0'); counter_P := (others=>'0'); write_FaultTable(i) <= '0'; row_FaultTablePorts_out(i) <= (others=>'0'); end if; if (clock'event and clock='1' and rx(i)='1') then --counter_write := counter_write + 1; case statusHamming(i) is when NE => counter_N := counter_N + 1; if (counter_N = N) then link_status := "00"; reset := '1'; end if; when EC => counter_M := counter_M + 1; if (counter_M = M) then link_status := "01"; reset := '1'; end if; when ED => counter_P := counter_P + 1; if (counter_P = P) then link_status := "10"; reset := '1'; end if; when others => null; end case; if (reset = '1') then reset := '0'; counter_N := (others=>'0'); counter_M := (others=>'0'); counter_P := (others=>'0'); end if; if (counter_write = COUNTER_UPDATE_TABLE) then --if (false) then write_FaultTable(i) <= '1'; row_FaultTablePorts_out(i) <= link_status & counter_N & counter_M & counter_P; counter_write := 0; else write_FaultTable(i) <= '0'; row_FaultTablePorts_out(i) <= (others=>'0'); end if; elsif (rx(i)='0') then write_FaultTable(i) <= '0'; row_FaultTablePorts_out(i) <= (others=>'0'); end if; end process; end generate; end FPPM;
---------------------------------------------------------------------------------- -- Company: ITESM CQ -- Engineer: Miguel Gonzalez A01203712 -- -- Create Date: 14:13:16 11/21/2015 -- Design Name: -- Module Name: Robot - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: Main Robot Module -- -- Dependencies: -- -- Revision: -- Revision 0.0.1 - File Created -- Revision 1.1.0 - Main Robot Module Implementation -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library work; use work.PKG_ROBOT_SUMO.all; entity Robot is Port ( in_sonic_1 : in STD_LOGIC; -- 0 no detecta # 1 detecta oponente enfrente in_color_1 : in STD_LOGIC; -- 0 negro normal # 1 blanco reversa in_clk : in STD_LOGIC; in_rst : in STD_LOGIC; out_action : out STD_LOGIC_VECTOR(2 downto 0)); end Robot; architecture Behavioral of Robot is --Declarar componentes -- Comp: U1_Motor Divisor de frequencia 100/1 component Freq_Div port ( in_rst : in STD_LOGIC; in_clk : in STD_LOGIC; out_time_base : out STD_LOGIC); end component; -- Comp : U1 State Register for Robot component State_Reg_Robot port ( in_clk : in STD_LOGIC; in_time_base : in STD_LOGIC; in_rst : in STD_LOGIC; in_next_state : in robot_state_values; out_pres_state : out robot_state_values); end component; -- Comp : U3 Finite State Machine component FSM_robot port ( in_pres_state : in robot_state_values; in_color_1 : in STD_LOGIC; in_sonic_1 : in STD_LOGIC; out_next_state_fsmr: out robot_state_values); end component; -- Comp : U4 Output Robot component Output_robot port ( in_pres_state : in robot_state_values; out_action : out STD_LOGIC_VECTOR(2 downto 0)); end component; -- seniales embebidas -- 1 bit signal time_base : STD_LOGIC; -- 2 o mas bits -- of types signal pres_state, next_state: robot_state_values; -- integers signal curr_state_duration : integer range 0 to ROBOT_MAX; begin -- instanciar componentes U2_1 : Freq_Div port map(in_rst, in_clk, time_base); U2_2 : State_Reg_Robot port map(in_clk, time_base, in_rst, next_state, pres_state); U2_3 : FSM_robot port map(pres_state, in_color_1, in_sonic_1, next_state); U2_4 : Output_robot port map(pres_state, out_action); end Behavioral;
-- Copyright (c) University of Florida -- -- This file is part of window_gen. -- -- window_gen is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- window_gen is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with window_gen. If not, see <http://www.gnu.org/licenses/>. -- Greg Stitt -- University of Florida -- Description: -- fifo_vr (variable read) -- This entity implements a fifo that writes a fixed (but configurable) -- number of inputs in parallel, while allowing a variable number of outputs -- to be read each cycle. -- -- The entity is useful for streams of data where upstream components always -- produce a fixed amount of data, but downstream components may need to -- read a variable amount of data. e.g., when streaming an image sequentially -- from memory into an FPGA, the memory might provide four pixels per cycle. -- If the circuit buffers each row into separate on-chip memories, then at the -- end of a row, the circuit may need to read less than four pixels if the # of -- columns is not a multiple of four. In this case, the buffer enables the -- memory to continually write four pixels per cycle, while the downstream -- circuit reads as much as needed. -- -- The size of the fifo is fixed because its main purpose is to dynamically -- read varying amounts of data from a stream. If a typical FIFO is needed for -- buffering, the user should connect that FIFO to the input of this -- entity. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.math_custom.all; ------------------------------------------------------------------------------- -- Generic Descriptions -- data_width : The width of a single element to read from the FIFO -- parallel_io : The number of parallel inputs written every cycle, which -- is also the max number of outputs that can be read each -- cycle. ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Port Descriptions (all control signals are active high) -- clk: clock -- rst: asynchronous reset -- rd : read data from the buffer (does nothing when empty is asserted) -- rd_amount : The amount of elements to read from the buffer when rd is -- asserted. Note that if rd_amount is larger than the actual -- amount of elements in the fifo, the fifo returns only what -- it has stored. e.g., If the fifo has 2 elements and rd_amount -- is 3 when rd is asserted, the fifo will output two valid -- elements and a third junk element. -- wr : write num_inputs inputs into the buffer (does nothing when -- full is asserted) -- empty : asserted when the buffer is empty (has 0 elements in fifo) -- full : asserted when there isn't room to write num_inputs inputs. -- input : num_inputs input values, concatenated into a big std_logic_vector -- output : max_outputs outputs. When rd_amount < max_outputs, the higher bits -- contains valid datas. -- count : the number of valid data_width elements in the fifo -- valid_out : individual valid bits for each output ------------------------------------------------------------------------------- entity fifo_vr is generic ( data_width : positive; parallel_io : positive; input0_at_MSB : boolean := false; output0_at_MSB : boolean := false); port ( clk : in std_logic; rst : in std_logic; rd : in std_logic; rd_amount : in std_logic_vector(bitsNeeded(parallel_io)-1 downto 0); wr : in std_logic; empty : out std_logic; full : out std_logic; input : in std_logic_vector(parallel_iodata_width-1 downto 0); output : out std_logic_vector(parallel_iodata_width-1 downto 0); count : out std_logic_vector(bitsNeeded(parallel_io)-1 downto 0); valid_out : out std_logic_vector(parallel_io-1 downto 0)); end fifo_vr; architecture DEFAULT of fifo_vr is type data_array is array (natural range <>) of std_logic_vector(data_width-1 downto 0); signal count_s : unsigned(bitsNeeded(parallel_io)-1 downto 0); signal front : integer range 0 to parallel_io-1; signal regs : data_array(0 to parallel_io2-1); signal valid_wr : std_logic; signal valid_rd : std_logic; signal full_s : std_logic; signal empty_s : std_logic; signal valid : std_logic_vector(0 to parallel_io2-1); signal valid_out_s : std_logic_vector(0 to parallel_io-1); signal inputs : data_array(0 to parallel_io-1); signal window_reset : std_logic; signal rd_amount_s : integer range 0 to parallel_io; begin -- the buffer is empty any of the valid bits in the lower half are '0' empty_s <= not valid(0); empty <= empty_s; -- the buffer is full when any of the valid bits in the upper half are -- asserted, but not when there is a valid read that resets the window full_s <= valid(parallel_io) and not (valid_rd and window_reset) and not empty_s; full <= full_s; -- check for valid rd/wr to avoid data loss valid_wr <= wr and not full_s; valid_rd <= rd and not empty_s; count <= std_logic_vector(count_s); valid_out <= valid_out_s; -- the window position is reset any time front extends past the first half window_reset <= '0' when front + rd_amount_s < parallel_io else '1'; -- devectorize the input vector into an array based on the whether or not -- the first input is at the MSB or LDB U_INPUT0_AT_MSB : if (INPUT0_AT_MSB) generate process(input) begin for i in 0 to parallel_io-1 loop inputs(i) <= input(input'length-idata_width-1 downto input'length-(i+1)data_width); end loop; end process; end generate; U_INPUT0_AT_LSB : if (INPUT0_AT_MSB = false) generate process(input) begin for i in 0 to parallel_io-1 loop inputs(i) <= input((i+1)data_width-1 downto idata_width); end loop; end process; end generate; -- calculate the number of valid bits in the output process(valid_out_s) variable temp : unsigned(bitsNeeded(parallel_io)-1 downto 0); begin -- calculate the number of valid outputs temp := (others => '0'); for i in 0 to parallel_io-1 loop if (valid_out_s(i) = '1') then temp := temp + 1; end if; end loop; count_s <= temp; end process; -- make sure rd_amount can't exceed number of valid outputs process(rd_amount, count_s) begin if (unsigned(rd_amount) > count_s) then rd_amount_s <= to_integer(unsigned(count_s)); else rd_amount_s <= to_integer(unsigned(rd_amount)); end if; end process; -- align the output with a parallel_io-element window starting at front process(regs, front, valid) variable index : integer range 0 to parallel_io2-2; begin for i in 0 to parallel_io-1 loop -- no need for mod because window gets reset to avoid extending -- past end of the buffer index := front + i; -- set the corresponding output bits for the current register if (OUTPUT0_AT_MSB) then -- the first output starts at the highest index, whereas -- the stored register values start at the lowest index output(output'length-data_widthi-1 downto output'length-data_width(i+1)) <= regs(index); -- align the output valid bits; valid_out_s(i) <= valid(index); else output((i+1)data_width-1 downto idata_width) <= regs(index); valid_out_s(parallel_io-i-1) <= valid(index); end if; end loop; end process; process(clk, rst) begin if (rst = '1') then for i in 0 to parallel_io2-1 loop regs(i) <= (others => '0'); valid(i) <= '0'; end loop; front <= 0; elsif (rising_edge(clk)) then -- during a read, slide the front of the window so the next output -- is aligned properly. if (valid_rd = '1') then if (window_reset = '0') then front <= front + rd_amount_s; else front <= front + rd_amount_s - parallel_io; end if; end if; -- check if the bottom half is empty. All parallel_io valid bits -- of each half should be the same, so only the first bit has to be -- checked if (valid(0) = '0' or (valid_rd = '1' and window_reset = '1')) then -- move the top half to the bottom. for i in 0 to parallel_io-1 loop regs(i) <= regs(i+parallel_io); valid(i) <= valid(i+parallel_io); end loop; -- reset the valid bits for the top half for i in parallel_io to parallel_io*2-1 loop valid(i) <= '0'; end loop; end if; -- write new data to the top half of buffer if (valid_wr = '1') then for i in 0 to parallel_io-1 loop regs(i+parallel_io) <= inputs(i); valid(i+parallel_io) <= '1'; end loop; end if; end if; end process; end DEFAULT;
------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00226 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 1.1.1.2 (8) -- -- DESIGN UNIT ORDERING: -- -- GENERIC_STANDARD_TYPES(ARCH00226) -- ENT00226_Test_Bench(ARCH00226_Test_Bench) -- -- REVISION HISTORY: -- -- 15-JUN-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES ; use STANDARD_TYPES.test_report, STANDARD_TYPES.switch, STANDARD_TYPES.up, STANDARD_TYPES.down, STANDARD_TYPES.toggle, STANDARD_TYPES."=" ; architecture ARCH00226 of GENERIC_STANDARD_TYPES is signal i_bit_vector_1, i_bit_vector_2 : st_bit_vector := c_st_bit_vector_1 ; signal i_string_1, i_string_2 : st_string := c_st_string_1 ; signal i_t_rec1_1, i_t_rec1_2 : st_rec1 := c_st_rec1_1 ; signal i_st_rec1_1, i_st_rec1_2 : st_rec1 := c_st_rec1_1 ; signal i_t_rec2_1, i_t_rec2_2 : st_rec2 := c_st_rec2_1 ; signal i_st_rec2_1, i_st_rec2_2 : st_rec2 := c_st_rec2_1 ; signal i_t_rec3_1, i_t_rec3_2 : st_rec3 := c_st_rec3_1 ; signal i_st_rec3_1, i_st_rec3_2 : st_rec3 := c_st_rec3_1 ; signal i_t_arr1_1, i_t_arr1_2 : st_arr1 := c_st_arr1_1 ; signal i_st_arr1_1, i_st_arr1_2 : st_arr1 := c_st_arr1_1 ; signal i_t_arr2_1, i_t_arr2_2 : st_arr2 := c_st_arr2_1 ; signal i_st_arr2_1, i_st_arr2_2 : st_arr2 := c_st_arr2_1 ; signal i_t_arr3_1, i_t_arr3_2 : st_arr3 := c_st_arr3_1 ; signal i_st_arr3_1, i_st_arr3_2 : st_arr3 := c_st_arr3_1 ; -- begin L1: block port ( i_bit_vector_1, i_bit_vector_2 : in bit_vector := c_st_bit_vector_1 ; i_string_1, i_string_2 : in string := c_st_string_1 ; i_t_rec1_1, i_t_rec1_2 : in t_rec1 := c_st_rec1_1 ; i_st_rec1_1, i_st_rec1_2 : in st_rec1 := c_st_rec1_1 ; i_t_rec2_1, i_t_rec2_2 : in t_rec2 := c_st_rec2_1 ; i_st_rec2_1, i_st_rec2_2 : in st_rec2 := c_st_rec2_1 ; i_t_rec3_1, i_t_rec3_2 : in t_rec3 := c_st_rec3_1 ; i_st_rec3_1, i_st_rec3_2 : in st_rec3 := c_st_rec3_1 ; i_t_arr1_1, i_t_arr1_2 : in t_arr1 := c_st_arr1_1 ; i_st_arr1_1, i_st_arr1_2 : in st_arr1 := c_st_arr1_1 ; i_t_arr2_1, i_t_arr2_2 : in t_arr2 := c_st_arr2_1 ; i_st_arr2_1, i_st_arr2_2 : in st_arr2 := c_st_arr2_1 ; i_t_arr3_1, i_t_arr3_2 : in t_arr3 := c_st_arr3_1 ; i_st_arr3_1, i_st_arr3_2 : in st_arr3 := c_st_arr3_1 ) ; port map ( i_bit_vector_1, i_bit_vector_2, i_string_1, i_string_2, i_t_rec1_1, i_t_rec1_2, i_st_rec1_1, i_st_rec1_2, i_t_rec2_1, i_t_rec2_2, i_st_rec2_1, i_st_rec2_2, i_t_rec3_1, i_t_rec3_2, i_st_rec3_1, i_st_rec3_2, i_t_arr1_1, i_t_arr1_2, i_st_arr1_1, i_st_arr1_2, i_t_arr2_1, i_t_arr2_2, i_st_arr2_1, i_st_arr2_2, i_t_arr3_1, i_t_arr3_2, i_st_arr3_1, i_st_arr3_2 ) ; -- begin process variable correct : boolean := true ; begin correct := correct and i_bit_vector_1 = c_st_bit_vector_1 and i_bit_vector_2 = c_st_bit_vector_1 ; correct := correct and i_string_1 = c_st_string_1 and i_string_2 = c_st_string_1 ; correct := correct and i_t_rec1_1 = c_st_rec1_1 and i_t_rec1_2 = c_st_rec1_1 ; correct := correct and i_st_rec1_1 = c_st_rec1_1 and i_st_rec1_2 = c_st_rec1_1 ; correct := correct and i_t_rec2_1 = c_st_rec2_1 and i_t_rec2_2 = c_st_rec2_1 ; correct := correct and i_st_rec2_1 = c_st_rec2_1 and i_st_rec2_2 = c_st_rec2_1 ; correct := correct and i_t_rec3_1 = c_st_rec3_1 and i_t_rec3_2 = c_st_rec3_1 ; correct := correct and i_st_rec3_1 = c_st_rec3_1 and i_st_rec3_2 = c_st_rec3_1 ; correct := correct and i_t_arr1_1 = c_st_arr1_1 and i_t_arr1_2 = c_st_arr1_1 ; correct := correct and i_st_arr1_1 = c_st_arr1_1 and i_st_arr1_2 = c_st_arr1_1 ; correct := correct and i_t_arr2_1 = c_st_arr2_1 and i_t_arr2_2 = c_st_arr2_1 ; correct := correct and i_st_arr2_1 = c_st_arr2_1 and i_st_arr2_2 = c_st_arr2_1 ; correct := correct and i_t_arr3_1 = c_st_arr3_1 and i_t_arr3_2 = c_st_arr3_1 ; correct := correct and i_st_arr3_1 = c_st_arr3_1 and i_st_arr3_2 = c_st_arr3_1 ; -- test_report ( "ENT00226" , "Associated composite in ports with generic subtypes" , correct) ; wait ; end process ; end block L1 ; end ARCH00226 ; -- entity ENT00226_Test_Bench is end ENT00226_Test_Bench ; -- architecture ARCH00226_Test_Bench of ENT00226_Test_Bench is begin L1: block component UUT end component ; -- for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00226 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00226_Test_Bench ;
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; -------------------------------------------------------- -- x^131 + x^8 + x^3 + x^2 + 1 entity serial_multiplier_131 is generic ( NUM_BITS : positive := 131 -- The order of the finite field ); port( ax : in std_logic_vector(NUM_BITS-1 downto 0); bx : in std_logic_vector(NUM_BITS-1 downto 0); cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx reset : in std_logic; clk : in std_logic; done : out std_logic ); end serial_multiplier_131; ----------------------------------------------------------- architecture behave of serial_multiplier_131 is ----------------------------------------------------------- signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers signal counter: std_logic_vector(7 downto 0); -- 8-bit counter, controling the number of iterations: m --señales para las xor de la reduccion: signal xor_1 : std_logic; signal xor_2 : std_logic; signal xor_3 : std_logic; ----------------------------------------------------------- -- States for the finite state machine ----------------------------------------------------------- type CurrentState_type is (NOTHING, END_STATE, MUL_STATE); signal CurrentState: CurrentState_type; ----------------------------------------------------------- begin ----------------------------------------------------------- -- Result of the multiplication xor_1 <= Cx_int(1) xor Cx_int(NUM_BITS-1); xor_2 <= Cx_int(2) xor Cx_int(NUM_BITS-1); xor_3 <= Cx_int(7) xor Cx_int(NUM_BITS-1); Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx to left one position ------------------------------------------------------------ -- The finite state machine, it takes m cycles to compute -- the multiplication, a counter is used to keep this count ------------------------------------------------------------ CELL_0: ENTITY work.basic_cell(behave) PORT MAP(Ax(0),Bx_int(NUM_BITS-1),Cx_int(NUM_BITS-1),clk,reset,Cx_int(0)); CELL_1: ENTITY work.basic_cell(behave) PORT MAP(Ax(1),Bx_int(NUM_BITS-1),Cx_int(0),clk,reset,Cx_int(1)); CELL_2: ENTITY work.basic_cell(behave) PORT MAP(Ax(2),Bx_int(NUM_BITS-1),xor_1,clk,reset,Cx_int(2)); CELL_3: ENTITY work.basic_cell(behave) PORT MAP(Ax(3),Bx_int(NUM_BITS-1),xor_2,clk,reset,Cx_int(3)); CELL_4: ENTITY work.basic_cell(behave) PORT MAP(Ax(4),Bx_int(NUM_BITS-1),Cx_int(3),clk,reset,Cx_int(4)); CELL_5: ENTITY work.basic_cell(behave) PORT MAP(Ax(5),Bx_int(NUM_BITS-1),Cx_int(4),clk,reset,Cx_int(5)); CELL_6: ENTITY work.basic_cell(behave) PORT MAP(Ax(6),Bx_int(NUM_BITS-1),Cx_int(5),clk,reset,Cx_int(6)); CELL_7: ENTITY work.basic_cell(behave) PORT MAP(Ax(7),Bx_int(NUM_BITS-1),Cx_int(6),clk,reset,Cx_int(7)); CELL_8: ENTITY work.basic_cell(behave) PORT MAP(Ax(8),Bx_int(NUM_BITS-1),xor_3,clk,reset,Cx_int(8)); CELL_9: ENTITY work.basic_cell(behave) PORT MAP(Ax(9),Bx_int(NUM_BITS-1),Cx_int(8),clk,reset,Cx_int(9)); CELL_10: ENTITY work.basic_cell(behave) PORT MAP(Ax(10),Bx_int(NUM_BITS-1),Cx_int(9),clk,reset,Cx_int(10)); CELL_11: ENTITY work.basic_cell(behave) PORT MAP(Ax(11),Bx_int(NUM_BITS-1),Cx_int(10),clk,reset,Cx_int(11)); CELL_12: ENTITY work.basic_cell(behave) PORT MAP(Ax(12),Bx_int(NUM_BITS-1),Cx_int(11),clk,reset,Cx_int(12)); CELL_13: ENTITY work.basic_cell(behave) PORT MAP(Ax(13),Bx_int(NUM_BITS-1),Cx_int(12),clk,reset,Cx_int(13)); CELL_14: ENTITY work.basic_cell(behave) PORT MAP(Ax(14),Bx_int(NUM_BITS-1),Cx_int(13),clk,reset,Cx_int(14)); CELL_15: ENTITY work.basic_cell(behave) PORT MAP(Ax(15),Bx_int(NUM_BITS-1),Cx_int(14),clk,reset,Cx_int(15)); CELL_16: ENTITY work.basic_cell(behave) PORT MAP(Ax(16),Bx_int(NUM_BITS-1),Cx_int(15),clk,reset,Cx_int(16)); CELL_17: ENTITY work.basic_cell(behave) PORT MAP(Ax(17),Bx_int(NUM_BITS-1),Cx_int(16),clk,reset,Cx_int(17)); CELL_18: ENTITY work.basic_cell(behave) PORT MAP(Ax(18),Bx_int(NUM_BITS-1),Cx_int(17),clk,reset,Cx_int(18)); CELL_19: ENTITY work.basic_cell(behave) PORT MAP(Ax(19),Bx_int(NUM_BITS-1),Cx_int(18),clk,reset,Cx_int(19)); CELL_20: ENTITY work.basic_cell(behave) PORT MAP(Ax(20),Bx_int(NUM_BITS-1),Cx_int(19),clk,reset,Cx_int(20)); CELL_21: ENTITY work.basic_cell(behave) PORT MAP(Ax(21),Bx_int(NUM_BITS-1),Cx_int(20),clk,reset,Cx_int(21)); CELL_22: ENTITY work.basic_cell(behave) PORT MAP(Ax(22),Bx_int(NUM_BITS-1),Cx_int(21),clk,reset,Cx_int(22)); CELL_23: ENTITY work.basic_cell(behave) PORT MAP(Ax(23),Bx_int(NUM_BITS-1),Cx_int(22),clk,reset,Cx_int(23)); CELL_24: ENTITY work.basic_cell(behave) PORT MAP(Ax(24),Bx_int(NUM_BITS-1),Cx_int(23),clk,reset,Cx_int(24)); CELL_25: ENTITY work.basic_cell(behave) PORT MAP(Ax(25),Bx_int(NUM_BITS-1),Cx_int(24),clk,reset,Cx_int(25)); CELL_26: ENTITY work.basic_cell(behave) PORT MAP(Ax(26),Bx_int(NUM_BITS-1),Cx_int(25),clk,reset,Cx_int(26)); CELL_27: ENTITY work.basic_cell(behave) PORT MAP(Ax(27),Bx_int(NUM_BITS-1),Cx_int(26),clk,reset,Cx_int(27)); CELL_28: ENTITY work.basic_cell(behave) PORT MAP(Ax(28),Bx_int(NUM_BITS-1),Cx_int(27),clk,reset,Cx_int(28)); CELL_29: ENTITY work.basic_cell(behave) PORT MAP(Ax(29),Bx_int(NUM_BITS-1),Cx_int(28),clk,reset,Cx_int(29)); CELL_30: ENTITY work.basic_cell(behave) PORT MAP(Ax(30),Bx_int(NUM_BITS-1),Cx_int(29),clk,reset,Cx_int(30)); CELL_31: ENTITY work.basic_cell(behave) PORT MAP(Ax(31),Bx_int(NUM_BITS-1),Cx_int(30),clk,reset,Cx_int(31)); CELL_32: ENTITY work.basic_cell(behave) PORT MAP(Ax(32),Bx_int(NUM_BITS-1),Cx_int(31),clk,reset,Cx_int(32)); CELL_33: ENTITY work.basic_cell(behave) PORT MAP(Ax(33),Bx_int(NUM_BITS-1),Cx_int(32),clk,reset,Cx_int(33)); CELL_34: ENTITY work.basic_cell(behave) PORT MAP(Ax(34),Bx_int(NUM_BITS-1),Cx_int(33),clk,reset,Cx_int(34)); CELL_35: ENTITY work.basic_cell(behave) PORT MAP(Ax(35),Bx_int(NUM_BITS-1),Cx_int(34),clk,reset,Cx_int(35)); CELL_36: ENTITY work.basic_cell(behave) PORT MAP(Ax(36),Bx_int(NUM_BITS-1),Cx_int(35),clk,reset,Cx_int(36)); CELL_37: ENTITY work.basic_cell(behave) PORT MAP(Ax(37),Bx_int(NUM_BITS-1),Cx_int(36),clk,reset,Cx_int(37)); CELL_38: ENTITY work.basic_cell(behave) PORT MAP(Ax(38),Bx_int(NUM_BITS-1),Cx_int(37),clk,reset,Cx_int(38)); CELL_39: ENTITY work.basic_cell(behave) PORT MAP(Ax(39),Bx_int(NUM_BITS-1),Cx_int(38),clk,reset,Cx_int(39)); CELL_40: ENTITY work.basic_cell(behave) PORT MAP(Ax(40),Bx_int(NUM_BITS-1),Cx_int(39),clk,reset,Cx_int(40)); CELL_41: ENTITY work.basic_cell(behave) PORT MAP(Ax(41),Bx_int(NUM_BITS-1),Cx_int(40),clk,reset,Cx_int(41)); CELL_42: ENTITY work.basic_cell(behave) PORT MAP(Ax(42),Bx_int(NUM_BITS-1),Cx_int(41),clk,reset,Cx_int(42)); CELL_43: ENTITY work.basic_cell(behave) PORT MAP(Ax(43),Bx_int(NUM_BITS-1),Cx_int(42),clk,reset,Cx_int(43)); CELL_44: ENTITY work.basic_cell(behave) PORT MAP(Ax(44),Bx_int(NUM_BITS-1),Cx_int(43),clk,reset,Cx_int(44)); CELL_45: ENTITY work.basic_cell(behave) PORT MAP(Ax(45),Bx_int(NUM_BITS-1),Cx_int(44),clk,reset,Cx_int(45)); CELL_46: ENTITY work.basic_cell(behave) PORT MAP(Ax(46),Bx_int(NUM_BITS-1),Cx_int(45),clk,reset,Cx_int(46)); CELL_47: ENTITY work.basic_cell(behave) PORT MAP(Ax(47),Bx_int(NUM_BITS-1),Cx_int(46),clk,reset,Cx_int(47)); CELL_48: ENTITY work.basic_cell(behave) PORT MAP(Ax(48),Bx_int(NUM_BITS-1),Cx_int(47),clk,reset,Cx_int(48)); CELL_49: ENTITY work.basic_cell(behave) PORT MAP(Ax(49),Bx_int(NUM_BITS-1),Cx_int(48),clk,reset,Cx_int(49)); CELL_50: ENTITY work.basic_cell(behave) PORT MAP(Ax(50),Bx_int(NUM_BITS-1),Cx_int(49),clk,reset,Cx_int(50)); CELL_51: ENTITY work.basic_cell(behave) PORT MAP(Ax(51),Bx_int(NUM_BITS-1),Cx_int(50),clk,reset,Cx_int(51)); CELL_52: ENTITY work.basic_cell(behave) PORT MAP(Ax(52),Bx_int(NUM_BITS-1),Cx_int(51),clk,reset,Cx_int(52)); CELL_53: ENTITY work.basic_cell(behave) PORT MAP(Ax(53),Bx_int(NUM_BITS-1),Cx_int(52),clk,reset,Cx_int(53)); CELL_54: ENTITY work.basic_cell(behave) PORT MAP(Ax(54),Bx_int(NUM_BITS-1),Cx_int(53),clk,reset,Cx_int(54)); CELL_55: ENTITY work.basic_cell(behave) PORT MAP(Ax(55),Bx_int(NUM_BITS-1),Cx_int(54),clk,reset,Cx_int(55)); CELL_56: ENTITY work.basic_cell(behave) PORT MAP(Ax(56),Bx_int(NUM_BITS-1),Cx_int(55),clk,reset,Cx_int(56)); CELL_57: ENTITY work.basic_cell(behave) PORT MAP(Ax(57),Bx_int(NUM_BITS-1),Cx_int(56),clk,reset,Cx_int(57)); CELL_58: ENTITY work.basic_cell(behave) PORT MAP(Ax(58),Bx_int(NUM_BITS-1),Cx_int(57),clk,reset,Cx_int(58)); CELL_59: ENTITY work.basic_cell(behave) PORT MAP(Ax(59),Bx_int(NUM_BITS-1),Cx_int(58),clk,reset,Cx_int(59)); CELL_60: ENTITY work.basic_cell(behave) PORT MAP(Ax(60),Bx_int(NUM_BITS-1),Cx_int(59),clk,reset,Cx_int(60)); CELL_61: ENTITY work.basic_cell(behave) PORT MAP(Ax(61),Bx_int(NUM_BITS-1),Cx_int(60),clk,reset,Cx_int(61)); CELL_62: ENTITY work.basic_cell(behave) PORT MAP(Ax(62),Bx_int(NUM_BITS-1),Cx_int(61),clk,reset,Cx_int(62)); CELL_63: ENTITY work.basic_cell(behave) PORT MAP(Ax(63),Bx_int(NUM_BITS-1),Cx_int(62),clk,reset,Cx_int(63)); CELL_64: ENTITY work.basic_cell(behave) PORT MAP(Ax(64),Bx_int(NUM_BITS-1),Cx_int(63),clk,reset,Cx_int(64)); CELL_65: ENTITY work.basic_cell(behave) PORT MAP(Ax(65),Bx_int(NUM_BITS-1),Cx_int(64),clk,reset,Cx_int(65)); CELL_66: ENTITY work.basic_cell(behave) PORT MAP(Ax(66),Bx_int(NUM_BITS-1),Cx_int(65),clk,reset,Cx_int(66)); CELL_67: ENTITY work.basic_cell(behave) PORT MAP(Ax(67),Bx_int(NUM_BITS-1),Cx_int(66),clk,reset,Cx_int(67)); CELL_68: ENTITY work.basic_cell(behave) PORT MAP(Ax(68),Bx_int(NUM_BITS-1),Cx_int(67),clk,reset,Cx_int(68)); CELL_69: ENTITY work.basic_cell(behave) PORT MAP(Ax(69),Bx_int(NUM_BITS-1),Cx_int(68),clk,reset,Cx_int(69)); CELL_70: ENTITY work.basic_cell(behave) PORT MAP(Ax(70),Bx_int(NUM_BITS-1),Cx_int(69),clk,reset,Cx_int(70)); CELL_71: ENTITY work.basic_cell(behave) PORT MAP(Ax(71),Bx_int(NUM_BITS-1),Cx_int(70),clk,reset,Cx_int(71)); CELL_72: ENTITY work.basic_cell(behave) PORT MAP(Ax(72),Bx_int(NUM_BITS-1),Cx_int(71),clk,reset,Cx_int(72)); CELL_73: ENTITY work.basic_cell(behave) PORT MAP(Ax(73),Bx_int(NUM_BITS-1),Cx_int(72),clk,reset,Cx_int(73)); CELL_74: ENTITY work.basic_cell(behave) PORT MAP(Ax(74),Bx_int(NUM_BITS-1),Cx_int(73),clk,reset,Cx_int(74)); CELL_75: ENTITY work.basic_cell(behave) PORT MAP(Ax(75),Bx_int(NUM_BITS-1),Cx_int(74),clk,reset,Cx_int(75)); CELL_76: ENTITY work.basic_cell(behave) PORT MAP(Ax(76),Bx_int(NUM_BITS-1),Cx_int(75),clk,reset,Cx_int(76)); CELL_77: ENTITY work.basic_cell(behave) PORT MAP(Ax(77),Bx_int(NUM_BITS-1),Cx_int(76),clk,reset,Cx_int(77)); CELL_78: ENTITY work.basic_cell(behave) PORT MAP(Ax(78),Bx_int(NUM_BITS-1),Cx_int(77),clk,reset,Cx_int(78)); CELL_79: ENTITY work.basic_cell(behave) PORT MAP(Ax(79),Bx_int(NUM_BITS-1),Cx_int(78),clk,reset,Cx_int(79)); CELL_80: ENTITY work.basic_cell(behave) PORT MAP(Ax(80),Bx_int(NUM_BITS-1),Cx_int(79),clk,reset,Cx_int(80)); CELL_81: ENTITY work.basic_cell(behave) PORT MAP(Ax(81),Bx_int(NUM_BITS-1),Cx_int(80),clk,reset,Cx_int(81)); CELL_82: ENTITY work.basic_cell(behave) PORT MAP(Ax(82),Bx_int(NUM_BITS-1),Cx_int(81),clk,reset,Cx_int(82)); CELL_83: ENTITY work.basic_cell(behave) PORT MAP(Ax(83),Bx_int(NUM_BITS-1),Cx_int(82),clk,reset,Cx_int(83)); CELL_84: ENTITY work.basic_cell(behave) PORT MAP(Ax(84),Bx_int(NUM_BITS-1),Cx_int(83),clk,reset,Cx_int(84)); CELL_85: ENTITY work.basic_cell(behave) PORT MAP(Ax(85),Bx_int(NUM_BITS-1),Cx_int(84),clk,reset,Cx_int(85)); CELL_86: ENTITY work.basic_cell(behave) PORT MAP(Ax(86),Bx_int(NUM_BITS-1),Cx_int(85),clk,reset,Cx_int(86)); CELL_87: ENTITY work.basic_cell(behave) PORT MAP(Ax(87),Bx_int(NUM_BITS-1),Cx_int(86),clk,reset,Cx_int(87)); CELL_88: ENTITY work.basic_cell(behave) PORT MAP(Ax(88),Bx_int(NUM_BITS-1),Cx_int(87),clk,reset,Cx_int(88)); CELL_89: ENTITY work.basic_cell(behave) PORT MAP(Ax(89),Bx_int(NUM_BITS-1),Cx_int(88),clk,reset,Cx_int(89)); CELL_90: ENTITY work.basic_cell(behave) PORT MAP(Ax(90),Bx_int(NUM_BITS-1),Cx_int(89),clk,reset,Cx_int(90)); CELL_91: ENTITY work.basic_cell(behave) PORT MAP(Ax(91),Bx_int(NUM_BITS-1),Cx_int(90),clk,reset,Cx_int(91)); CELL_92: ENTITY work.basic_cell(behave) PORT MAP(Ax(92),Bx_int(NUM_BITS-1),Cx_int(91),clk,reset,Cx_int(92)); CELL_93: ENTITY work.basic_cell(behave) PORT MAP(Ax(93),Bx_int(NUM_BITS-1),Cx_int(92),clk,reset,Cx_int(93)); CELL_94: ENTITY work.basic_cell(behave) PORT MAP(Ax(94),Bx_int(NUM_BITS-1),Cx_int(93),clk,reset,Cx_int(94)); CELL_95: ENTITY work.basic_cell(behave) PORT MAP(Ax(95),Bx_int(NUM_BITS-1),Cx_int(94),clk,reset,Cx_int(95)); CELL_96: ENTITY work.basic_cell(behave) PORT MAP(Ax(96),Bx_int(NUM_BITS-1),Cx_int(95),clk,reset,Cx_int(96)); CELL_97: ENTITY work.basic_cell(behave) PORT MAP(Ax(97),Bx_int(NUM_BITS-1),Cx_int(96),clk,reset,Cx_int(97)); CELL_98: ENTITY work.basic_cell(behave) PORT MAP(Ax(98),Bx_int(NUM_BITS-1),Cx_int(97),clk,reset,Cx_int(98)); CELL_99: ENTITY work.basic_cell(behave) PORT MAP(Ax(99),Bx_int(NUM_BITS-1),Cx_int(98),clk,reset,Cx_int(99)); CELL_100: ENTITY work.basic_cell(behave) PORT MAP(Ax(100),Bx_int(NUM_BITS-1),Cx_int(99),clk,reset,Cx_int(100)); CELL_101: ENTITY work.basic_cell(behave) PORT MAP(Ax(101),Bx_int(NUM_BITS-1),Cx_int(100),clk,reset,Cx_int(101)); CELL_102: ENTITY work.basic_cell(behave) PORT MAP(Ax(102),Bx_int(NUM_BITS-1),Cx_int(101),clk,reset,Cx_int(102)); CELL_103: ENTITY work.basic_cell(behave) PORT MAP(Ax(103),Bx_int(NUM_BITS-1),Cx_int(102),clk,reset,Cx_int(103)); CELL_104: ENTITY work.basic_cell(behave) PORT MAP(Ax(104),Bx_int(NUM_BITS-1),Cx_int(103),clk,reset,Cx_int(104)); CELL_105: ENTITY work.basic_cell(behave) PORT MAP(Ax(105),Bx_int(NUM_BITS-1),Cx_int(104),clk,reset,Cx_int(105)); CELL_106: ENTITY work.basic_cell(behave) PORT MAP(Ax(106),Bx_int(NUM_BITS-1),Cx_int(105),clk,reset,Cx_int(106)); CELL_107: ENTITY work.basic_cell(behave) PORT MAP(Ax(107),Bx_int(NUM_BITS-1),Cx_int(106),clk,reset,Cx_int(107)); CELL_108: ENTITY work.basic_cell(behave) PORT MAP(Ax(108),Bx_int(NUM_BITS-1),Cx_int(107),clk,reset,Cx_int(108)); CELL_109: ENTITY work.basic_cell(behave) PORT MAP(Ax(109),Bx_int(NUM_BITS-1),Cx_int(108),clk,reset,Cx_int(109)); CELL_110: ENTITY work.basic_cell(behave) PORT MAP(Ax(110),Bx_int(NUM_BITS-1),Cx_int(109),clk,reset,Cx_int(110)); CELL_111: ENTITY work.basic_cell(behave) PORT MAP(Ax(111),Bx_int(NUM_BITS-1),Cx_int(110),clk,reset,Cx_int(111)); CELL_112: ENTITY work.basic_cell(behave) PORT MAP(Ax(112),Bx_int(NUM_BITS-1),Cx_int(111),clk,reset,Cx_int(112)); CELL_113: ENTITY work.basic_cell(behave) PORT MAP(Ax(113),Bx_int(NUM_BITS-1),Cx_int(112),clk,reset,Cx_int(113)); CELL_114: ENTITY work.basic_cell(behave) PORT MAP(Ax(114),Bx_int(NUM_BITS-1),Cx_int(113),clk,reset,Cx_int(114)); CELL_115: ENTITY work.basic_cell(behave) PORT MAP(Ax(115),Bx_int(NUM_BITS-1),Cx_int(114),clk,reset,Cx_int(115)); CELL_116: ENTITY work.basic_cell(behave) PORT MAP(Ax(116),Bx_int(NUM_BITS-1),Cx_int(115),clk,reset,Cx_int(116)); CELL_117: ENTITY work.basic_cell(behave) PORT MAP(Ax(117),Bx_int(NUM_BITS-1),Cx_int(116),clk,reset,Cx_int(117)); CELL_118: ENTITY work.basic_cell(behave) PORT MAP(Ax(118),Bx_int(NUM_BITS-1),Cx_int(117),clk,reset,Cx_int(118)); CELL_119: ENTITY work.basic_cell(behave) PORT MAP(Ax(119),Bx_int(NUM_BITS-1),Cx_int(118),clk,reset,Cx_int(119)); CELL_120: ENTITY work.basic_cell(behave) PORT MAP(Ax(120),Bx_int(NUM_BITS-1),Cx_int(119),clk,reset,Cx_int(120)); CELL_121: ENTITY work.basic_cell(behave) PORT MAP(Ax(121),Bx_int(NUM_BITS-1),Cx_int(120),clk,reset,Cx_int(121)); CELL_122: ENTITY work.basic_cell(behave) PORT MAP(Ax(122),Bx_int(NUM_BITS-1),Cx_int(121),clk,reset,Cx_int(122)); CELL_123: ENTITY work.basic_cell(behave) PORT MAP(Ax(123),Bx_int(NUM_BITS-1),Cx_int(122),clk,reset,Cx_int(123)); CELL_124: ENTITY work.basic_cell(behave) PORT MAP(Ax(124),Bx_int(NUM_BITS-1),Cx_int(123),clk,reset,Cx_int(124)); CELL_125: ENTITY work.basic_cell(behave) PORT MAP(Ax(125),Bx_int(NUM_BITS-1),Cx_int(124),clk,reset,Cx_int(125)); CELL_126: ENTITY work.basic_cell(behave) PORT MAP(Ax(126),Bx_int(NUM_BITS-1),Cx_int(125),clk,reset,Cx_int(126)); CELL_127: ENTITY work.basic_cell(behave) PORT MAP(Ax(127),Bx_int(NUM_BITS-1),Cx_int(126),clk,reset,Cx_int(127)); CELL_128: ENTITY work.basic_cell(behave) PORT MAP(Ax(128),Bx_int(NUM_BITS-1),Cx_int(127),clk,reset,Cx_int(128)); CELL_129: ENTITY work.basic_cell(behave) PORT MAP(Ax(129),Bx_int(NUM_BITS-1),Cx_int(128),clk,reset,Cx_int(129)); CELL_130: ENTITY work.basic_cell(behave) PORT MAP(Ax(130),Bx_int(NUM_BITS-1),Cx_int(129),clk,reset,Cx_int(130)); FSM_MUL: process (CLK) Begin if CLK'event and CLK = '1' then if Reset = '1' then counter <= "10000010"; -- m-1 value, in this case, it is 112, be sure to set the correct value bx_int <= bx; cx <= (others => '0'); Done <= '0'; CurrentState <= MUL_STATE; else case CurrentState is when MUL_STATE => -- processes a bit of bx counter <= counter - 1; if counter = "0000000" then -- The done signal is asserted at the same time that the result is computed. CurrentState <= END_STATE; else bx_int <= bx_shift; end if; when END_STATE => Cx <= Cx_int; Done <= '1'; CurrentState <= NOTHING; when others => null; end case; end if; end if; end process; end behave;
-- EMACS settings: -- tab-width: 2; indent-tabs-mode: t -- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel -- Patrick Lehmann -- -- Package: Project specific configuration. -- -- Description: -- ------------------------------------ -- Configuration file for a Xilinx Atlys board. -- -- -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= -- -- package my_config is -- Change these lines to setup configuration. constant MY_BOARD : string := "Atlys"; -- Digilent Atlys - Xilinx Spartan-6: XC6SLX45 constant MY_DEVICE : string := "None"; -- infer from MY_BOARD -- For internal use only constant MY_VERBOSE : boolean := FALSE; end package;
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ledController IS PORT( clk : in std_logic; rst : in std_logic; bus_addr : in std_LOGIC_VECTOR(15 downto 0); bus_dq : in STD_LOGIC_VECTOR(15 DOWNTO 0); bus_req : in std_LOGIC; bus_rw : in std_LOGIC; q : out STD_LOGIC_VECTOR(15 downto 0) ); END ledController; ARCHITECTURE behavioral OF ledController IS SIGNAL data : STD_LOGIC_VECTOR(15 DOWNTO 0) := x"0000"; BEGIN process(rst , clk) begin if(rst = '1') then data <= x"0000"; elsif(rising_edge(clk)) then if(bus_req = '1' and bus_rw = '1' and bus_addr= x"978") then data <= bus_dq; end if; q <= data; end if; end process; END behavioral;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2215.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b06x00p01n01i02215ent IS END c07s02b06x00p01n01i02215ent; ARCHITECTURE c07s02b06x00p01n01i02215arch OF c07s02b06x00p01n01i02215ent IS BEGIN TESTING: PROCESS -- All different non-numeric type declarations. -- Local declarations. variable CHARV : CHARACTER := '0'; variable k : integer; BEGIN k := NULL mod CHARV; assert FALSE report "***FAILED TEST: c07s02b06x00p01n01i02215 - Operators mod and rem are predefined for any integer type only." severity ERROR; wait; END PROCESS TESTING; END c07s02b06x00p01n01i02215arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2215.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b06x00p01n01i02215ent IS END c07s02b06x00p01n01i02215ent; ARCHITECTURE c07s02b06x00p01n01i02215arch OF c07s02b06x00p01n01i02215ent IS BEGIN TESTING: PROCESS -- All different non-numeric type declarations. -- Local declarations. variable CHARV : CHARACTER := '0'; variable k : integer; BEGIN k := NULL mod CHARV; assert FALSE report "***FAILED TEST: c07s02b06x00p01n01i02215 - Operators mod and rem are predefined for any integer type only." severity ERROR; wait; END PROCESS TESTING; END c07s02b06x00p01n01i02215arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2215.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b06x00p01n01i02215ent IS END c07s02b06x00p01n01i02215ent; ARCHITECTURE c07s02b06x00p01n01i02215arch OF c07s02b06x00p01n01i02215ent IS BEGIN TESTING: PROCESS -- All different non-numeric type declarations. -- Local declarations. variable CHARV : CHARACTER := '0'; variable k : integer; BEGIN k := NULL mod CHARV; assert FALSE report "***FAILED TEST: c07s02b06x00p01n01i02215 - Operators mod and rem are predefined for any integer type only." severity ERROR; wait; END PROCESS TESTING; END c07s02b06x00p01n01i02215arch;
-- Twofish_ecb_vt_testbench_256bits.vhd -- Copyright (C) 2006 Spyros Ninos -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this library; see the file COPYING. If not, write to: -- -- Free Software Foundation -- 59 Temple Place - Suite 330 -- Boston, MA 02111-1307, USA. -- -- description : this file is the testbench for the VARIABLE TEXT KAT of the twofish cipher with 256 bit key -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_textio.all; use ieee.std_logic_arith.all; use std.textio.all; entity vt_testbench256 is end vt_testbench256; architecture vt_encryption256_testbench_arch of vt_testbench256 is component reg128 port ( in_reg128 : in std_logic_vector(127 downto 0); out_reg128 : out std_logic_vector(127 downto 0); enable_reg128, reset_reg128, clk_reg128 : in std_logic ); end component; component twofish_keysched256 port ( odd_in_tk256, even_in_tk256 : in std_logic_vector(7 downto 0); in_key_tk256 : in std_logic_vector(255 downto 0); out_key_up_tk256, out_key_down_tk256 : out std_logic_vector(31 downto 0) ); end component; component twofish_whit_keysched256 port ( in_key_twk256 : in std_logic_vector(255 downto 0); out_K0_twk256, out_K1_twk256, out_K2_twk256, out_K3_twk256, out_K4_twk256, out_K5_twk256, out_K6_twk256, out_K7_twk256 : out std_logic_vector(31 downto 0) ); end component; component twofish_encryption_round256 port ( in1_ter256, in2_ter256, in3_ter256, in4_ter256, in_Sfirst_ter256, in_Ssecond_ter256, in_Sthird_ter256, in_Sfourth_ter256, in_key_up_ter256, in_key_down_ter256 : in std_logic_vector(31 downto 0); out1_ter256, out2_ter256, out3_ter256, out4_ter256 : out std_logic_vector(31 downto 0) ); end component; component twofish_data_input port ( in_tdi : in std_logic_vector(127 downto 0); out_tdi : out std_logic_vector(127 downto 0) ); end component; component twofish_data_output port ( in_tdo : in std_logic_vector(127 downto 0); out_tdo : out std_logic_vector(127 downto 0) ); end component; component demux128 port ( in_demux128 : in std_logic_vector(127 downto 0); out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0); selection_demux128 : in std_logic ); end component; component mux128 port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0); selection_mux128 : in std_logic; out_mux128 : out std_logic_vector(127 downto 0) ); end component; component twofish_S256 port ( in_key_ts256 : in std_logic_vector(255 downto 0); out_Sfirst_ts256, out_Ssecond_ts256, out_Sthird_ts256, out_Sfourth_ts256 : out std_logic_vector(31 downto 0) ); end component; FILE input_file : text is in "twofish_ecb_vt_testvalues_256bits.txt"; FILE output_file : text is out "twofish_ecb_vt_256bits_results.txt"; -- we create the functions that transform a number to text -- transforming a signle digit to a character function digit_to_char(number : integer range 0 to 9) return character is begin case number is when 0 => return '0'; when 1 => return '1'; when 2 => return '2'; when 3 => return '3'; when 4 => return '4'; when 5 => return '5'; when 6 => return '6'; when 7 => return '7'; when 8 => return '8'; when 9 => return '9'; end case; end; -- transforming multi-digit number to text function to_text(int_number : integer range 1 to 256) return string is variable our_text : string (1 to 3) := (others => ' '); variable hundreds, tens, ones : integer range 0 to 9; begin ones := int_number mod 10; tens := ((int_number mod 100) - ones) / 10; hundreds := (int_number - (int_number mod 100)) / 100; our_text(1) := digit_to_char(hundreds); our_text(2) := digit_to_char(tens); our_text(3) := digit_to_char(ones); return our_text; end; signal odd_number, even_number : std_logic_vector(7 downto 0); signal input_data, output_data, to_encr_reg128, from_tdi_to_xors, to_output_whit_xors, from_xors_to_tdo, to_mux, to_demux, from_input_whit_xors, to_round, to_input_mux : std_logic_vector(127 downto 0) ; signal twofish_key : std_logic_vector(255 downto 0); signal key_up, key_down, Sfirst, Ssecond, Sthird, Sfourth, from_xor0, from_xor1, from_xor2, from_xor3, K0,K1,K2,K3, K4,K5,K6,K7 : std_logic_vector(31 downto 0); signal clk : std_logic := '0'; signal mux_selection : std_logic := '0'; signal demux_selection: std_logic := '0'; signal enable_encr_reg : std_logic := '0'; signal reset : std_logic := '0'; signal enable_round_reg : std_logic := '0'; -- begin the testbench arch description begin -- getting data to encrypt data_input: twofish_data_input port map ( in_tdi => input_data, out_tdi => from_tdi_to_xors ); -- producing whitening keys K0..7 the_whitening_step: twofish_whit_keysched256 port map ( in_key_twk256 => twofish_key, out_K0_twk256 => K0, out_K1_twk256 => K1, out_K2_twk256 => K2, out_K3_twk256 => K3, out_K4_twk256 => K4, out_K5_twk256 => K5, out_K6_twk256 => K6, out_K7_twk256 => K7 ); -- performing the input whitening XORs from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96); from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64); from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32); from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0); from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3; round_reg: reg128 port map ( in_reg128 => from_input_whit_xors, out_reg128 => to_input_mux, enable_reg128 => enable_round_reg, reset_reg128 => reset, clk_reg128 => clk ); input_mux: mux128 port map ( in1_mux128 => to_input_mux, in2_mux128 => to_mux, out_mux128 => to_round, selection_mux128 => mux_selection ); -- creating a round the_keysched_of_the_round: twofish_keysched256 port map ( odd_in_tk256 => odd_number, even_in_tk256 => even_number, in_key_tk256 => twofish_key, out_key_up_tk256 => key_up, out_key_down_tk256 => key_down ); producing_the_Skeys: twofish_S256 port map ( in_key_ts256 => twofish_key, out_Sfirst_ts256 => Sfirst, out_Ssecond_ts256 => Ssecond, out_Sthird_ts256 => Sthird, out_Sfourth_ts256 => Sfourth ); the_encryption_circuit: twofish_encryption_round256 port map ( in1_ter256 => to_round(127 downto 96), in2_ter256 => to_round(95 downto 64), in3_ter256 => to_round(63 downto 32), in4_ter256 => to_round(31 downto 0), in_Sfirst_ter256 => Sfirst, in_Ssecond_ter256 => Ssecond, in_Sthird_ter256 => Sthird, in_Sfourth_ter256 => Sfourth, in_key_up_ter256 => key_up, in_key_down_ter256 => key_down, out1_ter256 => to_encr_reg128(127 downto 96), out2_ter256 => to_encr_reg128(95 downto 64), out3_ter256 => to_encr_reg128(63 downto 32), out4_ter256 => to_encr_reg128(31 downto 0) ); encr_reg: reg128 port map ( in_reg128 => to_encr_reg128, out_reg128 => to_demux, enable_reg128 => enable_encr_reg, reset_reg128 => reset, clk_reg128 => clk ); output_demux: demux128 port map ( in_demux128 => to_demux, out1_demux128 => to_output_whit_xors, out2_demux128 => to_mux, selection_demux128 => demux_selection ); -- don't forget the last swap !!! from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32); from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0); from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96); from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64); taking_the_output: twofish_data_output port map ( in_tdo => from_xors_to_tdo, out_tdo => output_data ); -- we create the clock clk <= not clk after 50 ns; -- period 100 ns vt_proc: process variable pt_f, -- plaintext from file ct_f : line; -- ciphertext from file variable pt_v, -- plaintext vector ct_v : std_logic_vector(127 downto 0); -- ciphertext vector variable counter : integer range 1 to 257 := 1; -- counts the encryptions variable round : integer range 1 to 16 := 1; -- holds the rounds of encryption begin -- key stays fixed to zero twofish_key <= (others => '0'); while not endfile(input_file) loop readline(input_file, pt_f); readline(input_file,ct_f); hread(pt_f,pt_v); hread(ct_f,ct_v); input_data <= pt_v; wait for 25 ns; reset <= '1'; wait for 50 ns; reset <= '0'; mux_selection <= '0'; demux_selection <= '1'; enable_encr_reg <= '0'; enable_round_reg <= '0'; wait for 50 ns; enable_round_reg <= '1'; wait for 50 ns; enable_round_reg <= '0'; -- the first round even_number <= "00001000"; -- 8 odd_number <= "00001001"; -- 9 wait for 50 ns; enable_encr_reg <= '1'; wait for 50 ns; enable_encr_reg <= '0'; demux_selection <= '1'; mux_selection <= '1'; -- the rest 15 rounds for round in 1 to 15 loop even_number <= conv_std_logic_vector(((round2)+8), 8); odd_number <= conv_std_logic_vector(((round2)+9), 8); wait for 50 ns; enable_encr_reg <= '1'; wait for 50 ns; enable_encr_reg <= '0'; end loop; -- taking final results demux_selection <= '0'; wait for 25 ns; assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure; assert (ct_v /= output_data) report "Encryption I=" & to_text(counter) &" OK" severity note; counter := counter+1; hwrite(ct_f,output_data); hwrite(pt_f,pt_v); writeline(output_file,pt_f); writeline(output_file,ct_f); end loop; assert false report "*** Variable Text Known Answer Test with 256 bits key size ended succesfully! :) ***" severity failure; end process vt_proc; end vt_encryption256_testbench_arch;
--*************************************************************************** -- @Copyright All rights reserved. -- Module name : frontend -- Call by : -- Description : -- IC : -- Version : 1.0 -- Note: : -- Author : QIU Weibao -- Date : 2013.08.06 -- Update : -- -- --*************************************************************************** library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity frontend is port ( I_reset_n : in std_logic; I_sys_clk : in std_logic; I_scan_trig : in std_logic; --scan triger I_reg_csr : in std_logic_vector(31 downto 0); --ADC I_adc_d : in std_logic_vector(11 downto 0); I_adc_or : in std_logic; I_f2pc_full : in std_logic; O_pixel_symbol : out std_logic; O_pixel_en : out std_logic; O_pixel_data : out std_logic_vector(15 downto 0); O_pulse_trig : out std_logic; O_shake_start : out std_logic ); end frontend; architecture rtl of frontend is --component fir_band_pass is --PORT --( -- clk : IN STD_LOGIC; -- reset_n : IN STD_LOGIC; -- ast_sink_data : IN STD_LOGIC_VECTOR (11 DOWNTO 0); -- ast_sink_valid : IN STD_LOGIC; -- ast_source_ready: IN STD_LOGIC; -- ast_sink_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0); -- ast_source_data : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); -- ast_sink_ready : OUT STD_LOGIC; -- ast_source_valid: OUT STD_LOGIC; -- ast_source_error: OUT STD_LOGIC_VECTOR (1 DOWNTO 0) --); --end component; component analytic_filter_h_a1 is -- component hilbert tansform generic( input_data_width : integer := 16; output_data_width : integer := 16; filter_delay_in_clks : integer := 7 --delay of hilbert filter (including pipeline delay) ); port( clk_i : in std_logic; rst_i : in std_logic; --high level reset data_str_i : in std_logic; --hilbert tranform enable data_i : in std_logic_vector(input_data_width-1 downto 0); data_i_o : out std_logic_vector(output_data_width-1 downto 0); data_q_o : out std_logic_vector(output_data_width-1 downto 0); data_str_o : out std_logic ); end component; component r2p_corproc port( clk : in std_logic; ena : in std_logic; Xin : in STD_LOGIC_VECTOR(15 downto 0); Yin : in STD_LOGIC_VECTOR(15 downto 0); Rout : out STD_LOGIC_VECTOR(19 downto 0); Aout : out STD_LOGIC_VECTOR(19 downto 0) ); end component; --constant C_FILTER_DELAY : integer := 17; --filter delay 15, adc buffer 2 constant C_CORDIC_DELAY : integer := 1000;--20; signal s_scan_trig : std_logic:='0'; signal s_work_start : std_logic; signal S_fir_sink_valid : std_logic; --filter input data valid signal S_fir_sink_ready : std_logic; --filter is able to accept data signal S_fir_source_valid : std_logic; --assert by fir filter when there is valid data to output signal S_fir_source_error : std_logic_vector(1 downto 0); --"00" no error signal S_fir_source_data : std_logic_vector(15 downto 0); --filter output data signal S_hilbert_reset : std_logic; --high level reset signal S_hilbert_data_str_i : std_logic; signal S_hilbert_data_io : std_logic_vector(15 downto 0); signal S_hilbert_data_qo : std_logic_vector(15 downto 0); signal S_hilbert_data_str_o : std_logic; signal S_cordic_rout : std_logic_vector(19 downto 0):=x"00000"; signal S_cordic_aout : std_logic_vector(19 downto 0); signal S_ad_buf : std_logic_vector(11 downto 0); signal S_ocnt : std_logic_vector(19 downto 0):="00000000000000000000"; signal S_state : std_logic_vector(2 downto 0); signal s_oen : std_logic; signal s_den : std_logic; signal s_scan_start : std_logic; signal S_scan_state : std_logic_vector(1 downto 0); signal s_work_start_buf : std_logic; signal S_line_num : std_logic_vector(9 downto 0); constant C_line_delay : integer := 17000;--4700;--181250;--40000; signal S_line_delay : std_logic_vector(19 downto 0):="00000000000000000000"; signal S_hilbert_data_i_0 : std_logic_vector(15 downto 0); signal S_hilbert_data_i_1 : std_logic_vector(15 downto 0); signal S_hilbert_data_i : std_logic_vector(15 downto 0); signal S_hilbert_data_i_temp : std_logic_vector(15 downto 0); signal S_pulse_trig : std_logic; signal S_data_type : std_logic_vector(1 downto 0); signal S_delay_cnt : std_logic_vector(20 downto 0); begin s_work_start <= '1';--I_reg_csr(0); S_hilbert_data_i_temp <= I_adc_d(11) & I_adc_d(11) & I_adc_d(11) & I_adc_d(11) & I_adc_d; O_pixel_symbol <= s_den; O_pixel_data <= S_hilbert_data_i; -- 将AD9230采集到的数据未经任何处理，直接上传上位机。 O_pixel_en <= s_oen; O_pulse_trig <= S_pulse_trig; --------------------RF DATA-------------------- S_data_type <= "01";--I_reg_csr(5 downto 4); process(I_sys_clk, I_reset_n) -- 打拍，把AD9230的数据读进来。 begin if (I_reset_n='0') then S_hilbert_data_i_0 <= (others=>'0'); S_hilbert_data_i_1 <= (others=>'0'); S_hilbert_data_i <= (others=>'0'); elsif(I_sys_clk'event and I_sys_clk='1') then S_hilbert_data_i_0 <= S_hilbert_data_i_temp; S_hilbert_data_i_1 <= S_hilbert_data_i_0; S_hilbert_data_i <= S_hilbert_data_i_1; end if; end process; process(I_sys_clk,I_reset_n) begin if (I_reset_n = '0') then S_state <= (others=>'0'); S_ocnt <= (others=>'0'); s_oen <= '0'; s_den <= '0'; S_pulse_trig <= '0'; S_hilbert_reset <= '1'; S_hilbert_data_str_i <= '0'; S_delay_cnt <= (others=>'0'); S_line_num <= (others => '0'); S_line_delay <= (others => '0'); elsif rising_edge(I_sys_clk) then s_work_start_buf <= s_work_start; s_scan_trig <= I_scan_trig; S_hilbert_data_str_i <= '1'; S_hilbert_reset <= '0'; case S_state is when "000" => -- 等待开始。 if (s_scan_trig = '0' and I_scan_trig = '1' and s_work_start_buf = '1')then S_state <= "001"; s_oen <= '1'; S_line_num <= (others => '0'); S_line_delay <= (others => '0'); else S_ocnt <= (others=>'0'); s_oen <= '0'; s_den <= '0'; S_line_num <= (others => '0'); S_line_delay <= (others => '0'); S_pulse_trig <= '0'; end if; when "001" => if S_delay_cnt >= 1000 then -- 丢掉测试前的1000个点，此处没特殊意义，调试遗留，不影响使用，可删除。 S_state <= "010"; S_delay_cnt <= (others=>'0'); else S_delay_cnt <= S_delay_cnt +1; end if; when "010" => S_pulse_trig <= '1'; -- 超声发射使能有效，开始超声激励。 --start trans-- S_delay_cnt <= (others=>'0'); if (S_ocnt >= C_CORDIC_DELAY) then -- 每条线丢掉前1000个点，因为离表面太近，数据不参与计算。 --recive delay time-- S_state <= "011"; s_den <= '1'; -- start receive -- S_ocnt <= (others=>'0'); else S_ocnt <= S_ocnt + 1; end if; when "011" => if (S_ocnt >= 4095) then -- 每条线采集4096点 S_state <= "100"; S_ocnt <= (others=>'0'); s_den <= '0'; -- stop receive-- S_line_num <= S_line_num + 1; S_pulse_trig <= '0'; -- stop trans --- else S_ocnt <= S_ocnt + 1; end if; S_line_delay <= S_line_delay + 1; when "100" => if S_line_num > 299 then -- 采集300条线 S_state <= "101"; else if S_line_delay > C_line_delay then S_state <= "010"; S_line_delay <= (others => '0'); else S_line_delay <= S_line_delay + 1; end if; end if; when "101" => S_state <= (others=>'0'); S_ocnt <= (others=>'0'); s_oen <= '0'; s_den <= '0'; S_pulse_trig <= '0'; S_line_num <= (others => '0'); when others=> S_state <= (others=>'0'); S_ocnt <= (others=>'0'); s_oen <= '0'; s_den <= '0'; S_pulse_trig <= '0'; S_line_num <= (others => '0'); end case ; end if; if S_line_num > 33 then -- 在采集第33条线时，电磁铁开始振动，此数值需结合算法修改，不能随意变动。 O_shake_start <= '1'; else O_shake_start <= '0'; end if; end process; U2_analytic_filter_h_a1_inst:analytic_filter_h_a1 -- 未使用 generic map( input_data_width => 16, output_data_width => 16, filter_delay_in_clks => 7 --delay of hilbert filter (including pipeline delay) ) port map( clk_i => I_sys_clk,--I_sys_clk, rst_i => S_hilbert_reset, --high reset data_str_i => S_hilbert_data_str_i, data_i => S_hilbert_data_i,--S_fir_source_data, data_i_o => S_hilbert_data_io, data_q_o => S_hilbert_data_qo, data_str_o => S_hilbert_data_str_o -- delay 7 clock than data_str_i ); U6_r2p_corproc_inst:r2p_corproc -- 未使用 port map ( clk => I_sys_clk,--I_sys_clk, ena => '1', Xin => S_hilbert_data_io, Yin => S_hilbert_data_qo, Rout => S_cordic_rout, Aout => S_cordic_aout ); -- end rtl;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use std.textio.all; use ieee.std_logic_textio.all; -- Instruction memory for DLX -- Memory filled by a process which reads from a file -- file name is "test.asm.mem" entity IRAM is generic ( RAM_DEPTH : integer := 48; I_SIZE : integer := 32 ); port ( Rst : in std_logic; Addr : in std_logic_vector(I_SIZE - 1 downto 0); Dout : out std_logic_vector(I_SIZE - 1 downto 0) ); end IRAM; architecture IRam_Bhe of IRAM is type RAMtype is array (0 to RAM_DEPTH - 1) of integer;-- std_logic_vector(I_SIZE - 1 downto 0); signal IRAM_mem : RAMtype; begin -- IRam_Bhe Dout <= conv_std_logic_vector(IRAM_mem(conv_integer(unsigned(Addr))),I_SIZE); -- purpose: This process is in charge of filling the Instruction RAM with the firmware -- type : combinational -- inputs : Rst -- outputs: IRAM_mem FILL_MEM_P: process (Rst) file mem_fp: text; variable file_line : line; variable index : integer := 0; variable tmp_data_u : std_logic_vector(I_SIZE-1 downto 0); begin -- process FILL_MEM_P if (Rst = '0') then file_open(mem_fp,"test.asm.mem",READ_MODE); while (not endfile(mem_fp)) loop readline(mem_fp,file_line); hread(file_line,tmp_data_u); IRAM_mem(index) <= conv_integer(unsigned(tmp_data_u)); index := index + 1; end loop; end if; end process FILL_MEM_P; end IRam_Bhe;
package rectype is type r1 is record x : integer; end record; end package; entity e is end entity; use work.rectype.all; architecture a of e is type r2 is record x : r1; end record; signal s : r2; begin p1: process is type r3 is record x : r2; end record; variable v : r3; begin v.x := s; wait; end process; end architecture;
------------------------------------------------------------------------------- -- Title : Clock -- Project : ------------------------------------------------------------------------------- -- File : bcdtime.vhd -- Author : Daniel Sun <[email protected]> -- Company : -- Created : 2016-05-04 -- Last update: 2016-08-22 -- Platform : -- Standard : VHDL'93 ------------------------------------------------------------------------------- -- Description: BCD Time counters ms resolution ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-05-04 1.0 dcsun88osh Created ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_ARITH.ALL; library work; use work.types_pkg.all; entity bcdtime is port ( rst_n : in std_logic; clk : in std_logic; tsc_1pps : in std_logic; tsc_1ppms : in std_logic; set : in std_logic; set_time : in time_ty; cur_time : out time_ty ); end bcdtime; architecture rtl of bcdtime is SIGNAL dig_1ms : std_logic_vector(3 downto 0); SIGNAL dig_10ms : std_logic_vector(3 downto 0); SIGNAL dig_100ms : std_logic_vector(3 downto 0); SIGNAL dig_1s : std_logic_vector(3 downto 0); SIGNAL dig_10s : std_logic_vector(3 downto 0); SIGNAL dig_1m : std_logic_vector(3 downto 0); SIGNAL dig_10m : std_logic_vector(3 downto 0); SIGNAL dig_1h : std_logic_vector(3 downto 0); SIGNAL dig_10h : std_logic_vector(3 downto 0); signal ms_carry : std_logic; signal s_carry : std_logic; signal m_carry : std_logic; signal h_carry : std_logic; signal sync_time : std_logic; begin -- Set latch time_set: process (rst_n, clk) is begin if (rst_n = '0') then sync_time <= '0'; elsif (clk'event and clk = '1') then if (set = '1') then sync_time <= '1'; elsif (tsc_1pps = '1') then sync_time <= '0'; end if; end if; end process; -- Clock ms counters 0-999 time_ms: process (rst_n, clk) is begin if (rst_n = '0') then dig_1ms <= (others => '0'); dig_10ms <= (others => '0'); dig_100ms <= (others => '0'); ms_carry <= '0'; elsif (clk'event and clk = '1') then if (sync_time = '1' and tsc_1pps = '1') then dig_1ms <= (others => '0'); dig_1ms(1) <= '1'; -- Set 2ms ahead for display pipe delay dig_10ms <= (others => '0'); dig_100ms <= (others => '0'); ms_carry <= '0'; elsif (tsc_1ppms = '1') then if (dig_1ms = 9) then dig_1ms <= (others => '0'); else dig_1ms <= dig_1ms + 1; end if; if (dig_1ms = 9) then if (dig_10ms = 9) then dig_10ms <= (others => '0'); else dig_10ms <= dig_10ms + 1; end if; end if; if (dig_1ms = 9 and dig_10ms = 9) then if (dig_100ms = 9) then dig_100ms <= (others => '0'); else dig_100ms <= dig_100ms + 1; end if; end if; if (dig_1ms = 8 and dig_10ms = 9 and dig_100ms = 9) then ms_carry <= '1'; else ms_carry <= '0'; end if; end if; end if; end process; -- Clock second counters 0 - 59 time_s: process (rst_n, clk) is begin if (rst_n = '0') then dig_1s <= (others => '0'); dig_10s <= (others => '0'); s_carry <= '0'; elsif (clk'event and clk = '1') then if (sync_time = '1' and tsc_1pps = '1') then dig_1s <= set_time.t_1s; dig_10s <= set_time.t_10s; s_carry <= '0'; elsif (tsc_1ppms = '1' and ms_carry = '1') then if (dig_1s = 9) then dig_1s <= (others => '0'); else dig_1s <= dig_1s + 1; end if; if (dig_1s = 9) then if (dig_10s = 5) then dig_10s <= (others => '0'); else dig_10s <= dig_10s + 1; end if; end if; if (dig_1s = 8 and dig_10s = 5) then s_carry <= '1'; else s_carry <= '0'; end if; end if; end if; end process; -- Clock minute counters 0 - 59 time_m: process (rst_n, clk) is begin if (rst_n = '0') then dig_1m <= (others => '0'); dig_10m <= (others => '0'); m_carry <= '0'; elsif (clk'event and clk = '1') then if (sync_time = '1' and tsc_1pps = '1') then dig_1m <= set_time.t_1m; dig_10m <= set_time.t_10m; m_carry <= '0'; elsif (tsc_1ppms = '1' and s_carry = '1' and ms_carry ='1') then if (dig_1m = 9) then dig_1m <= (others => '0'); else dig_1m <= dig_1m + 1; end if; if (dig_1m = 9) then if (dig_10m = 5) then dig_10m <= (others => '0'); else dig_10m <= dig_10m + 1; end if; end if; if (dig_1m = 8 and dig_10m = 5) then m_carry <= '1'; else m_carry <= '0'; end if; end if; end if; end process; -- Clock hour counters 0 - 23 time_h: process (rst_n, clk) is begin if (rst_n = '0') then dig_1h <= (others => '0'); dig_10h <= (others => '0'); h_carry <= '0'; elsif (clk'event and clk = '1') then if (sync_time = '1' and tsc_1pps = '1') then dig_1h <= set_time.t_1h; dig_10h <= set_time.t_10h; h_carry <= '0'; elsif (tsc_1ppms = '1' and m_carry = '1' and s_carry = '1' and ms_carry = '1') then if (dig_1h = 9 or (dig_1h = 3 and dig_10h = 2)) then dig_1h <= (others => '0'); else dig_1h <= dig_1h + 1; end if; if (dig_1h = 9 or (dig_1h = 3 and dig_10h = 2)) then if (dig_1h = 3 and dig_10h = 2) then dig_10h <= (others => '0'); else dig_10h <= dig_10h + 1; end if; end if; if (dig_1h = 2 and dig_10h = 2) then h_carry <= '1'; else h_carry <= '0'; end if; end if; end if; end process; cur_time.t_1ms <= dig_1ms; cur_time.t_10ms <= dig_10ms; cur_time.t_100ms <= dig_100ms; cur_time.t_1s <= dig_1s; cur_time.t_10s <= dig_10s; cur_time.t_1m <= dig_1m; cur_time.t_10m <= dig_10m; cur_time.t_1h <= dig_1h; cur_time.t_10h <= dig_10h; end rtl;

------------------------------------------------------------------------------- -- axi_datamover_s2mm_realign.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_s2mm_realign.vhd -- -- Description: -- This file implements the S2MM Data Realignment module. THe S2MM direction is -- more complex than the MM2S direction since the DRE needs to be upstream from -- the Write Data Controller. This requires the S2MM DRE to be running 2 to -- 3 clocks ahead of the Write Data controller to minimize/eliminate xfer -- bubble insertion. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1_10; use axi_datamover_v5_1_10.axi_datamover_fifo; use axi_datamover_v5_1_10.axi_datamover_s2mm_dre; use axi_datamover_v5_1_10.axi_datamover_s2mm_scatter; ------------------------------------------------------------------------------- entity axi_datamover_s2mm_realign is generic ( C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0; -- Specifies if the IBTT Indeterminate BTT Module is enabled -- for use (outside of this module) C_INCLUDE_DRE : Integer range 0 to 1 := 1; -- Includes/Omits the S2MM DRE -- 0 = Omit -- 1 = Include C_DRE_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 1; -- Specifies the depth of the internal command queue fifo C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2; -- Sets the width of the DRE alignment control ports C_SUPPORT_SCATTER : Integer range 0 to 1 := 1; -- Includes/Omits the Scatter functionality -- 0 = omit -- 1 = include C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1; C_BTT_USED : Integer range 8 to 23 := 16; -- Indicates the width of the input command BTT that is actually -- used C_STREAM_DWIDTH : Integer range 8 to 1024 := 32; -- Sets the width of the Input and Output Stream Data ports C_TAG_WIDTH : Integer range 1 to 8 := 4; -- Sets the width of the input command Tag port C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 1 ; -- Sets the width of the Store and Forward Start offset ports C_FAMILY : String := "virtex7" -- specifies the target FPGA familiy ); port ( -- Clock and Reset Inputs ------------------------------------------- -- primary_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- mmap_reset : in std_logic; -- -- Reset used for the internal master logic -- --------------------------------------------------------------------- -- Write Data Controller or IBTT Indeterminate BTT I/O ------------------------- -- wdc2dre_wready : In std_logic; -- -- Write READY input from WDC or SF -- -- dre2wdc_wvalid : Out std_logic; -- -- Write VALID output to WDC or SF -- -- dre2wdc_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); -- -- Write DATA output to WDC or SF -- -- dre2wdc_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); -- -- Write DATA output to WDC or SF -- -- dre2wdc_wlast : Out std_logic; -- -- Write LAST output to WDC or SF -- -- dre2wdc_eop : Out std_logic; -- -- End of Packet indicator for the Stream input to WDC or SF -- -------------------------------------------------------------------------------- -- Starting offset output for the Store and Forward Modules ------------------- -- dre2sf_strt_offset : Out std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);-- -- Outputs the starting offset of a transfer. This is used with Store -- -- and Forward Packer/Unpacker logic -- -------------------------------------------------------------------------------- -- AXI Slave Stream In ---------------------------------------------------------- -- s2mm_strm_wready : Out Std_logic; -- -- AXI Stream READY input -- -- s2mm_strm_wvalid : In std_logic; -- -- AXI Stream VALID Output -- -- s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); -- -- AXI Stream data output -- -- s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); -- -- AXI Stream STRB output -- -- s2mm_strm_wlast : In std_logic; -- -- AXI Stream LAST output -- -------------------------------------------------------------------------------- -- Command Calculator Interface --------------------------------------------------- -- dre2mstr_cmd_ready : Out std_logic ; -- -- Indication from the DRE that the command is being -- -- accepted from the Command Calculator -- -- mstr2dre_cmd_valid : In std_logic; -- -- The next command valid indication to the DRE -- -- from the Command Calculator -- -- mstr2dre_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The next command tag -- -- mstr2dre_dre_src_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); -- -- The source (input) alignment for the DRE -- -- mstr2dre_dre_dest_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); -- -- The destinstion (output) alignment for the DRE -- -- mstr2dre_btt : In std_logic_vector(C_BTT_USED-1 downto 0); -- -- The bytes to transfer value for the input command -- -- mstr2dre_drr : In std_logic; -- -- The starting tranfer of a sequence of transfers -- -- mstr2dre_eof : In std_logic; -- -- The endiing tranfer of a sequence of transfers -- -- mstr2dre_cmd_cmplt : In std_logic; -- -- The last tranfer command of a sequence of transfers -- -- spawned from a single parent command -- -- mstr2dre_calc_error : In std_logic; -- -- Indication if the next command in the calculation pipe -- -- has a calculation error -- -- mstr2dre_strt_offset : In std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);-- -- Outputs the starting offset of a transfer. This is used with Store -- -- and Forward Packer/Unpacker logic -- ----------------------------------------------------------------------------------- -- Premature TLAST assertion error flag ----------------------------- -- dre2all_tlast_error : Out std_logic; -- -- When asserted, this indicates the DRE detected -- -- a Early/Late TLAST assertion on the incoming data stream. -- --------------------------------------------------------------------- -- DRE Halted Status ------------------------------------------------ -- dre2all_halted : Out std_logic -- -- When asserted, this indicates the DRE has satisfied -- -- all pending transfers queued by the command calculator -- -- and is halted. -- --------------------------------------------------------------------- ); end entity axi_datamover_s2mm_realign; architecture implementation of axi_datamover_s2mm_realign is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Declarations -------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_size_realign_fifo -- -- Function Description: -- Assures that the Realigner cmd fifo depth is at least 4 deep else it -- is equal to the pipe depth. -- ------------------------------------------------------------------- function funct_size_realign_fifo (pipe_depth : integer) return integer is Variable temp_fifo_depth : Integer := 4; begin If (pipe_depth < 4) Then temp_fifo_depth := 4; Else temp_fifo_depth := pipe_depth; End if; Return (temp_fifo_depth); end function funct_size_realign_fifo; -- Constant Declarations -------------------------------------------- Constant BYTE_WIDTH : integer := 8; -- bits Constant STRM_NUM_BYTE_LANES : integer := C_STREAM_DWIDTH/BYTE_WIDTH; Constant STRM_STRB_WIDTH : integer := STRM_NUM_BYTE_LANES; Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1; Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1; Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0'); Constant USE_SYNC_FIFO : integer := 0; Constant REG_FIFO_PRIM : integer := 0; Constant BRAM_FIFO_PRIM : integer := 1; Constant SRL_FIFO_PRIM : integer := 2; Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM; Constant TAG_WIDTH : integer := C_TAG_WIDTH; Constant SRC_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH; Constant DEST_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH; Constant BTT_WIDTH : integer := C_BTT_USED; Constant DRR_WIDTH : integer := 1; Constant EOF_WIDTH : integer := 1; Constant SEQUENTIAL_WIDTH : integer := 1; Constant CALC_ERR_WIDTH : integer := 1; Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH; Constant BTT_OF_ZERO : std_logic_vector(BTT_WIDTH-1 downto 0) := (others => '0'); Constant DRECTL_FIFO_DEPTH : integer := funct_size_realign_fifo(C_DRE_CNTL_FIFO_DEPTH); Constant DRECTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field SRC_ALIGN_WIDTH + -- Source align field width DEST_ALIGN_WIDTH + -- Dest align field width BTT_WIDTH + -- BTT field width DRR_WIDTH + -- DRE Re-alignment Request Flag Field EOF_WIDTH + -- EOF flag field SEQUENTIAL_WIDTH + -- Sequential command flag CALC_ERR_WIDTH + -- Calc error flag SF_OFFSET_WIDTH; -- Store and Forward Offset Constant TAG_STRT_INDEX : integer := 0; Constant SRC_ALIGN_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH; Constant DEST_ALIGN_STRT_INDEX : integer := SRC_ALIGN_STRT_INDEX + SRC_ALIGN_WIDTH; Constant BTT_STRT_INDEX : integer := DEST_ALIGN_STRT_INDEX + DEST_ALIGN_WIDTH; Constant DRR_STRT_INDEX : integer := BTT_STRT_INDEX + BTT_WIDTH; Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH; Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH; Constant CALC_ERR_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH; Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH; Constant INCLUDE_DRE : boolean := (C_INCLUDE_DRE = 1 and C_STREAM_DWIDTH <= 64 and C_STREAM_DWIDTH >= 16); Constant OMIT_DRE : boolean := not(INCLUDE_DRE); -- Type Declarations -------------------------------------------- type TYPE_CMD_CNTL_SM is ( INIT, LD_DRE_SCATTER_FIRST, CHK_POP_FIRST , LD_DRE_SCATTER_SECOND, CHK_POP_SECOND, ERROR_TRAP ); -- Signal Declarations -------------------------------------------- Signal sig_cmdcntl_sm_state : TYPE_CMD_CNTL_SM := INIT; Signal sig_cmdcntl_sm_state_ns : TYPE_CMD_CNTL_SM := INIT; signal sig_sm_ld_dre_cmd_ns : std_logic := '0'; signal sig_sm_ld_dre_cmd : std_logic := '0'; signal sig_sm_ld_scatter_cmd_ns : std_logic := '0'; signal sig_sm_ld_scatter_cmd : std_logic := '0'; signal sig_sm_pop_cmd_fifo_ns : std_logic := '0'; signal sig_sm_pop_cmd_fifo : std_logic := '0'; signal sig_cmd_fifo_data_in : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_fifo_data_out : std_logic_vector(DRECTL_FIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_fifo_wr_cmd_valid : std_logic := '0'; signal sig_fifo_wr_cmd_ready : std_logic := '0'; signal sig_curr_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_curr_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_curr_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_curr_btt_reg : std_logic_vector(BTT_WIDTH-1 downto 0) := (others => '0'); signal sig_curr_drr_reg : std_logic := '0'; signal sig_curr_eof_reg : std_logic := '0'; signal sig_curr_cmd_cmplt_reg : std_logic := '0'; signal sig_curr_calc_error_reg : std_logic := '0'; signal sig_dre_align_ready : std_logic := '0'; signal sig_dre_use_autodest : std_logic := '0'; signal sig_dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_dre_dest_align : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_dre_flush : std_logic := '0'; signal sig_dre2wdc_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0'); signal sig_dre2wdc_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0'); signal sig_dre2wdc_tlast : std_logic := '0'; signal sig_dre2wdc_tvalid : std_logic := '0'; signal sig_wdc2dre_tready : std_logic := '0'; signal sig_tlast_err0r : std_logic := '0'; signal sig_dre_halted : std_logic := '0'; signal sig_strm2scatter_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0'); signal sig_strm2scatter_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0'); signal sig_strm2scatter_tlast : std_logic := '0'; signal sig_strm2scatter_tvalid : std_logic := '0'; signal sig_scatter2strm_tready : std_logic := '0'; signal sig_scatter2dre_tstrb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0'); signal sig_scatter2dre_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0'); signal sig_scatter2dre_tlast : std_logic := '0'; signal sig_scatter2dre_tvalid : std_logic := '0'; signal sig_dre2scatter_tready : std_logic := '0'; signal sig_scatter2dre_flush : std_logic := '0'; signal sig_scatter2drc_eop : std_logic := '0'; signal sig_scatter2dre_src_align : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0'); signal sig_scatter2drc_cmd_ready : std_logic := '0'; signal sig_drc2scatter_push_cmd : std_logic; signal sig_drc2scatter_btt : std_logic_vector(BTT_WIDTH-1 downto 0); signal sig_drc2scatter_eof : std_logic; signal sig_scatter2all_tlast_error : std_logic := '0'; signal sig_need_cmd_flush : std_logic := '0'; signal sig_fifo_rd_cmd_valid : std_logic := '0'; signal sig_curr_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_ld_strt_offset : std_logic := '0'; signal sig_output_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_dre2sf_strt_offset : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0'); begin --(architecture implementation) ------------------------------------------------------------- -- Port connections -- Input Stream Attachment s2mm_strm_wready <= sig_scatter2strm_tready ; sig_strm2scatter_tvalid <= s2mm_strm_wvalid ; sig_strm2scatter_tdata <= s2mm_strm_wdata ; sig_strm2scatter_tstrb <= s2mm_strm_wstrb ; sig_strm2scatter_tlast <= s2mm_strm_wlast ; -- Write Data Controller Stream Attachment sig_wdc2dre_tready <= wdc2dre_wready ; dre2wdc_wvalid <= sig_dre2wdc_tvalid ; dre2wdc_wdata <= sig_dre2wdc_tdata ; dre2wdc_wstrb <= sig_dre2wdc_tstrb ; dre2wdc_wlast <= sig_dre2wdc_tlast ; -- Status/Error flags dre2all_tlast_error <= sig_tlast_err0r ; dre2all_halted <= sig_dre_halted ; -- Store and Forward Starting Offset Output dre2sf_strt_offset <= sig_dre2sf_strt_offset ; ------------------------------------------------------------- -- Internal logic sig_dre_halted <= sig_dre_align_ready; ------------------------------------------------------------- -- DRE Handshake signals sig_dre_src_align <= sig_curr_src_align_reg ; sig_dre_dest_align <= sig_curr_dest_align_reg; sig_dre_use_autodest <= '0'; -- not used sig_dre_flush <= '0'; -- not used ------------------------------------------------------------------------- -------- Realigner Command FIFO and controls ------------------------------------------------------------------------- -- Command Calculator Handshake sig_fifo_wr_cmd_valid <= mstr2dre_cmd_valid ; dre2mstr_cmd_ready <= sig_fifo_wr_cmd_ready; -- Format the input fifo data word sig_cmd_fifo_data_in <= mstr2dre_strt_offset & mstr2dre_calc_error & mstr2dre_cmd_cmplt & mstr2dre_eof & mstr2dre_drr & mstr2dre_btt & mstr2dre_dre_dest_align & mstr2dre_dre_src_align & mstr2dre_tag ; -- Rip the output fifo data word sig_curr_tag_reg <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX); sig_curr_src_align_reg <= sig_cmd_fifo_data_out((SRC_ALIGN_STRT_INDEX+SRC_ALIGN_WIDTH)-1 downto SRC_ALIGN_STRT_INDEX); sig_curr_dest_align_reg <= sig_cmd_fifo_data_out((DEST_ALIGN_STRT_INDEX+DEST_ALIGN_WIDTH)-1 downto DEST_ALIGN_STRT_INDEX); sig_curr_btt_reg <= sig_cmd_fifo_data_out((BTT_STRT_INDEX+BTT_WIDTH)-1 downto BTT_STRT_INDEX); sig_curr_drr_reg <= sig_cmd_fifo_data_out(DRR_STRT_INDEX); sig_curr_eof_reg <= sig_cmd_fifo_data_out(EOF_STRT_INDEX); sig_curr_cmd_cmplt_reg <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX); sig_curr_calc_error_reg <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX); sig_curr_strt_offset_reg <= sig_cmd_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto SF_OFFSET_STRT_INDEX); ------------------------------------------------------------ -- Instance: I_DRE_CNTL_FIFO -- -- Description: -- Instance for the DRE Control FIFO -- ------------------------------------------------------------ I_DRE_CNTL_FIFO : entity axi_datamover_v5_1_10.axi_datamover_fifo generic map ( C_DWIDTH => DRECTL_FIFO_WIDTH , C_DEPTH => DRECTL_FIFO_DEPTH , C_IS_ASYNC => USE_SYNC_FIFO , C_PRIM_TYPE => FIFO_PRIM_TYPE , C_FAMILY => C_FAMILY ) port map ( -- Write Clock and reset fifo_wr_reset => mmap_reset , fifo_wr_clk => primary_aclk , -- Write Side fifo_wr_tvalid => sig_fifo_wr_cmd_valid , fifo_wr_tready => sig_fifo_wr_cmd_ready , fifo_wr_tdata => sig_cmd_fifo_data_in , fifo_wr_full => open , -- Read Clock and reset fifo_async_rd_reset => mmap_reset , fifo_async_rd_clk => primary_aclk , -- Read Side fifo_rd_tvalid => sig_fifo_rd_cmd_valid , fifo_rd_tready => sig_sm_pop_cmd_fifo , fifo_rd_tdata => sig_cmd_fifo_data_out , fifo_rd_empty => open ); ------------------------------------------------------------------------- -------- DRE and Scatter Command Loader State Machine ------------------------------------------------------------------------- ------------------------------------------------------------- -- Combinational Process -- -- Label: CMDCNTL_SM_COMBINATIONAL -- -- Process Description: -- Command Controller State Machine combinational implementation -- The design is based on the premise that for every parent -- command loaded into the S2MM, the Realigner can be loaded with -- 1 or 2 commands spawned from it. The first command is used to -- align ensuing transfers (in MMap space) to a max burst address -- boundary. Then, if the parent command's BTT value is not satisfied -- after the first command completes, a second command is generated -- and loaded in the Realigner for the remaining BTT value. The -- command complete bit in the Realigner command indicates if the -- first command the final command or the second command (if needed) -- is the final command, ------------------------------------------------------------- CMDCNTL_SM_COMBINATIONAL : process (sig_cmdcntl_sm_state , sig_fifo_rd_cmd_valid , sig_dre_align_ready , sig_scatter2drc_cmd_ready , sig_need_cmd_flush , sig_curr_cmd_cmplt_reg , sig_curr_calc_error_reg ) begin -- SM Defaults sig_cmdcntl_sm_state_ns <= INIT; sig_sm_ld_dre_cmd_ns <= '0'; sig_sm_ld_scatter_cmd_ns <= '0'; sig_sm_pop_cmd_fifo_ns <= '0'; case sig_cmdcntl_sm_state is -------------------------------------------- when INIT => sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST; -------------------------------------------- when LD_DRE_SCATTER_FIRST => If (sig_fifo_rd_cmd_valid = '1' and sig_curr_calc_error_reg = '1') Then sig_cmdcntl_sm_state_ns <= ERROR_TRAP; elsif (sig_fifo_rd_cmd_valid = '1' and sig_dre_align_ready = '1' and sig_scatter2drc_cmd_ready = '1') Then sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ; sig_sm_ld_dre_cmd_ns <= '1'; sig_sm_ld_scatter_cmd_ns <= '1'; sig_sm_pop_cmd_fifo_ns <= '1'; else sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST; End if; -------------------------------------------- when CHK_POP_FIRST => If (sig_curr_cmd_cmplt_reg = '1') Then sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST; Else sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND; End if; -------------------------------------------- when LD_DRE_SCATTER_SECOND => If (sig_fifo_rd_cmd_valid = '1' and sig_curr_calc_error_reg = '1') Then sig_cmdcntl_sm_state_ns <= ERROR_TRAP; elsif (sig_fifo_rd_cmd_valid = '1' and sig_need_cmd_flush = '1') Then sig_cmdcntl_sm_state_ns <= CHK_POP_SECOND ; sig_sm_pop_cmd_fifo_ns <= '1'; elsif (sig_fifo_rd_cmd_valid = '1' and sig_dre_align_ready = '1' and sig_scatter2drc_cmd_ready = '1') Then sig_cmdcntl_sm_state_ns <= CHK_POP_FIRST ; sig_sm_ld_dre_cmd_ns <= '1'; sig_sm_ld_scatter_cmd_ns <= '1'; sig_sm_pop_cmd_fifo_ns <= '1'; else sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_SECOND; End if; -------------------------------------------- when CHK_POP_SECOND => sig_cmdcntl_sm_state_ns <= LD_DRE_SCATTER_FIRST ; -------------------------------------------- when ERROR_TRAP => sig_cmdcntl_sm_state_ns <= ERROR_TRAP ; -------------------------------------------- when others => sig_cmdcntl_sm_state_ns <= INIT; end case; end process CMDCNTL_SM_COMBINATIONAL; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: CMDCNTL_SM_REGISTERED -- -- Process Description: -- Command Controller State Machine registered implementation -- ------------------------------------------------------------- CMDCNTL_SM_REGISTERED : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_cmdcntl_sm_state <= INIT; sig_sm_ld_dre_cmd <= '0' ; sig_sm_ld_scatter_cmd <= '0' ; sig_sm_pop_cmd_fifo <= '0' ; else sig_cmdcntl_sm_state <= sig_cmdcntl_sm_state_ns ; sig_sm_ld_dre_cmd <= sig_sm_ld_dre_cmd_ns ; sig_sm_ld_scatter_cmd <= sig_sm_ld_scatter_cmd_ns ; sig_sm_pop_cmd_fifo <= sig_sm_pop_cmd_fifo_ns ; end if; end if; end process CMDCNTL_SM_REGISTERED; ------------------------------------------------------------------------- -------- DRE Instance and controls ------------------------------------------------------------------------- ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_DRE -- -- If Generate Description: -- Includes the instance for the DRE -- -- ------------------------------------------------------------ GEN_INCLUDE_DRE : if (INCLUDE_DRE) generate signal lsig_eop_reg : std_logic := '0'; signal lsig_dre_load_beat : std_logic := '0'; signal lsig_dre_tlast_output_beat : std_logic := '0'; signal lsig_set_eop : std_logic := '0'; signal lsig_tlast_err_reg1 : std_logic := '0'; signal lsig_tlast_err_reg2 : std_logic := '0'; signal lsig_push_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal lsig_pushreg_full : std_logic := '0'; signal lsig_pushreg_empty : std_logic := '0'; signal lsig_pull_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal lsig_pullreg_full : std_logic := '0'; signal lsig_pullreg_empty : std_logic := '0'; signal lsig_pull_new_offset : std_logic := '0'; signal lsig_push_new_offset : std_logic := '0'; begin ------------------------------------------------------------ -- Instance: I_S2MM_DRE_BLOCK -- -- Description: -- Instance for the S2MM Data Realignment Engine (DRE) -- ------------------------------------------------------------ I_S2MM_DRE_BLOCK : entity axi_datamover_v5_1_10.axi_datamover_s2mm_dre generic map ( C_DWIDTH => C_STREAM_DWIDTH , C_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH ) port map ( -- Clock and Reset dre_clk => primary_aclk , dre_rst => mmap_reset , -- Alignment Control (Independent from Stream Input timing) dre_align_ready => sig_dre_align_ready , dre_align_valid => sig_sm_ld_dre_cmd , dre_use_autodest => sig_dre_use_autodest , dre_src_align => sig_scatter2dre_src_align , dre_dest_align => sig_dre_dest_align , -- Flush Control (Aligned to input Stream timing) dre_flush => sig_scatter2dre_flush , -- Stream Inputs dre_in_tstrb => sig_scatter2dre_tstrb , dre_in_tdata => sig_scatter2dre_tdata , dre_in_tlast => sig_scatter2dre_tlast , dre_in_tvalid => sig_scatter2dre_tvalid , dre_in_tready => sig_dre2scatter_tready , -- Stream Outputs dre_out_tstrb => sig_dre2wdc_tstrb , dre_out_tdata => sig_dre2wdc_tdata , dre_out_tlast => sig_dre2wdc_tlast , dre_out_tvalid => sig_dre2wdc_tvalid , dre_out_tready => sig_wdc2dre_tready ); lsig_dre_load_beat <= sig_scatter2dre_tvalid and sig_dre2scatter_tready; lsig_set_eop <= sig_scatter2drc_eop and lsig_dre_load_beat ; lsig_dre_tlast_output_beat <= sig_dre2wdc_tvalid and sig_wdc2dre_tready and sig_dre2wdc_tlast; dre2wdc_eop <= lsig_dre_tlast_output_beat and lsig_eop_reg; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_EOP_REG -- -- Process Description: -- Implements a flop for holding the EOP from the Scatter -- Engine until the corresponding packet clears out of the DRE. -- THis is used to transfer the EOP marker to the DRE output -- stream without the need for the DRE to pass it through. -- ------------------------------------------------------------- IMP_EOP_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or (lsig_dre_tlast_output_beat = '1' and lsig_set_eop = '0')) then lsig_eop_reg <= '0'; elsif (lsig_set_eop = '1') then lsig_eop_reg <= '1'; else null; -- Hold current state end if; end if; end process IMP_EOP_REG; -- Delay TLAST Error by 2 clocks to compensate for DRE minimum -- delay of 2 clocks for the stream data. sig_tlast_err0r <= lsig_tlast_err_reg2; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_TLAST_ERR_DELAY -- -- Process Description: -- Implements a 2 clock delay to better align the TLAST -- error detection with the Stream output data to the WDC -- which has a minimum 2 clock delay through the DRE. -- ------------------------------------------------------------- IMP_TLAST_ERR_DELAY : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then lsig_tlast_err_reg1 <= '0'; lsig_tlast_err_reg2 <= '0'; else lsig_tlast_err_reg1 <= sig_scatter2all_tlast_error; lsig_tlast_err_reg2 <= lsig_tlast_err_reg1; end if; end if; end process IMP_TLAST_ERR_DELAY; ------------------------------------------------------------------------- -- Store and Forward Start Address Offset Registers Logic -- Push-pull register is used to to time align the starting address -- offset (ripped from the Realigner command via parsing) to DRE -- TLAST output timing. The offset output of the pull register must -- be valid on the first output databeat of the DRE to the Store and -- Forward module. ------------------------------------------------------------------------- sig_dre2sf_strt_offset <= lsig_pull_strt_offset_reg; -- lsig_push_new_offset <= sig_dre_align_ready and -- sig_gated_dre_align_valid ; lsig_push_new_offset <= sig_sm_ld_dre_cmd ; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_PUSH_STRT_OFFSET_REG -- -- Process Description: -- Implements the input register for holding the starting address -- offset sent to the external Store and Forward functions. -- ------------------------------------------------------------- IMP_PUSH_STRT_OFFSET_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then lsig_push_strt_offset_reg <= (others => '0'); lsig_pushreg_full <= '0'; lsig_pushreg_empty <= '1'; elsif (lsig_push_new_offset = '1') then lsig_push_strt_offset_reg <= sig_curr_strt_offset_reg; lsig_pushreg_full <= '1'; lsig_pushreg_empty <= '0'; elsif (lsig_pull_new_offset = '1') then lsig_push_strt_offset_reg <= (others => '0'); lsig_pushreg_full <= '0'; lsig_pushreg_empty <= '1'; else null; -- Hold Current State end if; end if; end process IMP_PUSH_STRT_OFFSET_REG; -- Pull the next offset (if one exists) into the pull register -- when the DRE outputs a TLAST. If the pull register is empty -- and the push register has an offset, then push the new value -- into the pull register. lsig_pull_new_offset <= (sig_dre2wdc_tlast and sig_dre2wdc_tvalid and sig_wdc2dre_tready) or (lsig_pushreg_full and lsig_pullreg_empty); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_PULL_STRT_OFFSET_REG -- -- Process Description: -- Implements the output register for holding the starting -- address offset sent to the Store and Forward modul's upsizer -- logic. -- ------------------------------------------------------------- IMP_PULL_STRT_OFFSET_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then lsig_pull_strt_offset_reg <= (others => '0'); lsig_pullreg_full <= '0'; lsig_pullreg_empty <= '1'; elsif (lsig_pull_new_offset = '1' and lsig_pushreg_full = '1') then lsig_pull_strt_offset_reg <= lsig_push_strt_offset_reg; lsig_pullreg_full <= '1'; lsig_pullreg_empty <= '0'; elsif (lsig_pull_new_offset = '1' and lsig_pushreg_full = '0') then lsig_pull_strt_offset_reg <= (others => '0'); lsig_pullreg_full <= '0'; lsig_pullreg_empty <= '1'; else null; -- Hold Current State end if; end if; end process IMP_PULL_STRT_OFFSET_REG; end generate GEN_INCLUDE_DRE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_OMIT_DRE -- -- If Generate Description: -- Omits the DRE from the Re-aligner. -- -- ------------------------------------------------------------ GEN_OMIT_DRE : if (OMIT_DRE) generate begin -- DRE always ready sig_dre_align_ready <= '1'; -- -- Let the Scatter engine control the Realigner command -- -- flow. -- sig_dre_align_ready <= sig_scatter2drc_cmd_ready; -- Pass through signal connections sig_dre2wdc_tstrb <= sig_scatter2dre_tstrb ; sig_dre2wdc_tdata <= sig_scatter2dre_tdata ; sig_dre2wdc_tlast <= sig_scatter2dre_tlast ; sig_dre2wdc_tvalid <= sig_scatter2dre_tvalid ; sig_dre2scatter_tready <= sig_wdc2dre_tready ; dre2wdc_eop <= sig_scatter2drc_eop ; -- Just pass TLAST Error through when no DRE is present sig_tlast_err0r <= sig_scatter2all_tlast_error; ------------------------------------------------------------------------- -------- Store and Forward Start Address Offset Register Logic ------------------------------------------------------------------------- sig_dre2sf_strt_offset <= sig_output_strt_offset_reg; sig_ld_strt_offset <= sig_sm_ld_dre_cmd; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_STRT_OFFSET_OUTPUT -- -- Process Description: -- Implements the register for holding the starting address -- offset sent to the S2MM Store and Forward module's upsizer -- logic. -- ------------------------------------------------------------- IMP_STRT_OFFSET_OUTPUT : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_output_strt_offset_reg <= (others => '0'); elsif (sig_ld_strt_offset = '1') then sig_output_strt_offset_reg <= sig_curr_strt_offset_reg; else null; -- Hold Current State end if; end if; end process IMP_STRT_OFFSET_OUTPUT; end generate GEN_OMIT_DRE; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_INCLUDE_SCATTER -- -- If Generate Description: -- This IfGen implements the Scatter function which is a pre- -- processor for the S2MM DRE. The scatter function breaks up -- a continous input stream of data into constituant parts -- as described by a set of loaded commands that together -- describe an entire input packet. -- ------------------------------------------------------------ GEN_INCLUDE_SCATTER : if (C_SUPPORT_SCATTER = 1) generate begin -- Load the Scatter Engine command when the DRE command -- is loaded -- sig_drc2scatter_push_cmd <= sig_dre_align_ready and -- sig_gated_dre_align_valid; sig_drc2scatter_push_cmd <= sig_sm_ld_scatter_cmd ; -- Assign the new Bytes to Transfer (BTT) qualifier for the -- Scatter Engine sig_drc2scatter_btt <= sig_curr_btt_reg; -- Assign the new End of Frame (EOF) qualifier for the -- Scatter Engine sig_drc2scatter_eof <= sig_curr_eof_reg; ------------------------------------------------------------ -- Instance: I_S2MM_SCATTER -- -- Description: -- Instance for the Scatter Engine. This block breaks up a -- input stream per commands loaded. -- ------------------------------------------------------------ I_S2MM_SCATTER : entity axi_datamover_v5_1_10.axi_datamover_s2mm_scatter generic map ( C_ENABLE_INDET_BTT => C_ENABLE_INDET_BTT , C_DRE_ALIGN_WIDTH => C_DRE_ALIGN_WIDTH , C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP , C_BTT_USED => BTT_WIDTH , C_STREAM_DWIDTH => C_STREAM_DWIDTH , C_FAMILY => C_FAMILY ) port map ( -- Clock input & Reset input primary_aclk => primary_aclk , mmap_reset => mmap_reset , -- DRE Realign Controller I/O ---------------------------- scatter2drc_cmd_ready => sig_scatter2drc_cmd_ready , drc2scatter_push_cmd => sig_drc2scatter_push_cmd , drc2scatter_btt => sig_drc2scatter_btt , drc2scatter_eof => sig_drc2scatter_eof , -- DRE Source Alignment ----------------------------------- scatter2drc_src_align => sig_scatter2dre_src_align , -- AXI Slave Stream In ----------------------------------- s2mm_strm_tready => sig_scatter2strm_tready , s2mm_strm_tvalid => sig_strm2scatter_tvalid , s2mm_strm_tdata => sig_strm2scatter_tdata , s2mm_strm_tstrb => sig_strm2scatter_tstrb , s2mm_strm_tlast => sig_strm2scatter_tlast , -- Stream Out to S2MM DRE --------------------------------- drc2scatter_tready => sig_dre2scatter_tready , scatter2drc_tvalid => sig_scatter2dre_tvalid , scatter2drc_tdata => sig_scatter2dre_tdata , scatter2drc_tstrb => sig_scatter2dre_tstrb , scatter2drc_tlast => sig_scatter2dre_tlast , scatter2drc_flush => sig_scatter2dre_flush , scatter2drc_eop => sig_scatter2drc_eop , -- Premature TLAST assertion error flag scatter2drc_tlast_error => sig_scatter2all_tlast_error ); end generate GEN_INCLUDE_SCATTER; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_OMIT_SCATTER -- -- If Generate Description: -- This IfGen omits the Scatter pre-processor. -- -- ------------------------------------------------------------ GEN_OMIT_SCATTER : if (C_SUPPORT_SCATTER = 0) generate begin -- Just housekeep the signaling sig_scatter2drc_cmd_ready <= '1' ; sig_scatter2drc_eop <= sig_strm2scatter_tlast ; sig_scatter2dre_src_align <= sig_dre_src_align ; sig_scatter2all_tlast_error <= '0' ; sig_scatter2dre_flush <= sig_dre_flush ; sig_scatter2dre_tstrb <= sig_strm2scatter_tstrb ; sig_scatter2dre_tdata <= sig_strm2scatter_tdata ; sig_scatter2dre_tlast <= sig_strm2scatter_tlast ; sig_scatter2dre_tvalid <= sig_strm2scatter_tvalid ; sig_scatter2strm_tready <= sig_dre2scatter_tready ; end generate GEN_OMIT_SCATTER; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_OMIT_INDET_BTT -- -- If Generate Description: -- Omit and special logic for Indeterminate BTT support. -- -- ------------------------------------------------------------ GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate begin sig_need_cmd_flush <= '0' ; -- not needed without Indeterminate BTT end generate GEN_OMIT_INDET_BTT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ENABLE_INDET_BTT -- -- If Generate Description: -- Include logic for the case when Indeterminate BTT is -- included as part of the S2MM. In this mode, the actual -- length of input stream packets is not known when the S2MM -- is loaded with a transfer command. -- ------------------------------------------------------------ GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate signal lsig_clr_cmd_flush : std_logic := '0'; signal lsig_set_cmd_flush : std_logic := '0'; signal lsig_cmd_set_fetch_pause : std_logic := '0'; signal lsig_cmd_clr_fetch_pause : std_logic := '0'; signal lsig_cmd_fetch_pause : std_logic := '0'; begin lsig_cmd_set_fetch_pause <= sig_drc2scatter_push_cmd and not(sig_curr_cmd_cmplt_reg) and not(sig_need_cmd_flush); lsig_cmd_clr_fetch_pause <= sig_scatter2dre_tvalid and sig_dre2scatter_tready and sig_scatter2dre_tlast; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CMD_FETCH_PAUSE -- -- Process Description: -- Implements the flop for the flag that causes the command -- queue manager to pause fetching the next command if the -- current command does not have the command complete bit set. -- The pause remains set until the associated TLAST for the -- command is output from the Scatter Engine. If the Tlast is -- also accompanied by a EOP and the pause is set, then the -- ensuing command (which will have the cmd cmplt bit set) must -- be flushed from the queue and not loaded into the Scatter -- Engine or DRE, This is normally associated with indeterminate -- packets that are actually shorter than the intial align to -- max burst child command sent to the Realigner, The next loaded -- child command is to finish the remainder of the indeterminate -- packet up to the full BTT value in the original parent command. -- This child command becomes stranded in the Realigner command fifo -- and has to be flushed. -- ------------------------------------------------------------- IMP_CMD_FETCH_PAUSE : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or lsig_cmd_clr_fetch_pause = '1') then lsig_cmd_fetch_pause <= '0'; elsif (lsig_cmd_set_fetch_pause = '1') then lsig_cmd_fetch_pause <= '1'; else null; -- Hold current state end if; end if; end process IMP_CMD_FETCH_PAUSE; -- Clear the flush needed flag when the command with the command -- complete marker is popped off of the command queue. lsig_clr_cmd_flush <= sig_need_cmd_flush and sig_sm_pop_cmd_fifo; -- The command queue has to be flushed if the stream EOP marker -- is transfered out of the Scatter Engine when the corresponding -- command being executed does not have the command complete -- marker set. lsig_set_cmd_flush <= lsig_cmd_fetch_pause and sig_scatter2dre_tvalid and sig_dre2scatter_tready and sig_scatter2drc_eop; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CMD_FLUSH_FLOP -- -- Process Description: -- Implements the flop for holding the command flush flag. -- This is only needed in Indeterminate BTT mode. -- ------------------------------------------------------------- IMP_CMD_FLUSH_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or lsig_clr_cmd_flush = '1') then sig_need_cmd_flush <= '0'; elsif (lsig_set_cmd_flush = '1') then sig_need_cmd_flush <= '1'; else null; -- Hold current state end if; end if; end process IMP_CMD_FLUSH_FLOP; end generate GEN_ENABLE_INDET_BTT; end implementation;

architecture RTl of FIFO is component fifo is end component fifo; -- Failures below component fifo is end component fifo; component fifo is end component fifo; begin end architecture RTL;

-- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_updt_cmdsts_if.vhd -- Description: This entity is the descriptor update command and status inteface -- for the Scatter Gather Engine AXI DataMover. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_sg_v4_1_3; use axi_sg_v4_1_3.axi_sg_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_updt_cmdsts_if is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 -- Master AXI Memory Map Address Width for Scatter Gather R/W Port ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- Update command write interface from fetch sm -- updt_cmnd_wr : in std_logic ; -- updt_cmnd_data : in std_logic_vector -- ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); -- -- -- User Command Interface Ports (AXI Stream) -- s_axis_updt_cmd_tvalid : out std_logic ; -- s_axis_updt_cmd_tready : in std_logic ; -- s_axis_updt_cmd_tdata : out std_logic_vector -- ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); -- -- -- User Status Interface Ports (AXI Stream) -- m_axis_updt_sts_tvalid : in std_logic ; -- m_axis_updt_sts_tready : out std_logic ; -- m_axis_updt_sts_tdata : in std_logic_vector(7 downto 0) ; -- m_axis_updt_sts_tkeep : in std_logic_vector(0 downto 0) ; -- -- -- Scatter Gather Fetch Status -- s2mm_err : in std_logic ; -- updt_done : out std_logic ; -- updt_error : out std_logic ; -- updt_interr : out std_logic ; -- updt_slverr : out std_logic ; -- updt_decerr : out std_logic -- ); end axi_sg_updt_cmdsts_if; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_updt_cmdsts_if is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- signal updt_slverr_i : std_logic := '0'; signal updt_decerr_i : std_logic := '0'; signal updt_interr_i : std_logic := '0'; signal s2mm_error : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin updt_slverr <= updt_slverr_i; updt_decerr <= updt_decerr_i; updt_interr <= updt_interr_i; ------------------------------------------------------------------------------- -- DataMover Command Interface ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- When command by fetch sm, drive descriptor update command to data mover. -- Hold until data mover indicates ready. ------------------------------------------------------------------------------- GEN_DATAMOVER_CMND : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then s_axis_updt_cmd_tvalid <= '0'; -- s_axis_updt_cmd_tdata <= (others => '0'); elsif(updt_cmnd_wr = '1')then s_axis_updt_cmd_tvalid <= '1'; -- s_axis_updt_cmd_tdata <= updt_cmnd_data; elsif(s_axis_updt_cmd_tready = '1')then s_axis_updt_cmd_tvalid <= '0'; -- s_axis_updt_cmd_tdata <= (others => '0'); end if; end if; end process GEN_DATAMOVER_CMND; s_axis_updt_cmd_tdata <= updt_cmnd_data; ------------------------------------------------------------------------------- -- DataMover Status Interface ------------------------------------------------------------------------------- -- Drive ready low during reset to indicate not ready REG_STS_READY : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then m_axis_updt_sts_tready <= '0'; else m_axis_updt_sts_tready <= '1'; end if; end if; end process REG_STS_READY; ------------------------------------------------------------------------------- -- Log status bits out of data mover. ------------------------------------------------------------------------------- DATAMOVER_STS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_slverr_i <= '0'; updt_decerr_i <= '0'; updt_interr_i <= '0'; -- Status valid, therefore capture status elsif(m_axis_updt_sts_tvalid = '1')then updt_slverr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT); updt_decerr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT); updt_interr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT); -- Only assert when valid else updt_slverr_i <= '0'; updt_decerr_i <= '0'; updt_interr_i <= '0'; end if; end if; end process DATAMOVER_STS; ------------------------------------------------------------------------------- -- Transfer Done ------------------------------------------------------------------------------- XFER_DONE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_done <= '0'; -- Status valid, therefore capture status elsif(m_axis_updt_sts_tvalid = '1')then updt_done <= m_axis_updt_sts_tdata(DATAMOVER_STS_CMDDONE_BIT) or m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT) or m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT) or m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT); -- Only assert when valid else updt_done <= '0'; end if; end if; end process XFER_DONE; ------------------------------------------------------------------------------- -- Register global error from data mover. ------------------------------------------------------------------------------- s2mm_error <= updt_slverr_i or updt_decerr_i or updt_interr_i; -- Log errors into a global error output UPDATE_ERROR_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_error <= '0'; elsif(s2mm_error = '1')then updt_error <= '1'; end if; end if; end process UPDATE_ERROR_PROCESS; end implementation;

-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_05_ch_05_14.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- entity ch_05_14 is end entity ch_05_14; ---------------------------------------------------------------- architecture test of ch_05_14 is signal PC, functional_next_PC, equivalent_next_PC : integer := 0; begin block_05_3_p : block is port ( next_PC : out integer ); port map ( next_PC => functional_next_PC ); begin -- code from book: PC_incr : next_PC <= PC + 4 after 5 ns; -- end of code from book end block block_05_3_p; ---------------- block_05_3_q : block is port ( next_PC : out integer ); port map ( next_PC => equivalent_next_PC ); begin -- code from book: PC_incr : process is begin next_PC <= PC + 4 after 5 ns; wait on PC; end process PC_incr; -- end of code from book end block block_05_3_q; ---------------- stimulus : process is begin for i in 1 to 10 loop PC <= i after 20 ns; wait for 20 ns; end loop; wait; end process stimulus; verifier : assert functional_next_PC = equivalent_next_PC report "Functional and equivalent models give different results"; end architecture test;

------------------------------------------------------------------------------- -- File Name : AC_ROM.vhd -- -- Project : JPEG_ENC -- -- Module : AC_ROM -- -- Content : AC_ROM Luminance -- -- Description : -- -- Spec. : -- -- Author : Michal Krepa -- ------------------------------------------------------------------------------- -- History : -- 20090228: (MK): Initial Creation. ------------------------------------------------------------------------------- -- ////////////////////////////////////////////////////////////////////////////// -- /// Copyright (c) 2013, Jahanzeb Ahmad -- /// All rights reserved. -- /// -- /// Redistribution and use in source and binary forms, with or without modification, -- /// are permitted provided that the following conditions are met: -- /// -- /// * Redistributions of source code must retain the above copyright notice, -- /// this list of conditions and the following disclaimer. -- /// * Redistributions in binary form must reproduce the above copyright notice, -- /// this list of conditions and the following disclaimer in the documentation and/or -- /// other materials provided with the distribution. -- /// -- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY -- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES -- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT -- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- /// POSSIBILITY OF SUCH DAMAGE. -- /// -- /// -- /// * http://opensource.org/licenses/MIT -- /// * http://copyfree.org/licenses/mit/license.txt -- /// -- ////////////////////////////////////////////////////////////////////////////// ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ----------------------------------- LIBRARY/PACKAGE --------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- generic packages/libraries: ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------------------------- -- user packages/libraries: ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ----------------------------------- ENTITY ------------------------------------ ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- entity AC_ROM is port ( CLK : in std_logic; RST : in std_logic; runlength : in std_logic_vector(3 downto 0); VLI_size : in std_logic_vector(3 downto 0); VLC_AC_size : out unsigned(4 downto 0); VLC_AC : out unsigned(15 downto 0) ); end entity AC_ROM; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- ----------------------------------- ARCHITECTURE ------------------------------ ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- architecture RTL of AC_ROM is signal rom_addr : std_logic_vector(7 downto 0); ------------------------------------------------------------------------------- -- Architecture: begin ------------------------------------------------------------------------------- begin rom_addr <= runlength & VLI_size; ------------------------------------------------------------------- -- AC-ROM ------------------------------------------------------------------- p_AC_ROM : process(CLK, RST) begin if RST = '1' then VLC_AC_size <= (others => '0'); VLC_AC <= (others => '0'); elsif CLK'event and CLK = '1' then case runlength is when X"0" => case VLI_size is when X"0" => VLC_AC_size <= to_unsigned(4, VLC_AC_size'length); VLC_AC <= resize("1010", VLC_AC'length); when X"1" => VLC_AC_size <= to_unsigned(2, VLC_AC_size'length); VLC_AC <= resize("00", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(2, VLC_AC_size'length); VLC_AC <= resize("01", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(3, VLC_AC_size'length); VLC_AC <= resize("100", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(4, VLC_AC_size'length); VLC_AC <= resize("1011", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(5, VLC_AC_size'length); VLC_AC <= resize("11010", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(7, VLC_AC_size'length); VLC_AC <= resize("1111000", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(8, VLC_AC_size'length); VLC_AC <= resize("11111000", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); VLC_AC <= resize("1111110110", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110000010", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110000011", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"1" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(4, VLC_AC_size'length); VLC_AC <= resize("1100", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(5, VLC_AC_size'length); VLC_AC <= resize("11011", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(7, VLC_AC_size'length); VLC_AC <= resize("1111001", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); VLC_AC <= resize("111110110", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); VLC_AC <= resize("11111110110", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110000100", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110000101", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110000110", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110000111", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001000", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"2" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(5, VLC_AC_size'length); VLC_AC <= resize("11100", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(8, VLC_AC_size'length); VLC_AC <= resize("11111001", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); VLC_AC <= resize("1111110111", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); VLC_AC <= resize("111111110100", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001001", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001010", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001011", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001100", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001101", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001110", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"3" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(6, VLC_AC_size'length); VLC_AC <= resize("111010", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); VLC_AC <= resize("111110111", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); VLC_AC <= resize("111111110101", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110001111", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010000", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010001", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010010", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010011", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010100", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010101", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"4" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(6, VLC_AC_size'length); VLC_AC <= resize("111011", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); VLC_AC <= resize("1111111000", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010110", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110010111", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011000", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011001", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011010", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011011", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011100", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011101", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"5" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(7, VLC_AC_size'length); VLC_AC <= resize("1111010", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); VLC_AC <= resize("11111110111", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011110", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110011111", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100000", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100001", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100010", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100011", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100100", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100101", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"6" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(7, VLC_AC_size'length); VLC_AC <= resize("1111011", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); VLC_AC <= resize("111111110110", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100110", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110100111", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101000", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101001", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101010", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101011", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101100", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101101", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"7" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(8, VLC_AC_size'length); VLC_AC <= resize("11111010", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(12, VLC_AC_size'length); VLC_AC <= resize("111111110111", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101110", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110101111", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110000", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110001", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110010", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110011", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110100", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110101", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"8" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); VLC_AC <= resize("111111000", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(15, VLC_AC_size'length); VLC_AC <= resize("111111111000000", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110110", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110110111", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111000", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111001", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111010", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111011", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111100", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111101", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"9" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); VLC_AC <= resize("111111001", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111110", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111110111111", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000000", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000001", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000010", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000011", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000100", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000101", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000110", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"A" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(9, VLC_AC_size'length); VLC_AC <= resize("111111010", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111000111", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001000", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001001", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001010", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001011", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001100", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001101", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001110", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111001111", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"B" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); VLC_AC <= resize("1111111001", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010000", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010001", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010010", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010011", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010100", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010101", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010110", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111010111", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011000", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"C" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(10, VLC_AC_size'length); VLC_AC <= resize("1111111010", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011001", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011010", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011011", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011100", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011101", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011110", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111011111", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100000", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100001", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"D" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); VLC_AC <= resize("11111111000", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100010", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100011", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100100", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100101", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100110", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111100111", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101000", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101001", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101010", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"E" => case VLI_size is when X"1" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101011", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101100", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101101", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101110", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111101111", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110000", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110001", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110010", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110011", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110100", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when X"F" => case VLI_size is when X"0" => VLC_AC_size <= to_unsigned(11, VLC_AC_size'length); VLC_AC <= resize("11111111001", VLC_AC'length); when X"1" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110101", VLC_AC'length); when X"2" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110110", VLC_AC'length); when X"3" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111110111", VLC_AC'length); when X"4" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111000", VLC_AC'length); when X"5" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111001", VLC_AC'length); when X"6" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111010", VLC_AC'length); when X"7" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111011", VLC_AC'length); when X"8" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111100", VLC_AC'length); when X"9" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111101", VLC_AC'length); when X"A" => VLC_AC_size <= to_unsigned(16, VLC_AC_size'length); VLC_AC <= resize("1111111111111110", VLC_AC'length); when others => VLC_AC_size <= to_unsigned(0, VLC_AC_size'length); VLC_AC <= resize("0", VLC_AC'length); end case; when others => VLC_AC_size <= (others => '0'); VLC_AC <= (others => '0'); end case; end if; end process; end architecture RTL; ------------------------------------------------------------------------------- -- Architecture: end -------------------------------------------------------------------------------

-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017 -- Date : Tue Oct 17 15:44:51 2017 -- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS -- Command : write_vhdl -force -mode synth_stub -- /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/led_controller/led_controller.srcs/sources_1/bd/led_controller_design/ip/led_controller_design_led_controller_0_0/led_controller_design_led_controller_0_0_stub.vhdl -- Design : led_controller_design_led_controller_0_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity led_controller_design_led_controller_0_0 is Port ( LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 ); s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 ); s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s00_axi_awvalid : in STD_LOGIC; s00_axi_awready : out STD_LOGIC; s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s00_axi_wvalid : in STD_LOGIC; s00_axi_wready : out STD_LOGIC; s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s00_axi_bvalid : out STD_LOGIC; s00_axi_bready : in STD_LOGIC; s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 ); s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s00_axi_arvalid : in STD_LOGIC; s00_axi_arready : out STD_LOGIC; s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s00_axi_rvalid : out STD_LOGIC; s00_axi_rready : in STD_LOGIC; s00_axi_aclk : in STD_LOGIC; s00_axi_aresetn : in STD_LOGIC ); end led_controller_design_led_controller_0_0; architecture stub of led_controller_design_led_controller_0_0 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "LEDs_out[7:0],s00_axi_awaddr[3:0],s00_axi_awprot[2:0],s00_axi_awvalid,s00_axi_awready,s00_axi_wdata[31:0],s00_axi_wstrb[3:0],s00_axi_wvalid,s00_axi_wready,s00_axi_bresp[1:0],s00_axi_bvalid,s00_axi_bready,s00_axi_araddr[3:0],s00_axi_arprot[2:0],s00_axi_arvalid,s00_axi_arready,s00_axi_rdata[31:0],s00_axi_rresp[1:0],s00_axi_rvalid,s00_axi_rready,s00_axi_aclk,s00_axi_aresetn"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "led_controller_v1_0,Vivado 2017.3"; begin end;

-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_05_tb_05_07.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $ -- $Revision: 1.1.1.1 $ -- -- --------------------------------------------------------------------- architecture functional of S_R_flipflop is begin q <= '1' when s = '1' else '0' when r = '1'; q_n <= '0' when s = '1' else '1' when r = '1'; end architecture functional; entity tb_05_07 is end entity tb_05_07; architecture test of tb_05_07 is signal s, r : bit := '0'; signal q, q_n : bit; begin dut : entity work.S_R_flipflop(functional) port map ( s => s, r => r, q => q, q_n => q_n ); stimulus : process is begin wait for 10 ns; s <= '1'; wait for 10 ns; s <= '0'; wait for 10 ns; r <= '1'; wait for 10 ns; r <= '0'; wait for 10 ns; s <= '1'; wait for 10 ns; r <= '1'; wait for 10 ns; s <= '0'; wait for 10 ns; r <= '0'; wait for 10 ns; wait; end process stimulus; end architecture test;

------------------------------------------------------------------------------- -- axi_datamover_wr_status_cntl.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_wr_status_cntl.vhd -- -- Description: -- This file implements the DataMover Master Write Status Controller. -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_datamover_wr_status_cntl.vhd -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- -- History: -- DET 04/19/2011 Initial Version for EDK 13.3 -- -- DET 7/11/2011 Initial Version for EDK 13.3 -- ~~~~~~ -- -- Per CR616212 -- - Changed logic to force a coesc register push when a TLAST error is -- reported by the Write Data Controller. -- ^^^^^^ -- -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1; use axi_datamover_v5_1.axi_datamover_fifo; ------------------------------------------------------------------------------- entity axi_datamover_wr_status_cntl is generic ( C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0; -- Specifies if the Indeterminate BTT Module is enabled -- for use (outside of this module) C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1; -- Sets the width of the data2wsc_bytes_rcvd port used for -- relaying the actual number of bytes received when Idet BTT is -- enabled (C_ENABLE_INDET_BTT = 1) C_STS_FIFO_DEPTH : Integer range 1 to 32 := 8; -- Specifies the depth of the internal status queue fifo C_STS_WIDTH : Integer range 8 to 32 := 8; -- sets the width of the Status ports C_TAG_WIDTH : Integer range 1 to 8 := 4; -- Sets the width of the Tag field in the Status reply C_FAMILY : String := "virtex7" -- Specifies the target FPGA device family ); port ( -- Clock and Reset inputs ------------------------------------------ -- primary_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- Reset input -- mmap_reset : in std_logic; -- -- Reset used for the internal master logic -- -------------------------------------------------------------------- -- Soft Shutdown Control interface -------------------------------- -- rst2wsc_stop_request : in std_logic; -- -- Active high soft stop request to modules -- -- wsc2rst_stop_cmplt : Out std_logic; -- -- Active high indication that the Write status Controller -- -- has completed any pending transfers committed by the -- -- Address Controller after a stop has been requested by -- -- the Reset module. -- -- addr2wsc_addr_posted : In std_logic ; -- -- Indication from the Address Channel Controller to the -- -- write Status Controller that an address has been posted -- -- to the AXI Address Channel -- -------------------------------------------------------------------- -- Write Response Channel Interface ------------------------------- -- s2mm_bresp : In std_logic_vector(1 downto 0); -- -- The Write response value -- -- s2mm_bvalid : In std_logic ; -- -- Indication from the Write Response Channel that a new -- -- write status input is valid -- -- s2mm_bready : out std_logic ; -- -- Indication to the Write Response Channel that the -- -- Status module is ready for a new status input -- -------------------------------------------------------------------- -- Command Calculator Interface ------------------------------------- -- calc2wsc_calc_error : in std_logic ; -- -- Indication from the Command Calculator that a calculation -- -- error has occured. -- --------------------------------------------------------------------- -- Address Controller Status ---------------------------------------- -- addr2wsc_calc_error : In std_logic ; -- -- Indication from the Address Channel Controller that it -- -- has encountered a calculation error from the command -- -- Calculator -- -- addr2wsc_fifo_empty : In std_logic ; -- -- Indication from the Address Controller FIFO that it -- -- is empty (no commands pending) -- --------------------------------------------------------------------- -- Data Controller Status --------------------------------------------------------- -- data2wsc_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); -- -- The command tag -- -- data2wsc_calc_error : In std_logic ; -- -- Indication from the Data Channel Controller FIFO that it -- -- has encountered a Calculation error in the command pipe -- -- data2wsc_last_error : In std_logic ; -- -- Indication from the Write Data Channel Controller that a -- -- premature TLAST assertion was encountered on the incoming -- -- Stream Channel -- -- data2wsc_cmd_cmplt : In std_logic ; -- -- Indication from the Data Channel Controller that the -- -- corresponding status is the final status for a parent -- -- command fetched from the command FIFO -- -- data2wsc_valid : In std_logic ; -- -- Indication from the Data Channel Controller FIFO that it -- -- has a new tag/error status to transfer -- -- wsc2data_ready : out std_logic ; -- -- Indication to the Data Channel Controller FIFO that the -- -- Status module is ready for a new tag/error status input -- -- -- data2wsc_eop : In std_logic; -- -- Input from the Write Data Controller indicating that the -- -- associated command status also corresponds to a End of Packet -- -- marker for the input Stream. This is only used when Store and -- -- Forward is enabled in the S2MM. -- -- data2wsc_bytes_rcvd : In std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); -- -- Input from the Write Data Controller indicating the actual -- -- number of bytes received from the Stream input for the -- -- corresponding command status. This is only used when Store and -- -- Forward is enabled in the S2MM. -- ------------------------------------------------------------------------------------ -- Command/Status Interface -------------------------------------------------------- -- wsc2stat_status : Out std_logic_vector(C_STS_WIDTH-1 downto 0); -- -- Read Status value collected during a Read Data transfer -- -- Output to the Command/Status Module -- -- stat2wsc_status_ready : In std_logic; -- -- Input from the Command/Status Module indicating that the -- -- Status Reg/FIFO is Full and cannot accept more staus writes -- -- wsc2stat_status_valid : Out std_logic ; -- -- Control Signal to Write the Status value to the Status -- -- Reg/FIFO -- ------------------------------------------------------------------------------------ -- Address and Data Controller Pipe halt -------------------------------- -- wsc2mstr_halt_pipe : Out std_logic -- -- Indication to Halt the Data and Address Command pipeline due -- -- to the Status pipe getting full at some point -- ------------------------------------------------------------------------- ); end entity axi_datamover_wr_status_cntl; architecture implementation of axi_datamover_wr_status_cntl is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_set_cnt_width -- -- Function Description: -- Sets a count width based on a fifo depth. A depth of 4 or less -- is a special case which requires a minimum count width of 3 bits. -- ------------------------------------------------------------------- function funct_set_cnt_width (fifo_depth : integer) return integer is Variable temp_cnt_width : Integer := 4; begin if (fifo_depth <= 4) then temp_cnt_width := 3; elsif (fifo_depth <= 8) then temp_cnt_width := 4; elsif (fifo_depth <= 16) then temp_cnt_width := 5; elsif (fifo_depth <= 32) then temp_cnt_width := 6; else -- fifo depth <= 64 temp_cnt_width := 7; end if; Return (temp_cnt_width); end function funct_set_cnt_width; -- Constant Declarations -------------------------------------------- Constant OKAY : std_logic_vector(1 downto 0) := "00"; Constant EXOKAY : std_logic_vector(1 downto 0) := "01"; Constant SLVERR : std_logic_vector(1 downto 0) := "10"; Constant DECERR : std_logic_vector(1 downto 0) := "11"; Constant STAT_RSVD : std_logic_vector(3 downto 0) := "0000"; Constant TAG_WIDTH : integer := C_TAG_WIDTH; Constant STAT_REG_TAG_WIDTH : integer := 4; Constant SYNC_FIFO_SELECT : integer := 0; Constant SRL_FIFO_TYPE : integer := 2; Constant DCNTL_SFIFO_DEPTH : integer := C_STS_FIFO_DEPTH; Constant DCNTL_STATCNT_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits Constant DCNTL_HALT_THRES : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := TO_UNSIGNED(DCNTL_SFIFO_DEPTH-2,DCNTL_STATCNT_WIDTH); Constant DCNTL_STATCNT_ZERO : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0'); Constant DCNTL_STATCNT_MAX : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := TO_UNSIGNED(DCNTL_SFIFO_DEPTH,DCNTL_STATCNT_WIDTH); Constant DCNTL_STATCNT_ONE : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := TO_UNSIGNED(1, DCNTL_STATCNT_WIDTH); Constant WRESP_WIDTH : integer := 2; Constant WRESP_SFIFO_WIDTH : integer := WRESP_WIDTH; Constant WRESP_SFIFO_DEPTH : integer := DCNTL_SFIFO_DEPTH; Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_STS_FIFO_DEPTH);-- bits Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0'); Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH); Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '1'); -- Signal Declarations -------------------------------------------- signal sig_valid_status_rdy : std_logic := '0'; signal sig_decerr : std_logic := '0'; signal sig_slverr : std_logic := '0'; signal sig_coelsc_okay_reg : std_logic := '0'; signal sig_coelsc_interr_reg : std_logic := '0'; signal sig_coelsc_decerr_reg : std_logic := '0'; signal sig_coelsc_slverr_reg : std_logic := '0'; signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_pop_coelsc_reg : std_logic := '0'; signal sig_push_coelsc_reg : std_logic := '0'; signal sig_coelsc_reg_empty : std_logic := '0'; signal sig_coelsc_reg_full : std_logic := '0'; signal sig_tag2status : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_data_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_data_err_reg : std_logic := '0'; signal sig_data_last_err_reg : std_logic := '0'; signal sig_data_cmd_cmplt_reg : std_logic := '0'; signal sig_bresp_reg : std_logic_vector(1 downto 0) := (others => '0'); signal sig_push_status : std_logic := '0'; Signal sig_status_push_ok : std_logic := '0'; signal sig_status_valid : std_logic := '0'; signal sig_wsc2data_ready : std_logic := '0'; signal sig_s2mm_bready : std_logic := '0'; signal sig_wresp_sfifo_in : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_wresp_sfifo_out : std_logic_vector(WRESP_SFIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_wresp_sfifo_wr_valid : std_logic := '0'; signal sig_wresp_sfifo_wr_ready : std_logic := '0'; signal sig_wresp_sfifo_wr_full : std_logic := '0'; signal sig_wresp_sfifo_rd_valid : std_logic := '0'; signal sig_wresp_sfifo_rd_ready : std_logic := '0'; signal sig_wresp_sfifo_rd_empty : std_logic := '0'; signal sig_halt_reg : std_logic := '0'; signal sig_halt_reg_dly1 : std_logic := '0'; signal sig_halt_reg_dly2 : std_logic := '0'; signal sig_halt_reg_dly3 : std_logic := '0'; signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_addr_posted_cntr_eq_0 : std_logic := '0'; signal sig_addr_posted_cntr_eq_1 : std_logic := '0'; signal sig_addr_posted_cntr_max : std_logic := '0'; signal sig_decr_addr_posted_cntr : std_logic := '0'; signal sig_incr_addr_posted_cntr : std_logic := '0'; signal sig_no_posted_cmds : std_logic := '0'; signal sig_addr_posted : std_logic := '0'; signal sig_all_cmds_done : std_logic := '0'; signal sig_wsc2stat_status : std_logic_vector(C_STS_WIDTH-1 downto 0) := (others => '0'); signal sig_dcntl_sfifo_wr_valid : std_logic := '0'; signal sig_dcntl_sfifo_wr_ready : std_logic := '0'; signal sig_dcntl_sfifo_wr_full : std_logic := '0'; signal sig_dcntl_sfifo_rd_valid : std_logic := '0'; signal sig_dcntl_sfifo_rd_ready : std_logic := '0'; signal sig_dcntl_sfifo_rd_empty : std_logic := '0'; signal sig_wdc_statcnt : unsigned(DCNTL_STATCNT_WIDTH-1 downto 0) := (others => '0'); signal sig_incr_statcnt : std_logic := '0'; signal sig_decr_statcnt : std_logic := '0'; signal sig_statcnt_eq_max : std_logic := '0'; signal sig_statcnt_eq_0 : std_logic := '0'; signal sig_statcnt_gt_eq_thres : std_logic := '0'; signal sig_wdc_status_going_full : std_logic := '0'; begin --(architecture implementation) -- Assign the ready output to the AXI Write Response Channel s2mm_bready <= sig_s2mm_bready or sig_halt_reg; -- force bready if a Halt is requested -- Assign the ready output to the Data Controller status interface wsc2data_ready <= sig_wsc2data_ready; -- Assign the status valid output control to the Status FIFO wsc2stat_status_valid <= sig_status_valid ; -- Formulate the status output value to the Status FIFO wsc2stat_status <= sig_wsc2stat_status; -- Formulate the status write request signal sig_status_valid <= sig_push_status; -- Indicate the desire to push a coelesced status word -- to the Status FIFO sig_push_status <= sig_coelsc_reg_full; -- Detect that a push of a new status word is completing sig_status_push_ok <= sig_status_valid and stat2wsc_status_ready; sig_pop_coelsc_reg <= sig_status_push_ok; -- Signal a halt to the execution pipe if new status -- is valid but the Status FIFO is not accepting it or -- the WDC Status FIFO is going full wsc2mstr_halt_pipe <= (sig_status_valid and not(stat2wsc_status_ready)) or sig_wdc_status_going_full; -- Monitor the Status capture registers to detect a -- qualified Status set and push to the coelescing register -- when available to do so sig_push_coelsc_reg <= sig_valid_status_rdy and sig_coelsc_reg_empty; -- pre CR616212 sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and -- pre CR616212 sig_dcntl_sfifo_rd_valid) or -- pre CR616212 (sig_data_err_reg and -- pre CR616212 sig_dcntl_sfifo_rd_valid); sig_valid_status_rdy <= (sig_wresp_sfifo_rd_valid and sig_dcntl_sfifo_rd_valid) or (sig_data_err_reg and sig_dcntl_sfifo_rd_valid) or -- or Added for CR616212 (sig_data_last_err_reg and -- Added for CR616212 sig_dcntl_sfifo_rd_valid); -- Added for CR616212 -- Decode the AXI MMap Read Respose sig_decerr <= '1' When sig_bresp_reg = DECERR Else '0'; sig_slverr <= '1' When sig_bresp_reg = SLVERR Else '0'; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_TAG_LE_STAT -- -- If Generate Description: -- Populates the TAG bits into the availble Status bits when -- the TAG width is less than or equal to the available number -- of bits in the Status word. -- ------------------------------------------------------------ GEN_TAG_LE_STAT : if (TAG_WIDTH <= STAT_REG_TAG_WIDTH) generate -- local signals signal lsig_temp_tag_small : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0'); begin sig_tag2status <= lsig_temp_tag_small; ------------------------------------------------------------- -- Combinational Process -- -- Label: POPULATE_SMALL_TAG -- -- Process Description: -- -- ------------------------------------------------------------- POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg) begin -- Set default value lsig_temp_tag_small <= (others => '0'); -- Now overload actual TAG bits lsig_temp_tag_small(TAG_WIDTH-1 downto 0) <= sig_coelsc_tag_reg; end process POPULATE_SMALL_TAG; end generate GEN_TAG_LE_STAT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_TAG_GT_STAT -- -- If Generate Description: -- Populates the TAG bits into the availble Status bits when -- the TAG width is greater than the available number of -- bits in the Status word. The upper bits of the TAG are -- clipped off (discarded). -- ------------------------------------------------------------ GEN_TAG_GT_STAT : if (TAG_WIDTH > STAT_REG_TAG_WIDTH) generate -- local signals signal lsig_temp_tag_big : std_logic_vector(STAT_REG_TAG_WIDTH-1 downto 0) := (others => '0'); begin sig_tag2status <= lsig_temp_tag_big; ------------------------------------------------------------- -- Combinational Process -- -- Label: POPULATE_BIG_TAG -- -- Process Description: -- -- ------------------------------------------------------------- POPULATE_SMALL_TAG : process (sig_coelsc_tag_reg) begin -- Set default value lsig_temp_tag_big <= (others => '0'); -- Now overload actual TAG bits lsig_temp_tag_big <= sig_coelsc_tag_reg(STAT_REG_TAG_WIDTH-1 downto 0); end process POPULATE_SMALL_TAG; end generate GEN_TAG_GT_STAT; ------------------------------------------------------------------------- -- Write Response Channel input FIFO and logic -- BRESP is the only fifo data sig_wresp_sfifo_in <= s2mm_bresp; -- The fifo output is already in the right format sig_bresp_reg <= sig_wresp_sfifo_out; -- Write Side assignments sig_wresp_sfifo_wr_valid <= s2mm_bvalid; sig_s2mm_bready <= sig_wresp_sfifo_wr_ready; -- read Side ready assignment sig_wresp_sfifo_rd_ready <= sig_push_coelsc_reg; ------------------------------------------------------------ -- Instance: I_WRESP_STATUS_FIFO -- -- Description: -- Instance for the AXI Write Response FIFO -- ------------------------------------------------------------ I_WRESP_STATUS_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo generic map ( C_DWIDTH => WRESP_SFIFO_WIDTH , C_DEPTH => WRESP_SFIFO_DEPTH , C_IS_ASYNC => SYNC_FIFO_SELECT , C_PRIM_TYPE => SRL_FIFO_TYPE , C_FAMILY => C_FAMILY ) port map ( -- Write Clock and reset fifo_wr_reset => mmap_reset , fifo_wr_clk => primary_aclk , -- Write Side fifo_wr_tvalid => sig_wresp_sfifo_wr_valid , fifo_wr_tready => sig_wresp_sfifo_wr_ready , fifo_wr_tdata => sig_wresp_sfifo_in , fifo_wr_full => sig_wresp_sfifo_wr_full , -- Read Clock and reset (not used in Sync mode) fifo_async_rd_reset => mmap_reset , fifo_async_rd_clk => primary_aclk , -- Read Side fifo_rd_tvalid => sig_wresp_sfifo_rd_valid , fifo_rd_tready => sig_wresp_sfifo_rd_ready , fifo_rd_tdata => sig_wresp_sfifo_out , fifo_rd_empty => sig_wresp_sfifo_rd_empty ); -------- Write Data Controller Status FIFO Going Full Logic ------------- sig_incr_statcnt <= sig_dcntl_sfifo_wr_valid and sig_dcntl_sfifo_wr_ready; sig_decr_statcnt <= sig_dcntl_sfifo_rd_valid and sig_dcntl_sfifo_rd_ready; sig_statcnt_eq_max <= '1' when (sig_wdc_statcnt = DCNTL_STATCNT_MAX) Else '0'; sig_statcnt_eq_0 <= '1' when (sig_wdc_statcnt = DCNTL_STATCNT_ZERO) Else '0'; sig_statcnt_gt_eq_thres <= '1' when (sig_wdc_statcnt >= DCNTL_HALT_THRES) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_WDC_GOING_FULL_FLOP -- -- Process Description: -- Implements a flop for the WDC Status FIFO going full flag. -- ------------------------------------------------------------- IMP_WDC_GOING_FULL_FLOP : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_wdc_status_going_full <= '0'; else sig_wdc_status_going_full <= sig_statcnt_gt_eq_thres; end if; end if; end process IMP_WDC_GOING_FULL_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_DCNTL_FIFO_CNTR -- -- Process Description: -- Implements a simple counter keeping track of the number -- of entries in the WDC Status FIFO. If the Status FIFO gets -- too full, the S2MM Data Pipe has to be halted. -- ------------------------------------------------------------- IMP_DCNTL_FIFO_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_wdc_statcnt <= (others => '0'); elsif (sig_incr_statcnt = '1' and sig_decr_statcnt = '0' and sig_statcnt_eq_max = '0') then sig_wdc_statcnt <= sig_wdc_statcnt + DCNTL_STATCNT_ONE; elsif (sig_incr_statcnt = '0' and sig_decr_statcnt = '1' and sig_statcnt_eq_0 = '0') then sig_wdc_statcnt <= sig_wdc_statcnt - DCNTL_STATCNT_ONE; else null; -- Hold current count value end if; end if; end process IMP_DCNTL_FIFO_CNTR; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_OMIT_INDET_BTT -- -- If Generate Description: -- Implements the logic needed when Indeterminate BTT is -- not enabled in the S2MM function. -- ------------------------------------------------------------ GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate -- Local Constants Constant DCNTL_SFIFO_WIDTH : integer := STAT_REG_TAG_WIDTH+3; Constant DCNTL_SFIFO_CMD_CMPLT_INDEX : integer := 0; Constant DCNTL_SFIFO_TLAST_ERR_INDEX : integer := 1; Constant DCNTL_SFIFO_CALC_ERR_INDEX : integer := 2; Constant DCNTL_SFIFO_TAG_INDEX : integer := DCNTL_SFIFO_CALC_ERR_INDEX+1; -- local signals signal sig_dcntl_sfifo_in : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_dcntl_sfifo_out : std_logic_vector(DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0'); begin sig_wsc2stat_status <= sig_coelsc_okay_reg & sig_coelsc_slverr_reg & sig_coelsc_decerr_reg & sig_coelsc_interr_reg & sig_tag2status; ----------------------------------------------------------------------------- -- Data Controller Status FIFO and Logic -- Concatonate Input bits to build Dcntl fifo data word sig_dcntl_sfifo_in <= data2wsc_tag & -- bit 3 to tag Width+2 data2wsc_calc_error & -- bit 2 data2wsc_last_error & -- bit 1 data2wsc_cmd_cmplt ; -- bit 0 -- Rip the DCntl fifo outputs back to constituant pieces sig_data_tag_reg <= sig_dcntl_sfifo_out((DCNTL_SFIFO_TAG_INDEX+STAT_REG_TAG_WIDTH)-1 downto DCNTL_SFIFO_TAG_INDEX); sig_data_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CALC_ERR_INDEX) ; sig_data_last_err_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_TLAST_ERR_INDEX); sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(DCNTL_SFIFO_CMD_CMPLT_INDEX); -- Data Control Valid/Ready assignments sig_dcntl_sfifo_wr_valid <= data2wsc_valid ; sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready; -- read side ready assignment sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg; ------------------------------------------------------------ -- Instance: I_DATA_CNTL_STATUS_FIFO -- -- Description: -- Instance for the Command Qualifier FIFO -- ------------------------------------------------------------ I_DATA_CNTL_STATUS_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo generic map ( C_DWIDTH => DCNTL_SFIFO_WIDTH , C_DEPTH => DCNTL_SFIFO_DEPTH , C_IS_ASYNC => SYNC_FIFO_SELECT , C_PRIM_TYPE => SRL_FIFO_TYPE , C_FAMILY => C_FAMILY ) port map ( -- Write Clock and reset fifo_wr_reset => mmap_reset , fifo_wr_clk => primary_aclk , -- Write Side fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid , fifo_wr_tready => sig_dcntl_sfifo_wr_ready , fifo_wr_tdata => sig_dcntl_sfifo_in , fifo_wr_full => sig_dcntl_sfifo_wr_full , -- Read Clock and reset (not used in Sync mode) fifo_async_rd_reset => mmap_reset , fifo_async_rd_clk => primary_aclk , -- Read Side fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid , fifo_rd_tready => sig_dcntl_sfifo_rd_ready , fifo_rd_tdata => sig_dcntl_sfifo_out , fifo_rd_empty => sig_dcntl_sfifo_rd_empty ); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: STATUS_COELESC_REG -- -- Process Description: -- Implement error status coelescing register. -- Once a bit is set it will remain set until the overall -- status is written to the Status FIFO. -- Tag bits are just registered at each valid dbeat. -- ------------------------------------------------------------- STATUS_COELESC_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_pop_coelsc_reg = '1') then sig_coelsc_tag_reg <= (others => '0'); sig_coelsc_interr_reg <= '0'; sig_coelsc_decerr_reg <= '0'; sig_coelsc_slverr_reg <= '0'; sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY" sig_coelsc_reg_full <= '0'; sig_coelsc_reg_empty <= '1'; Elsif (sig_push_coelsc_reg = '1') Then sig_coelsc_tag_reg <= sig_data_tag_reg; sig_coelsc_interr_reg <= sig_data_err_reg or sig_data_last_err_reg or sig_coelsc_interr_reg; sig_coelsc_decerr_reg <= not(sig_data_err_reg) and (sig_decerr or sig_coelsc_decerr_reg); sig_coelsc_slverr_reg <= not(sig_data_err_reg) and (sig_slverr or sig_coelsc_slverr_reg); sig_coelsc_okay_reg <= not(sig_decerr or sig_coelsc_decerr_reg or sig_slverr or sig_coelsc_slverr_reg or sig_data_err_reg or sig_data_last_err_reg or sig_coelsc_interr_reg ); sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg; sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg); else null; -- hold current state end if; end if; end process STATUS_COELESC_REG; end generate GEN_OMIT_INDET_BTT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_ENABLE_INDET_BTT -- -- If Generate Description: -- Implements the logic needed when Indeterminate BTT is -- enabled in the S2MM function. Primary difference is the -- addition to the reported status of the End of Packet -- marker (EOP) and the received byte count for the parent -- command. -- ------------------------------------------------------------ GEN_ENABLE_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate -- Local Constants Constant SF_DCNTL_SFIFO_WIDTH : integer := TAG_WIDTH + C_SF_BYTES_RCVD_WIDTH + 3; Constant SF_SFIFO_LS_TAG_INDEX : integer := 0; Constant SF_SFIFO_MS_TAG_INDEX : integer := SF_SFIFO_LS_TAG_INDEX + (TAG_WIDTH-1); Constant SF_SFIFO_CALC_ERR_INDEX : integer := SF_SFIFO_MS_TAG_INDEX+1; Constant SF_SFIFO_CMD_CMPLT_INDEX : integer := SF_SFIFO_CALC_ERR_INDEX+1; Constant SF_SFIFO_LS_BYTES_RCVD_INDEX : integer := SF_SFIFO_CMD_CMPLT_INDEX+1; Constant SF_SFIFO_MS_BYTES_RCVD_INDEX : integer := SF_SFIFO_LS_BYTES_RCVD_INDEX+ (C_SF_BYTES_RCVD_WIDTH-1); Constant SF_SFIFO_EOP_INDEX : integer := SF_SFIFO_MS_BYTES_RCVD_INDEX+1; Constant BYTES_RCVD_FIELD_WIDTH : integer := 23; -- local signals signal sig_dcntl_sfifo_in : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_dcntl_sfifo_out : std_logic_vector(SF_DCNTL_SFIFO_WIDTH-1 downto 0) := (others => '0'); signal sig_data_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0'); signal sig_data_eop : std_logic := '0'; signal sig_coelsc_bytes_rcvd : std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0'); signal sig_coelsc_eop : std_logic := '0'; signal sig_coelsc_bytes_rcvd_pad : std_logic_vector(BYTES_RCVD_FIELD_WIDTH-1 downto 0) := (others => '0'); begin sig_wsc2stat_status <= sig_coelsc_eop & sig_coelsc_bytes_rcvd_pad & sig_coelsc_okay_reg & sig_coelsc_slverr_reg & sig_coelsc_decerr_reg & sig_coelsc_interr_reg & sig_tag2status; ----------------------------------------------------------------------------- -- Data Controller Status FIFO and Logic -- Concatonate Input bits to build Dcntl fifo input data word sig_dcntl_sfifo_in <= data2wsc_eop & -- ms bit data2wsc_bytes_rcvd & -- bit 7 to C_SF_BYTES_RCVD_WIDTH+7 data2wsc_cmd_cmplt & -- bit 6 data2wsc_calc_error & -- bit 4 data2wsc_tag; -- bits 0 to 3 -- Rip the DCntl fifo outputs back to constituant pieces sig_data_eop <= sig_dcntl_sfifo_out(SF_SFIFO_EOP_INDEX); sig_data_bytes_rcvd <= sig_dcntl_sfifo_out(SF_SFIFO_MS_BYTES_RCVD_INDEX downto SF_SFIFO_LS_BYTES_RCVD_INDEX); sig_data_cmd_cmplt_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CMD_CMPLT_INDEX); sig_data_err_reg <= sig_dcntl_sfifo_out(SF_SFIFO_CALC_ERR_INDEX); sig_data_tag_reg <= sig_dcntl_sfifo_out(SF_SFIFO_MS_TAG_INDEX downto SF_SFIFO_LS_TAG_INDEX) ; -- Data Control Valid/Ready assignments sig_dcntl_sfifo_wr_valid <= data2wsc_valid ; sig_wsc2data_ready <= sig_dcntl_sfifo_wr_ready; -- read side ready assignment sig_dcntl_sfifo_rd_ready <= sig_push_coelsc_reg; ------------------------------------------------------------ -- Instance: I_SF_DATA_CNTL_STATUS_FIFO -- -- Description: -- Instance for the Command Qualifier FIFO when Store and -- Forward is included. -- ------------------------------------------------------------ I_SF_DATA_CNTL_STATUS_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo generic map ( C_DWIDTH => SF_DCNTL_SFIFO_WIDTH , C_DEPTH => DCNTL_SFIFO_DEPTH , C_IS_ASYNC => SYNC_FIFO_SELECT , C_PRIM_TYPE => SRL_FIFO_TYPE , C_FAMILY => C_FAMILY ) port map ( -- Write Clock and reset fifo_wr_reset => mmap_reset , fifo_wr_clk => primary_aclk , -- Write Side fifo_wr_tvalid => sig_dcntl_sfifo_wr_valid , fifo_wr_tready => sig_dcntl_sfifo_wr_ready , fifo_wr_tdata => sig_dcntl_sfifo_in , fifo_wr_full => sig_dcntl_sfifo_wr_full , -- Read Clock and reset (not used in Sync mode) fifo_async_rd_reset => mmap_reset , fifo_async_rd_clk => primary_aclk , -- Read Side fifo_rd_tvalid => sig_dcntl_sfifo_rd_valid , fifo_rd_tready => sig_dcntl_sfifo_rd_ready , fifo_rd_tdata => sig_dcntl_sfifo_out , fifo_rd_empty => sig_dcntl_sfifo_rd_empty ); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SF_STATUS_COELESC_REG -- -- Process Description: -- Implement error status coelescing register. -- Once a bit is set it will remain set until the overall -- status is written to the Status FIFO. -- Tag bits are just registered at each valid dbeat. -- ------------------------------------------------------------- SF_STATUS_COELESC_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1' or sig_pop_coelsc_reg = '1') then sig_coelsc_tag_reg <= (others => '0'); sig_coelsc_interr_reg <= '0'; sig_coelsc_decerr_reg <= '0'; sig_coelsc_slverr_reg <= '0'; sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY" sig_coelsc_bytes_rcvd <= (others => '0'); sig_coelsc_eop <= '0'; sig_coelsc_reg_full <= '0'; sig_coelsc_reg_empty <= '1'; Elsif (sig_push_coelsc_reg = '1') Then sig_coelsc_tag_reg <= sig_data_tag_reg; sig_coelsc_interr_reg <= sig_data_err_reg or sig_coelsc_interr_reg; sig_coelsc_decerr_reg <= not(sig_data_err_reg) and (sig_decerr or sig_coelsc_decerr_reg); sig_coelsc_slverr_reg <= not(sig_data_err_reg) and (sig_slverr or sig_coelsc_slverr_reg); sig_coelsc_okay_reg <= not(sig_decerr or sig_coelsc_decerr_reg or sig_slverr or sig_coelsc_slverr_reg or sig_data_err_reg or sig_coelsc_interr_reg ); sig_coelsc_bytes_rcvd <= sig_data_bytes_rcvd; sig_coelsc_eop <= sig_data_eop; sig_coelsc_reg_full <= sig_data_cmd_cmplt_reg; sig_coelsc_reg_empty <= not(sig_data_cmd_cmplt_reg); else null; -- hold current state end if; end if; end process SF_STATUS_COELESC_REG; ------------------------------------------------------------ -- If Generate -- -- Label: SF_GEN_PAD_BYTES_RCVD -- -- If Generate Description: -- Pad the bytes received value with zeros to fill in the -- status field width. -- -- ------------------------------------------------------------ SF_GEN_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH < BYTES_RCVD_FIELD_WIDTH) generate begin sig_coelsc_bytes_rcvd_pad(BYTES_RCVD_FIELD_WIDTH-1 downto C_SF_BYTES_RCVD_WIDTH) <= (others => '0'); sig_coelsc_bytes_rcvd_pad(C_SF_BYTES_RCVD_WIDTH-1 downto 0) <= sig_coelsc_bytes_rcvd; end generate SF_GEN_PAD_BYTES_RCVD; ------------------------------------------------------------ -- If Generate -- -- Label: SF_GEN_NO_PAD_BYTES_RCVD -- -- If Generate Description: -- No padding required for the bytes received value. -- -- ------------------------------------------------------------ SF_GEN_NO_PAD_BYTES_RCVD : if (C_SF_BYTES_RCVD_WIDTH = BYTES_RCVD_FIELD_WIDTH) generate begin sig_coelsc_bytes_rcvd_pad <= sig_coelsc_bytes_rcvd; -- no pad required end generate SF_GEN_NO_PAD_BYTES_RCVD; end generate GEN_ENABLE_INDET_BTT; ------- Soft Shutdown Logic ------------------------------- -- Address Posted Counter Logic ---------------------t----------------- -- Supports soft shutdown by tracking when all commited Write -- transfers to the AXI Bus have had corresponding Write Status -- Reponses Received. sig_addr_posted <= addr2wsc_addr_posted ; sig_incr_addr_posted_cntr <= sig_addr_posted ; sig_decr_addr_posted_cntr <= sig_s2mm_bready and s2mm_bvalid ; sig_addr_posted_cntr_eq_0 <= '1' when (sig_addr_posted_cntr = ADDR_POSTED_ZERO) Else '0'; sig_addr_posted_cntr_eq_1 <= '1' when (sig_addr_posted_cntr = ADDR_POSTED_ONE) Else '0'; sig_addr_posted_cntr_max <= '1' when (sig_addr_posted_cntr = ADDR_POSTED_MAX) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_ADDR_POSTED_FIFO_CNTR -- -- Process Description: -- This process implements a counter for the tracking -- if an Address has been posted on the AXI address channel. -- The counter is used to track flushing operations where all -- transfers committed on the AXI Address Channel have to -- be completed before a halt can occur. ------------------------------------------------------------- IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_addr_posted_cntr <= ADDR_POSTED_ZERO; elsif (sig_incr_addr_posted_cntr = '1' and sig_decr_addr_posted_cntr = '0' and sig_addr_posted_cntr_max = '0') then sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ; elsif (sig_incr_addr_posted_cntr = '0' and sig_decr_addr_posted_cntr = '1' and sig_addr_posted_cntr_eq_0 = '0') then sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ; else null; -- don't change state end if; end if; end process IMP_ADDR_POSTED_FIFO_CNTR; wsc2rst_stop_cmplt <= sig_all_cmds_done; sig_no_posted_cmds <= (sig_addr_posted_cntr_eq_0 and not(addr2wsc_calc_error)) or (sig_addr_posted_cntr_eq_1 and addr2wsc_calc_error); sig_all_cmds_done <= sig_no_posted_cmds and sig_halt_reg_dly3; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_HALT_REQ_REG -- -- Process Description: -- Implements the flop for capturing the Halt request from -- the Reset module. -- ------------------------------------------------------------- IMP_HALT_REQ_REG : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_halt_reg <= '0'; elsif (rst2wsc_stop_request = '1') then sig_halt_reg <= '1'; else null; -- Hold current State end if; end if; end process IMP_HALT_REQ_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_HALT_REQ_REG_DLY -- -- Process Description: -- Implements the flops for delaying the halt request by 3 -- clocks to allow the Address Controller to halt before the -- Data Contoller can safely indicate it has exhausted all -- transfers committed to the AXI Address Channel by the Address -- Controller. -- ------------------------------------------------------------- IMP_HALT_REQ_REG_DLY : process (primary_aclk) begin if (primary_aclk'event and primary_aclk = '1') then if (mmap_reset = '1') then sig_halt_reg_dly1 <= '0'; sig_halt_reg_dly2 <= '0'; sig_halt_reg_dly3 <= '0'; else sig_halt_reg_dly1 <= sig_halt_reg; sig_halt_reg_dly2 <= sig_halt_reg_dly1; sig_halt_reg_dly3 <= sig_halt_reg_dly2; end if; end if; end process IMP_HALT_REQ_REG_DLY; end implementation;

-- ------------------------------------------------------------- -- -- Entity Declaration for inst_ok_2_e -- -- Generated -- by: wig -- on: Fri Jul 15 13:54:30 2005 -- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls -- -- !!! Do not edit this file! Autogenerated by MIX !!! -- $Author: wig $ -- $Id: inst_ok_2_e-e.vhd,v 1.2 2005/07/15 16:20:00 wig Exp $ -- $Date: 2005/07/15 16:20:00 $ -- $Log: inst_ok_2_e-e.vhd,v $ -- Revision 1.2 2005/07/15 16:20:00 wig -- Update all testcases; still problems though -- -- -- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v -- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp -- -- Generator: mix_0.pl Version: Revision: 1.36 , [email protected] -- (C) 2003 Micronas GmbH -- -- -------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; -- No project specific VHDL libraries/enty -- -- -- Start of Generated Entity inst_ok_2_e -- entity inst_ok_2_e is -- Generics: -- No Generated Generics for Entity inst_ok_2_e -- Generated Port Declaration: -- No Generated Port for Entity inst_ok_2_e end inst_ok_2_e; -- -- End of Generated Entity inst_ok_2_e -- -- --!End of Entity/ies -- --------------------------------------------------------------

----------------------------------------------------------------------------------------------------------------------- -- Author: Jonny Doin, [email protected], [email protected] -- -- Create Date: 09:56:30 07/06/2011 -- Module Name: grp_debouncer - RTL -- Project Name: basic functions -- Target Devices: Spartan-6 -- Tool versions: ISE 13.1 -- Description: -- -- This block is a generic multiple input debouncing circuit. -- It handles multiple inputs, like mechanical switch inputs, and outputs a debounced, stable registered version of the inputs. -- A 'new_data' one-cycle strobe is also available, to sync downstream logic. -- -- CONCEPTUAL CIRCUIT -- ================== -- -- W -- /----------------/----------------\ -- | | -- | | -- | ______ ______ | _____ -- | W | | W |fdr | W | W |cmp \ -- \----/---| +1 |---/----| |--/--+----/----| \ -- | | | | | \ -- ------ | | \ | -- | | | = |-----\ -- |> R | / | | -- ---+-- | / | -- | CNT_VAL---| / | -- | |____/ | -- | | -- \------------\ | -- | | -- N ____ | | -- /-------/---)) \ ____ | | -- | ))XOR |-----) \ | | -- | /------))___/ )OR |-----/ | -- | | /---)___/ | -- | | | | -- | | \----------\ | -- | | N | | -- | \--------/-----------\ +----------------------+---------\ -- | | | | -- \---\ | | | -- ______ | ______ | | ______ | -- | fd | | | fd | | | |fde | | -- [data_i]----/-----| |---/---+---/----| |---/---+----)---| |---/---+---/-----------)------------------------[data_o] -- N | | N N | | N | | | | N | N | -- | | | | | \---|CE | | | -- | | | | | | | | | -- [clk_i]----> |> | |> | | |> | | | ____ ______ -- ------ ------ | ------ | N ____ \---| \ | fd | -- | \---/---)) \ |AND |-----| |----[strb_o] -- | ))XOR |-----|___/ | | -- \-------------------------/---))___/ | | -- N | | -- |> | -- ------ -- -- -- PIPELINE LOGIC -- ============== -- -- This debouncer circuit detects edges in an input signal, and waits the signal to stabilize for the designated time -- before transferring the stable signal to the registered output. -- A one-clock-cyle strobe is pulsed at the output to signalize a new data available. -- The core clock should be the system clock, to optimize use of global clock resources. -- -- GROUP DEBOUNCING -- ================ -- -- A change in state in any bit in the input word causes reload of the delay counter, and the output word is updated only -- when all bits are stable for the specified period. Therefore, the grouping of signals and delay selection should match -- behaviour of the selected signals. -- -- RESOURCES USED -- ============== -- -- The number of registers inferred is: 3*N + (LOG(CNT_VAL)/LOG(2)) + 1 registers. -- The number of LUTs inferred is roughly: ((4*N+2)/6)+2. -- The slice distribution will vary, and depends on the control set restrictions and LUT-FF pairs resulting from map+p&r. -- -- This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints. -- Verification in silicon was done on a Digilent Atlys board with a Spartan-6 FPGA @100MHz clock. -- The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools. -- ------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- -- -- -- Author(s): Jonny Doin, [email protected], [email protected] -- -- Copyright (C) 2011 Jonny Doin -- ----------------------------- -- -- This source file may be used and distributed without restriction provided that this copyright statement is not -- removed from the file and that any derivative work contains the original copyright notice and the associated -- disclaimer. -- -- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser -- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or -- (at your option) any later version. -- -- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied -- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more -- details. -- -- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download -- it from http://www.gnu.org/licenses/lgpl.txt -- ------------------------------ REVISION HISTORY ----------------------------------------------------------------------- -- -- 2011/07/06 v0.01.0010 [JD] started development. verification of synthesis circuit inference. -- 2011/07/07 v1.00.0020 [JD] verification in silicon. operation at 100MHz, tested on the Atlys board (Spartan-6 LX45). -- 2011/08/10 v1.01.0025 [JD] added one pipeline delay to new data strobe output. -- 2011/09/19 v1.01.0030 [JD] changed range for internal counter (cnt_reg, cnt_next) to avoid adder flipover (Altera/ModelSim). -- ----------------------------------------------------------------------------------------------------------------------- -- TODO -- ==== -- -- The circuit can easily be extended to have a signature of which inputs changed at the data out port. -- ----------------------------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity GRP_DEBOUNCER is generic ( N : positive := 8; -- input bus width CNT_VAL : positive := 10000 -- clock counts for debounce period ); port ( CLK_I : in std_logic := 'X'; -- system clock DATA_I : in std_logic_vector(N - 1 downto 0) := (others => 'X'); -- noisy input data DATA_O : out std_logic_vector(N - 1 downto 0); -- registered stable output data STRB_O : out std_logic -- strobe for new data available ); end entity GRP_DEBOUNCER; architecture RTL of GRP_DEBOUNCER is -- datapath pipeline signal reg_a, reg_b : std_logic_vector(N - 1 downto 0) := (others => '0'); -- debounce edge detectors signal reg_out : std_logic_vector(N - 1 downto 0) := (others => '0'); -- registered output signal dat_strb : std_logic := '0'; -- data transfer strobe signal strb_reg : std_logic := '0'; -- registered strobe signal strb_next : std_logic := '0'; -- lookahead strobe signal dat_diff : std_logic := '0'; -- edge detector -- debounce counter signal cnt_reg : integer range CNT_VAL + 1 downto 0 := 0; -- debounce period counter signal cnt_next : integer range CNT_VAL + 1 downto 0 := 0; -- combinatorial signal begin --============================================================================================= -- DEBOUNCE COUNTER LOGIC --============================================================================================= -- This counter is implemented as a up-counter with reset and final count detection via compare, -- instead of a down-counter with preset and final count detection via nonzero detection. -- This is better for Spartan-6 and Virtex-6 CLB architecture, because it uses less control sets. -- -- cnt_reg register transfer logic CNT_REG_PROC : process (CLK_I) is begin if (CLK_I'event and CLK_I = '1') then cnt_reg <= cnt_next; end if; end process CNT_REG_PROC; -- cnt_next combinatorial logic cnt_next <= 0 when dat_diff = '1' or dat_strb = '1' else cnt_reg + 1; -- final count combinatorial logic dat_strb <= '1' when cnt_reg = CNT_VAL else '0'; --============================================================================================= -- DATAPATH SIGNAL PIPELINE --============================================================================================= -- input pipeline logic PIPELINE_PROC : process (CLK_I) is begin if (CLK_I'event and CLK_I = '1') then -- edge detection pipeline reg_a <= DATA_I; reg_b <= reg_a; -- new data strobe pipeline delay strb_reg <= strb_next; end if; -- output data pipeline if (CLK_I'event and CLK_I = '1') then if (dat_strb = '1') then reg_out <= reg_b; end if; end if; end process PIPELINE_PROC; -- edge detector dat_diff <= '1' when reg_a /= reg_b else '0'; -- lookahead new data strobe strb_next <= '1' when ((reg_out /= reg_b) and dat_strb = '1') else '0'; --============================================================================================= -- OUTPUT LOGIC --============================================================================================= -- connect output ports DATA_O <= reg_out; STRB_O <= strb_reg; end architecture RTL;

-------------------------------------------------------------------------------- -- -- Title : ctrl_leds.vhd -- Design : Example -- Author : Kapitanov -- Company : InSys -- -- Version : 1.0 -------------------------------------------------------------------------------- -- -- Description : Controller LEDs 8x8 -- -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity ctrl_leds is port( -- system signals: clk : in std_logic; --! clock clk_dv : in std_logic; --! clock/2 reset : in std_logic; --! system reset pwm_ena : in std_logic; --! enable PWM -- buttons: cbut : in std_logic_vector(5 downto 1); --! buttons -- leds vectors: led_x : out std_logic_vector(7 downto 0); --! LED X led_y : out std_logic_vector(7 downto 0) --! LED y ); end ctrl_leds; architecture ctrl_leds of ctrl_leds is component ctrl_led8x8_heart is port ( clk : in std_logic; -- Clock rst : in std_logic; -- Reset rst_reg : in std_logic; -- Count reset ch_freq : in std_logic; -- Change frequency led_y : out std_logic_vector(7 downto 0); -- LED Y led_x : out std_logic_vector(7 downto 0) -- LED X ); end component; component ctrl_pwm is port ( clk : in std_logic; -- Clock rst : in std_logic; -- Reset rst_reg : in std_logic; -- Count reset zoom_reg : in std_logic; -- Switch change zoom_cnt : in std_logic; -- Switch counter log_led : out std_logic -- Pulsed LED enable ); end component; component ctrl_jazz is port( clk : in std_logic; -- Clock button : in std_logic; -- Button in reset : in std_logic; -- Reset clrbutton : out std_logic -- Button out ); end component; signal clbutton : std_logic_vector(5 downto 1); signal log_led : std_logic; signal log_hearty : std_logic_vector(7 downto 0); signal log_heartx : std_logic_vector(7 downto 0); begin x_GEN_LEDX : for ii in 0 to 7 generate led_x(ii) <= log_led or log_heartx(ii) when pwm_ena = '0' else log_heartx(ii); end generate; x_GEN_LEDY : for ii in 0 to 7 generate led_y(ii) <= (log_led or log_hearty(ii)) when pwm_ena = '0' else log_hearty(ii); end generate; ---------------- PULSE-WITDH MODULO ---------------- xCTRL_PWM : ctrl_pwm port map ( clk => clk_dv, rst => reset, rst_reg => clbutton(1), zoom_reg => clbutton(2), zoom_cnt => clbutton(3), log_led => log_led ); ---------------- CTRL MATRIX 8X8 ---------------- xCTRL_LED : ctrl_led8x8_heart port map ( clk => clk_dv, rst => reset, rst_reg => clbutton(1), ch_freq => clbutton(2), led_y => log_hearty, led_x => log_heartx ); ---------------- DEBOUNCE ---------------- xDEBOUNCE: for ii in 1 to 5 generate x_buttons: ctrl_jazz port map ( clk => clk, button => cbut(ii), reset => reset, clrbutton => clbutton(ii) ); end generate; end ctrl_leds;

-- $Id: sys_w11a_n3.vhd 1181 2019-07-08 17:00:50Z mueller $ -- SPDX-License-Identifier: GPL-3.0-or-later -- Copyright 2011-2019 by Walter F.J. Mueller <[email protected]> -- ------------------------------------------------------------------------------ -- Module Name: sys_w11a_n3 - syn -- Description: w11a test design for nexys3 -- -- Dependencies: vlib/xlib/s6_cmt_sfs -- vlib/genlib/clkdivce -- bplib/bpgen/bp_rs232_2l4l_iob -- bplib/fx2rlink/rlink_sp1c_fx2 -- w11a/pdp11_sys70 -- ibus/ibdr_maxisys -- bplib/nxcramlib/nx_cram_memctl_as -- bplib/fx2rlink/ioleds_sp1c_fx2 -- w11a/pdp11_hio70 -- bplib/bpgen/sn_humanio_rbus -- vlib/rbus/rb_sres_or_2 -- -- Test bench: tb/tb_sys_w11a_n3 -- -- Target Devices: generic -- Tool versions: xst 13.1-14.7; ghdl 0.29-0.35 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri -- 2019-05-19 1150 14.7 131013 xc6slx16-2 3167 6052 248 2130 ok: +dz11 93% -- 2019-05-01 1143 14.7 131013 xc6slx16-2 3062 5761 232 2057 ok: +m9312 90% -- 2019-04-27 1140 14.7 131013 xc6slx16-2 3053 5742 232 2050 ok: +dlbuf 89% -- 2019-04-24 1137 14.7 131013 xc6slx16-2 3049 5727 223 2045 ok: +pcbuf 89% -- 2019-03-17 1123 14.7 131013 xc6slx16-2 3059 5722 212 2041 ok: +lpbuf 89% -- 2019-03-02 1116 14.7 131013 xc6slx16-2 3048 5741 212 2030 ok: +ibtst 89% -- 2019-01-27 1108 14.7 131013 xc6slx16-2 2979 5542 201 2018 ok: -iist 88% -- 2018-10-13 1055 14.7 131013 xc6slx16-2 3057 5822 201 2064 ok: +dmpcnt 90% -- 2018-09-15 1045 14.7 131013 xc6slx16-2 2851 5453 177 1932 ok: +KW11P 84% -- 2017-03-30 888 14.7 131013 xc6slx16-2 2790 5352 177 1943 ok: +fx2dbg 85% -- 2017-03-04 858 14.7 131013 xc6slx16-2 2717 5273 177 1885 ok: +deuna 82% -- 2017-01-29 846 14.7 131013 xc6slx16-2 2680 5208 177 1860 ok: +int24 81% -- 2015-07-05 698 14.7 131013 xc6slx16-2 2500 4852 161 1782 ok: +dmhbpt 78% -- 2015-07-05 697 14.7 131013 xc6slx16-2 2428 4786 161 1756 ok: +dmcmon 77% -- 2015-06-27 695 14.7 131013 xc6slx16-2 2281 4638 161 1714 ok: +dmscnt 75% -- 2015-06-21 692 14.7 131013 xc6slx16-2 2192 4518 161 1584 ok: rhrp fixes -- 2015-06-04 686 14.7 131013 xc6slx16-2 2189 4492 161 1543 ok: +TM11 67% -- 2015-05-14 680 14.7 131013 xc6slx16-2 2120 4443 161 1546 ok: +ibmon 67% -- 2015-04-06 664 14.7 131013 xc6slx16-2 1991 4350 167 1489 ok: +RHRP 65% -- 2015-02-21 649 14.7 131013 xc6slx16-2 1819 3905 160 1380 ok: +RL11 61% -- 2014-12-22 619 14.7 131013 xc6slx16-2 1742 3767 150 1350 ok: +rbmon -- 2014-12-20 614 14.7 131013 xc6slx16-2 1640 3692 150 1297 ok: -RL11,rlv4 -- 2014-06-08 561 14.7 131013 xc6slx16-2 1531 3500 142 1165 ok: +RL11 -- 2014-05-29 556 14.7 131013 xc6slx16-2 1459 3342 128 1154 ok: 51% -- 2013-04-21 509 13.3 O76d xc6slx16-2 1516 3274 140 1184 ok: now + FX2 ! -- 2011-12-18 440 13.1 O40d xc6slx16-2 1441 3161 96 1084 ok: LP+PC+DL+II -- 2011-11-20 430 13.1 O40d xc6slx16-2 1412 3206 84 1063 ok: LP+PC+DL+II -- -- Revision History: -- Date Rev Version Comment -- 2018-10-13 1055 2.3 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT -- 2017-04-30 888 2.2 use SWI(7:6) to allow fx2 debug via LEDs -- 2016-03-19 748 2.1.1 define rlink SYSID -- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul -- 2015-05-01 672 2.0 use pdp11_sys70 and pdp11_hio70 -- 2015-04-24 668 1.8.3 added ibd_ibmon -- 2015-04-11 666 1.8.2 rearrange XON handling -- 2015-02-21 649 1.8.1 use ioleds_sp1c,pdp11_(statleds,ledmux,dspmux) -- 2015-02-15 647 1.8 drop bram and minisys options -- 2014-12-24 620 1.7.2 relocate ibus window and hio rbus address -- 2014-12-22 619 1.7.1 add rbus monitor rbd_rbmon -- 2014-08-28 588 1.7 use new rlink v4 iface generics and 4 bit STAT -- 2014-08-15 583 1.6 rb_mreq addr now 16 bit -- 2013-10-06 538 1.5 pll support, use clksys_vcodivide ect -- 2013-04-21 509 1.4 added fx2 (cuff) support -- 2011-12-18 440 1.0.4 use rlink_sp1c -- 2011-12-04 435 1.0.3 increase ATOWIDTH 6->7 (saw i/o timeouts on wblks) -- 2011-11-26 433 1.0.2 use nx_cram_(dummy|memctl_as) now -- 2011-11-23 432 1.0.1 fixup PPCM handling -- 2011-11-20 430 1.0 Initial version (derived from sys_w11a_n2) ------------------------------------------------------------------------------ -- -- w11a test design for nexys3 -- w11a + rlink + serport -- -- Usage of Nexys 3 Switches, Buttons, LEDs: -- -- SWI(7:6): select LED display mode -- 0x w11 sys70 LED display (further controlled by SWI(3)) -- 10 FX2 debug: fx2 fifo states -- 11 FX2 debug: fx2 fsm states -- (5:4): select DSP -- 00 abclkdiv & abclkdiv_f -- 01 PC -- 10 DISPREG -- 11 DR emulation -- (3): select LED display -- 0 overall status -- 1 DR emulation -- (2) 0 -> int/ext RS242 port for rlink -- 1 -> use USB interface for rlink -- (1): 1 enable XON -- (0): 0 -> main board RS232 port -- 1 -> Pmod B/top RS232 port -- -- LEDs if SWI(7) = 0 and SWI(3) = 1 -- (7:0) DR emulation; shows R0(lower 8 bits) during wait like 11/45+70 -- -- LEDs if SWI(7) = 0 and SWI(3) = 0 -- (7) MEM_ACT_W -- (6) MEM_ACT_R -- (5) cmdbusy (all rlink access, mostly rdma) -- (4:0) if cpugo=1 show cpu mode activity -- (4) kernel mode, pri>0 -- (3) kernel mode, pri=0 -- (2) kernel mode, wait -- (1) supervisor mode -- (0) user mode -- if cpugo=0 shows cpurust -- (4) '1' -- (3:0) cpurust code -- -- LEDs if SWI(7) = 1 -- (7) fifo_ep4 -- (6) fifo_ep6 -- (5) fsm_rx -- (4) fsm_tx -- LEDs if SWI(7) = 1 and SWI(6) = 0 -- (3) flag_ep4_empty -- (2) flag_ep4_almost -- (1) flag_ep6_full -- (0) flag_ep6_almost -- LEDs if SWI(7) = 1 and SWI(6) = 1 -- (3) fsm_idle -- (2) fsm_prep -- (1) fsm_disp -- (0) fsm_pipe -- -- DP(3:0) shows IO activity -- if SWI(2)=0 (serport) -- (3): not SER_MONI.txok (shows tx back pressure) -- (2): SER_MONI.txact (shows tx activity) -- (1): not SER_MONI.rxok (shows rx back pressure) -- (0): SER_MONI.rxact (shows rx activity) -- if SWI(2)=1 (fx2-usb) -- (3): RB_SRES.busy (shows rbus back pressure) -- (2): RLB_TXBUSY (shows tx back pressure) -- (1): RLB_TXENA (shows tx activity) -- (0): RLB_RXVAL (shows rx activity) -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; use work.xlib.all; use work.genlib.all; use work.serportlib.all; use work.rblib.all; use work.rlinklib.all; use work.fx2lib.all; use work.fx2rlinklib.all; use work.bpgenlib.all; use work.bpgenrbuslib.all; use work.nxcramlib.all; use work.iblib.all; use work.ibdlib.all; use work.pdp11.all; use work.sys_conf.all; -- ---------------------------------------------------------------------------- entity sys_w11a_n3 is -- top level -- implements nexys3_fusp_cuff_aif port ( I_CLK100 : in slbit; -- 100 MHz clock I_RXD : in slbit; -- receive data (board view) O_TXD : out slbit; -- transmit data (board view) I_SWI : in slv8; -- n3 switches I_BTN : in slv5; -- n3 buttons O_LED : out slv8; -- n3 leds O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) O_MEM_WE_N : out slbit; -- cram: write enable (act.low) O_MEM_OE_N : out slbit; -- cram: output enable (act.low) O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) O_MEM_CLK : out slbit; -- cram: clock O_MEM_CRE : out slbit; -- cram: command register enable I_MEM_WAIT : in slbit; -- cram: mem wait O_MEM_ADDR : out slv23; -- cram: address lines IO_MEM_DATA : inout slv16; -- cram: data lines O_PPCM_CE_N : out slbit; -- ppcm: ... O_PPCM_RST_N : out slbit; -- ppcm: ... O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n I_FUSP_RXD : in slbit; -- fusp: rs232 rx O_FUSP_TXD : out slbit; -- fusp: rs232 tx I_FX2_IFCLK : in slbit; -- fx2: interface clock O_FX2_FIFO : out slv2; -- fx2: fifo address I_FX2_FLAG : in slv4; -- fx2: fifo flags O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low) O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low) O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low) O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low) IO_FX2_DATA : inout slv8 -- fx2: data lines ); end sys_w11a_n3; architecture syn of sys_w11a_n3 is signal CLK : slbit := '0'; signal RESET : slbit := '0'; signal CE_USEC : slbit := '0'; signal CE_MSEC : slbit := '0'; signal RXD : slbit := '1'; signal TXD : slbit := '0'; signal RTS_N : slbit := '0'; signal CTS_N : slbit := '0'; signal RB_MREQ : rb_mreq_type := rb_mreq_init; signal RB_SRES : rb_sres_type := rb_sres_init; signal RB_SRES_CPU : rb_sres_type := rb_sres_init; signal RB_SRES_HIO : rb_sres_type := rb_sres_init; signal RB_LAM : slv16 := (others=>'0'); signal RB_STAT : slv4 := (others=>'0'); signal RLB_MONI : rlb_moni_type := rlb_moni_init; signal SER_MONI : serport_moni_type := serport_moni_init; signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init; signal GRESET : slbit := '0'; -- general reset (from rbus) signal CRESET : slbit := '0'; -- cpu reset (from cp) signal BRESET : slbit := '0'; -- bus reset (from cp or cpu) signal PERFEXT : slv8 := (others=>'0'); signal EI_PRI : slv3 := (others=>'0'); signal EI_VECT : slv9_2 := (others=>'0'); signal EI_ACKM : slbit := '0'; signal CP_STAT : cp_stat_type := cp_stat_init; signal DM_STAT_EXP : dm_stat_exp_type := dm_stat_exp_init; signal MEM_REQ : slbit := '0'; signal MEM_WE : slbit := '0'; signal MEM_BUSY : slbit := '0'; signal MEM_ACK_R : slbit := '0'; signal MEM_ACT_R : slbit := '0'; signal MEM_ACT_W : slbit := '0'; signal MEM_ADDR : slv20 := (others=>'0'); signal MEM_BE : slv4 := (others=>'0'); signal MEM_DI : slv32 := (others=>'0'); signal MEM_DO : slv32 := (others=>'0'); signal MEM_ADDR_EXT : slv22 := (others=>'0'); signal IB_MREQ : ib_mreq_type := ib_mreq_init; signal IB_SRES_IBDR : ib_sres_type := ib_sres_init; signal DISPREG : slv16 := (others=>'0'); signal ABCLKDIV : slv16 := (others=>'0'); signal LED70 : slv8 := (others=>'0'); signal SWI : slv8 := (others=>'0'); signal BTN : slv5 := (others=>'0'); signal LED : slv8 := (others=>'0'); signal DSP_DAT : slv16 := (others=>'0'); signal DSP_DP : slv4 := (others=>'0'); constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx constant rbaddr_hio : slv16 := x"fef0"; -- fef0/0008: 1111 1110 1111 0xxx constant sysid_proj : slv16 := x"0201"; -- w11a constant sysid_board : slv8 := x"03"; -- nexys3 constant sysid_vers : slv8 := x"00"; begin assert (sys_conf_clksys mod 1000000) = 0 report "assert sys_conf_clksys on MHz grid" severity failure; GEN_CLKSYS : s6_cmt_sfs -- clock generator ------------------- generic map ( VCO_DIVIDE => sys_conf_clksys_vcodivide, VCO_MULTIPLY => sys_conf_clksys_vcomultiply, OUT_DIVIDE => sys_conf_clksys_outdivide, CLKIN_PERIOD => 10.0, CLKIN_JITTER => 0.01, STARTUP_WAIT => false, GEN_TYPE => sys_conf_clksys_gentype) port map ( CLKIN => I_CLK100, CLKFX => CLK, LOCKED => open ); CLKDIV : clkdivce -- usec/msec clock divider ----------- generic map ( CDUWIDTH => 7, USECDIV => sys_conf_clksys_mhz, MSECDIV => 1000) port map ( CLK => CLK, CE_USEC => CE_USEC, CE_MSEC => CE_MSEC ); IOB_RS232 : bp_rs232_2l4l_iob -- serport iob/switch ---------------- port map ( CLK => CLK, RESET => '0', SEL => SWI(0), RXD => RXD, TXD => TXD, CTS_N => CTS_N, RTS_N => RTS_N, I_RXD0 => I_RXD, O_TXD0 => O_TXD, I_RXD1 => I_FUSP_RXD, O_TXD1 => O_FUSP_TXD, I_CTS1_N => I_FUSP_CTS_N, O_RTS1_N => O_FUSP_RTS_N ); RLINK : rlink_sp1c_fx2 -- rlink for serport + fx2 ----------- generic map ( BTOWIDTH => 7, -- 128 cycles access timeout RTAWIDTH => 12, SYSID => (others=>'0'), IFAWIDTH => 5, -- 32 word input fifo OFAWIDTH => 5, -- 32 word output fifo PETOWIDTH => sys_conf_fx2_petowidth, CCWIDTH => sys_conf_fx2_ccwidth, ENAPIN_RLMON => sbcntl_sbf_rlmon, ENAPIN_RBMON => sbcntl_sbf_rbmon, CDWIDTH => 13, CDINIT => sys_conf_ser2rri_cdinit, RBMON_AWIDTH => sys_conf_rbmon_awidth, RBMON_RBADDR => rbaddr_rbmon) port map ( CLK => CLK, CE_USEC => CE_USEC, CE_MSEC => CE_MSEC, CE_INT => CE_MSEC, RESET => RESET, ENAXON => SWI(1), ENAFX2 => SWI(2), RXSD => RXD, TXSD => TXD, CTS_N => CTS_N, RTS_N => RTS_N, RB_MREQ => RB_MREQ, RB_SRES => RB_SRES, RB_LAM => RB_LAM, RB_STAT => RB_STAT, RL_MONI => open, RLB_MONI => RLB_MONI, SER_MONI => SER_MONI, FX2_MONI => FX2_MONI, I_FX2_IFCLK => I_FX2_IFCLK, O_FX2_FIFO => O_FX2_FIFO, I_FX2_FLAG => I_FX2_FLAG, O_FX2_SLRD_N => O_FX2_SLRD_N, O_FX2_SLWR_N => O_FX2_SLWR_N, O_FX2_SLOE_N => O_FX2_SLOE_N, O_FX2_PKTEND_N => O_FX2_PKTEND_N, IO_FX2_DATA => IO_FX2_DATA ); PERFEXT(0) <= '0'; -- unused (ext_rdrhit) PERFEXT(1) <= '0'; -- unused (ext_wrrhit) PERFEXT(2) <= '0'; -- unused (ext_wrflush) PERFEXT(3) <= RLB_MONI.rxval and not RLB_MONI.rxhold; -- ext_rlrxact PERFEXT(4) <= RLB_MONI.rxhold; -- ext_rlrxback PERFEXT(5) <= RLB_MONI.txena and not RLB_MONI.txbusy; -- ext_rltxact PERFEXT(6) <= RLB_MONI.txbusy; -- ext_rltxback PERFEXT(7) <= CE_USEC; -- ext_usec SYS70 : pdp11_sys70 -- 1 cpu system ---------------------- port map ( CLK => CLK, RESET => RESET, RB_MREQ => RB_MREQ, RB_SRES => RB_SRES_CPU, RB_STAT => RB_STAT, RB_LAM_CPU => RB_LAM(0), GRESET => GRESET, CRESET => CRESET, BRESET => BRESET, CP_STAT => CP_STAT, EI_PRI => EI_PRI, EI_VECT => EI_VECT, EI_ACKM => EI_ACKM, PERFEXT => PERFEXT, IB_MREQ => IB_MREQ, IB_SRES => IB_SRES_IBDR, MEM_REQ => MEM_REQ, MEM_WE => MEM_WE, MEM_BUSY => MEM_BUSY, MEM_ACK_R => MEM_ACK_R, MEM_ADDR => MEM_ADDR, MEM_BE => MEM_BE, MEM_DI => MEM_DI, MEM_DO => MEM_DO, DM_STAT_EXP => DM_STAT_EXP ); IBDR_SYS : ibdr_maxisys -- IO system ------------------------- port map ( CLK => CLK, CE_USEC => CE_USEC, CE_MSEC => CE_MSEC, RESET => GRESET, BRESET => BRESET, ITIMER => DM_STAT_EXP.se_itimer, IDEC => DM_STAT_EXP.se_idec, CPUSUSP => CP_STAT.cpususp, RB_LAM => RB_LAM(15 downto 1), IB_MREQ => IB_MREQ, IB_SRES => IB_SRES_IBDR, EI_ACKM => EI_ACKM, EI_PRI => EI_PRI, EI_VECT => EI_VECT, DISPREG => DISPREG ); MEM_ADDR_EXT <= "00" & MEM_ADDR; -- just use lower 4 MB (of 16 MB) CRAMCTL: nx_cram_memctl_as -- memory controller ----------------- generic map ( READ0DELAY => sys_conf_memctl_read0delay, READ1DELAY => sys_conf_memctl_read1delay, WRITEDELAY => sys_conf_memctl_writedelay) port map ( CLK => CLK, RESET => GRESET, REQ => MEM_REQ, WE => MEM_WE, BUSY => MEM_BUSY, ACK_R => MEM_ACK_R, ACK_W => open, ACT_R => MEM_ACT_R, ACT_W => MEM_ACT_W, ADDR => MEM_ADDR_EXT, BE => MEM_BE, DI => MEM_DI, DO => MEM_DO, O_MEM_CE_N => O_MEM_CE_N, O_MEM_BE_N => O_MEM_BE_N, O_MEM_WE_N => O_MEM_WE_N, O_MEM_OE_N => O_MEM_OE_N, O_MEM_ADV_N => O_MEM_ADV_N, O_MEM_CLK => O_MEM_CLK, O_MEM_CRE => O_MEM_CRE, I_MEM_WAIT => I_MEM_WAIT, O_MEM_ADDR => O_MEM_ADDR, IO_MEM_DATA => IO_MEM_DATA ); O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled O_PPCM_RST_N <= '1'; -- LED_IO : ioleds_sp1c_fx2 -- hio leds from serport or fx2 ------ port map ( CLK => CLK, CE_USEC => CE_USEC, RESET => GRESET, ENAFX2 => SWI(2), RB_SRES => RB_SRES, RLB_MONI => RLB_MONI, SER_MONI => SER_MONI, IOLEDS => DSP_DP ); ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f; HIO70 : pdp11_hio70 -- hio from sys70 -------------------- generic map ( LWIDTH => LED'length, DCWIDTH => 2) port map ( SEL_LED => SWI(3), SEL_DSP => SWI(5 downto 4), MEM_ACT_R => MEM_ACT_R, MEM_ACT_W => MEM_ACT_W, CP_STAT => CP_STAT, DM_STAT_EXP => DM_STAT_EXP, ABCLKDIV => ABCLKDIV, DISPREG => DISPREG, LED => LED70, DSP_DAT => DSP_DAT ); proc_fx2leds: process (SWI, LED70, FX2_MONI) -- hio LED handler ------------ variable iled : slv8 := (others=>'0'); begin iled := (others=>'0'); if SWI(7) = '0' then iled := LED70; else iled(7) := FX2_MONI.fifo_ep4; iled(6) := FX2_MONI.fifo_ep6; iled(5) := FX2_MONI.fsm_rx; iled(4) := FX2_MONI.fsm_tx; if SWI(6) = '0' then iled(3) := FX2_MONI.flag_ep4_empty; iled(2) := FX2_MONI.flag_ep4_almost; iled(1) := FX2_MONI.flag_ep6_full; iled(0) := FX2_MONI.flag_ep6_almost; else iled(3) := FX2_MONI.fsm_idle; iled(2) := FX2_MONI.fsm_prep; iled(1) := FX2_MONI.fsm_disp; iled(0) := FX2_MONI.fsm_pipe; end if; end if; LED <= iled; end process proc_fx2leds; HIO : sn_humanio_rbus -- hio manager ----------------------- generic map ( BWIDTH => 5, DEBOUNCE => sys_conf_hio_debounce, RB_ADDR => rbaddr_hio) port map ( CLK => CLK, RESET => RESET, CE_MSEC => CE_MSEC, RB_MREQ => RB_MREQ, RB_SRES => RB_SRES_HIO, SWI => SWI, BTN => BTN, LED => LED, DSP_DAT => DSP_DAT, DSP_DP => DSP_DP, I_SWI => I_SWI, I_BTN => I_BTN, O_LED => O_LED, O_ANO_N => O_ANO_N, O_SEG_N => O_SEG_N ); RB_SRES_OR : rb_sres_or_2 -- rbus or --------------------------- port map ( RB_SRES_1 => RB_SRES_CPU, RB_SRES_2 => RB_SRES_HIO, RB_SRES_OR => RB_SRES ); end syn;

-- ------------------------------------------------------------- -- -- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF1_3_block2.vhd -- Created: 2017-03-27 23:13:58 -- -- Generated by MATLAB 9.1 and HDL Coder 3.9 -- -- ------------------------------------------------------------- -- ------------------------------------------------------------- -- -- Module: RADIX22FFT_SDNF1_3_block2 -- Source Path: fft_16_bit/FFT HDL Optimized/RADIX22FFT_SDNF1_3 -- Hierarchy Level: 2 -- -- ------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; ENTITY RADIX22FFT_SDNF1_3_block2 IS PORT( clk : IN std_logic; reset : IN std_logic; enb : IN std_logic; twdlXdin_6_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_6_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_8_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_8_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20 twdlXdin_1_vld : IN std_logic; softReset : IN std_logic; dout_7_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_7_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_8_re : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_8_im : OUT std_logic_vector(19 DOWNTO 0); -- sfix20 dout_7_vld : OUT std_logic ); END RADIX22FFT_SDNF1_3_block2; ARCHITECTURE rtl OF RADIX22FFT_SDNF1_3_block2 IS -- Signals SIGNAL twdlXdin_6_re_signed : signed(19 DOWNTO 0); -- sfix20 SIGNAL twdlXdin_6_im_signed : signed(19 DOWNTO 0); -- sfix20 SIGNAL twdlXdin_8_re_signed : signed(19 DOWNTO 0); -- sfix20 SIGNAL twdlXdin_8_im_signed : signed(19 DOWNTO 0); -- sfix20 SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(20 DOWNTO 0); -- sfix21 SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(20 DOWNTO 0); -- sfix21 SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(20 DOWNTO 0); -- sfix21 SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(20 DOWNTO 0); -- sfix21 SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic; SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(20 DOWNTO 0); -- sfix21 SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(20 DOWNTO 0); -- sfix21 SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(20 DOWNTO 0); -- sfix21 SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(20 DOWNTO 0); -- sfix21 SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic; SIGNAL dout_7_re_tmp : signed(19 DOWNTO 0); -- sfix20 SIGNAL dout_7_im_tmp : signed(19 DOWNTO 0); -- sfix20 SIGNAL dout_8_re_tmp : signed(19 DOWNTO 0); -- sfix20 SIGNAL dout_8_im_tmp : signed(19 DOWNTO 0); -- sfix20 BEGIN twdlXdin_6_re_signed <= signed(twdlXdin_6_re); twdlXdin_6_im_signed <= signed(twdlXdin_6_im); twdlXdin_8_re_signed <= signed(twdlXdin_8_re); twdlXdin_8_im_signed <= signed(twdlXdin_8_im); -- Radix22ButterflyG1_NF Radix22ButterflyG1_NF_process : PROCESS (clk, reset) BEGIN IF reset = '1' THEN Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#000000#, 21); Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#000000#, 21); Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#000000#, 21); Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#000000#, 21); Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0'; ELSIF clk'EVENT AND clk = '1' THEN IF enb = '1' THEN Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next; Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next; Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next; Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next; Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next; END IF; END IF; END PROCESS Radix22ButterflyG1_NF_process; Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg, Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg, Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_6_re_signed, twdlXdin_6_im_signed, twdlXdin_8_re_signed, twdlXdin_8_im_signed, twdlXdin_1_vld) BEGIN Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg; Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg; Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg; Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg; Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld; IF twdlXdin_1_vld = '1' THEN Radix22ButterflyG1_NF_btf1_re_reg_next <= resize(twdlXdin_6_re_signed, 21) + resize(twdlXdin_8_re_signed, 21); Radix22ButterflyG1_NF_btf2_re_reg_next <= resize(twdlXdin_6_re_signed, 21) - resize(twdlXdin_8_re_signed, 21); Radix22ButterflyG1_NF_btf1_im_reg_next <= resize(twdlXdin_6_im_signed, 21) + resize(twdlXdin_8_im_signed, 21); Radix22ButterflyG1_NF_btf2_im_reg_next <= resize(twdlXdin_6_im_signed, 21) - resize(twdlXdin_8_im_signed, 21); END IF; dout_7_re_tmp <= Radix22ButterflyG1_NF_btf1_re_reg(19 DOWNTO 0); dout_7_im_tmp <= Radix22ButterflyG1_NF_btf1_im_reg(19 DOWNTO 0); dout_8_re_tmp <= Radix22ButterflyG1_NF_btf2_re_reg(19 DOWNTO 0); dout_8_im_tmp <= Radix22ButterflyG1_NF_btf2_im_reg(19 DOWNTO 0); dout_7_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1; END PROCESS Radix22ButterflyG1_NF_output; dout_7_re <= std_logic_vector(dout_7_re_tmp); dout_7_im <= std_logic_vector(dout_7_im_tmp); dout_8_re <= std_logic_vector(dout_8_re_tmp); dout_8_im <= std_logic_vector(dout_8_im_tmp); END rtl;

--! --! Copyright (C) 2012 - 2014 Creonic GmbH --! --! This file is part of the Creonic Viterbi Decoder, which is distributed --! under the terms of the GNU General Public License version 2. --! --! @file --! @brief AXI4-Stream buffer that allows to buffer the accept-signal. --! @author Matthias Alles --! @date 2012/04/18 --! --! @details --! One problem when concatenating multiple AXI4-Stream builind blocks is that --! the accept signal has to pass from the very last component to the input --! of the very first component. Only then it is possible to have an interruption --! free data processing within the whole chain. The drawback of this approach is --! that the accept signal has a long path and high fanouts. --! This entity allows to use registers on the accept signals by introducing buffers --! for storing the input values. It should improve timing of bigger building blocks. --! library ieee; use ieee.std_logic_1164.all; entity axi4s_buffer is generic ( DATA_WIDTH : natural := 1 ); port ( clk : in std_logic; rst : in std_logic; -- Input data handling ---------------------- input : in std_logic_vector(DATA_WIDTH - 1 downto 0); input_valid : in std_logic; input_last : in std_logic; input_accept : out std_logic; -- Output data handling ----------------------- output : out std_logic_vector(DATA_WIDTH - 1 downto 0); output_valid : out std_logic; output_last : out std_logic; output_accept : in std_logic ); end entity axi4s_buffer; architecture rtl of axi4s_buffer is signal input_accept_int : std_logic; signal output_reg : std_logic_vector(DATA_WIDTH - 1 downto 0); signal output_last_reg : std_logic; signal output_valid_reg : std_logic; signal buffer_full : std_logic; signal buffer_data : std_logic_vector(DATA_WIDTH - 1 downto 0); signal buffer_last : std_logic; begin input_accept <= input_accept_int; output <= output_reg; output_last <= output_last_reg; output_valid <= output_valid_reg; -- -- This process registers all signals. -- No combinatorial logic is bypassed from input to output and vice versa. -- pr_reg: process(clk) is begin if rising_edge(clk) then if rst = '1' then output_reg <= (others => '0'); output_last_reg <= '0'; output_valid_reg <= '0'; input_accept_int <= '1'; buffer_full <= '0'; buffer_data <= (others => '0'); buffer_last <= '0'; else -- -- Data is coming, buf output data can't be sent => Store input data in buffer -- and remove input_accept signal! -- if input_valid = '1' and input_accept_int = '1' and output_valid_reg = '1' and output_accept = '0' then buffer_data <= input; buffer_last <= input_last; buffer_full <= '1'; input_accept_int <= '0'; end if; -- -- Output data is being read but there is data in the buffer waiting for being sent -- => Use the buffer data! -- if output_accept = '1' and output_valid_reg = '1' and buffer_full = '1' then output_reg <= buffer_data; output_last_reg <= buffer_last; output_valid_reg <= '1'; buffer_full <= '0'; input_accept_int <= '1'; -- -- Data is being read and buffer is empty => Use input data directly! -- Output register is empty => Use input data directly! -- elsif (output_accept = '1' and output_valid_reg = '1') or output_valid_reg = '0' then output_reg <= input; output_last_reg <= input_last; output_valid_reg <= input_valid; end if; end if; end if; end process pr_reg; end architecture rtl;

-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_06_tofpt.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $ -- $Revision: 1.1.1.1 $ -- -- --------------------------------------------------------------------- entity to_fp_test is end entity to_fp_test;

Library ieee; Use ieee.std_logic_1164.all; Use ieee.numeric_std.all; Entity System is Port(door: IN std_logic_vector(3 downto 0); ARM, clock : IN std_logic; ready, delay, SysArm, AlrOn: OUT std_logic); end System; Architecture Basic of System is Type StateName is (sysoff, syson, alr); signal Prest,NxtSt,sysoffnext,sysonnext,alrnext: StateName; begin sysoffnext <=syson when arm ='1' else sysoff; sysonnext <= sysoff when arm ='1' else alr when door /="0000" else syson; alrnext <= sysoff when arm ='1' else alr; NxtSt <= sysoffnext when prest = sysoff else sysonnext when prest = syson else alrnext; Prest <= NxtSt when Rising_edge(clock); ready <= '1' when door = "0000" else '0'; SysArm <= '1' when NxtSt = syson OR NxtSt = alr else '0'; AlrOn <= '1' when nxtSt = alr else '0' when NxtSt = sysoff OR nxtSt = syson; end Basic; Architecture thelayed of System is Component TenSecDelay is Port (load, clock: in std_logic; TC: out std_logic); End Component TenSecDelay; Type StateName is (sysoff, syson, alr); signal Prest,NxtSt,sysoffnext,sysonnext,alrnext: StateName; signal sload, sTC: std_logic; begin sysoffnext <=syson when arm ='1' else sysoff; sysonnext <= sysoff when arm ='1' else alr when (door /="0000" AND sTC ='0') else syson; alrnext <= sysoff when arm ='1' else alr; NxtSt <= sysoffnext when prest = sysoff else sysonnext when prest = syson else alrnext; Prest <= NxtSt when Rising_edge(clock); ready <= '1' when door = "0000" else '0'; SysArm <= '1' when NxtSt = syson OR NxtSt = alr else '0'; AlrOn <= '1' when (prest = alr AND sTC ='0') else '0'; --when NxtSt = sysoff OR nxtSt = syson; delay <= stc; sload<= '1' when (prest = sysoff and nxtst = syson) OR (prest = syson AND door /="0000") else '0'; stage0: entity work.tensecdelay port map(load=>sload, clock=> clock, TC=>sTC); end thelayed;

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 10:51:25 10/20/2017 -- Design Name: -- Module Name: MuxRF - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity MuxRF is Port ( Rd : in STD_LOGIC_VECTOR (5 downto 0); O7 : in STD_LOGIC_VECTOR (5 downto 0); RFDEST : in STD_LOGIC; nRD : out STD_LOGIC_VECTOR (5 downto 0)); end MuxRF; architecture Behavioral of MuxRF is begin process (Rd,O7,RFDEST) begin case (RFDEST) is when '0' => nRD <= Rd; when '1' => nRD <= O7; when others => nRD <= Rd; end case; end process; end Behavioral;

------------------------------------------------------------------------------- -- gpio_core - entity/architecture pair ------------------------------------------------------------------------------- -- *************************************************************************** -- DISCLAIMER OF LIABILITY -- -- This file contains proprietary and confidential information of -- Xilinx, Inc. ("Xilinx"), that is distributed under a license -- from Xilinx, and may be used, copied and/or disclosed only -- pursuant to the terms of a valid license agreement with Xilinx. -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx -- does not warrant that functions included in the Materials will -- meet the requirements of Licensee, or that the operation of the -- Materials will be uninterrupted or error-free, or that defects -- in the Materials will be corrected. Furthermore, Xilinx does -- not warrant or make any representations regarding use, or the -- results of the use, of the Materials in terms of correctness, -- accuracy, reliability or otherwise. -- -- Xilinx products are not designed or intended to be fail-safe, -- or for use in any application requiring fail-safe performance, -- such as life-support or safety devices or systems, Class III -- medical devices, nuclear facilities, applications related to -- the deployment of airbags, or any other applications that could -- lead to death, personal injury or severe property or -- environmental damage (individually and collectively, "critical -- applications"). Customer assumes the sole risk and liability -- of any use of Xilinx products in critical applications, -- subject only to applicable laws and regulations governing -- limitations on product liability. -- -- Copyright 2009 Xilinx, Inc. -- All rights reserved. -- -- This disclaimer and copyright notice must be retained as part -- of this file at all times. -- *************************************************************************** -- ------------------------------------------------------------------------------- -- Filename: gpio_core.vhd -- Version: v1.01a -- Description: General Purpose I/O for AXI Interface -- ------------------------------------------------------------------------------- -- Structure: -- axi_gpio.vhd -- -- axi_lite_ipif.vhd -- -- interrupt_control.vhd -- -- gpio_core.vhd -- ------------------------------------------------------------------------------- -- -- Author: KSB -- History: -- ~~~~~~~~~~~~~~ -- KSB 09/15/09 -- ^^^^^^^^^^^^^^ -- ~~~~~~~~~~~~~~ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_cmb" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; library lib_cdc_v1_0_2; ------------------------------------------------------------------------------- -- Definition of Generics : -- ------------------------------------------------------------------------------- -- C_DW -- Data width of PLB BUS. -- C_AW -- Address width of PLB BUS. -- C_GPIO_WIDTH -- GPIO Data Bus width. -- C_GPIO2_WIDTH -- GPIO2 Data Bus width. -- C_INTERRUPT_PRESENT -- GPIO Interrupt. -- C_DOUT_DEFAULT -- GPIO_DATA Register reset value. -- C_TRI_DEFAULT -- GPIO_TRI Register reset value. -- C_IS_DUAL -- Dual Channel GPIO. -- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value. -- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value. -- C_FAMILY -- XILINX FPGA family ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Definition of Ports -- ------------------------------------------------------------------------------- -- Clk -- Input clock -- Rst -- Reset -- ABus_Reg -- Bus to IP address -- BE_Reg -- Bus to IP byte enables -- DBus_Reg -- Bus to IP data bus -- RNW_Reg -- Bus to IP read write control -- GPIO_DBus -- IP to Bus data bus -- GPIO_xferAck -- GPIO transfer acknowledge -- GPIO_intr -- GPIO channel 1 interrupt to IPIC -- GPIO2_intr -- GPIO channel 2 interrupt to IPIC -- GPIO_Select -- GPIO select -- -- GPIO_IO_I -- Channel 1 General purpose I/O in port -- GPIO_IO_O -- Channel 1 General purpose I/O out port -- GPIO_IO_T -- Channel 1 General purpose I/O TRI-STATE control port -- GPIO2_IO_I -- Channel 2 General purpose I/O in port -- GPIO2_IO_O -- Channel 2 General purpose I/O out port -- GPIO2_IO_T -- Channel 2 General purpose I/O TRI-STATE control port ------------------------------------------------------------------------------- entity GPIO_Core is generic ( C_DW : integer := 32; C_AW : integer := 32; C_GPIO_WIDTH : integer := 32; C_GPIO2_WIDTH : integer := 32; C_MAX_GPIO_WIDTH : integer := 32; C_INTERRUPT_PRESENT : integer := 0; C_DOUT_DEFAULT : std_logic_vector (0 to 31) := X"0000_0000"; C_TRI_DEFAULT : std_logic_vector (0 to 31) := X"FFFF_FFFF"; C_IS_DUAL : integer := 0; C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013 C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013 C_ALL_INPUTS : integer range 0 to 1 := 0; C_ALL_INPUTS_2 : integer range 0 to 1 := 0; C_DOUT_DEFAULT_2 : std_logic_vector (0 to 31) := X"0000_0000"; C_TRI_DEFAULT_2 : std_logic_vector (0 to 31) := X"FFFF_FFFF"; C_FAMILY : string := "virtex7" ); port ( Clk : in std_logic; Rst : in std_logic; ABus_Reg : in std_logic_vector(0 to C_AW-1); BE_Reg : in std_logic_vector(0 to C_DW/8-1); DBus_Reg : in std_logic_vector(0 to C_MAX_GPIO_WIDTH-1); RNW_Reg : in std_logic; GPIO_DBus : out std_logic_vector(0 to C_DW-1); GPIO_xferAck : out std_logic; GPIO_intr : out std_logic; GPIO2_intr : out std_logic; GPIO_Select : in std_logic; GPIO_IO_I : in std_logic_vector(0 to C_GPIO_WIDTH-1); GPIO_IO_O : out std_logic_vector(0 to C_GPIO_WIDTH-1); GPIO_IO_T : out std_logic_vector(0 to C_GPIO_WIDTH-1); GPIO2_IO_I : in std_logic_vector(0 to C_GPIO2_WIDTH-1); GPIO2_IO_O : out std_logic_vector(0 to C_GPIO2_WIDTH-1); GPIO2_IO_T : out std_logic_vector(0 to C_GPIO2_WIDTH-1) ); end entity GPIO_Core; ------------------------------------------------------------------------------- -- Architecture section ------------------------------------------------------------------------------- architecture IMP of GPIO_Core is -- Pragma Added to supress synth warnings attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes"; ---------------------------------------------------------------------- -- Function for Reduction OR ---------------------------------------------------------------------- function or_reduce(l : std_logic_vector) return std_logic is variable v : std_logic := '0'; begin for i in l'range loop v := v or l(i); end loop; return v; end; --------------------------------------------------------------------- -- End of Function ------------------------------------------------------------------- --constant GPIO_G_W : integer = C_GPIO_WIDTH when (C_GPIO_WIDTH > C_GPIO2_WIDTH) else C_GPIO2_; signal gpio_Data_Select : std_logic_vector(0 to C_IS_DUAL); signal gpio_OE_Select : std_logic_vector(0 to C_IS_DUAL); signal Read_Reg_Rst : STD_LOGIC; signal Read_Reg_In : std_logic_vector(0 to C_GPIO_WIDTH-1); signal Read_Reg_CE : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_Data_Out : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_DOUT_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1); signal gpio_Data_In : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_in_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_in_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_io_i_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_io_i_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_OE : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_TRI_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1); signal GPIO_DBus_i : std_logic_vector(0 to C_DW-1); signal gpio_data_in_xor : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_data_in_xor_reg : std_logic_vector(0 to C_GPIO_WIDTH-1); signal or_ints : std_logic_vector(0 to 0); signal or_ints2 : std_logic_vector(0 to 0); signal iGPIO_xferAck : STD_LOGIC; signal gpio_xferAck_Reg : STD_LOGIC; signal dout_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1); signal tri_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1); signal reset_zeros : std_logic_vector(0 to C_GPIO_WIDTH-1); signal dout2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal tri2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal reset2_zeros : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio_reg_en : std_logic; begin -- architecture IMP reset_zeros <= (others => '0'); reset2_zeros <= (others => '0'); TIE_DEFAULTS_GENERATE : if C_DW >= C_GPIO_WIDTH generate SELECT_BITS_GENERATE : for i in 0 to C_GPIO_WIDTH-1 generate dout_default_i(i) <= C_DOUT_DEFAULT(i-C_GPIO_WIDTH+C_DW); tri_default_i(i) <= C_TRI_DEFAULT(i-C_GPIO_WIDTH+C_DW); end generate SELECT_BITS_GENERATE; end generate TIE_DEFAULTS_GENERATE; TIE_DEFAULTS_2_GENERATE : if C_DW >= C_GPIO2_WIDTH generate SELECT_BITS_2_GENERATE : for i in 0 to C_GPIO2_WIDTH-1 generate dout2_default_i(i) <= C_DOUT_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW); tri2_default_i(i) <= C_TRI_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW); end generate SELECT_BITS_2_GENERATE; end generate TIE_DEFAULTS_2_GENERATE; Read_Reg_Rst <= iGPIO_xferAck or gpio_xferAck_Reg or (not GPIO_Select) or (GPIO_Select and not RNW_Reg); gpio_reg_en <= GPIO_Select when (ABus_Reg(0) = '0') else '0'; ----------------------------------------------------------------------------- -- XFER_ACK_PROCESS ----------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ----------------------------------------------------------------------------- XFER_ACK_PROCESS : process (Clk) is begin if (Clk'EVENT and Clk = '1') then if (Rst = '1') then iGPIO_xferAck <= '0'; else iGPIO_xferAck <= GPIO_Select and not gpio_xferAck_Reg; if iGPIO_xferAck = '1' then iGPIO_xferAck <= '0'; end if; end if; end if; end process XFER_ACK_PROCESS; ----------------------------------------------------------------------------- -- DELAYED_XFER_ACK_PROCESS ----------------------------------------------------------------------------- -- Single Reg stage to make Transfer Ack period one clock pulse wide ----------------------------------------------------------------------------- DELAYED_XFER_ACK_PROCESS : process (Clk) is begin if (Clk'EVENT and Clk = '1') then if (Rst = '1') then gpio_xferAck_Reg <= '0'; else gpio_xferAck_Reg <= iGPIO_xferAck; end if; end if; end process DELAYED_XFER_ACK_PROCESS; GPIO_xferAck <= iGPIO_xferAck; ----------------------------------------------------------------------------- -- Drive GPIO interrupts to '0' when interrupt not present ----------------------------------------------------------------------------- DONT_GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate gpio_intr <= '0'; gpio2_intr <= '0'; end generate DONT_GEN_INTERRUPT; ---------------------------------------------------------------------------- -- When only one channel is used, the additional logic for the second -- channel ports is not present ----------------------------------------------------------------------------- Not_Dual : if (C_IS_DUAL = 0) generate GPIO2_IO_O <= C_DOUT_DEFAULT(0 to C_GPIO2_WIDTH-1); GPIO2_IO_T <= C_TRI_DEFAULT_2(0 to C_GPIO2_WIDTH-1); ALLOUT_ND : if (C_ALL_OUTPUTS = 1) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLOUT_ND; ALLIN1_ND : if (C_ALL_INPUTS = 1) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLIN1_ND; ALLOUT0_ND : if (C_ALL_OUTPUTS = 0 and C_ALL_INPUTS = 0) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else if (gpio_OE(i) = '0' and gpio_OE_Select(0) = '0')then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); end if; --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLOUT0_ND; TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0'); end generate TIE_DBUS_GENERATE; ----------------------------------------------------------------------------- -- GPIO_DBUS_PROCESS ----------------------------------------------------------------------------- -- This process generates the GPIO DATA BUS from the GPIO_DBUS_I based on -- the channel select signals ----------------------------------------------------------------------------- GPIO_DBus <= GPIO_DBus_i; ----------------------------------------------------------------------------- -- REG_SELECT_PROCESS ----------------------------------------------------------------------------- -- GPIO REGISTER selection decoder for single channel configuration ----------------------------------------------------------------------------- --REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is begin gpio_Data_Select(0) <= '0'; gpio_OE_Select(0) <= '0'; --if GPIO_Select = '1' then if gpio_reg_en = '1' then if (ABus_Reg(5) = '0') then case ABus_Reg(6) is -- bit A29 when '0' => gpio_Data_Select(0) <= '1'; when '1' => gpio_OE_Select(0) <= '1'; -- coverage off when others => null; -- coverage on end case; end if; end if; end process REG_SELECT_PROCESS; INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 0, C_VECTOR_WIDTH => C_GPIO_WIDTH, C_MTBF_STAGES => 4 ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => '0', prmry_vect_in => GPIO_IO_I, scndry_aclk => Clk, scndry_resetn => '0', scndry_out => open, scndry_vect_out => gpio_io_i_d2 ); --------------------------------------------------------------------------- -- GPIO_INDATA_BIRDIR_PROCESS --------------------------------------------------------------------------- -- Reading of channel 1 data from Bidirectional GPIO port -- to GPIO_DATA REGISTER --------------------------------------------------------------------------- GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then -- gpio_io_i_d1 <= GPIO_IO_I; -- gpio_io_i_d2 <= gpio_io_i_d1; gpio_Data_In <= gpio_io_i_d2; end if; end process GPIO_INDATA_BIRDIR_PROCESS; --------------------------------------------------------------------------- -- GPIO_OUTDATA_PROCESS --------------------------------------------------------------------------- -- Writing to Channel 1 GPIO_DATA REGISTER --------------------------------------------------------------------------- GPIO_OUTDATA_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio_Data_Out <= dout_default_i; elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO_WIDTH-1 loop gpio_Data_Out(i) <= DBus_Reg(i); end loop; end if; end if; end process GPIO_OUTDATA_PROCESS; --------------------------------------------------------------------------- -- READ_MUX_PROCESS --------------------------------------------------------------------------- -- Selects GPIO_TRI control or GPIO_DATA Register to be read --------------------------------------------------------------------------- READ_MUX_PROCESS : process (gpio_Data_In, gpio_Data_Select, gpio_OE, gpio_OE_Select,gpio_Data_Out) is begin Read_Reg_In <= (others => '0'); if gpio_Data_Select(0) = '1' then Read_Reg_In <= gpio_Data_In; --Read_Reg_In <= gpio_Data_In; elsif gpio_OE_Select(0) = '1' then Read_Reg_In <= gpio_OE; end if; end process READ_MUX_PROCESS; --------------------------------------------------------------------------- -- GPIO_OE_PROCESS --------------------------------------------------------------------------- -- Writing to Channel 1 GPIO_TRI Control REGISTER --------------------------------------------------------------------------- GPIO_OE_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio_OE <= tri_default_i; elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO_WIDTH-1 loop gpio_OE(i) <= DBus_Reg(i); end loop; end if; end if; end process GPIO_OE_PROCESS; GPIO_IO_O <= gpio_Data_Out; GPIO_IO_T <= gpio_OE; ---------------------------------------------------------------------------- -- INTERRUPT IS PRESENT ---------------------------------------------------------------------------- -- When the C_INTERRUPT_PRESENT=1, the interrupt is driven based on whether -- there is a change in the data coming in at the GPIO_IO_I port or GPIO_In -- port ---------------------------------------------------------------------------- GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 1) generate gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2; ------------------------------------------------------------------------- -- An interrupt conditon exists if there is a change on any bit. ------------------------------------------------------------------------- or_ints(0) <= or_reduce(gpio_data_in_xor_reg); ------------------------------------------------------------------------- -- Registering Interrupt condition ------------------------------------------------------------------------- REGISTER_XOR_INTR : process (Clk) is begin if (Clk'EVENT and Clk = '1') then if (Rst = '1') then gpio_data_in_xor_reg <= reset_zeros; GPIO_intr <= '0'; else gpio_data_in_xor_reg <= gpio_data_in_xor; GPIO_intr <= or_ints(0); end if; end if; end process REGISTER_XOR_INTR; gpio2_intr <= '0'; -- Channel 2 interrupt is driven low end generate GEN_INTERRUPT; end generate Not_Dual; ---)(------------------------------------------------------------------------ -- When both the channels are used, the additional logic for the second -- channel ports ----------------------------------------------------------------------------- Dual : if (C_IS_DUAL = 1) generate signal gpio2_Data_In : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_in_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_in_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_io_i_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_io_i_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_data_in_xor : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_data_in_xor_reg : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_Data_Out : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_DOUT_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1); signal gpio2_OE : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_TRI_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1); signal Read_Reg2_In : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal Read_Reg2_CE : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal GPIO2_DBus_i : std_logic_vector(0 to C_DW-1); begin ALLOUT0_ND_G0 : if (C_ALL_OUTPUTS = 0 and C_ALL_INPUTS = 0) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else if (gpio_OE(i) = '0' and gpio_OE_Select(0) = '0') then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); end if; --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLOUT0_ND_G0; ALLIN0_ND_G0 : if (C_ALL_INPUTS = 1) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLIN0_ND_G0; ALLOUT0_ND_G1 : if (C_ALL_OUTPUTS = 1) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate begin -------------------------------------------------------------------------- -- GPIO_DBUS_I_PROCESS -------------------------------------------------------------------------- -- This process generates the GPIO CHANNEL1 DATA BUS -------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLOUT0_ND_G1; TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0'); end generate TIE_DBUS_GENERATE; ALLIN0_ND_G2 : if (C_ALL_OUTPUTS_2 = 0 and C_ALL_INPUTS_2 = 1) generate READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate -------------------------------------------------------------------------- -- GPIO2_DBUS_I_PROCESS -------------------------------------------------------------------------- -- This process generates the GPIO CHANNEL2 DATA BUS -------------------------------------------------------------------------- GPIO2_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0'; else GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i); --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); end if; end if; end process; end generate READ_REG2_GEN; end generate ALLIN0_ND_G2; ALLOUT0_ND_G2 : if (C_ALL_OUTPUTS_2 = 0 and C_ALL_INPUTS_2 = 0) generate READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate -------------------------------------------------------------------------- -- GPIO2_DBUS_I_PROCESS -------------------------------------------------------------------------- -- This process generates the GPIO CHANNEL2 DATA BUS -------------------------------------------------------------------------- GPIO2_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0'; else if (gpio2_OE(i) = '0' and gpio_OE_Select(1) = '0') then GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i); else GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i); end if; -- GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i) when (gpio2_OE(i) = '1') else Read_Reg2_In(i); --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); end if; end if; end process; end generate READ_REG2_GEN; end generate ALLOUT0_ND_G2; ALLOUT1_ND_G2 : if (C_ALL_OUTPUTS_2 = 1) generate READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate -------------------------------------------------------------------------- -- GPIO2_DBUS_I_PROCESS -------------------------------------------------------------------------- -- This process generates the GPIO CHANNEL2 DATA BUS -------------------------------------------------------------------------- GPIO2_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0'; else GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i); end if; end if; end process; end generate READ_REG2_GEN; end generate ALLOUT1_ND_G2; TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0'); end generate TIE_DBUS2_GENERATE; --------------------------------------------------------------------------- -- GPIO_DBUS_PROCESS --------------------------------------------------------------------------- -- This process generates the GPIO DATA BUS from the GPIO_DBUS_I and -- GPIO2_DBUS_I based on which channel is selected --------------------------------------------------------------------------- GPIO_DBus <= GPIO_DBus_i when (((gpio_Data_Select(0) = '1') or (gpio_OE_Select(0) = '1')) and (RNW_Reg = '1')) else GPIO2_DBus_i; ----------------------------------------------------------------------------- -- DUAL_REG_SELECT_PROCESS ----------------------------------------------------------------------------- -- GPIO REGISTER selection decoder for Dual channel configuration ----------------------------------------------------------------------------- --DUAL_REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is DUAL_REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is variable ABus_reg_select : std_logic_vector(0 to 1); begin ABus_reg_select := ABus_Reg(5 to 6); gpio_Data_Select <= (others => '0'); gpio_OE_Select <= (others => '0'); --if GPIO_Select = '1' then if gpio_reg_en = '1' then -- case ABus_Reg(28 to 29) is -- bit A28,A29 for dual case ABus_reg_select is -- bit A28,A29 for dual when "00" => gpio_Data_Select(0) <= '1'; when "01" => gpio_OE_Select(0) <= '1'; when "10" => gpio_Data_Select(1) <= '1'; when "11" => gpio_OE_Select(1) <= '1'; -- coverage off when others => null; -- coverage on end case; end if; end process DUAL_REG_SELECT_PROCESS; --------------------------------------------------------------------------- -- GPIO_INDATA_BIRDIR_PROCESS --------------------------------------------------------------------------- -- Reading of channel 1 data from Bidirectional GPIO port -- to GPIO_DATA REGISTER --------------------------------------------------------------------------- INPUT_DOUBLE_REGS4 : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 0, C_VECTOR_WIDTH => C_GPIO_WIDTH, C_MTBF_STAGES => 4 ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => '0', prmry_vect_in => GPIO_IO_I, scndry_aclk => Clk, scndry_resetn => '0', scndry_out => open, scndry_vect_out => gpio_io_i_d2 ); GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then -- gpio_io_i_d1 <= GPIO_IO_I; -- gpio_io_i_d2 <= gpio_io_i_d1; --if (C_ALL_OUTPUTS = '1') then -- gpio_Data_In <= gpio_Data_Out; -- else gpio_Data_In <= gpio_io_i_d2; -- end if; end if; end process GPIO_INDATA_BIRDIR_PROCESS; INPUT_DOUBLE_REGS5 : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 0, C_VECTOR_WIDTH => C_GPIO2_WIDTH, C_MTBF_STAGES => 4 ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => '0', prmry_vect_in => GPIO2_IO_I, scndry_aclk => Clk, scndry_resetn => '0', scndry_out => open, scndry_vect_out => gpio2_io_i_d2 ); --------------------------------------------------------------------------- -- GPIO2_INDATA_BIRDIR_PROCESS --------------------------------------------------------------------------- -- Reading of channel 2 data from Bidirectional GPIO2 port -- to GPIO2_DATA REGISTER --------------------------------------------------------------------------- GPIO2_INDATA_BIRDIR_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then -- gpio2_io_i_d1 <= GPIO2_IO_I; -- gpio2_io_i_d2 <= gpio2_io_i_d1; -- if (C_ALL_OUTPUTS = '1') then -- gpio2_Data_In <= gpio2_Data_Out; -- else gpio2_Data_In <= gpio2_io_i_d2; -- end if; end if; end process GPIO2_INDATA_BIRDIR_PROCESS; --------------------------------------------------------------------------- -- GPIO_OUTDATA_PROCESS_0_0 --------------------------------------------------------------------------- -- Writing to Channel 1 GPIO_DATA REGISTER --------------------------------------------------------------------------- GPIO_OUTDATA_PROCESS_0_0 : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio_Data_Out <= dout_default_i; elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO_WIDTH-1 loop gpio_Data_Out(i) <= DBus_Reg(i); end loop; end if; end if; end process GPIO_OUTDATA_PROCESS_0_0; --------------------------------------------------------------------------- -- GPIO_OE_PROCESS_0_0 --------------------------------------------------------------------------- -- Writing to Channel 1 GPIO_TRI Control REGISTER --------------------------------------------------------------------------- GPIO_OE_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio_OE <= tri_default_i; elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO_WIDTH-1 loop gpio_OE(i) <= DBus_Reg(i); -- end if; end loop; end if; end if; end process GPIO_OE_PROCESS; --------------------------------------------------------------------------- -- GPIO2_OUTDATA_PROCESS_0_0 --------------------------------------------------------------------------- -- Writing to Channel 2 GPIO2_DATA REGISTER --------------------------------------------------------------------------- GPIO2_OUTDATA_PROCESS_0_0 : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio2_Data_Out <= dout2_default_i; elsif gpio_Data_Select(1) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO2_WIDTH-1 loop gpio2_Data_Out(i) <= DBus_Reg(i); -- end if; end loop; end if; end if; end process GPIO2_OUTDATA_PROCESS_0_0; --------------------------------------------------------------------------- -- GPIO2_OE_PROCESS_0_0 --------------------------------------------------------------------------- -- Writing to Channel 2 GPIO2_TRI Control REGISTER --------------------------------------------------------------------------- GPIO2_OE_PROCESS_0_0 : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio2_OE <= tri2_default_i; elsif gpio_OE_Select(1) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO2_WIDTH-1 loop gpio2_OE(i) <= DBus_Reg(i); end loop; end if; end if; end process GPIO2_OE_PROCESS_0_0; GPIO_IO_O <= gpio_Data_Out; GPIO_IO_T <= gpio_OE; GPIO2_IO_O <= gpio2_Data_Out; GPIO2_IO_T <= gpio2_OE; --------------------------------------------------------------------------- -- READ_MUX_PROCESS_0_0 --------------------------------------------------------------------------- -- Selects among Channel 1 GPIO_DATA ,GPIO_TRI and Channel 2 GPIO2_DATA -- GPIO2_TRI REGISTERS for reading --------------------------------------------------------------------------- READ_MUX_PROCESS_0_0 : process (gpio2_Data_In, gpio2_OE, gpio_Data_In, gpio_Data_Select, gpio_OE, gpio_OE_Select,gpio_Data_Out,gpio2_Data_Out) is begin Read_Reg_In <= (others => '0'); Read_Reg2_In <= (others => '0'); if gpio_Data_Select(0) = '1' then Read_Reg_In <= gpio_Data_In; --Read_Reg_In <= gpio_Data_In; elsif gpio_OE_Select(0) = '1' then Read_Reg_In <= gpio_OE; elsif gpio_Data_Select(1) = '1' then Read_Reg2_In <= gpio2_Data_In; --Read_Reg2_In <= gpio2_Data_In; --Read_Reg2_In<= gpio2_Data_In; elsif gpio_OE_Select(1) = '1' then Read_Reg2_In <= gpio2_OE; end if; end process READ_MUX_PROCESS_0_0; --------------------------------------------------------------------------- -- INTERRUPT IS PRESENT --------------------------------------------------------------------------- gen_interrupt_dual : if (C_INTERRUPT_PRESENT = 1) generate gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2; gpio2_data_in_xor <= gpio2_Data_In xor gpio2_io_i_d2; ------------------------------------------------------------------------- -- An interrupt conditon exists if there is a change any bit. ------------------------------------------------------------------------- or_ints(0) <= or_reduce(gpio_data_in_xor_reg); or_ints2(0) <= or_reduce(gpio2_data_in_xor_reg); ------------------------------------------------------------------------- -- Registering Interrupt condition ------------------------------------------------------------------------- REGISTER_XORs_INTRs : process (Clk) is begin if (Clk'EVENT and Clk = '1') then if (Rst = '1') then gpio_data_in_xor_reg <= reset_zeros; gpio2_data_in_xor_reg <= reset2_zeros; GPIO_intr <= '0'; GPIO2_intr <= '0'; else gpio_data_in_xor_reg <= gpio_data_in_xor; gpio2_data_in_xor_reg <= gpio2_data_in_xor; GPIO_intr <= or_ints(0); GPIO2_intr <= or_ints2(0); end if; end if; end process REGISTER_XORs_INTRs; end generate gen_interrupt_dual; end generate Dual; end architecture IMP; ------------------------------------------------------------------------------- -- AXI_GPIO - entity/architecture pair ------------------------------------------------------------------------------- -- -- *************************************************************************** -- DISCLAIMER OF LIABILITY -- -- This file contains proprietary and confidential information of -- Xilinx, Inc. ("Xilinx"), that is distributed under a license -- from Xilinx, and may be used, copied and/or disclosed only -- pursuant to the terms of a valid license agreement with Xilinx. -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx -- does not warrant that functions included in the Materials will -- meet the requirements of Licensee, or that the operation of the -- Materials will be uninterrupted or error-free, or that defects -- in the Materials will be corrected. Furthermore, Xilinx does -- not warrant or make any representations regarding use, or the -- results of the use, of the Materials in terms of correctness, -- accuracy, reliability or otherwise. -- -- Xilinx products are not designed or intended to be fail-safe, -- or for use in any application requiring fail-safe performance, -- such as life-support or safety devices or systems, Class III -- medical devices, nuclear facilities, applications related to -- the deployment of airbags, or any other applications that could -- lead to death, personal injury or severe property or -- environmental damage (individually and collectively, "critical -- applications"). Customer assumes the sole risk and liability -- of any use of Xilinx products in critical applications, -- subject only to applicable laws and regulations governing -- limitations on product liability. -- -- Copyright 2009 Xilinx, Inc. -- All rights reserved. -- -- This disclaimer and copyright notice must be retained as part -- of this file at all times. -- *************************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_gpio.vhd -- Version: v2.0 -- Description: General Purpose I/O for AXI Interface -- ------------------------------------------------------------------------------- -- Structure: -- axi_gpio.vhd -- -- axi_lite_ipif.vhd -- -- interrupt_control.vhd -- -- gpio_core.vhd ------------------------------------------------------------------------------- -- Author: KSB -- History: -- ~~~~~~~~~~~~~~ -- KSB 07/28/09 -- ^^^^^^^^^^^^^^ -- First version of axi_gpio. Based on xps_gpio 2.00a -- -- KSB 05/20/10 -- ^^^^^^^^^^^^^^ -- Updated for holes in address range -- ~~~~~~~~~~~~~~ -- VB 09/23/10 -- ^^^^^^^^^^^^^^ -- Updated for axi_lite_ipfi_v1_01_a -- ~~~~~~~~~~~~~~ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_cmb" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; use std.textio.all; ------------------------------------------------------------------------------- -- AXI common package of the proc common library is used for different -- function declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- axi_gpio_v2_0_15 library is used for axi4 component declarations ------------------------------------------------------------------------------- library axi_lite_ipif_v3_0_4; use axi_lite_ipif_v3_0_4.ipif_pkg.calc_num_ce; use axi_lite_ipif_v3_0_4.ipif_pkg.INTEGER_ARRAY_TYPE; use axi_lite_ipif_v3_0_4.ipif_pkg.SLV64_ARRAY_TYPE; ------------------------------------------------------------------------------- -- axi_gpio_v2_0_15 library is used for interrupt controller component -- declarations ------------------------------------------------------------------------------- library interrupt_control_v3_1_4; ------------------------------------------------------------------------------- -- axi_gpio_v2_0_15 library is used for axi_gpio component declarations ------------------------------------------------------------------------------- library axi_gpio_v2_0_15; ------------------------------------------------------------------------------- -- Defination of Generics : -- ------------------------------------------------------------------------------- -- AXI generics -- C_BASEADDR -- Base address of the core -- C_HIGHADDR -- Permits alias of address space -- by making greater than xFFF -- C_S_AXI_ADDR_WIDTH -- Width of AXI Address interface (in bits) -- C_S_AXI_DATA_WIDTH -- Width of the AXI Data interface (in bits) -- C_FAMILY -- XILINX FPGA family -- C_INSTANCE -- Instance name ot the core in the EDK system -- C_GPIO_WIDTH -- GPIO Data Bus width. -- C_ALL_INPUTS -- Inputs Only. -- C_INTERRUPT_PRESENT -- GPIO Interrupt. -- C_IS_BIDIR -- Selects gpio_io_i as input. -- C_DOUT_DEFAULT -- GPIO_DATA Register reset value. -- C_TRI_DEFAULT -- GPIO_TRI Register reset value. -- C_IS_DUAL -- Dual Channel GPIO. -- C_ALL_INPUTS_2 -- Channel2 Inputs only. -- C_IS_BIDIR_2 -- Selects gpio2_io_i as input. -- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value. -- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value. ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Defination of Ports -- ------------------------------------------------------------------------------- -- AXI signals -- s_axi_awaddr -- AXI Write address -- s_axi_awvalid -- Write address valid -- s_axi_awready -- Write address ready -- s_axi_wdata -- Write data -- s_axi_wstrb -- Write strobes -- s_axi_wvalid -- Write valid -- s_axi_wready -- Write ready -- s_axi_bresp -- Write response -- s_axi_bvalid -- Write response valid -- s_axi_bready -- Response ready -- s_axi_araddr -- Read address -- s_axi_arvalid -- Read address valid -- s_axi_arready -- Read address ready -- s_axi_rdata -- Read data -- s_axi_rresp -- Read response -- s_axi_rvalid -- Read valid -- s_axi_rready -- Read ready -- GPIO Signals -- gpio_io_i -- Channel 1 General purpose I/O in port -- gpio_io_o -- Channel 1 General purpose I/O out port -- gpio_io_t -- Channel 1 General purpose I/O -- TRI-STATE control port -- gpio2_io_i -- Channel 2 General purpose I/O in port -- gpio2_io_o -- Channel 2 General purpose I/O out port -- gpio2_io_t -- Channel 2 General purpose I/O -- TRI-STATE control port -- System Signals -- s_axi_aclk -- AXI Clock -- s_axi_aresetn -- AXI Reset -- ip2intc_irpt -- AXI GPIO Interrupt ------------------------------------------------------------------------------- entity axi_gpio is generic ( -- -- System Parameter C_FAMILY : string := "virtex7"; -- -- AXI Parameters C_S_AXI_ADDR_WIDTH : integer range 9 to 9 := 9; C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32; -- -- GPIO Parameter C_GPIO_WIDTH : integer range 1 to 32 := 32; C_GPIO2_WIDTH : integer range 1 to 32 := 32; C_ALL_INPUTS : integer range 0 to 1 := 0; C_ALL_INPUTS_2 : integer range 0 to 1 := 0; C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013 C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013 C_INTERRUPT_PRESENT : integer range 0 to 1 := 0; C_DOUT_DEFAULT : std_logic_vector (31 downto 0) := X"0000_0000"; C_TRI_DEFAULT : std_logic_vector (31 downto 0) := X"FFFF_FFFF"; C_IS_DUAL : integer range 0 to 1 := 0; C_DOUT_DEFAULT_2 : std_logic_vector (31 downto 0) := X"0000_0000"; C_TRI_DEFAULT_2 : std_logic_vector (31 downto 0) := X"FFFF_FFFF" ); port ( -- AXI interface Signals -------------------------------------------------- s_axi_aclk : in std_logic; s_axi_aresetn : in std_logic; s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); s_axi_wvalid : in std_logic; s_axi_wready : out std_logic; s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_arvalid : in std_logic; s_axi_arready : out std_logic; s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rvalid : out std_logic; s_axi_rready : in std_logic; -- Interrupt--------------------------------------------------------------- ip2intc_irpt : out std_logic; -- GPIO Signals------------------------------------------------------------ gpio_io_i : in std_logic_vector(C_GPIO_WIDTH-1 downto 0); gpio_io_o : out std_logic_vector(C_GPIO_WIDTH-1 downto 0); gpio_io_t : out std_logic_vector(C_GPIO_WIDTH-1 downto 0); gpio2_io_i : in std_logic_vector(C_GPIO2_WIDTH-1 downto 0); gpio2_io_o : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0); gpio2_io_t : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0) ); ------------------------------------------------------------------------------- -- fan-out attributes for XST ------------------------------------------------------------------------------- attribute MAX_FANOUT : string; attribute MAX_FANOUT of s_axi_aclk : signal is "10000"; attribute MAX_FANOUT of s_axi_aresetn : signal is "10000"; ------------------------------------------------------------------------------- -- Attributes for MPD file ------------------------------------------------------------------------------- attribute IP_GROUP : string ; attribute IP_GROUP of axi_gpio : entity is "LOGICORE"; attribute SIGIS : string ; attribute SIGIS of s_axi_aclk : signal is "Clk"; attribute SIGIS of s_axi_aresetn : signal is "Rst"; attribute SIGIS of ip2intc_irpt : signal is "INTR_LEVEL_HIGH"; end entity axi_gpio; ------------------------------------------------------------------------------- -- Architecture Section ------------------------------------------------------------------------------- architecture imp of axi_gpio is -- Pragma Added to supress synth warnings attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; ------------------------------------------------------------------------------- -- constant added for webtalk information ------------------------------------------------------------------------------- --function chr(sl: std_logic) return character is -- variable c: character; -- begin -- case sl is -- when '0' => c:= '0'; -- when '1' => c:= '1'; -- when 'Z' => c:= 'Z'; -- when 'U' => c:= 'U'; -- when 'X' => c:= 'X'; -- when 'W' => c:= 'W'; -- when 'L' => c:= 'L'; -- when 'H' => c:= 'H'; -- when '-' => c:= '-'; -- end case; -- return c; -- end chr; -- --function str(slv: std_logic_vector) return string is -- variable result : string (1 to slv'length); -- variable r : integer; -- begin -- r := 1; -- for i in slv'range loop -- result(r) := chr(slv(i)); -- r := r + 1; -- end loop; -- return result; -- end str; type bo2na_type is array (boolean) of natural; -- boolean to --natural conversion constant bo2na : bo2na_type := (false => 0, true => 1); ------------------------------------------------------------------------------- -- Function Declarations ------------------------------------------------------------------------------- type BOOLEAN_ARRAY_TYPE is array(natural range <>) of boolean; ---------------------------------------------------------------------------- -- This function returns the number of elements that are true in -- a boolean array. ---------------------------------------------------------------------------- function num_set( ba : BOOLEAN_ARRAY_TYPE ) return natural is variable n : natural := 0; begin for i in ba'range loop n := n + bo2na(ba(i)); end loop; return n; end; ---------------------------------------------------------------------------- -- This function returns a num_ce integer array that is constructed by -- taking only those elements of superset num_ce integer array -- that will be defined by the current case. -- The superset num_ce array is given by parameter num_ce_by_ard. -- The current case the ard elements that will be used is given -- by parameter defined_ards. ---------------------------------------------------------------------------- function qual_ard_num_ce_array( defined_ards : BOOLEAN_ARRAY_TYPE; num_ce_by_ard : INTEGER_ARRAY_TYPE ) return INTEGER_ARRAY_TYPE is variable res : INTEGER_ARRAY_TYPE(num_set(defined_ards)-1 downto 0); variable i : natural := 0; variable j : natural := defined_ards'left; begin while i /= res'length loop -- coverage off while defined_ards(j) = false loop j := j+1; end loop; -- coverage on res(i) := num_ce_by_ard(j); i := i+1; j := j+1; end loop; return res; end; ---------------------------------------------------------------------------- -- This function returns a addr_range array that is constructed by -- taking only those elements of superset addr_range array -- that will be defined by the current case. -- The superset addr_range array is given by parameter addr_range_by_ard. -- The current case the ard elements that will be used is given -- by parameter defined_ards. ---------------------------------------------------------------------------- function qual_ard_addr_range_array( defined_ards : BOOLEAN_ARRAY_TYPE; addr_range_by_ard : SLV64_ARRAY_TYPE ) return SLV64_ARRAY_TYPE is variable res : SLV64_ARRAY_TYPE(0 to 2*num_set(defined_ards)-1); variable i : natural := 0; variable j : natural := defined_ards'left; begin while i /= res'length loop -- coverage off while defined_ards(j) = false loop j := j+1; end loop; -- coverage on res(i) := addr_range_by_ard(2*j); res(i+1) := addr_range_by_ard((2*j)+1); i := i+2; j := j+1; end loop; return res; end; function qual_ard_ce_valid( defined_ards : BOOLEAN_ARRAY_TYPE ) return std_logic_vector is variable res : std_logic_vector(0 to 31); begin res := (others => '0'); if defined_ards(defined_ards'right) then res(0 to 3) := "1111"; res(12) := '1'; res(13) := '1'; res(15) := '1'; else res(0 to 3) := "1111"; end if; return res; end; ---------------------------------------------------------------------------- -- This function returns the maximum width amongst the two GPIO Channels -- and if there is only one channel, it returns just the width of that -- channel. ---------------------------------------------------------------------------- function max_width( dual_channel : INTEGER; channel1_width : INTEGER; channel2_width : INTEGER ) return INTEGER is begin if (dual_channel = 0) then return channel1_width; else if (channel1_width > channel2_width) then return channel1_width; else return channel2_width; end if; end if; end; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- constant C_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF"; constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0'); constant INTR_TYPE : integer := 5; constant INTR_BASEADDR : std_logic_vector(0 to 31):= X"00000100"; constant INTR_HIGHADDR : std_logic_vector(0 to 31):= X"000001FF"; constant GPIO_HIGHADDR : std_logic_vector(0 to 31):= X"0000000F"; constant MAX_GPIO_WIDTH : integer := max_width (C_IS_DUAL,C_GPIO_WIDTH,C_GPIO2_WIDTH); constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := qual_ard_addr_range_array( (true,C_INTERRUPT_PRESENT=1), (ZERO_ADDR_PAD & X"00000000", ZERO_ADDR_PAD & GPIO_HIGHADDR, ZERO_ADDR_PAD & INTR_BASEADDR, ZERO_ADDR_PAD & INTR_HIGHADDR ) ); constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := qual_ard_num_ce_array( (true,C_INTERRUPT_PRESENT=1), (4,16) ); constant ARD_CE_VALID : std_logic_vector(0 to 31) := qual_ard_ce_valid( (true,C_INTERRUPT_PRESENT=1) ); constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to 0+bo2na(C_IS_DUAL=1)) := (others => 5); constant C_USE_WSTRB : integer := 0; constant C_DPHASE_TIMEOUT : integer := 8; ------------------------------------------------------------------------------- -- Signal and Type Declarations ------------------------------------------------------------------------------- signal ip2bus_intrevent : std_logic_vector(0 to 1); signal GPIO_xferAck_i : std_logic; signal Bus2IP_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal Bus2IP1_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal Bus2IP2_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); -- IPIC Used Signals signal ip2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal bus2ip_addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1); signal bus2ip_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal bus2ip_rnw : std_logic; signal bus2ip_cs : std_logic_vector(0 to 0 + bo2na (C_INTERRUPT_PRESENT=1)); signal bus2ip_rdce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); signal bus2ip_wrce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); signal Intrpt_bus2ip_rdce : std_logic_vector(0 to 15); signal Intrpt_bus2ip_wrce : std_logic_vector(0 to 15); signal intr_wr_ce_or_reduce : std_logic; signal intr_rd_ce_or_reduce : std_logic; signal ip2Bus_RdAck_intr_reg_hole : std_logic; signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic; signal ip2Bus_WrAck_intr_reg_hole : std_logic; signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic; signal bus2ip_be : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH / 8) - 1); signal bus2ip_clk : std_logic; signal bus2ip_reset : std_logic; signal bus2ip_resetn : std_logic; signal intr2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal intr2bus_wrack : std_logic; signal intr2bus_rdack : std_logic; signal intr2bus_error : std_logic; signal ip2bus_data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal ip2bus_data_i_D1 : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal ip2bus_wrack_i : std_logic; signal ip2bus_wrack_i_D1 : std_logic; signal ip2bus_rdack_i : std_logic; signal ip2bus_rdack_i_D1 : std_logic; signal ip2bus_error_i : std_logic; signal IP2INTC_Irpt_i : std_logic; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- begin -- architecture IMP AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif generic map ( C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, C_S_AXI_MIN_SIZE => C_AXI_MIN_SIZE, C_USE_WSTRB => C_USE_WSTRB, C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY, C_FAMILY => C_FAMILY ) port map ( S_AXI_ACLK => s_axi_aclk, S_AXI_ARESETN => s_axi_aresetn, S_AXI_AWADDR => s_axi_awaddr, S_AXI_AWVALID => s_axi_awvalid, S_AXI_AWREADY => s_axi_awready, S_AXI_WDATA => s_axi_wdata, S_AXI_WSTRB => s_axi_wstrb, S_AXI_WVALID => s_axi_wvalid, S_AXI_WREADY => s_axi_wready, S_AXI_BRESP => s_axi_bresp, S_AXI_BVALID => s_axi_bvalid, S_AXI_BREADY => s_axi_bready, S_AXI_ARADDR => s_axi_araddr, S_AXI_ARVALID => s_axi_arvalid, S_AXI_ARREADY => s_axi_arready, S_AXI_RDATA => s_axi_rdata, S_AXI_RRESP => s_axi_rresp, S_AXI_RVALID => s_axi_rvalid, S_AXI_RREADY => s_axi_rready, -- IP Interconnect (IPIC) port signals Bus2IP_Clk => bus2ip_clk, Bus2IP_Resetn => bus2ip_resetn, IP2Bus_Data => ip2bus_data_i_D1, IP2Bus_WrAck => ip2bus_wrack_i_D1, IP2Bus_RdAck => ip2bus_rdack_i_D1, --IP2Bus_WrAck => ip2bus_wrack_i, --IP2Bus_RdAck => ip2bus_rdack_i, IP2Bus_Error => ip2bus_error_i, Bus2IP_Addr => bus2ip_addr, Bus2IP_Data => bus2ip_data, Bus2IP_RNW => bus2ip_rnw, Bus2IP_BE => bus2ip_be, Bus2IP_CS => bus2ip_cs, Bus2IP_RdCE => bus2ip_rdce, Bus2IP_WrCE => bus2ip_wrce ); ip2bus_data_i <= intr2bus_data or ip2bus_data; ip2bus_wrack_i <= intr2bus_wrack or (GPIO_xferAck_i and not(bus2ip_rnw)) or ip2Bus_WrAck_intr_reg_hole;-- Holes in Address range ip2bus_rdack_i <= intr2bus_rdack or (GPIO_xferAck_i and bus2ip_rnw) or ip2Bus_RdAck_intr_reg_hole; -- Holes in Address range I_WRACK_RDACK_DELAYS: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2bus_wrack_i_D1 <= '0'; ip2bus_rdack_i_D1 <= '0'; ip2bus_data_i_D1 <= (others => '0'); else ip2bus_wrack_i_D1 <= ip2bus_wrack_i; ip2bus_rdack_i_D1 <= ip2bus_rdack_i; ip2bus_data_i_D1 <= ip2bus_data_i; end if; end if; end process I_WRACK_RDACK_DELAYS; ip2bus_error_i <= intr2bus_error; ---------------------- --REG_RESET_FROM_IPIF: convert active low to active hig reset to rest of -- the core. ---------------------- REG_RESET_FROM_IPIF: process (s_axi_aclk) is begin if(s_axi_aclk'event and s_axi_aclk = '1') then bus2ip_reset <= not(bus2ip_resetn); end if; end process REG_RESET_FROM_IPIF; --------------------------------------------------------------------------- -- Interrupts --------------------------------------------------------------------------- INTR_CTRLR_GEN : if (C_INTERRUPT_PRESENT = 1) generate constant NUM_IPIF_IRPT_SRC : natural := 1; constant NUM_CE : integer := 16; signal errack_reserved : std_logic_vector(0 to 1); signal ipif_lvl_interrupts : std_logic_vector(0 to NUM_IPIF_IRPT_SRC-1); begin ipif_lvl_interrupts <= (others => '0'); errack_reserved <= (others => '0'); --- Addr 0X11c, 0X120, 0X128 valid addresses, remaining are holes Intrpt_bus2ip_rdce <= "0000000" & bus2ip_rdce(11) & bus2ip_rdce(12) & '0' & bus2ip_rdce(14) & "00000"; Intrpt_bus2ip_wrce <= "0000000" & bus2ip_wrce(11) & bus2ip_wrce(12) & '0' & bus2ip_wrce(14) & "00000"; intr_rd_ce_or_reduce <= or_reduce(bus2ip_rdce(4 to 10)) or Bus2IP_RdCE(13) or or_reduce(Bus2IP_RdCE(15 to 19)); intr_wr_ce_or_reduce <= or_reduce(bus2ip_wrce(4 to 10)) or bus2ip_wrce(13) or or_reduce(bus2ip_wrce(15 to 19)); I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2Bus_RdAck_intr_reg_hole <= '0'; ip2Bus_RdAck_intr_reg_hole_d1 <= '0'; else ip2Bus_RdAck_intr_reg_hole_d1 <= intr_rd_ce_or_reduce; ip2Bus_RdAck_intr_reg_hole <= intr_rd_ce_or_reduce and (not ip2Bus_RdAck_intr_reg_hole_d1); end if; end if; end process I_READ_ACK_INTR_HOLES; I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2Bus_WrAck_intr_reg_hole <= '0'; ip2Bus_WrAck_intr_reg_hole_d1 <= '0'; else ip2Bus_WrAck_intr_reg_hole_d1 <= intr_wr_ce_or_reduce; ip2Bus_WrAck_intr_reg_hole <= intr_wr_ce_or_reduce and (not ip2Bus_WrAck_intr_reg_hole_d1); end if; end if; end process I_WRITE_ACK_INTR_HOLES; INTERRUPT_CONTROL_I : entity interrupt_control_v3_1_4.interrupt_control generic map ( C_NUM_CE => NUM_CE, C_NUM_IPIF_IRPT_SRC => NUM_IPIF_IRPT_SRC, C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY, C_INCLUDE_DEV_PENCODER => false, C_INCLUDE_DEV_ISC => false, C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH ) port map ( -- Inputs From the IPIF Bus Bus2IP_Clk => Bus2IP_Clk, Bus2IP_Reset => bus2ip_reset, Bus2IP_Data => bus2ip_data, Bus2IP_BE => bus2ip_be, Interrupt_RdCE => Intrpt_bus2ip_rdce, Interrupt_WrCE => Intrpt_bus2ip_wrce, -- Interrupt inputs from the IPIF sources that will -- get registered in this design IPIF_Reg_Interrupts => errack_reserved, -- Level Interrupt inputs from the IPIF sources IPIF_Lvl_Interrupts => ipif_lvl_interrupts, -- Inputs from the IP Interface IP2Bus_IntrEvent => ip2bus_intrevent(IP_INTR_MODE_ARRAY'range), -- Final Device Interrupt Output Intr2Bus_DevIntr => IP2INTC_Irpt_i, -- Status Reply Outputs to the Bus Intr2Bus_DBus => intr2bus_data, Intr2Bus_WrAck => intr2bus_wrack, Intr2Bus_RdAck => intr2bus_rdack, Intr2Bus_Error => intr2bus_error, Intr2Bus_Retry => open, Intr2Bus_ToutSup => open ); -- registering interrupt I_INTR_DELAY: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2intc_irpt <= '0'; else ip2intc_irpt <= IP2INTC_Irpt_i; end if; end if; end process I_INTR_DELAY; end generate INTR_CTRLR_GEN; ----------------------------------------------------------------------- -- Assigning the intr2bus signal to zero's when interrupt is not -- present ----------------------------------------------------------------------- REMOVE_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate intr2bus_data <= (others => '0'); ip2intc_irpt <= '0'; intr2bus_error <= '0'; intr2bus_rdack <= '0'; intr2bus_wrack <= '0'; ip2Bus_WrAck_intr_reg_hole <= '0'; ip2Bus_RdAck_intr_reg_hole <= '0'; end generate REMOVE_INTERRUPT; gpio_core_1 : entity axi_gpio_v2_0_15.gpio_core generic map ( C_DW => C_S_AXI_DATA_WIDTH, C_AW => C_S_AXI_ADDR_WIDTH, C_GPIO_WIDTH => C_GPIO_WIDTH, C_GPIO2_WIDTH => C_GPIO2_WIDTH, C_MAX_GPIO_WIDTH => MAX_GPIO_WIDTH, C_INTERRUPT_PRESENT => C_INTERRUPT_PRESENT, C_DOUT_DEFAULT => C_DOUT_DEFAULT, C_TRI_DEFAULT => C_TRI_DEFAULT, C_IS_DUAL => C_IS_DUAL, C_ALL_OUTPUTS => C_ALL_OUTPUTS, C_ALL_INPUTS => C_ALL_INPUTS, C_ALL_INPUTS_2 => C_ALL_INPUTS_2, C_ALL_OUTPUTS_2 => C_ALL_OUTPUTS_2, C_DOUT_DEFAULT_2 => C_DOUT_DEFAULT_2, C_TRI_DEFAULT_2 => C_TRI_DEFAULT_2, C_FAMILY => C_FAMILY ) port map ( Clk => Bus2IP_Clk, Rst => bus2ip_reset, ABus_Reg => Bus2IP_Addr, BE_Reg => Bus2IP_BE(0 to C_S_AXI_DATA_WIDTH/8-1), DBus_Reg => Bus2IP_Data_i(0 to MAX_GPIO_WIDTH-1), RNW_Reg => Bus2IP_RNW, GPIO_DBus => IP2Bus_Data(0 to C_S_AXI_DATA_WIDTH-1), GPIO_xferAck => GPIO_xferAck_i, GPIO_Select => bus2ip_cs(0), GPIO_intr => ip2bus_intrevent(0), GPIO2_intr => ip2bus_intrevent(1), GPIO_IO_I => gpio_io_i, GPIO_IO_O => gpio_io_o, GPIO_IO_T => gpio_io_t, GPIO2_IO_I => gpio2_io_i, GPIO2_IO_O => gpio2_io_o, GPIO2_IO_T => gpio2_io_t ); Bus2IP_Data_i <= Bus2IP1_Data_i when bus2ip_cs(0) = '1' and bus2ip_addr (5) = '0'else Bus2IP2_Data_i; BUS_CONV_ch1 : for i in 0 to C_GPIO_WIDTH-1 generate Bus2IP1_Data_i(i) <= Bus2IP_Data(i+ C_S_AXI_DATA_WIDTH-C_GPIO_WIDTH); end generate BUS_CONV_ch1; BUS_CONV_ch2 : for i in 0 to C_GPIO2_WIDTH-1 generate Bus2IP2_Data_i(i) <= Bus2IP_Data(i+ C_S_AXI_DATA_WIDTH-C_GPIO2_WIDTH); end generate BUS_CONV_ch2; end architecture imp;

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block dPI2Kuf4xz7CemPH/QlaD7hcYqKhcR3NrIcD8v0oKrpOlL+W1YPz0HzOs6fITkhHPw6GpiNmP1w0 YZaKH/vuQw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block LKBMBPM2d4xR6GBUOC+BvDP5wZzXqqQ9m1OpIG5zDdhNfLoiwTXATh3DCuN3aa/Dayo8pfS08DWr aASYjAENp3kVaM5l4J30ay8/s6VsyQ5q+TLsgX3YbPs0REJKOp9L7P+uikKwGIdh8jywuE4A7peh 5WSRnykewDaNFp6V0D4= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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------------------------------------------------------------------------------- -- -- Title : req_ack -- Design : plk_mn -- ------------------------------------------------------------------------------- -- -- File : C:\my_designs\PLK_MN\plk_mn\src\lib\req_ack.vhd -- Generated : Mon Aug 1 15:58:57 2011 -- From : interface description file -- By : Itf2Vhdl ver. 1.22 -- ------------------------------------------------------------------------------- -- -- (c) B&R, 2011 -- -- Redistribution and use in source and binary forms, with or without -- modification, are permitted provided that the following conditions -- are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- -- 2. Redistributions in binary form must reproduce the above copyright -- notice, this list of conditions and the following disclaimer in the -- documentation and/or other materials provided with the distribution. -- -- 3. Neither the name of B&R nor the names of its -- contributors may be used to endorse or promote products derived -- from this software without prior written permission. For written -- permission, please contact [email protected] -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- -- -- 2011-08-01 V0.01 zelenkaj First version -- 2011-11-30 V0.02 zelenkaj removed enable at ack output -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; USE ieee.math_real.log2; USE ieee.math_real.ceil; entity req_ack is generic( ack_delay_g : integer := 1; zero_delay_g : boolean := false ); port( clk : in std_logic; rst : in std_logic; enable : in std_logic; ack : out std_logic ); end req_ack; architecture rtl of req_ack is constant iMaxCnt : integer := ack_delay_g; constant iMaxCntLog2 : integer := integer(ceil(log2(real(iMaxCnt)))); signal cnt, cnt_next : std_logic_vector(iMaxCntLog2 downto 0); signal cnt_tc : std_logic; begin genDelay : if zero_delay_g = false generate theCnter : process(clk, rst) begin if rst = '1' then cnt <= (others => '0'); elsif clk = '1' and clk'event then cnt <= cnt_next; end if; end process; cnt_next <= cnt + 1 when enable = '1' and cnt_tc /= '1' else (others => '0'); cnt_tc <= '1' when cnt = iMaxCnt else '0'; ack <= cnt_tc; end generate; genNoDelay : if zero_delay_g = true generate ack <= enable; end generate; end rtl;

library IEEE; use IEEE.std_logic_1164.all; entity com1_pkg1_lib2 is generic ( WITH_GENERIC: boolean:=TRUE ); port ( data_i : in std_logic; data_o : out std_logic ); end entity com1_pkg1_lib2; architecture RTL of com1_pkg1_lib2 is begin data_o <= data_i; end architecture RTL;

-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net> -- This software is distributed under the terms of the MIT License shown below. -- -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to -- deal in the Software without restriction, including without limitation the -- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or -- sell copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- -- The above copyright notice and this permission notice shall be included in -- all copies or substantial portions of the Software. -- -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -- IN THE SOFTWARE. -- Implements a synchronous register of a given width. library ieee; use ieee.std_logic_1164.all; entity reg is generic ( WIDTH : positive := 1 ); port ( clk : in std_logic; rst : in std_logic; d : in std_logic_vector(WIDTH-1 downto 0); q : out std_logic_vector(WIDTH-1 downto 0) ); end reg; architecture BHV of reg is begin process(clk, rst) begin if(rst = '1') then q <= (others => '0'); elsif(rising_edge(clk)) then q <= d; end if; end process; end BHV;

entity \test \ is end;

-- $Id: sys_tst_serloop1_n3.vhd 476 2013-01-26 22:23:53Z mueller $ -- -- Copyright 2011- by Walter F.J. Mueller <[email protected]> -- -- This program is free software; you may redistribute and/or modify it under -- the terms of the GNU General Public License as published by the Free -- Software Foundation, either version 2, or at your option any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY -- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for complete details. -- ------------------------------------------------------------------------------ -- Module Name: sys_tst_serloop1_n3 - syn -- Description: Tester serial link for nexys3 (serport_1clock case) -- -- Dependencies: genlib/clkdivce -- bpgen/bp_rs232_2l4l_iob -- bpgen/sn_humanio -- tst_serloop_hiomap -- vlib/serport/serport_1clock -- tst_serloop -- vlib/nxcramlib/nx_cram_dummy -- -- Test bench: - -- -- Target Devices: generic -- Tool versions: xst 13.1; ghdl 0.29 -- -- Synthesized (xst): -- Date Rev ise Target flop lutl lutm slic t peri -- 2011-12-11 438 13.1 O40d xc6slx16-2 419 650 32 221 t 7.7 -- -- Revision History: -- Date Rev Version Comment -- 2011-12-11 438 1.0 Initial version (derived from sys_tst_serloop_n3) ------------------------------------------------------------------------------ -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.slvtypes.all; use work.xlib.all; use work.genlib.all; use work.bpgenlib.all; use work.tst_serlooplib.all; use work.serportlib.all; use work.nxcramlib.all; use work.sys_conf.all; -- ---------------------------------------------------------------------------- entity sys_tst_serloop1_n3 is -- top level -- implements nexys3_fusp_aif port ( I_CLK100 : in slbit; -- 100 MHz clock I_RXD : in slbit; -- receive data (board view) O_TXD : out slbit; -- transmit data (board view) I_SWI : in slv8; -- n3 switches I_BTN : in slv5; -- n3 buttons O_LED : out slv8; -- n3 leds O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low) O_SEG_N : out slv8; -- 7 segment disp: segments (act.low) O_MEM_CE_N : out slbit; -- cram: chip enable (act.low) O_MEM_BE_N : out slv2; -- cram: byte enables (act.low) O_MEM_WE_N : out slbit; -- cram: write enable (act.low) O_MEM_OE_N : out slbit; -- cram: output enable (act.low) O_MEM_ADV_N : out slbit; -- cram: address valid (act.low) O_MEM_CLK : out slbit; -- cram: clock O_MEM_CRE : out slbit; -- cram: command register enable I_MEM_WAIT : in slbit; -- cram: mem wait O_MEM_ADDR : out slv23; -- cram: address lines IO_MEM_DATA : inout slv16; -- cram: data lines O_PPCM_CE_N : out slbit; -- ppcm: ... O_PPCM_RST_N : out slbit; -- ppcm: ... O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n I_FUSP_RXD : in slbit; -- fusp: rs232 rx O_FUSP_TXD : out slbit -- fusp: rs232 tx ); end sys_tst_serloop1_n3; architecture syn of sys_tst_serloop1_n3 is signal CLK : slbit := '0'; signal RESET : slbit := '0'; signal CE_USEC : slbit := '0'; signal CE_MSEC : slbit := '0'; signal RXD : slbit := '0'; signal TXD : slbit := '0'; signal CTS_N : slbit := '0'; signal RTS_N : slbit := '0'; signal SWI : slv8 := (others=>'0'); signal BTN : slv5 := (others=>'0'); signal LED : slv8 := (others=>'0'); signal DSP_DAT : slv16 := (others=>'0'); signal DSP_DP : slv4 := (others=>'0'); signal HIO_CNTL : hio_cntl_type := hio_cntl_init; signal HIO_STAT : hio_stat_type := hio_stat_init; signal RXDATA : slv8 := (others=>'0'); signal RXVAL : slbit := '0'; signal RXHOLD : slbit := '0'; signal TXDATA : slv8 := (others=>'0'); signal TXENA : slbit := '0'; signal TXBUSY : slbit := '0'; signal SER_MONI : serport_moni_type := serport_moni_init; begin CLK <= I_CLK100; CLKDIV : clkdivce generic map ( CDUWIDTH => 8, USECDIV => sys_conf_clkdiv_usecdiv, -- syn: 100 sim: 20 MSECDIV => sys_conf_clkdiv_msecdiv) -- syn: 1000 sim: 5 port map ( CLK => CLK, CE_USEC => open, CE_MSEC => CE_MSEC ); HIO : sn_humanio generic map ( BWIDTH => 5, DEBOUNCE => sys_conf_hio_debounce) port map ( CLK => CLK, RESET => '0', CE_MSEC => CE_MSEC, SWI => SWI, BTN => BTN, LED => LED, DSP_DAT => DSP_DAT, DSP_DP => DSP_DP, I_SWI => I_SWI, I_BTN => I_BTN, O_LED => O_LED, O_ANO_N => O_ANO_N, O_SEG_N => O_SEG_N ); RESET <= BTN(0); -- BTN(0) will reset tester !! HIOMAP : tst_serloop_hiomap port map ( CLK => CLK, RESET => RESET, HIO_CNTL => HIO_CNTL, HIO_STAT => HIO_STAT, SER_MONI => SER_MONI, SWI => SWI, BTN => BTN(3 downto 0), LED => LED, DSP_DAT => DSP_DAT, DSP_DP => DSP_DP ); IOB_RS232 : bp_rs232_2l4l_iob port map ( CLK => CLK, RESET => '0', SEL => SWI(0), -- port selection RXD => RXD, TXD => TXD, CTS_N => CTS_N, RTS_N => RTS_N, I_RXD0 => I_RXD, O_TXD0 => O_TXD, I_RXD1 => I_FUSP_RXD, O_TXD1 => O_FUSP_TXD, I_CTS1_N => I_FUSP_CTS_N, O_RTS1_N => O_FUSP_RTS_N ); SERPORT : serport_1clock generic map ( CDWIDTH => 15, CDINIT => sys_conf_uart_cdinit, RXFAWIDTH => 5, TXFAWIDTH => 5) port map ( CLK => CLK, CE_MSEC => CE_MSEC, RESET => RESET, ENAXON => HIO_CNTL.enaxon, ENAESC => HIO_CNTL.enaesc, RXDATA => RXDATA, RXVAL => RXVAL, RXHOLD => RXHOLD, TXDATA => TXDATA, TXENA => TXENA, TXBUSY => TXBUSY, MONI => SER_MONI, RXSD => RXD, TXSD => TXD, RXRTS_N => RTS_N, TXCTS_N => CTS_N ); TESTER : tst_serloop port map ( CLK => CLK, RESET => RESET, CE_MSEC => CE_MSEC, HIO_CNTL => HIO_CNTL, HIO_STAT => HIO_STAT, SER_MONI => SER_MONI, RXDATA => RXDATA, RXVAL => RXVAL, RXHOLD => RXHOLD, TXDATA => TXDATA, TXENA => TXENA, TXBUSY => TXBUSY ); SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy port map ( O_MEM_CE_N => O_MEM_CE_N, O_MEM_BE_N => O_MEM_BE_N, O_MEM_WE_N => O_MEM_WE_N, O_MEM_OE_N => O_MEM_OE_N, O_MEM_ADV_N => O_MEM_ADV_N, O_MEM_CLK => O_MEM_CLK, O_MEM_CRE => O_MEM_CRE, I_MEM_WAIT => I_MEM_WAIT, O_MEM_ADDR => O_MEM_ADDR, IO_MEM_DATA => IO_MEM_DATA ); O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled O_PPCM_RST_N <= '1'; -- end syn;

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v3_00_a; use proc_common_v3_00_a.proc_common_pkg.all; use proc_common_v3_00_a.ipif_pkg.all; library plbv46_slave_single_v1_01_a; use plbv46_slave_single_v1_01_a.plbv46_slave_single; library simple_timebase_v1_00_a; use simple_timebase_v1_00_a.user_logic; entity simple_timebase is generic ( C_BASEADDR : std_logic_vector := X"FFFFFFFF"; C_HIGHADDR : std_logic_vector := X"00000000"; C_SPLB_AWIDTH : integer := 32; C_SPLB_DWIDTH : integer := 128; C_SPLB_NUM_MASTERS : integer := 8; C_SPLB_MID_WIDTH : integer := 3; C_SPLB_NATIVE_DWIDTH : integer := 32; C_SPLB_P2P : integer := 0; C_SPLB_SUPPORT_BURSTS : integer := 0; C_SPLB_SMALLEST_MASTER : integer := 32; C_SPLB_CLK_PERIOD_PS : integer := 10000; C_INCLUDE_DPHASE_TIMER : integer := 0; C_FAMILY : string := "virtex5" ); port ( SPLB_Clk : in std_logic; SPLB_Rst : in std_logic; PLB_ABus : in std_logic_vector(0 to 31); PLB_UABus : in std_logic_vector(0 to 31); PLB_PAValid : in std_logic; PLB_SAValid : in std_logic; PLB_rdPrim : in std_logic; PLB_wrPrim : in std_logic; PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1); PLB_abort : in std_logic; PLB_busLock : in std_logic; PLB_RNW : in std_logic; PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1); PLB_MSize : in std_logic_vector(0 to 1); PLB_size : in std_logic_vector(0 to 3); PLB_type : in std_logic_vector(0 to 2); PLB_lockErr : in std_logic; PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1); PLB_wrBurst : in std_logic; PLB_rdBurst : in std_logic; PLB_wrPendReq : in std_logic; PLB_rdPendReq : in std_logic; PLB_wrPendPri : in std_logic_vector(0 to 1); PLB_rdPendPri : in std_logic_vector(0 to 1); PLB_reqPri : in std_logic_vector(0 to 1); PLB_TAttribute : in std_logic_vector(0 to 15); Sl_addrAck : out std_logic; Sl_SSize : out std_logic_vector(0 to 1); Sl_wait : out std_logic; Sl_rearbitrate : out std_logic; Sl_wrDAck : out std_logic; Sl_wrComp : out std_logic; Sl_wrBTerm : out std_logic; Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1); Sl_rdWdAddr : out std_logic_vector(0 to 3); Sl_rdDAck : out std_logic; Sl_rdComp : out std_logic; Sl_rdBTerm : out std_logic; Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1); Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1) ); attribute SIGIS : string; attribute SIGIS of SPLB_Clk : signal is "CLK"; attribute SIGIS of SPLB_Rst : signal is "RST"; end entity simple_timebase; architecture IMP of simple_timebase is constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0'); constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR; constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR; constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := ( ZERO_ADDR_PAD & USER_SLV_BASEADDR, ZERO_ADDR_PAD & USER_SLV_HIGHADDR ); constant USER_SLV_NUM_REG : integer := 1; constant USER_NUM_REG : integer := USER_SLV_NUM_REG; constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => pad_power2(USER_SLV_NUM_REG) ); constant IPIF_BUS2CORE_CLK_RATIO : integer := 1; constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH; constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH; constant USER_SLV_CS_INDEX : integer := 0; constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX); constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX; signal ipif_Bus2IP_Clk : std_logic; signal ipif_Bus2IP_Reset : std_logic; signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1); signal ipif_IP2Bus_WrAck : std_logic; signal ipif_IP2Bus_RdAck : std_logic; signal ipif_IP2Bus_Error : std_logic; signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1); signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1); signal ipif_Bus2IP_RNW : std_logic; signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1); signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1); signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1); signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1); signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1); signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1); signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1); signal user_IP2Bus_RdAck : std_logic; signal user_IP2Bus_WrAck : std_logic; signal user_IP2Bus_Error : std_logic; begin PLBV46_SLAVE_SINGLE_I : entity plbv46_slave_single_v1_01_a.plbv46_slave_single generic map ( C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY, C_SPLB_P2P => C_SPLB_P2P, C_BUS2CORE_CLK_RATIO => IPIF_BUS2CORE_CLK_RATIO, C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH, C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS, C_SPLB_AWIDTH => C_SPLB_AWIDTH, C_SPLB_DWIDTH => C_SPLB_DWIDTH, C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH, C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER, C_FAMILY => C_FAMILY ) port map ( SPLB_Clk => SPLB_Clk, SPLB_Rst => SPLB_Rst, PLB_ABus => PLB_ABus, PLB_UABus => PLB_UABus, PLB_PAValid => PLB_PAValid, PLB_SAValid => PLB_SAValid, PLB_rdPrim => PLB_rdPrim, PLB_wrPrim => PLB_wrPrim, PLB_masterID => PLB_masterID, PLB_abort => PLB_abort, PLB_busLock => PLB_busLock, PLB_RNW => PLB_RNW, PLB_BE => PLB_BE, PLB_MSize => PLB_MSize, PLB_size => PLB_size, PLB_type => PLB_type, PLB_lockErr => PLB_lockErr, PLB_wrDBus => PLB_wrDBus, PLB_wrBurst => PLB_wrBurst, PLB_rdBurst => PLB_rdBurst, PLB_wrPendReq => PLB_wrPendReq, PLB_rdPendReq => PLB_rdPendReq, PLB_wrPendPri => PLB_wrPendPri, PLB_rdPendPri => PLB_rdPendPri, PLB_reqPri => PLB_reqPri, PLB_TAttribute => PLB_TAttribute, Sl_addrAck => Sl_addrAck, Sl_SSize => Sl_SSize, Sl_wait => Sl_wait, Sl_rearbitrate => Sl_rearbitrate, Sl_wrDAck => Sl_wrDAck, Sl_wrComp => Sl_wrComp, Sl_wrBTerm => Sl_wrBTerm, Sl_rdDBus => Sl_rdDBus, Sl_rdWdAddr => Sl_rdWdAddr, Sl_rdDAck => Sl_rdDAck, Sl_rdComp => Sl_rdComp, Sl_rdBTerm => Sl_rdBTerm, Sl_MBusy => Sl_MBusy, Sl_MWrErr => Sl_MWrErr, Sl_MRdErr => Sl_MRdErr, Sl_MIRQ => Sl_MIRQ, Bus2IP_Clk => ipif_Bus2IP_Clk, Bus2IP_Reset => ipif_Bus2IP_Reset, IP2Bus_Data => ipif_IP2Bus_Data, IP2Bus_WrAck => ipif_IP2Bus_WrAck, IP2Bus_RdAck => ipif_IP2Bus_RdAck, IP2Bus_Error => ipif_IP2Bus_Error, Bus2IP_Addr => ipif_Bus2IP_Addr, Bus2IP_Data => ipif_Bus2IP_Data, Bus2IP_RNW => ipif_Bus2IP_RNW, Bus2IP_BE => ipif_Bus2IP_BE, Bus2IP_CS => ipif_Bus2IP_CS, Bus2IP_RdCE => ipif_Bus2IP_RdCE, Bus2IP_WrCE => ipif_Bus2IP_WrCE ); USER_LOGIC_I : entity simple_timebase_v1_00_a.user_logic generic map ( C_SLV_DWIDTH => USER_SLV_DWIDTH, C_NUM_REG => USER_NUM_REG ) port map ( Bus2IP_Clk => ipif_Bus2IP_Clk, Bus2IP_Reset => ipif_Bus2IP_Reset, Bus2IP_Data => ipif_Bus2IP_Data, Bus2IP_BE => ipif_Bus2IP_BE, Bus2IP_RdCE => user_Bus2IP_RdCE, Bus2IP_WrCE => user_Bus2IP_WrCE, IP2Bus_Data => user_IP2Bus_Data, IP2Bus_RdAck => user_IP2Bus_RdAck, IP2Bus_WrAck => user_IP2Bus_WrAck, IP2Bus_Error => user_IP2Bus_Error ); ipif_IP2Bus_Data <= user_IP2Bus_Data; ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck; ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck; ipif_IP2Bus_Error <= user_IP2Bus_Error; user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1); user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1); end IMP;

-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2209.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b06x00p01n01i02209ent IS END c07s02b06x00p01n01i02209ent; ARCHITECTURE c07s02b06x00p01n01i02209arch OF c07s02b06x00p01n01i02209ent IS BEGIN TESTING: PROCESS -- All different non-numeric type declarations. -- enumerated types. type SWITCH_LEVEL is ('0', '1', 'X'); -- Local declarations. variable SWITCHV : SWITCH_LEVEL := '0'; variable k : integer; BEGIN k := SWITCHV mod '1'; assert FALSE report "***FAILED TEST: c07s02b06x00p01n01i02209 - Operators mod and rem are predefined for any integer type only." severity ERROR; wait; END PROCESS TESTING; END c07s02b06x00p01n01i02209arch;

SIGNAL I_BUFFERED : std_logic_vector(0 TO %%I_MAX); SIGNAL C_SIG : std_logic_vector(0 TO %%C_MAX); SIGNAL STATE, NEXTSTATE : std_logic_vector(%%STATEWIDTH_M1 DOWNTO 0);

-------------------------------------------------------------------------------- -- Copyright (c) 1995-2003 Xilinx, Inc. -- All Right Reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 7.1.04i -- \ \ Application : sch2vhdl -- / / Filename : ISAintfc.vhf -- /___/ /\ Timestamp : 01/05/2006 10:51:23 -- \ \ / \ -- \___\/\___\ -- --Command: C:/Xilinx/bin/nt/sch2vhdl.exe -intstyle ise -family xc9500 -flat -suppress -w ISAintfc.sch ISAintfc.vhf --Design Name: ISAintfc --Device: xc9500 --Purpose: -- This vhdl netlist is translated from an ECS schematic. It can be -- synthesis and simulted, but it should not be modified. -- library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; -- synopsys translate_off library UNISIM; use UNISIM.Vcomponents.ALL; -- synopsys translate_on entity FD_MXILINX_ISAintfc is port ( C : in std_logic; D : in std_logic; Q : out std_logic); end FD_MXILINX_ISAintfc; architecture BEHAVIORAL of FD_MXILINX_ISAintfc is attribute BOX_TYPE : string ; signal XLXN_4 : std_logic; component GND port ( G : out std_logic); end component; attribute BOX_TYPE of GND : component is "BLACK_BOX"; component FDCP port ( C : in std_logic; CLR : in std_logic; D : in std_logic; PRE : in std_logic; Q : out std_logic); end component; attribute BOX_TYPE of FDCP : component is "BLACK_BOX"; begin I_36_43 : GND port map (G=>XLXN_4); U0 : FDCP port map (C=>C, CLR=>XLXN_4, D=>D, PRE=>XLXN_4, Q=>Q); end BEHAVIORAL; library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; -- synopsys translate_off library UNISIM; use UNISIM.Vcomponents.ALL; -- synopsys translate_on entity D3_8E_MXILINX_ISAintfc is port ( A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; E : in std_logic; D0 : out std_logic; D1 : out std_logic; D2 : out std_logic; D3 : out std_logic; D4 : out std_logic; D5 : out std_logic; D6 : out std_logic; D7 : out std_logic); end D3_8E_MXILINX_ISAintfc; architecture BEHAVIORAL of D3_8E_MXILINX_ISAintfc is attribute BOX_TYPE : string ; component AND4 port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND4 : component is "BLACK_BOX"; component AND4B1 port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND4B1 : component is "BLACK_BOX"; component AND4B2 port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND4B2 : component is "BLACK_BOX"; component AND4B3 port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND4B3 : component is "BLACK_BOX"; begin I_36_30 : AND4 port map (I0=>A2, I1=>A1, I2=>A0, I3=>E, O=>D7); I_36_31 : AND4B1 port map (I0=>A0, I1=>A2, I2=>A1, I3=>E, O=>D6); I_36_32 : AND4B1 port map (I0=>A1, I1=>A2, I2=>A0, I3=>E, O=>D5); I_36_33 : AND4B2 port map (I0=>A1, I1=>A0, I2=>A2, I3=>E, O=>D4); I_36_34 : AND4B1 port map (I0=>A2, I1=>A0, I2=>A1, I3=>E, O=>D3); I_36_35 : AND4B2 port map (I0=>A2, I1=>A0, I2=>A1, I3=>E, O=>D2); I_36_36 : AND4B2 port map (I0=>A2, I1=>A1, I2=>A0, I3=>E, O=>D1); I_36_37 : AND4B3 port map (I0=>A2, I1=>A1, I2=>A0, I3=>E, O=>D0); end BEHAVIORAL; library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; -- synopsys translate_off library UNISIM; use UNISIM.Vcomponents.ALL; -- synopsys translate_on entity FD4CE_MXILINX_ISAintfc is port ( C : in std_logic; CE : in std_logic; CLR : in std_logic; D0 : in std_logic; D1 : in std_logic; D2 : in std_logic; D3 : in std_logic; Q0 : out std_logic; Q1 : out std_logic; Q2 : out std_logic; Q3 : out std_logic); end FD4CE_MXILINX_ISAintfc; architecture BEHAVIORAL of FD4CE_MXILINX_ISAintfc is attribute BOX_TYPE : string ; component FDCE port ( C : in std_logic; CE : in std_logic; CLR : in std_logic; D : in std_logic; Q : out std_logic); end component; attribute BOX_TYPE of FDCE : component is "BLACK_BOX"; begin U0 : FDCE port map (C=>C, CE=>CE, CLR=>CLR, D=>D0, Q=>Q0); U1 : FDCE port map (C=>C, CE=>CE, CLR=>CLR, D=>D1, Q=>Q1); U2 : FDCE port map (C=>C, CE=>CE, CLR=>CLR, D=>D2, Q=>Q2); U3 : FDCE port map (C=>C, CE=>CE, CLR=>CLR, D=>D3, Q=>Q3); end BEHAVIORAL; library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; -- synopsys translate_off library UNISIM; use UNISIM.Vcomponents.ALL; -- synopsys translate_on entity ISAintfc is port ( BRDSELO : in std_logic; FIFOCTL : in std_logic_vector (7 downto 0); IORN : in std_logic; IOWN : in std_logic; SA0 : in std_logic; SA1 : in std_logic; SA2 : in std_logic; SA3 : in std_logic; SA4 : in std_logic; PLLOUT : in std_logic; A2DDATA : out std_logic; A2DSTAT : out std_logic; D2A0 : out std_logic; D2A1 : out std_logic; D2A2 : out std_logic; FIFO : out std_logic; FIFOSTAT : out std_logic; IOCS16N : out std_logic; I2CSCL : out std_logic; LBSD3 : out std_logic; SIOR : out std_logic; SIORN : out std_logic; SIORW : out std_logic; SIOW : out std_logic; SIOWN : out std_logic; SYSCTL : out std_logic; BSD : inout std_logic_vector (15 downto 0); I2CSDA : inout std_logic); end ISAintfc; architecture BEHAVIORAL of ISAintfc is attribute BOX_TYPE : string ; attribute HU_SET : string ; signal BRDSELI : std_logic; signal FSEL : std_logic; signal XLXN_157 : std_logic; signal XLXN_158 : std_logic; signal XLXN_159 : std_logic; signal XLXN_161 : std_logic; signal XLXN_206 : std_logic; signal XLXN_210 : std_logic; signal XLXN_212 : std_logic; signal XLXN_214 : std_logic; signal XLXN_216 : std_logic; signal XLXN_221 : std_logic; signal XLXN_222 : std_logic; signal XLXN_370 : std_logic; -- signal XLXN_223a : std_logic; -- signal XLXN_223b : std_logic; -- signal XLXN_223c : std_logic; -- signal XLXN_223d : std_logic; -- signal XLXN_223e : std_logic; -- signal XLXN_223f : std_logic; signal XLXN_225 : std_logic; signal XLXN_229 : std_logic; signal XLXN_230 : std_logic; signal A2DSTAT_DUMMY : std_logic; signal SIOWN_DUMMY : std_logic; signal SIOR_DUMMY : std_logic; signal SIORN_DUMMY : std_logic; signal SIOW_DUMMY : std_logic; signal SIORW_DUMMY : std_logic; signal D2A2_DUMMY : std_logic; -- signal MY_SIORW : std_logic; -- signal cnt : std_logic_vector(1 downto 0):="00"; component INV port ( I : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of INV : component is "BLACK_BOX"; component FD4CE_MXILINX_ISAintfc port ( C : in std_logic; CE : in std_logic; CLR : in std_logic; D0 : in std_logic; D1 : in std_logic; D2 : in std_logic; D3 : in std_logic; Q0 : out std_logic; Q1 : out std_logic; Q2 : out std_logic; Q3 : out std_logic); end component; component D3_8E_MXILINX_ISAintfc port ( A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; E : in std_logic; D0 : out std_logic; D1 : out std_logic; D2 : out std_logic; D3 : out std_logic; D4 : out std_logic; D5 : out std_logic; D6 : out std_logic; D7 : out std_logic); end component; component GND port ( G : out std_logic); end component; attribute BOX_TYPE of GND : component is "BLACK_BOX"; component VCC port ( P : out std_logic); end component; attribute BOX_TYPE of VCC : component is "BLACK_BOX"; component NAND2 port ( I0 : in std_logic; I1 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of NAND2 : component is "BLACK_BOX"; component NOR2 port ( I0 : in std_logic; I1 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of NOR2 : component is "BLACK_BOX"; component BUFE port ( E : in std_logic; I : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of BUFE : component is "BLACK_BOX"; component AND5 port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic; I4 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND5 : component is "BLACK_BOX"; component AND2 port ( I0 : in std_logic; I1 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND2 : component is "BLACK_BOX"; component FD_MXILINX_ISAintfc port ( C : in std_logic; D : in std_logic; Q : out std_logic); end component; attribute HU_SET of XLXI_60 : label is "XLXI_60_0"; attribute HU_SET of XLXI_61 : label is "XLXI_61_1"; attribute HU_SET of XLXI_102 : label is "XLXI_102_2"; attribute HU_SET of XLXI_103 : label is "XLXI_103_3"; begin A2DSTAT <= A2DSTAT_DUMMY; SIOR <= SIOR_DUMMY; SIORN <= SIORN_DUMMY; SIOW <= SIOW_DUMMY; SIOWN <= SIOWN_DUMMY; D2A2 <= D2A2_DUMMY; XLXI_30 : INV port map (I=>SIOW_DUMMY, O=>SIOWN_DUMMY); XLXI_143 : VCC port map (P=>XLXN_370); XLXI_60 : FD4CE_MXILINX_ISAintfc port map (C=>SIOWN_DUMMY, CE=>FSEL, CLR=>XLXN_210, D0=>BSD(0), D1=>BSD(1), D2=>BSD(2), D3=>BSD(3), Q0=>XLXN_157, Q1=>XLXN_158, Q2=>XLXN_159, Q3=>LBSD3); XLXI_61 : D3_8E_MXILINX_ISAintfc port map (A0=>XLXN_157, A1=>XLXN_158, A2=>XLXN_159, E=>XLXN_206, D0=>FIFO, D1=>A2DSTAT_DUMMY, D2=>A2DDATA, D3=>D2A0, D4=>D2A1, D5=>D2A2_DUMMY, D6=>SYSCTL, D7=>FIFOSTAT); XLXI_63 : GND port map (G=>XLXN_210); XLXI_66 : NAND2 port map (I0=>SIORN_DUMMY, I1=>SIOWN_DUMMY, O=>SIORW); XLXI_69 : INV port map (I=>SIOR_DUMMY, O=>SIORN_DUMMY); XLXI_75 : NOR2 port map (I0=>IOWN, I1=>BRDSELO, O=>SIOW_DUMMY); XLXI_76 : NOR2 port map (I0=>IORN, I1=>BRDSELO, O=>SIOR_DUMMY); XLXI_80 : BUFE port map (E=>BRDSELI, I=>XLXN_161, O=>IOCS16N); XLXI_81 : INV port map (I=>BRDSELO, O=>BRDSELI); XLXI_82 : GND port map (G=>XLXN_161); XLXI_90 : INV port map (I=>FSEL, O=>XLXN_206); XLXI_92 : AND5 port map (I0=>BRDSELI, I1=>SA3, I2=>SA2, I3=>SA1, -- I4=>SA0, I4=>XLXN_370, O=>FSEL); XLXI_93 : AND2 -- port map (I0=>FIFOCTL(1), -- I1=>A2DSTAT_DUMMY, port map (I0=>FIFOCTL(7), I1=>D2A2_DUMMY, O=>XLXN_230); XLXI_94 : AND2 port map (I0=>SIOR_DUMMY, I1=>XLXN_230, O=>XLXN_229); XLXI_95 : NAND2 port map (I0=>SIOW_DUMMY, I1=>XLXN_230, O=>XLXN_216); XLXI_96 : INV port map (I=>BSD(0), O=>XLXN_212); XLXI_97 : INV port map (I=>BSD(1), O=>XLXN_214); XLXI_98 : INV port map (I=>XLXN_221, O=>XLXN_222); XLXI_99 : INV port map (I=>XLXN_225, O=>I2CSCL); XLXI_100 : BUFE port map (E=>XLXN_229, I=>I2CSDA, O=>BSD(0)); XLXI_101 : BUFE port map (E=>XLXN_221, I=>XLXN_222, O=>I2CSDA); XLXI_102 : FD_MXILINX_ISAintfc port map (C=>XLXN_216, D=>XLXN_212, Q=>XLXN_221); XLXI_103 : FD_MXILINX_ISAintfc port map (C=>XLXN_216, D=>XLXN_214, Q=>XLXN_225); -- delay: process(pllout,FSEL) -- begin -- if FSEL = '1' then -- cnt <= "00"; -- elsif cnt = "00" and FSEL = '0' then -- cnt <= "01"; -- elsif cnt = "01" and FSEL = '0' then -- cnt <= "10"; -- else -- cnt <= cnt; -- end if; -- end process delay; end BEHAVIORAL;

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use std.textio.all; entity test_typecasts is end test_typecasts; architecture behavioural of test_typecasts is constant natural_value : natural range 255 downto 0 := 164; constant slv_value : std_logic_vector(7 downto 0) := "10100100"; function chr(sl: std_logic) return character is variable c: character; begin case sl is when 'U' => c:= 'U'; when 'X' => c:= 'X'; when '0' => c:= '0'; when '1' => c:= '1'; when 'Z' => c:= 'Z'; when 'W' => c:= 'W'; when 'L' => c:= 'L'; when 'H' => c:= 'H'; when '-' => c:= '-'; end case; return c; end chr; function str(slv: std_logic_vector) return string is variable result : string (1 to slv'length); variable r : integer; begin r := 1; for i in slv'range loop result(r) := chr(slv(i)); r := r + 1; end loop; return result; end str; begin process variable natural_holder : natural range 255 downto 0; variable slv_holder : std_logic_vector(7 downto 0); variable oline: line; begin natural_holder := to_integer(unsigned(slv_value)); assert natural_holder = natural_value report "1 natural and slv should match" severity error; slv_holder := std_logic_vector(to_unsigned(natural_value, slv_holder'length)); assert slv_holder = slv_value report "2 slv and natural should match" severity error; write(oline, str(slv_holder)); write(oline, '='); write(oline, str(slv_value)); writeline(output, oline); wait; end process; end behavioural;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity speccy is Port ( CLK50 : in std_logic; MCU_READY : in std_logic; KEYB_CLK : in std_logic; KEYB_DATA : in std_logic; SD_MOSI : out std_logic; SD_MISO : in std_logic; SD_SCK : out std_logic; SD_CS : out std_logic; SOUND_L : out std_logic; SOUND_R : out std_logic; SRAM_A : out std_logic_vector(17 downto 0); SRAM_D : inout std_logic_vector(15 downto 0); SRAM_WE : out std_logic; SRAM_OE : out std_logic; SRAM_UB : out std_logic; SRAM_LB : out std_logic; SRAM_CE0 : out std_logic; SRAM_CE1 : out std_logic; VGA_R : out std_logic_vector(3 downto 0); VGA_G : out std_logic_vector(3 downto 0); VGA_B : out std_logic_vector(3 downto 0); VGA_HSYNC : out std_logic; VGA_VSYNC : out std_logic ); end speccy; architecture rtl of speccy is signal CLK : std_logic; signal VGA_CLK : std_logic; signal LOCKED : std_logic; signal RESET : std_logic; signal TICK : unsigned(3 downto 0); signal CLC_TICK : std_logic; signal CPU_CLK : std_logic; signal CPU_RESET : std_logic; signal CPU_INT : std_logic; signal CPU_NMI : std_logic; signal CPU_MREQ : std_logic; signal CPU_IORQ : std_logic; signal CPU_M1 : std_logic; signal CPU_RD : std_logic; signal CPU_WR : std_logic; signal CPU_A : std_logic_vector(15 downto 0); signal CPU_DI : std_logic_vector(7 downto 0); signal CPU_DO : std_logic_vector(7 downto 0); signal ROM_DO : std_logic_vector(7 downto 0); signal DIVROM_DO : std_logic_vector(7 downto 0); signal RAM_A : std_logic_vector(19 downto 0); signal RAM_DO : std_logic_vector(7 downto 0); signal RAM_RW : std_logic; signal RAM_REQ : std_logic; signal VRAM_WR : std_logic_vector(0 downto 0); signal VRAM_A : std_logic_vector(13 downto 0); signal VRAM_VA : std_logic_vector(12 downto 0); signal VRAM_VD : std_logic_vector(7 downto 0); signal BORDERCOLOR : std_logic_vector(2 downto 0); signal KEYB_DO : std_logic_vector(4 downto 0); signal RESET_TICK : std_logic; signal RESET_ONESHOT: std_logic; signal NMI_TICK : std_logic; signal NMI_ONESHOT : std_logic; signal BEEPER : std_logic; signal CLC : std_logic; signal AY_CS : std_logic; signal AY_DO : std_logic_vector(7 downto 0); signal AY_A : std_logic_vector(7 downto 0); signal AY_B : std_logic_vector(7 downto 0); signal AY_C : std_logic_vector(7 downto 0); signal AUDIO_L : std_logic_vector(9 downto 0); signal AUDIO_R : std_logic_vector(9 downto 0); ------------------------- 128K ------------------------- signal PAGE : std_logic_vector(2 downto 0) := "000"; signal SCREEN : std_logic := '0'; signal ROMSEL : std_logic := '0'; signal DISABLE : std_logic := '0'; ------------------------ DIVMMC ------------------------ signal BANK : std_logic_vector(5 downto 0) := "000000"; signal CONMEM : std_logic := '0'; signal MAPRAM : std_logic := '0'; signal MAPCOND : std_logic := '0'; signal AUTOMAP : std_logic := '0'; signal counter : unsigned(3 downto 0); -- Shift register has an extra bit because we write on the -- falling edge and read on the rising edge signal shift_reg : std_logic_vector(8 downto 0); signal in_reg : std_logic_vector(7 downto 0); begin u_CLOCK : entity work.clock port map( CLK50 => CLK50, CLK => CLK, VGA_CLK => VGA_CLK, LOCKED => LOCKED ); u_VIDEO : entity work.video port map( VGA_CLK => VGA_CLK, RESET => '0', BORDERCOLOR => BORDERCOLOR, INT => CPU_INT, VA => VRAM_VA, VD => VRAM_VD, VGA_R => VGA_R, VGA_G => VGA_G, VGA_B => VGA_B, VGA_HSYNC => VGA_HSYNC, VGA_VSYNC => VGA_VSYNC ); u_ROM : entity work.rom port map( clka => CLK, addra => ROMSEL & CPU_A(13 downto 0), douta => ROM_DO ); u_DIVROM : entity work.divrom port map( clka => CLK, addra => CPU_A(12 downto 0), douta => DIVROM_DO ); u_VRAM : entity work.vram port map( clka => CLK, wea => VRAM_WR, addra => VRAM_A, dina => CPU_DO, clkb => VGA_CLK, addrb => SCREEN & VRAM_VA, doutb => VRAM_VD ); u_CPU : entity work.T80se port map( RESET_n => CPU_RESET, --not RESET, CLK_n => CLK, CLKEN => CPU_CLK, WAIT_n => '1', INT_n => CPU_INT, NMI_n => CPU_NMI, BUSRQ_n => '1', M1_n => CPU_M1, MREQ_n => CPU_MREQ, IORQ_n => CPU_IORQ, RD_n => CPU_RD, WR_n => CPU_WR, RFSH_n => OPEN, HALT_n => OPEN, BUSAK_n => OPEN, A => CPU_A, DI => CPU_DI, DO => CPU_DO ); u_RAM : entity work.memctrl port map( CLK => CLK, RESET => RESET, MEM_A => RAM_A, MEM_DI => CPU_DO, MEM_DO => RAM_DO, MEM_RW => RAM_RW, MEM_REQ => RAM_REQ, MEM_ACK => open, SRAM_A => SRAM_A, SRAM_D => SRAM_D, SRAM_CE0 => SRAM_CE0, SRAM_CE1 => SRAM_CE1, SRAM_OE => SRAM_OE, SRAM_WE => SRAM_WE, SRAM_UB => SRAM_UB, SRAM_LB => SRAM_LB ); u_KEYBOARD: entity work.keyboard port map( CLK => CLK, RESET => RESET, PS2_CLK => KEYB_CLK, PS2_DATA => KEYB_DATA, KEYB_ADDR => CPU_A(15 downto 8), KEYB_DATA => KEYB_DO, RESET_TICK => RESET_TICK, NMI_TICK => NMI_TICK ); u_ONESHOT_RESET : entity work.oneshot port map( CLK => CLK, RESET => RESET, ONESHOT_IN => RESET_TICK, ONESHOT_OUT => RESET_ONESHOT ); u_ONESHOT_NMI : entity work.oneshot port map( CLK => CLK, RESET => RESET, ONESHOT_IN => NMI_TICK, ONESHOT_OUT => NMI_ONESHOT ); u_AY8910 : entity work.ay8910 port map( CLK => CLK, CLC => CLC, RESET => CPU_RESET, BDIR => not CPU_WR, CS => AY_CS, BC => CPU_A(14), DI => CPU_DO, DO => AY_DO, OUT_A => AY_A, OUT_B => AY_B, OUT_C => AY_C ); u_DAC_L : entity work.dac port map( clk_i => CLK, res_n_i => CPU_RESET, dac_i => AUDIO_L, dac_o => SOUND_L ); u_DAC_R : entity work.dac port map( clk_i => CLK, res_n_i => CPU_RESET, dac_i => AUDIO_R, dac_o => SOUND_R ); AUDIO_L <= std_logic_vector(unsigned('0' & AY_A & '0') + unsigned('0' & BEEPER & AY_B)); AUDIO_R <= std_logic_vector(unsigned('0' & AY_C & '0') + unsigned('0' & BEEPER & AY_B)); CPU_RESET <= not RESET_ONESHOT; reset_and_clock : process(CLK) begin if rising_edge(CLK) then if LOCKED = '0' or MCU_READY = '0' then TICK <= "0000"; RESET <= '1'; CPU_CLK <= '0'; CLC <= '0'; CLC_TICK <= '0'; else CPU_CLK <= '0'; CLC <= '0'; TICK <= TICK + 1; if TICK = "1111" then CPU_CLK <= '1'; RESET <= '0'; CLC_TICK <= not CLC_TICK; if CLC_TICK = '1' then CLC <= '1'; end if; end if; end if; end if; end process; CPU_DI <= ROM_DO when CPU_A(15 downto 14) = "00" and CPU_MREQ = '0' and AUTOMAP = '0' and CONMEM = '0' else DIVROM_DO when CPU_A(15 downto 13) = "000" and CPU_MREQ = '0' and (AUTOMAP = '1' or CONMEM = '1') else RAM_DO when CPU_A(15 downto 13) = "001" and CPU_MREQ = '0' and (AUTOMAP = '1' or CONMEM = '1') else RAM_DO when CPU_A(15 downto 14) /= "00" and CPU_MREQ = '0' else AY_DO when AY_CS = '0' else in_reg when CPU_A(7 downto 0) = X"EB" and CPU_IORQ = '0' else "111" & KEYB_DO when CPU_A(0) = '0' and CPU_IORQ = '0' else "11111111"; VRAM_WR <= "1" when ((CPU_A(15 downto 13) = "010") or (CPU_A(15 downto 13) = "110" and PAGE(2) = '1' and PAGE(0) = '1')) and CPU_MREQ = '0' and CPU_WR = '0' else "0"; VRAM_A <= '0' & CPU_A(12 downto 0) when CPU_A(15 downto 13) = "010" else PAGE(1) & CPU_A(12 downto 0); RAM_A <= '1' & BANK & CPU_A(12 downto 0) when CPU_A(15 downto 13) = "001" and (AUTOMAP = '1' or CONMEM = '1') else "000" & PAGE & CPU_A(13 downto 0) when CPU_A(15 downto 14) = "11" else "000" & CPU_A(14) & CPU_A; RAM_RW <= '1' when CPU_MREQ = '0' and CPU_WR = '0' and (CPU_A(15 downto 14) /= "00" or (CPU_A(15 downto 13) = "001" and (AUTOMAP = '1' or CONMEM = '1'))) else '0'; RAM_REQ <= '1' when TICK = "0100" else '0'; AY_CS <= '0' when CPU_A(15) = '1' and CPU_A(13) = '1' and CPU_A(1) = '0' and CPU_M1 = '1' and CPU_IORQ = '0' else '1'; process(CLK) begin if rising_edge(CLK) then if CPU_RESET = '0' then SD_CS <= '1'; PAGE <= "000"; SCREEN <= '0'; ROMSEL <= '0'; DISABLE <= '0'; elsif TICK = "0011" then if CPU_MREQ = '0' then if CPU_M1 = '0' and CPU_A(15 downto 3) = "0001111111111" then MAPCOND <= '0'; elsif (CPU_M1 = '0' and (CPU_A = X"0000" or CPU_A = X"0008" or CPU_A = X"0038" or CPU_A = X"0066" or CPU_A = X"04C6" or CPU_A = X"0562")) or (CPU_M1 = '0' and CPU_A(15 downto 8) = X"3D") then MAPCOND <= '1'; end if; if MAPCOND = '1' or (CPU_M1 = '0' and CPU_A(15 downto 8) = X"3D") then AUTOMAP <= '1'; else AUTOMAP <= '0'; end if; end if; if CPU_IORQ = '0' and CPU_WR = '0' then if CPU_A(7 downto 0) = X"E7" then -- Port #E7 SD_CS <= CPU_DO(0); elsif CPU_A(7 downto 0) = X"E3" then -- Port #E3 BANK <= CPU_DO(5 downto 0); CONMEM <= CPU_DO(7); MAPRAM <= CPU_DO(6) or MAPRAM; elsif CPU_A(15) = '0' and CPU_A(1) = '0' then -- Port #7FFD if DISABLE = '0' then -- not locked in 48K-mode PAGE <= CPU_DO(2 downto 0); SCREEN <= CPU_DO(3); ROMSEL <= CPU_DO(4); DISABLE <= CPU_DO(5); end if; elsif CPU_A(0) = '0' then -- Port #FE BORDERCOLOR <= CPU_DO(2 downto 0); BEEPER <= CPU_DO(4); end if; end if; end if; end if; end process; CPU_NMI <= '0' when NMI_ONESHOT = '1' and MAPCOND = '0' else '1'; sd_card : process(CLK) begin if rising_edge(CLK) then if CPU_RESET = '0' then shift_reg <= (others => '1'); in_reg <= (others => '1'); counter <= "1111"; -- Idle elsif TICK = "0011" then if counter = "1111" then in_reg <= shift_reg(7 downto 0); if CPU_IORQ = '0' and CPU_A(7 downto 0) = X"EB" then if CPU_WR = '1' then shift_reg <= (others => '1'); else shift_reg <= CPU_DO & '1'; end if; counter <= "0000"; end if; else counter <= counter + 1; if counter(0) = '0' then shift_reg(0) <= SD_MISO; else shift_reg <= shift_reg(7 downto 0) & '1'; end if; end if; end if; end if; end process; SD_SCK <= counter(0); SD_MOSI <= shift_reg(8); end rtl;

entity tb_cnt01 is end tb_cnt01; library ieee; use ieee.std_logic_1164.all; architecture behav of tb_cnt01 is signal clk : std_logic; signal rst : std_logic; signal clr : std_logic; signal en : std_logic; signal cnt : std_logic_vector (9 downto 0); begin dut: entity work.cnt01 port map (clock => clk, reset => rst, clear_count => clr, enable => en, counter_out => cnt); process procedure pulse is begin clk <= '0'; wait for 1 ns; clk <= '1'; wait for 1 ns; end pulse; begin clk <= '0'; clr <= '0'; en <= '0'; rst <= '1'; wait for 1 ns; assert cnt = "0000000000" severity failure; rst <= '0'; pulse; assert cnt = "0000000000" severity failure; en <= '1'; pulse; assert cnt = "0000000001" severity failure; en <= '0'; pulse; assert cnt = "0000000001" severity failure; en <= '1'; pulse; assert cnt = "0000000010" severity failure; en <= '1'; pulse; assert cnt = "0000000011" severity failure; en <= '1'; clr <= '1'; pulse; assert cnt = "0000000000" severity failure; en <= '1'; clr <= '0'; pulse; assert cnt = "0000000001" severity failure; wait; end process; end behav;

-- ------------------------------------------------------------- -- -- File Name: hdlsrc\hdlcodercpu_eml\SinglePortRAM_Inst0.vhd -- Created: 2014-08-26 11:41:14 -- -- Generated by MATLAB 8.3 and HDL Coder 3.4 -- -- ------------------------------------------------------------- -- ------------------------------------------------------------- -- -- Module: SinglePortRAM_Inst0 -- Source Path: hdlcodercpu_eml/CPU_Subsystem_8_bit/SinglePortRAM_Inst0 -- Hierarchy Level: 1 -- -- ------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; ENTITY SinglePortRAM_Inst0 IS PORT( clk : IN std_logic; enb : IN std_logic; din : IN std_logic_vector(7 DOWNTO 0); -- int8 addr : IN std_logic_vector(7 DOWNTO 0); -- uint8 we : IN std_logic; -- ufix1 dout : OUT std_logic_vector(7 DOWNTO 0) -- int8 ); END SinglePortRAM_Inst0; ARCHITECTURE rtl OF SinglePortRAM_Inst0 IS -- Component Declarations COMPONENT SinglePortRAM_256x8b PORT( clk : IN std_logic; enb : IN std_logic; din : IN std_logic_vector(7 DOWNTO 0); -- int8 addr : IN std_logic_vector(7 DOWNTO 0); -- uint8 we : IN std_logic; -- ufix1 dout : OUT std_logic_vector(7 DOWNTO 0) -- int8 ); END COMPONENT; -- Component Configuration Statements FOR ALL : SinglePortRAM_256x8b USE ENTITY work.SinglePortRAM_256x8b(rtl); -- Signals SIGNAL dout_tmp : std_logic_vector(7 DOWNTO 0); -- ufix8 BEGIN u_SinglePortRAM_256x8b : SinglePortRAM_256x8b PORT MAP( clk => clk, enb => enb, din => din, -- int8 addr => addr, -- uint8 we => we, -- ufix1 dout => dout_tmp -- int8 ); dout <= dout_tmp; END rtl;

-------------------------------------------------------------------------------- -- -- FIFO Generator Core Demo Testbench -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: fg_tb_pkg.vhd -- -- Description: -- This is the demo testbench package file for fifo_generator_v8.4 core. -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE ieee.std_logic_arith.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; PACKAGE fg_tb_pkg IS FUNCTION divroundup ( data_value : INTEGER; divisor : INTEGER) RETURN INTEGER; ------------------------ FUNCTION if_then_else ( condition : BOOLEAN; true_case : INTEGER; false_case : INTEGER) RETURN INTEGER; ------------------------ FUNCTION if_then_else ( condition : BOOLEAN; true_case : STD_LOGIC; false_case : STD_LOGIC) RETURN STD_LOGIC; ------------------------ FUNCTION if_then_else ( condition : BOOLEAN; true_case : TIME; false_case : TIME) RETURN TIME; ------------------------ FUNCTION log2roundup ( data_value : INTEGER) RETURN INTEGER; ------------------------ FUNCTION hexstr_to_std_logic_vec( arg1 : string; size : integer ) RETURN std_logic_vector; ------------------------ COMPONENT fg_tb_rng IS GENERIC (WIDTH : integer := 8; SEED : integer := 3); PORT ( CLK : IN STD_LOGIC; RESET : IN STD_LOGIC; ENABLE : IN STD_LOGIC; RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) ); END COMPONENT; ------------------------ COMPONENT fg_tb_dgen IS GENERIC ( C_DIN_WIDTH : INTEGER := 32; C_DOUT_WIDTH : INTEGER := 32; C_CH_TYPE : INTEGER := 0; TB_SEED : INTEGER := 2 ); PORT ( RESET : IN STD_LOGIC; WR_CLK : IN STD_LOGIC; PRC_WR_EN : IN STD_LOGIC; FULL : IN STD_LOGIC; WR_EN : OUT STD_LOGIC; WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0) ); END COMPONENT; ------------------------ COMPONENT fg_tb_dverif IS GENERIC( C_DIN_WIDTH : INTEGER := 0; C_DOUT_WIDTH : INTEGER := 0; C_USE_EMBEDDED_REG : INTEGER := 0; C_CH_TYPE : INTEGER := 0; TB_SEED : INTEGER := 2 ); PORT( RESET : IN STD_LOGIC; RD_CLK : IN STD_LOGIC; PRC_RD_EN : IN STD_LOGIC; EMPTY : IN STD_LOGIC; DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); RD_EN : OUT STD_LOGIC; DOUT_CHK : OUT STD_LOGIC ); END COMPONENT; ------------------------ COMPONENT fg_tb_pctrl IS GENERIC( AXI_CHANNEL : STRING := "NONE"; C_APPLICATION_TYPE : INTEGER := 0; C_DIN_WIDTH : INTEGER := 0; C_DOUT_WIDTH : INTEGER := 0; C_WR_PNTR_WIDTH : INTEGER := 0; C_RD_PNTR_WIDTH : INTEGER := 0; C_CH_TYPE : INTEGER := 0; FREEZEON_ERROR : INTEGER := 0; TB_STOP_CNT : INTEGER := 2; TB_SEED : INTEGER := 2 ); PORT( RESET_WR : IN STD_LOGIC; RESET_RD : IN STD_LOGIC; WR_CLK : IN STD_LOGIC; RD_CLK : IN STD_LOGIC; FULL : IN STD_LOGIC; EMPTY : IN STD_LOGIC; ALMOST_FULL : IN STD_LOGIC; ALMOST_EMPTY : IN STD_LOGIC; DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0); DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0); DOUT_CHK : IN STD_LOGIC; PRC_WR_EN : OUT STD_LOGIC; PRC_RD_EN : OUT STD_LOGIC; RESET_EN : OUT STD_LOGIC; SIM_DONE : OUT STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; ------------------------ COMPONENT fg_tb_synth IS GENERIC( FREEZEON_ERROR : INTEGER := 0; TB_STOP_CNT : INTEGER := 0; TB_SEED : INTEGER := 1 ); PORT( CLK : IN STD_LOGIC; RESET : IN STD_LOGIC; SIM_DONE : OUT STD_LOGIC; STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; ------------------------ COMPONENT gc_command_fifo_top IS PORT ( CLK : IN std_logic; DATA_COUNT : OUT std_logic_vector(5-1 DOWNTO 0); RST : IN std_logic; PROG_FULL : OUT std_logic; WR_EN : IN std_logic; RD_EN : IN std_logic; DIN : IN std_logic_vector(29-1 DOWNTO 0); DOUT : OUT std_logic_vector(29-1 DOWNTO 0); FULL : OUT std_logic; EMPTY : OUT std_logic); END COMPONENT; ------------------------ END fg_tb_pkg; PACKAGE BODY fg_tb_pkg IS FUNCTION divroundup ( data_value : INTEGER; divisor : INTEGER) RETURN INTEGER IS VARIABLE div : INTEGER; BEGIN div := data_value/divisor; IF ( (data_value MOD divisor) /= 0) THEN div := div+1; END IF; RETURN div; END divroundup; --------------------------------- FUNCTION if_then_else ( condition : BOOLEAN; true_case : INTEGER; false_case : INTEGER) RETURN INTEGER IS VARIABLE retval : INTEGER := 0; BEGIN IF condition=false THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; --------------------------------- FUNCTION if_then_else ( condition : BOOLEAN; true_case : STD_LOGIC; false_case : STD_LOGIC) RETURN STD_LOGIC IS VARIABLE retval : STD_LOGIC := '0'; BEGIN IF condition=false THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; --------------------------------- FUNCTION if_then_else ( condition : BOOLEAN; true_case : TIME; false_case : TIME) RETURN TIME IS VARIABLE retval : TIME := 0 ps; BEGIN IF condition=false THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; ------------------------------- FUNCTION log2roundup ( data_value : INTEGER) RETURN INTEGER IS VARIABLE width : INTEGER := 0; VARIABLE cnt : INTEGER := 1; BEGIN IF (data_value <= 1) THEN width := 1; ELSE WHILE (cnt < data_value) LOOP width := width + 1; cnt := cnt *2; END LOOP; END IF; RETURN width; END log2roundup; ------------------------------------------------------------------------------ -- hexstr_to_std_logic_vec -- This function converts a hex string to a std_logic_vector ------------------------------------------------------------------------------ FUNCTION hexstr_to_std_logic_vec( arg1 : string; size : integer ) RETURN std_logic_vector IS VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0'); VARIABLE bin : std_logic_vector(3 DOWNTO 0); VARIABLE index : integer := 0; BEGIN FOR i IN arg1'reverse_range LOOP CASE arg1(i) IS WHEN '0' => bin := (OTHERS => '0'); WHEN '1' => bin := (0 => '1', OTHERS => '0'); WHEN '2' => bin := (1 => '1', OTHERS => '0'); WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0'); WHEN '4' => bin := (2 => '1', OTHERS => '0'); WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0'); WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0'); WHEN '7' => bin := (3 => '0', OTHERS => '1'); WHEN '8' => bin := (3 => '1', OTHERS => '0'); WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0'); WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1'); WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1'); WHEN 'B' => bin := (2 => '0', OTHERS => '1'); WHEN 'b' => bin := (2 => '0', OTHERS => '1'); WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1'); WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1'); WHEN 'D' => bin := (1 => '0', OTHERS => '1'); WHEN 'd' => bin := (1 => '0', OTHERS => '1'); WHEN 'E' => bin := (0 => '0', OTHERS => '1'); WHEN 'e' => bin := (0 => '0', OTHERS => '1'); WHEN 'F' => bin := (OTHERS => '1'); WHEN 'f' => bin := (OTHERS => '1'); WHEN OTHERS => FOR j IN 0 TO 3 LOOP bin(j) := 'X'; END LOOP; END CASE; FOR j IN 0 TO 3 LOOP IF (index*4)+j < size THEN result((index*4)+j) := bin(j); END IF; END LOOP; index := index + 1; END LOOP; RETURN result; END hexstr_to_std_logic_vec; END fg_tb_pkg;

architecture RTL of BLOCK_EXAMPLE is begin -- correct block format BLK : block is begin BLK2 : block is begin BLK3 : block is begin end block BLK3; end block BLK2; BLK4 : block is begin BLK5 : block is begin BLK6 : block is begin end block BLK6; end block BLK5; end block BLK4; end block BLK; b1 : block begin end block; process begin end process; b1 : block begin process begin end process; end block; assert true report "something" severity failure; end architecture RTL;

------------------------------------------------------------------------------- -- Title : Onewire Master Testbench - Reset Operation ------------------------------------------------------------------------------- -- Author : [email protected] ------------------------------------------------------------------------------- -- Created : 2014-12-13 ------------------------------------------------------------------------------- -- Copyright (c) 2014, Carl Treudler -- All Rights Reserved. -- -- The file is part for the Loa project and is released under the -- 3-clause BSD license. See the file `LICENSE` for the full license -- governing this code. ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; use work.onewire_pkg.all; use work.onewire_cfg_pkg.all; ------------------------------------------------------------------------------- entity onewire_reset_tb is end onewire_reset_tb; ------------------------------------------------------------------------------- architecture tb of onewire_reset_tb is component onewire port ( onewire_in : in onewire_in_type; onewire_out : out onewire_out_type; onewire_bus_in : in onewire_bus_in_type; onewire_bus_out : out onewire_bus_out_type; clk : in std_logic); end component; -- component ports signal onewire_in : onewire_in_type; signal onewire_out : onewire_out_type; signal onewire_bus_in : onewire_bus_in_type; signal onewire_bus_out : onewire_bus_out_type; -- clock signal Clk : std_logic := '1'; begin -- tb -- component instantiation DUT : onewire port map ( onewire_in => onewire_in, onewire_out => onewire_out, onewire_bus_in => onewire_bus_in, onewire_bus_out => onewire_bus_out, clk => clk); -- clock generation Clk <= not Clk after 10 ns; -- 50MHz Clock -- waveform generation WaveGen_Proc : process begin onewire_in.d <= (others => '0'); onewire_in.re <= '0'; onewire_in.we <= '0'; onewire_in.reset_bus <= '0'; wait until Clk = '1'; wait until Clk = '1'; wait until Clk = '1'; onewire_in.reset_bus <= '1'; wait until Clk = '1'; onewire_in.reset_bus <= '0'; wait for 2.5 ms; end process WaveGen_Proc; WaveGen_onewire_device : process variable device_response : std_logic := '0'; begin onewire_bus_in.d <= '1'; wait until onewire_bus_out.en_driver = '1'; wait for 480 us; wait for 60 us; onewire_bus_in.d <= device_response; device_response := not device_response; -- Bus reset will fail every second -- time. wait for 240 us; end process WaveGen_onewire_device; end tb;

library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.numeric_std.all; entity add_393 is port ( result : out std_logic_vector(31 downto 0); in_a : in std_logic_vector(31 downto 0); in_b : in std_logic_vector(31 downto 0) ); end add_393; architecture augh of add_393 is signal carry_inA : std_logic_vector(33 downto 0); signal carry_inB : std_logic_vector(33 downto 0); signal carry_res : std_logic_vector(33 downto 0); begin -- To handle the CI input, the operation is '1' + CI -- If CI is not present, the operation is '1' + '0' carry_inA <= '0' & in_a & '1'; carry_inB <= '0' & in_b & '0'; -- Compute the result carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB)); -- Set the outputs result <= carry_res(32 downto 1); end architecture;

architecture RTL of FIFO is function func1 return integer is begin END function func1; function func1 return integer is begin END function func1; function func1 return integer is begin END function func1; procedure proc1 is begin End procedure proc1; begin end architecture RTL;

entity tb_revrng01 is end tb_revrng01; library ieee; use ieee.std_logic_1164.all; architecture behav of tb_revrng01 is signal a, z : std_logic_vector (7 downto 0); begin dut: entity work.revrng01 port map (a, z); process begin a <= x"a1"; wait for 1 ns; assert z = x"85" severity failure; wait; end process; end behav;

library verilog; use verilog.vl_types.all; entity dummy_hub is generic( sld_node_ir_width: integer := 16 ); port( jtag_tck : in vl_logic; jtag_tdi : in vl_logic; jtag_tms : in vl_logic; jtag_usr1 : in vl_logic; jtag_state_tlr : in vl_logic; jtag_state_rti : in vl_logic; jtag_state_drs : in vl_logic; jtag_state_cdr : in vl_logic; jtag_state_sdr : in vl_logic; jtag_state_e1dr : in vl_logic; jtag_state_pdr : in vl_logic; jtag_state_e2dr : in vl_logic; jtag_state_udr : in vl_logic; jtag_state_irs : in vl_logic; jtag_state_cir : in vl_logic; jtag_state_sir : in vl_logic; jtag_state_e1ir : in vl_logic; jtag_state_pir : in vl_logic; jtag_state_e2ir : in vl_logic; jtag_state_uir : in vl_logic; dummy_tdo : in vl_logic; virtual_ir_out : in vl_logic_vector; jtag_tdo : out vl_logic; dummy_tck : out vl_logic; dummy_tdi : out vl_logic; dummy_tms : out vl_logic; dummy_state_tlr : out vl_logic; dummy_state_rti : out vl_logic; dummy_state_drs : out vl_logic; dummy_state_cdr : out vl_logic; dummy_state_sdr : out vl_logic; dummy_state_e1dr: out vl_logic; dummy_state_pdr : out vl_logic; dummy_state_e2dr: out vl_logic; dummy_state_udr : out vl_logic; dummy_state_irs : out vl_logic; dummy_state_cir : out vl_logic; dummy_state_sir : out vl_logic; dummy_state_e1ir: out vl_logic; dummy_state_pir : out vl_logic; dummy_state_e2ir: out vl_logic; dummy_state_uir : out vl_logic; virtual_state_cdr: out vl_logic; virtual_state_sdr: out vl_logic; virtual_state_e1dr: out vl_logic; virtual_state_pdr: out vl_logic; virtual_state_e2dr: out vl_logic; virtual_state_udr: out vl_logic; virtual_state_cir: out vl_logic; virtual_state_uir: out vl_logic; virtual_ir_in : out vl_logic_vector ); attribute mti_svvh_generic_type : integer; attribute mti_svvh_generic_type of sld_node_ir_width : constant is 1; end dummy_hub;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity CU is Port ( OP : in STD_LOGIC_VECTOR (1 downto 0); OP3 : in STD_LOGIC_VECTOR (5 downto 0); icc : in STD_LOGIC_VECTOR (3 downto 0); Cond : in STD_LOGIC_VECTOR (3 downto 0); wren : out STD_LOGIC; PCsource : out STD_LOGIC_VECTOR (1 downto 0); ALUOP : out STD_LOGIC_VECTOR (5 downto 0); RdEnMem : out STD_LOGIC; WrEnMem : out STD_LOGIC; RFsource : out STD_LOGIC_VECTOR (1 downto 0); RFdest : out STD_LOGIC ); end CU; architecture Behavioral of CU is signal calcicc : std_logic := '0'; begin process(op, op3, icc, cond) begin --valores for defecto PCsource <= "11"; RFsource <= "01"; wren <= '0'; RdEnMem <= '0'; WrEnMem <= '0'; RFdest <= '0'; if(op = "10") then --formato3 wren <= '1'; case op3 is when "000000" => --Add aluop <= "000000"; --0 when "000100" => --Sub aluop <= "000001"; --1 when "000001" => -- And aluop <= "000010"; --2 when "000101" => --Andn aluop <= "000011"; --3 when "000010" => --or aluop <= "000100"; --4 when "000110" => --orn aluop <= "000101"; --5 when "000011" => --xor aluop <= "000110"; --6 when "000111" => --xnor aluop <= "000111"; --7 when "010100" => --SUBcc aluop <= "001000"; --8 when "001100" => --SUBx aluop <= "001001"; --9 when "011100" => --SUBxcc aluop <= "001010"; --10 when "010001" => --ANDcc aluop <= "001011"; --11 when "010101" => --ANDNcc aluop <= "001100"; --12 when "010010" => --ORcc aluop <= "001101"; --13 when "010110" => --ORNcc aluop <= "001110"; --14 when "010011" => --XORcc aluop <= "001111"; --15 when "010111" => --XNORcc aluop <= "010000"; --16 when "001000" => --ADDx aluop <= "010001"; --17 when "011000" => --ADDxcc aluop <= "010010"; --18 when "010000" => --ADDcc aluop <= "010011"; --19 when "100101" => AluOp <= "100101";--SLL Shift Left Logical 37 when "100110" => AluOp <= "100110";--SRL Shift Right Logical 38 when "111100" => AluOp <= "111100";--Save 60 when "111101" => AluOp <= "111101";--RESTORE 61 when "111000" => ALUOP <= "010100"; RFsource <= "10";--selecciona PC como datatoreg PCsource <= "00";--operacion de la alu RFdest <= '0';--seleccion nRD when others => aluop <= (others=>'1'); --error end case; elsif (op = "11") then case OP3 is when "000000" =>--load word ALUOP <= "010101"; --21 RdEnMem <= '1';--activa lectura en memoria WrEnMem <= '0'; RFsource <= "00";--selecciona dato de memoria como datatoreg wren <= '1'; when "000100" =>--store word ALUOP <= "010110"; --22 WrEnMem <= '1';--activa escritura en memoria RdEnMem <= '0'; when others => ALUOP <= "000000"; end case; elsif(OP = "01") then ALUOP <= "000000"; wren <='0'; RFsource <= "10";--selecciona PC como datatoreg RFdest <= '1';--selecciona no7 como registro de destino PCsource <= "01";--selecciona disp30 como source del PC WrEnMem <= '0'; RdEnMem <= '1'; elsif(OP = "00") then --NZCV wren <= '0'; ALUOP <= "000000"; case cond is when "1000" => PCsource <= "10";--BA escoge disp22 como source when "1001" =>--BNE calcicc <= not icc(2); if(calcicc = '1') then PCsource <= "10"; end if; when "0001" =>--BE calcicc <= icc(2); if(calcicc='1') then PCsource <= "10"; end if; when "1010" =>--BG calcicc <= not (icc(2) or (icc(3) xor icc(0))); if(calcicc = '1') then PCsource <= "10"; end if; when "0010" =>--BLE calcicc <= icc(2) or (icc(3) xor icc(0)); if(calcicc='1') then PCsource <= "10"; end if; when "1011" =>--BGE calcicc <= not(icc(3) xor icc(0)); if(calcicc='1') then PCsource <= "10"; end if; when "0011" =>--BL calcicc <= (icc(3) xor icc(0)); if(calcicc='1') then PCsource <= "10"; end if; when "1100" =>--BGU calcicc <= not(icc(1) or icc(2)); if(calcicc='1') then PCsource <= "10"; end if; when "0100" =>--BLEU calcicc <= (icc(1) or icc(2)); if(calcicc='1') then PCsource <= "10"; end if; when "1101" =>--BCC calcicc <= not icc(1); if(calcicc='1') then PCsource <= "10"; end if; when "0101" =>--BCS calcicc <= icc(1); if(calcicc='1') then PCsource <= "10"; end if; when "1110" =>--BPOS calcicc <= not icc(3); if(calcicc='1') then PCsource <= "10"; end if; when "0110" =>--BNEG calcicc <= icc(3); if(calcicc='1') then PCsource <= "10"; end if; when "1111" =>--BVC calcicc <= not icc(0); if(calcicc='1') then PCsource <= "10"; end if; when "0111" =>--BVS calcicc <= icc(0); if(calcicc='1') then PCsource <= "10"; end if; when others => PCsource <="00"; end case; end if; end process; end Behavioral;

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 12:12:44 08/17/2014 -- Design Name: -- Module Name: vga_tx_display - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity vga_tx_display is Port ( clk : in STD_LOGIC; E_TX_CLK : in STD_LOGIC; E_TXD : in STD_LOGIC_VECTOR (3 downto 0); E_TX_EN : in std_logic; Char_DI : out STD_LOGIC_VECTOR (7 downto 0); Char_WE : out STD_LOGIC; reset : in std_logic); end vga_tx_display; architecture Behavioral of vga_tx_display is type state_type is (IDLE, START_RISING_EDGE, KEEP_RISING_EDGE, START_FALLING_EDGE, WAIT_FOR_DOWN); signal state, next_state : state_type; signal latched_data : std_logic_vector(3 downto 0) := (others=>'0'); begin process (E_TX_CLK) begin if rising_edge(E_TX_CLK) then if(E_TX_EN = '1') then latched_data <= E_TXD(3 downto 0); end if; end if; end process; SYNC_PROC: process (clk) begin if rising_edge(clk) then if (reset = '1') then state <= IDLE; else state <= next_state; end if; end if; end process; OUTPUT_DECODE: process (state) begin if state = IDLE then Char_DI <= (others=>'0'); Char_WE <= '0'; elsif state = START_RISING_EDGE then Char_DI <= "0011" & latched_data; Char_WE <= '1'; elsif state = START_FALLING_EDGE then Char_DI <= (others=>'0'); Char_WE <= '0'; else Char_DI <= (others=>'0'); Char_WE <= '0'; end if; end process; NEXT_STATE_DECODE: process (state, E_TX_CLK) begin next_state <= state; case (state) is when IDLE => if E_TX_EN = '1' and E_TX_CLK = '1' then next_state <= START_RISING_EDGE; end if; when START_RISING_EDGE => next_state <= START_FALLING_EDGE; when START_FALLING_EDGE => next_state <= WAIT_FOR_DOWN; when WAIT_FOR_DOWN => if E_TX_CLK = '0' then next_state <= IDLE; end if; when others => next_state <= IDLE; end case; end process; end Behavioral;

entity FIFO is generic ( G_GEN1 : integer; G_GEN2 : std_logic; G_GENA : t_user2; G_GEN3 : std_logic_vector(3 downto 0); G_GEN4 : signed(15 downto 0); G_GEN5 : unsigned(7 downto 0); G_GEN6 : std_ulogic; G_GEN7 : t_user1 ); end entity FIFO; -- Violation below entity FIFO is generic ( G_GEN1 : integer; G_GEN2 : std_logic; G_GENA : T_USER2; G_GEN3 : std_logic_vector(3 downto 0); G_GEN4 : signed(15 downto 0); G_GEN5 : unsigned(7 downto 0); G_GEN6 : std_ulogic; G_GEN7 : T_USER1 ); end entity FIFO;

-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_13_fg_13_25.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- entity nand3 is generic ( Tpd : delay_length ); port ( a, b, c : in bit; y : out bit ); end entity nand3; architecture basic of nand3 is begin y <= not (a and b and c) after Tpd; end architecture basic; library project_lib; library stimulus; use stimulus.stimulus_generators.all; entity misc_logic is end entity misc_logic; -- code from book architecture gate_level of misc_logic is component nand3 is generic ( Tpd : delay_length ); port ( a, b, c : in bit; y : out bit ); end component nand3; for all : nand3 use entity project_lib.nand3(basic); -- . . . -- not in book signal sig1, sig2, sig3, out_sig : bit; signal test_vector : bit_vector(1 to 3); -- end not in book begin gate1 : component nand3 generic map ( Tpd => 2 ns ) port map ( a => sig1, b => sig2, c => sig3, y => out_sig ); -- . . . -- not in book all_possible_values(test_vector, 10 ns); (sig1, sig2, sig3) <= test_vector; -- end not in book end architecture gate_level; -- end code from book

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; use work.HammingPack16.all; use work.PhoenixPackage.all; entity HAM_ENC is port ( data_in : in regflit; -- data input data_out : out reghamm -- data output ); end HAM_ENC; architecture HAM_ENC of HAM_ENC is signal P : Std_logic_vector(5 downto 1); --Hamming bits begin P(1) <= xor_reduce(data_in and MaskP1); P(2) <= xor_reduce(data_in and MaskP2); P(3) <= xor_reduce(data_in and MaskP4); P(4) <= xor_reduce(data_in and MaskP8); P(5) <= xor_reduce(data_in and MaskP16); data_out <= P & xor_reduce(P & data_in); end HAM_ENC;

------------------------------------------------------------------------------- -- axi_cdma_sg_cntlr ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_cdma_sg_cntlr.vhd -- Description: This entity is reset module entity for the AXI DMA core. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library lib_pkg_v1_0; use lib_pkg_v1_0.lib_pkg.all; library axi_cdma_v4_1; use axi_cdma_v4_1.axi_cdma_pulse_gen; ------------------------------------------------------------------------------- entity axi_cdma_sg_cntlr is Generic ( C_SG_ADDR_WIDTH : integer := 32; C_SG_FETCH_DWIDTH : integer := 32; C_SG_PTR_UPDATE_DWIDTH : integer := 32; C_SG_STS_UPDATE_DWIDTH : integer := 33; C_DM_CMD_WIDTH : integer := 72; C_DM_DATA_WIDTH : integer := 32; C_DM_MM2S_STATUS_WIDTH : integer := 8; C_DM_S2MM_STATUS_WIDTH : integer := 8; C_FAMILY : String := "virtex7" ); port ( -- Clock Input axi_aclk : in std_logic ; -- Reset Input (active high) axi_reset : in std_logic ; -- Halt request from the Reset module rst2sgcntl_halt : in std_logic ; -- Halt complete status to the Reset module sgcntl2rst_halt_cmplt : out std_logic ; -- SG Queue Flush Request sgcntlr2sg_desc_flush : out std_logic ; -- Register Module SG Mode Control reg2sgcntl_sg_mode : in std_logic ; -- MM2S Type of Burst, 1 is increment, 0 is fixed burst_type_read : in std_logic; -- S2MM Type of Burst, 1 is increment, 0 is fixed burst_type_write : in std_logic; -- Register Module Tail pointer updated flag reg2sgcntl_tailpntr_updated : in std_logic ; -- Register Module Current Desciptor pointer updated flag reg2sgcntl_currdesc_updated : in std_logic ; -- Run/Stop Control to SG sgcntlr2sg_run_stop : out std_logic ; -- Idle bit set to Register Module Status Register sgcntl2reg_idle_set : out std_logic ; -- Idle bit clear to Register Module Status Register sgcntl2reg_idle_clr : out std_logic ; -- SOF control to SG sgcntl2sg_pkt_sof : out std_logic ; -- EOF control to SG sgcntl2sg_pkt_eof : out std_logic ; -- Interrupt on complete status bit set from SG sg2sgcntl_ioc_irq_set : in std_logic ; -- Delay Interrupt status bit set from SG sg2sgcntl_dly_irq_set : in std_logic ; -- Interrupt on complete status bit set to Register Module sgcntl2reg_ioc_irq_set : out std_logic ; -- Delay Interrupt status bit set to Register Module sgcntl2reg_dly_irq_set : out std_logic ; -- Descriptor Fetch Stream Interface from SG sgcntl2sg_ftch_tready : out std_logic ; -- Axi4-Stream sg2sgcntlr_ftch_tvalid : in std_logic ; -- Axi4-Stream sg2sgcntlr_ftch_tvalid_new : in std_logic ; -- Axi4-Stream sg2sgcntlr_ftch_tdata : in std_logic_vector(C_SG_FETCH_DWIDTH-1 downto 0) ; -- Axi4-Stream sg2sgcntlr_ftch_tdata_new : in std_logic_vector(127 downto 0) ; -- Axi4-Stream sg2sgcntlr_ftch_tlast : in std_logic ; -- Axi4-Stream sig_sg2sgcntlr_ftch_desc_available : in std_logic; -- Descriptor Pointer Update Stream to SG sg2sgcntlr_updptr_tready : in std_logic ; -- Axi4-Stream sgcntl2sg_updptr_tvalid : out std_logic ; -- Axi4-Stream sgcntl2sg_updptr_tdata : out std_logic_vector(C_SG_PTR_UPDATE_DWIDTH-1 downto 0) ;-- Axi4-Stream sgcntl2sg_updptr_tlast : out std_logic ; -- Axi4-Stream -- Descriptor Status Update Stream to SG sg2sgcntlr_updsts_tready : in std_logic ; -- Axi4-Stream sgcntl2sg_updsts_tvalid : out std_logic ; -- Axi4-Stream sgcntl2sg_updsts_tdata : out std_logic_vector(C_SG_STS_UPDATE_DWIDTH-1 downto 0) ;-- Axi4-Stream sgcntl2sg_updsts_tlast : out std_logic ; -- Axi4-Stream -- Descriptor Fetch Idle status from SG sg2sgcntlr_ftch_idle : in std_logic ; -- Descriptor Fetch error early from SG sg2sgcntlr_ftch_err_early : in std_logic ; -- Descriptor Fetch stale descriptor error from SG sg2sgcntlr_ftch_stale_desc : in std_logic ; -- Descriptor Fetch error from SG sg2sgcntlr_ftch_error : in std_logic ; -- Descriptor update Idle status from SG sg2sgcntlr_updt_idle : in std_logic ; -- Descriptor interrupt on complete bit set from SG sg2sgcntlr_updt_ioc_irq_set : in std_logic ; -- Descriptor Update error from SG sg2sgcntlr_updt_error : in std_logic ; -- Echo of Main DataMover internal error from SG sg2sgcntlr_dma_interr_set : in std_logic ; -- Echo of Main DataMover Slave error from SG sg2sgcntlr_dma_slverr_set : in std_logic ; -- Echo of Main DataMover Decode error from SG sg2sgcntlr_dma_decerr_set : in std_logic ; -- Echo of Main DataMover internal error to the Register Module sgcntlr2reg_dma_interr_set : out std_logic ; -- Echo of Main DataMover Slave error to the Register Module sgcntlr2reg_dma_slverr_set : out std_logic ; -- Echo of Main DataMover Decode error to the Register Module sgcntlr2reg_dma_decerr_set : out std_logic ; -- Current Descriptor write control to Register Module sgcntlr2reg_new_curdesc_wren : out std_logic ; -- Current Descriptor to Register Module sgcntlr2reg_new_curdesc : out std_logic_vector(C_SG_ADDR_WIDTH-1 downto 0) ; -- DataMover MM2S Command Interface Ports (AXI Stream) mm2s2sgcntl_cmd_tready : in std_logic ; -- DM MM2S CMD IF sgcntl2mm2s_cmd_tvalid : out std_logic ; -- DM MM2S CMD IF sgcntl2mm2s_cmd_tdata : out std_logic_vector(C_DM_CMD_WIDTH-1 downto 0); -- DM MM2S CMD IF -- DataMover MM2S Status Interface Ports (AXI Stream) sgcntl2mm2s_sts_tready : out std_logic ; -- DM MM2S Status IF mm2s2sgcntl_sts_tvalid : in std_logic ; -- DM MM2S Status IF mm2s2sgcntl_sts_tdata : in std_logic_vector(C_DM_MM2S_STATUS_WIDTH-1 downto 0); -- DM MM2S Status IF mm2s2sgcntl_sts_tstrb : in std_logic_vector((C_DM_MM2S_STATUS_WIDTH/8)-1 downto 0); -- DM MM2S Status IF -- DataMover MM2S error discrete mm2s2sgcntl_err : in std_logic ; -- DataMover MM2S Halt request input sgcntl2mm2s_halt : Out std_logic ; -- DataMover MM2S Halt complete flag mm2s2sgcntl_halt_cmplt : In std_logic ; -- DataMover S2MM Command Interface Ports (AXI Stream) s2mm2sgcntl_cmd_tready : in std_logic ; -- DM S2MM CMD IF sgcntl2s2mm_cmd_tvalid : out std_logic ; -- DM S2MM CMD IF sgcntl2s2mm_cmd_tdata : out std_logic_vector(C_DM_CMD_WIDTH-1 downto 0); -- DM S2MM CMD IF -- DataMover S2MM Status Interface Ports (AXI Stream) sgcntl2s2mm_sts_tready : out std_logic ; -- DM S2MM Status IF s2mm2sgcntl_sts_tvalid : in std_logic ; -- DM S2MM Status IF s2mm2sgcntl_sts_tdata : in std_logic_vector(C_DM_S2MM_STATUS_WIDTH-1 downto 0); -- DM S2MM Status IF s2mm2sgcntl_sts_tstrb : in std_logic_vector((C_DM_S2MM_STATUS_WIDTH/8)-1 downto 0);-- DM S2MM Status IF -- DataMover S2MM error discrete s2mm2sgcntl_err : in std_logic ; -- DataMover S2MM Halt request input sgcntl2s2mm_halt : Out std_logic ; -- DataMover S2MM Halt complete flag s2mm2sgcntl_halt_cmplt : In std_logic ); end axi_cdma_sg_cntlr; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_cdma_sg_cntlr is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: funct_calc_offset_bits -- -- Function Description: -- Calculates the width of the destination address offset bits -- needed for populating the MM2S Command DSA field. -- ------------------------------------------------------------------- function funct_calc_offset_bits (data_width : integer) return integer is Variable lvar_bits_needed : Integer := 0; begin case data_width is when 32 => lvar_bits_needed := 2; when 64 => lvar_bits_needed := 3; when 128 => lvar_bits_needed := 4; when others => -- 256 bits lvar_bits_needed := 5; end case; Return (lvar_bits_needed); end function funct_calc_offset_bits; attribute mark_debug : string; ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- Constant DM_CMD_PEND_WIDTH : integer := 5; -- bits Constant DM_CMD_PEND_ONE : unsigned(DM_CMD_PEND_WIDTH-1 downto 0) := TO_UNSIGNED(1,DM_CMD_PEND_WIDTH); Constant DM_CMD_PEND_ZERO : unsigned(DM_CMD_PEND_WIDTH-1 downto 0) := TO_UNSIGNED(0,DM_CMD_PEND_WIDTH); Constant NO_SYNCHRONIZERS : integer := 0; Constant POSITIVE_EDGE_TRIGGER : integer := 1; Constant NEGATIVE_EDGE_TRIGGER : integer := 0; Constant TWO_CLKS : integer := 2; Constant ONE_CLK : integer := 1; Constant CMD_TAG_WIDTH : integer := 4; Constant CMD_DSA_WIDTH : integer := 6; Constant DSA_ADDR_OFFSET_WIDTH : integer := funct_calc_offset_bits(C_DM_DATA_WIDTH); Constant CMD_RSVD : std_logic_vector(3 downto 0) := (others => '0'); Constant CMD_DSA_ZEROED : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0'); Constant STS_TAG_MS_INDEX : integer := CMD_TAG_WIDTH-1; Constant STS_INTERR_INDEX : integer := STS_TAG_MS_INDEX+1; Constant STS_DECERR_INDEX : integer := STS_INTERR_INDEX+1; Constant STS_SLVERR_INDEX : integer := STS_DECERR_INDEX+1; Constant STS_OK_INDEX : integer := STS_SLVERR_INDEX+1; Constant DM_ADDR_FIELD_WIDTH : integer := 32; Constant DM_BTT_FIELD_WIDTH : integer := 23; Constant BTT_ZERO : std_logic_vector(DM_BTT_FIELD_WIDTH-1 downto 0) := (others => '0'); Constant TAG_CNT_ONE : unsigned(CMD_TAG_WIDTH-1 downto 0) := TO_UNSIGNED(1,CMD_TAG_WIDTH); Constant DESCR_DBEAT_CNT_WIDTH : integer := 3; -- bits Constant DESCR_DBEAT_CNT_ONE : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(1,DESCR_DBEAT_CNT_WIDTH); -- Descriptor Load databeat positions Constant CDA_LS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(0,DESCR_DBEAT_CNT_WIDTH); Constant CDA_MS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(1,DESCR_DBEAT_CNT_WIDTH); -- Constant SA_LS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(2,DESCR_DBEAT_CNT_WIDTH); Constant SA_LS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(1,DESCR_DBEAT_CNT_WIDTH); Constant SA_MS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(3,DESCR_DBEAT_CNT_WIDTH); -- Constant DA_LS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(4,DESCR_DBEAT_CNT_WIDTH); Constant DA_LS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(2,DESCR_DBEAT_CNT_WIDTH); Constant DA_MS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(5,DESCR_DBEAT_CNT_WIDTH); -- Constant BTT : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(6,DESCR_DBEAT_CNT_WIDTH); Constant BTT : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(3,DESCR_DBEAT_CNT_WIDTH); Constant STATUS : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := TO_UNSIGNED(7,DESCR_DBEAT_CNT_WIDTH); -- Status update word reserved field Constant STATUS_USED_WIDTH : integer := 1 -- Update IOC bit + 1 -- Cmplt bit + 1 -- DMADecErr bit + 1 -- DMASlvErr bit + 1 ; -- DMAIntErr bit Constant STATUS_RSVD_WIDTH : integer := C_SG_STS_UPDATE_DWIDTH - STATUS_USED_WIDTH; Constant STATUS_RSVD : std_logic_vector(STATUS_RSVD_WIDTH-1 downto 0) := (others => '0'); Constant FTCH_UPDT_CNTR_WIDTH : integer := 5; -- 5 bits wide Constant FTCH_UPDT_ZERO : unsigned(FTCH_UPDT_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(0, FTCH_UPDT_CNTR_WIDTH); Constant FTCH_UPDT_ONE : unsigned(FTCH_UPDT_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(1, FTCH_UPDT_CNTR_WIDTH); Constant UPDT_FLTR_WIDTH : integer := 8; -- 8 clocks Constant UPDT_FLTR_CNTR_WIDTH : integer := 4; -- 4 bits wide Constant UPDT_FLTR_CNTR_LD_VALUE : unsigned(UPDT_FLTR_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(UPDT_FLTR_WIDTH, UPDT_FLTR_CNTR_WIDTH); Constant UPDT_FLTR_CNTR_ZERO : unsigned(UPDT_FLTR_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(0, UPDT_FLTR_CNTR_WIDTH); Constant UPDT_FLTR_CNTR_ONE : unsigned(UPDT_FLTR_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(1, UPDT_FLTR_CNTR_WIDTH); Constant FETCH_LIMIT : integer := 4; -- limit of allowed prefetches for DM Cmds Constant FTCH_LIMITER_CNTR_WIDTH : integer := 4; -- 4 bits wide (16 values) Constant FTCH_LIMIT_VALUE : unsigned(UPDT_FLTR_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(FETCH_LIMIT, FTCH_LIMITER_CNTR_WIDTH); Constant FTCH_LIMITER_CNTR_ZERO : unsigned(UPDT_FLTR_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(0, FTCH_LIMITER_CNTR_WIDTH); Constant FTCH_LIMITER_CNTR_ONE : unsigned(UPDT_FLTR_CNTR_WIDTH-1 downto 0) := TO_UNSIGNED(1, FTCH_LIMITER_CNTR_WIDTH); ------------------------------------------------------------------------------- -- Type Declarations ------------------------------------------------------------------------------- -- Define the Fetch State Machine type and states type sg_fetch_sm_type is (FTCH_IDLE , CHK_SG_DM_RDY , LOAD_DESC , XFER_DONE ); -- Define the Status State Machine type and states type sg_status_sm_type is (STS_IDLE , GET_MM2S_STATUS , GET_S2MM_STATUS , DO_UPDATE ); -- Update Stream arbiter type type update_arb_type is (ARB_IDLE , ARB_GRANT_FETCH , ARB_GRANT_STATUS ); -- shutdown sequencer type type shtdwn_type is (SHTDWN_IDLE , HALT_FTCH_DM , WAIT_FTCH_IDLE , WAIT_FTCH_UPDATE , WAIT_DM_HALT_CMPLT , WAIT_STS_IDLE , WAIT_STS_UPDATE , WAIT_SG_UPDATE , SHTDWN_CMPLT ); ------------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------------- -- Fetch State machine signal sig_ftch_sm_state : sg_fetch_sm_type := FTCH_IDLE; signal sig_ftch_sm_state_ns : sg_fetch_sm_type := FTCH_IDLE; signal sig_ftch_sm_set_getdesc : std_logic := '0'; signal sig_ftch_sm_set_getdesc_ns : std_logic := '0'; signal sig_ftch_sm_ld_dm_cmd : std_logic := '0'; signal sig_ftch_sm_ld_dm_cmd_ns : std_logic := '0'; signal sig_ftch_sm_push_updt : std_logic := '0'; signal sig_ftch_sm_push_updt_ns : std_logic := '0'; signal sig_ftch_sm_done : std_logic := '0'; signal sig_ftch_sm_done_ns : std_logic := '0'; -- Status State machine signal sig_sts_sm_state : sg_status_sm_type := STS_IDLE; signal sig_sts_sm_state_ns : sg_status_sm_type := STS_IDLE; signal sig_sts_sm_pop_mm2s_sts : std_logic := '0'; signal sig_sts_sm_pop_mm2s_sts_ns : std_logic := '0'; signal sig_sts_sm_pop_s2mm_sts : std_logic := '0'; signal sig_sts_sm_pop_s2mm_sts_ns : std_logic := '0'; signal sig_sts_sm_push_updt : std_logic := '0'; signal sig_sts_sm_push_updt_ns : std_logic := '0'; -- High level control signal sig_sg_active : std_logic := '1'; signal sig_sg_run : std_logic := '0'; attribute mark_debug of sig_sg_run : signal is "true"; signal sig_idle_clr : std_logic := '0'; signal sig_idle_set : std_logic := '0'; attribute mark_debug of sig_idle_set : signal is "true"; signal sig_dm_cmd_pend_cntr : unsigned(DM_CMD_PEND_WIDTH-1 downto 0) := (others => '0'); signal sig_inc_cmd_pending : std_logic := '0'; signal sig_decr_cmd_pending : std_logic := '0'; signal sig_dm_cmd_pend_eq0 : std_logic := '0'; signal sig_composite_idle : std_logic := '0'; -- Soft shutdown support signal sig_halt_request : std_logic := '0'; signal sig_halt_cmplt_reg : std_logic := '0'; -- DataMover Cmd/Status IF signal sig_cmd_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_cmd_tag_cntr : unsigned(CMD_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mm2s_dsa_offset : std_logic_vector(DSA_ADDR_OFFSET_WIDTH-1 downto 0) := (others => '0'); signal sig_mm2s_dsa_field : std_logic_vector(CMD_DSA_WIDTH-1 downto 0) := (others => '0'); signal sig_btt_dm_slice : std_logic_vector(DM_BTT_FIELD_WIDTH-1 downto 0) := (others => '0'); signal sig_mm2s_s2mm_cmd_rdy : std_logic := '0'; signal sig_mm2s_cmd : std_logic_vector(C_DM_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_mm2s_cmd_valid : std_logic := '0'; attribute mark_debug of sig_mm2s_cmd_valid : signal is "true"; attribute mark_debug of sig_mm2s_cmd : signal is "true"; signal sig_mm2s_cmd_ready : std_logic := '0'; signal sig_mm2s_sts_tready : std_logic ; signal sig_mm2s_sts_tvalid : std_logic ; signal sig_mm2s_sts_tdata : std_logic_vector(C_DM_MM2S_STATUS_WIDTH-1 downto 0); signal sig_s2mm_cmd : std_logic_vector(C_DM_CMD_WIDTH-1 downto 0) := (others => '0'); signal sig_s2mm_cmd_valid : std_logic := '0'; attribute mark_debug of sig_s2mm_cmd_valid : signal is "true"; attribute mark_debug of sig_s2mm_cmd : signal is "true"; signal sig_s2mm_cmd_ready : std_logic := '0'; signal sig_s2mm_sts_tready : std_logic ; signal sig_s2mm_sts_tvalid : std_logic ; signal sig_s2mm_sts_tdata : std_logic_vector(C_DM_MM2S_STATUS_WIDTH-1 downto 0); -- DataMover Status Scoring and Update signal sig_mm2s_status_reg : std_logic_vector(C_DM_MM2S_STATUS_WIDTH-1 downto 0) := (others => '0'); signal sig_s2mm_status_reg : std_logic_vector(C_DM_MM2S_STATUS_WIDTH-1 downto 0) := (others => '0'); signal sig_mm2s_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_mm2s_slverr : std_logic := '0'; signal sig_mm2s_decerr : std_logic := '0'; signal sig_mm2s_interr : std_logic := '0'; attribute mark_debug of sig_mm2s_slverr : signal is "true"; attribute mark_debug of sig_mm2s_decerr : signal is "true"; attribute mark_debug of sig_mm2s_interr : signal is "true"; signal sig_s2mm_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0'); signal sig_s2mm_slverr : std_logic := '0'; signal sig_s2mm_decerr : std_logic := '0'; signal sig_s2mm_interr : std_logic := '0'; attribute mark_debug of sig_s2mm_slverr : signal is "true"; attribute mark_debug of sig_s2mm_decerr : signal is "true"; attribute mark_debug of sig_s2mm_interr : signal is "true"; signal sig_mm2s2cntl_err : std_logic := '0'; signal sig_s2mm2cntl_err : std_logic := '0'; signal sig_composite_interr : std_logic := '0'; signal sig_composite_slverr : std_logic := '0'; signal sig_composite_decerr : std_logic := '0'; signal sig_tag_error : std_logic := '0'; -- SG Update Ready signals signal sig_fetch_updptr_tready : std_logic := '0'; signal sig_status_updsts_tready : std_logic := '0'; -- Descriptor Fetch support signal sig_fetch_dbeat_cnt : unsigned(DESCR_DBEAT_CNT_WIDTH-1 downto 0) := (others => '0'); signal sig_good_fetch_dbeat : std_logic := '0'; signal sig_fetch_go : std_logic := '0'; signal sig_fetch_done : std_logic := '0'; signal sig_fetch_last : std_logic := '0'; -- Descriptor fetch holding registers signal sig_curr_desc_pntr_reg : std_logic_vector(C_SG_FETCH_DWIDTH-1 downto 0) := (others => '0'); signal sig_src_addr_reg : std_logic_vector(C_SG_FETCH_DWIDTH-1 downto 0) := (others => '0'); signal sig_dest_addr_reg : std_logic_vector(C_SG_FETCH_DWIDTH-1 downto 0) := (others => '0'); signal sig_btt_reg : std_logic_vector(C_SG_FETCH_DWIDTH-1 downto 0) := (others => '0'); -- Descriptor fetch SG update support signal sig_ld_fetch_update_reg : std_logic := '0'; signal sig_pop_fetch_update_reg : std_logic := '0'; signal sig_fetch_update_reg : std_logic_vector(C_SG_PTR_UPDATE_DWIDTH-1 downto 0) := (others => '0'); signal sig_fetch_update_full_1 : std_logic := '0'; signal sig_fetch_update_empty_1 : std_logic := '0'; signal sig_fetch_update_full : std_logic := '0'; signal sig_fetch_update_empty : std_logic := '0'; signal sig_fetch_update_last : std_logic := '0'; -- Status SG Update support signal sig_ld_dm_status_reg : std_logic := '0'; signal sig_pop_dm_status_reg : std_logic := '0'; signal sig_dm_status_reg : std_logic_vector(C_SG_STS_UPDATE_DWIDTH-1 downto 0) := (others => '0'); signal sig_dm_status_full : std_logic := '0'; signal sig_dm_status_empty : std_logic := '0'; -- Controlled Shutdown support Signal sig_shtdwn_sm_state : shtdwn_type := SHTDWN_IDLE; Signal sig_shtdwn_sm_state_ns : shtdwn_type := SHTDWN_IDLE; signal sig_shtdwn_sm_flush_sg : std_logic := '0'; signal sig_shtdwn_sm_flush_sg_ns : std_logic := '0'; signal sig_shtdwn_sm_set_ftch_halt : std_logic := '0'; signal sig_shtdwn_sm_set_ftch_halt_ns : std_logic := '0'; signal sig_shtdwn_sm_set_dm_halt : std_logic := '0'; signal sig_shtdwn_sm_set_dm_halt_ns : std_logic := '0'; signal sig_shtdwn_sm_set_sts_halt : std_logic := '0'; signal sig_shtdwn_sm_set_sts_halt_ns : std_logic := '0'; signal sig_shtdwn_sm_set_cmplt : std_logic := '0'; signal sig_shtdwn_sm_set_cmplt_ns : std_logic := '0'; signal sig_do_shutdown : std_logic := '0'; signal sig_sg_error : std_logic := '0'; signal sig_halt_fetch : std_logic := '0'; signal sig_halt_status : std_logic := '0'; signal sig_halt_dm : std_logic := '0'; signal sig_dmhalt_cmplt : std_logic := '0'; signal sig_flush_sg : std_logic := '0'; signal sig_ftchsm_idle : std_logic := '0'; signal sig_stssm_idle : std_logic := '0'; -- SG Idle detection enhancement signal sig_ftch_updt_cntr : unsigned(FTCH_UPDT_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_incr_ftch_updt_cntr : std_logic := '0'; signal sig_decr_ftch_updt_cntr : std_logic := '0'; signal sig_ftch_updt_cntr_eq0 : std_logic := '0'; signal sig_final_updt_idle : std_logic := '0'; signal sig_update_idle_rising : std_logic := '0'; signal sig_shutdown_idle : std_logic := '0'; signal sig_shutdown_idle_rising : std_logic := '0'; signal sig_updt_filter_cntr : unsigned(UPDT_FLTR_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_updt_filter_cntr_eq0 : std_logic := '0'; signal sig_ld_updt_filter_cntr : std_logic := '0'; -- SG Fetch Limiter (lock up avoidance) signal sig_ftch_limit_cntr : unsigned(FTCH_LIMITER_CNTR_WIDTH-1 downto 0) := (others => '0'); signal sig_incr_ftch_limit_cntr : std_logic := '0'; signal sig_decr_ftch_limit_cntr : std_logic := '0'; signal sig_ftch_limit_cntr_eq0 : std_logic := '0'; signal sig_ftch_limit_cntr_eqlimit : std_logic := '0'; signal type_of_burst_write : std_logic; signal type_of_burst : std_logic; signal ZERO_WORD : std_logic_vector (31 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin ------------------------------------------------------------------------------- -- SG Run/Stop ------------------------------------------------------------------------------- sgcntlr2sg_run_stop <= sig_sg_run ; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SG_RUN_FLOP -- -- Process Description: -- Implements the flop for the SG Run control. The Run/Stop -- control is set when SG Mode is enabled and the Current -- Descriptor Register is updated by SW (in the Reg Module). -- ------------------------------------------------------------- IMP_SG_RUN_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or reg2sgcntl_sg_mode = '0') then sig_sg_run <= '0'; elsif (reg2sgcntl_currdesc_updated = '1') then sig_sg_run <= '1'; else null; -- Hold Current State end if; end if; end process IMP_SG_RUN_FLOP; ------------------------------------------------------------------------------- -- SG Xfer "Really" Done Detection ------------------------------------------------------------------------------- sig_idle_set <= (not(sig_do_shutdown) and -- not in a shutdown sequence sig_update_idle_rising and -- update engine done sig_ftch_updt_cntr_eq0 and -- the last update queued sig_updt_filter_cntr_eq0 and sg2sgcntlr_ftch_idle) or -- not in update filter period sig_shutdown_idle_rising; -- in shutdown and complete sig_incr_ftch_updt_cntr <= sig_ftch_sm_set_getdesc ; sig_decr_ftch_updt_cntr <= sig_pop_dm_status_reg ; sig_ftch_updt_cntr_eq0 <= '1' when sig_ftch_updt_cntr = FTCH_UPDT_ZERO Else '0'; sig_final_updt_idle <= sig_ftch_updt_cntr_eq0 and -- all fetches have corresponding updates sg2sgcntlr_updt_idle ; -- and the SG Update engine is idle ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FTCH_UPDT_CNTR -- -- Process Description: -- Implements a counter to keep track of the number of -- descriptor fetches and updates. This is used to detirmine -- when SG operation are really completed. -- ------------------------------------------------------------- IMP_FTCH_UPDT_CNTR : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_ftch_updt_cntr <= FTCH_UPDT_ZERO; elsif (sig_incr_ftch_updt_cntr = '1' and sig_decr_ftch_updt_cntr = '0') then sig_ftch_updt_cntr <= sig_ftch_updt_cntr + FTCH_UPDT_ONE; Elsif (sig_ftch_updt_cntr_eq0 = '0' and sig_decr_ftch_updt_cntr = '1' and sig_incr_ftch_updt_cntr = '0') Then sig_ftch_updt_cntr <= sig_ftch_updt_cntr - FTCH_UPDT_ONE; else null; -- Hold Current State end if; end if; end process IMP_FTCH_UPDT_CNTR; ------------------------------------------------------------ -- Instance: I_GEN_SG_IDLE_RISE -- -- Description: -- Generates a pulse signaling the last SG update -- operation has completed. -- ------------------------------------------------------------ I_GEN_SG_IDLE_RISE : entity axi_cdma_v4_1.axi_cdma_pulse_gen generic map ( C_INCLUDE_SYNCHRO => NO_SYNCHRONIZERS , C_POS_EDGE_TRIG => POSITIVE_EDGE_TRIGGER , C_PULSE_WIDTH_CLKS => ONE_CLK ) port map ( Clk_In => axi_aclk , Rst_In => axi_reset , Sig_in => sg2sgcntlr_updt_idle , Pulse_Out => sig_update_idle_rising ); ------------------------------------------------------------------------------- -- Update Filter Counter -- -- Used to filter the lag between the acceptance of an update by the SG -- and the Update Idle flag being reset by the SG (going to not idle). -- ------------------------------------------------------------------------------- -- Start the filter counter when a status update is accepted -- by the SG Update interface sig_ld_updt_filter_cntr <= sig_pop_dm_status_reg; sig_updt_filter_cntr_eq0 <= '1' when (sig_updt_filter_cntr = UPDT_FLTR_CNTR_ZERO) else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_UPDT_FILTER_CNTR -- -- Process Description: -- Implements a counter to filter the time lag between an update -- being accepted by the SG and the Update Idle Flag being reset -- by the SG. -- ------------------------------------------------------------- IMP_UPDT_FILTER_CNTR : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_updt_filter_cntr <= UPDT_FLTR_CNTR_ZERO; Elsif (sig_ld_updt_filter_cntr = '1') Then sig_updt_filter_cntr <= UPDT_FLTR_CNTR_LD_VALUE; Elsif (sig_updt_filter_cntr_eq0 = '0') Then sig_updt_filter_cntr <= sig_updt_filter_cntr - UPDT_FLTR_CNTR_ONE; else null; -- Hold Current State end if; end if; end process IMP_UPDT_FILTER_CNTR; ------------------------------------------------------------------------------- -- Idle Set and Clear logic ------------------------------------------------------------------------------- -- The SG operation starts when the Tail Pointer is written by SW in the -- Register Module sgcntl2reg_idle_set <= sig_idle_set ; sgcntl2reg_idle_clr <= sig_idle_clr ; ------------------------------------------------------------ -- Instance: I_GEN_IDLE_CLR -- -- Description: -- Generates the Idle Clear pulse of 1 clock width. -- ------------------------------------------------------------ I_GEN_IDLE_CLR : entity axi_cdma_v4_1.axi_cdma_pulse_gen generic map ( C_INCLUDE_SYNCHRO => NO_SYNCHRONIZERS , C_POS_EDGE_TRIG => POSITIVE_EDGE_TRIGGER , C_PULSE_WIDTH_CLKS => ONE_CLK ) port map ( Clk_In => axi_aclk , Rst_In => axi_reset , Sig_in => reg2sgcntl_tailpntr_updated, Pulse_Out => sig_idle_clr ); sig_shutdown_idle <= (sig_do_shutdown and -- In a shutdown sequence and sig_halt_cmplt_reg ); -- shutdown complete ------------------------------------------------------------ -- Instance: I_GEN_IDLE_SET -- -- Description: -- Generates the Idle Set pulse of 1 clock width. -- ------------------------------------------------------------ I_GEN_IDLE_SET : entity axi_cdma_v4_1.axi_cdma_pulse_gen generic map ( C_INCLUDE_SYNCHRO => NO_SYNCHRONIZERS , C_POS_EDGE_TRIG => POSITIVE_EDGE_TRIGGER , C_PULSE_WIDTH_CLKS => ONE_CLK ) port map ( Clk_In => axi_aclk , Rst_In => axi_reset , Sig_in => sig_shutdown_idle , Pulse_Out => sig_shutdown_idle_rising ); -- Controls for the DataMover Command pending counter sig_inc_cmd_pending <= sig_ftch_sm_ld_dm_cmd; sig_decr_cmd_pending <= sig_sts_sm_push_updt ; sig_dm_cmd_pend_eq0 <= '1' when (sig_dm_cmd_pend_cntr = DM_CMD_PEND_ZERO) Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_DM_CMD_PEND_CNTR -- -- Process Description: -- -- ------------------------------------------------------------- IMP_DM_CMD_PEND_CNTR : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_dm_cmd_pend_cntr <= DM_CMD_PEND_ZERO; elsif (sig_inc_cmd_pending = '1' and sig_decr_cmd_pending = '0') then sig_dm_cmd_pend_cntr <= sig_dm_cmd_pend_cntr + DM_CMD_PEND_ONE; elsif (sig_inc_cmd_pending = '0' and sig_decr_cmd_pending = '1' and sig_dm_cmd_pend_eq0 = '0') then sig_dm_cmd_pend_cntr <= sig_dm_cmd_pend_cntr - DM_CMD_PEND_ONE; else null; -- Hold Current State end if; end if; end process IMP_DM_CMD_PEND_CNTR; ------------------------------------------------------------------------------- -- SOF/EOF control logic ------------------------------------------------------------------------------- -- Since CDMA does not need to support SOF/EOF concept (no Stream IF) then -- every descriptor processed is by definition a EOF/SOF case (from the -- viewpoint of the DataMover and the SG engine). sgcntl2sg_pkt_sof <= sig_idle_clr or -- Used to stop Delay Timer when a descr is ready or sig_shtdwn_sm_set_cmplt ; -- Stop delay timer on shutdown completion sgcntl2sg_pkt_eof <= sig_idle_set ; -- Used to start Delay timer ------------------------------------------------------------------------------- -- IOC and Delay Interrupt set control logic ------------------------------------------------------------------------------- -- Just pass these through the SG Controller for now. These were -- brought through the SG Controller just in case the need arose -- for some protection from the register module during simple DMA -- mode. sgcntl2reg_ioc_irq_set <= sg2sgcntl_ioc_irq_set; sgcntl2reg_dly_irq_set <= sg2sgcntl_dly_irq_set; ------------------------------------------------------------------------------- -- Current Descriptor Update to Register module control logic ------------------------------------------------------------------------------- -- Update the Register module with the latest Descriptor's Current -- DEscriptor Address when the SG Fetch Update occurs. sgcntlr2reg_new_curdesc_wren <= sig_ftch_sm_push_updt ; sgcntlr2reg_new_curdesc <= sig_curr_desc_pntr_reg ; ------------------------------------------------------------------------------- -- SG DMA Error set control logic ------------------------------------------------------------------------------- -- Just pass these through the SG Controller for now. These were -- brought through the SG Controller just in case the need arose -- for some protection from the register module during simple DMA -- mode. sgcntlr2reg_dma_interr_set <= sg2sgcntlr_dma_interr_set ; sgcntlr2reg_dma_slverr_set <= sg2sgcntlr_dma_slverr_set ; sgcntlr2reg_dma_decerr_set <= sg2sgcntlr_dma_decerr_set ; ------------------------------------------------------------------------------- -- Misc logic ------------------------------------------------------------------------------- -- See if DataMover is ready for next command sig_mm2s_s2mm_cmd_rdy <= sig_mm2s_cmd_ready and sig_s2mm_cmd_ready; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SG_ACTIVE_FLAG -- -- Process Description: -- Internal flag for enable and disable of state machines. -- ------------------------------------------------------------- IMP_SG_ACTIVE_FLAG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_idle_set = '1') then -- sig_sg_active <= '0'; elsif (sig_idle_clr = '1') then -- sig_sg_active <= '1'; else null; -- Hold Current State end if; end if; end process IMP_SG_ACTIVE_FLAG; ------------------------------------------------------------------------------- -- FETCH Prefetch Limiter Logic ------------------------------------------------------------------------------- sig_incr_ftch_limit_cntr <= sig_ftch_sm_set_getdesc ; sig_decr_ftch_limit_cntr <= sig_pop_dm_status_reg ; sig_ftch_limit_cntr_eq0 <= '1' when sig_ftch_limit_cntr = FTCH_LIMITER_CNTR_ZERO Else '0'; sig_ftch_limit_cntr_eqlimit <= '1' when sig_ftch_limit_cntr = FTCH_LIMIT_VALUE Else '0'; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FTCH_LIMIT_CNTR -- -- Process Description: -- Implements a counter to keep track of the number of -- descriptor fetches and updates. This is used to limit the -- difference to a fixed value to keep the SG Update Queue from -- going full. The SG Update Queue full can lead to SG lockup. -- ------------------------------------------------------------- IMP_FTCH_LIMIT_CNTR : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_ftch_limit_cntr <= FTCH_LIMITER_CNTR_ZERO; elsif (sig_incr_ftch_limit_cntr = '1' and sig_decr_ftch_limit_cntr = '0') then sig_ftch_limit_cntr <= sig_ftch_limit_cntr + FTCH_LIMITER_CNTR_ONE; Elsif (sig_ftch_limit_cntr_eq0 = '0' and sig_decr_ftch_limit_cntr = '1' and sig_incr_ftch_limit_cntr = '0') Then sig_ftch_limit_cntr <= sig_ftch_limit_cntr - FTCH_LIMITER_CNTR_ONE; else null; -- Hold Current State end if; end if; end process IMP_FTCH_LIMIT_CNTR; ------------------------------------------------------------------------------- -- Descriptor Fetch Logic ------------------------------------------------------------------------------- sgcntl2sg_ftch_tready <= sig_fetch_go or sig_halt_fetch ; -- force tready high on a shutdown -- sig_fetch_last <= sg2sgcntlr_ftch_tlast; sig_fetch_last <= '1'; --sg2sgcntlr_ftch_tlast; -- sig_good_fetch_dbeat <= sig_fetch_go and sig_good_fetch_dbeat <= sg2sgcntlr_ftch_tvalid_new; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FETCH_GO_FLOP -- -- Process Description: -- Implements the fetch go and done flags -- ------------------------------------------------------------- IMP_FETCH_GO_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_ftch_sm_done = '1') then -- sig_fetch_go <= '0'; -- sig_fetch_done <= '0'; elsif (sig_ftch_sm_set_getdesc_ns = '1') then -- sig_fetch_go <= '1'; -- sig_fetch_done <= '0'; Elsif (sig_good_fetch_dbeat = '1' and sig_fetch_last = '1') Then -- sig_fetch_go <= '0'; -- sig_fetch_done <= '1'; else null; -- hold current state end if; end if; end process IMP_FETCH_GO_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FETCH_DB_CNTR -- -- Process Description: -- Implements the descriptor fetch data beat counter -- ------------------------------------------------------------- IMP_FETCH_DB_CNTR : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_ftch_sm_set_getdesc_ns = '1') then sig_fetch_dbeat_cnt <= (others => '0'); elsif (sig_good_fetch_dbeat = '1' and sig_fetch_done = '0' and sig_fetch_last = '0') then sig_fetch_dbeat_cnt <= sig_fetch_dbeat_cnt + DESCR_DBEAT_CNT_ONE ; else null; -- Hold Current State end if; end if; end process IMP_FETCH_DB_CNTR; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CURR_DESC_PNTR_REG -- -- Process Description: -- Implements the Next descriptor pointer reg. It is -- cleared when the fetch process is complete. -- ------------------------------------------------------------- -- IMP_CURR_DESC_PNTR_REG : process (axi_aclk) -- begin -- if (axi_aclk'event and axi_aclk = '1') then -- if (axi_reset = '1' or -- sig_ftch_sm_done = '1') then -- sig_curr_desc_pntr_reg <= (others => '0'); -- elsif (sig_good_fetch_dbeat = '1' and -- sig_fetch_dbeat_cnt = CDA_LS) then sig_curr_desc_pntr_reg <= sg2sgcntlr_ftch_tdata_new (127 downto 96); -- else -- null; -- Hold Current State -- end if; -- end if; -- end process IMP_CURR_DESC_PNTR_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SRC_ADDR_REG -- -- Process Description: -- Implements the Source Address register. It is -- cleared when the fetch process is complete. -- ------------------------------------------------------------- -- IMP_SRC_ADDR_REG : process (axi_aclk) -- begin -- if (axi_aclk'event and axi_aclk = '1') then -- if (axi_reset = '1' or -- sig_ftch_sm_done = '1') then -- sig_src_addr_reg <= (others => '0'); -- elsif (sig_good_fetch_dbeat = '1' and -- sig_fetch_dbeat_cnt = SA_LS) then sig_src_addr_reg <= sg2sgcntlr_ftch_tdata_new (31 downto 0); -- else -- null; -- Hold Current State -- end if; -- end if; -- end process IMP_SRC_ADDR_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_DEST_ADDR_REG -- -- Process Description: -- Implements the Destination Address register. It is -- cleared when the fetch process is complete. -- ------------------------------------------------------------- -- IMP_DEST_ADDR_REG : process (axi_aclk) -- begin -- if (axi_aclk'event and axi_aclk = '1') then -- if (axi_reset = '1' or -- sig_ftch_sm_done = '1') then -- sig_dest_addr_reg <= (others => '0'); -- elsif (sig_good_fetch_dbeat = '1' and -- sig_fetch_dbeat_cnt = DA_LS) then sig_dest_addr_reg <= sg2sgcntlr_ftch_tdata_new (63 downto 32); -- else -- null; -- Hold Current State -- end if; -- end if; -- end process IMP_DEST_ADDR_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_BTT_REG -- -- Process Description: -- Implements the BTT register. It is -- cleared when the fetch process is complete. -- ------------------------------------------------------------- -- IMP_BTT_REG : process (axi_aclk) -- begin -- if (axi_aclk'event and axi_aclk = '1') then -- if (axi_reset = '1' or -- sig_ftch_sm_done = '1') then -- sig_btt_reg <= (others => '0'); -- elsif (sig_good_fetch_dbeat = '1' and -- sig_fetch_dbeat_cnt = BTT) then sig_btt_reg <= sg2sgcntlr_ftch_tdata_new (95 downto 64); -- else -- null; -- Hold Current State -- end if; -- end if; -- end process IMP_BTT_REG; ------------------------------------------------------------------------------- -- Rip the needed BTT bits for the DataMover from the descriptor BTT register ------------------------------------------------------------------------------- sig_btt_dm_slice <= sig_btt_reg(DM_BTT_FIELD_WIDTH-1 downto 0); ------------------------------------------------------------------------------- -- Command TAG Generator (just an incrementing counter) -- The Command tag is used for test and debug to track command execution flow -- through the DataMover. ------------------------------------------------------------------------------- sig_cmd_tag <= STD_LOGIC_VECTOR(sig_cmd_tag_cntr); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: DM_TAG_CNTR -- -- Process Description: -- Command tag generator. This is just a simple counter -- that increments every time a command is loaded into the -- DataMover. Counter rollover is ok. -- ------------------------------------------------------------- DM_TAG_CNTR : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or reg2sgcntl_sg_mode = '0') then sig_cmd_tag_cntr <= (others => '0'); elsif (sig_ftch_sm_ld_dm_cmd = '1') then sig_cmd_tag_cntr <= sig_cmd_tag_cntr + TAG_CNT_ONE; else null; -- hold current state end if; end if; end process DM_TAG_CNTR; ------------------------------------------------------------------------------- -- MM2S Command Generation ------------------------------------------------------------------------------- sgcntl2mm2s_cmd_tdata <= sig_mm2s_cmd ; sgcntl2mm2s_cmd_tvalid <= sig_mm2s_cmd_valid ; sig_mm2s_cmd_ready <= mm2s2sgcntl_cmd_tready ; sig_mm2s_cmd_valid <= sig_ftch_sm_ld_dm_cmd ; type_of_burst <= '1' and (not burst_type_read); -- Formulate the MM2S Command sig_mm2s_cmd <= CMD_RSVD & -- reserved sig_cmd_tag & -- Tag sig_src_addr_reg & -- Address '1' & -- DRR bit '1' & -- EOF bit sig_mm2s_dsa_field & -- DSA Field Assignment type_of_burst & -- '1' & -- Incrementing burst type sig_btt_dm_slice ; -- BTT -- Rip the Destnation address offset bits sig_mm2s_dsa_offset <= sig_dest_addr_reg(DSA_ADDR_OFFSET_WIDTH-1 downto 0); -- Size the dest addr offset to the DSA field width sig_mm2s_dsa_field <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(sig_mm2s_dsa_offset), CMD_DSA_WIDTH)); ------------------------------------------------------------------------------- -- MM2S Status Reg and logic ------------------------------------------------------------------------------- sgcntl2mm2s_sts_tready <= sig_sts_sm_pop_mm2s_sts or sig_halt_dm ; -- allow status to flush on shutdown sig_mm2s_sts_tvalid <= mm2s2sgcntl_sts_tvalid ; sig_mm2s_sts_tdata <= mm2s2sgcntl_sts_tdata ; -- DataMover MM2S Error discrete sig_mm2s2cntl_err <= mm2s2sgcntl_err ; -- Rip the status bits from the status register sig_mm2s_tag <= sig_mm2s_status_reg(STS_TAG_MS_INDEX downto 0); sig_mm2s_interr <= sig_mm2s_status_reg(STS_INTERR_INDEX); sig_mm2s_decerr <= sig_mm2s_status_reg(STS_DECERR_INDEX); sig_mm2s_slverr <= sig_mm2s_status_reg(STS_SLVERR_INDEX); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_MM2S_STATUS_REG -- -- Process Description: -- Implements the MM2S status reply holding register. -- ------------------------------------------------------------- IMP_MM2S_STATUS_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_sts_sm_push_updt = '1') then sig_mm2s_status_reg <= (others => '0'); elsif (sig_sts_sm_pop_mm2s_sts = '1') then sig_mm2s_status_reg <= sig_mm2s_sts_tdata; else null; -- hold current state end if; end if; end process IMP_MM2S_STATUS_REG; ------------------------------------------------------------------------------- -- S2MM Command Generation ------------------------------------------------------------------------------- sgcntl2s2mm_cmd_tdata <= sig_s2mm_cmd ; sgcntl2s2mm_cmd_tvalid <= sig_s2mm_cmd_valid ; sig_s2mm_cmd_ready <= s2mm2sgcntl_cmd_tready ; sig_s2mm_cmd_valid <= sig_ftch_sm_ld_dm_cmd ; type_of_burst_write <= '1' and (not burst_type_write); -- Formulate the S2MM Command sig_s2mm_cmd <= CMD_RSVD & -- reserved sig_cmd_tag & -- Tag sig_dest_addr_reg & -- Address '1' & -- DRR bit '1' & -- EOF bit CMD_DSA_ZEROED & -- DSA Field Assignment type_of_burst_write & -- '1' & -- Incrementing burst type sig_btt_dm_slice ; -- BTT ------------------------------------------------------------------------------- -- S2MM Status Reg and logic ------------------------------------------------------------------------------- sgcntl2s2mm_sts_tready <= sig_sts_sm_pop_s2mm_sts or sig_halt_dm ; -- allow status to flush on shutdown; sig_s2mm_sts_tvalid <= s2mm2sgcntl_sts_tvalid ; sig_s2mm_sts_tdata <= s2mm2sgcntl_sts_tdata ; -- DataMover S2MM Error discrete sig_s2mm2cntl_err <= s2mm2sgcntl_err ; -- Rip the status bits from the status register sig_s2mm_tag <= sig_s2mm_status_reg(STS_TAG_MS_INDEX downto 0); sig_s2mm_interr <= sig_s2mm_status_reg(STS_INTERR_INDEX); sig_s2mm_decerr <= sig_s2mm_status_reg(STS_DECERR_INDEX); sig_s2mm_slverr <= sig_s2mm_status_reg(STS_SLVERR_INDEX); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_S2MM_STATUS_REG -- -- Process Description: -- Implements the MM2S status reply holding register. -- ------------------------------------------------------------- IMP_S2MM_STATUS_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_sts_sm_push_updt = '1') then sig_s2mm_status_reg <= (others => '0'); elsif (sig_sts_sm_pop_s2mm_sts = '1') then sig_s2mm_status_reg <= sig_s2mm_sts_tdata; else null; -- hold current state end if; end if; end process IMP_S2MM_STATUS_REG; ------------------------------------------------------------------------------- -- Fetch Update words formulation ------------------------------------------------------------------------------- -- Assign the Fetch update outputs to the SG Fetch Update port sgcntl2sg_updptr_tvalid <= sig_fetch_update_full ; sgcntl2sg_updptr_tdata <= sig_fetch_update_reg ; sgcntl2sg_updptr_tlast <= sig_fetch_update_last ; sig_fetch_updptr_tready <= sg2sgcntlr_updptr_tready ; sig_fetch_update_last <= sig_fetch_update_full;-- and -- not(sig_fetch_update_full_1); sig_ld_fetch_update_reg <= sig_ftch_sm_push_updt and sig_fetch_update_empty ; sig_pop_fetch_update_reg <= sig_fetch_update_full and sig_fetch_updptr_tready ; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FETCH_UPDATE_FLAGS -- -- Process Description: -- Implements the Fetch Update Register status flags. -- Note that this simulates a 2-deep register requiring -- 2 pops to become empty (not full). -- ------------------------------------------------------------- IMP_FETCH_UPDATE_FLAGS : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_pop_fetch_update_reg = '1' or sig_halt_fetch = '1') then -- sig_fetch_update_full_1 <= '0'; sig_fetch_update_full <= '0'; -- sig_fetch_update_empty_1 <= '1'; sig_fetch_update_empty <= '1'; elsif (sig_ld_fetch_update_reg = '1') then -- sig_fetch_update_full_1 <= '1'; sig_fetch_update_full <= '1'; -- sig_fetch_update_empty_1 <= '0'; sig_fetch_update_empty <= '0'; -- elsif (sig_pop_fetch_update_reg = '1') then -- sig_fetch_update_full_1 <= '0'; -- sig_fetch_update_full <= sig_fetch_update_full_1; -- sig_fetch_update_empty_1 <= '1'; -- sig_fetch_update_empty <= sig_fetch_update_empty_1; else null; -- Hold Current State end if; end if; end process IMP_FETCH_UPDATE_FLAGS; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FETCH_UPDATE_REG -- -- Process Description: -- Implements the fetch update register for the current -- descriptor address write to the SG Update port. -- ------------------------------------------------------------- IMP_FETCH_UPDATE_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_pop_fetch_update_reg = '1') then sig_fetch_update_reg <= (others => '0'); elsif (sig_ld_fetch_update_reg = '1') then sig_fetch_update_reg <= sig_curr_desc_pntr_reg; -- Curr Descr Pointer LS else null; -- Hold Current State end if; end if; end process IMP_FETCH_UPDATE_REG; ------------------------------------------------------------------------------- -- Status DM Error merging ------------------------------------------------------------------------------- -- If the MM2S Status tag does not match the S2MM Status tag, -- this is a nasty internal error where a status reply has been -- dropped by the DataMover. This is a unique condition for the -- CDMA application. sig_tag_error <= '0' When (sig_halt_dm = '1') else '1' when (sig_s2mm_tag /= sig_mm2s_tag) Else '0'; sig_composite_interr <= (sig_s2mm_interr or sig_mm2s_interr or sig_tag_error) and not(sig_halt_dm) ; sig_composite_slverr <= (sig_s2mm_slverr or sig_mm2s_slverr) and not(sig_halt_dm) ; sig_composite_decerr <= (sig_s2mm_decerr or sig_mm2s_decerr) and not(sig_halt_dm) ; ------------------------------------------------------------------------------- -- Status Update Register Logic ------------------------------------------------------------------------------- -- Assign Output Stream port to SG Status Update interface sgcntl2sg_updsts_tvalid <= sig_dm_status_full; sgcntl2sg_updsts_tdata <= sig_dm_status_reg ; sgcntl2sg_updsts_tlast <= '1' ; sig_status_updsts_tready <= sg2sgcntlr_updsts_tready ; sig_ld_dm_status_reg <= sig_sts_sm_push_updt and sig_dm_status_empty; sig_pop_dm_status_reg <= sig_dm_status_full and sig_status_updsts_tready ; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_DM_STATUS_REG -- -- Process Description: -- Implements the composite transfer status register for the -- descriptor. -- ------------------------------------------------------------- IMP_DM_STATUS_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1' or sig_pop_dm_status_reg = '1' or sig_halt_status = '1') then sig_dm_status_reg <= (others => '0'); sig_dm_status_full <= '0'; sig_dm_status_empty <= '1'; elsif (sig_ld_dm_status_reg = '1') then sig_dm_status_reg <= '1' & -- SG Update IOC bit '1' & -- Descriptor Cmplt bit sig_composite_decerr & -- DM Decode Error sig_composite_slverr & -- DM Slave Error sig_composite_interr & -- DM Internal Error STATUS_RSVD ; -- Unused (zeros) sig_dm_status_full <= '1'; sig_dm_status_empty <= '0'; else null; -- Hold Current State end if; end if; end process IMP_DM_STATUS_REG; ------------------------------------------------------------------------------- -- Descriptor Fetch State Machine ------------------------------------------------------------------------------- ------------------------------------------------------------- -- Combinational Process -- -- Label: IMP_FETCH_SM_COMB -- -- Process Description: -- Implements the combinatorial portion of the Descriptor -- Fetch from SG state machine. -- ------------------------------------------------------------- IMP_FETCH_SM_COMB : process (sig_ftch_sm_state , sig_halt_fetch , sig_sg_active , sig_sg2sgcntlr_ftch_desc_available , sig_mm2s_s2mm_cmd_rdy , sig_fetch_update_empty , -- sig_fetch_done , sig_ftch_limit_cntr_eqlimit ) begin -- assign the default values sig_ftch_sm_state_ns <= FTCH_IDLE ; sig_ftch_sm_set_getdesc_ns <= '0' ; sig_ftch_sm_ld_dm_cmd_ns <= '0' ; sig_ftch_sm_push_updt_ns <= '0' ; sig_ftch_sm_done_ns <= '0' ; case sig_ftch_sm_state is --------------------------------- when FTCH_IDLE => If (sig_sg_active = '1' and sig_halt_fetch = '0') Then -- Start operations sig_ftch_sm_state_ns <= CHK_SG_DM_RDY ; Else -- wait here sig_ftch_sm_state_ns <= FTCH_IDLE ; End if; --------------------------------- when CHK_SG_DM_RDY => if (sig_halt_fetch = '1') then sig_ftch_sm_state_ns <= XFER_DONE ; elsif (sig_ftch_limit_cntr_eqlimit = '0' and sig_sg2sgcntlr_ftch_desc_available = '1' and sig_mm2s_s2mm_cmd_rdy = '1' and sig_fetch_update_empty = '1') then sig_ftch_sm_state_ns <= LOAD_DESC ; sig_ftch_sm_set_getdesc_ns <= '1' ; sig_ftch_sm_ld_dm_cmd_ns <= '1' ; sig_ftch_sm_push_updt_ns <= '1' ; else sig_ftch_sm_state_ns <= CHK_SG_DM_RDY ; end if; --------------------------------- when LOAD_DESC => sig_ftch_sm_set_getdesc_ns <= '0' ; if (sig_halt_fetch = '1') then sig_ftch_sm_state_ns <= XFER_DONE ; else --if (sig_fetch_done = '1') then sig_ftch_sm_state_ns <= XFER_DONE ; -- sig_ftch_sm_ld_dm_cmd_ns <= '1' ; -- sig_ftch_sm_push_updt_ns <= '1' ; -- else -- sig_ftch_sm_state_ns <= LOAD_DESC ; end if; --------------------------------- when XFER_DONE => sig_ftch_sm_state_ns <= FTCH_IDLE ; sig_ftch_sm_done_ns <= '1' ; --------------------------------- when others => sig_ftch_sm_state_ns <= FTCH_IDLE ; end case; end process IMP_FETCH_SM_COMB; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FETCH_SM_REG -- -- Process Description: -- Implements the registered portion of the descriptor Fetch -- State Machine. -- ------------------------------------------------------------- IMP_FETCH_SM_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_ftch_sm_state <= FTCH_IDLE ; sig_ftch_sm_set_getdesc <= '0' ; sig_ftch_sm_ld_dm_cmd <= '0' ; sig_ftch_sm_push_updt <= '0' ; sig_ftch_sm_done <= '0' ; -- sig_fetch_go <= '0' ; sig_fetch_done <= '0' ; else sig_ftch_sm_state <= sig_ftch_sm_state_ns ; sig_ftch_sm_set_getdesc <= sig_ftch_sm_set_getdesc_ns ; -- sig_fetch_go <= sig_ftch_sm_set_getdesc_ns ; sig_fetch_done <= sig_fetch_go; sig_ftch_sm_ld_dm_cmd <= sig_ftch_sm_ld_dm_cmd_ns ; sig_ftch_sm_push_updt <= sig_ftch_sm_push_updt_ns ; sig_ftch_sm_done <= sig_ftch_sm_done_ns ; end if; end if; end process IMP_FETCH_SM_REG; sig_fetch_go <= sig_ftch_sm_set_getdesc_ns ; ------------------------------------------------------------------------------- -- Status Update State Machine ------------------------------------------------------------------------------- ------------------------------------------------------------- -- Combinational Process -- -- Label: IMP_STATUS_SM_COMB -- -- Process Description: -- Implements the combinatorial portion of the Status Update -- State Machine. -- ------------------------------------------------------------- IMP_STATUS_SM_COMB : process (sig_sts_sm_state , sig_halt_status , sig_sg_active , sig_dm_cmd_pend_eq0 , sig_mm2s_sts_tvalid , sig_s2mm_sts_tvalid , sig_dm_status_empty ) begin -- assign the default values sig_sts_sm_state_ns <= STS_IDLE ; sig_sts_sm_pop_mm2s_sts_ns <= '0' ; sig_sts_sm_pop_s2mm_sts_ns <= '0' ; sig_sts_sm_push_updt_ns <= '0' ; case sig_sts_sm_state is --------------------------------- when STS_IDLE => If (sig_sg_active = '1' and sig_halt_status = '0') Then -- Start operations sig_sts_sm_state_ns <= GET_MM2S_STATUS ; Else -- wait here sig_sts_sm_state_ns <= STS_IDLE ; End if; --------------------------------- when GET_MM2S_STATUS => if (sig_halt_status = '1') then sig_sts_sm_state_ns <= STS_IDLE ; elsif (sig_mm2s_sts_tvalid = '1') then sig_sts_sm_state_ns <= GET_S2MM_STATUS ; sig_sts_sm_pop_mm2s_sts_ns <= '1' ; else sig_sts_sm_state_ns <= GET_MM2S_STATUS ; end if; --------------------------------- when GET_S2MM_STATUS => if (sig_halt_status = '1') then sig_sts_sm_state_ns <= STS_IDLE ; elsif (sig_s2mm_sts_tvalid = '1') then sig_sts_sm_state_ns <= DO_UPDATE ; sig_sts_sm_pop_s2mm_sts_ns <= '1' ; else sig_sts_sm_state_ns <= GET_S2MM_STATUS ; end if; --------------------------------- when DO_UPDATE => If (sig_dm_status_empty = '1') Then sig_sts_sm_state_ns <= STS_IDLE ; sig_sts_sm_push_updt_ns <= '1' ; Else sig_sts_sm_state_ns <= DO_UPDATE ; End if; --------------------------------- when others => -- shouldn't ever get here sig_sts_sm_state_ns <= STS_IDLE ; end case; end process IMP_STATUS_SM_COMB; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_STATUS_SM_REG -- -- Process Description: -- Implements the registered portion of the Status Update -- State Machine. -- ------------------------------------------------------------- IMP_STATUS_SM_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_sts_sm_state <= STS_IDLE ; sig_sts_sm_pop_mm2s_sts <= '0' ; sig_sts_sm_pop_s2mm_sts <= '0' ; sig_sts_sm_push_updt <= '0' ; else sig_sts_sm_state <= sig_sts_sm_state_ns ; sig_sts_sm_pop_mm2s_sts <= sig_sts_sm_pop_mm2s_sts_ns ; sig_sts_sm_pop_s2mm_sts <= sig_sts_sm_pop_s2mm_sts_ns ; sig_sts_sm_push_updt <= sig_sts_sm_push_updt_ns ; end if; end if; end process IMP_STATUS_SM_REG; ------------------------------------------------------------------------------- -- controlled Shutdown State Machine and related logic ------------------------------------------------------------------------------- -- Reset Module HALT request and complete reply sig_halt_request <= rst2sgcntl_halt ; sgcntl2rst_halt_cmplt <= sig_halt_cmplt_reg; -- SG Descriptor Queue flush request sgcntlr2sg_desc_flush <= sig_flush_sg ; -- DataMover Halt requests sgcntl2mm2s_halt <= sig_halt_dm ; sgcntl2s2mm_halt <= sig_halt_dm ; -- Composite DataMover halt complete flag sig_dmhalt_cmplt <= mm2s2sgcntl_halt_cmplt and s2mm2sgcntl_halt_cmplt ; -- Fetch State Machine Idle flag sig_ftchsm_idle <= '1' when (sig_ftch_sm_state = FTCH_IDLE) Else '0'; -- Status State Machine Idle flag sig_stssm_idle <= '1' when (sig_sts_sm_state = STS_IDLE) Else '0'; -- Composite error flag indicating that an error occured -- during a descriptor fetch or update operation sig_sg_error <= sg2sgcntlr_ftch_error or sg2sgcntlr_updt_error ; -- Formulate the shutdown request decision logic sig_do_shutdown <= sig_halt_request or sig_sg_error or sg2sgcntlr_ftch_stale_desc or sg2sgcntlr_dma_interr_set or sg2sgcntlr_dma_slverr_set or sg2sgcntlr_dma_decerr_set ; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_HALT_CMPLT_REG -- -- Process Description: -- Implements the Halt Complete register. -- This is sticky and is only cleared by a reset. -- ------------------------------------------------------------- IMP_HALT_CMPLT_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_halt_cmplt_reg <= '0'; elsif (sig_shtdwn_sm_set_cmplt_ns = '1') then sig_halt_cmplt_reg <= '1'; else null; -- hold current state end if; end if; end process IMP_HALT_CMPLT_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_DM_HALT_FLOP -- -- Process Description: -- Implements the sticky flag that requests a DataMover -- HALT. -- This is sticky and is only cleared by a reset. -- ------------------------------------------------------------- IMP_DM_HALT_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_halt_dm <= '0'; elsif (sig_shtdwn_sm_set_dm_halt_ns = '1') then sig_halt_dm <= '1'; else null; -- Hold Current State end if; end if; end process IMP_DM_HALT_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_FTCH_HALT_FLOP -- -- Process Description: -- Implements the sticky flag that requests a DataMover -- HALT. -- This is sticky and is only cleared by a reset. -- ------------------------------------------------------------- IMP_FTCH_HALT_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_halt_fetch <= '0'; elsif (sig_shtdwn_sm_set_ftch_halt_ns = '1') then sig_halt_fetch <= '1'; else null; -- Hold Current State end if; end if; end process IMP_FTCH_HALT_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_DM_SG_FLUSH -- -- Process Description: -- Implements the sticky flag that requests a SG -- Queue flush. The Shutdown state Machine controls -- when it is set. -- This is sticky and is only cleared by a reset. -- ------------------------------------------------------------- IMP_DM_SG_FLUSH : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_flush_sg <= '0'; elsif (sig_shtdwn_sm_flush_sg_ns = '1') then sig_flush_sg <= '1'; else null; -- Hold Current State end if; end if; end process IMP_DM_SG_FLUSH; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_STS_HALT_FLOP -- -- Process Description: -- Implements the sticky flag that requests a Status State -- Machine halt. -- This is sticky and is only cleared by a reset. -- ------------------------------------------------------------- IMP_STS_HALT_FLOP : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_halt_status <= '0'; elsif (sig_shtdwn_sm_set_sts_halt_ns = '1') then sig_halt_status <= '1'; else null; -- Hold Current State end if; end if; end process IMP_STS_HALT_FLOP; ------------------------------------------------------------- -- Combinational Process -- -- Label: IMP_SHTDWN_SM_COMB -- -- Process Description: -- Implements the combinatorial portion of the Shutdown -- State Machine. The shutdown sequence is activated by -- either a soft reset request from the reset module or -- by a detected error condition. -- ------------------------------------------------------------- IMP_SHTDWN_SM_COMB : process (sig_shtdwn_sm_state , sig_do_shutdown , sg2sgcntlr_ftch_idle , sg2sgcntlr_updt_idle , sig_ftchsm_idle , sig_stssm_idle , sig_dm_status_empty , sig_fetch_update_empty , sig_dmhalt_cmplt , sig_sg_error ) begin -- assign the default values sig_shtdwn_sm_state_ns <= SHTDWN_IDLE ; sig_shtdwn_sm_flush_sg_ns <= '0'; sig_shtdwn_sm_set_ftch_halt_ns <= '0'; sig_shtdwn_sm_set_dm_halt_ns <= '0'; sig_shtdwn_sm_set_sts_halt_ns <= '0'; sig_shtdwn_sm_set_cmplt_ns <= '0'; case sig_shtdwn_sm_state is --------------------------------- when SHTDWN_IDLE => if (sig_do_shutdown = '1') then -- start shutdown sequence sig_shtdwn_sm_state_ns <= HALT_FTCH_DM; sig_shtdwn_sm_set_ftch_halt_ns <= '1'; sig_shtdwn_sm_set_dm_halt_ns <= '1'; else -- Stay here sig_shtdwn_sm_state_ns <= SHTDWN_IDLE ; end if; --------------------------------- when HALT_FTCH_DM => sig_shtdwn_sm_state_ns <= WAIT_FTCH_IDLE ; sig_shtdwn_sm_flush_sg_ns <= '1' ; --------------------------------- when WAIT_FTCH_IDLE => if (sig_ftchsm_idle = '1') then sig_shtdwn_sm_state_ns <= WAIT_FTCH_UPDATE ; else sig_shtdwn_sm_state_ns <= WAIT_FTCH_IDLE ; end if; --------------------------------- when WAIT_FTCH_UPDATE => if (sg2sgcntlr_ftch_idle = '1' and sig_ftchsm_idle = '1') then sig_shtdwn_sm_state_ns <= WAIT_DM_HALT_CMPLT ; else sig_shtdwn_sm_state_ns <= WAIT_FTCH_UPDATE ; end if; --------------------------------- when WAIT_DM_HALT_CMPLT => if (sig_dmhalt_cmplt = '1') then sig_shtdwn_sm_state_ns <= WAIT_STS_IDLE ; sig_shtdwn_sm_set_sts_halt_ns <= '1' ; else sig_shtdwn_sm_state_ns <= WAIT_DM_HALT_CMPLT ; end if; --------------------------------- when WAIT_STS_IDLE => if (sig_stssm_idle = '1') then sig_shtdwn_sm_state_ns <= WAIT_STS_UPDATE ; else sig_shtdwn_sm_state_ns <= WAIT_STS_IDLE ; end if; --------------------------------- when WAIT_STS_UPDATE => if (sig_dm_status_empty = '1') then sig_shtdwn_sm_state_ns <= WAIT_SG_UPDATE ; else sig_shtdwn_sm_state_ns <= WAIT_STS_UPDATE ; end if; --------------------------------- when WAIT_SG_UPDATE => if (sg2sgcntlr_updt_idle = '1') then sig_shtdwn_sm_state_ns <= SHTDWN_CMPLT ; sig_shtdwn_sm_set_cmplt_ns <= '1'; else sig_shtdwn_sm_state_ns <= WAIT_SG_UPDATE ; end if; --------------------------------- when SHTDWN_CMPLT => sig_shtdwn_sm_state_ns <= SHTDWN_CMPLT ; sig_shtdwn_sm_set_cmplt_ns <= '1'; --------------------------------- when others => -- shouldn't ever get here sig_shtdwn_sm_state_ns <= SHTDWN_IDLE ; end case; end process IMP_SHTDWN_SM_COMB; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_SHTDWN_SM_REG -- -- Process Description: -- Implements the registered portion of the shutdown -- State Machine. -- ------------------------------------------------------------- IMP_SHTDWN_SM_REG : process (axi_aclk) begin if (axi_aclk'event and axi_aclk = '1') then if (axi_reset = '1') then sig_shtdwn_sm_state <= SHTDWN_IDLE ; sig_shtdwn_sm_flush_sg <= '0' ; sig_shtdwn_sm_set_ftch_halt <= '0' ; sig_shtdwn_sm_set_dm_halt <= '0' ; sig_shtdwn_sm_set_sts_halt <= '0' ; sig_shtdwn_sm_set_cmplt <= '0' ; else sig_shtdwn_sm_state <= sig_shtdwn_sm_state_ns ; sig_shtdwn_sm_flush_sg <= sig_shtdwn_sm_flush_sg_ns ; sig_shtdwn_sm_set_ftch_halt <= sig_shtdwn_sm_set_ftch_halt_ns ; sig_shtdwn_sm_set_dm_halt <= sig_shtdwn_sm_set_dm_halt_ns ; sig_shtdwn_sm_set_sts_halt <= sig_shtdwn_sm_set_sts_halt_ns ; sig_shtdwn_sm_set_cmplt <= sig_shtdwn_sm_set_cmplt_ns ; end if; end if; end process IMP_SHTDWN_SM_REG; end implementation;

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The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2005 - 2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: cntr_incr_decr_addn_f.vhd -- -- Description: This counter can increment, decrement or skip ahead -- by an arbitrary amount. -- -- If Reset is active, the value Cnt synchronously resets -- to all ones. (This reset value, different than the -- customary reset value of zero, caters to the original -- application of cntr_incr_decr_addn_f as the address -- counter for srl_fifo_rbu_f.) -- -- Otherwise, on each Clk, one is added to Cnt if Incr is -- asserted and one is subtracted if Decr is asserted. (If -- both are asserted, then there is no change to Cnt.) -- -- If Decr is not asserted, then the input value, -- Nm_to_add, is added. (Simultaneous assertion of Incr -- would add one more.) If Decr is asserted, then -- N_to_add, is ignored, i.e., it is possible to decrement -- by one or add N, but not both, and Decr overrides. -- -- The value that Cnt will take on at the next clock -- is available as Cnt_p1. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- cntr_incr_decr_addn_f.vhd -- ------------------------------------------------------------------------------- -- -- History: -- FLO 12/30/05 First Version. -- -- ~~~~~~ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- predecessor value by # clks: "*_p#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- entity cntr_incr_decr_addn_f is generic ( C_SIZE : natural; C_FAMILY : string := "nofamily" ); port ( Clk : in std_logic; Reset : in std_logic; -- Note: the counter resets to all ones! Incr : in std_logic; Decr : in std_logic; N_to_add : in std_logic_vector(C_SIZE-1 downto 0); Cnt : out std_logic_vector(C_SIZE-1 downto 0); Cnt_p1 : out std_logic_vector(C_SIZE-1 downto 0) ); end entity cntr_incr_decr_addn_f; ---( library proc_common_v3_00_a; library ieee; use ieee.numeric_std.UNSIGNED; use ieee.numeric_std."+"; library unisim; use unisim.all; -- Make unisim entities available for default binding. -- architecture imp of cntr_incr_decr_addn_f is use proc_common_v3_00_a.family_support; use family_support.all; -- primitives_type, primitive_array_type, supported constant COUNTER_PRIMS_AVAIL : boolean := supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDS)); signal cnt_i : std_logic_vector(Cnt'range); signal cnt_i_p1 : std_logic_vector(Cnt'range); ---------------------------------------------------------------------------- -- Unisim components declared locally for maximum avoidance of default -- binding and vcomponents version issues. ---------------------------------------------------------------------------- component MUXCY_L port ( LO : out std_ulogic; CI : in std_ulogic; DI : in std_ulogic; S : in std_ulogic ); end component; component XORCY port ( O : out std_ulogic; CI : in std_ulogic; LI : in std_ulogic ); end component; component FDS generic ( INIT : bit := '1' ); port ( Q : out std_ulogic; C : in std_ulogic; D : in std_ulogic; S : in std_ulogic ); end component; begin -- architecture imp ---( STRUCTURAL_A_GEN : if COUNTER_PRIMS_AVAIL = true generate signal hsum_A : std_logic_vector(Cnt'range); signal cry : std_logic_vector(Cnt'length downto 0); begin ---( cry(0) <= Incr; Addr_Counters : for I in cnt_i'range generate hsum_A(I) <= ((Decr or N_to_add(i)) xor cnt_i(I)); MUXCY_L_I : component MUXCY_L port map ( DI => cnt_i(I), CI => cry(I), S => hsum_A(I), LO => cry(I+1)); XORCY_I : component XORCY port map ( LI => hsum_A(I), CI => cry(I), O => cnt_i_p1(I)); FDS_I : component FDS port map ( Q => cnt_i(I), C => Clk, D => cnt_i_p1(I), S => Reset); end generate Addr_Counters; ---) end generate STRUCTURAL_A_GEN; ---) ---( INFERRED_GEN : if COUNTER_PRIMS_AVAIL = false generate -- CNT_I_P1_PROC : process( cnt_i, N_to_add, Decr, Incr ) is -- function qual_n_to_add(N_to_add : std_logic_vector; Decr : std_logic ) return UNSIGNED is variable r: UNSIGNED(N_to_add'range); begin for i in r'range loop r(i) := N_to_add(i) or Decr; end loop; return r; end; -- function to_singleton_unsigned(s : std_logic) return unsigned is variable r : unsigned(0 to 0) := (others => s); begin return r; end; -- begin cnt_i_p1 <= std_logic_vector( UNSIGNED(cnt_i) + qual_n_to_add(N_to_add, Decr) + to_singleton_unsigned(Incr) ); end process; -- CNT_I_PROC : process(Clk) is begin if Clk'event and Clk = '1' then if Reset = '1' then cnt_i <= (others => '1'); else cnt_i <= cnt_i_p1; end if; end if; end process; -- end generate INFERRED_GEN; ---) Cnt <= cnt_i; Cnt_p1 <= cnt_i_p1; end architecture imp; ---)

---------------------------------------------------------------------------------- -- Engineer: Mike Field <[email protected]> -- -- Description: Top level for the OV7670 camera project. ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; Library UNISIM; use UNISIM.vcomponents.all; entity ov7670_top is Port ( clk100 : in STD_LOGIC; OV7670_SIOC : out STD_LOGIC; OV7670_SIOD : inout STD_LOGIC; OV7670_RESET : out STD_LOGIC; OV7670_PWDN : out STD_LOGIC; OV7670_VSYNC : in STD_LOGIC; OV7670_HREF : in STD_LOGIC; OV7670_PCLK : in STD_LOGIC; OV7670_XCLK : out STD_LOGIC; OV7670_D : in STD_LOGIC_VECTOR(7 downto 0); LED : out STD_LOGIC_VECTOR(7 downto 0); vga_red : out STD_LOGIC_VECTOR(3 downto 0); vga_green : out STD_LOGIC_VECTOR(3 downto 0); vga_blue : out STD_LOGIC_VECTOR(3 downto 0); vga_hsync : out STD_LOGIC; vga_vsync : out STD_LOGIC; btn : in STD_LOGIC ); end ov7670_top; architecture Behavioral of ov7670_top is COMPONENT debounce PORT( clk : IN std_logic; i : IN std_logic; o : OUT std_logic ); END COMPONENT; component clocking port (-- Clock in ports CLK_100 : in std_logic; -- Clock out ports CLK_50 : out std_logic; CLK_25 : out std_logic ); end component; COMPONENT ov7670_controller PORT( clk : IN std_logic; resend: IN std_logic; config_finished : out std_logic; siod : INOUT std_logic; sioc : OUT std_logic; reset : OUT std_logic; pwdn : OUT std_logic; xclk : OUT std_logic ); END COMPONENT; COMPONENT frame_buffer PORT ( clka : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(18 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(11 DOWNTO 0); clkb : IN STD_LOGIC; addrb : IN STD_LOGIC_VECTOR(18 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) ); END COMPONENT; COMPONENT ov7670_capture PORT( pclk : IN std_logic; vsync : IN std_logic; href : IN std_logic; d : IN std_logic_vector(7 downto 0); addr : OUT std_logic_vector(18 downto 0); dout : OUT std_logic_vector(11 downto 0); we : OUT std_logic ); END COMPONENT; COMPONENT vga PORT( clk25 : IN std_logic; vga_red : OUT std_logic_vector(3 downto 0); vga_green : OUT std_logic_vector(3 downto 0); vga_blue : OUT std_logic_vector(3 downto 0); vga_hsync : OUT std_logic; vga_vsync : OUT std_logic; frame_addr : OUT std_logic_vector(18 downto 0); frame_pixel : IN std_logic_vector(11 downto 0) ); END COMPONENT; signal frame_addr : std_logic_vector(18 downto 0); signal frame_pixel : std_logic_vector(11 downto 0); signal capture_addr : std_logic_vector(18 downto 0); signal capture_data : std_logic_vector(11 downto 0); signal capture_we : std_logic_vector(0 downto 0); signal resend : std_logic; signal config_finished : std_logic; signal clk_feedback : std_logic; signal clk50u : std_logic; signal clk50 : std_logic; signal clk25u : std_logic; signal clk25 : std_logic; signal buffered_pclk : std_logic; begin btn_debounce: debounce PORT MAP( clk => clk50, i => btn, o => resend ); Inst_vga: vga PORT MAP( clk25 => clk25, vga_red => vga_red, vga_green => vga_green, vga_blue => vga_blue, vga_hsync => vga_hsync, vga_vsync => vga_vsync, frame_addr => frame_addr, frame_pixel => frame_pixel ); fb : frame_buffer PORT MAP ( clka => OV7670_PCLK, wea => capture_we, addra => capture_addr, dina => capture_data, clkb => clk50, addrb => frame_addr, doutb => frame_pixel ); led <= "0000000" & config_finished; capture: ov7670_capture PORT MAP( pclk => OV7670_PCLK, vsync => OV7670_VSYNC, href => OV7670_HREF, d => OV7670_D, addr => capture_addr, dout => capture_data, we => capture_we(0) ); controller: ov7670_controller PORT MAP( clk => clk50, sioc => ov7670_sioc, resend => resend, config_finished => config_finished, siod => ov7670_siod, pwdn => OV7670_PWDN, reset => OV7670_RESET, xclk => OV7670_XCLK ); your_instance_name : clocking port map (-- Clock in ports CLK_100 => CLK100, -- Clock out ports CLK_50 => CLK50, CLK_25 => CLK25); end Behavioral;

package pkg1 is type my_int1 is range 1 to 10; type my_int2 is range 1 to 10; type my_int3 is range 1 to 10; end package; ------------------------------------------------------------------------------- package pkg2 is use work.pkg1.my_int2; -- OK function func return my_int2; end package; package body pkg2 is use work.pkg1.my_int1; -- OK constant x : my_int1 := 2; -- OK function func return my_int2 is -- OK use work.pkg1.my_int3; -- OK variable y : my_int3; -- OK begin return 0; end function; constant y : my_int3; -- Error end package body; ------------------------------------------------------------------------------- entity ent is use work.pkg1.my_int1; -- OK constant c : my_int1 := 2; -- OK end entity;

library verilog; use verilog.vl_types.all; entity finalproject_mm_interconnect_0_cmd_demux_001 is port( sink_valid : in vl_logic_vector(0 downto 0); sink_data : in vl_logic_vector(104 downto 0); sink_channel : in vl_logic_vector(5 downto 0); sink_startofpacket: in vl_logic; sink_endofpacket: in vl_logic; sink_ready : out vl_logic; src0_valid : out vl_logic; src0_data : out vl_logic_vector(104 downto 0); src0_channel : out vl_logic_vector(5 downto 0); src0_startofpacket: out vl_logic; src0_endofpacket: out vl_logic; src0_ready : in vl_logic; src1_valid : out vl_logic; src1_data : out vl_logic_vector(104 downto 0); src1_channel : out vl_logic_vector(5 downto 0); src1_startofpacket: out vl_logic; src1_endofpacket: out vl_logic; src1_ready : in vl_logic; src2_valid : out vl_logic; src2_data : out vl_logic_vector(104 downto 0); src2_channel : out vl_logic_vector(5 downto 0); src2_startofpacket: out vl_logic; src2_endofpacket: out vl_logic; src2_ready : in vl_logic; clk : in vl_logic; reset : in vl_logic ); end finalproject_mm_interconnect_0_cmd_demux_001;

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; use work.PhoenixPackage.regNport; use work.HammingPack16.all; entity FPPM is port ( clock : in std_logic; reset_in : in std_logic; -- reset geral da NoC rx : in regHamm_Nport; -- rx (sinal que indica que estou recebendo transmissao) statusHamming : in array_statusHamming; -- status (sem erro, erro corrigido, erro detectado) das 4 portas (EAST,WEST,NORTH,SOUTH) write_FaultTable : out regHamm_Nport; -- sinal para indicar escrita na tabela de falhas row_FaultTablePorts_out : out row_FaultTable_Ports -- linha a ser escrita na tabela de falhas ); end FPPM; architecture FPPM of FPPM is -- CUIDADO! Os contadores tem apenas COUNTERS_SIZE bits! constant N: integer range 1 to 31 := 8; constant M: integer range 1 to 31 := 4; constant P: integer range 1 to 31 := 30; constant COUNTER_UPDATE_TABLE: integer := 1; -- numero de flits recebidos necessarios para atualizar a tabela begin FPPM_generate: for i in 0 to (HAMM_NPORT-1) generate begin process(clock, reset_in) variable counter_write: integer range 0 to COUNTER_UPDATE_TABLE; variable reset: std_logic := '0'; variable counter_N, counter_M, counter_P: std_logic_vector((COUNTERS_SIZE-1) downto 0); variable link_status: std_logic_vector(1 downto 0) := "00"; begin if (reset_in='1') then reset := '0'; counter_N := (others=>'0'); counter_M := (others=>'0'); counter_P := (others=>'0'); write_FaultTable(i) <= '0'; row_FaultTablePorts_out(i) <= (others=>'0'); end if; if (clock'event and clock='1' and rx(i)='1') then --counter_write := counter_write + 1; case statusHamming(i) is when NE => counter_N := counter_N + 1; if (counter_N = N) then link_status := "00"; reset := '1'; end if; when EC => counter_M := counter_M + 1; if (counter_M = M) then link_status := "01"; reset := '1'; end if; when ED => counter_P := counter_P + 1; if (counter_P = P) then link_status := "10"; reset := '1'; end if; when others => null; end case; if (reset = '1') then reset := '0'; counter_N := (others=>'0'); counter_M := (others=>'0'); counter_P := (others=>'0'); end if; if (counter_write = COUNTER_UPDATE_TABLE) then --if (false) then write_FaultTable(i) <= '1'; row_FaultTablePorts_out(i) <= link_status & counter_N & counter_M & counter_P; counter_write := 0; else write_FaultTable(i) <= '0'; row_FaultTablePorts_out(i) <= (others=>'0'); end if; elsif (rx(i)='0') then write_FaultTable(i) <= '0'; row_FaultTablePorts_out(i) <= (others=>'0'); end if; end process; end generate; end FPPM;

---------------------------------------------------------------------------------- -- Company: ITESM CQ -- Engineer: Miguel Gonzalez A01203712 -- -- Create Date: 14:13:16 11/21/2015 -- Design Name: -- Module Name: Robot - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: Main Robot Module -- -- Dependencies: -- -- Revision: -- Revision 0.0.1 - File Created -- Revision 1.1.0 - Main Robot Module Implementation -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library work; use work.PKG_ROBOT_SUMO.all; entity Robot is Port ( in_sonic_1 : in STD_LOGIC; -- 0 no detecta # 1 detecta oponente enfrente in_color_1 : in STD_LOGIC; -- 0 negro normal # 1 blanco reversa in_clk : in STD_LOGIC; in_rst : in STD_LOGIC; out_action : out STD_LOGIC_VECTOR(2 downto 0)); end Robot; architecture Behavioral of Robot is --Declarar componentes -- Comp: U1_Motor Divisor de frequencia 100/1 component Freq_Div port ( in_rst : in STD_LOGIC; in_clk : in STD_LOGIC; out_time_base : out STD_LOGIC); end component; -- Comp : U1 State Register for Robot component State_Reg_Robot port ( in_clk : in STD_LOGIC; in_time_base : in STD_LOGIC; in_rst : in STD_LOGIC; in_next_state : in robot_state_values; out_pres_state : out robot_state_values); end component; -- Comp : U3 Finite State Machine component FSM_robot port ( in_pres_state : in robot_state_values; in_color_1 : in STD_LOGIC; in_sonic_1 : in STD_LOGIC; out_next_state_fsmr: out robot_state_values); end component; -- Comp : U4 Output Robot component Output_robot port ( in_pres_state : in robot_state_values; out_action : out STD_LOGIC_VECTOR(2 downto 0)); end component; -- seniales embebidas -- 1 bit signal time_base : STD_LOGIC; -- 2 o mas bits -- of types signal pres_state, next_state: robot_state_values; -- integers signal curr_state_duration : integer range 0 to ROBOT_MAX; begin -- instanciar componentes U2_1 : Freq_Div port map(in_rst, in_clk, time_base); U2_2 : State_Reg_Robot port map(in_clk, time_base, in_rst, next_state, pres_state); U2_3 : FSM_robot port map(pres_state, in_color_1, in_sonic_1, next_state); U2_4 : Output_robot port map(pres_state, out_action); end Behavioral;

-- Copyright (c) University of Florida -- -- This file is part of window_gen. -- -- window_gen is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- window_gen is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with window_gen. If not, see <http://www.gnu.org/licenses/>. -- Greg Stitt -- University of Florida -- Description: -- fifo_vr (variable read) -- This entity implements a fifo that writes a fixed (but configurable) -- number of inputs in parallel, while allowing a variable number of outputs -- to be read each cycle. -- -- The entity is useful for streams of data where upstream components always -- produce a fixed amount of data, but downstream components may need to -- read a variable amount of data. e.g., when streaming an image sequentially -- from memory into an FPGA, the memory might provide four pixels per cycle. -- If the circuit buffers each row into separate on-chip memories, then at the -- end of a row, the circuit may need to read less than four pixels if the # of -- columns is not a multiple of four. In this case, the buffer enables the -- memory to continually write four pixels per cycle, while the downstream -- circuit reads as much as needed. -- -- The size of the fifo is fixed because its main purpose is to dynamically -- read varying amounts of data from a stream. If a typical FIFO is needed for -- buffering, the user should connect that FIFO to the input of this -- entity. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.math_custom.all; ------------------------------------------------------------------------------- -- Generic Descriptions -- data_width : The width of a single element to read from the FIFO -- parallel_io : The number of parallel inputs written every cycle, which -- is also the max number of outputs that can be read each -- cycle. ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Port Descriptions (all control signals are active high) -- clk: clock -- rst: asynchronous reset -- rd : read data from the buffer (does nothing when empty is asserted) -- rd_amount : The amount of elements to read from the buffer when rd is -- asserted. Note that if rd_amount is larger than the actual -- amount of elements in the fifo, the fifo returns only what -- it has stored. e.g., If the fifo has 2 elements and rd_amount -- is 3 when rd is asserted, the fifo will output two valid -- elements and a third junk element. -- wr : write num_inputs inputs into the buffer (does nothing when -- full is asserted) -- empty : asserted when the buffer is empty (has 0 elements in fifo) -- full : asserted when there isn't room to write num_inputs inputs. -- input : num_inputs input values, concatenated into a big std_logic_vector -- output : max_outputs outputs. When rd_amount < max_outputs, the higher bits -- contains valid datas. -- count : the number of valid data_width elements in the fifo -- valid_out : individual valid bits for each output ------------------------------------------------------------------------------- entity fifo_vr is generic ( data_width : positive; parallel_io : positive; input0_at_MSB : boolean := false; output0_at_MSB : boolean := false); port ( clk : in std_logic; rst : in std_logic; rd : in std_logic; rd_amount : in std_logic_vector(bitsNeeded(parallel_io)-1 downto 0); wr : in std_logic; empty : out std_logic; full : out std_logic; input : in std_logic_vector(parallel_io*data_width-1 downto 0); output : out std_logic_vector(parallel_io*data_width-1 downto 0); count : out std_logic_vector(bitsNeeded(parallel_io)-1 downto 0); valid_out : out std_logic_vector(parallel_io-1 downto 0)); end fifo_vr; architecture DEFAULT of fifo_vr is type data_array is array (natural range <>) of std_logic_vector(data_width-1 downto 0); signal count_s : unsigned(bitsNeeded(parallel_io)-1 downto 0); signal front : integer range 0 to parallel_io-1; signal regs : data_array(0 to parallel_io*2-1); signal valid_wr : std_logic; signal valid_rd : std_logic; signal full_s : std_logic; signal empty_s : std_logic; signal valid : std_logic_vector(0 to parallel_io*2-1); signal valid_out_s : std_logic_vector(0 to parallel_io-1); signal inputs : data_array(0 to parallel_io-1); signal window_reset : std_logic; signal rd_amount_s : integer range 0 to parallel_io; begin -- the buffer is empty any of the valid bits in the lower half are '0' empty_s <= not valid(0); empty <= empty_s; -- the buffer is full when any of the valid bits in the upper half are -- asserted, but not when there is a valid read that resets the window full_s <= valid(parallel_io) and not (valid_rd and window_reset) and not empty_s; full <= full_s; -- check for valid rd/wr to avoid data loss valid_wr <= wr and not full_s; valid_rd <= rd and not empty_s; count <= std_logic_vector(count_s); valid_out <= valid_out_s; -- the window position is reset any time front extends past the first half window_reset <= '0' when front + rd_amount_s < parallel_io else '1'; -- devectorize the input vector into an array based on the whether or not -- the first input is at the MSB or LDB U_INPUT0_AT_MSB : if (INPUT0_AT_MSB) generate process(input) begin for i in 0 to parallel_io-1 loop inputs(i) <= input(input'length-i*data_width-1 downto input'length-(i+1)*data_width); end loop; end process; end generate; U_INPUT0_AT_LSB : if (INPUT0_AT_MSB = false) generate process(input) begin for i in 0 to parallel_io-1 loop inputs(i) <= input((i+1)*data_width-1 downto i*data_width); end loop; end process; end generate; -- calculate the number of valid bits in the output process(valid_out_s) variable temp : unsigned(bitsNeeded(parallel_io)-1 downto 0); begin -- calculate the number of valid outputs temp := (others => '0'); for i in 0 to parallel_io-1 loop if (valid_out_s(i) = '1') then temp := temp + 1; end if; end loop; count_s <= temp; end process; -- make sure rd_amount can't exceed number of valid outputs process(rd_amount, count_s) begin if (unsigned(rd_amount) > count_s) then rd_amount_s <= to_integer(unsigned(count_s)); else rd_amount_s <= to_integer(unsigned(rd_amount)); end if; end process; -- align the output with a parallel_io-element window starting at front process(regs, front, valid) variable index : integer range 0 to parallel_io*2-2; begin for i in 0 to parallel_io-1 loop -- no need for mod because window gets reset to avoid extending -- past end of the buffer index := front + i; -- set the corresponding output bits for the current register if (OUTPUT0_AT_MSB) then -- the first output starts at the highest index, whereas -- the stored register values start at the lowest index output(output'length-data_width*i-1 downto output'length-data_width*(i+1)) <= regs(index); -- align the output valid bits; valid_out_s(i) <= valid(index); else output((i+1)*data_width-1 downto i*data_width) <= regs(index); valid_out_s(parallel_io-i-1) <= valid(index); end if; end loop; end process; process(clk, rst) begin if (rst = '1') then for i in 0 to parallel_io*2-1 loop regs(i) <= (others => '0'); valid(i) <= '0'; end loop; front <= 0; elsif (rising_edge(clk)) then -- during a read, slide the front of the window so the next output -- is aligned properly. if (valid_rd = '1') then if (window_reset = '0') then front <= front + rd_amount_s; else front <= front + rd_amount_s - parallel_io; end if; end if; -- check if the bottom half is empty. All parallel_io valid bits -- of each half should be the same, so only the first bit has to be -- checked if (valid(0) = '0' or (valid_rd = '1' and window_reset = '1')) then -- move the top half to the bottom. for i in 0 to parallel_io-1 loop regs(i) <= regs(i+parallel_io); valid(i) <= valid(i+parallel_io); end loop; -- reset the valid bits for the top half for i in parallel_io to parallel_io*2-1 loop valid(i) <= '0'; end loop; end if; -- write new data to the top half of buffer if (valid_wr = '1') then for i in 0 to parallel_io-1 loop regs(i+parallel_io) <= inputs(i); valid(i+parallel_io) <= '1'; end loop; end if; end if; end process; end DEFAULT;

------------------------------------------------------------------------------- -- -- Copyright (c) 1989 by Intermetrics, Inc. -- All rights reserved. -- ------------------------------------------------------------------------------- -- -- TEST NAME: -- -- CT00226 -- -- AUTHOR: -- -- A. Wilmot -- -- TEST OBJECTIVES: -- -- 1.1.1.2 (8) -- -- DESIGN UNIT ORDERING: -- -- GENERIC_STANDARD_TYPES(ARCH00226) -- ENT00226_Test_Bench(ARCH00226_Test_Bench) -- -- REVISION HISTORY: -- -- 15-JUN-1987 - initial revision -- -- NOTES: -- -- self-checking -- automatically generated -- use WORK.STANDARD_TYPES ; use STANDARD_TYPES.test_report, STANDARD_TYPES.switch, STANDARD_TYPES.up, STANDARD_TYPES.down, STANDARD_TYPES.toggle, STANDARD_TYPES."=" ; architecture ARCH00226 of GENERIC_STANDARD_TYPES is signal i_bit_vector_1, i_bit_vector_2 : st_bit_vector := c_st_bit_vector_1 ; signal i_string_1, i_string_2 : st_string := c_st_string_1 ; signal i_t_rec1_1, i_t_rec1_2 : st_rec1 := c_st_rec1_1 ; signal i_st_rec1_1, i_st_rec1_2 : st_rec1 := c_st_rec1_1 ; signal i_t_rec2_1, i_t_rec2_2 : st_rec2 := c_st_rec2_1 ; signal i_st_rec2_1, i_st_rec2_2 : st_rec2 := c_st_rec2_1 ; signal i_t_rec3_1, i_t_rec3_2 : st_rec3 := c_st_rec3_1 ; signal i_st_rec3_1, i_st_rec3_2 : st_rec3 := c_st_rec3_1 ; signal i_t_arr1_1, i_t_arr1_2 : st_arr1 := c_st_arr1_1 ; signal i_st_arr1_1, i_st_arr1_2 : st_arr1 := c_st_arr1_1 ; signal i_t_arr2_1, i_t_arr2_2 : st_arr2 := c_st_arr2_1 ; signal i_st_arr2_1, i_st_arr2_2 : st_arr2 := c_st_arr2_1 ; signal i_t_arr3_1, i_t_arr3_2 : st_arr3 := c_st_arr3_1 ; signal i_st_arr3_1, i_st_arr3_2 : st_arr3 := c_st_arr3_1 ; -- begin L1: block port ( i_bit_vector_1, i_bit_vector_2 : in bit_vector := c_st_bit_vector_1 ; i_string_1, i_string_2 : in string := c_st_string_1 ; i_t_rec1_1, i_t_rec1_2 : in t_rec1 := c_st_rec1_1 ; i_st_rec1_1, i_st_rec1_2 : in st_rec1 := c_st_rec1_1 ; i_t_rec2_1, i_t_rec2_2 : in t_rec2 := c_st_rec2_1 ; i_st_rec2_1, i_st_rec2_2 : in st_rec2 := c_st_rec2_1 ; i_t_rec3_1, i_t_rec3_2 : in t_rec3 := c_st_rec3_1 ; i_st_rec3_1, i_st_rec3_2 : in st_rec3 := c_st_rec3_1 ; i_t_arr1_1, i_t_arr1_2 : in t_arr1 := c_st_arr1_1 ; i_st_arr1_1, i_st_arr1_2 : in st_arr1 := c_st_arr1_1 ; i_t_arr2_1, i_t_arr2_2 : in t_arr2 := c_st_arr2_1 ; i_st_arr2_1, i_st_arr2_2 : in st_arr2 := c_st_arr2_1 ; i_t_arr3_1, i_t_arr3_2 : in t_arr3 := c_st_arr3_1 ; i_st_arr3_1, i_st_arr3_2 : in st_arr3 := c_st_arr3_1 ) ; port map ( i_bit_vector_1, i_bit_vector_2, i_string_1, i_string_2, i_t_rec1_1, i_t_rec1_2, i_st_rec1_1, i_st_rec1_2, i_t_rec2_1, i_t_rec2_2, i_st_rec2_1, i_st_rec2_2, i_t_rec3_1, i_t_rec3_2, i_st_rec3_1, i_st_rec3_2, i_t_arr1_1, i_t_arr1_2, i_st_arr1_1, i_st_arr1_2, i_t_arr2_1, i_t_arr2_2, i_st_arr2_1, i_st_arr2_2, i_t_arr3_1, i_t_arr3_2, i_st_arr3_1, i_st_arr3_2 ) ; -- begin process variable correct : boolean := true ; begin correct := correct and i_bit_vector_1 = c_st_bit_vector_1 and i_bit_vector_2 = c_st_bit_vector_1 ; correct := correct and i_string_1 = c_st_string_1 and i_string_2 = c_st_string_1 ; correct := correct and i_t_rec1_1 = c_st_rec1_1 and i_t_rec1_2 = c_st_rec1_1 ; correct := correct and i_st_rec1_1 = c_st_rec1_1 and i_st_rec1_2 = c_st_rec1_1 ; correct := correct and i_t_rec2_1 = c_st_rec2_1 and i_t_rec2_2 = c_st_rec2_1 ; correct := correct and i_st_rec2_1 = c_st_rec2_1 and i_st_rec2_2 = c_st_rec2_1 ; correct := correct and i_t_rec3_1 = c_st_rec3_1 and i_t_rec3_2 = c_st_rec3_1 ; correct := correct and i_st_rec3_1 = c_st_rec3_1 and i_st_rec3_2 = c_st_rec3_1 ; correct := correct and i_t_arr1_1 = c_st_arr1_1 and i_t_arr1_2 = c_st_arr1_1 ; correct := correct and i_st_arr1_1 = c_st_arr1_1 and i_st_arr1_2 = c_st_arr1_1 ; correct := correct and i_t_arr2_1 = c_st_arr2_1 and i_t_arr2_2 = c_st_arr2_1 ; correct := correct and i_st_arr2_1 = c_st_arr2_1 and i_st_arr2_2 = c_st_arr2_1 ; correct := correct and i_t_arr3_1 = c_st_arr3_1 and i_t_arr3_2 = c_st_arr3_1 ; correct := correct and i_st_arr3_1 = c_st_arr3_1 and i_st_arr3_2 = c_st_arr3_1 ; -- test_report ( "ENT00226" , "Associated composite in ports with generic subtypes" , correct) ; wait ; end process ; end block L1 ; end ARCH00226 ; -- entity ENT00226_Test_Bench is end ENT00226_Test_Bench ; -- architecture ARCH00226_Test_Bench of ENT00226_Test_Bench is begin L1: block component UUT end component ; -- for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00226 ) ; begin CIS1 : UUT ; end block L1 ; end ARCH00226_Test_Bench ;

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; -------------------------------------------------------- -- x^131 + x^8 + x^3 + x^2 + 1 entity serial_multiplier_131 is generic ( NUM_BITS : positive := 131 -- The order of the finite field ); port( ax : in std_logic_vector(NUM_BITS-1 downto 0); bx : in std_logic_vector(NUM_BITS-1 downto 0); cx : out std_logic_vector(NUM_BITS-1 downto 0); -- cx = ax*bx mod Fx reset : in std_logic; clk : in std_logic; done : out std_logic ); end serial_multiplier_131; ----------------------------------------------------------- architecture behave of serial_multiplier_131 is ----------------------------------------------------------- signal bx_shift : std_logic_vector(NUM_BITS-1 downto 0); -- B and C shifted one position to the rigth signal bx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers signal cx_int : std_logic_vector(NUM_BITS-1 downto 0); -- Internal registers signal counter: std_logic_vector(7 downto 0); -- 8-bit counter, controling the number of iterations: m --señales para las xor de la reduccion: signal xor_1 : std_logic; signal xor_2 : std_logic; signal xor_3 : std_logic; ----------------------------------------------------------- -- States for the finite state machine ----------------------------------------------------------- type CurrentState_type is (NOTHING, END_STATE, MUL_STATE); signal CurrentState: CurrentState_type; ----------------------------------------------------------- begin ----------------------------------------------------------- -- Result of the multiplication xor_1 <= Cx_int(1) xor Cx_int(NUM_BITS-1); xor_2 <= Cx_int(2) xor Cx_int(NUM_BITS-1); xor_3 <= Cx_int(7) xor Cx_int(NUM_BITS-1); Bx_shift <= bx_int(NUM_BITS-2 downto 0)& '0'; -- Shift Bx to left one position ------------------------------------------------------------ -- The finite state machine, it takes m cycles to compute -- the multiplication, a counter is used to keep this count ------------------------------------------------------------ CELL_0: ENTITY work.basic_cell(behave) PORT MAP(Ax(0),Bx_int(NUM_BITS-1),Cx_int(NUM_BITS-1),clk,reset,Cx_int(0)); CELL_1: ENTITY work.basic_cell(behave) PORT MAP(Ax(1),Bx_int(NUM_BITS-1),Cx_int(0),clk,reset,Cx_int(1)); CELL_2: ENTITY work.basic_cell(behave) PORT MAP(Ax(2),Bx_int(NUM_BITS-1),xor_1,clk,reset,Cx_int(2)); CELL_3: ENTITY work.basic_cell(behave) PORT MAP(Ax(3),Bx_int(NUM_BITS-1),xor_2,clk,reset,Cx_int(3)); CELL_4: ENTITY work.basic_cell(behave) PORT MAP(Ax(4),Bx_int(NUM_BITS-1),Cx_int(3),clk,reset,Cx_int(4)); CELL_5: ENTITY work.basic_cell(behave) PORT MAP(Ax(5),Bx_int(NUM_BITS-1),Cx_int(4),clk,reset,Cx_int(5)); CELL_6: ENTITY work.basic_cell(behave) PORT MAP(Ax(6),Bx_int(NUM_BITS-1),Cx_int(5),clk,reset,Cx_int(6)); CELL_7: ENTITY work.basic_cell(behave) PORT MAP(Ax(7),Bx_int(NUM_BITS-1),Cx_int(6),clk,reset,Cx_int(7)); CELL_8: ENTITY work.basic_cell(behave) PORT MAP(Ax(8),Bx_int(NUM_BITS-1),xor_3,clk,reset,Cx_int(8)); CELL_9: ENTITY work.basic_cell(behave) PORT MAP(Ax(9),Bx_int(NUM_BITS-1),Cx_int(8),clk,reset,Cx_int(9)); CELL_10: ENTITY work.basic_cell(behave) PORT MAP(Ax(10),Bx_int(NUM_BITS-1),Cx_int(9),clk,reset,Cx_int(10)); CELL_11: ENTITY work.basic_cell(behave) PORT MAP(Ax(11),Bx_int(NUM_BITS-1),Cx_int(10),clk,reset,Cx_int(11)); CELL_12: ENTITY work.basic_cell(behave) PORT MAP(Ax(12),Bx_int(NUM_BITS-1),Cx_int(11),clk,reset,Cx_int(12)); CELL_13: ENTITY work.basic_cell(behave) PORT MAP(Ax(13),Bx_int(NUM_BITS-1),Cx_int(12),clk,reset,Cx_int(13)); CELL_14: ENTITY work.basic_cell(behave) PORT MAP(Ax(14),Bx_int(NUM_BITS-1),Cx_int(13),clk,reset,Cx_int(14)); CELL_15: ENTITY work.basic_cell(behave) PORT MAP(Ax(15),Bx_int(NUM_BITS-1),Cx_int(14),clk,reset,Cx_int(15)); CELL_16: ENTITY work.basic_cell(behave) PORT MAP(Ax(16),Bx_int(NUM_BITS-1),Cx_int(15),clk,reset,Cx_int(16)); CELL_17: ENTITY work.basic_cell(behave) PORT MAP(Ax(17),Bx_int(NUM_BITS-1),Cx_int(16),clk,reset,Cx_int(17)); CELL_18: ENTITY work.basic_cell(behave) PORT MAP(Ax(18),Bx_int(NUM_BITS-1),Cx_int(17),clk,reset,Cx_int(18)); CELL_19: ENTITY work.basic_cell(behave) PORT MAP(Ax(19),Bx_int(NUM_BITS-1),Cx_int(18),clk,reset,Cx_int(19)); CELL_20: ENTITY work.basic_cell(behave) PORT MAP(Ax(20),Bx_int(NUM_BITS-1),Cx_int(19),clk,reset,Cx_int(20)); CELL_21: ENTITY work.basic_cell(behave) PORT MAP(Ax(21),Bx_int(NUM_BITS-1),Cx_int(20),clk,reset,Cx_int(21)); CELL_22: ENTITY work.basic_cell(behave) PORT MAP(Ax(22),Bx_int(NUM_BITS-1),Cx_int(21),clk,reset,Cx_int(22)); CELL_23: ENTITY work.basic_cell(behave) PORT MAP(Ax(23),Bx_int(NUM_BITS-1),Cx_int(22),clk,reset,Cx_int(23)); CELL_24: ENTITY work.basic_cell(behave) PORT MAP(Ax(24),Bx_int(NUM_BITS-1),Cx_int(23),clk,reset,Cx_int(24)); CELL_25: ENTITY work.basic_cell(behave) PORT MAP(Ax(25),Bx_int(NUM_BITS-1),Cx_int(24),clk,reset,Cx_int(25)); CELL_26: ENTITY work.basic_cell(behave) PORT MAP(Ax(26),Bx_int(NUM_BITS-1),Cx_int(25),clk,reset,Cx_int(26)); CELL_27: ENTITY work.basic_cell(behave) PORT MAP(Ax(27),Bx_int(NUM_BITS-1),Cx_int(26),clk,reset,Cx_int(27)); CELL_28: ENTITY work.basic_cell(behave) PORT MAP(Ax(28),Bx_int(NUM_BITS-1),Cx_int(27),clk,reset,Cx_int(28)); CELL_29: ENTITY work.basic_cell(behave) PORT MAP(Ax(29),Bx_int(NUM_BITS-1),Cx_int(28),clk,reset,Cx_int(29)); CELL_30: ENTITY work.basic_cell(behave) PORT MAP(Ax(30),Bx_int(NUM_BITS-1),Cx_int(29),clk,reset,Cx_int(30)); CELL_31: ENTITY work.basic_cell(behave) PORT MAP(Ax(31),Bx_int(NUM_BITS-1),Cx_int(30),clk,reset,Cx_int(31)); CELL_32: ENTITY work.basic_cell(behave) PORT MAP(Ax(32),Bx_int(NUM_BITS-1),Cx_int(31),clk,reset,Cx_int(32)); CELL_33: ENTITY work.basic_cell(behave) PORT MAP(Ax(33),Bx_int(NUM_BITS-1),Cx_int(32),clk,reset,Cx_int(33)); CELL_34: ENTITY work.basic_cell(behave) PORT MAP(Ax(34),Bx_int(NUM_BITS-1),Cx_int(33),clk,reset,Cx_int(34)); CELL_35: ENTITY work.basic_cell(behave) PORT MAP(Ax(35),Bx_int(NUM_BITS-1),Cx_int(34),clk,reset,Cx_int(35)); CELL_36: ENTITY work.basic_cell(behave) PORT MAP(Ax(36),Bx_int(NUM_BITS-1),Cx_int(35),clk,reset,Cx_int(36)); CELL_37: ENTITY work.basic_cell(behave) PORT MAP(Ax(37),Bx_int(NUM_BITS-1),Cx_int(36),clk,reset,Cx_int(37)); CELL_38: ENTITY work.basic_cell(behave) PORT MAP(Ax(38),Bx_int(NUM_BITS-1),Cx_int(37),clk,reset,Cx_int(38)); CELL_39: ENTITY work.basic_cell(behave) PORT MAP(Ax(39),Bx_int(NUM_BITS-1),Cx_int(38),clk,reset,Cx_int(39)); CELL_40: ENTITY work.basic_cell(behave) PORT MAP(Ax(40),Bx_int(NUM_BITS-1),Cx_int(39),clk,reset,Cx_int(40)); CELL_41: ENTITY work.basic_cell(behave) PORT MAP(Ax(41),Bx_int(NUM_BITS-1),Cx_int(40),clk,reset,Cx_int(41)); CELL_42: ENTITY work.basic_cell(behave) PORT MAP(Ax(42),Bx_int(NUM_BITS-1),Cx_int(41),clk,reset,Cx_int(42)); CELL_43: ENTITY work.basic_cell(behave) PORT MAP(Ax(43),Bx_int(NUM_BITS-1),Cx_int(42),clk,reset,Cx_int(43)); CELL_44: ENTITY work.basic_cell(behave) PORT MAP(Ax(44),Bx_int(NUM_BITS-1),Cx_int(43),clk,reset,Cx_int(44)); CELL_45: ENTITY work.basic_cell(behave) PORT MAP(Ax(45),Bx_int(NUM_BITS-1),Cx_int(44),clk,reset,Cx_int(45)); CELL_46: ENTITY work.basic_cell(behave) PORT MAP(Ax(46),Bx_int(NUM_BITS-1),Cx_int(45),clk,reset,Cx_int(46)); CELL_47: ENTITY work.basic_cell(behave) PORT MAP(Ax(47),Bx_int(NUM_BITS-1),Cx_int(46),clk,reset,Cx_int(47)); CELL_48: ENTITY work.basic_cell(behave) PORT MAP(Ax(48),Bx_int(NUM_BITS-1),Cx_int(47),clk,reset,Cx_int(48)); CELL_49: ENTITY work.basic_cell(behave) PORT MAP(Ax(49),Bx_int(NUM_BITS-1),Cx_int(48),clk,reset,Cx_int(49)); CELL_50: ENTITY work.basic_cell(behave) PORT MAP(Ax(50),Bx_int(NUM_BITS-1),Cx_int(49),clk,reset,Cx_int(50)); CELL_51: ENTITY work.basic_cell(behave) PORT MAP(Ax(51),Bx_int(NUM_BITS-1),Cx_int(50),clk,reset,Cx_int(51)); CELL_52: ENTITY work.basic_cell(behave) PORT MAP(Ax(52),Bx_int(NUM_BITS-1),Cx_int(51),clk,reset,Cx_int(52)); CELL_53: ENTITY work.basic_cell(behave) PORT MAP(Ax(53),Bx_int(NUM_BITS-1),Cx_int(52),clk,reset,Cx_int(53)); CELL_54: ENTITY work.basic_cell(behave) PORT MAP(Ax(54),Bx_int(NUM_BITS-1),Cx_int(53),clk,reset,Cx_int(54)); CELL_55: ENTITY work.basic_cell(behave) PORT MAP(Ax(55),Bx_int(NUM_BITS-1),Cx_int(54),clk,reset,Cx_int(55)); CELL_56: ENTITY work.basic_cell(behave) PORT MAP(Ax(56),Bx_int(NUM_BITS-1),Cx_int(55),clk,reset,Cx_int(56)); CELL_57: ENTITY work.basic_cell(behave) PORT MAP(Ax(57),Bx_int(NUM_BITS-1),Cx_int(56),clk,reset,Cx_int(57)); CELL_58: ENTITY work.basic_cell(behave) PORT MAP(Ax(58),Bx_int(NUM_BITS-1),Cx_int(57),clk,reset,Cx_int(58)); CELL_59: ENTITY work.basic_cell(behave) PORT MAP(Ax(59),Bx_int(NUM_BITS-1),Cx_int(58),clk,reset,Cx_int(59)); CELL_60: ENTITY work.basic_cell(behave) PORT MAP(Ax(60),Bx_int(NUM_BITS-1),Cx_int(59),clk,reset,Cx_int(60)); CELL_61: ENTITY work.basic_cell(behave) PORT MAP(Ax(61),Bx_int(NUM_BITS-1),Cx_int(60),clk,reset,Cx_int(61)); CELL_62: ENTITY work.basic_cell(behave) PORT MAP(Ax(62),Bx_int(NUM_BITS-1),Cx_int(61),clk,reset,Cx_int(62)); CELL_63: ENTITY work.basic_cell(behave) PORT MAP(Ax(63),Bx_int(NUM_BITS-1),Cx_int(62),clk,reset,Cx_int(63)); CELL_64: ENTITY work.basic_cell(behave) PORT MAP(Ax(64),Bx_int(NUM_BITS-1),Cx_int(63),clk,reset,Cx_int(64)); CELL_65: ENTITY work.basic_cell(behave) PORT MAP(Ax(65),Bx_int(NUM_BITS-1),Cx_int(64),clk,reset,Cx_int(65)); CELL_66: ENTITY work.basic_cell(behave) PORT MAP(Ax(66),Bx_int(NUM_BITS-1),Cx_int(65),clk,reset,Cx_int(66)); CELL_67: ENTITY work.basic_cell(behave) PORT MAP(Ax(67),Bx_int(NUM_BITS-1),Cx_int(66),clk,reset,Cx_int(67)); CELL_68: ENTITY work.basic_cell(behave) PORT MAP(Ax(68),Bx_int(NUM_BITS-1),Cx_int(67),clk,reset,Cx_int(68)); CELL_69: ENTITY work.basic_cell(behave) PORT MAP(Ax(69),Bx_int(NUM_BITS-1),Cx_int(68),clk,reset,Cx_int(69)); CELL_70: ENTITY work.basic_cell(behave) PORT MAP(Ax(70),Bx_int(NUM_BITS-1),Cx_int(69),clk,reset,Cx_int(70)); CELL_71: ENTITY work.basic_cell(behave) PORT MAP(Ax(71),Bx_int(NUM_BITS-1),Cx_int(70),clk,reset,Cx_int(71)); CELL_72: ENTITY work.basic_cell(behave) PORT MAP(Ax(72),Bx_int(NUM_BITS-1),Cx_int(71),clk,reset,Cx_int(72)); CELL_73: ENTITY work.basic_cell(behave) PORT MAP(Ax(73),Bx_int(NUM_BITS-1),Cx_int(72),clk,reset,Cx_int(73)); CELL_74: ENTITY work.basic_cell(behave) PORT MAP(Ax(74),Bx_int(NUM_BITS-1),Cx_int(73),clk,reset,Cx_int(74)); CELL_75: ENTITY work.basic_cell(behave) PORT MAP(Ax(75),Bx_int(NUM_BITS-1),Cx_int(74),clk,reset,Cx_int(75)); CELL_76: ENTITY work.basic_cell(behave) PORT MAP(Ax(76),Bx_int(NUM_BITS-1),Cx_int(75),clk,reset,Cx_int(76)); CELL_77: ENTITY work.basic_cell(behave) PORT MAP(Ax(77),Bx_int(NUM_BITS-1),Cx_int(76),clk,reset,Cx_int(77)); CELL_78: ENTITY work.basic_cell(behave) PORT MAP(Ax(78),Bx_int(NUM_BITS-1),Cx_int(77),clk,reset,Cx_int(78)); CELL_79: ENTITY work.basic_cell(behave) PORT MAP(Ax(79),Bx_int(NUM_BITS-1),Cx_int(78),clk,reset,Cx_int(79)); CELL_80: ENTITY work.basic_cell(behave) PORT MAP(Ax(80),Bx_int(NUM_BITS-1),Cx_int(79),clk,reset,Cx_int(80)); CELL_81: ENTITY work.basic_cell(behave) PORT MAP(Ax(81),Bx_int(NUM_BITS-1),Cx_int(80),clk,reset,Cx_int(81)); CELL_82: ENTITY work.basic_cell(behave) PORT MAP(Ax(82),Bx_int(NUM_BITS-1),Cx_int(81),clk,reset,Cx_int(82)); CELL_83: ENTITY work.basic_cell(behave) PORT MAP(Ax(83),Bx_int(NUM_BITS-1),Cx_int(82),clk,reset,Cx_int(83)); CELL_84: ENTITY work.basic_cell(behave) PORT MAP(Ax(84),Bx_int(NUM_BITS-1),Cx_int(83),clk,reset,Cx_int(84)); CELL_85: ENTITY work.basic_cell(behave) PORT MAP(Ax(85),Bx_int(NUM_BITS-1),Cx_int(84),clk,reset,Cx_int(85)); CELL_86: ENTITY work.basic_cell(behave) PORT MAP(Ax(86),Bx_int(NUM_BITS-1),Cx_int(85),clk,reset,Cx_int(86)); CELL_87: ENTITY work.basic_cell(behave) PORT MAP(Ax(87),Bx_int(NUM_BITS-1),Cx_int(86),clk,reset,Cx_int(87)); CELL_88: ENTITY work.basic_cell(behave) PORT MAP(Ax(88),Bx_int(NUM_BITS-1),Cx_int(87),clk,reset,Cx_int(88)); CELL_89: ENTITY work.basic_cell(behave) PORT MAP(Ax(89),Bx_int(NUM_BITS-1),Cx_int(88),clk,reset,Cx_int(89)); CELL_90: ENTITY work.basic_cell(behave) PORT MAP(Ax(90),Bx_int(NUM_BITS-1),Cx_int(89),clk,reset,Cx_int(90)); CELL_91: ENTITY work.basic_cell(behave) PORT MAP(Ax(91),Bx_int(NUM_BITS-1),Cx_int(90),clk,reset,Cx_int(91)); CELL_92: ENTITY work.basic_cell(behave) PORT MAP(Ax(92),Bx_int(NUM_BITS-1),Cx_int(91),clk,reset,Cx_int(92)); CELL_93: ENTITY work.basic_cell(behave) PORT MAP(Ax(93),Bx_int(NUM_BITS-1),Cx_int(92),clk,reset,Cx_int(93)); CELL_94: ENTITY work.basic_cell(behave) PORT MAP(Ax(94),Bx_int(NUM_BITS-1),Cx_int(93),clk,reset,Cx_int(94)); CELL_95: ENTITY work.basic_cell(behave) PORT MAP(Ax(95),Bx_int(NUM_BITS-1),Cx_int(94),clk,reset,Cx_int(95)); CELL_96: ENTITY work.basic_cell(behave) PORT MAP(Ax(96),Bx_int(NUM_BITS-1),Cx_int(95),clk,reset,Cx_int(96)); CELL_97: ENTITY work.basic_cell(behave) PORT MAP(Ax(97),Bx_int(NUM_BITS-1),Cx_int(96),clk,reset,Cx_int(97)); CELL_98: ENTITY work.basic_cell(behave) PORT MAP(Ax(98),Bx_int(NUM_BITS-1),Cx_int(97),clk,reset,Cx_int(98)); CELL_99: ENTITY work.basic_cell(behave) PORT MAP(Ax(99),Bx_int(NUM_BITS-1),Cx_int(98),clk,reset,Cx_int(99)); CELL_100: ENTITY work.basic_cell(behave) PORT MAP(Ax(100),Bx_int(NUM_BITS-1),Cx_int(99),clk,reset,Cx_int(100)); CELL_101: ENTITY work.basic_cell(behave) PORT MAP(Ax(101),Bx_int(NUM_BITS-1),Cx_int(100),clk,reset,Cx_int(101)); CELL_102: ENTITY work.basic_cell(behave) PORT MAP(Ax(102),Bx_int(NUM_BITS-1),Cx_int(101),clk,reset,Cx_int(102)); CELL_103: ENTITY work.basic_cell(behave) PORT MAP(Ax(103),Bx_int(NUM_BITS-1),Cx_int(102),clk,reset,Cx_int(103)); CELL_104: ENTITY work.basic_cell(behave) PORT MAP(Ax(104),Bx_int(NUM_BITS-1),Cx_int(103),clk,reset,Cx_int(104)); CELL_105: ENTITY work.basic_cell(behave) PORT MAP(Ax(105),Bx_int(NUM_BITS-1),Cx_int(104),clk,reset,Cx_int(105)); CELL_106: ENTITY work.basic_cell(behave) PORT MAP(Ax(106),Bx_int(NUM_BITS-1),Cx_int(105),clk,reset,Cx_int(106)); CELL_107: ENTITY work.basic_cell(behave) PORT MAP(Ax(107),Bx_int(NUM_BITS-1),Cx_int(106),clk,reset,Cx_int(107)); CELL_108: ENTITY work.basic_cell(behave) PORT MAP(Ax(108),Bx_int(NUM_BITS-1),Cx_int(107),clk,reset,Cx_int(108)); CELL_109: ENTITY work.basic_cell(behave) PORT MAP(Ax(109),Bx_int(NUM_BITS-1),Cx_int(108),clk,reset,Cx_int(109)); CELL_110: ENTITY work.basic_cell(behave) PORT MAP(Ax(110),Bx_int(NUM_BITS-1),Cx_int(109),clk,reset,Cx_int(110)); CELL_111: ENTITY work.basic_cell(behave) PORT MAP(Ax(111),Bx_int(NUM_BITS-1),Cx_int(110),clk,reset,Cx_int(111)); CELL_112: ENTITY work.basic_cell(behave) PORT MAP(Ax(112),Bx_int(NUM_BITS-1),Cx_int(111),clk,reset,Cx_int(112)); CELL_113: ENTITY work.basic_cell(behave) PORT MAP(Ax(113),Bx_int(NUM_BITS-1),Cx_int(112),clk,reset,Cx_int(113)); CELL_114: ENTITY work.basic_cell(behave) PORT MAP(Ax(114),Bx_int(NUM_BITS-1),Cx_int(113),clk,reset,Cx_int(114)); CELL_115: ENTITY work.basic_cell(behave) PORT MAP(Ax(115),Bx_int(NUM_BITS-1),Cx_int(114),clk,reset,Cx_int(115)); CELL_116: ENTITY work.basic_cell(behave) PORT MAP(Ax(116),Bx_int(NUM_BITS-1),Cx_int(115),clk,reset,Cx_int(116)); CELL_117: ENTITY work.basic_cell(behave) PORT MAP(Ax(117),Bx_int(NUM_BITS-1),Cx_int(116),clk,reset,Cx_int(117)); CELL_118: ENTITY work.basic_cell(behave) PORT MAP(Ax(118),Bx_int(NUM_BITS-1),Cx_int(117),clk,reset,Cx_int(118)); CELL_119: ENTITY work.basic_cell(behave) PORT MAP(Ax(119),Bx_int(NUM_BITS-1),Cx_int(118),clk,reset,Cx_int(119)); CELL_120: ENTITY work.basic_cell(behave) PORT MAP(Ax(120),Bx_int(NUM_BITS-1),Cx_int(119),clk,reset,Cx_int(120)); CELL_121: ENTITY work.basic_cell(behave) PORT MAP(Ax(121),Bx_int(NUM_BITS-1),Cx_int(120),clk,reset,Cx_int(121)); CELL_122: ENTITY work.basic_cell(behave) PORT MAP(Ax(122),Bx_int(NUM_BITS-1),Cx_int(121),clk,reset,Cx_int(122)); CELL_123: ENTITY work.basic_cell(behave) PORT MAP(Ax(123),Bx_int(NUM_BITS-1),Cx_int(122),clk,reset,Cx_int(123)); CELL_124: ENTITY work.basic_cell(behave) PORT MAP(Ax(124),Bx_int(NUM_BITS-1),Cx_int(123),clk,reset,Cx_int(124)); CELL_125: ENTITY work.basic_cell(behave) PORT MAP(Ax(125),Bx_int(NUM_BITS-1),Cx_int(124),clk,reset,Cx_int(125)); CELL_126: ENTITY work.basic_cell(behave) PORT MAP(Ax(126),Bx_int(NUM_BITS-1),Cx_int(125),clk,reset,Cx_int(126)); CELL_127: ENTITY work.basic_cell(behave) PORT MAP(Ax(127),Bx_int(NUM_BITS-1),Cx_int(126),clk,reset,Cx_int(127)); CELL_128: ENTITY work.basic_cell(behave) PORT MAP(Ax(128),Bx_int(NUM_BITS-1),Cx_int(127),clk,reset,Cx_int(128)); CELL_129: ENTITY work.basic_cell(behave) PORT MAP(Ax(129),Bx_int(NUM_BITS-1),Cx_int(128),clk,reset,Cx_int(129)); CELL_130: ENTITY work.basic_cell(behave) PORT MAP(Ax(130),Bx_int(NUM_BITS-1),Cx_int(129),clk,reset,Cx_int(130)); FSM_MUL: process (CLK) Begin if CLK'event and CLK = '1' then if Reset = '1' then counter <= "10000010"; -- m-1 value, in this case, it is 112, be sure to set the correct value bx_int <= bx; cx <= (others => '0'); Done <= '0'; CurrentState <= MUL_STATE; else case CurrentState is when MUL_STATE => -- processes a bit of bx counter <= counter - 1; if counter = "0000000" then -- The done signal is asserted at the same time that the result is computed. CurrentState <= END_STATE; else bx_int <= bx_shift; end if; when END_STATE => Cx <= Cx_int; Done <= '1'; CurrentState <= NOTHING; when others => null; end case; end if; end if; end process; end behave;

-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Thomas B. Preusser -- Martin Zabel -- Patrick Lehmann -- -- Package: Project specific configuration. -- -- Description: -- ------------------------------------ -- Configuration file for a Xilinx Atlys board. -- -- -- License: -- ============================================================================= -- Copyright 2007-2016 Technische Universitaet Dresden - Germany, -- Chair for VLSI-Design, Diagnostics and Architecture -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= -- -- package my_config is -- Change these lines to setup configuration. constant MY_BOARD : string := "Atlys"; -- Digilent Atlys - Xilinx Spartan-6: XC6SLX45 constant MY_DEVICE : string := "None"; -- infer from MY_BOARD -- For internal use only constant MY_VERBOSE : boolean := FALSE; end package;

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ledController IS PORT( clk : in std_logic; rst : in std_logic; bus_addr : in std_LOGIC_VECTOR(15 downto 0); bus_dq : in STD_LOGIC_VECTOR(15 DOWNTO 0); bus_req : in std_LOGIC; bus_rw : in std_LOGIC; q : out STD_LOGIC_VECTOR(15 downto 0) ); END ledController; ARCHITECTURE behavioral OF ledController IS SIGNAL data : STD_LOGIC_VECTOR(15 DOWNTO 0) := x"0000"; BEGIN process(rst , clk) begin if(rst = '1') then data <= x"0000"; elsif(rising_edge(clk)) then if(bus_req = '1' and bus_rw = '1' and bus_addr= x"978") then data <= bus_dq; end if; q <= data; end if; end process; END behavioral;

-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc2215.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b06x00p01n01i02215ent IS END c07s02b06x00p01n01i02215ent; ARCHITECTURE c07s02b06x00p01n01i02215arch OF c07s02b06x00p01n01i02215ent IS BEGIN TESTING: PROCESS -- All different non-numeric type declarations. -- Local declarations. variable CHARV : CHARACTER := '0'; variable k : integer; BEGIN k := NULL mod CHARV; assert FALSE report "***FAILED TEST: c07s02b06x00p01n01i02215 - Operators mod and rem are predefined for any integer type only." severity ERROR; wait; END PROCESS TESTING; END c07s02b06x00p01n01i02215arch;

-- Twofish_ecb_vt_testbench_256bits.vhd -- Copyright (C) 2006 Spyros Ninos -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this library; see the file COPYING. If not, write to: -- -- Free Software Foundation -- 59 Temple Place - Suite 330 -- Boston, MA 02111-1307, USA. -- -- description : this file is the testbench for the VARIABLE TEXT KAT of the twofish cipher with 256 bit key -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_textio.all; use ieee.std_logic_arith.all; use std.textio.all; entity vt_testbench256 is end vt_testbench256; architecture vt_encryption256_testbench_arch of vt_testbench256 is component reg128 port ( in_reg128 : in std_logic_vector(127 downto 0); out_reg128 : out std_logic_vector(127 downto 0); enable_reg128, reset_reg128, clk_reg128 : in std_logic ); end component; component twofish_keysched256 port ( odd_in_tk256, even_in_tk256 : in std_logic_vector(7 downto 0); in_key_tk256 : in std_logic_vector(255 downto 0); out_key_up_tk256, out_key_down_tk256 : out std_logic_vector(31 downto 0) ); end component; component twofish_whit_keysched256 port ( in_key_twk256 : in std_logic_vector(255 downto 0); out_K0_twk256, out_K1_twk256, out_K2_twk256, out_K3_twk256, out_K4_twk256, out_K5_twk256, out_K6_twk256, out_K7_twk256 : out std_logic_vector(31 downto 0) ); end component; component twofish_encryption_round256 port ( in1_ter256, in2_ter256, in3_ter256, in4_ter256, in_Sfirst_ter256, in_Ssecond_ter256, in_Sthird_ter256, in_Sfourth_ter256, in_key_up_ter256, in_key_down_ter256 : in std_logic_vector(31 downto 0); out1_ter256, out2_ter256, out3_ter256, out4_ter256 : out std_logic_vector(31 downto 0) ); end component; component twofish_data_input port ( in_tdi : in std_logic_vector(127 downto 0); out_tdi : out std_logic_vector(127 downto 0) ); end component; component twofish_data_output port ( in_tdo : in std_logic_vector(127 downto 0); out_tdo : out std_logic_vector(127 downto 0) ); end component; component demux128 port ( in_demux128 : in std_logic_vector(127 downto 0); out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0); selection_demux128 : in std_logic ); end component; component mux128 port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0); selection_mux128 : in std_logic; out_mux128 : out std_logic_vector(127 downto 0) ); end component; component twofish_S256 port ( in_key_ts256 : in std_logic_vector(255 downto 0); out_Sfirst_ts256, out_Ssecond_ts256, out_Sthird_ts256, out_Sfourth_ts256 : out std_logic_vector(31 downto 0) ); end component; FILE input_file : text is in "twofish_ecb_vt_testvalues_256bits.txt"; FILE output_file : text is out "twofish_ecb_vt_256bits_results.txt"; -- we create the functions that transform a number to text -- transforming a signle digit to a character function digit_to_char(number : integer range 0 to 9) return character is begin case number is when 0 => return '0'; when 1 => return '1'; when 2 => return '2'; when 3 => return '3'; when 4 => return '4'; when 5 => return '5'; when 6 => return '6'; when 7 => return '7'; when 8 => return '8'; when 9 => return '9'; end case; end; -- transforming multi-digit number to text function to_text(int_number : integer range 1 to 256) return string is variable our_text : string (1 to 3) := (others => ' '); variable hundreds, tens, ones : integer range 0 to 9; begin ones := int_number mod 10; tens := ((int_number mod 100) - ones) / 10; hundreds := (int_number - (int_number mod 100)) / 100; our_text(1) := digit_to_char(hundreds); our_text(2) := digit_to_char(tens); our_text(3) := digit_to_char(ones); return our_text; end; signal odd_number, even_number : std_logic_vector(7 downto 0); signal input_data, output_data, to_encr_reg128, from_tdi_to_xors, to_output_whit_xors, from_xors_to_tdo, to_mux, to_demux, from_input_whit_xors, to_round, to_input_mux : std_logic_vector(127 downto 0) ; signal twofish_key : std_logic_vector(255 downto 0); signal key_up, key_down, Sfirst, Ssecond, Sthird, Sfourth, from_xor0, from_xor1, from_xor2, from_xor3, K0,K1,K2,K3, K4,K5,K6,K7 : std_logic_vector(31 downto 0); signal clk : std_logic := '0'; signal mux_selection : std_logic := '0'; signal demux_selection: std_logic := '0'; signal enable_encr_reg : std_logic := '0'; signal reset : std_logic := '0'; signal enable_round_reg : std_logic := '0'; -- begin the testbench arch description begin -- getting data to encrypt data_input: twofish_data_input port map ( in_tdi => input_data, out_tdi => from_tdi_to_xors ); -- producing whitening keys K0..7 the_whitening_step: twofish_whit_keysched256 port map ( in_key_twk256 => twofish_key, out_K0_twk256 => K0, out_K1_twk256 => K1, out_K2_twk256 => K2, out_K3_twk256 => K3, out_K4_twk256 => K4, out_K5_twk256 => K5, out_K6_twk256 => K6, out_K7_twk256 => K7 ); -- performing the input whitening XORs from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96); from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64); from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32); from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0); from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3; round_reg: reg128 port map ( in_reg128 => from_input_whit_xors, out_reg128 => to_input_mux, enable_reg128 => enable_round_reg, reset_reg128 => reset, clk_reg128 => clk ); input_mux: mux128 port map ( in1_mux128 => to_input_mux, in2_mux128 => to_mux, out_mux128 => to_round, selection_mux128 => mux_selection ); -- creating a round the_keysched_of_the_round: twofish_keysched256 port map ( odd_in_tk256 => odd_number, even_in_tk256 => even_number, in_key_tk256 => twofish_key, out_key_up_tk256 => key_up, out_key_down_tk256 => key_down ); producing_the_Skeys: twofish_S256 port map ( in_key_ts256 => twofish_key, out_Sfirst_ts256 => Sfirst, out_Ssecond_ts256 => Ssecond, out_Sthird_ts256 => Sthird, out_Sfourth_ts256 => Sfourth ); the_encryption_circuit: twofish_encryption_round256 port map ( in1_ter256 => to_round(127 downto 96), in2_ter256 => to_round(95 downto 64), in3_ter256 => to_round(63 downto 32), in4_ter256 => to_round(31 downto 0), in_Sfirst_ter256 => Sfirst, in_Ssecond_ter256 => Ssecond, in_Sthird_ter256 => Sthird, in_Sfourth_ter256 => Sfourth, in_key_up_ter256 => key_up, in_key_down_ter256 => key_down, out1_ter256 => to_encr_reg128(127 downto 96), out2_ter256 => to_encr_reg128(95 downto 64), out3_ter256 => to_encr_reg128(63 downto 32), out4_ter256 => to_encr_reg128(31 downto 0) ); encr_reg: reg128 port map ( in_reg128 => to_encr_reg128, out_reg128 => to_demux, enable_reg128 => enable_encr_reg, reset_reg128 => reset, clk_reg128 => clk ); output_demux: demux128 port map ( in_demux128 => to_demux, out1_demux128 => to_output_whit_xors, out2_demux128 => to_mux, selection_demux128 => demux_selection ); -- don't forget the last swap !!! from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32); from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0); from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96); from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64); taking_the_output: twofish_data_output port map ( in_tdo => from_xors_to_tdo, out_tdo => output_data ); -- we create the clock clk <= not clk after 50 ns; -- period 100 ns vt_proc: process variable pt_f, -- plaintext from file ct_f : line; -- ciphertext from file variable pt_v, -- plaintext vector ct_v : std_logic_vector(127 downto 0); -- ciphertext vector variable counter : integer range 1 to 257 := 1; -- counts the encryptions variable round : integer range 1 to 16 := 1; -- holds the rounds of encryption begin -- key stays fixed to zero twofish_key <= (others => '0'); while not endfile(input_file) loop readline(input_file, pt_f); readline(input_file,ct_f); hread(pt_f,pt_v); hread(ct_f,ct_v); input_data <= pt_v; wait for 25 ns; reset <= '1'; wait for 50 ns; reset <= '0'; mux_selection <= '0'; demux_selection <= '1'; enable_encr_reg <= '0'; enable_round_reg <= '0'; wait for 50 ns; enable_round_reg <= '1'; wait for 50 ns; enable_round_reg <= '0'; -- the first round even_number <= "00001000"; -- 8 odd_number <= "00001001"; -- 9 wait for 50 ns; enable_encr_reg <= '1'; wait for 50 ns; enable_encr_reg <= '0'; demux_selection <= '1'; mux_selection <= '1'; -- the rest 15 rounds for round in 1 to 15 loop even_number <= conv_std_logic_vector(((round*2)+8), 8); odd_number <= conv_std_logic_vector(((round*2)+9), 8); wait for 50 ns; enable_encr_reg <= '1'; wait for 50 ns; enable_encr_reg <= '0'; end loop; -- taking final results demux_selection <= '0'; wait for 25 ns; assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure; assert (ct_v /= output_data) report "Encryption I=" & to_text(counter) &" OK" severity note; counter := counter+1; hwrite(ct_f,output_data); hwrite(pt_f,pt_v); writeline(output_file,pt_f); writeline(output_file,ct_f); end loop; assert false report "***** Variable Text Known Answer Test with 256 bits key size ended succesfully! :) *****" severity failure; end process vt_proc; end vt_encryption256_testbench_arch;

--***************************************************************************** -- @Copyright All rights reserved. -- Module name : frontend -- Call by : -- Description : -- IC : -- Version : 1.0 -- Note: : -- Author : QIU Weibao -- Date : 2013.08.06 -- Update : -- -- --***************************************************************************** library IEEE; use IEEE.std_logic_1164.ALL; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity frontend is port ( I_reset_n : in std_logic; I_sys_clk : in std_logic; I_scan_trig : in std_logic; --scan triger I_reg_csr : in std_logic_vector(31 downto 0); --ADC I_adc_d : in std_logic_vector(11 downto 0); I_adc_or : in std_logic; I_f2pc_full : in std_logic; O_pixel_symbol : out std_logic; O_pixel_en : out std_logic; O_pixel_data : out std_logic_vector(15 downto 0); O_pulse_trig : out std_logic; O_shake_start : out std_logic ); end frontend; architecture rtl of frontend is --component fir_band_pass is --PORT --( -- clk : IN STD_LOGIC; -- reset_n : IN STD_LOGIC; -- ast_sink_data : IN STD_LOGIC_VECTOR (11 DOWNTO 0); -- ast_sink_valid : IN STD_LOGIC; -- ast_source_ready: IN STD_LOGIC; -- ast_sink_error : IN STD_LOGIC_VECTOR (1 DOWNTO 0); -- ast_source_data : OUT STD_LOGIC_VECTOR (15 DOWNTO 0); -- ast_sink_ready : OUT STD_LOGIC; -- ast_source_valid: OUT STD_LOGIC; -- ast_source_error: OUT STD_LOGIC_VECTOR (1 DOWNTO 0) --); --end component; component analytic_filter_h_a1 is -- component hilbert tansform generic( input_data_width : integer := 16; output_data_width : integer := 16; filter_delay_in_clks : integer := 7 --delay of hilbert filter (including pipeline delay) ); port( clk_i : in std_logic; rst_i : in std_logic; --high level reset data_str_i : in std_logic; --hilbert tranform enable data_i : in std_logic_vector(input_data_width-1 downto 0); data_i_o : out std_logic_vector(output_data_width-1 downto 0); data_q_o : out std_logic_vector(output_data_width-1 downto 0); data_str_o : out std_logic ); end component; component r2p_corproc port( clk : in std_logic; ena : in std_logic; Xin : in STD_LOGIC_VECTOR(15 downto 0); Yin : in STD_LOGIC_VECTOR(15 downto 0); Rout : out STD_LOGIC_VECTOR(19 downto 0); Aout : out STD_LOGIC_VECTOR(19 downto 0) ); end component; --constant C_FILTER_DELAY : integer := 17; --filter delay 15, adc buffer 2 constant C_CORDIC_DELAY : integer := 1000;--20; signal s_scan_trig : std_logic:='0'; signal s_work_start : std_logic; signal S_fir_sink_valid : std_logic; --filter input data valid signal S_fir_sink_ready : std_logic; --filter is able to accept data signal S_fir_source_valid : std_logic; --assert by fir filter when there is valid data to output signal S_fir_source_error : std_logic_vector(1 downto 0); --"00" no error signal S_fir_source_data : std_logic_vector(15 downto 0); --filter output data signal S_hilbert_reset : std_logic; --high level reset signal S_hilbert_data_str_i : std_logic; signal S_hilbert_data_io : std_logic_vector(15 downto 0); signal S_hilbert_data_qo : std_logic_vector(15 downto 0); signal S_hilbert_data_str_o : std_logic; signal S_cordic_rout : std_logic_vector(19 downto 0):=x"00000"; signal S_cordic_aout : std_logic_vector(19 downto 0); signal S_ad_buf : std_logic_vector(11 downto 0); signal S_ocnt : std_logic_vector(19 downto 0):="00000000000000000000"; signal S_state : std_logic_vector(2 downto 0); signal s_oen : std_logic; signal s_den : std_logic; signal s_scan_start : std_logic; signal S_scan_state : std_logic_vector(1 downto 0); signal s_work_start_buf : std_logic; signal S_line_num : std_logic_vector(9 downto 0); constant C_line_delay : integer := 17000;--4700;--181250;--40000; signal S_line_delay : std_logic_vector(19 downto 0):="00000000000000000000"; signal S_hilbert_data_i_0 : std_logic_vector(15 downto 0); signal S_hilbert_data_i_1 : std_logic_vector(15 downto 0); signal S_hilbert_data_i : std_logic_vector(15 downto 0); signal S_hilbert_data_i_temp : std_logic_vector(15 downto 0); signal S_pulse_trig : std_logic; signal S_data_type : std_logic_vector(1 downto 0); signal S_delay_cnt : std_logic_vector(20 downto 0); begin s_work_start <= '1';--I_reg_csr(0); S_hilbert_data_i_temp <= I_adc_d(11) & I_adc_d(11) & I_adc_d(11) & I_adc_d(11) & I_adc_d; O_pixel_symbol <= s_den; O_pixel_data <= S_hilbert_data_i; -- 将AD9230采集到的数据未经任何处理，直接上传上位机。 O_pixel_en <= s_oen; O_pulse_trig <= S_pulse_trig; --------------------RF DATA-------------------- S_data_type <= "01";--I_reg_csr(5 downto 4); process(I_sys_clk, I_reset_n) -- 打拍，把AD9230的数据读进来。 begin if (I_reset_n='0') then S_hilbert_data_i_0 <= (others=>'0'); S_hilbert_data_i_1 <= (others=>'0'); S_hilbert_data_i <= (others=>'0'); elsif(I_sys_clk'event and I_sys_clk='1') then S_hilbert_data_i_0 <= S_hilbert_data_i_temp; S_hilbert_data_i_1 <= S_hilbert_data_i_0; S_hilbert_data_i <= S_hilbert_data_i_1; end if; end process; process(I_sys_clk,I_reset_n) begin if (I_reset_n = '0') then S_state <= (others=>'0'); S_ocnt <= (others=>'0'); s_oen <= '0'; s_den <= '0'; S_pulse_trig <= '0'; S_hilbert_reset <= '1'; S_hilbert_data_str_i <= '0'; S_delay_cnt <= (others=>'0'); S_line_num <= (others => '0'); S_line_delay <= (others => '0'); elsif rising_edge(I_sys_clk) then s_work_start_buf <= s_work_start; s_scan_trig <= I_scan_trig; S_hilbert_data_str_i <= '1'; S_hilbert_reset <= '0'; case S_state is when "000" => -- 等待开始。 if (s_scan_trig = '0' and I_scan_trig = '1' and s_work_start_buf = '1')then S_state <= "001"; s_oen <= '1'; S_line_num <= (others => '0'); S_line_delay <= (others => '0'); else S_ocnt <= (others=>'0'); s_oen <= '0'; s_den <= '0'; S_line_num <= (others => '0'); S_line_delay <= (others => '0'); S_pulse_trig <= '0'; end if; when "001" => if S_delay_cnt >= 1000 then -- 丢掉测试前的1000个点，此处没特殊意义，调试遗留，不影响使用，可删除。 S_state <= "010"; S_delay_cnt <= (others=>'0'); else S_delay_cnt <= S_delay_cnt +1; end if; when "010" => S_pulse_trig <= '1'; -- 超声发射使能有效，开始超声激励。 --start trans-- S_delay_cnt <= (others=>'0'); if (S_ocnt >= C_CORDIC_DELAY) then -- 每条线丢掉前1000个点，因为离表面太近，数据不参与计算。 --recive delay time-- S_state <= "011"; s_den <= '1'; -- start receive -- S_ocnt <= (others=>'0'); else S_ocnt <= S_ocnt + 1; end if; when "011" => if (S_ocnt >= 4095) then -- 每条线采集4096点 S_state <= "100"; S_ocnt <= (others=>'0'); s_den <= '0'; -- stop receive-- S_line_num <= S_line_num + 1; S_pulse_trig <= '0'; -- stop trans --- else S_ocnt <= S_ocnt + 1; end if; S_line_delay <= S_line_delay + 1; when "100" => if S_line_num > 299 then -- 采集300条线 S_state <= "101"; else if S_line_delay > C_line_delay then S_state <= "010"; S_line_delay <= (others => '0'); else S_line_delay <= S_line_delay + 1; end if; end if; when "101" => S_state <= (others=>'0'); S_ocnt <= (others=>'0'); s_oen <= '0'; s_den <= '0'; S_pulse_trig <= '0'; S_line_num <= (others => '0'); when others=> S_state <= (others=>'0'); S_ocnt <= (others=>'0'); s_oen <= '0'; s_den <= '0'; S_pulse_trig <= '0'; S_line_num <= (others => '0'); end case ; end if; if S_line_num > 33 then -- 在采集第33条线时，电磁铁开始振动，此数值需结合算法修改，不能随意变动。 O_shake_start <= '1'; else O_shake_start <= '0'; end if; end process; U2_analytic_filter_h_a1_inst:analytic_filter_h_a1 -- 未使用 generic map( input_data_width => 16, output_data_width => 16, filter_delay_in_clks => 7 --delay of hilbert filter (including pipeline delay) ) port map( clk_i => I_sys_clk,--I_sys_clk, rst_i => S_hilbert_reset, --high reset data_str_i => S_hilbert_data_str_i, data_i => S_hilbert_data_i,--S_fir_source_data, data_i_o => S_hilbert_data_io, data_q_o => S_hilbert_data_qo, data_str_o => S_hilbert_data_str_o -- delay 7 clock than data_str_i ); U6_r2p_corproc_inst:r2p_corproc -- 未使用 port map ( clk => I_sys_clk,--I_sys_clk, ena => '1', Xin => S_hilbert_data_io, Yin => S_hilbert_data_qo, Rout => S_cordic_rout, Aout => S_cordic_aout ); -- end rtl;

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use std.textio.all; use ieee.std_logic_textio.all; -- Instruction memory for DLX -- Memory filled by a process which reads from a file -- file name is "test.asm.mem" entity IRAM is generic ( RAM_DEPTH : integer := 48; I_SIZE : integer := 32 ); port ( Rst : in std_logic; Addr : in std_logic_vector(I_SIZE - 1 downto 0); Dout : out std_logic_vector(I_SIZE - 1 downto 0) ); end IRAM; architecture IRam_Bhe of IRAM is type RAMtype is array (0 to RAM_DEPTH - 1) of integer;-- std_logic_vector(I_SIZE - 1 downto 0); signal IRAM_mem : RAMtype; begin -- IRam_Bhe Dout <= conv_std_logic_vector(IRAM_mem(conv_integer(unsigned(Addr))),I_SIZE); -- purpose: This process is in charge of filling the Instruction RAM with the firmware -- type : combinational -- inputs : Rst -- outputs: IRAM_mem FILL_MEM_P: process (Rst) file mem_fp: text; variable file_line : line; variable index : integer := 0; variable tmp_data_u : std_logic_vector(I_SIZE-1 downto 0); begin -- process FILL_MEM_P if (Rst = '0') then file_open(mem_fp,"test.asm.mem",READ_MODE); while (not endfile(mem_fp)) loop readline(mem_fp,file_line); hread(file_line,tmp_data_u); IRAM_mem(index) <= conv_integer(unsigned(tmp_data_u)); index := index + 1; end loop; end if; end process FILL_MEM_P; end IRam_Bhe;

package rectype is type r1 is record x : integer; end record; end package; entity e is end entity; use work.rectype.all; architecture a of e is type r2 is record x : r1; end record; signal s : r2; begin p1: process is type r3 is record x : r2; end record; variable v : r3; begin v.x := s; wait; end process; end architecture;

------------------------------------------------------------------------------- -- Title : Clock -- Project : ------------------------------------------------------------------------------- -- File : bcdtime.vhd -- Author : Daniel Sun <[email protected]> -- Company : -- Created : 2016-05-04 -- Last update: 2016-08-22 -- Platform : -- Standard : VHDL'93 ------------------------------------------------------------------------------- -- Description: BCD Time counters ms resolution ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-05-04 1.0 dcsun88osh Created ------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_ARITH.ALL; library work; use work.types_pkg.all; entity bcdtime is port ( rst_n : in std_logic; clk : in std_logic; tsc_1pps : in std_logic; tsc_1ppms : in std_logic; set : in std_logic; set_time : in time_ty; cur_time : out time_ty ); end bcdtime; architecture rtl of bcdtime is SIGNAL dig_1ms : std_logic_vector(3 downto 0); SIGNAL dig_10ms : std_logic_vector(3 downto 0); SIGNAL dig_100ms : std_logic_vector(3 downto 0); SIGNAL dig_1s : std_logic_vector(3 downto 0); SIGNAL dig_10s : std_logic_vector(3 downto 0); SIGNAL dig_1m : std_logic_vector(3 downto 0); SIGNAL dig_10m : std_logic_vector(3 downto 0); SIGNAL dig_1h : std_logic_vector(3 downto 0); SIGNAL dig_10h : std_logic_vector(3 downto 0); signal ms_carry : std_logic; signal s_carry : std_logic; signal m_carry : std_logic; signal h_carry : std_logic; signal sync_time : std_logic; begin -- Set latch time_set: process (rst_n, clk) is begin if (rst_n = '0') then sync_time <= '0'; elsif (clk'event and clk = '1') then if (set = '1') then sync_time <= '1'; elsif (tsc_1pps = '1') then sync_time <= '0'; end if; end if; end process; -- Clock ms counters 0-999 time_ms: process (rst_n, clk) is begin if (rst_n = '0') then dig_1ms <= (others => '0'); dig_10ms <= (others => '0'); dig_100ms <= (others => '0'); ms_carry <= '0'; elsif (clk'event and clk = '1') then if (sync_time = '1' and tsc_1pps = '1') then dig_1ms <= (others => '0'); dig_1ms(1) <= '1'; -- Set 2ms ahead for display pipe delay dig_10ms <= (others => '0'); dig_100ms <= (others => '0'); ms_carry <= '0'; elsif (tsc_1ppms = '1') then if (dig_1ms = 9) then dig_1ms <= (others => '0'); else dig_1ms <= dig_1ms + 1; end if; if (dig_1ms = 9) then if (dig_10ms = 9) then dig_10ms <= (others => '0'); else dig_10ms <= dig_10ms + 1; end if; end if; if (dig_1ms = 9 and dig_10ms = 9) then if (dig_100ms = 9) then dig_100ms <= (others => '0'); else dig_100ms <= dig_100ms + 1; end if; end if; if (dig_1ms = 8 and dig_10ms = 9 and dig_100ms = 9) then ms_carry <= '1'; else ms_carry <= '0'; end if; end if; end if; end process; -- Clock second counters 0 - 59 time_s: process (rst_n, clk) is begin if (rst_n = '0') then dig_1s <= (others => '0'); dig_10s <= (others => '0'); s_carry <= '0'; elsif (clk'event and clk = '1') then if (sync_time = '1' and tsc_1pps = '1') then dig_1s <= set_time.t_1s; dig_10s <= set_time.t_10s; s_carry <= '0'; elsif (tsc_1ppms = '1' and ms_carry = '1') then if (dig_1s = 9) then dig_1s <= (others => '0'); else dig_1s <= dig_1s + 1; end if; if (dig_1s = 9) then if (dig_10s = 5) then dig_10s <= (others => '0'); else dig_10s <= dig_10s + 1; end if; end if; if (dig_1s = 8 and dig_10s = 5) then s_carry <= '1'; else s_carry <= '0'; end if; end if; end if; end process; -- Clock minute counters 0 - 59 time_m: process (rst_n, clk) is begin if (rst_n = '0') then dig_1m <= (others => '0'); dig_10m <= (others => '0'); m_carry <= '0'; elsif (clk'event and clk = '1') then if (sync_time = '1' and tsc_1pps = '1') then dig_1m <= set_time.t_1m; dig_10m <= set_time.t_10m; m_carry <= '0'; elsif (tsc_1ppms = '1' and s_carry = '1' and ms_carry ='1') then if (dig_1m = 9) then dig_1m <= (others => '0'); else dig_1m <= dig_1m + 1; end if; if (dig_1m = 9) then if (dig_10m = 5) then dig_10m <= (others => '0'); else dig_10m <= dig_10m + 1; end if; end if; if (dig_1m = 8 and dig_10m = 5) then m_carry <= '1'; else m_carry <= '0'; end if; end if; end if; end process; -- Clock hour counters 0 - 23 time_h: process (rst_n, clk) is begin if (rst_n = '0') then dig_1h <= (others => '0'); dig_10h <= (others => '0'); h_carry <= '0'; elsif (clk'event and clk = '1') then if (sync_time = '1' and tsc_1pps = '1') then dig_1h <= set_time.t_1h; dig_10h <= set_time.t_10h; h_carry <= '0'; elsif (tsc_1ppms = '1' and m_carry = '1' and s_carry = '1' and ms_carry = '1') then if (dig_1h = 9 or (dig_1h = 3 and dig_10h = 2)) then dig_1h <= (others => '0'); else dig_1h <= dig_1h + 1; end if; if (dig_1h = 9 or (dig_1h = 3 and dig_10h = 2)) then if (dig_1h = 3 and dig_10h = 2) then dig_10h <= (others => '0'); else dig_10h <= dig_10h + 1; end if; end if; if (dig_1h = 2 and dig_10h = 2) then h_carry <= '1'; else h_carry <= '0'; end if; end if; end if; end process; cur_time.t_1ms <= dig_1ms; cur_time.t_10ms <= dig_10ms; cur_time.t_100ms <= dig_100ms; cur_time.t_1s <= dig_1s; cur_time.t_10s <= dig_10s; cur_time.t_1m <= dig_1m; cur_time.t_10m <= dig_10m; cur_time.t_1h <= dig_1h; cur_time.t_10h <= dig_10h; end rtl;