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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:10:50 03/29/2014
-- Design Name:
-- Module Name: ramlut - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ramlut is
generic(
sine_length_bits: integer := 10
);
port(
x_in: in std_logic_vector(sine_length_bits-1 downto 0);
sine_out: out std_logic_vector(11 downto 0); -- 12 bit output for DAC
clk: in std_logic
);
end ramlut;
architecture Behavioral of ramlut is
type sine_mem_type is array (0 to (2**sine_length_bits) - 1) of unsigned(11 downto 0);
function initialize_ram return sine_mem_type is
variable temp_mem: sine_mem_type;
constant x_scale: real := 0.000976;
constant y_adjust: real := 1.0;
constant y_scale: real := 2047.0;
begin
for i in 0 to (2**sine_length_bits) - 1 loop
temp_mem(i) := to_unsigned(integer((sin(real(i) * 2.0 * MATH_PI * x_scale) + y_adjust) * y_scale),12);
end loop;
return temp_mem;
end;
constant sine_mem: sine_mem_type := initialize_ram;
begin
process(clk)
begin
if(rising_edge(clk)) then
sine_out <= std_logic_vector(sine_mem(to_integer(unsigned(x_in))));
end if;
end process;
end Behavioral;
|
-- Some comment
entity FIFO is
end entity;
library ieee;
entity FIFO is
end entity;
library ieee;
-- First Comment
-- Second Comment
-- Third Comment
entity fifo is end entity;
library ieee;
-- First Comment
-- Second Comment
-- Third Comment
entity fifo is end entity;
entity fifo is end entity;
|
----- Libraries------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----- Entity ------
entity Alarm is
port( bin_min1, bin_min10, bin_hrs1, bin_hrs10 : in std_logic_vector(3 downto 0);
time_alarm : out std_logic_vector(15 downto 0)
);
end Alarm;
-----Architecture-----
architecture Alerter of Alarm is
begin
time_alarm <= bin_hrs10 & bin_hrs1 & bin_min10 & bin_min1;
end Alerter; |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:43:39 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_xbar_0/system_xbar_0_stub.vhdl
-- Design : system_xbar_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_xbar_0 is
Port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 255 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 255 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end system_xbar_0;
architecture stub of system_xbar_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awid[1:0],s_axi_awaddr[63:0],s_axi_awlen[15:0],s_axi_awsize[5:0],s_axi_awburst[3:0],s_axi_awlock[1:0],s_axi_awcache[7:0],s_axi_awprot[5:0],s_axi_awqos[7:0],s_axi_awvalid[1:0],s_axi_awready[1:0],s_axi_wdata[255:0],s_axi_wstrb[31:0],s_axi_wlast[1:0],s_axi_wvalid[1:0],s_axi_wready[1:0],s_axi_bid[1:0],s_axi_bresp[3:0],s_axi_bvalid[1:0],s_axi_bready[1:0],s_axi_arid[1:0],s_axi_araddr[63:0],s_axi_arlen[15:0],s_axi_arsize[5:0],s_axi_arburst[3:0],s_axi_arlock[1:0],s_axi_arcache[7:0],s_axi_arprot[5:0],s_axi_arqos[7:0],s_axi_arvalid[1:0],s_axi_arready[1:0],s_axi_rid[1:0],s_axi_rdata[255:0],s_axi_rresp[3:0],s_axi_rlast[1:0],s_axi_rvalid[1:0],s_axi_rready[1:0],m_axi_awid[0:0],m_axi_awaddr[31:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid[0:0],m_axi_awready[0:0],m_axi_wdata[127:0],m_axi_wstrb[15:0],m_axi_wlast[0:0],m_axi_wvalid[0:0],m_axi_wready[0:0],m_axi_bid[0:0],m_axi_bresp[1:0],m_axi_bvalid[0:0],m_axi_bready[0:0],m_axi_arid[0:0],m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid[0:0],m_axi_arready[0:0],m_axi_rid[0:0],m_axi_rdata[127:0],m_axi_rresp[1:0],m_axi_rlast[0:0],m_axi_rvalid[0:0],m_axi_rready[0:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4";
begin
end;
|
--
-- Copyright (C) 2014 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_32to8 is
port(
-- System clock & reset
clk_in : in std_logic;
reset_in : in std_logic;
-- 32-bit data coming in
data32_in : in std_logic_vector(31 downto 0);
valid32_in : in std_logic;
ready32_out : out std_logic;
-- 8-bit data going out
data8_out : out std_logic_vector(7 downto 0);
valid8_out : out std_logic;
ready8_in : in std_logic
);
end entity;
architecture rtl of conv_32to8 is
type StateType is (
S_WRITE0,
S_WRITE1,
S_WRITE2,
S_WRITE3
);
signal state : StateType := S_WRITE0;
signal state_next : StateType;
signal wip : std_logic_vector(23 downto 0) := (others => '0');
signal wip_next : std_logic_vector(23 downto 0);
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
state <= S_WRITE0;
wip <= (others => '0');
else
state <= state_next;
wip <= wip_next;
end if;
end if;
end process;
-- Next state logic
process(state, wip, data32_in, valid32_in, ready8_in)
begin
state_next <= state;
valid8_out <= '0';
wip_next <= wip;
case state is
-- Write byte 1
when S_WRITE1 =>
ready32_out <= '0'; -- not ready for data from 32-bit side
data8_out <= wip(23 downto 16);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE2;
end if;
-- Write byte 2
when S_WRITE2 =>
ready32_out <= '0'; -- not ready for data from 32-bit side
data8_out <= wip(15 downto 8);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE3;
end if;
-- Write byte 3 (LSB)
when S_WRITE3 =>
ready32_out <= '0'; -- not ready for data from 32-bit side
data8_out <= wip(7 downto 0);
if ( ready8_in = '1' ) then
valid8_out <= '1';
state_next <= S_WRITE0;
end if;
-- When a word arrives, write byte 0 (MSB)
when others =>
ready32_out <= ready8_in; -- ready for data from 32-bit side
data8_out <= data32_in(31 downto 24);
valid8_out <= valid32_in;
if ( valid32_in = '1' and ready8_in = '1' ) then
wip_next <= data32_in(23 downto 0);
state_next <= S_WRITE1;
end if;
end case;
end process;
end architecture;
|
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`protect end_protected
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY PISO8bits_TB IS
END PISO8bits_TB;
ARCHITECTURE behavior OF PISO8bits_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PISO8bits
PORT(
Reset : IN std_logic;
D : IN std_logic_vector(7 downto 0);
CLK : IN std_logic;
SL : IN std_logic;
O : OUT std_logic
);
END COMPONENT;
--Inputs
signal Reset : std_logic := '0';
signal D : std_logic_vector(7 downto 0) := (others => '0');
signal CLK : std_logic := '0';
signal SL : std_logic := '0';
--Outputs
signal O : std_logic;
-- Clock period definitions
constant CLK_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PISO8bits PORT MAP (
Reset => Reset,
D => D,
CLK => CLK,
SL => SL,
O => O
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 10 ns;
SL <= '1';
D <= "10011010";
wait for 10 ns;
SL <= '0';
D <= "00000000";
wait;
end process;
END;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc821.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s02b02x00p02n01i00821ent IS
END c01s02b02x00p02n01i00821ent;
ARCHITECTURE c01s02b02x00p02n01i00821arch OF c01s02b02x00p02n01i00821ent IS
signal err : boolean := true;
BEGIN
case err is -- illegal location for case statement
when true | false =>
assert false
report "'case' statement accepted in an entity statement."
severity note ;
end case;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s02b02x00p02n01i00821 - Architecture statement can only have concurrent statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s02b02x00p02n01i00821arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc821.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s02b02x00p02n01i00821ent IS
END c01s02b02x00p02n01i00821ent;
ARCHITECTURE c01s02b02x00p02n01i00821arch OF c01s02b02x00p02n01i00821ent IS
signal err : boolean := true;
BEGIN
case err is -- illegal location for case statement
when true | false =>
assert false
report "'case' statement accepted in an entity statement."
severity note ;
end case;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s02b02x00p02n01i00821 - Architecture statement can only have concurrent statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s02b02x00p02n01i00821arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc821.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s02b02x00p02n01i00821ent IS
END c01s02b02x00p02n01i00821ent;
ARCHITECTURE c01s02b02x00p02n01i00821arch OF c01s02b02x00p02n01i00821ent IS
signal err : boolean := true;
BEGIN
case err is -- illegal location for case statement
when true | false =>
assert false
report "'case' statement accepted in an entity statement."
severity note ;
end case;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s02b02x00p02n01i00821 - Architecture statement can only have concurrent statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s02b02x00p02n01i00821arch;
|
---------------------------------------------------------------------
-- TITLE: Random Access Memory
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 4/21/01
-- FILENAME: ram.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the RAM, reads the executable from either "code.txt",
-- or for Altera "code[0-3].hex".
-- Modified from "The Designer's Guide to VHDL" by Peter J. Ashenden
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
entity ram is
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
constant ADDRESS_WIDTH : natural := 15;
subtype word is std_logic_vector(data_write'length-1 downto 0);
type storage_array is
array(natural range 0 to (2 ** ADDRESS_WIDTH)/4 - 1) of word;
signal storage : storage_array;
begin
ram_proc: process(clk, enable, write_byte_enable,
address, data_write) --mem_write, mem_sel
variable data : std_logic_vector(31 downto 0);
variable index : natural := 0;
file load_file : text open read_mode is stim_file;
variable hex_file_line : line;
begin
--Load in the ram executable image
if index = 0 then
while not endfile(load_file) loop
--The following two lines had to be commented out for synthesis
readline(load_file, hex_file_line);
hread(hex_file_line, data);
storage(index) <= data;
index := index + 1;
end loop;
end if;
if rising_edge(clk) then
index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
data := storage(index);
if enable = '1' then
if write_byte_enable(0) = '1' then
data(7 downto 0) := data_write(7 downto 0);
end if;
if write_byte_enable(1) = '1' then
data(15 downto 8) := data_write(15 downto 8);
end if;
if write_byte_enable(2) = '1' then
data(23 downto 16) := data_write(23 downto 16);
end if;
if write_byte_enable(3) = '1' then
data(31 downto 24) := data_write(31 downto 24);
end if;
end if;
if write_byte_enable /= "0000" then
storage(index) <= data;
end if;
end if;
data_read <= data;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Random Access Memory
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 4/21/01
-- FILENAME: ram.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the RAM, reads the executable from either "code.txt",
-- or for Altera "code[0-3].hex".
-- Modified from "The Designer's Guide to VHDL" by Peter J. Ashenden
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
entity ram is
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
constant ADDRESS_WIDTH : natural := 15;
subtype word is std_logic_vector(data_write'length-1 downto 0);
type storage_array is
array(natural range 0 to (2 ** ADDRESS_WIDTH)/4 - 1) of word;
signal storage : storage_array;
begin
ram_proc: process(clk, enable, write_byte_enable,
address, data_write) --mem_write, mem_sel
variable data : std_logic_vector(31 downto 0);
variable index : natural := 0;
file load_file : text open read_mode is stim_file;
variable hex_file_line : line;
begin
--Load in the ram executable image
if index = 0 then
while not endfile(load_file) loop
--The following two lines had to be commented out for synthesis
readline(load_file, hex_file_line);
hread(hex_file_line, data);
storage(index) <= data;
index := index + 1;
end loop;
end if;
if rising_edge(clk) then
index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
data := storage(index);
if enable = '1' then
if write_byte_enable(0) = '1' then
data(7 downto 0) := data_write(7 downto 0);
end if;
if write_byte_enable(1) = '1' then
data(15 downto 8) := data_write(15 downto 8);
end if;
if write_byte_enable(2) = '1' then
data(23 downto 16) := data_write(23 downto 16);
end if;
if write_byte_enable(3) = '1' then
data(31 downto 24) := data_write(31 downto 24);
end if;
end if;
if write_byte_enable /= "0000" then
storage(index) <= data;
end if;
end if;
data_read <= data;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Random Access Memory
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 4/21/01
-- FILENAME: ram.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the RAM, reads the executable from either "code.txt",
-- or for Altera "code[0-3].hex".
-- Modified from "The Designer's Guide to VHDL" by Peter J. Ashenden
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
entity ram is
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
constant ADDRESS_WIDTH : natural := 15;
subtype word is std_logic_vector(data_write'length-1 downto 0);
type storage_array is
array(natural range 0 to (2 ** ADDRESS_WIDTH)/4 - 1) of word;
signal storage : storage_array;
begin
ram_proc: process(clk, enable, write_byte_enable,
address, data_write) --mem_write, mem_sel
variable data : std_logic_vector(31 downto 0);
variable index : natural := 0;
file load_file : text open read_mode is stim_file;
variable hex_file_line : line;
begin
--Load in the ram executable image
if index = 0 then
while not endfile(load_file) loop
--The following two lines had to be commented out for synthesis
readline(load_file, hex_file_line);
hread(hex_file_line, data);
storage(index) <= data;
index := index + 1;
end loop;
end if;
if rising_edge(clk) then
index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
data := storage(index);
if enable = '1' then
if write_byte_enable(0) = '1' then
data(7 downto 0) := data_write(7 downto 0);
end if;
if write_byte_enable(1) = '1' then
data(15 downto 8) := data_write(15 downto 8);
end if;
if write_byte_enable(2) = '1' then
data(23 downto 16) := data_write(23 downto 16);
end if;
if write_byte_enable(3) = '1' then
data(31 downto 24) := data_write(31 downto 24);
end if;
end if;
if write_byte_enable /= "0000" then
storage(index) <= data;
end if;
end if;
data_read <= data;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Random Access Memory
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 4/21/01
-- FILENAME: ram.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the RAM, reads the executable from either "code.txt",
-- or for Altera "code[0-3].hex".
-- Modified from "The Designer's Guide to VHDL" by Peter J. Ashenden
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
entity ram is
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
constant ADDRESS_WIDTH : natural := 15;
subtype word is std_logic_vector(data_write'length-1 downto 0);
type storage_array is
array(natural range 0 to (2 ** ADDRESS_WIDTH)/4 - 1) of word;
signal storage : storage_array;
begin
ram_proc: process(clk, enable, write_byte_enable,
address, data_write) --mem_write, mem_sel
variable data : std_logic_vector(31 downto 0);
variable index : natural := 0;
file load_file : text open read_mode is stim_file;
variable hex_file_line : line;
begin
--Load in the ram executable image
if index = 0 then
while not endfile(load_file) loop
--The following two lines had to be commented out for synthesis
readline(load_file, hex_file_line);
hread(hex_file_line, data);
storage(index) <= data;
index := index + 1;
end loop;
end if;
if rising_edge(clk) then
index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
data := storage(index);
if enable = '1' then
if write_byte_enable(0) = '1' then
data(7 downto 0) := data_write(7 downto 0);
end if;
if write_byte_enable(1) = '1' then
data(15 downto 8) := data_write(15 downto 8);
end if;
if write_byte_enable(2) = '1' then
data(23 downto 16) := data_write(23 downto 16);
end if;
if write_byte_enable(3) = '1' then
data(31 downto 24) := data_write(31 downto 24);
end if;
end if;
if write_byte_enable /= "0000" then
storage(index) <= data;
end if;
end if;
data_read <= data;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Random Access Memory
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 4/21/01
-- FILENAME: ram.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the RAM, reads the executable from either "code.txt",
-- or for Altera "code[0-3].hex".
-- Modified from "The Designer's Guide to VHDL" by Peter J. Ashenden
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
entity ram is
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
constant ADDRESS_WIDTH : natural := 15;
subtype word is std_logic_vector(data_write'length-1 downto 0);
type storage_array is
array(natural range 0 to (2 ** ADDRESS_WIDTH)/4 - 1) of word;
signal storage : storage_array;
begin
ram_proc: process(clk, enable, write_byte_enable,
address, data_write) --mem_write, mem_sel
variable data : std_logic_vector(31 downto 0);
variable index : natural := 0;
file load_file : text open read_mode is stim_file;
variable hex_file_line : line;
begin
--Load in the ram executable image
if index = 0 then
while not endfile(load_file) loop
--The following two lines had to be commented out for synthesis
readline(load_file, hex_file_line);
hread(hex_file_line, data);
storage(index) <= data;
index := index + 1;
end loop;
end if;
if rising_edge(clk) then
index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
data := storage(index);
if enable = '1' then
if write_byte_enable(0) = '1' then
data(7 downto 0) := data_write(7 downto 0);
end if;
if write_byte_enable(1) = '1' then
data(15 downto 8) := data_write(15 downto 8);
end if;
if write_byte_enable(2) = '1' then
data(23 downto 16) := data_write(23 downto 16);
end if;
if write_byte_enable(3) = '1' then
data(31 downto 24) := data_write(31 downto 24);
end if;
end if;
if write_byte_enable /= "0000" then
storage(index) <= data;
end if;
end if;
data_read <= data;
end process;
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Random Access Memory
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 4/21/01
-- FILENAME: ram.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the RAM, reads the executable from either "code.txt",
-- or for Altera "code[0-3].hex".
-- Modified from "The Designer's Guide to VHDL" by Peter J. Ashenden
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
entity ram is
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
constant ADDRESS_WIDTH : natural := 15;
subtype word is std_logic_vector(data_write'length-1 downto 0);
type storage_array is
array(natural range 0 to (2 ** ADDRESS_WIDTH)/4 - 1) of word;
signal storage : storage_array;
begin
ram_proc: process(clk, enable, write_byte_enable,
address, data_write) --mem_write, mem_sel
variable data : std_logic_vector(31 downto 0);
variable index : natural := 0;
file load_file : text open read_mode is stim_file;
variable hex_file_line : line;
begin
--Load in the ram executable image
if index = 0 then
while not endfile(load_file) loop
--The following two lines had to be commented out for synthesis
readline(load_file, hex_file_line);
hread(hex_file_line, data);
storage(index) <= data;
index := index + 1;
end loop;
end if;
if rising_edge(clk) then
index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
data := storage(index);
if enable = '1' then
if write_byte_enable(0) = '1' then
data(7 downto 0) := data_write(7 downto 0);
end if;
if write_byte_enable(1) = '1' then
data(15 downto 8) := data_write(15 downto 8);
end if;
if write_byte_enable(2) = '1' then
data(23 downto 16) := data_write(23 downto 16);
end if;
if write_byte_enable(3) = '1' then
data(31 downto 24) := data_write(31 downto 24);
end if;
end if;
if write_byte_enable /= "0000" then
storage(index) <= data;
end if;
end if;
data_read <= data;
end process;
end; --architecture logic
|
-------------------------------------------------------------------------------
-- AXI_GPIO - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_gpio.vhd
-- Version: v2.0
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
-------------------------------------------------------------------------------
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 07/28/09
-- ^^^^^^^^^^^^^^
-- First version of axi_gpio. Based on xps_gpio 2.00a
--
-- KSB 05/20/10
-- ^^^^^^^^^^^^^^
-- Updated for holes in address range
-- ~~~~~~~~~~~~~~
-- VB 09/23/10
-- ^^^^^^^^^^^^^^
-- Updated for axi_lite_ipfi_v1_01_a
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use std.textio.all;
-------------------------------------------------------------------------------
-- AXI common package of the proc common library is used for different
-- function declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_9 library is used for axi4 component declarations
-------------------------------------------------------------------------------
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0_3.ipif_pkg.INTEGER_ARRAY_TYPE;
use axi_lite_ipif_v3_0_3.ipif_pkg.SLV64_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_9 library is used for interrupt controller component
-- declarations
-------------------------------------------------------------------------------
library interrupt_control_v3_1_3;
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_9 library is used for axi_gpio component declarations
-------------------------------------------------------------------------------
library axi_gpio_v2_0_9;
-------------------------------------------------------------------------------
-- Defination of Generics : --
-------------------------------------------------------------------------------
-- AXI generics
-- C_BASEADDR -- Base address of the core
-- C_HIGHADDR -- Permits alias of address space
-- by making greater than xFFF
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address interface (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data interface (in bits)
-- C_FAMILY -- XILINX FPGA family
-- C_INSTANCE -- Instance name ot the core in the EDK system
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_ALL_INPUTS -- Inputs Only.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_IS_BIDIR -- Selects gpio_io_i as input.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_ALL_INPUTS_2 -- Channel2 Inputs only.
-- C_IS_BIDIR_2 -- Selects gpio2_io_i as input.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Defination of Ports --
-------------------------------------------------------------------------------
-- AXI signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- GPIO Signals
-- gpio_io_i -- Channel 1 General purpose I/O in port
-- gpio_io_o -- Channel 1 General purpose I/O out port
-- gpio_io_t -- Channel 1 General purpose I/O
-- TRI-STATE control port
-- gpio2_io_i -- Channel 2 General purpose I/O in port
-- gpio2_io_o -- Channel 2 General purpose I/O out port
-- gpio2_io_t -- Channel 2 General purpose I/O
-- TRI-STATE control port
-- System Signals
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- ip2intc_irpt -- AXI GPIO Interrupt
-------------------------------------------------------------------------------
entity axi_gpio is
generic
(
-- -- System Parameter
C_FAMILY : string := "virtex7";
-- -- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer range 9 to 9 := 9;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
-- -- GPIO Parameter
C_GPIO_WIDTH : integer range 1 to 32 := 32;
C_GPIO2_WIDTH : integer range 1 to 32 := 32;
C_ALL_INPUTS : integer range 0 to 1 := 0;
C_ALL_INPUTS_2 : integer range 0 to 1 := 0;
C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013
C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013
C_INTERRUPT_PRESENT : integer range 0 to 1 := 0;
C_DOUT_DEFAULT : std_logic_vector (31 downto 0) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (31 downto 0) := X"FFFF_FFFF";
C_IS_DUAL : integer range 0 to 1 := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (31 downto 0) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (31 downto 0) := X"FFFF_FFFF"
);
port
(
-- AXI interface Signals --------------------------------------------------
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1
downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1
downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1
downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1
downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1
downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Interrupt---------------------------------------------------------------
ip2intc_irpt : out std_logic;
-- GPIO Signals------------------------------------------------------------
gpio_io_i : in std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio_io_o : out std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio_io_t : out std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio2_io_i : in std_logic_vector(C_GPIO2_WIDTH-1 downto 0);
gpio2_io_o : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0);
gpio2_io_t : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0)
);
-------------------------------------------------------------------------------
-- fan-out attributes for XST
-------------------------------------------------------------------------------
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of s_axi_aclk : signal is "10000";
attribute MAX_FANOUT of s_axi_aresetn : signal is "10000";
-------------------------------------------------------------------------------
-- Attributes for MPD file
-------------------------------------------------------------------------------
attribute IP_GROUP : string ;
attribute IP_GROUP of axi_gpio : entity is "LOGICORE";
attribute SIGIS : string ;
attribute SIGIS of s_axi_aclk : signal is "Clk";
attribute SIGIS of s_axi_aresetn : signal is "Rst";
attribute SIGIS of ip2intc_irpt : signal is "INTR_LEVEL_HIGH";
end entity axi_gpio;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture imp of axi_gpio is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- constant added for webtalk information
-------------------------------------------------------------------------------
--function chr(sl: std_logic) return character is
-- variable c: character;
-- begin
-- case sl is
-- when '0' => c:= '0';
-- when '1' => c:= '1';
-- when 'Z' => c:= 'Z';
-- when 'U' => c:= 'U';
-- when 'X' => c:= 'X';
-- when 'W' => c:= 'W';
-- when 'L' => c:= 'L';
-- when 'H' => c:= 'H';
-- when '-' => c:= '-';
-- end case;
-- return c;
-- end chr;
--
--function str(slv: std_logic_vector) return string is
-- variable result : string (1 to slv'length);
-- variable r : integer;
-- begin
-- r := 1;
-- for i in slv'range loop
-- result(r) := chr(slv(i));
-- r := r + 1;
-- end loop;
-- return result;
-- end str;
type bo2na_type is array (boolean) of natural; -- boolean to
--natural conversion
constant bo2na : bo2na_type := (false => 0, true => 1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
type BOOLEAN_ARRAY_TYPE is array(natural range <>) of boolean;
----------------------------------------------------------------------------
-- This function returns the number of elements that are true in
-- a boolean array.
----------------------------------------------------------------------------
function num_set( ba : BOOLEAN_ARRAY_TYPE ) return natural is
variable n : natural := 0;
begin
for i in ba'range loop
n := n + bo2na(ba(i));
end loop;
return n;
end;
----------------------------------------------------------------------------
-- This function returns a num_ce integer array that is constructed by
-- taking only those elements of superset num_ce integer array
-- that will be defined by the current case.
-- The superset num_ce array is given by parameter num_ce_by_ard.
-- The current case the ard elements that will be used is given
-- by parameter defined_ards.
----------------------------------------------------------------------------
function qual_ard_num_ce_array( defined_ards : BOOLEAN_ARRAY_TYPE;
num_ce_by_ard : INTEGER_ARRAY_TYPE
) return INTEGER_ARRAY_TYPE is
variable res : INTEGER_ARRAY_TYPE(num_set(defined_ards)-1 downto 0);
variable i : natural := 0;
variable j : natural := defined_ards'left;
begin
while i /= res'length loop
-- coverage off
while defined_ards(j) = false loop
j := j+1;
end loop;
-- coverage on
res(i) := num_ce_by_ard(j);
i := i+1;
j := j+1;
end loop;
return res;
end;
----------------------------------------------------------------------------
-- This function returns a addr_range array that is constructed by
-- taking only those elements of superset addr_range array
-- that will be defined by the current case.
-- The superset addr_range array is given by parameter addr_range_by_ard.
-- The current case the ard elements that will be used is given
-- by parameter defined_ards.
----------------------------------------------------------------------------
function qual_ard_addr_range_array( defined_ards : BOOLEAN_ARRAY_TYPE;
addr_range_by_ard : SLV64_ARRAY_TYPE
) return SLV64_ARRAY_TYPE is
variable res : SLV64_ARRAY_TYPE(0 to 2*num_set(defined_ards)-1);
variable i : natural := 0;
variable j : natural := defined_ards'left;
begin
while i /= res'length loop
-- coverage off
while defined_ards(j) = false loop
j := j+1;
end loop;
-- coverage on
res(i) := addr_range_by_ard(2*j);
res(i+1) := addr_range_by_ard((2*j)+1);
i := i+2;
j := j+1;
end loop;
return res;
end;
function qual_ard_ce_valid( defined_ards : BOOLEAN_ARRAY_TYPE
) return std_logic_vector is
variable res : std_logic_vector(0 to 31);
begin
res := (others => '0');
if defined_ards(defined_ards'right) then
res(0 to 3) := "1111";
res(12) := '1';
res(13) := '1';
res(15) := '1';
else
res(0 to 3) := "1111";
end if;
return res;
end;
----------------------------------------------------------------------------
-- This function returns the maximum width amongst the two GPIO Channels
-- and if there is only one channel, it returns just the width of that
-- channel.
----------------------------------------------------------------------------
function max_width( dual_channel : INTEGER;
channel1_width : INTEGER;
channel2_width : INTEGER
) return INTEGER is
begin
if (dual_channel = 0) then
return channel1_width;
else
if (channel1_width > channel2_width) then
return channel1_width;
else
return channel2_width;
end if;
end if;
end;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant C_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) :=
(others => '0');
constant INTR_TYPE : integer := 5;
constant INTR_BASEADDR : std_logic_vector(0 to 31):= X"00000100";
constant INTR_HIGHADDR : std_logic_vector(0 to 31):= X"000001FF";
constant GPIO_HIGHADDR : std_logic_vector(0 to 31):= X"0000000F";
constant MAX_GPIO_WIDTH : integer := max_width
(C_IS_DUAL,C_GPIO_WIDTH,C_GPIO2_WIDTH);
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
qual_ard_addr_range_array(
(true,C_INTERRUPT_PRESENT=1),
(ZERO_ADDR_PAD & X"00000000",
ZERO_ADDR_PAD & GPIO_HIGHADDR,
ZERO_ADDR_PAD & INTR_BASEADDR,
ZERO_ADDR_PAD & INTR_HIGHADDR
)
);
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
qual_ard_num_ce_array(
(true,C_INTERRUPT_PRESENT=1),
(4,16)
);
constant ARD_CE_VALID : std_logic_vector(0 to 31) :=
qual_ard_ce_valid(
(true,C_INTERRUPT_PRESENT=1)
);
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to 0+bo2na(C_IS_DUAL=1))
:= (others => 5);
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 8;
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal ip2bus_intrevent : std_logic_vector(0 to 1);
signal GPIO_xferAck_i : std_logic;
signal Bus2IP_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal Bus2IP1_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal Bus2IP2_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
-- IPIC Used Signals
signal ip2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1);
signal bus2ip_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_rnw : std_logic;
signal bus2ip_cs : std_logic_vector(0 to 0 + bo2na
(C_INTERRUPT_PRESENT=1));
signal bus2ip_rdce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal bus2ip_wrce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal Intrpt_bus2ip_rdce : std_logic_vector(0 to 15);
signal Intrpt_bus2ip_wrce : std_logic_vector(0 to 15);
signal intr_wr_ce_or_reduce : std_logic;
signal intr_rd_ce_or_reduce : std_logic;
signal ip2Bus_RdAck_intr_reg_hole : std_logic;
signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic;
signal ip2Bus_WrAck_intr_reg_hole : std_logic;
signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic;
signal bus2ip_be : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH / 8) - 1);
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
signal bus2ip_resetn : std_logic;
signal intr2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal intr2bus_wrack : std_logic;
signal intr2bus_rdack : std_logic;
signal intr2bus_error : std_logic;
signal ip2bus_data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2bus_data_i_D1 : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2bus_wrack_i : std_logic;
signal ip2bus_wrack_i_D1 : std_logic;
signal ip2bus_rdack_i : std_logic;
signal ip2bus_rdack_i_D1 : std_logic;
signal ip2bus_error_i : std_logic;
signal IP2INTC_Irpt_i : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_3.axi_lite_ipif
generic map
(
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data_i_D1,
IP2Bus_WrAck => ip2bus_wrack_i_D1,
IP2Bus_RdAck => ip2bus_rdack_i_D1,
--IP2Bus_WrAck => ip2bus_wrack_i,
--IP2Bus_RdAck => ip2bus_rdack_i,
IP2Bus_Error => ip2bus_error_i,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => bus2ip_rnw,
Bus2IP_BE => bus2ip_be,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
ip2bus_data_i <= intr2bus_data or ip2bus_data;
ip2bus_wrack_i <= intr2bus_wrack or
(GPIO_xferAck_i and not(bus2ip_rnw)) or
ip2Bus_WrAck_intr_reg_hole;-- Holes in Address range
ip2bus_rdack_i <= intr2bus_rdack or
(GPIO_xferAck_i and bus2ip_rnw) or
ip2Bus_RdAck_intr_reg_hole; -- Holes in Address range
I_WRACK_RDACK_DELAYS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2bus_wrack_i_D1 <= '0';
ip2bus_rdack_i_D1 <= '0';
ip2bus_data_i_D1 <= (others => '0');
else
ip2bus_wrack_i_D1 <= ip2bus_wrack_i;
ip2bus_rdack_i_D1 <= ip2bus_rdack_i;
ip2bus_data_i_D1 <= ip2bus_data_i;
end if;
end if;
end process I_WRACK_RDACK_DELAYS;
ip2bus_error_i <= intr2bus_error;
----------------------
--REG_RESET_FROM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RESET_FROM_IPIF: process (s_axi_aclk) is
begin
if(s_axi_aclk'event and s_axi_aclk = '1') then
bus2ip_reset <= not(bus2ip_resetn);
end if;
end process REG_RESET_FROM_IPIF;
---------------------------------------------------------------------------
-- Interrupts
---------------------------------------------------------------------------
INTR_CTRLR_GEN : if (C_INTERRUPT_PRESENT = 1) generate
constant NUM_IPIF_IRPT_SRC : natural := 1;
constant NUM_CE : integer := 16;
signal errack_reserved : std_logic_vector(0 to 1);
signal ipif_lvl_interrupts : std_logic_vector(0 to
NUM_IPIF_IRPT_SRC-1);
begin
ipif_lvl_interrupts <= (others => '0');
errack_reserved <= (others => '0');
--- Addr 0X11c, 0X120, 0X128 valid addresses, remaining are holes
Intrpt_bus2ip_rdce <= "0000000" & bus2ip_rdce(11) & bus2ip_rdce(12) & '0'
& bus2ip_rdce(14) & "00000";
Intrpt_bus2ip_wrce <= "0000000" & bus2ip_wrce(11) & bus2ip_wrce(12) & '0'
& bus2ip_wrce(14) & "00000";
intr_rd_ce_or_reduce <= or_reduce(bus2ip_rdce(4 to 10)) or
Bus2IP_RdCE(13) or
or_reduce(Bus2IP_RdCE(15 to 19));
intr_wr_ce_or_reduce <= or_reduce(bus2ip_wrce(4 to 10)) or
bus2ip_wrce(13) or
or_reduce(bus2ip_wrce(15 to 19));
I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2Bus_RdAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_RdAck_intr_reg_hole_d1 <= intr_rd_ce_or_reduce;
ip2Bus_RdAck_intr_reg_hole <= intr_rd_ce_or_reduce and
(not ip2Bus_RdAck_intr_reg_hole_d1);
end if;
end if;
end process I_READ_ACK_INTR_HOLES;
I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_WrAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_WrAck_intr_reg_hole_d1 <= intr_wr_ce_or_reduce;
ip2Bus_WrAck_intr_reg_hole <= intr_wr_ce_or_reduce and
(not ip2Bus_WrAck_intr_reg_hole_d1);
end if;
end if;
end process I_WRITE_ACK_INTR_HOLES;
INTERRUPT_CONTROL_I : entity interrupt_control_v3_1_3.interrupt_control
generic map
(
C_NUM_CE => NUM_CE,
C_NUM_IPIF_IRPT_SRC => NUM_IPIF_IRPT_SRC,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_INCLUDE_DEV_PENCODER => false,
C_INCLUDE_DEV_ISC => false,
C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH
)
port map
(
-- Inputs From the IPIF Bus
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => bus2ip_reset,
Bus2IP_Data => bus2ip_data,
Bus2IP_BE => bus2ip_be,
Interrupt_RdCE => Intrpt_bus2ip_rdce,
Interrupt_WrCE => Intrpt_bus2ip_wrce,
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
IPIF_Reg_Interrupts => errack_reserved,
-- Level Interrupt inputs from the IPIF sources
IPIF_Lvl_Interrupts => ipif_lvl_interrupts,
-- Inputs from the IP Interface
IP2Bus_IntrEvent => ip2bus_intrevent(IP_INTR_MODE_ARRAY'range),
-- Final Device Interrupt Output
Intr2Bus_DevIntr => IP2INTC_Irpt_i,
-- Status Reply Outputs to the Bus
Intr2Bus_DBus => intr2bus_data,
Intr2Bus_WrAck => intr2bus_wrack,
Intr2Bus_RdAck => intr2bus_rdack,
Intr2Bus_Error => intr2bus_error,
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
-- registering interrupt
I_INTR_DELAY: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2intc_irpt <= '0';
else
ip2intc_irpt <= IP2INTC_Irpt_i;
end if;
end if;
end process I_INTR_DELAY;
end generate INTR_CTRLR_GEN;
-----------------------------------------------------------------------
-- Assigning the intr2bus signal to zero's when interrupt is not
-- present
-----------------------------------------------------------------------
REMOVE_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
intr2bus_data <= (others => '0');
ip2intc_irpt <= '0';
intr2bus_error <= '0';
intr2bus_rdack <= '0';
intr2bus_wrack <= '0';
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole <= '0';
end generate REMOVE_INTERRUPT;
gpio_core_1 : entity axi_gpio_v2_0_9.gpio_core
generic map
(
C_DW => C_S_AXI_DATA_WIDTH,
C_AW => C_S_AXI_ADDR_WIDTH,
C_GPIO_WIDTH => C_GPIO_WIDTH,
C_GPIO2_WIDTH => C_GPIO2_WIDTH,
C_MAX_GPIO_WIDTH => MAX_GPIO_WIDTH,
C_INTERRUPT_PRESENT => C_INTERRUPT_PRESENT,
C_DOUT_DEFAULT => C_DOUT_DEFAULT,
C_TRI_DEFAULT => C_TRI_DEFAULT,
C_IS_DUAL => C_IS_DUAL,
C_DOUT_DEFAULT_2 => C_DOUT_DEFAULT_2,
C_TRI_DEFAULT_2 => C_TRI_DEFAULT_2,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Bus2IP_Clk,
Rst => bus2ip_reset,
ABus_Reg => Bus2IP_Addr,
BE_Reg => Bus2IP_BE(0 to C_S_AXI_DATA_WIDTH/8-1),
DBus_Reg => Bus2IP_Data_i(0 to MAX_GPIO_WIDTH-1),
RNW_Reg => Bus2IP_RNW,
GPIO_DBus => IP2Bus_Data(0 to C_S_AXI_DATA_WIDTH-1),
GPIO_xferAck => GPIO_xferAck_i,
GPIO_Select => bus2ip_cs(0),
GPIO_intr => ip2bus_intrevent(0),
GPIO2_intr => ip2bus_intrevent(1),
GPIO_IO_I => gpio_io_i,
GPIO_IO_O => gpio_io_o,
GPIO_IO_T => gpio_io_t,
GPIO2_IO_I => gpio2_io_i,
GPIO2_IO_O => gpio2_io_o,
GPIO2_IO_T => gpio2_io_t
);
Bus2IP_Data_i <= Bus2IP1_Data_i when bus2ip_cs(0) = '1'
and bus2ip_addr (5) = '0'else
Bus2IP2_Data_i;
BUS_CONV_ch1 : for i in 0 to C_GPIO_WIDTH-1 generate
Bus2IP1_Data_i(i) <= Bus2IP_Data(i+
C_S_AXI_DATA_WIDTH-C_GPIO_WIDTH);
end generate BUS_CONV_ch1;
BUS_CONV_ch2 : for i in 0 to C_GPIO2_WIDTH-1 generate
Bus2IP2_Data_i(i) <= Bus2IP_Data(i+
C_S_AXI_DATA_WIDTH-C_GPIO2_WIDTH);
end generate BUS_CONV_ch2;
end architecture imp;
|
-------------------------------------------------------------------------------
-- AXI_GPIO - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_gpio.vhd
-- Version: v2.0
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
-------------------------------------------------------------------------------
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 07/28/09
-- ^^^^^^^^^^^^^^
-- First version of axi_gpio. Based on xps_gpio 2.00a
--
-- KSB 05/20/10
-- ^^^^^^^^^^^^^^
-- Updated for holes in address range
-- ~~~~~~~~~~~~~~
-- VB 09/23/10
-- ^^^^^^^^^^^^^^
-- Updated for axi_lite_ipfi_v1_01_a
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use std.textio.all;
-------------------------------------------------------------------------------
-- AXI common package of the proc common library is used for different
-- function declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_9 library is used for axi4 component declarations
-------------------------------------------------------------------------------
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0_3.ipif_pkg.INTEGER_ARRAY_TYPE;
use axi_lite_ipif_v3_0_3.ipif_pkg.SLV64_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_9 library is used for interrupt controller component
-- declarations
-------------------------------------------------------------------------------
library interrupt_control_v3_1_3;
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_9 library is used for axi_gpio component declarations
-------------------------------------------------------------------------------
library axi_gpio_v2_0_9;
-------------------------------------------------------------------------------
-- Defination of Generics : --
-------------------------------------------------------------------------------
-- AXI generics
-- C_BASEADDR -- Base address of the core
-- C_HIGHADDR -- Permits alias of address space
-- by making greater than xFFF
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address interface (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data interface (in bits)
-- C_FAMILY -- XILINX FPGA family
-- C_INSTANCE -- Instance name ot the core in the EDK system
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_ALL_INPUTS -- Inputs Only.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_IS_BIDIR -- Selects gpio_io_i as input.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_ALL_INPUTS_2 -- Channel2 Inputs only.
-- C_IS_BIDIR_2 -- Selects gpio2_io_i as input.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Defination of Ports --
-------------------------------------------------------------------------------
-- AXI signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- GPIO Signals
-- gpio_io_i -- Channel 1 General purpose I/O in port
-- gpio_io_o -- Channel 1 General purpose I/O out port
-- gpio_io_t -- Channel 1 General purpose I/O
-- TRI-STATE control port
-- gpio2_io_i -- Channel 2 General purpose I/O in port
-- gpio2_io_o -- Channel 2 General purpose I/O out port
-- gpio2_io_t -- Channel 2 General purpose I/O
-- TRI-STATE control port
-- System Signals
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- ip2intc_irpt -- AXI GPIO Interrupt
-------------------------------------------------------------------------------
entity axi_gpio is
generic
(
-- -- System Parameter
C_FAMILY : string := "virtex7";
-- -- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer range 9 to 9 := 9;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
-- -- GPIO Parameter
C_GPIO_WIDTH : integer range 1 to 32 := 32;
C_GPIO2_WIDTH : integer range 1 to 32 := 32;
C_ALL_INPUTS : integer range 0 to 1 := 0;
C_ALL_INPUTS_2 : integer range 0 to 1 := 0;
C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013
C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013
C_INTERRUPT_PRESENT : integer range 0 to 1 := 0;
C_DOUT_DEFAULT : std_logic_vector (31 downto 0) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (31 downto 0) := X"FFFF_FFFF";
C_IS_DUAL : integer range 0 to 1 := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (31 downto 0) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (31 downto 0) := X"FFFF_FFFF"
);
port
(
-- AXI interface Signals --------------------------------------------------
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1
downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1
downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1
downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1
downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1
downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Interrupt---------------------------------------------------------------
ip2intc_irpt : out std_logic;
-- GPIO Signals------------------------------------------------------------
gpio_io_i : in std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio_io_o : out std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio_io_t : out std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio2_io_i : in std_logic_vector(C_GPIO2_WIDTH-1 downto 0);
gpio2_io_o : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0);
gpio2_io_t : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0)
);
-------------------------------------------------------------------------------
-- fan-out attributes for XST
-------------------------------------------------------------------------------
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of s_axi_aclk : signal is "10000";
attribute MAX_FANOUT of s_axi_aresetn : signal is "10000";
-------------------------------------------------------------------------------
-- Attributes for MPD file
-------------------------------------------------------------------------------
attribute IP_GROUP : string ;
attribute IP_GROUP of axi_gpio : entity is "LOGICORE";
attribute SIGIS : string ;
attribute SIGIS of s_axi_aclk : signal is "Clk";
attribute SIGIS of s_axi_aresetn : signal is "Rst";
attribute SIGIS of ip2intc_irpt : signal is "INTR_LEVEL_HIGH";
end entity axi_gpio;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture imp of axi_gpio is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- constant added for webtalk information
-------------------------------------------------------------------------------
--function chr(sl: std_logic) return character is
-- variable c: character;
-- begin
-- case sl is
-- when '0' => c:= '0';
-- when '1' => c:= '1';
-- when 'Z' => c:= 'Z';
-- when 'U' => c:= 'U';
-- when 'X' => c:= 'X';
-- when 'W' => c:= 'W';
-- when 'L' => c:= 'L';
-- when 'H' => c:= 'H';
-- when '-' => c:= '-';
-- end case;
-- return c;
-- end chr;
--
--function str(slv: std_logic_vector) return string is
-- variable result : string (1 to slv'length);
-- variable r : integer;
-- begin
-- r := 1;
-- for i in slv'range loop
-- result(r) := chr(slv(i));
-- r := r + 1;
-- end loop;
-- return result;
-- end str;
type bo2na_type is array (boolean) of natural; -- boolean to
--natural conversion
constant bo2na : bo2na_type := (false => 0, true => 1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
type BOOLEAN_ARRAY_TYPE is array(natural range <>) of boolean;
----------------------------------------------------------------------------
-- This function returns the number of elements that are true in
-- a boolean array.
----------------------------------------------------------------------------
function num_set( ba : BOOLEAN_ARRAY_TYPE ) return natural is
variable n : natural := 0;
begin
for i in ba'range loop
n := n + bo2na(ba(i));
end loop;
return n;
end;
----------------------------------------------------------------------------
-- This function returns a num_ce integer array that is constructed by
-- taking only those elements of superset num_ce integer array
-- that will be defined by the current case.
-- The superset num_ce array is given by parameter num_ce_by_ard.
-- The current case the ard elements that will be used is given
-- by parameter defined_ards.
----------------------------------------------------------------------------
function qual_ard_num_ce_array( defined_ards : BOOLEAN_ARRAY_TYPE;
num_ce_by_ard : INTEGER_ARRAY_TYPE
) return INTEGER_ARRAY_TYPE is
variable res : INTEGER_ARRAY_TYPE(num_set(defined_ards)-1 downto 0);
variable i : natural := 0;
variable j : natural := defined_ards'left;
begin
while i /= res'length loop
-- coverage off
while defined_ards(j) = false loop
j := j+1;
end loop;
-- coverage on
res(i) := num_ce_by_ard(j);
i := i+1;
j := j+1;
end loop;
return res;
end;
----------------------------------------------------------------------------
-- This function returns a addr_range array that is constructed by
-- taking only those elements of superset addr_range array
-- that will be defined by the current case.
-- The superset addr_range array is given by parameter addr_range_by_ard.
-- The current case the ard elements that will be used is given
-- by parameter defined_ards.
----------------------------------------------------------------------------
function qual_ard_addr_range_array( defined_ards : BOOLEAN_ARRAY_TYPE;
addr_range_by_ard : SLV64_ARRAY_TYPE
) return SLV64_ARRAY_TYPE is
variable res : SLV64_ARRAY_TYPE(0 to 2*num_set(defined_ards)-1);
variable i : natural := 0;
variable j : natural := defined_ards'left;
begin
while i /= res'length loop
-- coverage off
while defined_ards(j) = false loop
j := j+1;
end loop;
-- coverage on
res(i) := addr_range_by_ard(2*j);
res(i+1) := addr_range_by_ard((2*j)+1);
i := i+2;
j := j+1;
end loop;
return res;
end;
function qual_ard_ce_valid( defined_ards : BOOLEAN_ARRAY_TYPE
) return std_logic_vector is
variable res : std_logic_vector(0 to 31);
begin
res := (others => '0');
if defined_ards(defined_ards'right) then
res(0 to 3) := "1111";
res(12) := '1';
res(13) := '1';
res(15) := '1';
else
res(0 to 3) := "1111";
end if;
return res;
end;
----------------------------------------------------------------------------
-- This function returns the maximum width amongst the two GPIO Channels
-- and if there is only one channel, it returns just the width of that
-- channel.
----------------------------------------------------------------------------
function max_width( dual_channel : INTEGER;
channel1_width : INTEGER;
channel2_width : INTEGER
) return INTEGER is
begin
if (dual_channel = 0) then
return channel1_width;
else
if (channel1_width > channel2_width) then
return channel1_width;
else
return channel2_width;
end if;
end if;
end;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant C_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) :=
(others => '0');
constant INTR_TYPE : integer := 5;
constant INTR_BASEADDR : std_logic_vector(0 to 31):= X"00000100";
constant INTR_HIGHADDR : std_logic_vector(0 to 31):= X"000001FF";
constant GPIO_HIGHADDR : std_logic_vector(0 to 31):= X"0000000F";
constant MAX_GPIO_WIDTH : integer := max_width
(C_IS_DUAL,C_GPIO_WIDTH,C_GPIO2_WIDTH);
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
qual_ard_addr_range_array(
(true,C_INTERRUPT_PRESENT=1),
(ZERO_ADDR_PAD & X"00000000",
ZERO_ADDR_PAD & GPIO_HIGHADDR,
ZERO_ADDR_PAD & INTR_BASEADDR,
ZERO_ADDR_PAD & INTR_HIGHADDR
)
);
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
qual_ard_num_ce_array(
(true,C_INTERRUPT_PRESENT=1),
(4,16)
);
constant ARD_CE_VALID : std_logic_vector(0 to 31) :=
qual_ard_ce_valid(
(true,C_INTERRUPT_PRESENT=1)
);
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to 0+bo2na(C_IS_DUAL=1))
:= (others => 5);
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 8;
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal ip2bus_intrevent : std_logic_vector(0 to 1);
signal GPIO_xferAck_i : std_logic;
signal Bus2IP_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal Bus2IP1_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal Bus2IP2_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
-- IPIC Used Signals
signal ip2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1);
signal bus2ip_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_rnw : std_logic;
signal bus2ip_cs : std_logic_vector(0 to 0 + bo2na
(C_INTERRUPT_PRESENT=1));
signal bus2ip_rdce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal bus2ip_wrce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal Intrpt_bus2ip_rdce : std_logic_vector(0 to 15);
signal Intrpt_bus2ip_wrce : std_logic_vector(0 to 15);
signal intr_wr_ce_or_reduce : std_logic;
signal intr_rd_ce_or_reduce : std_logic;
signal ip2Bus_RdAck_intr_reg_hole : std_logic;
signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic;
signal ip2Bus_WrAck_intr_reg_hole : std_logic;
signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic;
signal bus2ip_be : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH / 8) - 1);
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
signal bus2ip_resetn : std_logic;
signal intr2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal intr2bus_wrack : std_logic;
signal intr2bus_rdack : std_logic;
signal intr2bus_error : std_logic;
signal ip2bus_data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2bus_data_i_D1 : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2bus_wrack_i : std_logic;
signal ip2bus_wrack_i_D1 : std_logic;
signal ip2bus_rdack_i : std_logic;
signal ip2bus_rdack_i_D1 : std_logic;
signal ip2bus_error_i : std_logic;
signal IP2INTC_Irpt_i : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_3.axi_lite_ipif
generic map
(
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data_i_D1,
IP2Bus_WrAck => ip2bus_wrack_i_D1,
IP2Bus_RdAck => ip2bus_rdack_i_D1,
--IP2Bus_WrAck => ip2bus_wrack_i,
--IP2Bus_RdAck => ip2bus_rdack_i,
IP2Bus_Error => ip2bus_error_i,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => bus2ip_rnw,
Bus2IP_BE => bus2ip_be,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
ip2bus_data_i <= intr2bus_data or ip2bus_data;
ip2bus_wrack_i <= intr2bus_wrack or
(GPIO_xferAck_i and not(bus2ip_rnw)) or
ip2Bus_WrAck_intr_reg_hole;-- Holes in Address range
ip2bus_rdack_i <= intr2bus_rdack or
(GPIO_xferAck_i and bus2ip_rnw) or
ip2Bus_RdAck_intr_reg_hole; -- Holes in Address range
I_WRACK_RDACK_DELAYS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2bus_wrack_i_D1 <= '0';
ip2bus_rdack_i_D1 <= '0';
ip2bus_data_i_D1 <= (others => '0');
else
ip2bus_wrack_i_D1 <= ip2bus_wrack_i;
ip2bus_rdack_i_D1 <= ip2bus_rdack_i;
ip2bus_data_i_D1 <= ip2bus_data_i;
end if;
end if;
end process I_WRACK_RDACK_DELAYS;
ip2bus_error_i <= intr2bus_error;
----------------------
--REG_RESET_FROM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RESET_FROM_IPIF: process (s_axi_aclk) is
begin
if(s_axi_aclk'event and s_axi_aclk = '1') then
bus2ip_reset <= not(bus2ip_resetn);
end if;
end process REG_RESET_FROM_IPIF;
---------------------------------------------------------------------------
-- Interrupts
---------------------------------------------------------------------------
INTR_CTRLR_GEN : if (C_INTERRUPT_PRESENT = 1) generate
constant NUM_IPIF_IRPT_SRC : natural := 1;
constant NUM_CE : integer := 16;
signal errack_reserved : std_logic_vector(0 to 1);
signal ipif_lvl_interrupts : std_logic_vector(0 to
NUM_IPIF_IRPT_SRC-1);
begin
ipif_lvl_interrupts <= (others => '0');
errack_reserved <= (others => '0');
--- Addr 0X11c, 0X120, 0X128 valid addresses, remaining are holes
Intrpt_bus2ip_rdce <= "0000000" & bus2ip_rdce(11) & bus2ip_rdce(12) & '0'
& bus2ip_rdce(14) & "00000";
Intrpt_bus2ip_wrce <= "0000000" & bus2ip_wrce(11) & bus2ip_wrce(12) & '0'
& bus2ip_wrce(14) & "00000";
intr_rd_ce_or_reduce <= or_reduce(bus2ip_rdce(4 to 10)) or
Bus2IP_RdCE(13) or
or_reduce(Bus2IP_RdCE(15 to 19));
intr_wr_ce_or_reduce <= or_reduce(bus2ip_wrce(4 to 10)) or
bus2ip_wrce(13) or
or_reduce(bus2ip_wrce(15 to 19));
I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2Bus_RdAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_RdAck_intr_reg_hole_d1 <= intr_rd_ce_or_reduce;
ip2Bus_RdAck_intr_reg_hole <= intr_rd_ce_or_reduce and
(not ip2Bus_RdAck_intr_reg_hole_d1);
end if;
end if;
end process I_READ_ACK_INTR_HOLES;
I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_WrAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_WrAck_intr_reg_hole_d1 <= intr_wr_ce_or_reduce;
ip2Bus_WrAck_intr_reg_hole <= intr_wr_ce_or_reduce and
(not ip2Bus_WrAck_intr_reg_hole_d1);
end if;
end if;
end process I_WRITE_ACK_INTR_HOLES;
INTERRUPT_CONTROL_I : entity interrupt_control_v3_1_3.interrupt_control
generic map
(
C_NUM_CE => NUM_CE,
C_NUM_IPIF_IRPT_SRC => NUM_IPIF_IRPT_SRC,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_INCLUDE_DEV_PENCODER => false,
C_INCLUDE_DEV_ISC => false,
C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH
)
port map
(
-- Inputs From the IPIF Bus
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => bus2ip_reset,
Bus2IP_Data => bus2ip_data,
Bus2IP_BE => bus2ip_be,
Interrupt_RdCE => Intrpt_bus2ip_rdce,
Interrupt_WrCE => Intrpt_bus2ip_wrce,
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
IPIF_Reg_Interrupts => errack_reserved,
-- Level Interrupt inputs from the IPIF sources
IPIF_Lvl_Interrupts => ipif_lvl_interrupts,
-- Inputs from the IP Interface
IP2Bus_IntrEvent => ip2bus_intrevent(IP_INTR_MODE_ARRAY'range),
-- Final Device Interrupt Output
Intr2Bus_DevIntr => IP2INTC_Irpt_i,
-- Status Reply Outputs to the Bus
Intr2Bus_DBus => intr2bus_data,
Intr2Bus_WrAck => intr2bus_wrack,
Intr2Bus_RdAck => intr2bus_rdack,
Intr2Bus_Error => intr2bus_error,
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
-- registering interrupt
I_INTR_DELAY: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2intc_irpt <= '0';
else
ip2intc_irpt <= IP2INTC_Irpt_i;
end if;
end if;
end process I_INTR_DELAY;
end generate INTR_CTRLR_GEN;
-----------------------------------------------------------------------
-- Assigning the intr2bus signal to zero's when interrupt is not
-- present
-----------------------------------------------------------------------
REMOVE_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
intr2bus_data <= (others => '0');
ip2intc_irpt <= '0';
intr2bus_error <= '0';
intr2bus_rdack <= '0';
intr2bus_wrack <= '0';
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole <= '0';
end generate REMOVE_INTERRUPT;
gpio_core_1 : entity axi_gpio_v2_0_9.gpio_core
generic map
(
C_DW => C_S_AXI_DATA_WIDTH,
C_AW => C_S_AXI_ADDR_WIDTH,
C_GPIO_WIDTH => C_GPIO_WIDTH,
C_GPIO2_WIDTH => C_GPIO2_WIDTH,
C_MAX_GPIO_WIDTH => MAX_GPIO_WIDTH,
C_INTERRUPT_PRESENT => C_INTERRUPT_PRESENT,
C_DOUT_DEFAULT => C_DOUT_DEFAULT,
C_TRI_DEFAULT => C_TRI_DEFAULT,
C_IS_DUAL => C_IS_DUAL,
C_DOUT_DEFAULT_2 => C_DOUT_DEFAULT_2,
C_TRI_DEFAULT_2 => C_TRI_DEFAULT_2,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Bus2IP_Clk,
Rst => bus2ip_reset,
ABus_Reg => Bus2IP_Addr,
BE_Reg => Bus2IP_BE(0 to C_S_AXI_DATA_WIDTH/8-1),
DBus_Reg => Bus2IP_Data_i(0 to MAX_GPIO_WIDTH-1),
RNW_Reg => Bus2IP_RNW,
GPIO_DBus => IP2Bus_Data(0 to C_S_AXI_DATA_WIDTH-1),
GPIO_xferAck => GPIO_xferAck_i,
GPIO_Select => bus2ip_cs(0),
GPIO_intr => ip2bus_intrevent(0),
GPIO2_intr => ip2bus_intrevent(1),
GPIO_IO_I => gpio_io_i,
GPIO_IO_O => gpio_io_o,
GPIO_IO_T => gpio_io_t,
GPIO2_IO_I => gpio2_io_i,
GPIO2_IO_O => gpio2_io_o,
GPIO2_IO_T => gpio2_io_t
);
Bus2IP_Data_i <= Bus2IP1_Data_i when bus2ip_cs(0) = '1'
and bus2ip_addr (5) = '0'else
Bus2IP2_Data_i;
BUS_CONV_ch1 : for i in 0 to C_GPIO_WIDTH-1 generate
Bus2IP1_Data_i(i) <= Bus2IP_Data(i+
C_S_AXI_DATA_WIDTH-C_GPIO_WIDTH);
end generate BUS_CONV_ch1;
BUS_CONV_ch2 : for i in 0 to C_GPIO2_WIDTH-1 generate
Bus2IP2_Data_i(i) <= Bus2IP_Data(i+
C_S_AXI_DATA_WIDTH-C_GPIO2_WIDTH);
end generate BUS_CONV_ch2;
end architecture imp;
|
-------------------------------------------------------------------------------
-- AXI_GPIO - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_gpio.vhd
-- Version: v2.0
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
-------------------------------------------------------------------------------
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 07/28/09
-- ^^^^^^^^^^^^^^
-- First version of axi_gpio. Based on xps_gpio 2.00a
--
-- KSB 05/20/10
-- ^^^^^^^^^^^^^^
-- Updated for holes in address range
-- ~~~~~~~~~~~~~~
-- VB 09/23/10
-- ^^^^^^^^^^^^^^
-- Updated for axi_lite_ipfi_v1_01_a
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use std.textio.all;
-------------------------------------------------------------------------------
-- AXI common package of the proc common library is used for different
-- function declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_9 library is used for axi4 component declarations
-------------------------------------------------------------------------------
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0_3.ipif_pkg.INTEGER_ARRAY_TYPE;
use axi_lite_ipif_v3_0_3.ipif_pkg.SLV64_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_9 library is used for interrupt controller component
-- declarations
-------------------------------------------------------------------------------
library interrupt_control_v3_1_3;
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_9 library is used for axi_gpio component declarations
-------------------------------------------------------------------------------
library axi_gpio_v2_0_9;
-------------------------------------------------------------------------------
-- Defination of Generics : --
-------------------------------------------------------------------------------
-- AXI generics
-- C_BASEADDR -- Base address of the core
-- C_HIGHADDR -- Permits alias of address space
-- by making greater than xFFF
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address interface (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data interface (in bits)
-- C_FAMILY -- XILINX FPGA family
-- C_INSTANCE -- Instance name ot the core in the EDK system
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_ALL_INPUTS -- Inputs Only.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_IS_BIDIR -- Selects gpio_io_i as input.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_ALL_INPUTS_2 -- Channel2 Inputs only.
-- C_IS_BIDIR_2 -- Selects gpio2_io_i as input.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Defination of Ports --
-------------------------------------------------------------------------------
-- AXI signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- GPIO Signals
-- gpio_io_i -- Channel 1 General purpose I/O in port
-- gpio_io_o -- Channel 1 General purpose I/O out port
-- gpio_io_t -- Channel 1 General purpose I/O
-- TRI-STATE control port
-- gpio2_io_i -- Channel 2 General purpose I/O in port
-- gpio2_io_o -- Channel 2 General purpose I/O out port
-- gpio2_io_t -- Channel 2 General purpose I/O
-- TRI-STATE control port
-- System Signals
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- ip2intc_irpt -- AXI GPIO Interrupt
-------------------------------------------------------------------------------
entity axi_gpio is
generic
(
-- -- System Parameter
C_FAMILY : string := "virtex7";
-- -- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer range 9 to 9 := 9;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
-- -- GPIO Parameter
C_GPIO_WIDTH : integer range 1 to 32 := 32;
C_GPIO2_WIDTH : integer range 1 to 32 := 32;
C_ALL_INPUTS : integer range 0 to 1 := 0;
C_ALL_INPUTS_2 : integer range 0 to 1 := 0;
C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013
C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013
C_INTERRUPT_PRESENT : integer range 0 to 1 := 0;
C_DOUT_DEFAULT : std_logic_vector (31 downto 0) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (31 downto 0) := X"FFFF_FFFF";
C_IS_DUAL : integer range 0 to 1 := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (31 downto 0) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (31 downto 0) := X"FFFF_FFFF"
);
port
(
-- AXI interface Signals --------------------------------------------------
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1
downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1
downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1
downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1
downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1
downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Interrupt---------------------------------------------------------------
ip2intc_irpt : out std_logic;
-- GPIO Signals------------------------------------------------------------
gpio_io_i : in std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio_io_o : out std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio_io_t : out std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio2_io_i : in std_logic_vector(C_GPIO2_WIDTH-1 downto 0);
gpio2_io_o : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0);
gpio2_io_t : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0)
);
-------------------------------------------------------------------------------
-- fan-out attributes for XST
-------------------------------------------------------------------------------
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of s_axi_aclk : signal is "10000";
attribute MAX_FANOUT of s_axi_aresetn : signal is "10000";
-------------------------------------------------------------------------------
-- Attributes for MPD file
-------------------------------------------------------------------------------
attribute IP_GROUP : string ;
attribute IP_GROUP of axi_gpio : entity is "LOGICORE";
attribute SIGIS : string ;
attribute SIGIS of s_axi_aclk : signal is "Clk";
attribute SIGIS of s_axi_aresetn : signal is "Rst";
attribute SIGIS of ip2intc_irpt : signal is "INTR_LEVEL_HIGH";
end entity axi_gpio;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture imp of axi_gpio is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- constant added for webtalk information
-------------------------------------------------------------------------------
--function chr(sl: std_logic) return character is
-- variable c: character;
-- begin
-- case sl is
-- when '0' => c:= '0';
-- when '1' => c:= '1';
-- when 'Z' => c:= 'Z';
-- when 'U' => c:= 'U';
-- when 'X' => c:= 'X';
-- when 'W' => c:= 'W';
-- when 'L' => c:= 'L';
-- when 'H' => c:= 'H';
-- when '-' => c:= '-';
-- end case;
-- return c;
-- end chr;
--
--function str(slv: std_logic_vector) return string is
-- variable result : string (1 to slv'length);
-- variable r : integer;
-- begin
-- r := 1;
-- for i in slv'range loop
-- result(r) := chr(slv(i));
-- r := r + 1;
-- end loop;
-- return result;
-- end str;
type bo2na_type is array (boolean) of natural; -- boolean to
--natural conversion
constant bo2na : bo2na_type := (false => 0, true => 1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
type BOOLEAN_ARRAY_TYPE is array(natural range <>) of boolean;
----------------------------------------------------------------------------
-- This function returns the number of elements that are true in
-- a boolean array.
----------------------------------------------------------------------------
function num_set( ba : BOOLEAN_ARRAY_TYPE ) return natural is
variable n : natural := 0;
begin
for i in ba'range loop
n := n + bo2na(ba(i));
end loop;
return n;
end;
----------------------------------------------------------------------------
-- This function returns a num_ce integer array that is constructed by
-- taking only those elements of superset num_ce integer array
-- that will be defined by the current case.
-- The superset num_ce array is given by parameter num_ce_by_ard.
-- The current case the ard elements that will be used is given
-- by parameter defined_ards.
----------------------------------------------------------------------------
function qual_ard_num_ce_array( defined_ards : BOOLEAN_ARRAY_TYPE;
num_ce_by_ard : INTEGER_ARRAY_TYPE
) return INTEGER_ARRAY_TYPE is
variable res : INTEGER_ARRAY_TYPE(num_set(defined_ards)-1 downto 0);
variable i : natural := 0;
variable j : natural := defined_ards'left;
begin
while i /= res'length loop
-- coverage off
while defined_ards(j) = false loop
j := j+1;
end loop;
-- coverage on
res(i) := num_ce_by_ard(j);
i := i+1;
j := j+1;
end loop;
return res;
end;
----------------------------------------------------------------------------
-- This function returns a addr_range array that is constructed by
-- taking only those elements of superset addr_range array
-- that will be defined by the current case.
-- The superset addr_range array is given by parameter addr_range_by_ard.
-- The current case the ard elements that will be used is given
-- by parameter defined_ards.
----------------------------------------------------------------------------
function qual_ard_addr_range_array( defined_ards : BOOLEAN_ARRAY_TYPE;
addr_range_by_ard : SLV64_ARRAY_TYPE
) return SLV64_ARRAY_TYPE is
variable res : SLV64_ARRAY_TYPE(0 to 2*num_set(defined_ards)-1);
variable i : natural := 0;
variable j : natural := defined_ards'left;
begin
while i /= res'length loop
-- coverage off
while defined_ards(j) = false loop
j := j+1;
end loop;
-- coverage on
res(i) := addr_range_by_ard(2*j);
res(i+1) := addr_range_by_ard((2*j)+1);
i := i+2;
j := j+1;
end loop;
return res;
end;
function qual_ard_ce_valid( defined_ards : BOOLEAN_ARRAY_TYPE
) return std_logic_vector is
variable res : std_logic_vector(0 to 31);
begin
res := (others => '0');
if defined_ards(defined_ards'right) then
res(0 to 3) := "1111";
res(12) := '1';
res(13) := '1';
res(15) := '1';
else
res(0 to 3) := "1111";
end if;
return res;
end;
----------------------------------------------------------------------------
-- This function returns the maximum width amongst the two GPIO Channels
-- and if there is only one channel, it returns just the width of that
-- channel.
----------------------------------------------------------------------------
function max_width( dual_channel : INTEGER;
channel1_width : INTEGER;
channel2_width : INTEGER
) return INTEGER is
begin
if (dual_channel = 0) then
return channel1_width;
else
if (channel1_width > channel2_width) then
return channel1_width;
else
return channel2_width;
end if;
end if;
end;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant C_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) :=
(others => '0');
constant INTR_TYPE : integer := 5;
constant INTR_BASEADDR : std_logic_vector(0 to 31):= X"00000100";
constant INTR_HIGHADDR : std_logic_vector(0 to 31):= X"000001FF";
constant GPIO_HIGHADDR : std_logic_vector(0 to 31):= X"0000000F";
constant MAX_GPIO_WIDTH : integer := max_width
(C_IS_DUAL,C_GPIO_WIDTH,C_GPIO2_WIDTH);
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
qual_ard_addr_range_array(
(true,C_INTERRUPT_PRESENT=1),
(ZERO_ADDR_PAD & X"00000000",
ZERO_ADDR_PAD & GPIO_HIGHADDR,
ZERO_ADDR_PAD & INTR_BASEADDR,
ZERO_ADDR_PAD & INTR_HIGHADDR
)
);
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
qual_ard_num_ce_array(
(true,C_INTERRUPT_PRESENT=1),
(4,16)
);
constant ARD_CE_VALID : std_logic_vector(0 to 31) :=
qual_ard_ce_valid(
(true,C_INTERRUPT_PRESENT=1)
);
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to 0+bo2na(C_IS_DUAL=1))
:= (others => 5);
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 8;
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal ip2bus_intrevent : std_logic_vector(0 to 1);
signal GPIO_xferAck_i : std_logic;
signal Bus2IP_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal Bus2IP1_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal Bus2IP2_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
-- IPIC Used Signals
signal ip2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1);
signal bus2ip_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_rnw : std_logic;
signal bus2ip_cs : std_logic_vector(0 to 0 + bo2na
(C_INTERRUPT_PRESENT=1));
signal bus2ip_rdce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal bus2ip_wrce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal Intrpt_bus2ip_rdce : std_logic_vector(0 to 15);
signal Intrpt_bus2ip_wrce : std_logic_vector(0 to 15);
signal intr_wr_ce_or_reduce : std_logic;
signal intr_rd_ce_or_reduce : std_logic;
signal ip2Bus_RdAck_intr_reg_hole : std_logic;
signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic;
signal ip2Bus_WrAck_intr_reg_hole : std_logic;
signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic;
signal bus2ip_be : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH / 8) - 1);
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
signal bus2ip_resetn : std_logic;
signal intr2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal intr2bus_wrack : std_logic;
signal intr2bus_rdack : std_logic;
signal intr2bus_error : std_logic;
signal ip2bus_data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2bus_data_i_D1 : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2bus_wrack_i : std_logic;
signal ip2bus_wrack_i_D1 : std_logic;
signal ip2bus_rdack_i : std_logic;
signal ip2bus_rdack_i_D1 : std_logic;
signal ip2bus_error_i : std_logic;
signal IP2INTC_Irpt_i : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_3.axi_lite_ipif
generic map
(
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data_i_D1,
IP2Bus_WrAck => ip2bus_wrack_i_D1,
IP2Bus_RdAck => ip2bus_rdack_i_D1,
--IP2Bus_WrAck => ip2bus_wrack_i,
--IP2Bus_RdAck => ip2bus_rdack_i,
IP2Bus_Error => ip2bus_error_i,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => bus2ip_rnw,
Bus2IP_BE => bus2ip_be,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
ip2bus_data_i <= intr2bus_data or ip2bus_data;
ip2bus_wrack_i <= intr2bus_wrack or
(GPIO_xferAck_i and not(bus2ip_rnw)) or
ip2Bus_WrAck_intr_reg_hole;-- Holes in Address range
ip2bus_rdack_i <= intr2bus_rdack or
(GPIO_xferAck_i and bus2ip_rnw) or
ip2Bus_RdAck_intr_reg_hole; -- Holes in Address range
I_WRACK_RDACK_DELAYS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2bus_wrack_i_D1 <= '0';
ip2bus_rdack_i_D1 <= '0';
ip2bus_data_i_D1 <= (others => '0');
else
ip2bus_wrack_i_D1 <= ip2bus_wrack_i;
ip2bus_rdack_i_D1 <= ip2bus_rdack_i;
ip2bus_data_i_D1 <= ip2bus_data_i;
end if;
end if;
end process I_WRACK_RDACK_DELAYS;
ip2bus_error_i <= intr2bus_error;
----------------------
--REG_RESET_FROM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RESET_FROM_IPIF: process (s_axi_aclk) is
begin
if(s_axi_aclk'event and s_axi_aclk = '1') then
bus2ip_reset <= not(bus2ip_resetn);
end if;
end process REG_RESET_FROM_IPIF;
---------------------------------------------------------------------------
-- Interrupts
---------------------------------------------------------------------------
INTR_CTRLR_GEN : if (C_INTERRUPT_PRESENT = 1) generate
constant NUM_IPIF_IRPT_SRC : natural := 1;
constant NUM_CE : integer := 16;
signal errack_reserved : std_logic_vector(0 to 1);
signal ipif_lvl_interrupts : std_logic_vector(0 to
NUM_IPIF_IRPT_SRC-1);
begin
ipif_lvl_interrupts <= (others => '0');
errack_reserved <= (others => '0');
--- Addr 0X11c, 0X120, 0X128 valid addresses, remaining are holes
Intrpt_bus2ip_rdce <= "0000000" & bus2ip_rdce(11) & bus2ip_rdce(12) & '0'
& bus2ip_rdce(14) & "00000";
Intrpt_bus2ip_wrce <= "0000000" & bus2ip_wrce(11) & bus2ip_wrce(12) & '0'
& bus2ip_wrce(14) & "00000";
intr_rd_ce_or_reduce <= or_reduce(bus2ip_rdce(4 to 10)) or
Bus2IP_RdCE(13) or
or_reduce(Bus2IP_RdCE(15 to 19));
intr_wr_ce_or_reduce <= or_reduce(bus2ip_wrce(4 to 10)) or
bus2ip_wrce(13) or
or_reduce(bus2ip_wrce(15 to 19));
I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2Bus_RdAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_RdAck_intr_reg_hole_d1 <= intr_rd_ce_or_reduce;
ip2Bus_RdAck_intr_reg_hole <= intr_rd_ce_or_reduce and
(not ip2Bus_RdAck_intr_reg_hole_d1);
end if;
end if;
end process I_READ_ACK_INTR_HOLES;
I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_WrAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_WrAck_intr_reg_hole_d1 <= intr_wr_ce_or_reduce;
ip2Bus_WrAck_intr_reg_hole <= intr_wr_ce_or_reduce and
(not ip2Bus_WrAck_intr_reg_hole_d1);
end if;
end if;
end process I_WRITE_ACK_INTR_HOLES;
INTERRUPT_CONTROL_I : entity interrupt_control_v3_1_3.interrupt_control
generic map
(
C_NUM_CE => NUM_CE,
C_NUM_IPIF_IRPT_SRC => NUM_IPIF_IRPT_SRC,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_INCLUDE_DEV_PENCODER => false,
C_INCLUDE_DEV_ISC => false,
C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH
)
port map
(
-- Inputs From the IPIF Bus
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => bus2ip_reset,
Bus2IP_Data => bus2ip_data,
Bus2IP_BE => bus2ip_be,
Interrupt_RdCE => Intrpt_bus2ip_rdce,
Interrupt_WrCE => Intrpt_bus2ip_wrce,
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
IPIF_Reg_Interrupts => errack_reserved,
-- Level Interrupt inputs from the IPIF sources
IPIF_Lvl_Interrupts => ipif_lvl_interrupts,
-- Inputs from the IP Interface
IP2Bus_IntrEvent => ip2bus_intrevent(IP_INTR_MODE_ARRAY'range),
-- Final Device Interrupt Output
Intr2Bus_DevIntr => IP2INTC_Irpt_i,
-- Status Reply Outputs to the Bus
Intr2Bus_DBus => intr2bus_data,
Intr2Bus_WrAck => intr2bus_wrack,
Intr2Bus_RdAck => intr2bus_rdack,
Intr2Bus_Error => intr2bus_error,
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
-- registering interrupt
I_INTR_DELAY: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2intc_irpt <= '0';
else
ip2intc_irpt <= IP2INTC_Irpt_i;
end if;
end if;
end process I_INTR_DELAY;
end generate INTR_CTRLR_GEN;
-----------------------------------------------------------------------
-- Assigning the intr2bus signal to zero's when interrupt is not
-- present
-----------------------------------------------------------------------
REMOVE_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
intr2bus_data <= (others => '0');
ip2intc_irpt <= '0';
intr2bus_error <= '0';
intr2bus_rdack <= '0';
intr2bus_wrack <= '0';
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole <= '0';
end generate REMOVE_INTERRUPT;
gpio_core_1 : entity axi_gpio_v2_0_9.gpio_core
generic map
(
C_DW => C_S_AXI_DATA_WIDTH,
C_AW => C_S_AXI_ADDR_WIDTH,
C_GPIO_WIDTH => C_GPIO_WIDTH,
C_GPIO2_WIDTH => C_GPIO2_WIDTH,
C_MAX_GPIO_WIDTH => MAX_GPIO_WIDTH,
C_INTERRUPT_PRESENT => C_INTERRUPT_PRESENT,
C_DOUT_DEFAULT => C_DOUT_DEFAULT,
C_TRI_DEFAULT => C_TRI_DEFAULT,
C_IS_DUAL => C_IS_DUAL,
C_DOUT_DEFAULT_2 => C_DOUT_DEFAULT_2,
C_TRI_DEFAULT_2 => C_TRI_DEFAULT_2,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Bus2IP_Clk,
Rst => bus2ip_reset,
ABus_Reg => Bus2IP_Addr,
BE_Reg => Bus2IP_BE(0 to C_S_AXI_DATA_WIDTH/8-1),
DBus_Reg => Bus2IP_Data_i(0 to MAX_GPIO_WIDTH-1),
RNW_Reg => Bus2IP_RNW,
GPIO_DBus => IP2Bus_Data(0 to C_S_AXI_DATA_WIDTH-1),
GPIO_xferAck => GPIO_xferAck_i,
GPIO_Select => bus2ip_cs(0),
GPIO_intr => ip2bus_intrevent(0),
GPIO2_intr => ip2bus_intrevent(1),
GPIO_IO_I => gpio_io_i,
GPIO_IO_O => gpio_io_o,
GPIO_IO_T => gpio_io_t,
GPIO2_IO_I => gpio2_io_i,
GPIO2_IO_O => gpio2_io_o,
GPIO2_IO_T => gpio2_io_t
);
Bus2IP_Data_i <= Bus2IP1_Data_i when bus2ip_cs(0) = '1'
and bus2ip_addr (5) = '0'else
Bus2IP2_Data_i;
BUS_CONV_ch1 : for i in 0 to C_GPIO_WIDTH-1 generate
Bus2IP1_Data_i(i) <= Bus2IP_Data(i+
C_S_AXI_DATA_WIDTH-C_GPIO_WIDTH);
end generate BUS_CONV_ch1;
BUS_CONV_ch2 : for i in 0 to C_GPIO2_WIDTH-1 generate
Bus2IP2_Data_i(i) <= Bus2IP_Data(i+
C_S_AXI_DATA_WIDTH-C_GPIO2_WIDTH);
end generate BUS_CONV_ch2;
end architecture imp;
|
-------------------------------------------------------------------------------
-- AXI_GPIO - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_gpio.vhd
-- Version: v2.0
-- Description: General Purpose I/O for AXI Interface
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_gpio.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- gpio_core.vhd
-------------------------------------------------------------------------------
-- Author: KSB
-- History:
-- ~~~~~~~~~~~~~~
-- KSB 07/28/09
-- ^^^^^^^^^^^^^^
-- First version of axi_gpio. Based on xps_gpio 2.00a
--
-- KSB 05/20/10
-- ^^^^^^^^^^^^^^
-- Updated for holes in address range
-- ~~~~~~~~~~~~~~
-- VB 09/23/10
-- ^^^^^^^^^^^^^^
-- Updated for axi_lite_ipfi_v1_01_a
-- ~~~~~~~~~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use std.textio.all;
-------------------------------------------------------------------------------
-- AXI common package of the proc common library is used for different
-- function declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_9 library is used for axi4 component declarations
-------------------------------------------------------------------------------
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0_3.ipif_pkg.INTEGER_ARRAY_TYPE;
use axi_lite_ipif_v3_0_3.ipif_pkg.SLV64_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_9 library is used for interrupt controller component
-- declarations
-------------------------------------------------------------------------------
library interrupt_control_v3_1_3;
-------------------------------------------------------------------------------
-- axi_gpio_v2_0_9 library is used for axi_gpio component declarations
-------------------------------------------------------------------------------
library axi_gpio_v2_0_9;
-------------------------------------------------------------------------------
-- Defination of Generics : --
-------------------------------------------------------------------------------
-- AXI generics
-- C_BASEADDR -- Base address of the core
-- C_HIGHADDR -- Permits alias of address space
-- by making greater than xFFF
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address interface (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data interface (in bits)
-- C_FAMILY -- XILINX FPGA family
-- C_INSTANCE -- Instance name ot the core in the EDK system
-- C_GPIO_WIDTH -- GPIO Data Bus width.
-- C_ALL_INPUTS -- Inputs Only.
-- C_INTERRUPT_PRESENT -- GPIO Interrupt.
-- C_IS_BIDIR -- Selects gpio_io_i as input.
-- C_DOUT_DEFAULT -- GPIO_DATA Register reset value.
-- C_TRI_DEFAULT -- GPIO_TRI Register reset value.
-- C_IS_DUAL -- Dual Channel GPIO.
-- C_ALL_INPUTS_2 -- Channel2 Inputs only.
-- C_IS_BIDIR_2 -- Selects gpio2_io_i as input.
-- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value.
-- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Defination of Ports --
-------------------------------------------------------------------------------
-- AXI signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- GPIO Signals
-- gpio_io_i -- Channel 1 General purpose I/O in port
-- gpio_io_o -- Channel 1 General purpose I/O out port
-- gpio_io_t -- Channel 1 General purpose I/O
-- TRI-STATE control port
-- gpio2_io_i -- Channel 2 General purpose I/O in port
-- gpio2_io_o -- Channel 2 General purpose I/O out port
-- gpio2_io_t -- Channel 2 General purpose I/O
-- TRI-STATE control port
-- System Signals
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- ip2intc_irpt -- AXI GPIO Interrupt
-------------------------------------------------------------------------------
entity axi_gpio is
generic
(
-- -- System Parameter
C_FAMILY : string := "virtex7";
-- -- AXI Parameters
C_S_AXI_ADDR_WIDTH : integer range 9 to 9 := 9;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
-- -- GPIO Parameter
C_GPIO_WIDTH : integer range 1 to 32 := 32;
C_GPIO2_WIDTH : integer range 1 to 32 := 32;
C_ALL_INPUTS : integer range 0 to 1 := 0;
C_ALL_INPUTS_2 : integer range 0 to 1 := 0;
C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013
C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013
C_INTERRUPT_PRESENT : integer range 0 to 1 := 0;
C_DOUT_DEFAULT : std_logic_vector (31 downto 0) := X"0000_0000";
C_TRI_DEFAULT : std_logic_vector (31 downto 0) := X"FFFF_FFFF";
C_IS_DUAL : integer range 0 to 1 := 0;
C_DOUT_DEFAULT_2 : std_logic_vector (31 downto 0) := X"0000_0000";
C_TRI_DEFAULT_2 : std_logic_vector (31 downto 0) := X"FFFF_FFFF"
);
port
(
-- AXI interface Signals --------------------------------------------------
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1
downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1
downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1
downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1
downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1
downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Interrupt---------------------------------------------------------------
ip2intc_irpt : out std_logic;
-- GPIO Signals------------------------------------------------------------
gpio_io_i : in std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio_io_o : out std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio_io_t : out std_logic_vector(C_GPIO_WIDTH-1 downto 0);
gpio2_io_i : in std_logic_vector(C_GPIO2_WIDTH-1 downto 0);
gpio2_io_o : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0);
gpio2_io_t : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0)
);
-------------------------------------------------------------------------------
-- fan-out attributes for XST
-------------------------------------------------------------------------------
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of s_axi_aclk : signal is "10000";
attribute MAX_FANOUT of s_axi_aresetn : signal is "10000";
-------------------------------------------------------------------------------
-- Attributes for MPD file
-------------------------------------------------------------------------------
attribute IP_GROUP : string ;
attribute IP_GROUP of axi_gpio : entity is "LOGICORE";
attribute SIGIS : string ;
attribute SIGIS of s_axi_aclk : signal is "Clk";
attribute SIGIS of s_axi_aresetn : signal is "Rst";
attribute SIGIS of ip2intc_irpt : signal is "INTR_LEVEL_HIGH";
end entity axi_gpio;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture imp of axi_gpio is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- constant added for webtalk information
-------------------------------------------------------------------------------
--function chr(sl: std_logic) return character is
-- variable c: character;
-- begin
-- case sl is
-- when '0' => c:= '0';
-- when '1' => c:= '1';
-- when 'Z' => c:= 'Z';
-- when 'U' => c:= 'U';
-- when 'X' => c:= 'X';
-- when 'W' => c:= 'W';
-- when 'L' => c:= 'L';
-- when 'H' => c:= 'H';
-- when '-' => c:= '-';
-- end case;
-- return c;
-- end chr;
--
--function str(slv: std_logic_vector) return string is
-- variable result : string (1 to slv'length);
-- variable r : integer;
-- begin
-- r := 1;
-- for i in slv'range loop
-- result(r) := chr(slv(i));
-- r := r + 1;
-- end loop;
-- return result;
-- end str;
type bo2na_type is array (boolean) of natural; -- boolean to
--natural conversion
constant bo2na : bo2na_type := (false => 0, true => 1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
type BOOLEAN_ARRAY_TYPE is array(natural range <>) of boolean;
----------------------------------------------------------------------------
-- This function returns the number of elements that are true in
-- a boolean array.
----------------------------------------------------------------------------
function num_set( ba : BOOLEAN_ARRAY_TYPE ) return natural is
variable n : natural := 0;
begin
for i in ba'range loop
n := n + bo2na(ba(i));
end loop;
return n;
end;
----------------------------------------------------------------------------
-- This function returns a num_ce integer array that is constructed by
-- taking only those elements of superset num_ce integer array
-- that will be defined by the current case.
-- The superset num_ce array is given by parameter num_ce_by_ard.
-- The current case the ard elements that will be used is given
-- by parameter defined_ards.
----------------------------------------------------------------------------
function qual_ard_num_ce_array( defined_ards : BOOLEAN_ARRAY_TYPE;
num_ce_by_ard : INTEGER_ARRAY_TYPE
) return INTEGER_ARRAY_TYPE is
variable res : INTEGER_ARRAY_TYPE(num_set(defined_ards)-1 downto 0);
variable i : natural := 0;
variable j : natural := defined_ards'left;
begin
while i /= res'length loop
-- coverage off
while defined_ards(j) = false loop
j := j+1;
end loop;
-- coverage on
res(i) := num_ce_by_ard(j);
i := i+1;
j := j+1;
end loop;
return res;
end;
----------------------------------------------------------------------------
-- This function returns a addr_range array that is constructed by
-- taking only those elements of superset addr_range array
-- that will be defined by the current case.
-- The superset addr_range array is given by parameter addr_range_by_ard.
-- The current case the ard elements that will be used is given
-- by parameter defined_ards.
----------------------------------------------------------------------------
function qual_ard_addr_range_array( defined_ards : BOOLEAN_ARRAY_TYPE;
addr_range_by_ard : SLV64_ARRAY_TYPE
) return SLV64_ARRAY_TYPE is
variable res : SLV64_ARRAY_TYPE(0 to 2*num_set(defined_ards)-1);
variable i : natural := 0;
variable j : natural := defined_ards'left;
begin
while i /= res'length loop
-- coverage off
while defined_ards(j) = false loop
j := j+1;
end loop;
-- coverage on
res(i) := addr_range_by_ard(2*j);
res(i+1) := addr_range_by_ard((2*j)+1);
i := i+2;
j := j+1;
end loop;
return res;
end;
function qual_ard_ce_valid( defined_ards : BOOLEAN_ARRAY_TYPE
) return std_logic_vector is
variable res : std_logic_vector(0 to 31);
begin
res := (others => '0');
if defined_ards(defined_ards'right) then
res(0 to 3) := "1111";
res(12) := '1';
res(13) := '1';
res(15) := '1';
else
res(0 to 3) := "1111";
end if;
return res;
end;
----------------------------------------------------------------------------
-- This function returns the maximum width amongst the two GPIO Channels
-- and if there is only one channel, it returns just the width of that
-- channel.
----------------------------------------------------------------------------
function max_width( dual_channel : INTEGER;
channel1_width : INTEGER;
channel2_width : INTEGER
) return INTEGER is
begin
if (dual_channel = 0) then
return channel1_width;
else
if (channel1_width > channel2_width) then
return channel1_width;
else
return channel2_width;
end if;
end if;
end;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant C_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) :=
(others => '0');
constant INTR_TYPE : integer := 5;
constant INTR_BASEADDR : std_logic_vector(0 to 31):= X"00000100";
constant INTR_HIGHADDR : std_logic_vector(0 to 31):= X"000001FF";
constant GPIO_HIGHADDR : std_logic_vector(0 to 31):= X"0000000F";
constant MAX_GPIO_WIDTH : integer := max_width
(C_IS_DUAL,C_GPIO_WIDTH,C_GPIO2_WIDTH);
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
qual_ard_addr_range_array(
(true,C_INTERRUPT_PRESENT=1),
(ZERO_ADDR_PAD & X"00000000",
ZERO_ADDR_PAD & GPIO_HIGHADDR,
ZERO_ADDR_PAD & INTR_BASEADDR,
ZERO_ADDR_PAD & INTR_HIGHADDR
)
);
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
qual_ard_num_ce_array(
(true,C_INTERRUPT_PRESENT=1),
(4,16)
);
constant ARD_CE_VALID : std_logic_vector(0 to 31) :=
qual_ard_ce_valid(
(true,C_INTERRUPT_PRESENT=1)
);
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to 0+bo2na(C_IS_DUAL=1))
:= (others => 5);
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 8;
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal ip2bus_intrevent : std_logic_vector(0 to 1);
signal GPIO_xferAck_i : std_logic;
signal Bus2IP_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal Bus2IP1_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal Bus2IP2_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
-- IPIC Used Signals
signal ip2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1);
signal bus2ip_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_rnw : std_logic;
signal bus2ip_cs : std_logic_vector(0 to 0 + bo2na
(C_INTERRUPT_PRESENT=1));
signal bus2ip_rdce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal bus2ip_wrce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1);
signal Intrpt_bus2ip_rdce : std_logic_vector(0 to 15);
signal Intrpt_bus2ip_wrce : std_logic_vector(0 to 15);
signal intr_wr_ce_or_reduce : std_logic;
signal intr_rd_ce_or_reduce : std_logic;
signal ip2Bus_RdAck_intr_reg_hole : std_logic;
signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic;
signal ip2Bus_WrAck_intr_reg_hole : std_logic;
signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic;
signal bus2ip_be : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH / 8) - 1);
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
signal bus2ip_resetn : std_logic;
signal intr2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal intr2bus_wrack : std_logic;
signal intr2bus_rdack : std_logic;
signal intr2bus_error : std_logic;
signal ip2bus_data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2bus_data_i_D1 : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
signal ip2bus_wrack_i : std_logic;
signal ip2bus_wrack_i_D1 : std_logic;
signal ip2bus_rdack_i : std_logic;
signal ip2bus_rdack_i_D1 : std_logic;
signal ip2bus_error_i : std_logic;
signal IP2INTC_Irpt_i : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_3.axi_lite_ipif
generic map
(
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data_i_D1,
IP2Bus_WrAck => ip2bus_wrack_i_D1,
IP2Bus_RdAck => ip2bus_rdack_i_D1,
--IP2Bus_WrAck => ip2bus_wrack_i,
--IP2Bus_RdAck => ip2bus_rdack_i,
IP2Bus_Error => ip2bus_error_i,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => bus2ip_rnw,
Bus2IP_BE => bus2ip_be,
Bus2IP_CS => bus2ip_cs,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
ip2bus_data_i <= intr2bus_data or ip2bus_data;
ip2bus_wrack_i <= intr2bus_wrack or
(GPIO_xferAck_i and not(bus2ip_rnw)) or
ip2Bus_WrAck_intr_reg_hole;-- Holes in Address range
ip2bus_rdack_i <= intr2bus_rdack or
(GPIO_xferAck_i and bus2ip_rnw) or
ip2Bus_RdAck_intr_reg_hole; -- Holes in Address range
I_WRACK_RDACK_DELAYS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2bus_wrack_i_D1 <= '0';
ip2bus_rdack_i_D1 <= '0';
ip2bus_data_i_D1 <= (others => '0');
else
ip2bus_wrack_i_D1 <= ip2bus_wrack_i;
ip2bus_rdack_i_D1 <= ip2bus_rdack_i;
ip2bus_data_i_D1 <= ip2bus_data_i;
end if;
end if;
end process I_WRACK_RDACK_DELAYS;
ip2bus_error_i <= intr2bus_error;
----------------------
--REG_RESET_FROM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RESET_FROM_IPIF: process (s_axi_aclk) is
begin
if(s_axi_aclk'event and s_axi_aclk = '1') then
bus2ip_reset <= not(bus2ip_resetn);
end if;
end process REG_RESET_FROM_IPIF;
---------------------------------------------------------------------------
-- Interrupts
---------------------------------------------------------------------------
INTR_CTRLR_GEN : if (C_INTERRUPT_PRESENT = 1) generate
constant NUM_IPIF_IRPT_SRC : natural := 1;
constant NUM_CE : integer := 16;
signal errack_reserved : std_logic_vector(0 to 1);
signal ipif_lvl_interrupts : std_logic_vector(0 to
NUM_IPIF_IRPT_SRC-1);
begin
ipif_lvl_interrupts <= (others => '0');
errack_reserved <= (others => '0');
--- Addr 0X11c, 0X120, 0X128 valid addresses, remaining are holes
Intrpt_bus2ip_rdce <= "0000000" & bus2ip_rdce(11) & bus2ip_rdce(12) & '0'
& bus2ip_rdce(14) & "00000";
Intrpt_bus2ip_wrce <= "0000000" & bus2ip_wrce(11) & bus2ip_wrce(12) & '0'
& bus2ip_wrce(14) & "00000";
intr_rd_ce_or_reduce <= or_reduce(bus2ip_rdce(4 to 10)) or
Bus2IP_RdCE(13) or
or_reduce(Bus2IP_RdCE(15 to 19));
intr_wr_ce_or_reduce <= or_reduce(bus2ip_wrce(4 to 10)) or
bus2ip_wrce(13) or
or_reduce(bus2ip_wrce(15 to 19));
I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2Bus_RdAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_RdAck_intr_reg_hole_d1 <= intr_rd_ce_or_reduce;
ip2Bus_RdAck_intr_reg_hole <= intr_rd_ce_or_reduce and
(not ip2Bus_RdAck_intr_reg_hole_d1);
end if;
end if;
end process I_READ_ACK_INTR_HOLES;
I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_WrAck_intr_reg_hole_d1 <= '0';
else
ip2Bus_WrAck_intr_reg_hole_d1 <= intr_wr_ce_or_reduce;
ip2Bus_WrAck_intr_reg_hole <= intr_wr_ce_or_reduce and
(not ip2Bus_WrAck_intr_reg_hole_d1);
end if;
end if;
end process I_WRITE_ACK_INTR_HOLES;
INTERRUPT_CONTROL_I : entity interrupt_control_v3_1_3.interrupt_control
generic map
(
C_NUM_CE => NUM_CE,
C_NUM_IPIF_IRPT_SRC => NUM_IPIF_IRPT_SRC,
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
C_INCLUDE_DEV_PENCODER => false,
C_INCLUDE_DEV_ISC => false,
C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH
)
port map
(
-- Inputs From the IPIF Bus
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => bus2ip_reset,
Bus2IP_Data => bus2ip_data,
Bus2IP_BE => bus2ip_be,
Interrupt_RdCE => Intrpt_bus2ip_rdce,
Interrupt_WrCE => Intrpt_bus2ip_wrce,
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
IPIF_Reg_Interrupts => errack_reserved,
-- Level Interrupt inputs from the IPIF sources
IPIF_Lvl_Interrupts => ipif_lvl_interrupts,
-- Inputs from the IP Interface
IP2Bus_IntrEvent => ip2bus_intrevent(IP_INTR_MODE_ARRAY'range),
-- Final Device Interrupt Output
Intr2Bus_DevIntr => IP2INTC_Irpt_i,
-- Status Reply Outputs to the Bus
Intr2Bus_DBus => intr2bus_data,
Intr2Bus_WrAck => intr2bus_wrack,
Intr2Bus_RdAck => intr2bus_rdack,
Intr2Bus_Error => intr2bus_error,
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
-- registering interrupt
I_INTR_DELAY: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (bus2ip_reset = '1') then
ip2intc_irpt <= '0';
else
ip2intc_irpt <= IP2INTC_Irpt_i;
end if;
end if;
end process I_INTR_DELAY;
end generate INTR_CTRLR_GEN;
-----------------------------------------------------------------------
-- Assigning the intr2bus signal to zero's when interrupt is not
-- present
-----------------------------------------------------------------------
REMOVE_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate
intr2bus_data <= (others => '0');
ip2intc_irpt <= '0';
intr2bus_error <= '0';
intr2bus_rdack <= '0';
intr2bus_wrack <= '0';
ip2Bus_WrAck_intr_reg_hole <= '0';
ip2Bus_RdAck_intr_reg_hole <= '0';
end generate REMOVE_INTERRUPT;
gpio_core_1 : entity axi_gpio_v2_0_9.gpio_core
generic map
(
C_DW => C_S_AXI_DATA_WIDTH,
C_AW => C_S_AXI_ADDR_WIDTH,
C_GPIO_WIDTH => C_GPIO_WIDTH,
C_GPIO2_WIDTH => C_GPIO2_WIDTH,
C_MAX_GPIO_WIDTH => MAX_GPIO_WIDTH,
C_INTERRUPT_PRESENT => C_INTERRUPT_PRESENT,
C_DOUT_DEFAULT => C_DOUT_DEFAULT,
C_TRI_DEFAULT => C_TRI_DEFAULT,
C_IS_DUAL => C_IS_DUAL,
C_DOUT_DEFAULT_2 => C_DOUT_DEFAULT_2,
C_TRI_DEFAULT_2 => C_TRI_DEFAULT_2,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Bus2IP_Clk,
Rst => bus2ip_reset,
ABus_Reg => Bus2IP_Addr,
BE_Reg => Bus2IP_BE(0 to C_S_AXI_DATA_WIDTH/8-1),
DBus_Reg => Bus2IP_Data_i(0 to MAX_GPIO_WIDTH-1),
RNW_Reg => Bus2IP_RNW,
GPIO_DBus => IP2Bus_Data(0 to C_S_AXI_DATA_WIDTH-1),
GPIO_xferAck => GPIO_xferAck_i,
GPIO_Select => bus2ip_cs(0),
GPIO_intr => ip2bus_intrevent(0),
GPIO2_intr => ip2bus_intrevent(1),
GPIO_IO_I => gpio_io_i,
GPIO_IO_O => gpio_io_o,
GPIO_IO_T => gpio_io_t,
GPIO2_IO_I => gpio2_io_i,
GPIO2_IO_O => gpio2_io_o,
GPIO2_IO_T => gpio2_io_t
);
Bus2IP_Data_i <= Bus2IP1_Data_i when bus2ip_cs(0) = '1'
and bus2ip_addr (5) = '0'else
Bus2IP2_Data_i;
BUS_CONV_ch1 : for i in 0 to C_GPIO_WIDTH-1 generate
Bus2IP1_Data_i(i) <= Bus2IP_Data(i+
C_S_AXI_DATA_WIDTH-C_GPIO_WIDTH);
end generate BUS_CONV_ch1;
BUS_CONV_ch2 : for i in 0 to C_GPIO2_WIDTH-1 generate
Bus2IP2_Data_i(i) <= Bus2IP_Data(i+
C_S_AXI_DATA_WIDTH-C_GPIO2_WIDTH);
end generate BUS_CONV_ch2;
end architecture imp;
|
entity e is
end entity;
architecture a of e is
type foo is (a, b, c);
type bar is (a, b, c);
signal x : foo := a;
signal y : bar := b;
begin
process is
begin
x <= c;
y <= a;
end process;
process is
begin
x <= foo'(a);
y <= bar'(a);
end process;
process is
type baz is (a, b, c, d);
variable z : baz := b;
begin
z := d;
z := a;
x <= a;
end process;
process is
begin
x <= bar'(c); -- Error!
end process;
process is
type small is range 10 downto -5;
variable z : small := -5;
variable a : boolean;
begin
a := z = -5;
a := -5 = z;
end process;
process is
variable a : bit_vector(3 downto 0);
variable x : character;
variable b : boolean;
begin
b := x = '1'; -- OK
b := '1' = x; -- OK
b := a = ('0', '1', '0', '1'); -- OK
b := ('0', '1', '0', '1') = a; -- OK
b := ('0', '1') = ('0', '1'); -- Error
end process;
process is
subtype some_foo is foo range a to b;
subtype less_foo is some_foo range a to a;
subtype all_foo is foo;
variable f : some_foo;
variable g : all_foo;
variable h : less_foo;
begin
f := a; -- OK
f := c; -- OK at semantic check
g := f; -- OK
g := h; -- OK
end process;
process is
type weird is ( '¢', '¦' );
variable x : weird;
variable y : character;
begin
x := '¢';
y := '¢';
report "foo¥bar";
end process;
process is
type t is (false, true);
begin
for i in false to false loop -- Error
end loop;
end process;
process is
function now return integer;
begin
for i in now to now loop -- Error
end loop;
end process;
process is
function false return integer is
begin
return 1;
end function;
begin
for i in false to false loop -- Error
end loop;
end process;
process is
function "="(a, b : foo) return boolean is
begin
return false;
end function;
variable x, y : foo;
begin
assert x = y; -- OK
end process;
end architecture;
package pack is
type my_int is range 1 to 10;
end package;
use work.pack.all;
package pack2 is
function "<"(a, b: my_int) return boolean;
end package;
use work.pack2.all;
use work.pack.all;
architecture a2 of e is
function ">"(a, b: my_int) return boolean;
begin
process is
variable x, y : my_int;
begin
assert x > y; -- OK
assert x < y; -- Error
end process;
end architecture;
architecture a3 of e is
type unsigned is array (natural range <>) of bit;
function "*"(a, b : unsigned) return bit_vector;
function "*"(a, b : bit_vector) return bit_vector;
function "*"(a, b : unsigned) return unsigned;
function "+"(a, b : unsigned) return bit_vector;
function "+"(a, b : bit_vector) return bit_vector;
function "+"(a, b : unsigned) return unsigned;
signal x, y, z : bit_vector(7 downto 0);
begin
x <= unsigned(y) * unsigned(z) + unsigned(z);
end architecture;
-- Test case reduced from Altera model
architecture a4 of e is
function resolved (x : bit_vector) return bit;
subtype rbit is resolved bit;
type rbit_vector is array (natural range <>) of rbit;
function "and" (x, y : rbit_vector) return rbit_vector;
signal mdio_wr : rbit;
signal reg_addr : rbit_vector(15 downto 0);
begin
process is
begin
assert ((X"0000" & mdio_wr) and reg_addr) /= X"0000";
end process;
end architecture;
architecture issue61 of e is
type ubit_vector is array (natural range <>) of bit;
begin
process is
variable x: bit_vector(4 downto 0);
variable y: ubit_vector(6 downto 0);
begin
y := ubit_vector(x & ('0' & '1'));
y := ubit_vector((x & '0') & '1');
y := ubit_vector(x & '0' & '1');
wait;
end process;
end architecture;
architecture cassign of e is
function "="(x, y : bit) return bit;
signal x, y, z : bit;
begin
x <= '1' when y = z else '0'; -- OK
end architecture;
-- -*- coding: latin-1; -*-
|
entity e is
end entity;
architecture a of e is
type foo is (a, b, c);
type bar is (a, b, c);
signal x : foo := a;
signal y : bar := b;
begin
process is
begin
x <= c;
y <= a;
end process;
process is
begin
x <= foo'(a);
y <= bar'(a);
end process;
process is
type baz is (a, b, c, d);
variable z : baz := b;
begin
z := d;
z := a;
x <= a;
end process;
process is
begin
x <= bar'(c); -- Error!
end process;
process is
type small is range 10 downto -5;
variable z : small := -5;
variable a : boolean;
begin
a := z = -5;
a := -5 = z;
end process;
process is
variable a : bit_vector(3 downto 0);
variable x : character;
variable b : boolean;
begin
b := x = '1'; -- OK
b := '1' = x; -- OK
b := a = ('0', '1', '0', '1'); -- OK
b := ('0', '1', '0', '1') = a; -- OK
b := ('0', '1') = ('0', '1'); -- Error
end process;
process is
subtype some_foo is foo range a to b;
subtype less_foo is some_foo range a to a;
subtype all_foo is foo;
variable f : some_foo;
variable g : all_foo;
variable h : less_foo;
begin
f := a; -- OK
f := c; -- OK at semantic check
g := f; -- OK
g := h; -- OK
end process;
process is
type weird is ( '¢', '¦' );
variable x : weird;
variable y : character;
begin
x := '¢';
y := '¢';
report "foo¥bar";
end process;
process is
type t is (false, true);
begin
for i in false to false loop -- Error
end loop;
end process;
process is
function now return integer;
begin
for i in now to now loop -- Error
end loop;
end process;
process is
function false return integer is
begin
return 1;
end function;
begin
for i in false to false loop -- Error
end loop;
end process;
process is
function "="(a, b : foo) return boolean is
begin
return false;
end function;
variable x, y : foo;
begin
assert x = y; -- OK
end process;
end architecture;
package pack is
type my_int is range 1 to 10;
end package;
use work.pack.all;
package pack2 is
function "<"(a, b: my_int) return boolean;
end package;
use work.pack2.all;
use work.pack.all;
architecture a2 of e is
function ">"(a, b: my_int) return boolean;
begin
process is
variable x, y : my_int;
begin
assert x > y; -- OK
assert x < y; -- Error
end process;
end architecture;
architecture a3 of e is
type unsigned is array (natural range <>) of bit;
function "*"(a, b : unsigned) return bit_vector;
function "*"(a, b : bit_vector) return bit_vector;
function "*"(a, b : unsigned) return unsigned;
function "+"(a, b : unsigned) return bit_vector;
function "+"(a, b : bit_vector) return bit_vector;
function "+"(a, b : unsigned) return unsigned;
signal x, y, z : bit_vector(7 downto 0);
begin
x <= unsigned(y) * unsigned(z) + unsigned(z);
end architecture;
-- Test case reduced from Altera model
architecture a4 of e is
function resolved (x : bit_vector) return bit;
subtype rbit is resolved bit;
type rbit_vector is array (natural range <>) of rbit;
function "and" (x, y : rbit_vector) return rbit_vector;
signal mdio_wr : rbit;
signal reg_addr : rbit_vector(15 downto 0);
begin
process is
begin
assert ((X"0000" & mdio_wr) and reg_addr) /= X"0000";
end process;
end architecture;
architecture issue61 of e is
type ubit_vector is array (natural range <>) of bit;
begin
process is
variable x: bit_vector(4 downto 0);
variable y: ubit_vector(6 downto 0);
begin
y := ubit_vector(x & ('0' & '1'));
y := ubit_vector((x & '0') & '1');
y := ubit_vector(x & '0' & '1');
wait;
end process;
end architecture;
architecture cassign of e is
function "="(x, y : bit) return bit;
signal x, y, z : bit;
begin
x <= '1' when y = z else '0'; -- OK
end architecture;
-- -*- coding: latin-1; -*-
|
entity e is
end entity;
architecture a of e is
type foo is (a, b, c);
type bar is (a, b, c);
signal x : foo := a;
signal y : bar := b;
begin
process is
begin
x <= c;
y <= a;
end process;
process is
begin
x <= foo'(a);
y <= bar'(a);
end process;
process is
type baz is (a, b, c, d);
variable z : baz := b;
begin
z := d;
z := a;
x <= a;
end process;
process is
begin
x <= bar'(c); -- Error!
end process;
process is
type small is range 10 downto -5;
variable z : small := -5;
variable a : boolean;
begin
a := z = -5;
a := -5 = z;
end process;
process is
variable a : bit_vector(3 downto 0);
variable x : character;
variable b : boolean;
begin
b := x = '1'; -- OK
b := '1' = x; -- OK
b := a = ('0', '1', '0', '1'); -- OK
b := ('0', '1', '0', '1') = a; -- OK
b := ('0', '1') = ('0', '1'); -- Error
end process;
process is
subtype some_foo is foo range a to b;
subtype less_foo is some_foo range a to a;
subtype all_foo is foo;
variable f : some_foo;
variable g : all_foo;
variable h : less_foo;
begin
f := a; -- OK
f := c; -- OK at semantic check
g := f; -- OK
g := h; -- OK
end process;
process is
type weird is ( '¢', '¦' );
variable x : weird;
variable y : character;
begin
x := '¢';
y := '¢';
report "foo¥bar";
end process;
process is
type t is (false, true);
begin
for i in false to false loop -- Error
end loop;
end process;
process is
function now return integer;
begin
for i in now to now loop -- Error
end loop;
end process;
process is
function false return integer is
begin
return 1;
end function;
begin
for i in false to false loop -- Error
end loop;
end process;
process is
function "="(a, b : foo) return boolean is
begin
return false;
end function;
variable x, y : foo;
begin
assert x = y; -- OK
end process;
end architecture;
package pack is
type my_int is range 1 to 10;
end package;
use work.pack.all;
package pack2 is
function "<"(a, b: my_int) return boolean;
end package;
use work.pack2.all;
use work.pack.all;
architecture a2 of e is
function ">"(a, b: my_int) return boolean;
begin
process is
variable x, y : my_int;
begin
assert x > y; -- OK
assert x < y; -- Error
end process;
end architecture;
architecture a3 of e is
type unsigned is array (natural range <>) of bit;
function "*"(a, b : unsigned) return bit_vector;
function "*"(a, b : bit_vector) return bit_vector;
function "*"(a, b : unsigned) return unsigned;
function "+"(a, b : unsigned) return bit_vector;
function "+"(a, b : bit_vector) return bit_vector;
function "+"(a, b : unsigned) return unsigned;
signal x, y, z : bit_vector(7 downto 0);
begin
x <= unsigned(y) * unsigned(z) + unsigned(z);
end architecture;
-- Test case reduced from Altera model
architecture a4 of e is
function resolved (x : bit_vector) return bit;
subtype rbit is resolved bit;
type rbit_vector is array (natural range <>) of rbit;
function "and" (x, y : rbit_vector) return rbit_vector;
signal mdio_wr : rbit;
signal reg_addr : rbit_vector(15 downto 0);
begin
process is
begin
assert ((X"0000" & mdio_wr) and reg_addr) /= X"0000";
end process;
end architecture;
architecture issue61 of e is
type ubit_vector is array (natural range <>) of bit;
begin
process is
variable x: bit_vector(4 downto 0);
variable y: ubit_vector(6 downto 0);
begin
y := ubit_vector(x & ('0' & '1'));
y := ubit_vector((x & '0') & '1');
y := ubit_vector(x & '0' & '1');
wait;
end process;
end architecture;
architecture cassign of e is
function "="(x, y : bit) return bit;
signal x, y, z : bit;
begin
x <= '1' when y = z else '0'; -- OK
end architecture;
-- -*- coding: latin-1; -*-
|
entity e is
end entity;
architecture a of e is
type foo is (a, b, c);
type bar is (a, b, c);
signal x : foo := a;
signal y : bar := b;
begin
process is
begin
x <= c;
y <= a;
end process;
process is
begin
x <= foo'(a);
y <= bar'(a);
end process;
process is
type baz is (a, b, c, d);
variable z : baz := b;
begin
z := d;
z := a;
x <= a;
end process;
process is
begin
x <= bar'(c); -- Error!
end process;
process is
type small is range 10 downto -5;
variable z : small := -5;
variable a : boolean;
begin
a := z = -5;
a := -5 = z;
end process;
process is
variable a : bit_vector(3 downto 0);
variable x : character;
variable b : boolean;
begin
b := x = '1'; -- OK
b := '1' = x; -- OK
b := a = ('0', '1', '0', '1'); -- OK
b := ('0', '1', '0', '1') = a; -- OK
b := ('0', '1') = ('0', '1'); -- Error
end process;
process is
subtype some_foo is foo range a to b;
subtype less_foo is some_foo range a to a;
subtype all_foo is foo;
variable f : some_foo;
variable g : all_foo;
variable h : less_foo;
begin
f := a; -- OK
f := c; -- OK at semantic check
g := f; -- OK
g := h; -- OK
end process;
process is
type weird is ( '¢', '¦' );
variable x : weird;
variable y : character;
begin
x := '¢';
y := '¢';
report "foo¥bar";
end process;
process is
type t is (false, true);
begin
for i in false to false loop -- Error
end loop;
end process;
process is
function now return integer;
begin
for i in now to now loop -- Error
end loop;
end process;
process is
function false return integer is
begin
return 1;
end function;
begin
for i in false to false loop -- Error
end loop;
end process;
process is
function "="(a, b : foo) return boolean is
begin
return false;
end function;
variable x, y : foo;
begin
assert x = y; -- OK
end process;
end architecture;
package pack is
type my_int is range 1 to 10;
end package;
use work.pack.all;
package pack2 is
function "<"(a, b: my_int) return boolean;
end package;
use work.pack2.all;
use work.pack.all;
architecture a2 of e is
function ">"(a, b: my_int) return boolean;
begin
process is
variable x, y : my_int;
begin
assert x > y; -- OK
assert x < y; -- Error
end process;
end architecture;
architecture a3 of e is
type unsigned is array (natural range <>) of bit;
function "*"(a, b : unsigned) return bit_vector;
function "*"(a, b : bit_vector) return bit_vector;
function "*"(a, b : unsigned) return unsigned;
function "+"(a, b : unsigned) return bit_vector;
function "+"(a, b : bit_vector) return bit_vector;
function "+"(a, b : unsigned) return unsigned;
signal x, y, z : bit_vector(7 downto 0);
begin
x <= unsigned(y) * unsigned(z) + unsigned(z);
end architecture;
-- Test case reduced from Altera model
architecture a4 of e is
function resolved (x : bit_vector) return bit;
subtype rbit is resolved bit;
type rbit_vector is array (natural range <>) of rbit;
function "and" (x, y : rbit_vector) return rbit_vector;
signal mdio_wr : rbit;
signal reg_addr : rbit_vector(15 downto 0);
begin
process is
begin
assert ((X"0000" & mdio_wr) and reg_addr) /= X"0000";
end process;
end architecture;
architecture issue61 of e is
type ubit_vector is array (natural range <>) of bit;
begin
process is
variable x: bit_vector(4 downto 0);
variable y: ubit_vector(6 downto 0);
begin
y := ubit_vector(x & ('0' & '1'));
y := ubit_vector((x & '0') & '1');
y := ubit_vector(x & '0' & '1');
wait;
end process;
end architecture;
architecture cassign of e is
function "="(x, y : bit) return bit;
signal x, y, z : bit;
begin
x <= '1' when y = z else '0'; -- OK
end architecture;
-- -*- coding: latin-1; -*-
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 752;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"1280000A";
when 16#00064# => romdata <= X"03200000";
when 16#00065# => romdata <= X"05040E00";
when 16#00066# => romdata <= X"8410A133";
when 16#00067# => romdata <= X"C4204000";
when 16#00068# => romdata <= X"0539AE03";
when 16#00069# => romdata <= X"8410A250";
when 16#0006A# => romdata <= X"C4206004";
when 16#0006B# => romdata <= X"050003FC";
when 16#0006C# => romdata <= X"C4206008";
when 16#0006D# => romdata <= X"05000080";
when 16#0006E# => romdata <= X"82100000";
when 16#0006F# => romdata <= X"80A0E000";
when 16#00070# => romdata <= X"02800005";
when 16#00071# => romdata <= X"01000000";
when 16#00072# => romdata <= X"82004002";
when 16#00073# => romdata <= X"10BFFFFC";
when 16#00074# => romdata <= X"8620E001";
when 16#00075# => romdata <= X"3D1003FF";
when 16#00076# => romdata <= X"BC17A3E0";
when 16#00077# => romdata <= X"BC278001";
when 16#00078# => romdata <= X"9C27A060";
when 16#00079# => romdata <= X"03100000";
when 16#0007A# => romdata <= X"07200001";
when 16#0007B# => romdata <= X"8610E200";
when 16#0007C# => romdata <= X"C220E014";
when 16#0007D# => romdata <= X"0500FFC0";
when 16#0007E# => romdata <= X"8410A2FF";
when 16#0007F# => romdata <= X"C420E004";
when 16#00080# => romdata <= X"05000280";
when 16#00081# => romdata <= X"8410A00A";
when 16#00082# => romdata <= X"C420E008";
when 16#00083# => romdata <= X"C420E00C";
when 16#00084# => romdata <= X"050104C0";
when 16#00085# => romdata <= X"8410A313";
when 16#00086# => romdata <= X"C420E004";
when 16#00087# => romdata <= X"84102021";
when 16#00088# => romdata <= X"C420E000";
when 16#00089# => romdata <= X"84102040";
when 16#0008A# => romdata <= X"84A0A001";
when 16#0008B# => romdata <= X"36BFFFFF";
when 16#0008C# => romdata <= X"C4284002";
when 16#0008D# => romdata <= X"84102040";
when 16#0008E# => romdata <= X"84A0A001";
when 16#0008F# => romdata <= X"36BFFFFF";
when 16#00090# => romdata <= X"C6084002";
when 16#00091# => romdata <= X"82006040";
when 16#00092# => romdata <= X"84102040";
when 16#00093# => romdata <= X"84A0A002";
when 16#00094# => romdata <= X"36BFFFFF";
when 16#00095# => romdata <= X"C4304002";
when 16#00096# => romdata <= X"84102040";
when 16#00097# => romdata <= X"84A0A002";
when 16#00098# => romdata <= X"36BFFFFF";
when 16#00099# => romdata <= X"C6104002";
when 16#0009A# => romdata <= X"82006040";
when 16#0009B# => romdata <= X"84102040";
when 16#0009C# => romdata <= X"84A0A004";
when 16#0009D# => romdata <= X"36BFFFFF";
when 16#0009E# => romdata <= X"C4204002";
when 16#0009F# => romdata <= X"84102040";
when 16#000A0# => romdata <= X"84A0A004";
when 16#000A1# => romdata <= X"36BFFFFF";
when 16#000A2# => romdata <= X"C6004002";
when 16#000A3# => romdata <= X"82006040";
when 16#000A4# => romdata <= X"84102040";
when 16#000A5# => romdata <= X"84A0A008";
when 16#000A6# => romdata <= X"36BFFFFF";
when 16#000A7# => romdata <= X"C4384002";
when 16#000A8# => romdata <= X"84102040";
when 16#000A9# => romdata <= X"84A0A008";
when 16#000AA# => romdata <= X"36BFFFFF";
when 16#000AB# => romdata <= X"C8184002";
when 16#000AC# => romdata <= X"10BFFFC9";
when 16#000AD# => romdata <= X"01000000";
when 16#000AE# => romdata <= X"C4004000";
when 16#000AF# => romdata <= X"C4184000";
when 16#000B0# => romdata <= X"C4186010";
when 16#000B1# => romdata <= X"82006020";
when 16#000B2# => romdata <= X"10BFFFF3";
when 16#000B3# => romdata <= X"01000000";
when 16#000B4# => romdata <= X"81C04000";
when 16#000B5# => romdata <= X"01000000";
when 16#000B6# => romdata <= X"01000000";
when 16#000B7# => romdata <= X"01000000";
when 16#000B8# => romdata <= X"00000000";
when 16#000B9# => romdata <= X"00000000";
when 16#000BA# => romdata <= X"00000000";
when 16#000BB# => romdata <= X"00000000";
when 16#000BC# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- Company: Red Diamond
-- Engineer: Alexander Geissler
--
-- Create Date: 23:40:00 11/27/2016
-- Design Name: i2s_tx.vhd
-- Project Name: red-diamond
-- Target Device: EP4CE22C8N
-- Tool Versions: 16.0
-- Description: This is a i2s tx modul. Two 24 bit shift registers clock
-- data to a D/A.
-- Key Features:
-- - configure receiver/transmitter, clock master/slave
-- word select master/slave
-- - ARM AMBA AXI4-Lite Bus (in future)
-- - Justification modes: normal, left, right
-- - Up to 8 I2S instances, configurable in different ways
-- - Testmodes
--
-- Dependencies:
--
-- Revision:
-- Revision 0.1 - File created
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.i2s_pkg.all;
entity i2s_tx is
--generic ( DATA_WIDTH : integer range 16 to 24
--);
port (
-- Synchronous reset
reset_n : in std_logic;
-- Master clock
mclk : in std_logic;
-- I2S interface
-- input
i2s_in : in t_i2s_in;
-- output
i2s_out : out t_i2s_out
);
end entity;
architecture rtl of i2s_tx is
constant c_cos_rom : mem_array := cos_lut;
type t_reg_type is record
word_clock : std_logic;
temp_reg : std_logic_vector(23 downto 0);
counter : std_logic_vector(4 downto 0);
end record;
signal r, r_next : t_reg_type;
begin
comb_proc : process(reset_n, r)
variable v : t_reg_type;
begin
v := r;
v.counter := std_logic_vector(unsigned(r.counter) + 1);
-- toggle word clock when 32bit have been clocked in
if r.counter = b"10000" then -- 32
v.word_clock := not r.word_clock; -- toggle word clock
v.counter := b"00000"; -- reset counter
-- latch data to temporariy register when 32 bit have been counted
if r.word_clock = '0' then
v.temp_reg := i2s_in.l_channel;
else
v.temp_reg := i2s_in.r_channel;
end if;
end if;
-- shift data to output
v.temp_reg(23 downto 1) := r.temp_reg(22 downto 0);
if reset_n = '0' then
v.word_clock := '0'; -- 0=left, 1=right
v.counter := b"00000";
end if;
r_next <= v;
i2s_out.sdata <= r.temp_reg(23);
i2s_out.wclk <= r.word_clock;
end process comb_proc;
seq_proc : process(mclk)
begin
if rising_edge(mclk) then
r <= r_next;
end if;
end process seq_proc;
end rtl;
|
library verilog;
use verilog.vl_types.all;
entity altera_avalon_sc_fifo is
generic(
SYMBOLS_PER_BEAT: integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
USE_STORE_FORWARD: integer := 0;
USE_ALMOST_FULL_IF: integer := 0;
USE_ALMOST_EMPTY_IF: integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS: integer := 1;
DATA_WIDTH : vl_notype;
EMPTY_WIDTH : vl_notype
);
port(
clk : in vl_logic;
reset : in vl_logic;
in_data : in vl_logic_vector;
in_valid : in vl_logic;
in_startofpacket: in vl_logic;
in_endofpacket : in vl_logic;
in_empty : in vl_logic_vector;
in_error : in vl_logic_vector;
in_channel : in vl_logic_vector;
in_ready : out vl_logic;
out_data : out vl_logic_vector;
out_valid : out vl_logic;
out_startofpacket: out vl_logic;
out_endofpacket : out vl_logic;
out_empty : out vl_logic_vector;
out_error : out vl_logic_vector;
out_channel : out vl_logic_vector;
out_ready : in vl_logic;
csr_address : in vl_logic_vector;
csr_write : in vl_logic;
csr_read : in vl_logic;
csr_writedata : in vl_logic_vector(31 downto 0);
csr_readdata : out vl_logic_vector(31 downto 0);
almost_full_data: out vl_logic;
almost_empty_data: out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of SYMBOLS_PER_BEAT : constant is 1;
attribute mti_svvh_generic_type of BITS_PER_SYMBOL : constant is 1;
attribute mti_svvh_generic_type of FIFO_DEPTH : constant is 1;
attribute mti_svvh_generic_type of CHANNEL_WIDTH : constant is 1;
attribute mti_svvh_generic_type of ERROR_WIDTH : constant is 1;
attribute mti_svvh_generic_type of USE_PACKETS : constant is 1;
attribute mti_svvh_generic_type of USE_FILL_LEVEL : constant is 1;
attribute mti_svvh_generic_type of USE_STORE_FORWARD : constant is 1;
attribute mti_svvh_generic_type of USE_ALMOST_FULL_IF : constant is 1;
attribute mti_svvh_generic_type of USE_ALMOST_EMPTY_IF : constant is 1;
attribute mti_svvh_generic_type of EMPTY_LATENCY : constant is 1;
attribute mti_svvh_generic_type of USE_MEMORY_BLOCKS : constant is 1;
attribute mti_svvh_generic_type of DATA_WIDTH : constant is 3;
attribute mti_svvh_generic_type of EMPTY_WIDTH : constant is 3;
end altera_avalon_sc_fifo;
|
library verilog;
use verilog.vl_types.all;
entity altera_avalon_sc_fifo is
generic(
SYMBOLS_PER_BEAT: integer := 1;
BITS_PER_SYMBOL : integer := 8;
FIFO_DEPTH : integer := 16;
CHANNEL_WIDTH : integer := 0;
ERROR_WIDTH : integer := 0;
USE_PACKETS : integer := 0;
USE_FILL_LEVEL : integer := 0;
USE_STORE_FORWARD: integer := 0;
USE_ALMOST_FULL_IF: integer := 0;
USE_ALMOST_EMPTY_IF: integer := 0;
EMPTY_LATENCY : integer := 3;
USE_MEMORY_BLOCKS: integer := 1;
DATA_WIDTH : vl_notype;
EMPTY_WIDTH : vl_notype
);
port(
clk : in vl_logic;
reset : in vl_logic;
in_data : in vl_logic_vector;
in_valid : in vl_logic;
in_startofpacket: in vl_logic;
in_endofpacket : in vl_logic;
in_empty : in vl_logic_vector;
in_error : in vl_logic_vector;
in_channel : in vl_logic_vector;
in_ready : out vl_logic;
out_data : out vl_logic_vector;
out_valid : out vl_logic;
out_startofpacket: out vl_logic;
out_endofpacket : out vl_logic;
out_empty : out vl_logic_vector;
out_error : out vl_logic_vector;
out_channel : out vl_logic_vector;
out_ready : in vl_logic;
csr_address : in vl_logic_vector;
csr_write : in vl_logic;
csr_read : in vl_logic;
csr_writedata : in vl_logic_vector(31 downto 0);
csr_readdata : out vl_logic_vector(31 downto 0);
almost_full_data: out vl_logic;
almost_empty_data: out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of SYMBOLS_PER_BEAT : constant is 1;
attribute mti_svvh_generic_type of BITS_PER_SYMBOL : constant is 1;
attribute mti_svvh_generic_type of FIFO_DEPTH : constant is 1;
attribute mti_svvh_generic_type of CHANNEL_WIDTH : constant is 1;
attribute mti_svvh_generic_type of ERROR_WIDTH : constant is 1;
attribute mti_svvh_generic_type of USE_PACKETS : constant is 1;
attribute mti_svvh_generic_type of USE_FILL_LEVEL : constant is 1;
attribute mti_svvh_generic_type of USE_STORE_FORWARD : constant is 1;
attribute mti_svvh_generic_type of USE_ALMOST_FULL_IF : constant is 1;
attribute mti_svvh_generic_type of USE_ALMOST_EMPTY_IF : constant is 1;
attribute mti_svvh_generic_type of EMPTY_LATENCY : constant is 1;
attribute mti_svvh_generic_type of USE_MEMORY_BLOCKS : constant is 1;
attribute mti_svvh_generic_type of DATA_WIDTH : constant is 3;
attribute mti_svvh_generic_type of EMPTY_WIDTH : constant is 3;
end altera_avalon_sc_fifo;
|
-- $Header: /syn/cvs/rcs/compilers/vhdl/vhd/synattr.vhd,v 1.90.2.14.2.1 2003/07/08 18:06:01 akapoor Exp $
-----------------------------------------------------------------------------
-- --
-- Copyright (c) 1997-2003 by Synplicity, Inc. All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- --
-- Library name: synplify --
-- Package name: attributes --
-- --
-- Description: This package contains declarations for synplify --
-- attributes --
-- --
-- --
-- --
-----------------------------------------------------------------------------
--
-- Definitions used for Scope Integration ----------------
--{tcl set actel "act* 40* 42* 32* 54* ex* ax*"}
--{tcl set altera "max* flex* acex*"}
--{tcl set altera_retiming "flex* acex* apex* mercury* excalibur*"}
--{tcl set apex "apex20k apexii excalibur*"}
--{tcl set apexe "apex20kc apex20ke mercury* stratix* cyclone"}
--{tcl set apex20k "apex20k*"}
--{tcl set lattice "pLSI*"}
--{tcl set mach "mach* isp* gal*"}
--{tcl set quicklogic "pasic* quick* eclipse*"}
--{tcl set lucent "orca*"}
--{tcl set xilinx "xc* vir* spart*"}
--{tcl set virtex "vir* spartan*"}
--{tcl set virtex2 "virtex2*"}
--{tcl set stratix "stratix*"}
--{tcl set triscend "triscend*" }
--{tcl set asic "asic*" }
--{tcl set atmel "fpslic" }
--{tcl set cp_only "apex20k* excalibur* mercury apexii stratix* cyclone spartan* virtex*" }
-------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package attributes is
-- Compiler attributes
-- {family *}
attribute phys_pin_loc : string; -- pin loacatin {objtype port} {desc Placement constarint for pin or pad} {physattr 1}
attribute phys_pin_hslots : string; -- pin loacatin {objtype module} {desc Set of slots or placable IO locations} {physattr 1}
attribute phys_pin_vslots : string; -- pin loacatin {objtype module} {desc Set of slots or placable IO locations} {physattr 1}
attribute phys_halo : string; -- pin loacatin {objtype module cell } {desc Halo to be used for the macros} {physattr 1}
-- syn_enum_encoding specifies the encoding for an enumeration type
attribute syn_enum_encoding : string; -- "onehot", "sequential", "gray" {noscope}
-- syn_encoding specifies the encoding for a state register
attribute syn_encoding : string; -- "onehot", "sequential", "gray", "safe" {objtype fsm} {desc FSM encoding (onehot, sequential, gray, safe)} {default gray} {enum onehot sequential gray safe safe,onehot safe,sequential safe,gray default}
-- syn_allow_retiming specifies if the register can be moved for retiming purpose
-- {family $altera_retiming $virtex $virtex2 $stratix }
attribute syn_allow_retiming : boolean; -- {objtype register} {desc Controls retiming of registers} {default 0}
attribute syn_state_machine : boolean; -- marks reg for SM extraction {noscope}
--
-- syn_preserve prevents optimization across registers it is
-- applied to. syn_preserve on a module/arch is applied to all
-- registers in the module/arch. syn_preserve on a register
-- will preserve redundant copies.
-- Can also be used to preserve redundant copies of instantiated
-- combinational cells.
attribute syn_preserve : boolean; -- {noscope}
-- syn_keep is used on signals keep the signal through optimization
-- so that timing constraints can be placed on the signal later.
-- The timing constraints can be multi-cycle path and clock.
attribute syn_keep : boolean; -- {noscope}
attribute syn_sharing : string; -- "off" or "on" {noscope}
-- syn_evaleffort is used on modules to define the effort to be used in
-- evaluating conditions for control structures. This is useful for
-- those modules that contain while loop or if-then-else conditions
-- that may evaluate to a constant if more effort is applied.
-- The higher this number, the higher the evaluation effort,
-- and consequently the memory requirement and CPU time. The default
-- value is 4.
-- This attribute is not recommended!
attribute syn_evaleffort : integer; -- an integer between 0 and 100 {noscope}
-- syn_cpueffort is used on modules to define the cpu effort to be used in
-- various optimizations (such as BDDs). It may take a value from 1 to 10,
-- with the default being 5. A value of 1 to 4 would result in less CPU
-- time and most likely less optimization, while a value of 6 to 10 would
-- result in longer CPU time and possibly more optimization.
--
-- This attribute is not recommended!
attribute syn_cpueffort : integer; -- an integer between 1 and 10 {noscope}
-- syn_looplimit my be attached to a loop label. It represents the maximum
-- number of loop iterations that are allowed. Use this attribute when
-- Synplify errors out after reaching the maximum loop limit.
attribute syn_looplimit : integer; -- the maximum loop count allowed {noscope}
-- the syn_pmux_slice attribute is used to enable the pmux optimization
-- code on/off. If on at the last architecture, it is carried on the
-- hierarcy chain until it finds an architecture in which the attribute
-- is expicitly set to off.
attribute syn_pmux_slice : boolean; -- a boolean value {noscope}
attribute syn_isclock : boolean; -- {noscope}
-- turn on or off priority mux code
attribute syn_primux : boolean; -- {noscope}
-- General mapping attributes
-- inst/module/arch
--{family *}
attribute syn_resources : string; -- spec resources used by module {noscope} {objtype cell} {desc Specifies resources used by module/architecture}
attribute syn_area : string; -- spec resources used by module {noscope}
attribute syn_noprune : boolean; -- keep object even if outputs unused {noscope} {objtype cell} {desc Retain instance when outputs are unused}
attribute syn_probe : string; -- {objtype signal} {app ~synplify_asic} {desc Send a signal to output port for testing} {enum 0 1}
attribute syn_direct_enable : boolean; -- {objtype signal} {app ~synplify_asic} {desc Prefered clock enable} {default 1} {enum 1}
-- registers
attribute syn_useenables : boolean; -- set to false to disable enable use {objtype register} {app ~synplify_asic} {desc Generate with clock enable pin}
-- registers
attribute syn_reference_clock : string; -- set to the name of the reference clock {objtype register} {desc Override the default clock with the given clock }
-- I/O registers
-- {family $lucent $apex $apexe $xilinx $quicklogic}
attribute syn_useioff : boolean; -- set to false to disable use of I/O FF {objtype global port register} {desc Embed flip-flps in the IO ring}
-- {family $xilinx $apex $apexe}
attribute syn_forward_io_constraints : boolean; -- set to true to forward annotate IO constraints {objtype global} {desc Forward annotate IO constraints}
-- used to specify implementations for dff in actel for now
-- {family $actel}
attribute syn_implement : string; -- "dff", "dffr", "dffs", "dffrs" {noscope}
attribute syn_radhardlevel : string; -- "none", "cc", "tmr", "tmr_cc" {objtype register } {desc Radiation-hardened implementation style} {enum none cc tmr tmr_cc}
-- {family asic}
attribute syn_ideal_net : string; -- {objtype signal} {desc Do not buffer this net during optimization} {enum 1}
-- {family asic}
attribute syn_ideal_network : string; -- {objtype signal} {desc Do not buffer this network during optimization} {enum 1}
-- {family asic}
attribute syn_no_reopt : string; -- {objtype module} {desc Do not resize during reoptimization} {enum 1}
-- {family asic}
attribute syn_wire_load : string; -- {objtype module} {desc Set the wire load model to use for this module} {enum -read-wireloads-}
-- {family *}
-- black box attributes
attribute syn_black_box : boolean; -- disables automatic black box warning {noscope}
-- OLD black box attributes
attribute black_box : boolean; -- disables automatic black box warning {noscope}
attribute black_box_pad_pin : string; -- names of I/O pad connections {noscope}
attribute black_box_tri_pins : string; -- names of tristate ports {noscope}
-- Black box timing attributes
-- tpd : timing propagation delay
-- tsu : timing setup delay
-- tco : timing clock to output delay
attribute syn_tpd1 : string; -- {noscope}
attribute syn_tpd2 : string; -- {noscope}
attribute syn_tpd3 : string; -- {noscope}
attribute syn_tpd4 : string; -- {noscope}
attribute syn_tpd5 : string; -- {noscope}
attribute syn_tpd6 : string; -- {noscope}
attribute syn_tpd7 : string; -- {noscope}
attribute syn_tpd8 : string; -- {noscope}
attribute syn_tpd9 : string; -- {noscope}
attribute syn_tpd10 : string; -- {noscope}
attribute syn_tsu1 : string; -- {noscope}
attribute syn_tsu2 : string; -- {noscope}
attribute syn_tsu3 : string; -- {noscope}
attribute syn_tsu4 : string; -- {noscope}
attribute syn_tsu5 : string; -- {noscope}
attribute syn_tsu6 : string; -- {noscope}
attribute syn_tsu7 : string; -- {noscope}
attribute syn_tsu8 : string; -- {noscope}
attribute syn_tsu9 : string; -- {noscope}
attribute syn_tsu10 : string; -- {noscope}
attribute syn_tco1 : string; -- {noscope}
attribute syn_tco2 : string; -- {noscope}
attribute syn_tco3 : string; -- {noscope}
attribute syn_tco4 : string; -- {noscope}
attribute syn_tco5 : string; -- {noscope}
attribute syn_tco6 : string; -- {noscope}
attribute syn_tco7 : string; -- {noscope}
attribute syn_tco8 : string; -- {noscope}
attribute syn_tco9 : string; -- {noscope}
attribute syn_tco10 : string; -- {noscope}
-- Mapping attributes
-- {family $actel $xilinx $lucent $quicklogic $altera $apex $apexe}
attribute syn_maxfan : integer; -- {objtype input_port register_output cell} {desc Overrides the default fanout}
-- {family $actel $xilinx $lucent $quicklogic $lattice $mach $virtex $virtex2 $triscend $asic $atmel $cp_only}
attribute syn_noclockbuf : boolean; -- {objtype global cell input_port module} {app ~synplify_asic} {desc Use normal input buffer}
-- {family $virtex stratix* }
attribute syn_srlstyle : string; -- {objtype cell global module} {desc Determines how seq. shift comp. are implemented} {default select_srl} {enum virtex (select_srl registers noextractff_srl) stratix(select_srl registers noextractff_srl altshift_tap)}
-- set syn_ramstyle to a value of "registers" to force the ram
-- to be implemented with registers.
-- {family $altera $apex $apexe $xilinx $lucent $quicklogic stratix* }
attribute syn_ramstyle : string; -- {objtype cell global module} {desc Map inferred RAM to registers} {default registers} {desc Special implementation of inferred RAM} {enum Virtex virtex-E spartan2 spartan2e virtex2 virtex2-pro(registers block_ram no_rw_check select_ram) xilinx_default (registers select_ram) stratix (registers block_ram no_rw_check) altera_default (registers block_ram) default (registers) all_enums (registers block_ram no_rw_check select_ram)}
-- {family $virtex2 $altera $apex $apexe $apex20k $lattice $lucent $mach excalibur*}
attribute syn_multstyle : string; -- {objtype cell global module} {default block_mult} {desc Special implementation of multipliers} {enum Virtex virtex-E spartan2 spartan2e virtex2 virtex2-pro(logic block_mult) stratix(logic lpm_mult block_mult) altera_default (logic lpm_mult) all_enums (logic block_mult lpm_mult)}
-- {family $virtex $virtex2}
attribute syn_tops_region_size : integer; -- {objtype global} {desc max. size of valid TOPS region in LUTs} {app amplify}
-- set syn_romstyle to a value of "logic" to force the rom
-- to be implemented with logic, select_rom/block_rom
-- {family $altera $apex $apexe $xilinx}
attribute syn_romstyle : string; -- {objtype cell global module} {desc Controls mapping of inferred ROM} {default logic} {desc Special implementation of inferred ROM} {enum xilinx_default (logic select_rom) altera_default(logic block_rom lpm_rom) default(logic) all_enums (logic select_rom block_rom) }
-- set syn_pipeline to a value 1 to pipeline the module front of it
-- {family $altera $apex $apexe $xilinx}
attribute syn_pipeline : boolean; -- {objtype register} {desc Controls pipelining of registers} {default 1} {desc Special implementation of pipelined module}
-- controls EDIF format. Set true on top level to disable array ports
-- {family *}
attribute syn_noarrayports : boolean; -- {objtype global} {app ~synplify_asic} {desc Disable array ports}
-- controls EDIF port name length. Currently used in Altera
-- {family $altera}
attribute syn_edif_name_length : string; -- {enum Restricted Unrestricted} {default Restricted} {objtype global} {desc Use Restricted for MAXII; Unrestricted for quartus}
-- {family *}
-- controls reconstruction of hierarchy. Set false on top level
-- to disable hierarchy reconstruction.
attribute syn_netlist_hierarchy : boolean; -- {objtype global} {app ~synplify_asic} {desc Enable hierarchy reconstruction}
--
-- syn_hier on an instance/module/architecture can be used
-- to control treatment of the level of hierarchy.
-- "macro" - preserve instantiated netlist
-- "hard" - preserves the interface of the design unit with no exceptions.
-- "remove"- removes level of hierarchy
-- "soft" - managed by Synplify (default)
-- "firm" - preserve during opt, but allow mapping across boundary
--
-- {family *}
attribute syn_hier: string; -- {objtype module} {desc Control hierarchy flattening} {enum proASIC (soft remove flatten firm) xilinx_default(hard soft remove flatten firm) actel_default altera_default all_enums(hard soft macro remove flatten firm) lucent_default (soft macro remove flatten firm) quicklogic_default(soft macro remove flatten firm) default(soft remove flatten firm)}
-- syn_flatten on a module/architecture will flatten out the
-- module all the way down to primitives.
attribute syn_flatten : boolean; -- {noscope}
-- {family $cp_only }
attribute syn_allowed_resources : string; -- {objtype module} {desc Control resource usage in a compile point}
-- Architecture specific attributes
-- Actel
-- {family $actel}
--
-- syn_preserve_sr_priority is used if you want to preserve
-- reset over set priority for DFFRS. Actel FF models produce
-- an X for set and reset active. This attribute costs gates and delay.
attribute syn_preserve_sr_priority : boolean; -- {noscope}
attribute alspin : string ; --{objtype port} {desc Pin locations for Actel I/Os}
attribute alspreserve : boolean ; --{objtype signal} {desc Not collapse a net in Actel}
attribute alsfc : string ; --{noscope}
attribute alsdc : string ; --{noscope}
attribute alsloc : string ; --{noscope}
attribute alscrt : string ; --{noscope}
-- Altera
-- {family $altera $apex $apexe}
attribute altera_implement_style : string; -- placement {noscope}
attribute altera_clique : string; -- placement {noscope}
attribute altera_chip_pin_lc : string; -- placement {objtype port} {desc I/O pin location}
-- inst/module/arch: put comb logic into rom
attribute altera_implement_in_eab : boolean; -- {objtype cell} {desc Implment in Altera EABs, apply to module/component instance name only} {default 1}
attribute altera_lcell: string; -- arch attribute with values of "lut" and "car" {noscope}
-- for lcell config
attribute altera_auto_use_eab : boolean; -- {objtype global} {desc Use EABs automatically} {default 1}
attribute altera_auto_use_esb : boolean; -- {objtype global} {desc Use ESBs automatically} {default 1}
-- Apex
-- {family $apex $apexe}
attribute altera_implement_in_esb : boolean; -- {objtype cell} {desc Implment in Altera ESBs, apply to module/component instance name only} {default 1}
-- Apex
-- {family $apex $apexe}
attribute altera_logiclock_location : string; -- {objtype module} {desc Give the location of LogicLock region } {default floating}
-- Apex
-- {family $apex $apexe}
attribute altera_logiclock_size : string; -- {objtype module} {desc Give the size of LogicLock region} {default auto}
-- {family apex20kc apex20ke excalibur* mercury* cyclone stratix* acex* flex10k* }
attribute altera_io_opendrain : boolean; -- set to true to get opendrain port in APEX {objtype port} {desc Use opendrain capability on port or bit-port.}
-- {family $altera_retiming}
attribute altera_io_powerup : string; -- set to high to get IO FF to powerup high in APEX {objtype port} {desc Powerup high or low on port or bit-port in APEX20KE.}
-- Lattice
-- {family $lattice $quicklogic}
attribute lock: string; -- pin placement {objtype port} {desc Pin locations for Lattice I/Os}
-- Lucent
-- {family $lucent}
attribute din : string; -- orca2 FF placement attribute, use value "" {objtype input_port} {desc Input register goes next to I/O pad}
attribute dout : string; -- orca2 FF placement attribute, use value "" {objtype output_port} {desc Output register goes next to I/O pad}
attribute orca_padtype : string; -- value selects synth pad type {objtype port} {desc Pad type for I/O}
attribute orca_props : string; -- attributes to pass for instance {objtype cell port} {desc Forward annotate attributes to ORCA back-end}
-- Both Lucent and Mach
-- {family $lucent $mach}
attribute loc : string; -- placment attribute {objtype port} {desc Pin location}
-- Quicklogic
-- {family $quicklogic}
-- I/O attributes
attribute ql_padtype : string; -- {objtype port} {desc Override default pad types (use BIDIR, INPUT, CLOCK)} {enum BIDIR INPUT CLOCK}
attribute ql_placement : string; -- {objtype port cell} {desc Placement location}
-- Xilinx
-- {family $xilinx}
-- Instance Placement attributes
attribute xc_loc : string; -- placement (pads) {objtype port} {desc Port placement}
attribute xc_rloc : string; -- see RPMs in xilinx doc {objtype cell} {desc Relative placement specification, use with xc_uset}
attribute xc_uset : string; -- see RPMs in xilinx doc {objtype cell} {desc Assign group name for placement, use with xc_rloc}
-- I/O attributes
attribute xc_fast : boolean; -- {objtype output_port} {desc Fast transition time}
attribute xc_ioff : boolean; -- {noscope}
attribute xc_nodelay : boolean; -- {objtype input_port} {desc Remove input delay}
attribute xc_slow : boolean; -- {objtype output_port} {desc Slow transition time}
attribute xc_ttl : boolean; -- {noscope}
attribute xc_cmos : boolean; -- {noscope}
attribute xc_pullup : boolean; -- add a pullup to I/O {objtype port} {desc Add a pullup}
attribute xc_pulldown : boolean; -- add a pulldown to I/O {objtype port} {desc Add a pulldown}
attribute xc_clockbuftype : string; -- {objtype input_port} {default BUFGDLL} {desc Use the Xilinx BUFGDLL clock buffer}
attribute xc_padtype : string; -- {objtype port} {desc Applies an I/O standard to an I/O buffer}
-- Top level architecture attributes
-- number of global buffers, used only for XC4000, XC4000E
attribute syn_global_buffers : integer; -- {objtype global} {desc Number of global buffers}
attribute xc_use_timespec_for_io : boolean; -- {objtype global} {desc Enable use of from-to timepsec instead of offset for I/O constraint} {default 0}
-- Xilinx Modular Design Flow --
attribute xc_pseudo_pin_loc : string; -- {objtype signal} {default CLB_RrrCcc:CLB_RrrCcc} {desc Pseudo pin location on place and route block }
attribute xc_modular_design : boolean; -- {objtype global } {default 1} {desc Enable modular design flow }
attribute xc_modular_region : string; -- {objtype cell } {default rr#cc#rr#cc} {desc Specifies the number of CLB's for a modular region}
-- Xilinx Incremental Design Flow --
attribute xc_area_group : string; -- {objtype cell } {default rr#cc#rr#cc} {desc Specifies the region where instance should be placed}
-- Black box attributes
-- {family $xilinx}
attribute xc_alias : string; -- cell name change in XNF writer {noscope}
attribute xc_props : string; -- extra XNF attributes to pass for instance {objtype cell} {desc Extra XNF attributes to pass for instance}
attribute xc_map : string; -- used to map entity to fmap/hmap/lut {objtype module} {desc Map entity to fmap/hmap/lut} {enum fmap hmap lut}
attribute xc_isgsr : boolean; -- used to mark port of core with built in GSR {noscope}
attribute syn_tristatetomux : integer ; -- {objtype module global} {desc Threshold for converting tristates to mux}
attribute syn_edif_bit_format : string ; -- {objtype global} {desc Format bus names} {enum %u<%i> %u[%i] %u(%i) %u_%i %u%i %d<%i> %d[%i] %d(%i) %d_%i %d%i %n<%i> %n[%i] %n(%i) %n_%i %n%i}
attribute syn_edif_scalar_format : string; -- {objtype global} {desc Format scaler names} {enum %u %n %d}
attribute xc_fast_auto : boolean; -- {objtype global} {desc Enable automatic fast output buffer use}
-- Triscend
-- {family $triscend}
attribute tr_map : string; -- used to map entity to LUT {objtype module} {desc Map entity to LUT}
attribute syn_props : string; -- extra attributes to pass to EDIF for instance {objtype cell} {desc Extra attributes to pass to EDIF for instance}
-- syn_replicate controls replication of registers
-- {family $virtex $virtex2 $altera $apex $apexe $apex20k}
attribute syn_replicate : boolean; -- {objtype global register} {desc Controls replication of registers} {default 0}
-- {family $xilinx}
attribute syn_verification_options : string; -- {objtype module} {default black_box} {desc Allows a module to be defined as a black_box for verification }
end attributes;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: analogdeviceinc.com:adi:axi_i2s_adi:1.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY adi_common_v1_00_a;
USE adi_common_v1_00_a.axi_i2s_adi;
ENTITY block_design_axi_i2s_adi_0_0 IS
PORT (
DATA_CLK_I : IN STD_LOGIC;
BCLK_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
LRCLK_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
SDATA_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
SDATA_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
MUTEN_O : OUT STD_LOGIC;
DMA_REQ_TX_ACLK : IN STD_LOGIC;
DMA_REQ_TX_RSTN : IN STD_LOGIC;
DMA_REQ_TX_DAVALID : IN STD_LOGIC;
DMA_REQ_TX_DATYPE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_TX_DAREADY : OUT STD_LOGIC;
DMA_REQ_TX_DRVALID : OUT STD_LOGIC;
DMA_REQ_TX_DRTYPE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_TX_DRLAST : OUT STD_LOGIC;
DMA_REQ_TX_DRREADY : IN STD_LOGIC;
DMA_REQ_RX_ACLK : IN STD_LOGIC;
DMA_REQ_RX_RSTN : IN STD_LOGIC;
DMA_REQ_RX_DAVALID : IN STD_LOGIC;
DMA_REQ_RX_DATYPE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_RX_DAREADY : OUT STD_LOGIC;
DMA_REQ_RX_DRVALID : OUT STD_LOGIC;
DMA_REQ_RX_DRTYPE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_RX_DRLAST : OUT STD_LOGIC;
DMA_REQ_RX_DRREADY : IN STD_LOGIC;
S_AXI_ACLK : IN STD_LOGIC;
S_AXI_ARESETN : IN STD_LOGIC;
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_WREADY : INOUT STD_LOGIC;
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : INOUT STD_LOGIC;
S_AXI_AWREADY : INOUT STD_LOGIC
);
END block_design_axi_i2s_adi_0_0;
ARCHITECTURE block_design_axi_i2s_adi_0_0_arch OF block_design_axi_i2s_adi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF block_design_axi_i2s_adi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_i2s_adi IS
GENERIC (
C_SLOT_WIDTH : INTEGER;
C_LRCLK_POL : INTEGER;
C_BCLK_POL : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_DMA_TYPE : INTEGER;
C_NUM_CH : INTEGER;
C_HAS_TX : INTEGER;
C_HAS_RX : INTEGER
);
PORT (
DATA_CLK_I : IN STD_LOGIC;
BCLK_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
LRCLK_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
SDATA_O : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
SDATA_I : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
MUTEN_O : OUT STD_LOGIC;
S_AXIS_ACLK : IN STD_LOGIC;
S_AXIS_ARESETN : IN STD_LOGIC;
S_AXIS_TREADY : OUT STD_LOGIC;
S_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXIS_TLAST : IN STD_LOGIC;
S_AXIS_TVALID : IN STD_LOGIC;
M_AXIS_ACLK : IN STD_LOGIC;
M_AXIS_TREADY : IN STD_LOGIC;
M_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXIS_TLAST : OUT STD_LOGIC;
M_AXIS_TVALID : OUT STD_LOGIC;
M_AXIS_TKEEP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DMA_REQ_TX_ACLK : IN STD_LOGIC;
DMA_REQ_TX_RSTN : IN STD_LOGIC;
DMA_REQ_TX_DAVALID : IN STD_LOGIC;
DMA_REQ_TX_DATYPE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_TX_DAREADY : OUT STD_LOGIC;
DMA_REQ_TX_DRVALID : OUT STD_LOGIC;
DMA_REQ_TX_DRTYPE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_TX_DRLAST : OUT STD_LOGIC;
DMA_REQ_TX_DRREADY : IN STD_LOGIC;
DMA_REQ_RX_ACLK : IN STD_LOGIC;
DMA_REQ_RX_RSTN : IN STD_LOGIC;
DMA_REQ_RX_DAVALID : IN STD_LOGIC;
DMA_REQ_RX_DATYPE : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_RX_DAREADY : OUT STD_LOGIC;
DMA_REQ_RX_DRVALID : OUT STD_LOGIC;
DMA_REQ_RX_DRTYPE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
DMA_REQ_RX_DRLAST : OUT STD_LOGIC;
DMA_REQ_RX_DRREADY : IN STD_LOGIC;
S_AXI_ACLK : IN STD_LOGIC;
S_AXI_ARESETN : IN STD_LOGIC;
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_WREADY : INOUT STD_LOGIC;
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : INOUT STD_LOGIC;
S_AXI_AWREADY : INOUT STD_LOGIC
);
END COMPONENT axi_i2s_adi;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF block_design_axi_i2s_adi_0_0_arch: ARCHITECTURE IS "axi_i2s_adi,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF block_design_axi_i2s_adi_0_0_arch : ARCHITECTURE IS "block_design_axi_i2s_adi_0_0,axi_i2s_adi,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 DMA_TX_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_RSTN: SIGNAL IS "xilinx.com:signal:reset:1.0 DMA_TX_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DAVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_TX_ACK TVALID";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DATYPE: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_TX_ACK TUSER";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DAREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_TX_ACK TREADY";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DRVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_TX_REQ TVALID";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DRTYPE: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_TX_REQ TUSER";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DRLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_TX_REQ TLAST";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_TX_DRREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_TX_REQ TREADY";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 DMA_RX_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_RSTN: SIGNAL IS "xilinx.com:signal:reset:1.0 DMA_RX_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DAVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_RX_ACK TVALID";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DATYPE: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_RX_ACK TUSER";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DAREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_RX_ACK TREADY";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DRVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_RX_REQ TVALID";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DRTYPE: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_RX_REQ TUSER";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DRLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_RX_REQ TLAST";
ATTRIBUTE X_INTERFACE_INFO OF DMA_REQ_RX_DRREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 DMA_RX_REQ TREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ACLK: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARESETN: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_AXI_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
BEGIN
U0 : axi_i2s_adi
GENERIC MAP (
C_SLOT_WIDTH => 24,
C_LRCLK_POL => 0,
C_BCLK_POL => 0,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ADDR_WIDTH => 32,
C_DMA_TYPE => 1,
C_NUM_CH => 1,
C_HAS_TX => 1,
C_HAS_RX => 1
)
PORT MAP (
DATA_CLK_I => DATA_CLK_I,
BCLK_O => BCLK_O,
LRCLK_O => LRCLK_O,
SDATA_O => SDATA_O,
SDATA_I => SDATA_I,
MUTEN_O => MUTEN_O,
S_AXIS_ACLK => '0',
S_AXIS_ARESETN => '0',
S_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_AXIS_TLAST => '0',
S_AXIS_TVALID => '0',
M_AXIS_ACLK => '0',
M_AXIS_TREADY => '0',
DMA_REQ_TX_ACLK => DMA_REQ_TX_ACLK,
DMA_REQ_TX_RSTN => DMA_REQ_TX_RSTN,
DMA_REQ_TX_DAVALID => DMA_REQ_TX_DAVALID,
DMA_REQ_TX_DATYPE => DMA_REQ_TX_DATYPE,
DMA_REQ_TX_DAREADY => DMA_REQ_TX_DAREADY,
DMA_REQ_TX_DRVALID => DMA_REQ_TX_DRVALID,
DMA_REQ_TX_DRTYPE => DMA_REQ_TX_DRTYPE,
DMA_REQ_TX_DRLAST => DMA_REQ_TX_DRLAST,
DMA_REQ_TX_DRREADY => DMA_REQ_TX_DRREADY,
DMA_REQ_RX_ACLK => DMA_REQ_RX_ACLK,
DMA_REQ_RX_RSTN => DMA_REQ_RX_RSTN,
DMA_REQ_RX_DAVALID => DMA_REQ_RX_DAVALID,
DMA_REQ_RX_DATYPE => DMA_REQ_RX_DATYPE,
DMA_REQ_RX_DAREADY => DMA_REQ_RX_DAREADY,
DMA_REQ_RX_DRVALID => DMA_REQ_RX_DRVALID,
DMA_REQ_RX_DRTYPE => DMA_REQ_RX_DRTYPE,
DMA_REQ_RX_DRLAST => DMA_REQ_RX_DRLAST,
DMA_REQ_RX_DRREADY => DMA_REQ_RX_DRREADY,
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY
);
END block_design_axi_i2s_adi_0_0_arch;
|
architecture RTL of FIFO is
attribute coordinate of comp_1 : component is (0.0, 17.5);
attribute coordinate of comp_1 : component is (0.0, 17.5);
-- Violations below
attribute coordinate of comp_1 : component is (0.0, 17.5);
begin
end architecture RTL;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CU is
Port (
--clk : in STD_LOGIC;
op : in STD_LOGIC_VECTOR (1 downto 0);
op2 : in STD_LOGIC_VECTOR (2 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
cond : in STD_LOGIC_VECTOR (3 downto 0);
icc : in STD_LOGIC_VECTOR (3 downto 0);
aluop : out STD_LOGIC_VECTOR (5 downto 0);
en_dm : out STD_LOGIC;
we_dm : out STD_LOGIC;
pc_src: out STD_LOGIC_VECTOR (1 downto 0);
we_rf : out STD_LOGIC;
rf_src: out STD_LOGIC_VECTOR (1 downto 0);
rf_dtn: out STD_LOGIC
);
end CU;
architecture Behavioral of CU is
begin
process(op,op2,op3,cond,icc)--, clk)
begin
--if (rising_edge(clk)) then
-- OP = 10
case op is
when "00" =>
case op2 is
when "010" =>
case cond is
--BA 1
when "1000" =>
--1
aluop <= "000001";
en_dm <= '1';
we_dm <= '0';
pc_src <= "10"; --pc+disp22
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
--BN 2
when "0000" =>
--0
aluop <= "000010";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
-- BNE 3
when "1001" =>
aluop <= "000011";
en_dm <= '1';
we_dm <= '0';
--not Z
if(not(icc(2)) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
--BE 4
when "0001" =>
aluop <= "000100";
en_dm <= '1';
we_dm <= '0';
--Z
if(icc(2) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
--BG 5
when "1010" =>
aluop <= "000101";
en_dm <= '1';
we_dm <= '0';
-- not(Z or (N xor V))
if((not(icc(2) or (icc(3) xor icc(1)))) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
--BLE 6
when "0010" =>
aluop <= "000110";
en_dm <= '1';
we_dm <= '0';
--Z or (N xor V)
if((icc(2) or (icc(3) xor icc(1))) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
-- BGE 7
when "1011" =>
aluop <= "000111";
en_dm <= '1';
we_dm <= '0';
--not (N xor V)
if((not(icc(3) xor icc(1))) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
--BL 8
when "0011" =>
aluop <= "001000";
en_dm <= '1';
we_dm <= '0';
-- (N xor V)
if((icc(3) xor icc(1)) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
--BGU 9
when "1100" =>
aluop <= "001001";
en_dm <= '1';
we_dm <= '0';
-- not(C or Z)
if((not(icc(0) or icc(2))) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
--BLEU 10
when "0100" =>
aluop <= "001010";
en_dm <= '1';
we_dm <= '0';
-- (C or Z)
if((icc(0) or icc(2)) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
--BCC 11
when "1101" =>
aluop <= "001011";
en_dm <= '1';
we_dm <= '0';
--not C
if(not(icc(0)) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
--BCS 12
when "0101" =>
aluop <= "001100";
en_dm <= '1';
we_dm <= '0';
--C
if(icc(0) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
--BPOS 13
when "1110" =>
aluop <= "001101";
en_dm <= '1';
we_dm <= '0';
--not N
if(not(icc(3)) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
--BNEG 14
when "0110" =>
aluop <= "001110";
en_dm <= '1';
we_dm <= '0';
--N
if(icc(3) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
--BVC 15
when "1111" =>
aluop <= "001111";
en_dm <= '1';
we_dm <= '0';
--not V
if(not(icc(1)) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
--BVS 16
when "0111" =>
aluop <= "010000";
en_dm <= '1';
we_dm <= '0';
--V
if(icc(1) = '1') then
pc_src <= "10"; --pc+disp22
else
pc_src <= "11"; --pc
end if;
we_rf <= '0';
rf_src <= "00";
rf_dtn <= '0';
when others =>
aluop <= (others=>'1');
en_dm <= '0';
we_dm <= '0'; --
pc_src <= "11"; --pc --
we_rf <= '0';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
end case;
when "100" =>
-- NOP 19
aluop <= "010011";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '0';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
when others =>
aluop <= (others=>'1');
en_dm <= '0';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '0';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
end case;
-- op = 01
when "01" =>
--CALL 0
aluop <= "000000";
en_dm <= '1';
we_dm <= '0';
pc_src <= "01"; --pc+disp30
we_rf <= '1';
rf_src <= "10"; --pc
rf_dtn <= '1';
-- op = 10
when "10" =>
case op3 is
--ADD 32
when "000000" =>
aluop <= "100000";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--ADDcc
when "010000" =>
aluop <= "100001";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--ADDX
when "001000" =>
aluop <= "100010";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--ADDXcc
when "011000" =>
aluop <= "100011";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--SUB 36
when "000100" =>
aluop <= "100100";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--SUBcc
when "010100" =>
aluop <= "100101";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--SUBX
when "001100" =>
aluop <= "100110";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--SUBXcc
when "011100" =>
aluop <= "100111";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--AND 40
when "000001" =>
aluop <= "101000";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--ANDcc
when "010001" =>
aluop <= "101001";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--ANDN
when "000101" =>
aluop <= "101010";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--ANDNcc
when "010101" =>
aluop <= "101011";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--OR
when "000010" =>
aluop <= "101100";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--ORcc
when "010010" =>
aluop <= "101101";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--ORN
when "000110" =>
aluop <= "101110";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--ORNcc
when "010110" =>
aluop <= "101111";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--XOR
when "000011" =>
aluop <= "110000";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--XORcc
when "010011" =>
aluop <= "110001";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--XNOR
when "000111" =>
aluop <= "110010";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--XNORcc 51
when "010111" =>
aluop <= "110011";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--SAVE 57
when "111100" =>
aluop <= "111001";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--RESTORE 58
when "111101" =>
aluop <= "111010";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
--JMPL 59
when "111000" =>
aluop <= "111011";
en_dm <= '1';
we_dm <= '0';
pc_src <= "00"; --alurs
we_rf <= '1';
rf_src <= "10"; --pc
rf_dtn <= '0'; --nrd
when others =>
aluop <= (others=>'1');
en_dm <= '0';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '0';
rf_src <= "01"; --alurs
rf_dtn <= '0';
end case;
-- OP = 11
when "11" =>
case op3 is
--LD 55
when "000000" =>
aluop <= "110111";
en_dm <= '1';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '1';
rf_src <= "00"; --dm
rf_dtn <= '0'; --nrd
--ST 56
when "000100" =>
aluop <= "111000";
en_dm <= '1';
we_dm <= '1';
pc_src <= "11"; --pc
we_rf <= '0';
rf_src <= "01"; --alurs
rf_dtn <= '0'; --nrd
when others =>
aluop <= (others=>'1');
en_dm <= '0';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '0';
rf_src <= "01"; --alurs
rf_dtn <= '0';
end case;
when others =>
aluop <= (others=>'1');
en_dm <= '0';
we_dm <= '0';
pc_src <= "11"; --pc
we_rf <= '0';
rf_src <= "01"; --alurs
rf_dtn <= '0';
end case;
--end if; -- risingEdge
end process;
end Behavioral;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
-- Date : Tue Sep 20 15:46:23 2016
-- Host : chinook.andrew.cmu.edu running 64-bit Red Hat Enterprise Linux Server release 7.2 (Maipo)
-- Command : write_vhdl -force -mode synth_stub
-- /afs/ece.cmu.edu/usr/jacobwei/Public/project_1/project_1.srcs/sources_1/ip/ila_0/ila_0_stub.vhdl
-- Design : ila_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ila_0 is
Port (
clk : in STD_LOGIC;
trig_out : out STD_LOGIC;
trig_out_ack : in STD_LOGIC;
trig_in : in STD_LOGIC;
trig_in_ack : out STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end ila_0;
architecture stub of ila_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,trig_out,trig_out_ack,trig_in,trig_in_ack,probe0[0:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2015.2";
begin
end;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
-- Date : Tue Sep 20 15:46:23 2016
-- Host : chinook.andrew.cmu.edu running 64-bit Red Hat Enterprise Linux Server release 7.2 (Maipo)
-- Command : write_vhdl -force -mode synth_stub
-- /afs/ece.cmu.edu/usr/jacobwei/Public/project_1/project_1.srcs/sources_1/ip/ila_0/ila_0_stub.vhdl
-- Design : ila_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ila_0 is
Port (
clk : in STD_LOGIC;
trig_out : out STD_LOGIC;
trig_out_ack : in STD_LOGIC;
trig_in : in STD_LOGIC;
trig_in_ack : out STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end ila_0;
architecture stub of ila_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,trig_out,trig_out_ack,trig_in,trig_in_ack,probe0[0:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2015.2";
begin
end;
|
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- SPDIF receiver component package. ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.8 2004/06/27 16:16:55 gedra
-- Signal renaming and bug fix.
--
-- Revision 1.7 2004/06/26 14:14:47 gedra
-- Converted to numeric_std and fixed a few bugs.
--
-- Revision 1.6 2004/06/23 18:10:17 gedra
-- Added Wishbone bus cycle decoder.
--
-- Revision 1.5 2004/06/16 19:03:45 gedra
-- Changed status reg. declaration
--
-- Revision 1.4 2004/06/13 18:08:09 gedra
-- Added frame decoder and sample extractor
--
-- Revision 1.3 2004/06/10 18:57:36 gedra
-- Cleaned up lint warnings.
--
-- Revision 1.2 2004/06/09 19:24:50 gedra
-- Added dual port ram.
--
-- Revision 1.1 2004/06/07 18:06:00 gedra
-- Receiver component declarations.
--
--
library IEEE;
use IEEE.std_logic_1164.all;
package rx_package is
-- type declarations
type bus_array is array (0 to 7) of std_logic_vector(31 downto 0);
-- components
component rx_ver_reg
generic (DATA_WIDTH: integer := 32;
ADDR_WIDTH: integer := 8;
CH_ST_CAPTURE: integer := 1);
port (
ver_rd: in std_logic; -- version register read
ver_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0)); -- read data
end component;
component gen_control_reg
generic (DATA_WIDTH: integer;
-- note that this vector is (0 to xx), reverse order
ACTIVE_BIT_MASK: std_logic_vector);
port (
clk: in std_logic; -- clock
rst: in std_logic; -- reset
ctrl_wr: in std_logic; -- control register write
ctrl_rd: in std_logic; -- control register read
ctrl_din: in std_logic_vector(DATA_WIDTH - 1 downto 0);
ctrl_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0);
ctrl_bits: out std_logic_vector(DATA_WIDTH - 1 downto 0));
end component;
component rx_status_reg
generic (DATA_WIDTH: integer := 32);
port (
up_clk: in std_logic; -- clock
status_rd: in std_logic; -- status register read
lock: in std_logic; -- signal lock status
chas: in std_logic; -- channel A or B select
rx_block_start: in std_logic; -- start of block signal
ch_data: in std_logic; -- channel status/user data
cs_a_en: in std_logic; -- channel status ch. A enable
cs_b_en: in std_logic; -- channel status ch. B enable
status_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0));
end component;
component gen_event_reg
generic (DATA_WIDTH: integer := 32);
port (
clk: in std_logic; -- clock
rst: in std_logic; -- reset
evt_wr: in std_logic; -- event register write
evt_rd: in std_logic; -- event register read
evt_din: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- write data
event: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- event vector
evt_mask: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- irq mask
evt_en: in std_logic; -- irq enable
evt_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0); -- read data
evt_irq: out std_logic); -- interrupt request
end component;
component rx_cap_reg
port (
clk: in std_logic; -- clock
rst: in std_logic; -- reset
--cap_ctrl_wr: in std_logic; -- control register write
--cap_ctrl_rd: in std_logic; -- control register read
--cap_data_rd: in std_logic; -- data register read
cap_reg: in std_logic_vector(31 downto 0);
cap_din: in std_logic_vector(31 downto 0); -- write data
rx_block_start: in std_logic; -- start of block signal
ch_data: in std_logic; -- channel status/user data
ud_a_en: in std_logic; -- user data ch. A enable
ud_b_en: in std_logic; -- user data ch. B enable
cs_a_en: in std_logic; -- channel status ch. A enable
cs_b_en: in std_logic; -- channel status ch. B enable
cap_dout: out std_logic_vector(31 downto 0); -- read data
cap_evt: out std_logic); -- capture event (interrupt)
end component;
component rx_phase_det
generic (AXI_FREQ: natural := 33); -- WishBone frequency in MHz
port (
up_clk: in std_logic;
rxen: in std_logic;
spdif: in std_logic;
lock: out std_logic;
lock_evt: out std_logic; -- lock status change event
rx_data: out std_logic;
rx_data_en: out std_logic;
rx_block_start: out std_logic;
rx_frame_start: out std_logic;
rx_channel_a: out std_logic;
rx_error: out std_logic;
ud_a_en: out std_logic; -- user data ch. A enable
ud_b_en: out std_logic; -- user data ch. B enable
cs_a_en: out std_logic; -- channel status ch. A enable
cs_b_en: out std_logic); -- channel status ch. B enable);
end component;
component dpram
generic (DATA_WIDTH: positive := 32;
RAM_WIDTH: positive := 8);
port (
clk: in std_logic;
rst: in std_logic; -- reset is optional, not used here
din: in std_logic_vector(DATA_WIDTH - 1 downto 0);
wr_en: in std_logic;
rd_en: in std_logic;
wr_addr: in std_logic_vector(RAM_WIDTH - 1 downto 0);
rd_addr: in std_logic_vector(RAM_WIDTH - 1 downto 0);
dout: out std_logic_vector(DATA_WIDTH - 1 downto 0));
end component;
component rx_decode
generic (DATA_WIDTH: integer range 16 to 32 := 32;
ADDR_WIDTH: integer range 8 to 64 := 8);
port (
up_clk: in std_logic;
conf_rxen: in std_logic;
conf_sample: in std_logic;
conf_valid: in std_logic;
conf_mode: in std_logic_vector(3 downto 0);
conf_blken: in std_logic;
conf_valen: in std_logic;
conf_useren: in std_logic;
conf_staten: in std_logic;
conf_paren: in std_logic;
lock: in std_logic;
rx_data: in std_logic;
rx_data_en: in std_logic;
rx_block_start: in std_logic;
rx_frame_start: in std_logic;
rx_channel_a: in std_logic;
wr_en: out std_logic;
wr_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0);
wr_data: out std_logic_vector(DATA_WIDTH - 1 downto 0);
stat_paritya: out std_logic;
stat_parityb: out std_logic;
stat_lsbf: out std_logic;
stat_hsbf: out std_logic);
end component;
component rx_wb_decoder
generic (DATA_WIDTH: integer := 32;
ADDR_WIDTH: integer := 8);
port (
up_clk: in std_logic; -- wishbone clock
wb_rst_i: in std_logic; -- reset signal
wb_sel_i: in std_logic; -- select input
wb_stb_i: in std_logic; -- strobe input
wb_we_i: in std_logic; -- write enable
wb_cyc_i: in std_logic; -- cycle input
wb_bte_i: in std_logic_vector(1 downto 0); -- burts type extension
wb_adr_i: in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- address
wb_cti_i: in std_logic_vector(2 downto 0); -- cycle type identifier
data_out: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- internal bus
wb_ack_o: out std_logic; -- acknowledge
wb_dat_o: out std_logic_vector(DATA_WIDTH - 1 downto 0); -- data out
version_rd: out std_logic; -- Version register read
config_rd: out std_logic; -- Config register read
config_wr: out std_logic; -- Config register write
status_rd: out std_logic; -- Status register read
intmask_rd: out std_logic; -- Interrupt mask register read
intmask_wr: out std_logic; -- Interrupt mask register write
intstat_rd: out std_logic; -- Interrupt status register read
intstat_wr: out std_logic; -- Interrupt status register read
mem_rd: out std_logic; -- Sample memory read
mem_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0); -- memory addr.
ch_st_cap_rd: out std_logic_vector(7 downto 0); -- Ch. status cap. read
ch_st_cap_wr: out std_logic_vector(7 downto 0); -- Ch. status cap. write
ch_st_data_rd: out std_logic_vector(7 downto 0)); -- Ch. status data read
end component;
end rx_package;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity datapath_tb is
end entity;
architecture TB of datapath_tb is
component datapath
port (
MemToReg : in std_logic;
MemWrite : in std_logic;
Branch : in std_logic;
AluSrc : in std_logic;
RegDst : in std_logic;
RegWrite : in std_logic;
Jump : in std_logic;
AluControl : in std_logic_vector(2 downto 0);
dump : in std_logic;
pc : out std_logic_vector(31 downto 0);
instr : out std_logic_vector(31 downto 0);
reset : in std_logic;
clk : in std_logic
);
end component;
signal MemToReg, MemWrite, Branch, AluSrc, RegDst, RegWrite, Jump,
dump, reset, clk : std_logic;
signal AluControl : std_logic_vector(2 downto 0);
signal pc, instr: std_logic_vector(31 downto 0);
begin
dut : datapath port map (
MemToReg => MemToReg,
MemWrite => MemWrite,
Branch => Branch,
AluSrc => AluSrc,
RegDst => RegDst,
RegWrite => RegWrite,
Jump => Jump,
AluControl => AluControl,
dump => dump,
pc => pc,
instr => instr,
reset => reset,
clk => clk
);
process begin
clk <= '1';
wait for 5 ns;
clk <= '0';
wait for 5 ns;
end process;
process begin
--ADD--
reset <= '1';
wait for 2 ns;
reset <= '0';
MemToReg <= '0';
MemWrite <= '0';
Branch <= '0'; --??
AluSrc <= '1';
RegDst <= '0'; --??
RegWrite <= '1';
Jump <= '1';
AluControl <= "010";
dump <= '1';
wait for 20 ns;
dump <= '0';
end process;
end TB;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity datapath_tb is
end entity;
architecture TB of datapath_tb is
component datapath
port (
MemToReg : in std_logic;
MemWrite : in std_logic;
Branch : in std_logic;
AluSrc : in std_logic;
RegDst : in std_logic;
RegWrite : in std_logic;
Jump : in std_logic;
AluControl : in std_logic_vector(2 downto 0);
dump : in std_logic;
pc : out std_logic_vector(31 downto 0);
instr : out std_logic_vector(31 downto 0);
reset : in std_logic;
clk : in std_logic
);
end component;
signal MemToReg, MemWrite, Branch, AluSrc, RegDst, RegWrite, Jump,
dump, reset, clk : std_logic;
signal AluControl : std_logic_vector(2 downto 0);
signal pc, instr: std_logic_vector(31 downto 0);
begin
dut : datapath port map (
MemToReg => MemToReg,
MemWrite => MemWrite,
Branch => Branch,
AluSrc => AluSrc,
RegDst => RegDst,
RegWrite => RegWrite,
Jump => Jump,
AluControl => AluControl,
dump => dump,
pc => pc,
instr => instr,
reset => reset,
clk => clk
);
process begin
clk <= '1';
wait for 5 ns;
clk <= '0';
wait for 5 ns;
end process;
process begin
--ADD--
reset <= '1';
wait for 2 ns;
reset <= '0';
MemToReg <= '0';
MemWrite <= '0';
Branch <= '0'; --??
AluSrc <= '1';
RegDst <= '0'; --??
RegWrite <= '1';
Jump <= '1';
AluControl <= "010";
dump <= '1';
wait for 20 ns;
dump <= '0';
end process;
end TB;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: math_real.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
---------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be included in this package.
--
-- ****************************************************************
-- * *
-- * W A R N I N G *
-- * *
-- * This DRAFT version IS NOT endorsed or approved by IEEE *
-- * *
-- ****************************************************************
--
-- Title: PACKAGE MATH_REAL
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Purpose: VHDL declarations for mathematical package MATH_REAL
-- which contains common real constants, common real
-- functions, and real trascendental functions.
--
-- Author: Based on work by IEEE VHDL Math Package Study Group
--
-- Notes:
-- The package body shall be considered the formal definition of
-- the semantics of this package. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- History:
-- Version 0.4 JAT 4/15/93
-------------------------------------------------------------
Library IEEE;
Package MATH_REAL is
--synopsys synthesis_off
constant MATH_E : real := 2.71828_18284_59045_23536;
-- value of e
constant MATH_1_E: real := 0.36787_94411_71442_32160;
-- value of 1/e
constant MATH_PI : real := 3.14159_26535_89793_23846;
-- value of pi
constant MATH_1_PI : real := 0.31830_98861_83790_67154;
-- value of 1/pi
constant MATH_LOG_OF_2: real := 0.69314_71805_59945_30942;
-- natural log of 2
constant MATH_LOG_OF_10: real := 2.30258_50929_94045_68402;
-- natural log of10
constant MATH_LOG2_OF_E: real := 1.44269_50408_88963_4074;
-- log base 2 of e
constant MATH_LOG10_OF_E: real := 0.43429_44819_03251_82765;
-- log base 10 of e
constant MATH_SQRT2: real := 1.41421_35623_73095_04880;
-- sqrt of 2
constant MATH_SQRT1_2: real := 0.70710_67811_86547_52440;
-- sqrt of 1/2
constant MATH_SQRT_PI: real := 1.77245_38509_05516_02730;
-- sqrt of pi
constant MATH_DEG_TO_RAD: real := 0.01745_32925_19943_29577;
-- conversion factor from degree to radian
constant MATH_RAD_TO_DEG: real := 57.29577_95130_82320_87685;
-- conversion factor from radian to degree
--
-- attribute for functions whose implementation is foreign (C native)
--
-- attribute FOREIGN: string; -- predefined attribute in VHDL-1992
--
function SIGN (X: real ) return real;
-- returns 1.0 if X > 0.0; 0.0 if X == 0.0; -1.0 if X < 0.0
function CEIL (X : real ) return real;
-- returns smallest integer value (as real) not less than X
function FLOOR (X : real ) return real;
-- returns largest integer value (as real) not greater than X
function ROUND (X : real ) return real;
-- returns FLOOR(X + 0.5) if X > 0.0;
-- return CEIL(X - 0.5) if X < 0.0
function FMAX (X, Y : real ) return real;
-- returns the algebraically larger of X and Y
function FMIN (X, Y : real ) return real;
-- returns the algebraically smaller of X and Y
function SRAND (seed: in integer ) return integer;
-- attribute FOREIGN of SRAND: function is "C_NATIVE";
-- for VHDL-1992 standard
--
-- sets value of seed for sequence of pseudo-random numbers.
-- returns the value of the seed.
-- It uses the native C function srand().
function RAND return integer;
-- attribute FOREIGN of RAND: function is "C_NATIVE";
-- for VHDL-1992 standard
--
-- returns an integer pseudo-random number with uniform distribution.
-- It uses the native C function rand().
-- Seed for the sequence is initialized with the
-- SRAND() function and value of the seed is changed every
-- time SRAND() is called, but it is not visible.
-- The range of generated values is platform dependent.
function GET_RAND_MAX return integer;
-- attribute FOREIGN of GET_RAND_MAX: function is "C_NATIVE";
-- for VHDL-1992 standard
--
-- returns the upper bound of the range of the
-- pseudo-random numbers generated by RAND().
-- The support for this function is platform dependent.
-- It may not be available in some platforms.
-- Note: the value of (RAND() / GET_RAND_MAX()) is a
-- pseudo-random number distributed between 0 & 1.
function SQRT (X : real ) return real;
-- returns square root of X; X >= 0.0
function CBRT (X : real ) return real;
-- returns cube root of X
function "**" (X : integer; Y : real) return real;
-- returns Y power of X ==> X**Y;
-- error if X = 0 and Y <= 0.0
-- error if X < 0 and Y does not have an integral value
function "**" (X : real; Y : real) return real;
-- returns Y power of X ==> X**Y;
-- error if X = 0.0 and Y <= 0.0
-- error if X < 0.0 and Y does not have an integral value
function EXP (X : real ) return real;
-- returns e**X; where e = MATH_E
function LOG (X : real ) return real;
-- returns natural logarithm of X; X > 0
function LOG (BASE: positive; X : real) return real;
-- returns logarithm base BASE of X; X > 0
function SIN (X : real ) return real;
-- returns sin X; X in radians
function COS ( X : real ) return real;
-- returns cos X; X in radians
function TAN (X : real ) return real;
-- returns tan X; X in radians
-- X /= ((2k+1) * PI/2), where k is an integer
function ASIN (X : real ) return real;
-- returns -PI/2 < asin X < PI/2; | X | <= 1.0
function ACOS (X : real ) return real;
-- returns 0 < acos X < PI; | X | <= 1.0
function ATAN (X : real) return real;
-- returns -PI/2 < atan X < PI/2
function ATAN2 (X : real; Y : real) return real;
-- returns atan (X/Y); -PI < atan2(X,Y) < PI; Y /= 0.0
function SINH (X : real) return real;
-- hyperbolic sine; returns (e**X - e**(-X))/2
function COSH (X : real) return real;
-- hyperbolic cosine; returns (e**X + e**(-X))/2
function TANH (X : real) return real;
-- hyperbolic tangent; -- returns (e**X - e**(-X))/(e**X + e**(-X))
function ASINH (X : real) return real;
-- returns ln( X + sqrt( X**2 + 1))
function ACOSH (X : real) return real;
-- returns ln( X + sqrt( X**2 - 1)); X >= 1.0
function ATANH (X : real) return real;
-- returns (ln( (1 + X)/(1 - X)))/2 ; | X | < 1.0
--synopsys synthesis_on
end MATH_REAL;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: math_real.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
---------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be included in this package.
--
-- ****************************************************************
-- * *
-- * W A R N I N G *
-- * *
-- * This DRAFT version IS NOT endorsed or approved by IEEE *
-- * *
-- ****************************************************************
--
-- Title: PACKAGE MATH_REAL
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Purpose: VHDL declarations for mathematical package MATH_REAL
-- which contains common real constants, common real
-- functions, and real trascendental functions.
--
-- Author: Based on work by IEEE VHDL Math Package Study Group
--
-- Notes:
-- The package body shall be considered the formal definition of
-- the semantics of this package. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- History:
-- Version 0.4 JAT 4/15/93
-------------------------------------------------------------
Library IEEE;
Package MATH_REAL is
--synopsys synthesis_off
constant MATH_E : real := 2.71828_18284_59045_23536;
-- value of e
constant MATH_1_E: real := 0.36787_94411_71442_32160;
-- value of 1/e
constant MATH_PI : real := 3.14159_26535_89793_23846;
-- value of pi
constant MATH_1_PI : real := 0.31830_98861_83790_67154;
-- value of 1/pi
constant MATH_LOG_OF_2: real := 0.69314_71805_59945_30942;
-- natural log of 2
constant MATH_LOG_OF_10: real := 2.30258_50929_94045_68402;
-- natural log of10
constant MATH_LOG2_OF_E: real := 1.44269_50408_88963_4074;
-- log base 2 of e
constant MATH_LOG10_OF_E: real := 0.43429_44819_03251_82765;
-- log base 10 of e
constant MATH_SQRT2: real := 1.41421_35623_73095_04880;
-- sqrt of 2
constant MATH_SQRT1_2: real := 0.70710_67811_86547_52440;
-- sqrt of 1/2
constant MATH_SQRT_PI: real := 1.77245_38509_05516_02730;
-- sqrt of pi
constant MATH_DEG_TO_RAD: real := 0.01745_32925_19943_29577;
-- conversion factor from degree to radian
constant MATH_RAD_TO_DEG: real := 57.29577_95130_82320_87685;
-- conversion factor from radian to degree
--
-- attribute for functions whose implementation is foreign (C native)
--
-- attribute FOREIGN: string; -- predefined attribute in VHDL-1992
--
function SIGN (X: real ) return real;
-- returns 1.0 if X > 0.0; 0.0 if X == 0.0; -1.0 if X < 0.0
function CEIL (X : real ) return real;
-- returns smallest integer value (as real) not less than X
function FLOOR (X : real ) return real;
-- returns largest integer value (as real) not greater than X
function ROUND (X : real ) return real;
-- returns FLOOR(X + 0.5) if X > 0.0;
-- return CEIL(X - 0.5) if X < 0.0
function FMAX (X, Y : real ) return real;
-- returns the algebraically larger of X and Y
function FMIN (X, Y : real ) return real;
-- returns the algebraically smaller of X and Y
function SRAND (seed: in integer ) return integer;
-- attribute FOREIGN of SRAND: function is "C_NATIVE";
-- for VHDL-1992 standard
--
-- sets value of seed for sequence of pseudo-random numbers.
-- returns the value of the seed.
-- It uses the native C function srand().
function RAND return integer;
-- attribute FOREIGN of RAND: function is "C_NATIVE";
-- for VHDL-1992 standard
--
-- returns an integer pseudo-random number with uniform distribution.
-- It uses the native C function rand().
-- Seed for the sequence is initialized with the
-- SRAND() function and value of the seed is changed every
-- time SRAND() is called, but it is not visible.
-- The range of generated values is platform dependent.
function GET_RAND_MAX return integer;
-- attribute FOREIGN of GET_RAND_MAX: function is "C_NATIVE";
-- for VHDL-1992 standard
--
-- returns the upper bound of the range of the
-- pseudo-random numbers generated by RAND().
-- The support for this function is platform dependent.
-- It may not be available in some platforms.
-- Note: the value of (RAND() / GET_RAND_MAX()) is a
-- pseudo-random number distributed between 0 & 1.
function SQRT (X : real ) return real;
-- returns square root of X; X >= 0.0
function CBRT (X : real ) return real;
-- returns cube root of X
function "**" (X : integer; Y : real) return real;
-- returns Y power of X ==> X**Y;
-- error if X = 0 and Y <= 0.0
-- error if X < 0 and Y does not have an integral value
function "**" (X : real; Y : real) return real;
-- returns Y power of X ==> X**Y;
-- error if X = 0.0 and Y <= 0.0
-- error if X < 0.0 and Y does not have an integral value
function EXP (X : real ) return real;
-- returns e**X; where e = MATH_E
function LOG (X : real ) return real;
-- returns natural logarithm of X; X > 0
function LOG (BASE: positive; X : real) return real;
-- returns logarithm base BASE of X; X > 0
function SIN (X : real ) return real;
-- returns sin X; X in radians
function COS ( X : real ) return real;
-- returns cos X; X in radians
function TAN (X : real ) return real;
-- returns tan X; X in radians
-- X /= ((2k+1) * PI/2), where k is an integer
function ASIN (X : real ) return real;
-- returns -PI/2 < asin X < PI/2; | X | <= 1.0
function ACOS (X : real ) return real;
-- returns 0 < acos X < PI; | X | <= 1.0
function ATAN (X : real) return real;
-- returns -PI/2 < atan X < PI/2
function ATAN2 (X : real; Y : real) return real;
-- returns atan (X/Y); -PI < atan2(X,Y) < PI; Y /= 0.0
function SINH (X : real) return real;
-- hyperbolic sine; returns (e**X - e**(-X))/2
function COSH (X : real) return real;
-- hyperbolic cosine; returns (e**X + e**(-X))/2
function TANH (X : real) return real;
-- hyperbolic tangent; -- returns (e**X - e**(-X))/(e**X + e**(-X))
function ASINH (X : real) return real;
-- returns ln( X + sqrt( X**2 + 1))
function ACOSH (X : real) return real;
-- returns ln( X + sqrt( X**2 - 1)); X >= 1.0
function ATANH (X : real) return real;
-- returns (ln( (1 + X)/(1 - X)))/2 ; | X | < 1.0
--synopsys synthesis_on
end MATH_REAL;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: math_real.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
---------------------------------------------------------------
--
-- This source file may be used and distributed without restriction.
-- No declarations or definitions shall be included in this package.
--
-- ****************************************************************
-- * *
-- * W A R N I N G *
-- * *
-- * This DRAFT version IS NOT endorsed or approved by IEEE *
-- * *
-- ****************************************************************
--
-- Title: PACKAGE MATH_REAL
--
-- Library: This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Purpose: VHDL declarations for mathematical package MATH_REAL
-- which contains common real constants, common real
-- functions, and real trascendental functions.
--
-- Author: Based on work by IEEE VHDL Math Package Study Group
--
-- Notes:
-- The package body shall be considered the formal definition of
-- the semantics of this package. Tool developers may choose to implement
-- the package body in the most efficient manner available to them.
--
-- History:
-- Version 0.4 JAT 4/15/93
-------------------------------------------------------------
Library IEEE;
Package MATH_REAL is
--synopsys synthesis_off
constant MATH_E : real := 2.71828_18284_59045_23536;
-- value of e
constant MATH_1_E: real := 0.36787_94411_71442_32160;
-- value of 1/e
constant MATH_PI : real := 3.14159_26535_89793_23846;
-- value of pi
constant MATH_1_PI : real := 0.31830_98861_83790_67154;
-- value of 1/pi
constant MATH_LOG_OF_2: real := 0.69314_71805_59945_30942;
-- natural log of 2
constant MATH_LOG_OF_10: real := 2.30258_50929_94045_68402;
-- natural log of10
constant MATH_LOG2_OF_E: real := 1.44269_50408_88963_4074;
-- log base 2 of e
constant MATH_LOG10_OF_E: real := 0.43429_44819_03251_82765;
-- log base 10 of e
constant MATH_SQRT2: real := 1.41421_35623_73095_04880;
-- sqrt of 2
constant MATH_SQRT1_2: real := 0.70710_67811_86547_52440;
-- sqrt of 1/2
constant MATH_SQRT_PI: real := 1.77245_38509_05516_02730;
-- sqrt of pi
constant MATH_DEG_TO_RAD: real := 0.01745_32925_19943_29577;
-- conversion factor from degree to radian
constant MATH_RAD_TO_DEG: real := 57.29577_95130_82320_87685;
-- conversion factor from radian to degree
--
-- attribute for functions whose implementation is foreign (C native)
--
-- attribute FOREIGN: string; -- predefined attribute in VHDL-1992
--
function SIGN (X: real ) return real;
-- returns 1.0 if X > 0.0; 0.0 if X == 0.0; -1.0 if X < 0.0
function CEIL (X : real ) return real;
-- returns smallest integer value (as real) not less than X
function FLOOR (X : real ) return real;
-- returns largest integer value (as real) not greater than X
function ROUND (X : real ) return real;
-- returns FLOOR(X + 0.5) if X > 0.0;
-- return CEIL(X - 0.5) if X < 0.0
function FMAX (X, Y : real ) return real;
-- returns the algebraically larger of X and Y
function FMIN (X, Y : real ) return real;
-- returns the algebraically smaller of X and Y
function SRAND (seed: in integer ) return integer;
-- attribute FOREIGN of SRAND: function is "C_NATIVE";
-- for VHDL-1992 standard
--
-- sets value of seed for sequence of pseudo-random numbers.
-- returns the value of the seed.
-- It uses the native C function srand().
function RAND return integer;
-- attribute FOREIGN of RAND: function is "C_NATIVE";
-- for VHDL-1992 standard
--
-- returns an integer pseudo-random number with uniform distribution.
-- It uses the native C function rand().
-- Seed for the sequence is initialized with the
-- SRAND() function and value of the seed is changed every
-- time SRAND() is called, but it is not visible.
-- The range of generated values is platform dependent.
function GET_RAND_MAX return integer;
-- attribute FOREIGN of GET_RAND_MAX: function is "C_NATIVE";
-- for VHDL-1992 standard
--
-- returns the upper bound of the range of the
-- pseudo-random numbers generated by RAND().
-- The support for this function is platform dependent.
-- It may not be available in some platforms.
-- Note: the value of (RAND() / GET_RAND_MAX()) is a
-- pseudo-random number distributed between 0 & 1.
function SQRT (X : real ) return real;
-- returns square root of X; X >= 0.0
function CBRT (X : real ) return real;
-- returns cube root of X
function "**" (X : integer; Y : real) return real;
-- returns Y power of X ==> X**Y;
-- error if X = 0 and Y <= 0.0
-- error if X < 0 and Y does not have an integral value
function "**" (X : real; Y : real) return real;
-- returns Y power of X ==> X**Y;
-- error if X = 0.0 and Y <= 0.0
-- error if X < 0.0 and Y does not have an integral value
function EXP (X : real ) return real;
-- returns e**X; where e = MATH_E
function LOG (X : real ) return real;
-- returns natural logarithm of X; X > 0
function LOG (BASE: positive; X : real) return real;
-- returns logarithm base BASE of X; X > 0
function SIN (X : real ) return real;
-- returns sin X; X in radians
function COS ( X : real ) return real;
-- returns cos X; X in radians
function TAN (X : real ) return real;
-- returns tan X; X in radians
-- X /= ((2k+1) * PI/2), where k is an integer
function ASIN (X : real ) return real;
-- returns -PI/2 < asin X < PI/2; | X | <= 1.0
function ACOS (X : real ) return real;
-- returns 0 < acos X < PI; | X | <= 1.0
function ATAN (X : real) return real;
-- returns -PI/2 < atan X < PI/2
function ATAN2 (X : real; Y : real) return real;
-- returns atan (X/Y); -PI < atan2(X,Y) < PI; Y /= 0.0
function SINH (X : real) return real;
-- hyperbolic sine; returns (e**X - e**(-X))/2
function COSH (X : real) return real;
-- hyperbolic cosine; returns (e**X + e**(-X))/2
function TANH (X : real) return real;
-- hyperbolic tangent; -- returns (e**X - e**(-X))/(e**X + e**(-X))
function ASINH (X : real) return real;
-- returns ln( X + sqrt( X**2 + 1))
function ACOSH (X : real) return real;
-- returns ln( X + sqrt( X**2 - 1)); X >= 1.0
function ATANH (X : real) return real;
-- returns (ln( (1 + X)/(1 - X)))/2 ; | X | < 1.0
--synopsys synthesis_on
end MATH_REAL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2622.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02622ent IS
END c13s03b01x00p02n01i02622ent;
ARCHITECTURE c13s03b01x00p02n01i02622arch OF c13s03b01x00p02n01i02622ent IS
BEGIN
TESTING: PROCESS
variable k=k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02622 - Identifier can not contain '='."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02622arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2622.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02622ent IS
END c13s03b01x00p02n01i02622ent;
ARCHITECTURE c13s03b01x00p02n01i02622arch OF c13s03b01x00p02n01i02622ent IS
BEGIN
TESTING: PROCESS
variable k=k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02622 - Identifier can not contain '='."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02622arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2622.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02622ent IS
END c13s03b01x00p02n01i02622ent;
ARCHITECTURE c13s03b01x00p02n01i02622arch OF c13s03b01x00p02n01i02622ent IS
BEGIN
TESTING: PROCESS
variable k=k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02622 - Identifier can not contain '='."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02622arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity inc_ent is
generic (
works : integer;
vec : std_logic_vector);
end entity;
architecture default of inc_ent is
begin
assert false report integer'image(works) & " " & integer'image(vec'length);
end architecture;
library ieee;
use ieee.std_logic_1164.all;
entity top_ent is end entity;
architecture default of top_ent is
constant foo_v : std_logic_vector(0 to 12) := (others => '1');
begin
g : for ix in 0 to 4 generate
constant foo_v : std_logic_vector(0 to ix) := (others => '1');
begin
inst : entity work.inc_ent
generic map (
works => 0,
vec => (0 to ix => '1')
);
inst2 : entity work.inc_ent
generic map (
works => 1,
vec => foo_v
);
end generate;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_in is
port (
CLOCK : in std_logic;
RESET : in std_logic;
DIN : in std_logic_vector(31 downto 0);
VIN : in std_logic;
RIN : out std_logic;
DOUT : out std_logic_vector(31 downto 0);
VOUT : out std_logic;
ROUT : in std_logic;
AX : out std_logic_vector(1 downto 0);
AY : out std_logic_vector(1 downto 0);
SZ : out std_logic_vector(15 downto 0);
HVAL : out std_logic
);
end entity;
architecture structure of fifo_in is
component fifo is
generic (
FIFO_WIDTH : positive := 10;
DATA_WIDTH : positive := 32
);
port (
-- clock and reset
CLOCK : in std_logic;
RESET : in std_logic;
-- fifo input interface
DAT_I : in std_logic_vector(DATA_WIDTH-1 downto 0); --din
VAL_I : in std_logic; --push
RDY_I : out std_logic; --ready for push
FULL : out std_logic; --not ready for push
-- fifo output interface
DAT_O : out std_logic_vector(DATA_WIDTH-1 downto 0); --dout
VAL_O : out std_logic; --ready for pop
RDY_O : in std_logic; --pop
EMPTY : out std_logic; --not ready for pop
OCC_SIZE : out std_logic_vector(FIFO_WIDTH-1 downto 0);
VAC_SIZE : out std_logic_vector(FIFO_WIDTH-1 downto 0)
);
end component;
component FIFO_32x1Kr is
Port (
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component;
constant RAW : boolean := false;
signal reset_n : std_logic;
signal inter_data : std_logic_vector(31 downto 0);
signal inter_valid : std_logic;
signal inter_ready : std_logic;
signal val3 : std_logic;
signal srs_vout : std_logic;
component shift_reg_stub is
port (
CLOCK : in std_logic;
RESET : in std_logic;
DIN : in std_logic_vector(31 downto 0);
VIN : in std_logic;
RIN : out std_logic;
DOUT : out std_logic_vector(31 downto 0);
VOUT : out std_logic;
ROUT : in std_logic;
AX : out std_logic_vector(1 downto 0);
AY : out std_logic_vector(1 downto 0);
SZ : out std_logic_vector(15 downto 0);
VAL3 : out std_logic
);
end component;
type state_t is (INIT, TRACK);
signal state, state_next : state_t;
signal count, count_next : unsigned(15 downto 0);
signal srs_size : std_logic_vector(15 downto 0);
begin
-- fifo
fifo_raw: if RAW = true generate
fifo_i: fifo
generic map (
FIFO_WIDTH => 10,
DATA_WIDTH => 32
)
port map (
-- clock and reset
CLOCK => CLOCK,
RESET => RESET,
-- fifo input interface
DAT_I => DIN,
VAL_I => VIN,
RDY_I => RIN,
FULL => open,
-- fifo output interface
DAT_O => inter_data,
VAL_O => inter_valid,
RDY_O => inter_ready,
EMPTY => open,
OCC_SIZE => open,
VAC_SIZE => open
);
end generate;
fifo_xil: if RAW = false generate
fifo_i: FIFO_32x1Kr
port map (
s_aclk => CLOCK,
s_aresetn => reset_n,
s_axis_tdata => DIN,
s_axis_tvalid => VIN,
s_axis_tready => RIN,
m_axis_tdata => inter_data,
m_axis_tvalid => inter_valid,
m_axis_tready => inter_ready
);
end generate;
reset_n <= not RESET;
-- srstub
srstub: shift_reg_stub
port map (
CLOCK => CLOCK,
RESET => RESET,
DIN => inter_data,
VIN => inter_valid,
RIN => inter_ready,
DOUT => DOUT,
VOUT => srs_vout,
ROUT => ROUT,
AX => AX,
AY => AY,
SZ => srs_size,
VAL3 => val3
);
VOUT <= srs_vout;
SZ <= srs_size;
process (CLOCK)
begin
if rising_edge(CLOCK) then
if RESET = '1' then
state <= INIT;
else
state <= state_next;
count <= count_next;
end if;
end if;
end process;
process (state, count, val3, ROUT, srs_size, srs_vout)
begin
state_next <= state;
count_next <= count;
HVAL <= '0';
case state is
when INIT =>
if val3 = '1' then
HVAL <= '1';
count_next <= unsigned(srs_size) - 1;
if ROUT = '1' and srs_vout = '1' then
state_next <= TRACK;
end if;
end if;
when TRACK =>
if ROUT = '1' and srs_vout = '1' then
count_next <= count - 1;
if count = 1 then -- last word is transfering
state_next <= INIT;
end if;
end if;
end case;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_in is
port (
CLOCK : in std_logic;
RESET : in std_logic;
DIN : in std_logic_vector(31 downto 0);
VIN : in std_logic;
RIN : out std_logic;
DOUT : out std_logic_vector(31 downto 0);
VOUT : out std_logic;
ROUT : in std_logic;
AX : out std_logic_vector(1 downto 0);
AY : out std_logic_vector(1 downto 0);
SZ : out std_logic_vector(15 downto 0);
HVAL : out std_logic
);
end entity;
architecture structure of fifo_in is
component fifo is
generic (
FIFO_WIDTH : positive := 10;
DATA_WIDTH : positive := 32
);
port (
-- clock and reset
CLOCK : in std_logic;
RESET : in std_logic;
-- fifo input interface
DAT_I : in std_logic_vector(DATA_WIDTH-1 downto 0); --din
VAL_I : in std_logic; --push
RDY_I : out std_logic; --ready for push
FULL : out std_logic; --not ready for push
-- fifo output interface
DAT_O : out std_logic_vector(DATA_WIDTH-1 downto 0); --dout
VAL_O : out std_logic; --ready for pop
RDY_O : in std_logic; --pop
EMPTY : out std_logic; --not ready for pop
OCC_SIZE : out std_logic_vector(FIFO_WIDTH-1 downto 0);
VAC_SIZE : out std_logic_vector(FIFO_WIDTH-1 downto 0)
);
end component;
component FIFO_32x1Kr is
Port (
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component;
constant RAW : boolean := false;
signal reset_n : std_logic;
signal inter_data : std_logic_vector(31 downto 0);
signal inter_valid : std_logic;
signal inter_ready : std_logic;
signal val3 : std_logic;
signal srs_vout : std_logic;
component shift_reg_stub is
port (
CLOCK : in std_logic;
RESET : in std_logic;
DIN : in std_logic_vector(31 downto 0);
VIN : in std_logic;
RIN : out std_logic;
DOUT : out std_logic_vector(31 downto 0);
VOUT : out std_logic;
ROUT : in std_logic;
AX : out std_logic_vector(1 downto 0);
AY : out std_logic_vector(1 downto 0);
SZ : out std_logic_vector(15 downto 0);
VAL3 : out std_logic
);
end component;
type state_t is (INIT, TRACK);
signal state, state_next : state_t;
signal count, count_next : unsigned(15 downto 0);
signal srs_size : std_logic_vector(15 downto 0);
begin
-- fifo
fifo_raw: if RAW = true generate
fifo_i: fifo
generic map (
FIFO_WIDTH => 10,
DATA_WIDTH => 32
)
port map (
-- clock and reset
CLOCK => CLOCK,
RESET => RESET,
-- fifo input interface
DAT_I => DIN,
VAL_I => VIN,
RDY_I => RIN,
FULL => open,
-- fifo output interface
DAT_O => inter_data,
VAL_O => inter_valid,
RDY_O => inter_ready,
EMPTY => open,
OCC_SIZE => open,
VAC_SIZE => open
);
end generate;
fifo_xil: if RAW = false generate
fifo_i: FIFO_32x1Kr
port map (
s_aclk => CLOCK,
s_aresetn => reset_n,
s_axis_tdata => DIN,
s_axis_tvalid => VIN,
s_axis_tready => RIN,
m_axis_tdata => inter_data,
m_axis_tvalid => inter_valid,
m_axis_tready => inter_ready
);
end generate;
reset_n <= not RESET;
-- srstub
srstub: shift_reg_stub
port map (
CLOCK => CLOCK,
RESET => RESET,
DIN => inter_data,
VIN => inter_valid,
RIN => inter_ready,
DOUT => DOUT,
VOUT => srs_vout,
ROUT => ROUT,
AX => AX,
AY => AY,
SZ => srs_size,
VAL3 => val3
);
VOUT <= srs_vout;
SZ <= srs_size;
process (CLOCK)
begin
if rising_edge(CLOCK) then
if RESET = '1' then
state <= INIT;
else
state <= state_next;
count <= count_next;
end if;
end if;
end process;
process (state, count, val3, ROUT, srs_size, srs_vout)
begin
state_next <= state;
count_next <= count;
HVAL <= '0';
case state is
when INIT =>
if val3 = '1' then
HVAL <= '1';
count_next <= unsigned(srs_size) - 1;
if ROUT = '1' and srs_vout = '1' then
state_next <= TRACK;
end if;
end if;
when TRACK =>
if ROUT = '1' and srs_vout = '1' then
count_next <= count - 1;
if count = 1 then -- last word is transfering
state_next <= INIT;
end if;
end if;
end case;
end process;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: tap_xilinx
-- File: tap_xilinx.vhd
-- Author: Edvin Catovic, Jiri Gaisler - Gaisler Research
-- Description: Xilinx TAP controllers wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex_tap is
component BSCAN_VIRTEX
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
begin
u0 : BSCAN_VIRTEX
port map (
DRCK1 => drck1,
DRCK2 => drck2,
RESET => tapo_rst,
SEL1 => sel1,
SEL2 => sel2,
SHIFT => tapo_shft,
TDI => tapo_tdi,
UPDATE => tapo_upd,
TDO1 => tapi_tdo1,
TDO2 => tapi_tdo2);
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2; tapo_capt <= '0';
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex2_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex2_tap is
component BSCAN_VIRTEX2
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
begin
u0 : BSCAN_VIRTEX2
port map (CAPTURE => tapo_capt,
DRCK1 => drck1,
DRCK2 => drck2,
RESET => tapo_rst,
SEL1 => sel1,
SEL2 => sel2,
SHIFT => tapo_shft,
TDI => tapo_tdi,
UPDATE => tapo_upd,
TDO1 => tapi_tdo1,
TDO2 => tapi_tdo2);
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BSCAN_SPARTAN3;
-- pragma translate_on
entity spartan3_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of spartan3_tap is
component BSCAN_SPARTAN3
port (CAPTURE : out STD_ULOGIC;
DRCK1 : out STD_ULOGIC;
DRCK2 : out STD_ULOGIC;
RESET : out STD_ULOGIC;
SEL1 : out STD_ULOGIC;
SEL2 : out STD_ULOGIC;
SHIFT : out STD_ULOGIC;
TDI : out STD_ULOGIC;
UPDATE : out STD_ULOGIC;
TDO1 : in STD_ULOGIC;
TDO2 : in STD_ULOGIC);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
begin
u0 : BSCAN_SPARTAN3
port map (CAPTURE => tapo_capt,
DRCK1 => drck1,
DRCK2 => drck2,
RESET => tapo_rst,
SEL1 => sel1,
SEL2 => sel2,
SHIFT => tapo_shft,
TDI => tapo_tdi,
UPDATE => tapo_upd,
TDO1 => tapi_tdo1,
TDO2 => tapi_tdo2);
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BSCAN_VIRTEX4;
-- pragma translate_on
entity virtex4_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex4_tap is
component BSCAN_VIRTEX4 generic ( JTAG_CHAIN : integer := 1);
port ( CAPTURE : out std_ulogic;
DRCK : out std_ulogic;
RESET : out std_ulogic;
SEL : out std_ulogic;
SHIFT : out std_ulogic;
TDI : out std_ulogic;
UPDATE : out std_ulogic;
TDO : in std_ulogic);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_VIRTEX4
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1
);
u1 : BSCAN_VIRTEX4
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BSCAN_VIRTEX5;
-- pragma translate_on
entity virtex5_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex5_tap is
component BSCAN_VIRTEX5 generic ( JTAG_CHAIN : integer := 1);
port ( CAPTURE : out std_ulogic;
DRCK : out std_ulogic;
RESET : out std_ulogic;
SEL : out std_ulogic;
SHIFT : out std_ulogic;
TDI : out std_ulogic;
UPDATE : out std_ulogic;
TDO : in std_ulogic);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_VIRTEX5
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1
);
u1 : BSCAN_VIRTEX5
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_tck <= drck1 when sel1 = '1' else drck2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex6_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex6_tap is
component BSCAN_VIRTEX6
generic (
DISABLE_JTAG : boolean := FALSE;
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_VIRTEX6
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCAN_VIRTEX6
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity spartan6_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of spartan6_tap is
component BSCAN_SPARTAN6
generic (
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCAN_SPARTAN6
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCAN_SPARTAN6
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity virtex7_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of virtex7_tap is
component BSCANE2
generic (
DISABLE_JTAG : string := "FALSE";
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCANE2
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCANE2
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity kintex7_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of kintex7_tap is
component BSCANE2
generic (
DISABLE_JTAG : string := "FALSE";
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCANE2
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCANE2
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.all;
-- pragma translate_on
entity artix7_tap is
port (
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of artix7_tap is
component BSCANE2
generic (
DISABLE_JTAG : string := "FALSE";
JTAG_CHAIN : integer := 1
);
port (
CAPTURE : out std_ulogic := 'H';
DRCK : out std_ulogic := 'H';
RESET : out std_ulogic := 'H';
RUNTEST : out std_ulogic := 'L';
SEL : out std_ulogic := 'L';
SHIFT : out std_ulogic := 'L';
TCK : out std_ulogic := 'L';
TDI : out std_ulogic := 'L';
TMS : out std_ulogic := 'L';
UPDATE : out std_ulogic := 'L';
TDO : in std_ulogic := 'X'
);
end component;
signal drck1, drck2, sel1, sel2 : std_ulogic;
signal capt1, capt2, rst1, rst2 : std_ulogic;
signal shift1, shift2, tdi1, tdi2 : std_ulogic;
signal update1, update2 : std_ulogic;
attribute dont_touch : boolean;
attribute dont_touch of u0 : label is true;
attribute dont_touch of u1 : label is true;
begin
u0 : BSCANE2
generic map (JTAG_CHAIN => 1)
port map (
CAPTURE => capt1,
DRCK => drck1,
RESET => rst1,
SEL => sel1,
SHIFT => shift1,
TDI => tdi1,
UPDATE => update1,
TDO => tapi_tdo1,
TCK => tapo_tck
);
u1 : BSCANE2
generic map (JTAG_CHAIN => 2)
port map (
CAPTURE => capt2,
DRCK => drck2,
RESET => rst2,
SEL => sel2,
SHIFT => shift2,
TDI => tdi2,
UPDATE => update2,
TDO => tapi_tdo2
);
tapo_capt <= capt1 when sel1 = '1' else capt2;
tapo_rst <= rst1 when sel1 = '1' else rst2;
tapo_shft <= shift1 when sel1 = '1' else shift2;
tapo_tdi <= tdi1 when sel1 = '1' else tdi2;
tapo_upd <= update1 when sel1 ='1' else update2;
tapo_xsel1 <= sel1; tapo_xsel2 <= sel2;
end;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_noqueue.vhd
-- Description: This entity provides the descriptor update for the No Queue mode
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_noqueue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33
-- 1 IOC bit + 32 Update Status Bits
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
updt2_active : in std_logic ; --
updt2_queue_empty : out std_logic ; --
updt2_ioc : out std_logic ; --
updt2_ioc_irq_set : in std_logic ; --
--
dma2_interr : out std_logic ; --
dma2_slverr : out std_logic ; --
dma2_decerr : out std_logic ; --
dma2_interr_set : in std_logic ; --
dma2_slverr_set : in std_logic ; --
dma2_decerr_set : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface In **-- --
--*********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
-- Update Pointer Stream --
s_axis2_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis2_updtptr_tvalid : in std_logic ; --
s_axis2_updtptr_tready : out std_logic ; --
s_axis2_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis2_updtsts_tvalid : in std_logic ; --
s_axis2_updtsts_tready : out std_logic ; --
s_axis2_updtsts_tlast : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface Out**-- --
--*********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_noqueue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_noqueue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Contstants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal writing_curdesc : std_logic := '0';
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
signal writing_status : std_logic := '0';
signal curdesc_tready : std_logic := '0';
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
signal writing_status_re_ch1 : std_logic := '0';
signal writing_status_re_ch2 : std_logic := '0';
signal updt_active_int : std_logic := '0';
signal s_axis_updtptr_tvalid_int : std_logic := '0';
signal s_axis_updtsts_tvalid_int : std_logic := '0';
signal s_axis_updtsts_tlast_int : std_logic := '0';
signal s_axis_updtptr_tdata_int : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axis_qual : std_logic := '0';
signal s_axis2_qual : std_logic := '0';
signal m_axis_updt_tdata_mm2s : std_logic_vector (31 downto 0); --
signal m_axis_updt_tlast_mm2s : std_logic ; --
signal m_axis_updt_tvalid_mm2s : std_logic ;
signal m_axis_updt_tdata_s2mm : std_logic_vector (31 downto 0); --
signal m_axis_updt_tlast_s2mm : std_logic ; --
signal m_axis_updt_tvalid_s2mm : std_logic ;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
m_axis_updt_tdata <= m_axis_updt_tdata_mm2s when updt_active = '1' else
m_axis_updt_tdata_s2mm;
m_axis_updt_tvalid <= m_axis_updt_tvalid_mm2s when updt_active = '1' else
m_axis_updt_tvalid_s2mm;
m_axis_updt_tlast <= m_axis_updt_tlast_mm2s when updt_active = '1' else
m_axis_updt_tlast_s2mm;
updt_active_int <= updt_active or updt2_active;
s_axis_updtptr_tvalid_int <= s_axis_updtptr_tvalid or s_axis2_updtptr_tvalid;
s_axis_updtsts_tvalid_int <= s_axis_updtsts_tvalid or s_axis2_updtsts_tvalid;
s_axis_updtsts_tlast_int <= s_axis_updtsts_tlast or s_axis2_updtsts_tlast;
s_axis_qual <= s_axis_updtsts_tvalid and s_axis_updtsts_tlast and updt_active;
s_axis2_qual <= s_axis2_updtsts_tvalid and s_axis2_updtsts_tlast and updt2_active;
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- the channel
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active or updt2_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re <= (updt_active or updt2_active) and not updt_active_d1;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active_int,
s_axis_updtptr_tvalid_int,
updt_active, updt2_active,
s_axis_qual, s_axis2_qual,
s_axis_updtptr_tvalid,
s_axis2_updtptr_tvalid,
s_axis_updtsts_tvalid_int,
m_axis_updt_tready)
begin
write_curdesc_lsb <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
writing_curdesc <= '0';
curdesc_tready <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if((s_axis_updtptr_tvalid = '1' and updt_active = '1') or
(s_axis2_updtptr_tvalid = '1' and updt2_active = '1')) then
writing_curdesc <= '1';
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor
when READ_CURDESC_LSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(s_axis_updtptr_tvalid_int = '1' and updt_active_int = '1')then
write_curdesc_lsb <= '1';
-- pntr_ns <= READ_CURDESC_MSB;
pntr_ns <= WRITE_STATUS;
else
-- coverage off
pntr_ns <= READ_CURDESC_LSB;
-- coverage on
end if;
-- coverage off
---------------------------------------------------------------
-- Get upper current descriptor
when READ_CURDESC_MSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
if(s_axis_updtptr_tvalid_int = '1')then
write_curdesc_msb <= '1';
pntr_ns <= WRITE_STATUS;
else
pntr_ns <= READ_CURDESC_MSB;
end if;
-- coverage on
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
writing_status <= '1'; --s_axis_updtsts_tvalid_int;
if((s_axis_qual = '1' and m_axis_updt_tready = '1') or
(s_axis2_qual = '1' and m_axis_updt_tready = '1')) then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
-- coverage off
when others =>
pntr_ns <= IDLE;
-- coverage on
end case;
end process CURDESC_PNTR_STATE;
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
-- Status stream signals
m_axis_updt_tdata_mm2s <= s_axis_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid_mm2s <= s_axis_updtsts_tvalid and writing_status;
m_axis_updt_tlast_mm2s <= s_axis_updtsts_tlast and writing_status;
s_axis_updtsts_tready <= m_axis_updt_tready and writing_status and updt_active;
-- Pointer stream signals
s_axis_updtptr_tready <= curdesc_tready and updt_active;
-- Indicate need for channel service for update state machine
updt_queue_empty <= not (s_axis_updtsts_tvalid); -- and writing_status);
m_axis_updt_tdata_s2mm <= s_axis2_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid_s2mm <= s_axis2_updtsts_tvalid and writing_status;
m_axis_updt_tlast_s2mm <= s_axis2_updtsts_tlast and writing_status;
s_axis2_updtsts_tready <= m_axis_updt_tready and writing_status and updt2_active;
-- Pointer stream signals
s_axis2_updtptr_tready <= curdesc_tready and updt2_active;
-- Indicate need for channel service for update state machine
updt2_queue_empty <= not (s_axis2_updtsts_tvalid); -- and writing_status);
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
s_axis_updtptr_tdata_int <= s_axis_updtptr_tdata when (updt_active = '1') else
s_axis2_updtptr_tdata;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1')then
updt_curdesc(31 downto 0) <= s_axis_updtptr_tdata_int(31 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(63 downto 32) <= (others => '0');
updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_lsb = '1')then
updt_curdesc(63 downto 32) <= s_axis_updtptr_tdata_int(C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_lsb = '1')then
-- elsif(write_curdesc_msb = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_NO_UPR_MSB_CURDESC;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
writing_status_re_ch1 <= writing_status_re and updt_active;
writing_status_re_ch2 <= writing_status_re and updt2_active;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re_ch1 = '1')then
updt_ioc <= s_axis_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_interr <= s_axis_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_slverr <= s_axis_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_decerr <= s_axis_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG2_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt2_ioc_irq_set = '1')then
updt2_ioc <= '0';
elsif(writing_status_re_ch2 = '1')then
updt2_ioc <= s_axis2_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG2_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE2_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_interr_set = '1')then
dma2_interr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_interr <= s_axis2_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE2_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE2_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_slverr_set = '1')then
dma2_slverr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_slverr <= s_axis2_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE2_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE2_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_decerr_set = '1')then
dma2_decerr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_decerr <= s_axis2_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE2_DMADEC_ERROR;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_noqueue.vhd
-- Description: This entity provides the descriptor update for the No Queue mode
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_noqueue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33
-- 1 IOC bit + 32 Update Status Bits
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
updt2_active : in std_logic ; --
updt2_queue_empty : out std_logic ; --
updt2_ioc : out std_logic ; --
updt2_ioc_irq_set : in std_logic ; --
--
dma2_interr : out std_logic ; --
dma2_slverr : out std_logic ; --
dma2_decerr : out std_logic ; --
dma2_interr_set : in std_logic ; --
dma2_slverr_set : in std_logic ; --
dma2_decerr_set : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface In **-- --
--*********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
-- Update Pointer Stream --
s_axis2_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis2_updtptr_tvalid : in std_logic ; --
s_axis2_updtptr_tready : out std_logic ; --
s_axis2_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis2_updtsts_tvalid : in std_logic ; --
s_axis2_updtsts_tready : out std_logic ; --
s_axis2_updtsts_tlast : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface Out**-- --
--*********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_noqueue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_noqueue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Contstants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal writing_curdesc : std_logic := '0';
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
signal writing_status : std_logic := '0';
signal curdesc_tready : std_logic := '0';
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
signal writing_status_re_ch1 : std_logic := '0';
signal writing_status_re_ch2 : std_logic := '0';
signal updt_active_int : std_logic := '0';
signal s_axis_updtptr_tvalid_int : std_logic := '0';
signal s_axis_updtsts_tvalid_int : std_logic := '0';
signal s_axis_updtsts_tlast_int : std_logic := '0';
signal s_axis_updtptr_tdata_int : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axis_qual : std_logic := '0';
signal s_axis2_qual : std_logic := '0';
signal m_axis_updt_tdata_mm2s : std_logic_vector (31 downto 0); --
signal m_axis_updt_tlast_mm2s : std_logic ; --
signal m_axis_updt_tvalid_mm2s : std_logic ;
signal m_axis_updt_tdata_s2mm : std_logic_vector (31 downto 0); --
signal m_axis_updt_tlast_s2mm : std_logic ; --
signal m_axis_updt_tvalid_s2mm : std_logic ;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
m_axis_updt_tdata <= m_axis_updt_tdata_mm2s when updt_active = '1' else
m_axis_updt_tdata_s2mm;
m_axis_updt_tvalid <= m_axis_updt_tvalid_mm2s when updt_active = '1' else
m_axis_updt_tvalid_s2mm;
m_axis_updt_tlast <= m_axis_updt_tlast_mm2s when updt_active = '1' else
m_axis_updt_tlast_s2mm;
updt_active_int <= updt_active or updt2_active;
s_axis_updtptr_tvalid_int <= s_axis_updtptr_tvalid or s_axis2_updtptr_tvalid;
s_axis_updtsts_tvalid_int <= s_axis_updtsts_tvalid or s_axis2_updtsts_tvalid;
s_axis_updtsts_tlast_int <= s_axis_updtsts_tlast or s_axis2_updtsts_tlast;
s_axis_qual <= s_axis_updtsts_tvalid and s_axis_updtsts_tlast and updt_active;
s_axis2_qual <= s_axis2_updtsts_tvalid and s_axis2_updtsts_tlast and updt2_active;
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- the channel
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active or updt2_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re <= (updt_active or updt2_active) and not updt_active_d1;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active_int,
s_axis_updtptr_tvalid_int,
updt_active, updt2_active,
s_axis_qual, s_axis2_qual,
s_axis_updtptr_tvalid,
s_axis2_updtptr_tvalid,
s_axis_updtsts_tvalid_int,
m_axis_updt_tready)
begin
write_curdesc_lsb <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
writing_curdesc <= '0';
curdesc_tready <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if((s_axis_updtptr_tvalid = '1' and updt_active = '1') or
(s_axis2_updtptr_tvalid = '1' and updt2_active = '1')) then
writing_curdesc <= '1';
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor
when READ_CURDESC_LSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(s_axis_updtptr_tvalid_int = '1' and updt_active_int = '1')then
write_curdesc_lsb <= '1';
-- pntr_ns <= READ_CURDESC_MSB;
pntr_ns <= WRITE_STATUS;
else
-- coverage off
pntr_ns <= READ_CURDESC_LSB;
-- coverage on
end if;
-- coverage off
---------------------------------------------------------------
-- Get upper current descriptor
when READ_CURDESC_MSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
if(s_axis_updtptr_tvalid_int = '1')then
write_curdesc_msb <= '1';
pntr_ns <= WRITE_STATUS;
else
pntr_ns <= READ_CURDESC_MSB;
end if;
-- coverage on
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
writing_status <= '1'; --s_axis_updtsts_tvalid_int;
if((s_axis_qual = '1' and m_axis_updt_tready = '1') or
(s_axis2_qual = '1' and m_axis_updt_tready = '1')) then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
-- coverage off
when others =>
pntr_ns <= IDLE;
-- coverage on
end case;
end process CURDESC_PNTR_STATE;
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
-- Status stream signals
m_axis_updt_tdata_mm2s <= s_axis_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid_mm2s <= s_axis_updtsts_tvalid and writing_status;
m_axis_updt_tlast_mm2s <= s_axis_updtsts_tlast and writing_status;
s_axis_updtsts_tready <= m_axis_updt_tready and writing_status and updt_active;
-- Pointer stream signals
s_axis_updtptr_tready <= curdesc_tready and updt_active;
-- Indicate need for channel service for update state machine
updt_queue_empty <= not (s_axis_updtsts_tvalid); -- and writing_status);
m_axis_updt_tdata_s2mm <= s_axis2_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid_s2mm <= s_axis2_updtsts_tvalid and writing_status;
m_axis_updt_tlast_s2mm <= s_axis2_updtsts_tlast and writing_status;
s_axis2_updtsts_tready <= m_axis_updt_tready and writing_status and updt2_active;
-- Pointer stream signals
s_axis2_updtptr_tready <= curdesc_tready and updt2_active;
-- Indicate need for channel service for update state machine
updt2_queue_empty <= not (s_axis2_updtsts_tvalid); -- and writing_status);
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
s_axis_updtptr_tdata_int <= s_axis_updtptr_tdata when (updt_active = '1') else
s_axis2_updtptr_tdata;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1')then
updt_curdesc(31 downto 0) <= s_axis_updtptr_tdata_int(31 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(63 downto 32) <= (others => '0');
updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_lsb = '1')then
updt_curdesc(63 downto 32) <= s_axis_updtptr_tdata_int(C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_lsb = '1')then
-- elsif(write_curdesc_msb = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_NO_UPR_MSB_CURDESC;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
writing_status_re_ch1 <= writing_status_re and updt_active;
writing_status_re_ch2 <= writing_status_re and updt2_active;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re_ch1 = '1')then
updt_ioc <= s_axis_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_interr <= s_axis_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_slverr <= s_axis_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_decerr <= s_axis_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG2_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt2_ioc_irq_set = '1')then
updt2_ioc <= '0';
elsif(writing_status_re_ch2 = '1')then
updt2_ioc <= s_axis2_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG2_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE2_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_interr_set = '1')then
dma2_interr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_interr <= s_axis2_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE2_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE2_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_slverr_set = '1')then
dma2_slverr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_slverr <= s_axis2_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE2_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE2_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_decerr_set = '1')then
dma2_decerr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_decerr <= s_axis2_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE2_DMADEC_ERROR;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_noqueue.vhd
-- Description: This entity provides the descriptor update for the No Queue mode
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_noqueue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33
-- 1 IOC bit + 32 Update Status Bits
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
updt2_active : in std_logic ; --
updt2_queue_empty : out std_logic ; --
updt2_ioc : out std_logic ; --
updt2_ioc_irq_set : in std_logic ; --
--
dma2_interr : out std_logic ; --
dma2_slverr : out std_logic ; --
dma2_decerr : out std_logic ; --
dma2_interr_set : in std_logic ; --
dma2_slverr_set : in std_logic ; --
dma2_decerr_set : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface In **-- --
--*********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
-- Update Pointer Stream --
s_axis2_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis2_updtptr_tvalid : in std_logic ; --
s_axis2_updtptr_tready : out std_logic ; --
s_axis2_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis2_updtsts_tvalid : in std_logic ; --
s_axis2_updtsts_tready : out std_logic ; --
s_axis2_updtsts_tlast : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface Out**-- --
--*********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_noqueue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_noqueue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Contstants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal writing_curdesc : std_logic := '0';
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
signal writing_status : std_logic := '0';
signal curdesc_tready : std_logic := '0';
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
signal writing_status_re_ch1 : std_logic := '0';
signal writing_status_re_ch2 : std_logic := '0';
signal updt_active_int : std_logic := '0';
signal s_axis_updtptr_tvalid_int : std_logic := '0';
signal s_axis_updtsts_tvalid_int : std_logic := '0';
signal s_axis_updtsts_tlast_int : std_logic := '0';
signal s_axis_updtptr_tdata_int : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axis_qual : std_logic := '0';
signal s_axis2_qual : std_logic := '0';
signal m_axis_updt_tdata_mm2s : std_logic_vector (31 downto 0); --
signal m_axis_updt_tlast_mm2s : std_logic ; --
signal m_axis_updt_tvalid_mm2s : std_logic ;
signal m_axis_updt_tdata_s2mm : std_logic_vector (31 downto 0); --
signal m_axis_updt_tlast_s2mm : std_logic ; --
signal m_axis_updt_tvalid_s2mm : std_logic ;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
m_axis_updt_tdata <= m_axis_updt_tdata_mm2s when updt_active = '1' else
m_axis_updt_tdata_s2mm;
m_axis_updt_tvalid <= m_axis_updt_tvalid_mm2s when updt_active = '1' else
m_axis_updt_tvalid_s2mm;
m_axis_updt_tlast <= m_axis_updt_tlast_mm2s when updt_active = '1' else
m_axis_updt_tlast_s2mm;
updt_active_int <= updt_active or updt2_active;
s_axis_updtptr_tvalid_int <= s_axis_updtptr_tvalid or s_axis2_updtptr_tvalid;
s_axis_updtsts_tvalid_int <= s_axis_updtsts_tvalid or s_axis2_updtsts_tvalid;
s_axis_updtsts_tlast_int <= s_axis_updtsts_tlast or s_axis2_updtsts_tlast;
s_axis_qual <= s_axis_updtsts_tvalid and s_axis_updtsts_tlast and updt_active;
s_axis2_qual <= s_axis2_updtsts_tvalid and s_axis2_updtsts_tlast and updt2_active;
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- the channel
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active or updt2_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re <= (updt_active or updt2_active) and not updt_active_d1;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active_int,
s_axis_updtptr_tvalid_int,
updt_active, updt2_active,
s_axis_qual, s_axis2_qual,
s_axis_updtptr_tvalid,
s_axis2_updtptr_tvalid,
s_axis_updtsts_tvalid_int,
m_axis_updt_tready)
begin
write_curdesc_lsb <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
writing_curdesc <= '0';
curdesc_tready <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if((s_axis_updtptr_tvalid = '1' and updt_active = '1') or
(s_axis2_updtptr_tvalid = '1' and updt2_active = '1')) then
writing_curdesc <= '1';
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor
when READ_CURDESC_LSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(s_axis_updtptr_tvalid_int = '1' and updt_active_int = '1')then
write_curdesc_lsb <= '1';
-- pntr_ns <= READ_CURDESC_MSB;
pntr_ns <= WRITE_STATUS;
else
-- coverage off
pntr_ns <= READ_CURDESC_LSB;
-- coverage on
end if;
-- coverage off
---------------------------------------------------------------
-- Get upper current descriptor
when READ_CURDESC_MSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
if(s_axis_updtptr_tvalid_int = '1')then
write_curdesc_msb <= '1';
pntr_ns <= WRITE_STATUS;
else
pntr_ns <= READ_CURDESC_MSB;
end if;
-- coverage on
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
writing_status <= '1'; --s_axis_updtsts_tvalid_int;
if((s_axis_qual = '1' and m_axis_updt_tready = '1') or
(s_axis2_qual = '1' and m_axis_updt_tready = '1')) then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
-- coverage off
when others =>
pntr_ns <= IDLE;
-- coverage on
end case;
end process CURDESC_PNTR_STATE;
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
-- Status stream signals
m_axis_updt_tdata_mm2s <= s_axis_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid_mm2s <= s_axis_updtsts_tvalid and writing_status;
m_axis_updt_tlast_mm2s <= s_axis_updtsts_tlast and writing_status;
s_axis_updtsts_tready <= m_axis_updt_tready and writing_status and updt_active;
-- Pointer stream signals
s_axis_updtptr_tready <= curdesc_tready and updt_active;
-- Indicate need for channel service for update state machine
updt_queue_empty <= not (s_axis_updtsts_tvalid); -- and writing_status);
m_axis_updt_tdata_s2mm <= s_axis2_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid_s2mm <= s_axis2_updtsts_tvalid and writing_status;
m_axis_updt_tlast_s2mm <= s_axis2_updtsts_tlast and writing_status;
s_axis2_updtsts_tready <= m_axis_updt_tready and writing_status and updt2_active;
-- Pointer stream signals
s_axis2_updtptr_tready <= curdesc_tready and updt2_active;
-- Indicate need for channel service for update state machine
updt2_queue_empty <= not (s_axis2_updtsts_tvalid); -- and writing_status);
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
s_axis_updtptr_tdata_int <= s_axis_updtptr_tdata when (updt_active = '1') else
s_axis2_updtptr_tdata;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1')then
updt_curdesc(31 downto 0) <= s_axis_updtptr_tdata_int(31 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(63 downto 32) <= (others => '0');
updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_lsb = '1')then
updt_curdesc(63 downto 32) <= s_axis_updtptr_tdata_int(C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_lsb = '1')then
-- elsif(write_curdesc_msb = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_NO_UPR_MSB_CURDESC;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
writing_status_re_ch1 <= writing_status_re and updt_active;
writing_status_re_ch2 <= writing_status_re and updt2_active;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re_ch1 = '1')then
updt_ioc <= s_axis_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_interr <= s_axis_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_slverr <= s_axis_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_decerr <= s_axis_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG2_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt2_ioc_irq_set = '1')then
updt2_ioc <= '0';
elsif(writing_status_re_ch2 = '1')then
updt2_ioc <= s_axis2_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG2_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE2_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_interr_set = '1')then
dma2_interr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_interr <= s_axis2_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE2_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE2_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_slverr_set = '1')then
dma2_slverr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_slverr <= s_axis2_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE2_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE2_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_decerr_set = '1')then
dma2_decerr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_decerr <= s_axis2_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE2_DMADEC_ERROR;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_noqueue.vhd
-- Description: This entity provides the descriptor update for the No Queue mode
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_noqueue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33
-- 1 IOC bit + 32 Update Status Bits
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
updt2_active : in std_logic ; --
updt2_queue_empty : out std_logic ; --
updt2_ioc : out std_logic ; --
updt2_ioc_irq_set : in std_logic ; --
--
dma2_interr : out std_logic ; --
dma2_slverr : out std_logic ; --
dma2_decerr : out std_logic ; --
dma2_interr_set : in std_logic ; --
dma2_slverr_set : in std_logic ; --
dma2_decerr_set : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface In **-- --
--*********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
-- Update Pointer Stream --
s_axis2_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis2_updtptr_tvalid : in std_logic ; --
s_axis2_updtptr_tready : out std_logic ; --
s_axis2_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis2_updtsts_tvalid : in std_logic ; --
s_axis2_updtsts_tready : out std_logic ; --
s_axis2_updtsts_tlast : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface Out**-- --
--*********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_noqueue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_noqueue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Contstants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal writing_curdesc : std_logic := '0';
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
signal writing_status : std_logic := '0';
signal curdesc_tready : std_logic := '0';
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
signal writing_status_re_ch1 : std_logic := '0';
signal writing_status_re_ch2 : std_logic := '0';
signal updt_active_int : std_logic := '0';
signal s_axis_updtptr_tvalid_int : std_logic := '0';
signal s_axis_updtsts_tvalid_int : std_logic := '0';
signal s_axis_updtsts_tlast_int : std_logic := '0';
signal s_axis_updtptr_tdata_int : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axis_qual : std_logic := '0';
signal s_axis2_qual : std_logic := '0';
signal m_axis_updt_tdata_mm2s : std_logic_vector (31 downto 0); --
signal m_axis_updt_tlast_mm2s : std_logic ; --
signal m_axis_updt_tvalid_mm2s : std_logic ;
signal m_axis_updt_tdata_s2mm : std_logic_vector (31 downto 0); --
signal m_axis_updt_tlast_s2mm : std_logic ; --
signal m_axis_updt_tvalid_s2mm : std_logic ;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
m_axis_updt_tdata <= m_axis_updt_tdata_mm2s when updt_active = '1' else
m_axis_updt_tdata_s2mm;
m_axis_updt_tvalid <= m_axis_updt_tvalid_mm2s when updt_active = '1' else
m_axis_updt_tvalid_s2mm;
m_axis_updt_tlast <= m_axis_updt_tlast_mm2s when updt_active = '1' else
m_axis_updt_tlast_s2mm;
updt_active_int <= updt_active or updt2_active;
s_axis_updtptr_tvalid_int <= s_axis_updtptr_tvalid or s_axis2_updtptr_tvalid;
s_axis_updtsts_tvalid_int <= s_axis_updtsts_tvalid or s_axis2_updtsts_tvalid;
s_axis_updtsts_tlast_int <= s_axis_updtsts_tlast or s_axis2_updtsts_tlast;
s_axis_qual <= s_axis_updtsts_tvalid and s_axis_updtsts_tlast and updt_active;
s_axis2_qual <= s_axis2_updtsts_tvalid and s_axis2_updtsts_tlast and updt2_active;
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- the channel
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active or updt2_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re <= (updt_active or updt2_active) and not updt_active_d1;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active_int,
s_axis_updtptr_tvalid_int,
updt_active, updt2_active,
s_axis_qual, s_axis2_qual,
s_axis_updtptr_tvalid,
s_axis2_updtptr_tvalid,
s_axis_updtsts_tvalid_int,
m_axis_updt_tready)
begin
write_curdesc_lsb <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
writing_curdesc <= '0';
curdesc_tready <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if((s_axis_updtptr_tvalid = '1' and updt_active = '1') or
(s_axis2_updtptr_tvalid = '1' and updt2_active = '1')) then
writing_curdesc <= '1';
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor
when READ_CURDESC_LSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(s_axis_updtptr_tvalid_int = '1' and updt_active_int = '1')then
write_curdesc_lsb <= '1';
-- pntr_ns <= READ_CURDESC_MSB;
pntr_ns <= WRITE_STATUS;
else
-- coverage off
pntr_ns <= READ_CURDESC_LSB;
-- coverage on
end if;
-- coverage off
---------------------------------------------------------------
-- Get upper current descriptor
when READ_CURDESC_MSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
if(s_axis_updtptr_tvalid_int = '1')then
write_curdesc_msb <= '1';
pntr_ns <= WRITE_STATUS;
else
pntr_ns <= READ_CURDESC_MSB;
end if;
-- coverage on
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
writing_status <= '1'; --s_axis_updtsts_tvalid_int;
if((s_axis_qual = '1' and m_axis_updt_tready = '1') or
(s_axis2_qual = '1' and m_axis_updt_tready = '1')) then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
-- coverage off
when others =>
pntr_ns <= IDLE;
-- coverage on
end case;
end process CURDESC_PNTR_STATE;
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
-- Status stream signals
m_axis_updt_tdata_mm2s <= s_axis_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid_mm2s <= s_axis_updtsts_tvalid and writing_status;
m_axis_updt_tlast_mm2s <= s_axis_updtsts_tlast and writing_status;
s_axis_updtsts_tready <= m_axis_updt_tready and writing_status and updt_active;
-- Pointer stream signals
s_axis_updtptr_tready <= curdesc_tready and updt_active;
-- Indicate need for channel service for update state machine
updt_queue_empty <= not (s_axis_updtsts_tvalid); -- and writing_status);
m_axis_updt_tdata_s2mm <= s_axis2_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid_s2mm <= s_axis2_updtsts_tvalid and writing_status;
m_axis_updt_tlast_s2mm <= s_axis2_updtsts_tlast and writing_status;
s_axis2_updtsts_tready <= m_axis_updt_tready and writing_status and updt2_active;
-- Pointer stream signals
s_axis2_updtptr_tready <= curdesc_tready and updt2_active;
-- Indicate need for channel service for update state machine
updt2_queue_empty <= not (s_axis2_updtsts_tvalid); -- and writing_status);
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
s_axis_updtptr_tdata_int <= s_axis_updtptr_tdata when (updt_active = '1') else
s_axis2_updtptr_tdata;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1')then
updt_curdesc(31 downto 0) <= s_axis_updtptr_tdata_int(31 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(63 downto 32) <= (others => '0');
updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_lsb = '1')then
updt_curdesc(63 downto 32) <= s_axis_updtptr_tdata_int(C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_lsb = '1')then
-- elsif(write_curdesc_msb = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_NO_UPR_MSB_CURDESC;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
writing_status_re_ch1 <= writing_status_re and updt_active;
writing_status_re_ch2 <= writing_status_re and updt2_active;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re_ch1 = '1')then
updt_ioc <= s_axis_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_interr <= s_axis_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_slverr <= s_axis_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_decerr <= s_axis_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG2_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt2_ioc_irq_set = '1')then
updt2_ioc <= '0';
elsif(writing_status_re_ch2 = '1')then
updt2_ioc <= s_axis2_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG2_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE2_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_interr_set = '1')then
dma2_interr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_interr <= s_axis2_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE2_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE2_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_slverr_set = '1')then
dma2_slverr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_slverr <= s_axis2_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE2_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE2_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_decerr_set = '1')then
dma2_decerr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_decerr <= s_axis2_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE2_DMADEC_ERROR;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_noqueue.vhd
-- Description: This entity provides the descriptor update for the No Queue mode
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_noqueue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33
-- 1 IOC bit + 32 Update Status Bits
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
updt2_active : in std_logic ; --
updt2_queue_empty : out std_logic ; --
updt2_ioc : out std_logic ; --
updt2_ioc_irq_set : in std_logic ; --
--
dma2_interr : out std_logic ; --
dma2_slverr : out std_logic ; --
dma2_decerr : out std_logic ; --
dma2_interr_set : in std_logic ; --
dma2_slverr_set : in std_logic ; --
dma2_decerr_set : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface In **-- --
--*********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
-- Update Pointer Stream --
s_axis2_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis2_updtptr_tvalid : in std_logic ; --
s_axis2_updtptr_tready : out std_logic ; --
s_axis2_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis2_updtsts_tvalid : in std_logic ; --
s_axis2_updtsts_tready : out std_logic ; --
s_axis2_updtsts_tlast : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface Out**-- --
--*********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_noqueue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_noqueue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Contstants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal writing_curdesc : std_logic := '0';
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
signal writing_status : std_logic := '0';
signal curdesc_tready : std_logic := '0';
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
signal writing_status_re_ch1 : std_logic := '0';
signal writing_status_re_ch2 : std_logic := '0';
signal updt_active_int : std_logic := '0';
signal s_axis_updtptr_tvalid_int : std_logic := '0';
signal s_axis_updtsts_tvalid_int : std_logic := '0';
signal s_axis_updtsts_tlast_int : std_logic := '0';
signal s_axis_updtptr_tdata_int : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axis_qual : std_logic := '0';
signal s_axis2_qual : std_logic := '0';
signal m_axis_updt_tdata_mm2s : std_logic_vector (31 downto 0); --
signal m_axis_updt_tlast_mm2s : std_logic ; --
signal m_axis_updt_tvalid_mm2s : std_logic ;
signal m_axis_updt_tdata_s2mm : std_logic_vector (31 downto 0); --
signal m_axis_updt_tlast_s2mm : std_logic ; --
signal m_axis_updt_tvalid_s2mm : std_logic ;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
m_axis_updt_tdata <= m_axis_updt_tdata_mm2s when updt_active = '1' else
m_axis_updt_tdata_s2mm;
m_axis_updt_tvalid <= m_axis_updt_tvalid_mm2s when updt_active = '1' else
m_axis_updt_tvalid_s2mm;
m_axis_updt_tlast <= m_axis_updt_tlast_mm2s when updt_active = '1' else
m_axis_updt_tlast_s2mm;
updt_active_int <= updt_active or updt2_active;
s_axis_updtptr_tvalid_int <= s_axis_updtptr_tvalid or s_axis2_updtptr_tvalid;
s_axis_updtsts_tvalid_int <= s_axis_updtsts_tvalid or s_axis2_updtsts_tvalid;
s_axis_updtsts_tlast_int <= s_axis_updtsts_tlast or s_axis2_updtsts_tlast;
s_axis_qual <= s_axis_updtsts_tvalid and s_axis_updtsts_tlast and updt_active;
s_axis2_qual <= s_axis2_updtsts_tvalid and s_axis2_updtsts_tlast and updt2_active;
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- the channel
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active or updt2_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re <= (updt_active or updt2_active) and not updt_active_d1;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active_int,
s_axis_updtptr_tvalid_int,
updt_active, updt2_active,
s_axis_qual, s_axis2_qual,
s_axis_updtptr_tvalid,
s_axis2_updtptr_tvalid,
s_axis_updtsts_tvalid_int,
m_axis_updt_tready)
begin
write_curdesc_lsb <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
writing_curdesc <= '0';
curdesc_tready <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if((s_axis_updtptr_tvalid = '1' and updt_active = '1') or
(s_axis2_updtptr_tvalid = '1' and updt2_active = '1')) then
writing_curdesc <= '1';
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor
when READ_CURDESC_LSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(s_axis_updtptr_tvalid_int = '1' and updt_active_int = '1')then
write_curdesc_lsb <= '1';
-- pntr_ns <= READ_CURDESC_MSB;
pntr_ns <= WRITE_STATUS;
else
-- coverage off
pntr_ns <= READ_CURDESC_LSB;
-- coverage on
end if;
-- coverage off
---------------------------------------------------------------
-- Get upper current descriptor
when READ_CURDESC_MSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
if(s_axis_updtptr_tvalid_int = '1')then
write_curdesc_msb <= '1';
pntr_ns <= WRITE_STATUS;
else
pntr_ns <= READ_CURDESC_MSB;
end if;
-- coverage on
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
writing_status <= '1'; --s_axis_updtsts_tvalid_int;
if((s_axis_qual = '1' and m_axis_updt_tready = '1') or
(s_axis2_qual = '1' and m_axis_updt_tready = '1')) then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
-- coverage off
when others =>
pntr_ns <= IDLE;
-- coverage on
end case;
end process CURDESC_PNTR_STATE;
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
-- Status stream signals
m_axis_updt_tdata_mm2s <= s_axis_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid_mm2s <= s_axis_updtsts_tvalid and writing_status;
m_axis_updt_tlast_mm2s <= s_axis_updtsts_tlast and writing_status;
s_axis_updtsts_tready <= m_axis_updt_tready and writing_status and updt_active;
-- Pointer stream signals
s_axis_updtptr_tready <= curdesc_tready and updt_active;
-- Indicate need for channel service for update state machine
updt_queue_empty <= not (s_axis_updtsts_tvalid); -- and writing_status);
m_axis_updt_tdata_s2mm <= s_axis2_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid_s2mm <= s_axis2_updtsts_tvalid and writing_status;
m_axis_updt_tlast_s2mm <= s_axis2_updtsts_tlast and writing_status;
s_axis2_updtsts_tready <= m_axis_updt_tready and writing_status and updt2_active;
-- Pointer stream signals
s_axis2_updtptr_tready <= curdesc_tready and updt2_active;
-- Indicate need for channel service for update state machine
updt2_queue_empty <= not (s_axis2_updtsts_tvalid); -- and writing_status);
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
s_axis_updtptr_tdata_int <= s_axis_updtptr_tdata when (updt_active = '1') else
s_axis2_updtptr_tdata;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1')then
updt_curdesc(31 downto 0) <= s_axis_updtptr_tdata_int(31 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(63 downto 32) <= (others => '0');
updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_lsb = '1')then
updt_curdesc(63 downto 32) <= s_axis_updtptr_tdata_int(C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_lsb = '1')then
-- elsif(write_curdesc_msb = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_NO_UPR_MSB_CURDESC;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
writing_status_re_ch1 <= writing_status_re and updt_active;
writing_status_re_ch2 <= writing_status_re and updt2_active;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re_ch1 = '1')then
updt_ioc <= s_axis_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_interr <= s_axis_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_slverr <= s_axis_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_decerr <= s_axis_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG2_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt2_ioc_irq_set = '1')then
updt2_ioc <= '0';
elsif(writing_status_re_ch2 = '1')then
updt2_ioc <= s_axis2_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG2_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE2_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_interr_set = '1')then
dma2_interr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_interr <= s_axis2_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE2_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE2_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_slverr_set = '1')then
dma2_slverr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_slverr <= s_axis2_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE2_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE2_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_decerr_set = '1')then
dma2_decerr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_decerr <= s_axis2_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE2_DMADEC_ERROR;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_noqueue.vhd
-- Description: This entity provides the descriptor update for the No Queue mode
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_noqueue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33
-- 1 IOC bit + 32 Update Status Bits
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
updt2_active : in std_logic ; --
updt2_queue_empty : out std_logic ; --
updt2_ioc : out std_logic ; --
updt2_ioc_irq_set : in std_logic ; --
--
dma2_interr : out std_logic ; --
dma2_slverr : out std_logic ; --
dma2_decerr : out std_logic ; --
dma2_interr_set : in std_logic ; --
dma2_slverr_set : in std_logic ; --
dma2_decerr_set : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface In **-- --
--*********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
-- Update Pointer Stream --
s_axis2_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis2_updtptr_tvalid : in std_logic ; --
s_axis2_updtptr_tready : out std_logic ; --
s_axis2_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis2_updtsts_tvalid : in std_logic ; --
s_axis2_updtsts_tready : out std_logic ; --
s_axis2_updtsts_tlast : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface Out**-- --
--*********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_noqueue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_noqueue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Contstants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal writing_curdesc : std_logic := '0';
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
signal writing_status : std_logic := '0';
signal curdesc_tready : std_logic := '0';
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
signal writing_status_re_ch1 : std_logic := '0';
signal writing_status_re_ch2 : std_logic := '0';
signal updt_active_int : std_logic := '0';
signal s_axis_updtptr_tvalid_int : std_logic := '0';
signal s_axis_updtsts_tvalid_int : std_logic := '0';
signal s_axis_updtsts_tlast_int : std_logic := '0';
signal s_axis_updtptr_tdata_int : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axis_qual : std_logic := '0';
signal s_axis2_qual : std_logic := '0';
signal m_axis_updt_tdata_mm2s : std_logic_vector (31 downto 0); --
signal m_axis_updt_tlast_mm2s : std_logic ; --
signal m_axis_updt_tvalid_mm2s : std_logic ;
signal m_axis_updt_tdata_s2mm : std_logic_vector (31 downto 0); --
signal m_axis_updt_tlast_s2mm : std_logic ; --
signal m_axis_updt_tvalid_s2mm : std_logic ;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
m_axis_updt_tdata <= m_axis_updt_tdata_mm2s when updt_active = '1' else
m_axis_updt_tdata_s2mm;
m_axis_updt_tvalid <= m_axis_updt_tvalid_mm2s when updt_active = '1' else
m_axis_updt_tvalid_s2mm;
m_axis_updt_tlast <= m_axis_updt_tlast_mm2s when updt_active = '1' else
m_axis_updt_tlast_s2mm;
updt_active_int <= updt_active or updt2_active;
s_axis_updtptr_tvalid_int <= s_axis_updtptr_tvalid or s_axis2_updtptr_tvalid;
s_axis_updtsts_tvalid_int <= s_axis_updtsts_tvalid or s_axis2_updtsts_tvalid;
s_axis_updtsts_tlast_int <= s_axis_updtsts_tlast or s_axis2_updtsts_tlast;
s_axis_qual <= s_axis_updtsts_tvalid and s_axis_updtsts_tlast and updt_active;
s_axis2_qual <= s_axis2_updtsts_tvalid and s_axis2_updtsts_tlast and updt2_active;
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- the channel
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active or updt2_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re <= (updt_active or updt2_active) and not updt_active_d1;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active_int,
s_axis_updtptr_tvalid_int,
updt_active, updt2_active,
s_axis_qual, s_axis2_qual,
s_axis_updtptr_tvalid,
s_axis2_updtptr_tvalid,
s_axis_updtsts_tvalid_int,
m_axis_updt_tready)
begin
write_curdesc_lsb <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
writing_curdesc <= '0';
curdesc_tready <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if((s_axis_updtptr_tvalid = '1' and updt_active = '1') or
(s_axis2_updtptr_tvalid = '1' and updt2_active = '1')) then
writing_curdesc <= '1';
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor
when READ_CURDESC_LSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(s_axis_updtptr_tvalid_int = '1' and updt_active_int = '1')then
write_curdesc_lsb <= '1';
-- pntr_ns <= READ_CURDESC_MSB;
pntr_ns <= WRITE_STATUS;
else
-- coverage off
pntr_ns <= READ_CURDESC_LSB;
-- coverage on
end if;
-- coverage off
---------------------------------------------------------------
-- Get upper current descriptor
when READ_CURDESC_MSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
if(s_axis_updtptr_tvalid_int = '1')then
write_curdesc_msb <= '1';
pntr_ns <= WRITE_STATUS;
else
pntr_ns <= READ_CURDESC_MSB;
end if;
-- coverage on
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
writing_status <= '1'; --s_axis_updtsts_tvalid_int;
if((s_axis_qual = '1' and m_axis_updt_tready = '1') or
(s_axis2_qual = '1' and m_axis_updt_tready = '1')) then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
-- coverage off
when others =>
pntr_ns <= IDLE;
-- coverage on
end case;
end process CURDESC_PNTR_STATE;
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
-- Status stream signals
m_axis_updt_tdata_mm2s <= s_axis_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid_mm2s <= s_axis_updtsts_tvalid and writing_status;
m_axis_updt_tlast_mm2s <= s_axis_updtsts_tlast and writing_status;
s_axis_updtsts_tready <= m_axis_updt_tready and writing_status and updt_active;
-- Pointer stream signals
s_axis_updtptr_tready <= curdesc_tready and updt_active;
-- Indicate need for channel service for update state machine
updt_queue_empty <= not (s_axis_updtsts_tvalid); -- and writing_status);
m_axis_updt_tdata_s2mm <= s_axis2_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid_s2mm <= s_axis2_updtsts_tvalid and writing_status;
m_axis_updt_tlast_s2mm <= s_axis2_updtsts_tlast and writing_status;
s_axis2_updtsts_tready <= m_axis_updt_tready and writing_status and updt2_active;
-- Pointer stream signals
s_axis2_updtptr_tready <= curdesc_tready and updt2_active;
-- Indicate need for channel service for update state machine
updt2_queue_empty <= not (s_axis2_updtsts_tvalid); -- and writing_status);
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
s_axis_updtptr_tdata_int <= s_axis_updtptr_tdata when (updt_active = '1') else
s_axis2_updtptr_tdata;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1')then
updt_curdesc(31 downto 0) <= s_axis_updtptr_tdata_int(31 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(63 downto 32) <= (others => '0');
updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_lsb = '1')then
updt_curdesc(63 downto 32) <= s_axis_updtptr_tdata_int(C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_lsb = '1')then
-- elsif(write_curdesc_msb = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_NO_UPR_MSB_CURDESC;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
writing_status_re_ch1 <= writing_status_re and updt_active;
writing_status_re_ch2 <= writing_status_re and updt2_active;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re_ch1 = '1')then
updt_ioc <= s_axis_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_interr <= s_axis_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_slverr <= s_axis_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_decerr <= s_axis_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG2_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt2_ioc_irq_set = '1')then
updt2_ioc <= '0';
elsif(writing_status_re_ch2 = '1')then
updt2_ioc <= s_axis2_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG2_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE2_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_interr_set = '1')then
dma2_interr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_interr <= s_axis2_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE2_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE2_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_slverr_set = '1')then
dma2_slverr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_slverr <= s_axis2_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE2_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE2_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_decerr_set = '1')then
dma2_decerr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_decerr <= s_axis2_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE2_DMADEC_ERROR;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_noqueue.vhd
-- Description: This entity provides the descriptor update for the No Queue mode
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_noqueue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33
-- 1 IOC bit + 32 Update Status Bits
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
updt2_active : in std_logic ; --
updt2_queue_empty : out std_logic ; --
updt2_ioc : out std_logic ; --
updt2_ioc_irq_set : in std_logic ; --
--
dma2_interr : out std_logic ; --
dma2_slverr : out std_logic ; --
dma2_decerr : out std_logic ; --
dma2_interr_set : in std_logic ; --
dma2_slverr_set : in std_logic ; --
dma2_decerr_set : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface In **-- --
--*********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
-- Update Pointer Stream --
s_axis2_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis2_updtptr_tvalid : in std_logic ; --
s_axis2_updtptr_tready : out std_logic ; --
s_axis2_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis2_updtsts_tvalid : in std_logic ; --
s_axis2_updtsts_tready : out std_logic ; --
s_axis2_updtsts_tlast : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface Out**-- --
--*********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_noqueue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_noqueue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Contstants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal writing_curdesc : std_logic := '0';
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
signal writing_status : std_logic := '0';
signal curdesc_tready : std_logic := '0';
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
signal writing_status_re_ch1 : std_logic := '0';
signal writing_status_re_ch2 : std_logic := '0';
signal updt_active_int : std_logic := '0';
signal s_axis_updtptr_tvalid_int : std_logic := '0';
signal s_axis_updtsts_tvalid_int : std_logic := '0';
signal s_axis_updtsts_tlast_int : std_logic := '0';
signal s_axis_updtptr_tdata_int : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axis_qual : std_logic := '0';
signal s_axis2_qual : std_logic := '0';
signal m_axis_updt_tdata_mm2s : std_logic_vector (31 downto 0); --
signal m_axis_updt_tlast_mm2s : std_logic ; --
signal m_axis_updt_tvalid_mm2s : std_logic ;
signal m_axis_updt_tdata_s2mm : std_logic_vector (31 downto 0); --
signal m_axis_updt_tlast_s2mm : std_logic ; --
signal m_axis_updt_tvalid_s2mm : std_logic ;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
m_axis_updt_tdata <= m_axis_updt_tdata_mm2s when updt_active = '1' else
m_axis_updt_tdata_s2mm;
m_axis_updt_tvalid <= m_axis_updt_tvalid_mm2s when updt_active = '1' else
m_axis_updt_tvalid_s2mm;
m_axis_updt_tlast <= m_axis_updt_tlast_mm2s when updt_active = '1' else
m_axis_updt_tlast_s2mm;
updt_active_int <= updt_active or updt2_active;
s_axis_updtptr_tvalid_int <= s_axis_updtptr_tvalid or s_axis2_updtptr_tvalid;
s_axis_updtsts_tvalid_int <= s_axis_updtsts_tvalid or s_axis2_updtsts_tvalid;
s_axis_updtsts_tlast_int <= s_axis_updtsts_tlast or s_axis2_updtsts_tlast;
s_axis_qual <= s_axis_updtsts_tvalid and s_axis_updtsts_tlast and updt_active;
s_axis2_qual <= s_axis2_updtsts_tvalid and s_axis2_updtsts_tlast and updt2_active;
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- the channel
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active or updt2_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re <= (updt_active or updt2_active) and not updt_active_d1;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active_int,
s_axis_updtptr_tvalid_int,
updt_active, updt2_active,
s_axis_qual, s_axis2_qual,
s_axis_updtptr_tvalid,
s_axis2_updtptr_tvalid,
s_axis_updtsts_tvalid_int,
m_axis_updt_tready)
begin
write_curdesc_lsb <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
writing_curdesc <= '0';
curdesc_tready <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if((s_axis_updtptr_tvalid = '1' and updt_active = '1') or
(s_axis2_updtptr_tvalid = '1' and updt2_active = '1')) then
writing_curdesc <= '1';
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor
when READ_CURDESC_LSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(s_axis_updtptr_tvalid_int = '1' and updt_active_int = '1')then
write_curdesc_lsb <= '1';
-- pntr_ns <= READ_CURDESC_MSB;
pntr_ns <= WRITE_STATUS;
else
-- coverage off
pntr_ns <= READ_CURDESC_LSB;
-- coverage on
end if;
-- coverage off
---------------------------------------------------------------
-- Get upper current descriptor
when READ_CURDESC_MSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
if(s_axis_updtptr_tvalid_int = '1')then
write_curdesc_msb <= '1';
pntr_ns <= WRITE_STATUS;
else
pntr_ns <= READ_CURDESC_MSB;
end if;
-- coverage on
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
writing_status <= '1'; --s_axis_updtsts_tvalid_int;
if((s_axis_qual = '1' and m_axis_updt_tready = '1') or
(s_axis2_qual = '1' and m_axis_updt_tready = '1')) then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
-- coverage off
when others =>
pntr_ns <= IDLE;
-- coverage on
end case;
end process CURDESC_PNTR_STATE;
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
-- Status stream signals
m_axis_updt_tdata_mm2s <= s_axis_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid_mm2s <= s_axis_updtsts_tvalid and writing_status;
m_axis_updt_tlast_mm2s <= s_axis_updtsts_tlast and writing_status;
s_axis_updtsts_tready <= m_axis_updt_tready and writing_status and updt_active;
-- Pointer stream signals
s_axis_updtptr_tready <= curdesc_tready and updt_active;
-- Indicate need for channel service for update state machine
updt_queue_empty <= not (s_axis_updtsts_tvalid); -- and writing_status);
m_axis_updt_tdata_s2mm <= s_axis2_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid_s2mm <= s_axis2_updtsts_tvalid and writing_status;
m_axis_updt_tlast_s2mm <= s_axis2_updtsts_tlast and writing_status;
s_axis2_updtsts_tready <= m_axis_updt_tready and writing_status and updt2_active;
-- Pointer stream signals
s_axis2_updtptr_tready <= curdesc_tready and updt2_active;
-- Indicate need for channel service for update state machine
updt2_queue_empty <= not (s_axis2_updtsts_tvalid); -- and writing_status);
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
s_axis_updtptr_tdata_int <= s_axis_updtptr_tdata when (updt_active = '1') else
s_axis2_updtptr_tdata;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1')then
updt_curdesc(31 downto 0) <= s_axis_updtptr_tdata_int(31 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(63 downto 32) <= (others => '0');
updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_lsb = '1')then
updt_curdesc(63 downto 32) <= s_axis_updtptr_tdata_int(C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_lsb = '1')then
-- elsif(write_curdesc_msb = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_NO_UPR_MSB_CURDESC;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
writing_status_re_ch1 <= writing_status_re and updt_active;
writing_status_re_ch2 <= writing_status_re and updt2_active;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re_ch1 = '1')then
updt_ioc <= s_axis_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_interr <= s_axis_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_slverr <= s_axis_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_decerr <= s_axis_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG2_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt2_ioc_irq_set = '1')then
updt2_ioc <= '0';
elsif(writing_status_re_ch2 = '1')then
updt2_ioc <= s_axis2_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG2_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE2_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_interr_set = '1')then
dma2_interr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_interr <= s_axis2_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE2_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE2_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_slverr_set = '1')then
dma2_slverr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_slverr <= s_axis2_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE2_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE2_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_decerr_set = '1')then
dma2_decerr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_decerr <= s_axis2_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE2_DMADEC_ERROR;
end implementation;
|
library ieee;
use ieee.std_logic_1164.all;
entity match01 is
port (a : in std_logic_vector (3 downto 0);
z : out std_logic);
end match01;
architecture behav of match01 is
begin
z <= a ?= "1--0";
end behav;
|
-- NEED RESULT: ARCH00281: Implicit signal GUARD used in a expression passed
-- NEED RESULT: ARCH00281: Implicit signal GUARD passed to procedure passed
-- NEED RESULT: ARCH00281: Implicit signal GUARD passed in to component passed
-- NEED RESULT: ARCH00281: Implicit signal GUARD used in a expression passed
-- NEED RESULT: ARCH00281: Implicit signal GUARD passed to procedure passed
-- NEED RESULT: ARCH00281: Implicit signal GUARD passed in to component passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00281
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.1 (3)
-- 9.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00281_1(ARCH00281_1)
-- E00000(ARCH00281)
-- ENT00281_Test_Bench(ARCH00281_Test_Bench)
--
-- REVISION HISTORY:
--
-- 21-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00281_1 is
port ( G : in boolean ;
P1 : in integer ;
P2 : in integer ) ;
end ;
architecture ARCH00281_1 of ENT00281_1 is
begin
process (G)
begin
test_report ( "ARCH00281" ,
"Implicit signal GUARD passed in to component" ,
(G = (P1 = P2)) ) ;
end process ;
end ;
use WORK.STANDARD_TYPES.all ;
architecture ARCH00281 of E00000 is
signal S1 : integer := 0 ;
signal S2 : integer := 1 ;
begin
B1 :
block ( S1 = S2 )
begin
process (GUARD)
begin
test_report ( "ARCH00281" ,
"Implicit signal GUARD used in a expression" ,
(GUARD = (S1 = S2)) ) ;
end process ;
end block B1 ;
B2 :
block ( S1 = S2 )
procedure Proc ( constant G : in boolean ;
constant P1, P2 : in integer ) is
begin
test_report ( "ARCH00281" ,
"Implicit signal GUARD passed to procedure" ,
(G = (P1 = P2)) ) ;
end Proc ;
begin
P1 :
process ( GUARD )
begin
Proc (GUARD, S1, S2) ;
end process P1 ;
end block B2 ;
B3 :
block ( S1 = S2 )
component Test_Comp
port ( G : in boolean ;
P1 : in integer ;
P2 : in integer ) ;
end component ;
for all : Test_Comp
use entity WORK.ENT00281_1 ( ARCH00281_1 );
begin
CIS1 : Test_Comp
port map ( GUARD, S1, S2 ) ;
end block B3 ;
S1 <= transport 1 after 10 ns ;
end ARCH00281 ;
entity ENT00281_Test_Bench is
end ENT00281_Test_Bench ;
architecture ARCH00281_Test_Bench of ENT00281_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00281 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00281_Test_Bench ;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SumadorCompleto is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
cout : out STD_LOGIC;
s : out STD_LOGIC);
end SumadorCompleto;
architecture Behavioral of SumadorCompleto is
signal s1 : std_logic := '0';
signal co1 : std_logic := '0';
signal co2 : std_logic := '0';
begin
s1 <= a xor b;
co1 <= a and b;
s <= s1 xor cin;
co2 <= s1 and cin;
cout <= co2 xor co1;
end Behavioral;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_a_e
--
-- Generated
-- by: wig
-- on: Thu Jan 19 08:01:06 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-conf-c.vhd,v 1.3 2006/01/19 08:50:40 wig Exp $
-- $Date: 2006/01/19 08:50:40 $
-- $Log: inst_a_e-rtl-conf-c.vhd,v $
-- Revision 1.3 2006/01/19 08:50:40 wig
-- Updated testcases, left 6 failing now (constant, bitsplice/X, ...)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.75 2006/01/18 16:59:29 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.43 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_a_e_rtl_conf / inst_a_e
--
configuration inst_a_e_rtl_conf of inst_a_e is
for rtl
-- Generated Configuration
for inst_aa_i : inst_xa_e
use configuration work.inst_xa_e_rtl_conf;
end for;
for inst_ab_i : inst_ab_e
use configuration work.inst_ab_e_rtl_conf;
end for;
end for;
end inst_a_e_rtl_conf;
--
-- End of Generated Configuration inst_a_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0;
USE axi_gpio_v2_0.axi_gpio;
ENTITY ZynqDesign_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ZynqDesign_axi_gpio_0_0;
ARCHITECTURE ZynqDesign_axi_gpio_0_0_arch OF ZynqDesign_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ZynqDesign_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 1,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
gpio_io_o => gpio_io_o,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END ZynqDesign_axi_gpio_0_0_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3168.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p17n01i03168ent IS
END c14s01b00x00p17n01i03168ent;
ARCHITECTURE c14s01b00x00p17n01i03168arch OF c14s01b00x00p17n01i03168ent IS
type color is (red, green, blue);
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( color'right = blue )
report "***PASSED TEST: c14s01b00x00p17n01i03168"
severity NOTE;
assert ( color'right = blue )
report "***FAILED TEST: c14s01b00x00p17n01i03168 - Predefined attribute RIGHT for enumeration type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p17n01i03168arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3168.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p17n01i03168ent IS
END c14s01b00x00p17n01i03168ent;
ARCHITECTURE c14s01b00x00p17n01i03168arch OF c14s01b00x00p17n01i03168ent IS
type color is (red, green, blue);
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( color'right = blue )
report "***PASSED TEST: c14s01b00x00p17n01i03168"
severity NOTE;
assert ( color'right = blue )
report "***FAILED TEST: c14s01b00x00p17n01i03168 - Predefined attribute RIGHT for enumeration type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p17n01i03168arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3168.vhd,v 1.2 2001-10-26 16:29:52 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c14s01b00x00p17n01i03168ent IS
END c14s01b00x00p17n01i03168ent;
ARCHITECTURE c14s01b00x00p17n01i03168arch OF c14s01b00x00p17n01i03168ent IS
type color is (red, green, blue);
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( color'right = blue )
report "***PASSED TEST: c14s01b00x00p17n01i03168"
severity NOTE;
assert ( color'right = blue )
report "***FAILED TEST: c14s01b00x00p17n01i03168 - Predefined attribute RIGHT for enumeration type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c14s01b00x00p17n01i03168arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity memory is
port ( Sysaddress : in std_logic_vector (15 downto 0);
Sysstrobe : in std_logic;
Sysrw : in std_logic;
Sysdata : inout std_logic_vector (7 downto 0));
end memory; |
library ieee;
use ieee.numeric_bit.all;
entity H24_Min60_Sec60_v2 is
port(Clk,Ldn,Reset:in bit;
Din :in unsigned(16 downto 1);
Qout:out unsigned(23 downto 0));
end entity H24_Min60_Sec60_v2;
architecture Behavior of H24_Min60_Sec60_v2 is
signal Q:unsigned(23 downto 0);
alias Second_low:unsigned(3 downto 0) is Q(3 downto 0);
alias Second_hig:unsigned(3 downto 0) is Q(7 downto 4);
alias Min_low: unsigned(3 downto 0) is Q(11 downto 8);
alias Min_hig: unsigned(3 downto 0) is Q(15 downto 12);
alias Hour_low: unsigned(3 downto 0) is Q(19 downto 16);
alias Hour_hig: unsigned(3 downto 0) is Q(23 downto 20);
--internal logic
-- signal second_count,min_count:integer range 0 to 59;--(63 downto 0);
-- signal hour_count: integer range 0 to 23;--(31 downto 0);
--signal carry_from_second,carry_from_min:bit;
constant CLs:unsigned(3 downto 0):="0000";
begin
Qout<=Q;
process(Clk,Ldn,Reset)
begin
if(Reset='0') then --min_count<=to_integer(Din(6 downto 1));hour_count<=to_integer(Din(13 downto 9));
Q<=(others=>'0');
elsif(Ldn='0' and Reset='1') then
Min_low <=Din(4 downto 1);
Min_hig <=Din(8 downto 5);
Hour_low<=Din(12 downto 9);
Hour_hig<=Din(16 downto 13);-- Q<=(others=>'0');
elsif(Clk'event and Clk='1') then
if(Second_low=9) then Second_low<=CLs;
if(Second_hig=5) then Second_hig<=CLs;
if(Min_low=9) then Min_low<=CLs;
if(Min_hig=5) then Min_hig<=CLs;
if(Hour_hig<2)then --09:59:59,19:59:59
if(Hour_low=9) then Hour_low<=CLs;Hour_hig<=Hour_hig+1;
else Hour_low<=Hour_low+1;
end if;
else --Hour_hig==2
if(Hour_low=3) then Hour_low<=CLs;Hour_hig<=CLs;
else Hour_low<=Hour_low+1;
end if;
end if;
else Min_hig<=Min_hig+1;
end if;
else Min_low<=Min_low+1;
end if;
else Second_hig<=Second_hig+1;
end if;
else Second_low<=Second_low+1;
end if;
-------------------------------------------old design,too much latchs...--------------------------
-- if(second_count=59) then second_count<=0;
-- if(min_count=59) then min_count<=0;
-- if(hour_count=23) then hour_count<=0;
-- else hour_count<=hour_count+1;
-- end if;
-- --carry_from_min<='1';
-- else min_count<=min_count+1;
-- end if;
-- --carry_from_second<='1';
-- else second_count<=second_count+1;
-- end if;
end if;
end process;
-- Second_low<=to_unsigned(second_count mod 10,4);
-- Second_hig<=to_unsigned(second_count/10,4);
-- Min_low<=to_unsigned(min_count mod 10,4);
-- Min_hig<=to_unsigned(min_count/10,4);
-- Hour_low<=to_unsigned(hour_count mod 10,4);
-- Hour_hig<=to_unsigned(hour_count/10,4);
end architecture Behavior; |
--Practica5 de Diseño Automatico de Sistemas
--Piano Electronico.
--Control de Teclado PS2.
--Desarrollada por Héctor Gutiérrez Palancarejo.
library ieee;
use ieee.std_logic_1164.all;
entity ps2_interface is
port(
clk : in std_logic;
rst : in std_logic;
ps2_clk : in std_logic;
ps2_data : in std_logic;
new_data_ack : in std_logic;
data : out std_logic_vector(7 downto 0);
new_data : out std_logic
);
end ps2_interface;
architecture rtl of ps2_interface is
component synchronizer is
port(
x : in std_logic;
rst : in std_logic;
clk : in std_logic;
xsync : out std_logic
);
end component;
component edgedetector is
port(
rst : in std_logic;
x : in std_logic;
clk : in std_logic;
x_falling_edge : out std_logic;
x_rising_edge : out std_logic
);
end component;
type states_ps2 is (esperando_datos,esperando_ack);
signal current_state,next_state : states_ps2;
signal shifter_out : std_logic_vector(10 downto 0);
signal shifter,clear_shifter,valid_data : std_logic;
signal clk_sync : std_logic;
signal ld_reg : std_logic;
signal reg_out : std_logic_vector(7 downto 0);
signal parity : std_logic;
--trimmed signals:
signal trim1 : std_logic;
begin
state : process(clk,rst)
begin
if(rst = '0') then
current_state <= esperando_datos;
elsif(rising_edge(clk)) then
current_state <= next_state;
end if;
end process;
gen_state : process(current_state,clear_shifter,new_data_ack,valid_data)
begin
next_state <= current_state;
case current_state is
when esperando_datos =>
if(valid_data = '1') then
next_state <= esperando_ack;
end if;
when esperando_ack =>
if(new_data_ack = '1') then
next_state <= esperando_datos;
end if;
end case;
end process;
gen_signals : process(current_state,clear_shifter,new_data_ack)
begin
case current_state is
when esperando_datos =>
new_data <= '0';
ld_reg <= '0';
if(clear_shifter = '1') then
ld_reg <= '1';
end if;
when esperando_ack =>
new_data <= '1';
ld_reg <= '0';
end case;
end process;
reg_shifter : process(clk,rst)
begin
if(rst = '0') then
shifter_out <= (others=>'1');
elsif(rising_edge(clk)) then
if(clear_shifter = '1') then
shifter_out <= (others=>'1');
end if;
if(shifter = '1') then
for i in 0 to 9 loop
shifter_out(i) <= shifter_out(i+1);
end loop;
shifter_out(10) <= ps2_data;
end if;
end if;
end process;
reg_data : process(clk,rst)
begin
if(rst = '0') then
reg_out <= (others=>'0');
elsif(rising_edge(clk)) then
if(ld_reg = '1') then
reg_out <= shifter_out(8 downto 1);
end if;
end if;
end process;
data <= reg_out;
parity <= (shifter_out(1) xor shifter_out(2) xor shifter_out(3) xor shifter_out(4)) xor (shifter_out(5) xor
shifter_out(6) xor shifter_out(7) xor shifter_out(8)) xor shifter_out(9);
clear_shifter <= not(shifter_out(0));
valid_data <= clear_shifter and parity;
u_sync_clk : synchronizer port map (x=>ps2_clk,rst=>rst,
clk=>clk,xsync=>clk_sync);
u_edge_clk : edgedetector port map (rst=>rst,x=>clk_sync,
clk=>clk,x_falling_edge=>shifter,x_rising_edge=>trim1);
end rtl; |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity input_split1 is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(4 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0);
wa0_en : in std_logic;
ra1_data : out std_logic_vector(31 downto 0);
ra1_addr : in std_logic_vector(4 downto 0);
ra2_data : out std_logic_vector(31 downto 0);
ra2_addr : in std_logic_vector(4 downto 0);
ra3_data : out std_logic_vector(31 downto 0);
ra3_addr : in std_logic_vector(4 downto 0);
clk : in std_logic
);
end input_split1;
architecture augh of input_split1 is
-- Embedded RAM
type ram_type is array (0 to 31) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
ra3_data <= ram( to_integer(ra3_addr) );
ra1_data <= ram( to_integer(ra1_addr) );
ra2_data <= ram( to_integer(ra2_addr) );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity input_split1 is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(4 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
ra0_addr : in std_logic_vector(4 downto 0);
wa0_en : in std_logic;
ra1_data : out std_logic_vector(31 downto 0);
ra1_addr : in std_logic_vector(4 downto 0);
ra2_data : out std_logic_vector(31 downto 0);
ra2_addr : in std_logic_vector(4 downto 0);
ra3_data : out std_logic_vector(31 downto 0);
ra3_addr : in std_logic_vector(4 downto 0);
clk : in std_logic
);
end input_split1;
architecture augh of input_split1 is
-- Embedded RAM
type ram_type is array (0 to 31) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
ra3_data <= ram( to_integer(ra3_addr) );
ra1_data <= ram( to_integer(ra1_addr) );
ra2_data <= ram( to_integer(ra2_addr) );
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bug is
generic(
ADDR_WIDTH : positive := 32;
BUS_WIDTH : positive := 4;
QUEUE_LENGTH : positive := 32
);
port(
clk : in std_ulogic;
reset_n : in std_ulogic
);
end bug;
architecture behav of bug is
signal write_start_addr : unsigned(ADDR_WIDTH-1 downto 0);
signal num_words : integer range 0 to QUEUE_LENGTH-1;
function non_4k_crossing_length(start_addr : unsigned(ADDR_WIDTH-1 downto 0);
max_length : integer range 0 to QUEUE_LENGTH-1) return integer is
constant words_per_page : integer := 4096/BUS_WIDTH;
constant diff : integer range 0 to words_per_page := (words_per_page-(to_integer(start_addr)/BUS_WIDTH mod words_per_page));
begin
return minimum(diff, max_length);
end function;
begin
process(clk, reset_n)
variable aligned_start_addr : unsigned(ADDR_WIDTH-1 downto 0);
variable write_length : integer range 0 to QUEUE_LENGTH-1;
begin
if reset_n = '0' then
elsif rising_edge(clk) then
aligned_start_addr := resize(write_start_addr/BUS_WIDTH*BUS_WIDTH, ADDR_WIDTH);
write_length := non_4k_crossing_length(aligned_start_addr, num_words);
end if;
end process;
end architecture;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity mixer is
port ( terminal inputs : electrical_vector(1 to 8);
terminal output : electrical );
end entity mixer;
----------------------------------------------------------------
architecture weighted of mixer is
quantity v_in across inputs;
quantity v_out across i_out through output;
constant gains : real_vector(1 to 8)
:= ( 0.01, 0.04, 0.15, 0.30, 0.03, 0.15, 0.04, 0.01 );
begin
apply_weights : procedural is
variable sum : real := 0.0;
begin
for index in v_in'range loop
sum := sum + v_in(index) * gains(index);
end loop;
v_out := sum;
end procedural apply_weights;
end architecture weighted;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity mixer is
port ( terminal inputs : electrical_vector(1 to 8);
terminal output : electrical );
end entity mixer;
----------------------------------------------------------------
architecture weighted of mixer is
quantity v_in across inputs;
quantity v_out across i_out through output;
constant gains : real_vector(1 to 8)
:= ( 0.01, 0.04, 0.15, 0.30, 0.03, 0.15, 0.04, 0.01 );
begin
apply_weights : procedural is
variable sum : real := 0.0;
begin
for index in v_in'range loop
sum := sum + v_in(index) * gains(index);
end loop;
v_out := sum;
end procedural apply_weights;
end architecture weighted;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity mixer is
port ( terminal inputs : electrical_vector(1 to 8);
terminal output : electrical );
end entity mixer;
----------------------------------------------------------------
architecture weighted of mixer is
quantity v_in across inputs;
quantity v_out across i_out through output;
constant gains : real_vector(1 to 8)
:= ( 0.01, 0.04, 0.15, 0.30, 0.03, 0.15, 0.04, 0.01 );
begin
apply_weights : procedural is
variable sum : real := 0.0;
begin
for index in v_in'range loop
sum := sum + v_in(index) * gains(index);
end loop;
v_out := sum;
end procedural apply_weights;
end architecture weighted;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: memory_virtex.vhd
-- Author: Aeroflex Gaisler AB
-- Description: Memory generators for Xilinx Virtex rams
------------------------------------------------------------------------------
-- parametrisable sync ram generator using UNISIM RAMB4 block rams
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB4_S1;
use unisim.RAMB4_S2;
use unisim.RAMB4_S4;
use unisim.RAMB4_S8;
use unisim.RAMB4_S16;
use unisim.RAMB4_S16_S16;
--pragma translate_on
library grlib;
use grlib.config_types.all;
use grlib.config.all;
library techmap;
use techmap.gencomp.all;
entity virtex_syncram is
generic ( abits : integer := 6; dbits : integer := 8);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of virtex_syncram is
component generic_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic);
end component;
component ramb4_s16 port (
do : out std_logic_vector (15 downto 0);
addr : in std_logic_vector (7 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (15 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S8
port (do : out std_logic_vector (7 downto 0);
addr : in std_logic_vector (8 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (7 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S4
port (do : out std_logic_vector (3 downto 0);
addr : in std_logic_vector (9 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (3 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S2
port (do : out std_logic_vector (1 downto 0);
addr : in std_logic_vector (10 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (1 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S1
port (do : out std_logic_vector (0 downto 0);
addr : in std_logic_vector (11 downto 0);
clk : in std_ulogic;
di : in std_logic_vector (0 downto 0);
en, rst, we : in std_ulogic);
end component;
component RAMB4_S16_S16
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
doa : out std_logic_vector (15 downto 0);
dob : out std_logic_vector (15 downto 0);
addra : in std_logic_vector (7 downto 0);
addrb : in std_logic_vector (7 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (15 downto 0);
dib : in std_logic_vector (15 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
signal gnd : std_ulogic;
signal do, di : std_logic_vector(dbits+32 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= '0';
dataout <= do(dbits-1 downto 0);
di(dbits-1 downto 0) <= datain; di(dbits+32 downto dbits) <= (others => '0');
xa(abits-1 downto 0) <= address; xa(19 downto abits) <= (others => '0');
ya(abits-1 downto 0) <= address; ya(19 downto abits) <= (others => '1');
a0 : if (abits <= 5) and (GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) = 0) generate
r0 : generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+32 downto dbits) <= (others => '0');
end generate;
a7 : if ((abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0) and
(abits <= 7) and (dbits <= 32)) generate
r0 : RAMB4_S16_S16
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map ( do(31 downto 16), do(15 downto 0),
xa(7 downto 0), ya(7 downto 0), clk, clk, di(31 downto 16),
di(15 downto 0), enable, enable, gnd, gnd, write, write);
do(dbits+32 downto 32) <= (others => '0');
end generate;
a8 : if (((abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0) and
(abits <= 7) and (dbits > 32)) or (abits = 8)) generate
x : for i in 0 to ((dbits-1)/16) generate
r : RAMB4_S16 port map ( do (((i+1)*16)-1 downto i*16), xa(7 downto 0),
clk, di (((i+1)*16)-1 downto i*16), enable, gnd, write );
end generate;
do(dbits+32 downto 16*(((dbits-1)/16)+1)) <= (others => '0');
end generate;
a9 : if abits = 9 generate
x : for i in 0 to ((dbits-1)/8) generate
r : RAMB4_S8 port map ( do (((i+1)*8)-1 downto i*8), xa(8 downto 0),
clk, di (((i+1)*8)-1 downto i*8), enable, gnd, write );
end generate;
do(dbits+32 downto 8*(((dbits-1)/8)+1)) <= (others => '0');
end generate;
a10 : if abits = 10 generate
x : for i in 0 to ((dbits-1)/4) generate
r : RAMB4_S4 port map ( do (((i+1)*4)-1 downto i*4), xa(9 downto 0),
clk, di (((i+1)*4)-1 downto i*4), enable, gnd, write );
end generate;
do(dbits+32 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/2) generate
r : RAMB4_S2 port map ( do (((i+1)*2)-1 downto i*2), xa(10 downto 0),
clk, di (((i+1)*2)-1 downto i*2), enable, gnd, write );
end generate;
do(dbits+32 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
end generate;
a12 : if abits = 12 generate
x : for i in 0 to (dbits-1) generate
r : RAMB4_S1 port map ( do (i downto i), xa(11 downto 0),
clk, di(i downto i), enable, gnd, write );
end generate;
do(dbits+32 downto dbits) <= (others => '0');
end generate;
a13 : if abits > 12 generate
x: generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+32 downto dbits) <= (others => '0');
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB4_S1_S1;
use unisim.RAMB4_S2_S2;
use unisim.RAMB4_S4_S4;
use unisim.RAMB4_S8_S8;
use unisim.RAMB4_S16_S16;
--pragma translate_on
entity virtex_syncram_dp is
generic (
abits : integer := 6; dbits : integer := 8
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of virtex_syncram_dp is
component RAMB4_S1_S1
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
doa : out std_logic_vector (0 downto 0);
dob : out std_logic_vector (0 downto 0);
addra : in std_logic_vector (11 downto 0);
addrb : in std_logic_vector (11 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (0 downto 0);
dib : in std_logic_vector (0 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S2_S2
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
doa : out std_logic_vector (1 downto 0);
dob : out std_logic_vector (1 downto 0);
addra : in std_logic_vector (10 downto 0);
addrb : in std_logic_vector (10 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (1 downto 0);
dib : in std_logic_vector (1 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S4_S4
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
doa : out std_logic_vector (3 downto 0);
dob : out std_logic_vector (3 downto 0);
addra : in std_logic_vector (9 downto 0);
addrb : in std_logic_vector (9 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (3 downto 0);
dib : in std_logic_vector (3 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S8_S8
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
doa : out std_logic_vector (7 downto 0);
dob : out std_logic_vector (7 downto 0);
addra : in std_logic_vector (8 downto 0);
addrb : in std_logic_vector (8 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (7 downto 0);
dib : in std_logic_vector (7 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
component RAMB4_S16_S16
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
doa : out std_logic_vector (15 downto 0);
dob : out std_logic_vector (15 downto 0);
addra : in std_logic_vector (7 downto 0);
addrb : in std_logic_vector (7 downto 0);
clka : in std_ulogic;
clkb : in std_ulogic;
dia : in std_logic_vector (15 downto 0);
dib : in std_logic_vector (15 downto 0);
ena : in std_ulogic;
enb : in std_ulogic;
rsta : in std_ulogic;
rstb : in std_ulogic;
wea : in std_ulogic;
web : in std_ulogic
);
end component;
signal gnd, vcc : std_ulogic;
signal do1, do2, di1, di2 : std_logic_vector(dbits+16 downto 0);
signal addr1, addr2 : std_logic_vector(19 downto 0);
begin
gnd <= '0'; vcc <= '1';
dataout1 <= do1(dbits-1 downto 0); dataout2 <= do2(dbits-1 downto 0);
di1(dbits-1 downto 0) <= datain1; di1(dbits+16 downto dbits) <= (others => '0');
di2(dbits-1 downto 0) <= datain2; di2(dbits+16 downto dbits) <= (others => '0');
addr1(abits-1 downto 0) <= address1; addr1(19 downto abits) <= (others => '0');
addr2(abits-1 downto 0) <= address2; addr2(19 downto abits) <= (others => '0');
a8 : if abits <= 8 generate
x : for i in 0 to ((dbits-1)/16) generate
r0 : RAMB4_S16_S16
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*16)-1 downto i*16), do2(((i+1)*16)-1 downto i*16),
addr1(7 downto 0), addr2(7 downto 0), clk1, clk2,
di1(((i+1)*16)-1 downto i*16), di2(((i+1)*16)-1 downto i*16),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
a9 : if abits = 9 generate
x : for i in 0 to ((dbits-1)/8) generate
r0 : RAMB4_S8_S8
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*8)-1 downto i*8), do2(((i+1)*8)-1 downto i*8),
addr1(8 downto 0), addr2(8 downto 0), clk1, clk2,
di1(((i+1)*8)-1 downto i*8), di2(((i+1)*8)-1 downto i*8),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
a10: if abits = 10 generate
x : for i in 0 to ((dbits-1)/4) generate
r0 : RAMB4_S4_S4
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*4)-1 downto i*4), do2(((i+1)*4)-1 downto i*4),
addr1(9 downto 0), addr2(9 downto 0), clk1, clk2,
di1(((i+1)*4)-1 downto i*4), di2(((i+1)*4)-1 downto i*4),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
a11: if abits = 11 generate
x : for i in 0 to ((dbits-1)/2) generate
r0 : RAMB4_S2_S2
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*2)-1 downto i*2), do2(((i+1)*2)-1 downto i*2),
addr1(10 downto 0), addr2(10 downto 0), clk1, clk2,
di1(((i+1)*2)-1 downto i*2), di2(((i+1)*2)-1 downto i*2),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
a12: if abits = 12 generate
x : for i in 0 to ((dbits-1)/1) generate
r0 : RAMB4_S1_S1
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*1)-1 downto i*1), do2(((i+1)*1)-1 downto i*1),
addr1(11 downto 0), addr2(11 downto 0), clk1, clk2,
di1(((i+1)*1)-1 downto i*1), di2(((i+1)*1)-1 downto i*1),
enable1, enable2, gnd, gnd, write1, write2);
end generate;
end generate;
-- pragma translate_off
a_to_high : if abits > 12 generate
x : process
begin
assert false
report "Address depth larger than 12 not supported for virtex_syncram_dp"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 08:38:15 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_zed_vga_0_0/system_zed_vga_0_0_stub.vhdl
-- Design : system_zed_vga_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_zed_vga_0_0 is
Port (
rgb565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
vga_r : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_g : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_b : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end system_zed_vga_0_0;
architecture stub of system_zed_vga_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "rgb565[15:0],vga_r[3:0],vga_g[3:0],vga_b[3:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "zed_vga,Vivado 2016.4";
begin
end;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY shifter_tb IS
END shifter_tb;
ARCHITECTURE behavior OF shifter_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT shifter
PORT(
clk : IN std_logic;
input : IN std_logic_vector(15 downto 0);
enable : IN std_logic;
active_output : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal input : std_logic_vector(15 downto 0) := (others => '0');
signal enable : std_logic := '0';
--Outputs
signal active_output : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: shifter PORT MAP (
clk => clk,
input => input,
enable => enable,
active_output => active_output
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
enable <= '0';
wait for clk_period;
enable <= '1';
input <= "0000000001111000";
-- wait for clk_period*3;
--
-- input <= "0000000000000111";
wait for clk_period;
input <= "0000000000000000";
wait;
end process;
END;
|
architecture ARCH of ENTITY1 is
begin
INST_INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
INST1 : INST1
generic map (
G_GEN_1 => 3,
G_GEN_2 => 4,
G_GEN_3 => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
|
-- Copyright 2017 Google Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity master_updateable_megarom is
Port (
D : inout std_logic_vector(7 downto 0);
bbc_A : in std_logic_vector(16 downto 0);
bbc_nCS : in std_logic;
flash_A : out std_logic_vector(18 downto 0);
--flash_nCE : out std_logic;
flash_nOE : out std_logic;
flash_nWE : out std_logic;
cpld_SCK : in std_logic;
cpld_MOSI : in std_logic;
cpld_SS : in std_logic;
cpld_MISO : out std_logic;
cpld_JP : in std_logic_vector(1 downto 0)
);
end master_updateable_megarom;
architecture Behavioural of master_updateable_megarom is
signal A : std_logic_vector(18 downto 0);
signal Dout : std_logic_vector(7 downto 0);
-- these two are set
signal allowing_bbc_access : std_logic := '1';
signal accessing_memory : std_logic := '0';
signal rnw : std_logic := '0';
-- SPI temp vars --
-- the value clocked out of D<7> on the falling SCK edge
signal last_d7 : std_logic := '0';
signal last_mosi : std_logic := '0';
-- flag to say if we're clocking through D/A/RnW or not (so we don't mess with them during the flash access period)
signal clocking_spi_data : std_logic := '0';
-- counts up to 50; need 6 bits
signal spi_bit_count : unsigned(5 downto 0) := "000000";
begin
-- We're either passing bbc_A through to flash_A, with D tristated, or we're
-- controlling both and ignoring bbc_A.
flash_A <= "00" & bbc_A when (allowing_bbc_access = '1') else A;
-- assert OE
flash_nOE <= '0' when (allowing_bbc_access = '1'
or (accessing_memory = '1' and rnw = '1')) else '1';
-- leave flash enabled all the time (TODO maybe just enable when /OE or /WE is active)
flash_nCE <= '0';
-- assert WE and D when the BBC is disabled and we're doing a memory write
flash_nWE <= '0' when (allowing_bbc_access = '0'
and (accessing_memory = '1' and rnw = '0')) else '1';
-- drive D when writing
D <= Dout when (allowing_bbc_access = '0'
and (accessing_memory = '1' and rnw = '0')) else "ZZZZZZZZ";
-- MISO always gets the last thing we clocked out of Dout
cpld_MISO <= last_d7;
process (cpld_SS, cpld_SCK)
begin
if cpld_SS = '1' then
clocking_spi_data <= '1';
accessing_memory <= '0';
spi_bit_count <= "000000";
elsif rising_edge(cpld_SCK) then
-- the master device should bring cpld_SS high between every transaction.
-- to block out the BBC and enable flash access: send 32 bits of zeros.
-- to reenable the BBC, send 32 bits of ones.
-- message format: 17 address bits, rnw, 8 data bits, 6 zeros (32 bits total) then 8 clocks to retrieve data
-- to get out of flash update mode, pass "000001" instead of the 6 zeros. (the last bit gets copied into allowing_bbc_access.)
-- we use the trailing zeros to perform the access to the flash chip.
-- the flash chip only needs a 40ns low pulse on /CE + /WE, and its read access time is 55-70ns;
-- there's another cycle time which is around 150ns also.
-- if we want the same timings as on the bbc (250ns), that means we're OK with an SPI clock up to maybe 24 MHz.
-- Example read, with RnW = 1:
-- SCK ___/^^^\___/^^^\___/^^^\___/^^^\___/^^^\___/^^^\___/^^^\___/^^^\___/^^^\___/^^^\___
-- MOSI X D1 X D0 X 0 X 0 X 0 X 0 X 0 X 0 X
-- MISO X D7 X D6 X ...
-- Because we have to clock D on falling edges, we're stuck doing that every time.
-- TODO switch it around so the count increments on the falling edge,
-- which lets us stop clocking as soon as we've got the last bit into D,
-- and start our memory access a half-cycle after bit 26 is in
if clocking_spi_data = '1' then
last_mosi <= cpld_MOSI;
A <= A(17 downto 0) & rnw;
rnw <= last_d7; -- change to use D(7) if we end up off by one here
end if;
-- stop clocking after the 26th bit, i.e. when count=25, and start again after bit 32
if spi_bit_count = 25 then
clocking_spi_data <= '0';
accessing_memory <= '1';
end if;
if spi_bit_count = 32 then
allowing_bbc_access <= cpld_MOSI;
accessing_memory <= '0';
clocking_spi_data <= '1';
end if;
spi_bit_count <= spi_bit_count + 1;
end if;
end process;
process (cpld_SS, cpld_SCK)
begin
if cpld_SS = '1' then
elsif falling_edge(cpld_SCK) then
if clocking_spi_data = '1' then
last_d7 <= Dout(7);
Dout <= D(6 downto 0) & last_mosi;
elsif accessing_memory = '1' and rnw = '1' then
Dout <= D;
end if;
end if;
end process;
end Behavioural;
|
-- niosii.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii is
port (
clk_clk : in std_logic := '0'; -- clk.clk
epcs_flash_dclk : out std_logic; -- epcs_flash.dclk
epcs_flash_sce : out std_logic; -- .sce
epcs_flash_sdo : out std_logic; -- .sdo
epcs_flash_data0 : in std_logic := '0'; -- .data0
ip_pwm_dir : out std_logic_vector(1 downto 0); -- ip_pwm.dir
ip_pwm_out : out std_logic_vector(1 downto 0); -- .out
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- pio_0_external_connection.export
reset_reset_n : in std_logic := '0'; -- reset.reset_n
uart_0_rxd : in std_logic := '0'; -- uart_0.rxd
uart_0_txd : out std_logic -- .txd
);
end entity niosii;
architecture rtl of niosii is
component niosii_altpll_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
read : in std_logic := 'X'; -- read
write : in std_logic := 'X'; -- write
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
c0 : out std_logic; -- clk
c1 : out std_logic; -- clk
c2 : out std_logic; -- clk
c3 : out std_logic; -- clk
areset : in std_logic := 'X'; -- export
locked : out std_logic; -- export
phasedone : out std_logic -- export
);
end component niosii_altpll_0;
component niosii_epcs_flash_controller_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
reset_req : in std_logic := 'X'; -- reset_req
address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
chipselect : in std_logic := 'X'; -- chipselect
dataavailable : out std_logic; -- dataavailable
endofpacket : out std_logic; -- endofpacket
read_n : in std_logic := 'X'; -- read_n
readdata : out std_logic_vector(31 downto 0); -- readdata
readyfordata : out std_logic; -- readyfordata
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
irq : out std_logic; -- irq
dclk : out std_logic; -- export
sce : out std_logic; -- export
sdo : out std_logic; -- export
data0 : in std_logic := 'X' -- export
);
end component niosii_epcs_flash_controller_0;
component ip_pwm_top is
port (
avs_s0_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
avs_s0_read : in std_logic := 'X'; -- read
avs_s0_readdata : out std_logic_vector(31 downto 0); -- readdata
avs_s0_write : in std_logic := 'X'; -- write
avs_s0_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avs_s0_waitrequest : out std_logic; -- waitrequest
clock_clk : in std_logic := 'X'; -- clk
reset_reset : in std_logic := 'X'; -- reset
pwm_dir : out std_logic_vector(1 downto 0); -- dir
pwm_out : out std_logic_vector(1 downto 0) -- out
);
end component ip_pwm_top;
component niosii_jtag_uart_0 is
port (
clk : in std_logic := 'X'; -- clk
rst_n : in std_logic := 'X'; -- reset_n
av_chipselect : in std_logic := 'X'; -- chipselect
av_address : in std_logic := 'X'; -- address
av_read_n : in std_logic := 'X'; -- read_n
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_write_n : in std_logic := 'X'; -- write_n
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_waitrequest : out std_logic; -- waitrequest
av_irq : out std_logic -- irq
);
end component niosii_jtag_uart_0;
component niosii_nios2_gen2_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
reset_req : in std_logic := 'X'; -- reset_req
d_address : out std_logic_vector(22 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(22 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
debug_reset_request : out std_logic; -- reset
debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
debug_mem_slave_read : in std_logic := 'X'; -- read
debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
debug_mem_slave_waitrequest : out std_logic; -- waitrequest
debug_mem_slave_write : in std_logic := 'X'; -- write
debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
dummy_ci_port : out std_logic -- readra
);
end component niosii_nios2_gen2_0;
component niosii_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(13 downto 0) := (others => 'X'); -- address
clken : in std_logic := 'X'; -- clken
chipselect : in std_logic := 'X'; -- chipselect
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X' -- reset_req
);
end component niosii_onchip_memory2_0;
component niosii_pio_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
out_port : out std_logic_vector(7 downto 0) -- export
);
end component niosii_pio_0;
component niosii_timer_ms is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
chipselect : in std_logic := 'X'; -- chipselect
write_n : in std_logic := 'X'; -- write_n
irq : out std_logic -- irq
);
end component niosii_timer_ms;
component niosii_timer_us is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
chipselect : in std_logic := 'X'; -- chipselect
write_n : in std_logic := 'X'; -- write_n
irq : out std_logic -- irq
);
end component niosii_timer_us;
component niosii_uart_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
begintransfer : in std_logic := 'X'; -- begintransfer
chipselect : in std_logic := 'X'; -- chipselect
read_n : in std_logic := 'X'; -- read_n
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
readdata : out std_logic_vector(15 downto 0); -- readdata
dataavailable : out std_logic; -- dataavailable
readyfordata : out std_logic; -- readyfordata
rxd : in std_logic := 'X'; -- export
txd : out std_logic; -- export
irq : out std_logic -- irq
);
end component niosii_uart_0;
component niosii_mm_interconnect_0 is
port (
altpll_0_c0_clk : in std_logic := 'X'; -- clk
altpll_0_c1_clk : in std_logic := 'X'; -- clk
altpll_0_c2_clk : in std_logic := 'X'; -- clk
altpll_0_c3_clk : in std_logic := 'X'; -- clk
clk_0_clk_clk : in std_logic := 'X'; -- clk
altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
epcs_flash_controller_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
ip_pwm_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
nios2_gen2_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
timer_us_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
nios2_gen2_0_data_master_address : in std_logic_vector(22 downto 0) := (others => 'X'); -- address
nios2_gen2_0_data_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
nios2_gen2_0_data_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata
nios2_gen2_0_data_master_write : in std_logic := 'X'; -- write
nios2_gen2_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess
nios2_gen2_0_instruction_master_address : in std_logic_vector(22 downto 0) := (others => 'X'); -- address
nios2_gen2_0_instruction_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_instruction_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata
altpll_0_pll_slave_address : out std_logic_vector(1 downto 0); -- address
altpll_0_pll_slave_write : out std_logic; -- write
altpll_0_pll_slave_read : out std_logic; -- read
altpll_0_pll_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
altpll_0_pll_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
epcs_flash_controller_0_epcs_control_port_address : out std_logic_vector(8 downto 0); -- address
epcs_flash_controller_0_epcs_control_port_write : out std_logic; -- write
epcs_flash_controller_0_epcs_control_port_read : out std_logic; -- read
epcs_flash_controller_0_epcs_control_port_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
epcs_flash_controller_0_epcs_control_port_writedata : out std_logic_vector(31 downto 0); -- writedata
epcs_flash_controller_0_epcs_control_port_chipselect : out std_logic; -- chipselect
ip_pwm_0_avs_s0_address : out std_logic_vector(7 downto 0); -- address
ip_pwm_0_avs_s0_write : out std_logic; -- write
ip_pwm_0_avs_s0_read : out std_logic; -- read
ip_pwm_0_avs_s0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
ip_pwm_0_avs_s0_writedata : out std_logic_vector(31 downto 0); -- writedata
ip_pwm_0_avs_s0_waitrequest : in std_logic := 'X'; -- waitrequest
jtag_uart_0_avalon_jtag_slave_address : out std_logic_vector(0 downto 0); -- address
jtag_uart_0_avalon_jtag_slave_write : out std_logic; -- write
jtag_uart_0_avalon_jtag_slave_read : out std_logic; -- read
jtag_uart_0_avalon_jtag_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
jtag_uart_0_avalon_jtag_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
jtag_uart_0_avalon_jtag_slave_waitrequest : in std_logic := 'X'; -- waitrequest
jtag_uart_0_avalon_jtag_slave_chipselect : out std_logic; -- chipselect
nios2_gen2_0_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address
nios2_gen2_0_debug_mem_slave_write : out std_logic; -- write
nios2_gen2_0_debug_mem_slave_read : out std_logic; -- read
nios2_gen2_0_debug_mem_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
nios2_gen2_0_debug_mem_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
nios2_gen2_0_debug_mem_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable
nios2_gen2_0_debug_mem_slave_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess : out std_logic; -- debugaccess
onchip_memory2_0_s1_address : out std_logic_vector(13 downto 0); -- address
onchip_memory2_0_s1_write : out std_logic; -- write
onchip_memory2_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
onchip_memory2_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
onchip_memory2_0_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable
onchip_memory2_0_s1_chipselect : out std_logic; -- chipselect
onchip_memory2_0_s1_clken : out std_logic; -- clken
pio_0_s1_address : out std_logic_vector(1 downto 0); -- address
pio_0_s1_write : out std_logic; -- write
pio_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
pio_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
pio_0_s1_chipselect : out std_logic; -- chipselect
timer_ms_s1_address : out std_logic_vector(2 downto 0); -- address
timer_ms_s1_write : out std_logic; -- write
timer_ms_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
timer_ms_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
timer_ms_s1_chipselect : out std_logic; -- chipselect
timer_us_s1_address : out std_logic_vector(2 downto 0); -- address
timer_us_s1_write : out std_logic; -- write
timer_us_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
timer_us_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
timer_us_s1_chipselect : out std_logic; -- chipselect
uart_0_s1_address : out std_logic_vector(2 downto 0); -- address
uart_0_s1_write : out std_logic; -- write
uart_0_s1_read : out std_logic; -- read
uart_0_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
uart_0_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
uart_0_s1_begintransfer : out std_logic; -- begintransfer
uart_0_s1_chipselect : out std_logic -- chipselect
);
end component niosii_mm_interconnect_0;
component niosii_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
receiver0_irq : in std_logic := 'X'; -- irq
receiver1_irq : in std_logic := 'X'; -- irq
receiver2_irq : in std_logic := 'X'; -- irq
receiver3_irq : in std_logic := 'X'; -- irq
receiver4_irq : in std_logic := 'X'; -- irq
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component niosii_irq_mapper;
component altera_irq_clock_crosser is
generic (
IRQ_WIDTH : integer := 1
);
port (
receiver_clk : in std_logic := 'X'; -- clk
sender_clk : in std_logic := 'X'; -- clk
receiver_reset : in std_logic := 'X'; -- reset
sender_reset : in std_logic := 'X'; -- reset
receiver_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
sender_irq : out std_logic_vector(0 downto 0) -- irq
);
end component altera_irq_clock_crosser;
component niosii_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component niosii_rst_controller;
component niosii_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component niosii_rst_controller_001;
signal altpll_0_c0_clk : std_logic; -- altpll_0:c0 -> [irq_mapper:clk, irq_synchronizer:sender_clk, irq_synchronizer_001:sender_clk, irq_synchronizer_002:sender_clk, irq_synchronizer_003:sender_clk, jtag_uart_0:clk, mm_interconnect_0:altpll_0_c0_clk, nios2_gen2_0:clk, onchip_memory2_0:clk, rst_controller_003:clk]
signal altpll_0_c1_clk : std_logic; -- altpll_0:c1 -> [ip_pwm_0:clock_clk, irq_synchronizer:receiver_clk, mm_interconnect_0:altpll_0_c1_clk, pio_0:clk, rst_controller_002:clk, uart_0:clk]
signal altpll_0_c2_clk : std_logic; -- altpll_0:c2 -> [irq_synchronizer_001:receiver_clk, irq_synchronizer_002:receiver_clk, mm_interconnect_0:altpll_0_c2_clk, rst_controller_004:clk, timer_ms:clk, timer_us:clk]
signal altpll_0_c3_clk : std_logic; -- altpll_0:c3 -> [epcs_flash_controller_0:clk, irq_synchronizer_003:receiver_clk, mm_interconnect_0:altpll_0_c3_clk, rst_controller_001:clk]
signal nios2_gen2_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
signal nios2_gen2_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
signal nios2_gen2_0_data_master_debugaccess : std_logic; -- nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
signal nios2_gen2_0_data_master_address : std_logic_vector(22 downto 0); -- nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
signal nios2_gen2_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
signal nios2_gen2_0_data_master_read : std_logic; -- nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
signal nios2_gen2_0_data_master_write : std_logic; -- nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
signal nios2_gen2_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
signal nios2_gen2_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
signal nios2_gen2_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
signal nios2_gen2_0_instruction_master_address : std_logic_vector(22 downto 0); -- nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
signal nios2_gen2_0_instruction_master_read : std_logic; -- nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_chipselect -> jtag_uart_0:av_chipselect
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata : std_logic_vector(31 downto 0); -- jtag_uart_0:av_readdata -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_readdata
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest : std_logic; -- jtag_uart_0:av_waitrequest -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_waitrequest
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address : std_logic_vector(0 downto 0); -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_address -> jtag_uart_0:av_address
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_read -> mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read:in
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_write -> mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write:in
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_writedata -> jtag_uart_0:av_writedata
signal mm_interconnect_0_ip_pwm_0_avs_s0_readdata : std_logic_vector(31 downto 0); -- ip_pwm_0:avs_s0_readdata -> mm_interconnect_0:ip_pwm_0_avs_s0_readdata
signal mm_interconnect_0_ip_pwm_0_avs_s0_waitrequest : std_logic; -- ip_pwm_0:avs_s0_waitrequest -> mm_interconnect_0:ip_pwm_0_avs_s0_waitrequest
signal mm_interconnect_0_ip_pwm_0_avs_s0_address : std_logic_vector(7 downto 0); -- mm_interconnect_0:ip_pwm_0_avs_s0_address -> ip_pwm_0:avs_s0_address
signal mm_interconnect_0_ip_pwm_0_avs_s0_read : std_logic; -- mm_interconnect_0:ip_pwm_0_avs_s0_read -> ip_pwm_0:avs_s0_read
signal mm_interconnect_0_ip_pwm_0_avs_s0_write : std_logic; -- mm_interconnect_0:ip_pwm_0_avs_s0_write -> ip_pwm_0:avs_s0_write
signal mm_interconnect_0_ip_pwm_0_avs_s0_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:ip_pwm_0_avs_s0_writedata -> ip_pwm_0:avs_s0_writedata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest : std_logic; -- nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
signal mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_chipselect : std_logic; -- mm_interconnect_0:epcs_flash_controller_0_epcs_control_port_chipselect -> epcs_flash_controller_0:chipselect
signal mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_readdata : std_logic_vector(31 downto 0); -- epcs_flash_controller_0:readdata -> mm_interconnect_0:epcs_flash_controller_0_epcs_control_port_readdata
signal mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:epcs_flash_controller_0_epcs_control_port_address -> epcs_flash_controller_0:address
signal mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_read : std_logic; -- mm_interconnect_0:epcs_flash_controller_0_epcs_control_port_read -> mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_read:in
signal mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_write : std_logic; -- mm_interconnect_0:epcs_flash_controller_0_epcs_control_port_write -> mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_write:in
signal mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:epcs_flash_controller_0_epcs_control_port_writedata -> epcs_flash_controller_0:writedata
signal mm_interconnect_0_altpll_0_pll_slave_readdata : std_logic_vector(31 downto 0); -- altpll_0:readdata -> mm_interconnect_0:altpll_0_pll_slave_readdata
signal mm_interconnect_0_altpll_0_pll_slave_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_address -> altpll_0:address
signal mm_interconnect_0_altpll_0_pll_slave_read : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_read -> altpll_0:read
signal mm_interconnect_0_altpll_0_pll_slave_write : std_logic; -- mm_interconnect_0:altpll_0_pll_slave_write -> altpll_0:write
signal mm_interconnect_0_altpll_0_pll_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:altpll_0_pll_slave_writedata -> altpll_0:writedata
signal mm_interconnect_0_onchip_memory2_0_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
signal mm_interconnect_0_onchip_memory2_0_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
signal mm_interconnect_0_onchip_memory2_0_s1_address : std_logic_vector(13 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
signal mm_interconnect_0_onchip_memory2_0_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
signal mm_interconnect_0_onchip_memory2_0_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
signal mm_interconnect_0_onchip_memory2_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
signal mm_interconnect_0_onchip_memory2_0_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
signal mm_interconnect_0_pio_0_s1_chipselect : std_logic; -- mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
signal mm_interconnect_0_pio_0_s1_readdata : std_logic_vector(31 downto 0); -- pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
signal mm_interconnect_0_pio_0_s1_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:pio_0_s1_address -> pio_0:address
signal mm_interconnect_0_pio_0_s1_write : std_logic; -- mm_interconnect_0:pio_0_s1_write -> mm_interconnect_0_pio_0_s1_write:in
signal mm_interconnect_0_pio_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
signal mm_interconnect_0_uart_0_s1_chipselect : std_logic; -- mm_interconnect_0:uart_0_s1_chipselect -> uart_0:chipselect
signal mm_interconnect_0_uart_0_s1_readdata : std_logic_vector(15 downto 0); -- uart_0:readdata -> mm_interconnect_0:uart_0_s1_readdata
signal mm_interconnect_0_uart_0_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:uart_0_s1_address -> uart_0:address
signal mm_interconnect_0_uart_0_s1_read : std_logic; -- mm_interconnect_0:uart_0_s1_read -> mm_interconnect_0_uart_0_s1_read:in
signal mm_interconnect_0_uart_0_s1_begintransfer : std_logic; -- mm_interconnect_0:uart_0_s1_begintransfer -> uart_0:begintransfer
signal mm_interconnect_0_uart_0_s1_write : std_logic; -- mm_interconnect_0:uart_0_s1_write -> mm_interconnect_0_uart_0_s1_write:in
signal mm_interconnect_0_uart_0_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:uart_0_s1_writedata -> uart_0:writedata
signal mm_interconnect_0_timer_us_s1_chipselect : std_logic; -- mm_interconnect_0:timer_us_s1_chipselect -> timer_us:chipselect
signal mm_interconnect_0_timer_us_s1_readdata : std_logic_vector(15 downto 0); -- timer_us:readdata -> mm_interconnect_0:timer_us_s1_readdata
signal mm_interconnect_0_timer_us_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:timer_us_s1_address -> timer_us:address
signal mm_interconnect_0_timer_us_s1_write : std_logic; -- mm_interconnect_0:timer_us_s1_write -> mm_interconnect_0_timer_us_s1_write:in
signal mm_interconnect_0_timer_us_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:timer_us_s1_writedata -> timer_us:writedata
signal mm_interconnect_0_timer_ms_s1_chipselect : std_logic; -- mm_interconnect_0:timer_ms_s1_chipselect -> timer_ms:chipselect
signal mm_interconnect_0_timer_ms_s1_readdata : std_logic_vector(15 downto 0); -- timer_ms:readdata -> mm_interconnect_0:timer_ms_s1_readdata
signal mm_interconnect_0_timer_ms_s1_address : std_logic_vector(2 downto 0); -- mm_interconnect_0:timer_ms_s1_address -> timer_ms:address
signal mm_interconnect_0_timer_ms_s1_write : std_logic; -- mm_interconnect_0:timer_ms_s1_write -> mm_interconnect_0_timer_ms_s1_write:in
signal mm_interconnect_0_timer_ms_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:timer_ms_s1_writedata -> timer_ms:writedata
signal irq_mapper_receiver0_irq : std_logic; -- jtag_uart_0:av_irq -> irq_mapper:receiver0_irq
signal nios2_gen2_0_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_gen2_0:irq
signal irq_mapper_receiver1_irq : std_logic; -- irq_synchronizer:sender_irq -> irq_mapper:receiver1_irq
signal irq_synchronizer_receiver_irq : std_logic_vector(0 downto 0); -- uart_0:irq -> irq_synchronizer:receiver_irq
signal irq_mapper_receiver2_irq : std_logic; -- irq_synchronizer_001:sender_irq -> irq_mapper:receiver2_irq
signal irq_synchronizer_001_receiver_irq : std_logic_vector(0 downto 0); -- timer_us:irq -> irq_synchronizer_001:receiver_irq
signal irq_mapper_receiver3_irq : std_logic; -- irq_synchronizer_002:sender_irq -> irq_mapper:receiver3_irq
signal irq_synchronizer_002_receiver_irq : std_logic_vector(0 downto 0); -- timer_ms:irq -> irq_synchronizer_002:receiver_irq
signal irq_mapper_receiver4_irq : std_logic; -- irq_synchronizer_003:sender_irq -> irq_mapper:receiver4_irq
signal irq_synchronizer_003_receiver_irq : std_logic_vector(0 downto 0); -- epcs_flash_controller_0:irq -> irq_synchronizer_003:receiver_irq
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [altpll_0:reset, mm_interconnect_0:altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset]
signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [irq_synchronizer_003:receiver_reset, mm_interconnect_0:epcs_flash_controller_0_reset_reset_bridge_in_reset_reset, rst_controller_001_reset_out_reset:in]
signal rst_controller_001_reset_out_reset_req : std_logic; -- rst_controller_001:reset_req -> [epcs_flash_controller_0:reset_req, rst_translator:reset_req_in]
signal rst_controller_002_reset_out_reset : std_logic; -- rst_controller_002:reset_out -> [ip_pwm_0:reset_reset, irq_synchronizer:receiver_reset, mm_interconnect_0:ip_pwm_0_reset_reset_bridge_in_reset_reset, rst_controller_002_reset_out_reset:in]
signal rst_controller_003_reset_out_reset : std_logic; -- rst_controller_003:reset_out -> [irq_mapper:reset, irq_synchronizer:sender_reset, irq_synchronizer_001:sender_reset, irq_synchronizer_002:sender_reset, irq_synchronizer_003:sender_reset, mm_interconnect_0:nios2_gen2_0_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, rst_controller_003_reset_out_reset:in, rst_translator_001:in_reset]
signal rst_controller_003_reset_out_reset_req : std_logic; -- rst_controller_003:reset_req -> [nios2_gen2_0:reset_req, onchip_memory2_0:reset_req, rst_translator_001:reset_req_in]
signal rst_controller_004_reset_out_reset : std_logic; -- rst_controller_004:reset_out -> [irq_synchronizer_001:receiver_reset, irq_synchronizer_002:receiver_reset, mm_interconnect_0:timer_us_reset_reset_bridge_in_reset_reset, rst_controller_004_reset_out_reset:in]
signal reset_reset_n_ports_inv : std_logic; -- reset_reset_n:inv -> [rst_controller:reset_in0, rst_controller_001:reset_in0, rst_controller_002:reset_in0, rst_controller_003:reset_in0, rst_controller_004:reset_in0]
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv : std_logic; -- mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read:inv -> jtag_uart_0:av_read_n
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv : std_logic; -- mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write:inv -> jtag_uart_0:av_write_n
signal mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_read_ports_inv : std_logic; -- mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_read:inv -> epcs_flash_controller_0:read_n
signal mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_write_ports_inv : std_logic; -- mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_write:inv -> epcs_flash_controller_0:write_n
signal mm_interconnect_0_pio_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_pio_0_s1_write:inv -> pio_0:write_n
signal mm_interconnect_0_uart_0_s1_read_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_read:inv -> uart_0:read_n
signal mm_interconnect_0_uart_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_uart_0_s1_write:inv -> uart_0:write_n
signal mm_interconnect_0_timer_us_s1_write_ports_inv : std_logic; -- mm_interconnect_0_timer_us_s1_write:inv -> timer_us:write_n
signal mm_interconnect_0_timer_ms_s1_write_ports_inv : std_logic; -- mm_interconnect_0_timer_ms_s1_write:inv -> timer_ms:write_n
signal rst_controller_001_reset_out_reset_ports_inv : std_logic; -- rst_controller_001_reset_out_reset:inv -> epcs_flash_controller_0:reset_n
signal rst_controller_002_reset_out_reset_ports_inv : std_logic; -- rst_controller_002_reset_out_reset:inv -> [pio_0:reset_n, uart_0:reset_n]
signal rst_controller_003_reset_out_reset_ports_inv : std_logic; -- rst_controller_003_reset_out_reset:inv -> [jtag_uart_0:rst_n, nios2_gen2_0:reset_n]
signal rst_controller_004_reset_out_reset_ports_inv : std_logic; -- rst_controller_004_reset_out_reset:inv -> [timer_ms:reset_n, timer_us:reset_n]
begin
altpll_0 : component niosii_altpll_0
port map (
clk => clk_clk, -- inclk_interface.clk
reset => rst_controller_reset_out_reset, -- inclk_interface_reset.reset
read => mm_interconnect_0_altpll_0_pll_slave_read, -- pll_slave.read
write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write
address => mm_interconnect_0_altpll_0_pll_slave_address, -- .address
readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata
writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata
c0 => altpll_0_c0_clk, -- c0.clk
c1 => altpll_0_c1_clk, -- c1.clk
c2 => altpll_0_c2_clk, -- c2.clk
c3 => altpll_0_c3_clk, -- c3.clk
areset => open, -- areset_conduit.export
locked => open, -- locked_conduit.export
phasedone => open -- phasedone_conduit.export
);
epcs_flash_controller_0 : component niosii_epcs_flash_controller_0
port map (
clk => altpll_0_c3_clk, -- clk.clk
reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req
address => mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_address, -- epcs_control_port.address
chipselect => mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_chipselect, -- .chipselect
dataavailable => open, -- .dataavailable
endofpacket => open, -- .endofpacket
read_n => mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_read_ports_inv, -- .read_n
readdata => mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_readdata, -- .readdata
readyfordata => open, -- .readyfordata
write_n => mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_writedata, -- .writedata
irq => irq_synchronizer_003_receiver_irq(0), -- irq.irq
dclk => epcs_flash_dclk, -- external.export
sce => epcs_flash_sce, -- .export
sdo => epcs_flash_sdo, -- .export
data0 => epcs_flash_data0 -- .export
);
ip_pwm_0 : component ip_pwm_top
port map (
avs_s0_address => mm_interconnect_0_ip_pwm_0_avs_s0_address, -- avs_s0.address
avs_s0_read => mm_interconnect_0_ip_pwm_0_avs_s0_read, -- .read
avs_s0_readdata => mm_interconnect_0_ip_pwm_0_avs_s0_readdata, -- .readdata
avs_s0_write => mm_interconnect_0_ip_pwm_0_avs_s0_write, -- .write
avs_s0_writedata => mm_interconnect_0_ip_pwm_0_avs_s0_writedata, -- .writedata
avs_s0_waitrequest => mm_interconnect_0_ip_pwm_0_avs_s0_waitrequest, -- .waitrequest
clock_clk => altpll_0_c1_clk, -- clock.clk
reset_reset => rst_controller_002_reset_out_reset, -- reset.reset
pwm_dir => ip_pwm_dir, -- pwm.dir
pwm_out => ip_pwm_out -- .out
);
jtag_uart_0 : component niosii_jtag_uart_0
port map (
clk => altpll_0_c0_clk, -- clk.clk
rst_n => rst_controller_003_reset_out_reset_ports_inv, -- reset.reset_n
av_chipselect => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect, -- avalon_jtag_slave.chipselect
av_address => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address(0), -- .address
av_read_n => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv, -- .read_n
av_readdata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata, -- .readdata
av_write_n => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv, -- .write_n
av_writedata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata, -- .writedata
av_waitrequest => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest, -- .waitrequest
av_irq => irq_mapper_receiver0_irq -- irq.irq
);
nios2_gen2_0 : component niosii_nios2_gen2_0
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset_n => rst_controller_003_reset_out_reset_ports_inv, -- reset.reset_n
reset_req => rst_controller_003_reset_out_reset_req, -- .reset_req
d_address => nios2_gen2_0_data_master_address, -- data_master.address
d_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
d_read => nios2_gen2_0_data_master_read, -- .read
d_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
d_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
d_write => nios2_gen2_0_data_master_write, -- .write
d_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
debug_mem_slave_debugaccess_to_roms => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
i_address => nios2_gen2_0_instruction_master_address, -- instruction_master.address
i_read => nios2_gen2_0_instruction_master_read, -- .read
i_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
i_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
irq => nios2_gen2_0_irq_irq, -- irq.irq
debug_reset_request => open, -- debug_reset_request.reset
debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- debug_mem_slave.address
debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
dummy_ci_port => open -- custom_instruction_master.readra
);
onchip_memory2_0 : component niosii_onchip_memory2_0
port map (
clk => altpll_0_c0_clk, -- clk1.clk
address => mm_interconnect_0_onchip_memory2_0_s1_address, -- s1.address
clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
reset => rst_controller_003_reset_out_reset, -- reset1.reset
reset_req => rst_controller_003_reset_out_reset_req -- .reset_req
);
pio_0 : component niosii_pio_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_002_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_pio_0_s1_address, -- s1.address
write_n => mm_interconnect_0_pio_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
out_port => pio_0_external_connection_export -- external_connection.export
);
timer_ms : component niosii_timer_ms
port map (
clk => altpll_0_c2_clk, -- clk.clk
reset_n => rst_controller_004_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_timer_ms_s1_address, -- s1.address
writedata => mm_interconnect_0_timer_ms_s1_writedata, -- .writedata
readdata => mm_interconnect_0_timer_ms_s1_readdata, -- .readdata
chipselect => mm_interconnect_0_timer_ms_s1_chipselect, -- .chipselect
write_n => mm_interconnect_0_timer_ms_s1_write_ports_inv, -- .write_n
irq => irq_synchronizer_002_receiver_irq(0) -- irq.irq
);
timer_us : component niosii_timer_us
port map (
clk => altpll_0_c2_clk, -- clk.clk
reset_n => rst_controller_004_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_timer_us_s1_address, -- s1.address
writedata => mm_interconnect_0_timer_us_s1_writedata, -- .writedata
readdata => mm_interconnect_0_timer_us_s1_readdata, -- .readdata
chipselect => mm_interconnect_0_timer_us_s1_chipselect, -- .chipselect
write_n => mm_interconnect_0_timer_us_s1_write_ports_inv, -- .write_n
irq => irq_synchronizer_001_receiver_irq(0) -- irq.irq
);
uart_0 : component niosii_uart_0
port map (
clk => altpll_0_c1_clk, -- clk.clk
reset_n => rst_controller_002_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_uart_0_s1_address, -- s1.address
begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer
chipselect => mm_interconnect_0_uart_0_s1_chipselect, -- .chipselect
read_n => mm_interconnect_0_uart_0_s1_read_ports_inv, -- .read_n
write_n => mm_interconnect_0_uart_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata
readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata
dataavailable => open, -- .dataavailable
readyfordata => open, -- .readyfordata
rxd => uart_0_rxd, -- external_connection.export
txd => uart_0_txd, -- .export
irq => irq_synchronizer_receiver_irq(0) -- irq.irq
);
mm_interconnect_0 : component niosii_mm_interconnect_0
port map (
altpll_0_c0_clk => altpll_0_c0_clk, -- altpll_0_c0.clk
altpll_0_c1_clk => altpll_0_c1_clk, -- altpll_0_c1.clk
altpll_0_c2_clk => altpll_0_c2_clk, -- altpll_0_c2.clk
altpll_0_c3_clk => altpll_0_c3_clk, -- altpll_0_c3.clk
clk_0_clk_clk => clk_clk, -- clk_0_clk.clk
altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- altpll_0_inclk_interface_reset_reset_bridge_in_reset.reset
epcs_flash_controller_0_reset_reset_bridge_in_reset_reset => rst_controller_001_reset_out_reset, -- epcs_flash_controller_0_reset_reset_bridge_in_reset.reset
ip_pwm_0_reset_reset_bridge_in_reset_reset => rst_controller_002_reset_out_reset, -- ip_pwm_0_reset_reset_bridge_in_reset.reset
nios2_gen2_0_reset_reset_bridge_in_reset_reset => rst_controller_003_reset_out_reset, -- nios2_gen2_0_reset_reset_bridge_in_reset.reset
timer_us_reset_reset_bridge_in_reset_reset => rst_controller_004_reset_out_reset, -- timer_us_reset_reset_bridge_in_reset.reset
nios2_gen2_0_data_master_address => nios2_gen2_0_data_master_address, -- nios2_gen2_0_data_master.address
nios2_gen2_0_data_master_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
nios2_gen2_0_data_master_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
nios2_gen2_0_data_master_read => nios2_gen2_0_data_master_read, -- .read
nios2_gen2_0_data_master_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
nios2_gen2_0_data_master_write => nios2_gen2_0_data_master_write, -- .write
nios2_gen2_0_data_master_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
nios2_gen2_0_data_master_debugaccess => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
nios2_gen2_0_instruction_master_address => nios2_gen2_0_instruction_master_address, -- nios2_gen2_0_instruction_master.address
nios2_gen2_0_instruction_master_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
nios2_gen2_0_instruction_master_read => nios2_gen2_0_instruction_master_read, -- .read
nios2_gen2_0_instruction_master_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
altpll_0_pll_slave_address => mm_interconnect_0_altpll_0_pll_slave_address, -- altpll_0_pll_slave.address
altpll_0_pll_slave_write => mm_interconnect_0_altpll_0_pll_slave_write, -- .write
altpll_0_pll_slave_read => mm_interconnect_0_altpll_0_pll_slave_read, -- .read
altpll_0_pll_slave_readdata => mm_interconnect_0_altpll_0_pll_slave_readdata, -- .readdata
altpll_0_pll_slave_writedata => mm_interconnect_0_altpll_0_pll_slave_writedata, -- .writedata
epcs_flash_controller_0_epcs_control_port_address => mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_address, -- epcs_flash_controller_0_epcs_control_port.address
epcs_flash_controller_0_epcs_control_port_write => mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_write, -- .write
epcs_flash_controller_0_epcs_control_port_read => mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_read, -- .read
epcs_flash_controller_0_epcs_control_port_readdata => mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_readdata, -- .readdata
epcs_flash_controller_0_epcs_control_port_writedata => mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_writedata, -- .writedata
epcs_flash_controller_0_epcs_control_port_chipselect => mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_chipselect, -- .chipselect
ip_pwm_0_avs_s0_address => mm_interconnect_0_ip_pwm_0_avs_s0_address, -- ip_pwm_0_avs_s0.address
ip_pwm_0_avs_s0_write => mm_interconnect_0_ip_pwm_0_avs_s0_write, -- .write
ip_pwm_0_avs_s0_read => mm_interconnect_0_ip_pwm_0_avs_s0_read, -- .read
ip_pwm_0_avs_s0_readdata => mm_interconnect_0_ip_pwm_0_avs_s0_readdata, -- .readdata
ip_pwm_0_avs_s0_writedata => mm_interconnect_0_ip_pwm_0_avs_s0_writedata, -- .writedata
ip_pwm_0_avs_s0_waitrequest => mm_interconnect_0_ip_pwm_0_avs_s0_waitrequest, -- .waitrequest
jtag_uart_0_avalon_jtag_slave_address => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address, -- jtag_uart_0_avalon_jtag_slave.address
jtag_uart_0_avalon_jtag_slave_write => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write, -- .write
jtag_uart_0_avalon_jtag_slave_read => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read, -- .read
jtag_uart_0_avalon_jtag_slave_readdata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata, -- .readdata
jtag_uart_0_avalon_jtag_slave_writedata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata, -- .writedata
jtag_uart_0_avalon_jtag_slave_waitrequest => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest, -- .waitrequest
jtag_uart_0_avalon_jtag_slave_chipselect => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect, -- .chipselect
nios2_gen2_0_debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- nios2_gen2_0_debug_mem_slave.address
nios2_gen2_0_debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
nios2_gen2_0_debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
nios2_gen2_0_debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
nios2_gen2_0_debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
nios2_gen2_0_debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
nios2_gen2_0_debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
onchip_memory2_0_s1_address => mm_interconnect_0_onchip_memory2_0_s1_address, -- onchip_memory2_0_s1.address
onchip_memory2_0_s1_write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
onchip_memory2_0_s1_readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
onchip_memory2_0_s1_writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
onchip_memory2_0_s1_byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
onchip_memory2_0_s1_chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
onchip_memory2_0_s1_clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
pio_0_s1_address => mm_interconnect_0_pio_0_s1_address, -- pio_0_s1.address
pio_0_s1_write => mm_interconnect_0_pio_0_s1_write, -- .write
pio_0_s1_readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
pio_0_s1_writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
pio_0_s1_chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
timer_ms_s1_address => mm_interconnect_0_timer_ms_s1_address, -- timer_ms_s1.address
timer_ms_s1_write => mm_interconnect_0_timer_ms_s1_write, -- .write
timer_ms_s1_readdata => mm_interconnect_0_timer_ms_s1_readdata, -- .readdata
timer_ms_s1_writedata => mm_interconnect_0_timer_ms_s1_writedata, -- .writedata
timer_ms_s1_chipselect => mm_interconnect_0_timer_ms_s1_chipselect, -- .chipselect
timer_us_s1_address => mm_interconnect_0_timer_us_s1_address, -- timer_us_s1.address
timer_us_s1_write => mm_interconnect_0_timer_us_s1_write, -- .write
timer_us_s1_readdata => mm_interconnect_0_timer_us_s1_readdata, -- .readdata
timer_us_s1_writedata => mm_interconnect_0_timer_us_s1_writedata, -- .writedata
timer_us_s1_chipselect => mm_interconnect_0_timer_us_s1_chipselect, -- .chipselect
uart_0_s1_address => mm_interconnect_0_uart_0_s1_address, -- uart_0_s1.address
uart_0_s1_write => mm_interconnect_0_uart_0_s1_write, -- .write
uart_0_s1_read => mm_interconnect_0_uart_0_s1_read, -- .read
uart_0_s1_readdata => mm_interconnect_0_uart_0_s1_readdata, -- .readdata
uart_0_s1_writedata => mm_interconnect_0_uart_0_s1_writedata, -- .writedata
uart_0_s1_begintransfer => mm_interconnect_0_uart_0_s1_begintransfer, -- .begintransfer
uart_0_s1_chipselect => mm_interconnect_0_uart_0_s1_chipselect -- .chipselect
);
irq_mapper : component niosii_irq_mapper
port map (
clk => altpll_0_c0_clk, -- clk.clk
reset => rst_controller_003_reset_out_reset, -- clk_reset.reset
receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq
receiver1_irq => irq_mapper_receiver1_irq, -- receiver1.irq
receiver2_irq => irq_mapper_receiver2_irq, -- receiver2.irq
receiver3_irq => irq_mapper_receiver3_irq, -- receiver3.irq
receiver4_irq => irq_mapper_receiver4_irq, -- receiver4.irq
sender_irq => nios2_gen2_0_irq_irq -- sender.irq
);
irq_synchronizer : component altera_irq_clock_crosser
generic map (
IRQ_WIDTH => 1
)
port map (
receiver_clk => altpll_0_c1_clk, -- receiver_clk.clk
sender_clk => altpll_0_c0_clk, -- sender_clk.clk
receiver_reset => rst_controller_002_reset_out_reset, -- receiver_clk_reset.reset
sender_reset => rst_controller_003_reset_out_reset, -- sender_clk_reset.reset
receiver_irq => irq_synchronizer_receiver_irq, -- receiver.irq
sender_irq(0) => irq_mapper_receiver1_irq -- sender.irq
);
irq_synchronizer_001 : component altera_irq_clock_crosser
generic map (
IRQ_WIDTH => 1
)
port map (
receiver_clk => altpll_0_c2_clk, -- receiver_clk.clk
sender_clk => altpll_0_c0_clk, -- sender_clk.clk
receiver_reset => rst_controller_004_reset_out_reset, -- receiver_clk_reset.reset
sender_reset => rst_controller_003_reset_out_reset, -- sender_clk_reset.reset
receiver_irq => irq_synchronizer_001_receiver_irq, -- receiver.irq
sender_irq(0) => irq_mapper_receiver2_irq -- sender.irq
);
irq_synchronizer_002 : component altera_irq_clock_crosser
generic map (
IRQ_WIDTH => 1
)
port map (
receiver_clk => altpll_0_c2_clk, -- receiver_clk.clk
sender_clk => altpll_0_c0_clk, -- sender_clk.clk
receiver_reset => rst_controller_004_reset_out_reset, -- receiver_clk_reset.reset
sender_reset => rst_controller_003_reset_out_reset, -- sender_clk_reset.reset
receiver_irq => irq_synchronizer_002_receiver_irq, -- receiver.irq
sender_irq(0) => irq_mapper_receiver3_irq -- sender.irq
);
irq_synchronizer_003 : component altera_irq_clock_crosser
generic map (
IRQ_WIDTH => 1
)
port map (
receiver_clk => altpll_0_c3_clk, -- receiver_clk.clk
sender_clk => altpll_0_c0_clk, -- sender_clk.clk
receiver_reset => rst_controller_001_reset_out_reset, -- receiver_clk_reset.reset
sender_reset => rst_controller_003_reset_out_reset, -- sender_clk_reset.reset
receiver_irq => irq_synchronizer_003_receiver_irq, -- receiver.irq
sender_irq(0) => irq_mapper_receiver4_irq -- sender.irq
);
rst_controller : component niosii_rst_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => clk_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_001 : component niosii_rst_controller_001
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 1,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => altpll_0_c3_clk, -- clk.clk
reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset
reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_002 : component niosii_rst_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => altpll_0_c1_clk, -- clk.clk
reset_out => rst_controller_002_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_003 : component niosii_rst_controller_001
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 1,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => altpll_0_c0_clk, -- clk.clk
reset_out => rst_controller_003_reset_out_reset, -- reset_out.reset
reset_req => rst_controller_003_reset_out_reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_004 : component niosii_rst_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => altpll_0_c2_clk, -- clk.clk
reset_out => rst_controller_004_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
reset_reset_n_ports_inv <= not reset_reset_n;
mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv <= not mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read;
mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv <= not mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write;
mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_read_ports_inv <= not mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_read;
mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_write_ports_inv <= not mm_interconnect_0_epcs_flash_controller_0_epcs_control_port_write;
mm_interconnect_0_pio_0_s1_write_ports_inv <= not mm_interconnect_0_pio_0_s1_write;
mm_interconnect_0_uart_0_s1_read_ports_inv <= not mm_interconnect_0_uart_0_s1_read;
mm_interconnect_0_uart_0_s1_write_ports_inv <= not mm_interconnect_0_uart_0_s1_write;
mm_interconnect_0_timer_us_s1_write_ports_inv <= not mm_interconnect_0_timer_us_s1_write;
mm_interconnect_0_timer_ms_s1_write_ports_inv <= not mm_interconnect_0_timer_ms_s1_write;
rst_controller_001_reset_out_reset_ports_inv <= not rst_controller_001_reset_out_reset;
rst_controller_002_reset_out_reset_ports_inv <= not rst_controller_002_reset_out_reset;
rst_controller_003_reset_out_reset_ports_inv <= not rst_controller_003_reset_out_reset;
rst_controller_004_reset_out_reset_ports_inv <= not rst_controller_004_reset_out_reset;
end architecture rtl; -- of niosii
|
package config is
constant width : integer;
end package;
-------------------------------------------------------------------------------
use work.config.all;
package types is
-- type pair is record
-- x, y : integer;
-- end record;
-- type pair_vec is array (natural range <>) of pair;
type rec is record
v : bit_vector(1 to width); -- OK
end record;
end package;
-------------------------------------------------------------------------------
package body config is
constant width : integer := 2;
end package body;
-------------------------------------------------------------------------------
entity record28 is
end entity;
use work.types.all;
architecture test of record28 is
signal r, s : rec;
begin
main: process is
begin
assert r.v'length = 2;
r <= ( v => "10" ) after 1 ns;
wait for 2 ns;
assert s.v = "10";
wait;
end process;
process (r) is
begin
s <= r;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use work.sampling.all;
package net_config is
constant tau : positive := 20;
constant num_samplers : integer := 128;
constant num_observers : natural := 16;
constant seeds : lfsr_state_array_t(1 to num_samplers) := (others => (others => '1'));
constant biases : weight_array_t(1 to num_samplers) := (
others => make_fixed(0.0, weight_width-weight_fraction-1, weight_fraction)
);
constant weights : weight_array2_t(1 to num_samplers, 1 to num_samplers) := (
others => (
others => make_fixed(0.0, weight_width-weight_fraction-1, weight_fraction)
)
);
constant observed_joints : state_array2_t(1 to num_observers, 1 to num_samplers) := (
others => (others => '0')
);
--constant biases : weight_array_t(1 to num_samplers) := (
--make_fixed(-1.0, 2, 1),
--make_fixed(-0.5, 2, 1),
--make_fixed(-2.0, 2, 1),
--make_fixed(-1.5, 2, 1)
--);
--constant weights : weight_array2_t(1 to num_samplers, 1 to num_samplers) := (
--(make_fixed(0.0, 2, 1), make_fixed(1.5, 2, 1), make_fixed(1.0, 2, 1), make_fixed(-1.0, 2, 1)),
--(make_fixed(1.5, 2, 1), make_fixed(0.0, 2, 1), make_fixed(1.0, 2, 1), make_fixed(-1.0, 2, 1)),
--(make_fixed(1.0, 2, 1), make_fixed(1.0, 2, 1), make_fixed(0.0, 2, 1), make_fixed(0.5, 2, 1)),
--(make_fixed(-1.0, 2, 1), make_fixed(-1.0, 2, 1), make_fixed(0.5, 2, 1), make_fixed(0.0, 2, 1))
--);
--constant observed_joints : state_array2_t(1 to num_observers, 1 to num_samplers) := (
--( '0', '0', '0', '0' ),
--( '0', '0', '0', '1' ),
--( '0', '0', '1', '0' ),
--( '0', '0', '1', '1' ),
--( '0', '1', '0', '0' ),
--( '0', '1', '0', '1' ),
--( '0', '1', '1', '0' ),
--( '0', '1', '1', '1' ),
--( '1', '0', '0', '0' ),
--( '1', '0', '0', '1' ),
--( '1', '0', '1', '0' ),
--( '1', '0', '1', '1' ),
--( '1', '1', '0', '0' ),
--( '1', '1', '0', '1' ),
--( '1', '1', '1', '0' ),
--( '1', '1', '1', '1' )
--);
end net_config;
-- vim: set et fenc= ff=unix sts=0 sw=2 ts=2 : --
|
USE work.opc_pack.all;
ENTITY tb_opc_circuit IS END tb_opc_circuit;
ARCHITECTURE test of tb_opc_circuit is
COMPONENT opc_circuit IS
PORT(a, b: IN opc;
q, qxor, qxnor: OUT opc);
END COMPONENT;
SIGNAL a, b, q, qxor, qxnor: opc;
SIGNAL clk1, clk2: bit;
BEGIN
T1: opc_circuit PORT MAP(a, b, q, qxor, qxnor);
PROCESS
BEGIN
FOR i IN opc5 LOOP
a<=i;
q<=i;
WAIT ON clk1 UNTIL clk1='1';
END LOOP;
END PROCESS;
PROCESS
BEGIN
FOR j IN opc5 LOOP
b<=j;
q<=j;
WAIT ON clk2 UNTIL clk2='1';
END LOOP;
END PROCESS;
clk1<=NOT(clk1) AFTER 10 ns;
clk2<=NOT(clk2) AFTER 50 ns;
END test; |
-- Chrono implements a simple chronometer with minutes:seconds display.
-- This is just to demonstrate VHDL code, the actual hardware is not suitable
-- for the instended purpose, at least LED drivers should be added, as it
-- stands display is too faint.
--
-- Copyright (C) 2014 Nicola Cimmino
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see http://www.gnu.org/licenses/.
--
-- We assume a 50MHz clock to be available.
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_textio.all;
use IEEE.numeric_std.all;
--------------------------------------------------
entity Chrono is
port(
CLK_50MHz : in std_logic;
DISPLAY_SEG : out std_logic_vector(6 downto 0);
DISPLAY_EN : out std_logic_vector(3 downto 0);
DISPLAY_DP : out std_logic
);
end Chrono;
architecture structure of Chrono is
-- Driver for a seven segment display.
-- Takes a bcd digit as input and drives directly one display.
component SevenSegmentDriver
port(
SEGM: out std_logic_vector(0 to 6);
BCD : in std_logic_vector(3 downto 0)
);
end component;
-- A 4-bit 3-state buffer.
-- Presents input state in output if EN is high, has
-- high impedance outputs othrwise.
component ThreeStateBuffer is
port(
I: in std_logic_vector(0 to 3);
O : out std_logic_vector(0 to 3);
EN: in std_logic
);
end component;
-- A 2 to 4 decoder.
-- Keeps high one of the four outputs depending on the
-- 2-bits input value.
component TwoToFourDecoder is
port(
I: in std_logic_vector(0 to 1);
O : out std_logic_vector(0 to 3)
);
end component;
-- A simple two bits counter.
-- Output increases at every positive edge of clock.
component TwoBitsCounter is
port(
CLK: in std_logic;
O : buffer std_logic_vector(1 downto 0)
);
end component;
-- Counter from 0 to 9.
-- Output increases at every positive edge of clock.
-- The carry output C is set when output rolls from 9 to 0.
component BCDCounter is
port(
CLK: in std_logic;
MAX: in std_logic_vector(3 downto 0);
O : buffer std_logic_vector(3 downto 0);
C : out std_logic
);
end component;
signal current_number : std_logic_vector(15 downto 0);
signal selected_bcd : std_logic_vector(3 downto 0);
signal en_d : std_logic_vector(3 downto 0);
signal cnt : std_logic_vector(1 downto 0);
signal clock_counter : std_logic_vector(25 downto 0);
signal clock_multiplexer : std_logic;
signal clock_1Hz : std_logic;
signal seconds_units_bcd, seconds_tens_bcd, minutes_units_bcd, minutes_tens_bcd : std_logic_vector(3 downto 0);
signal seconds_units_carry, seconds_tens_carry, minutes_units_carry, minutes_tens_carry : std_logic;
begin
-- These are the 4 BCD counters set to have maximum of 5,9,5 and 9 respectively (59:59), they are cascaded so that at each
-- digit carry the following digit will increase. The chain is fed by the 1Hz clock.
--
seconds_unit: BCDCounter port map (CLK => clock_1Hz, MAX => "1001", O => seconds_units_bcd, C => seconds_units_carry);
seconds_tens: BCDCounter port map (CLK => seconds_units_carry, MAX => "0101", O => seconds_tens_bcd, C => seconds_tens_carry);
minutes_units: BCDCounter port map (CLK => seconds_tens_carry, MAX => "1001", O => minutes_units_bcd, C => minutes_units_carry);
minutes_tens: BCDCounter port map (CLK => minutes_units_carry, MAX => "0101", O => minutes_tens_bcd);
-- These are the display drivers and the multiplexing logic. The display multiplexing is timed by the clock_multiplexer signal
-- which runs at roughly 190Hz. The digital point is set only on the two middle digits, this is because the display used was
-- ment specifically for clocks and has a colon separator in the middle connected to the second and third digit.
--
buf_0 : ThreeStateBuffer port map (I => seconds_units_bcd, O => selected_bcd, EN => en_d(3));
buf_1 : ThreeStateBuffer port map (I => seconds_tens_bcd, O => selected_bcd, EN => en_d(2));
buf_2 : ThreeStateBuffer port map (I => minutes_units_bcd, O => selected_bcd, EN => en_d(1));
buf_3 : ThreeStateBuffer port map (I => minutes_tens_bcd, O => selected_bcd, EN => en_d(0));
decoder : TwoToFourDecoder port map (I => cnt, O=>en_d);
counter: TwoBitsCounter port map (CLK => clock_multiplexer, O => cnt);
display_driver: SevenSegmentDriver port map (SEGM => DISPLAY_SEG, BCD => selected_bcd);
DISPLAY_EN <= en_d;
DISPLAY_DP <= clock_1Hz or (not (en_d(1) or en_d(2)));
-- Here we generate the board clocks starting from the 50MHz clock present in the circuit.
-- We need:
-- 1 Hz for time keeping
-- 190 Hz for display multiplexing
--
process (CLK_50MHz)
begin
if(CLK_50MHz = '1' and CLK_50MHz'event) then
clock_counter <= clock_counter + 1;
if(clock_counter = 25000000) then
clock_1Hz <= not clock_1Hz;
clock_counter <= std_logic_vector(to_unsigned(0, clock_counter'length));
end if;
-- This is roughly 190Hz (50E6 / 2^18)
-- There is no reason for this value, as long as it's reasonably low but not too low
-- to prevent flickering. Tapping on a bit of a counter is the easiert way to divide.
clock_multiplexer <= clock_counter(17);
end if;
end process;
end structure;
--------------------------------------------------
|
--------------------------------------------------------------------------------
-- (c) Copyright 2011 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the FIR Compiler IP core.
-- The testbench has been generated by Vivado to accompany the IP core
-- instance you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with your core.
--
-- See the FIR Compiler product guide for further information
-- about this core.
--
--------------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated FIR Compiler core
-- instance named "fir_lp_15kHz".
--
-- Use Vivado's Run Simulation flow to run this testbench. See the Vivado
-- documentation for details.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_fir_lp_15kHz is
end tb_fir_lp_15kHz;
architecture tb of tb_fir_lp_15kHz is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
-----------------------------------------------------------------------
-- DUT signals
-----------------------------------------------------------------------
-- General signals
signal aclk : std_logic := '0'; -- the master clock
-- Data slave channel signals
signal s_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal s_axis_data_tready : std_logic := '1'; -- slave is ready
signal s_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload
-- Data master channel signals
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal m_axis_data_tdata : std_logic_vector(47 downto 0) := (others => '0'); -- data payload
-----------------------------------------------------------------------
-- Aliases for AXI channel TDATA and TUSER fields
-- These are a convenience for viewing data in a simulator waveform viewer.
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
-- to prevent the simulator optimizing away these signals.
-----------------------------------------------------------------------
-- Data slave channel alias signals
signal s_axis_data_tdata_data : std_logic_vector(15 downto 0) := (others => '0');
-- Data master channel alias signals
signal m_axis_data_tdata_data : std_logic_vector(44 downto 0) := (others => '0');
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.fir_lp_15kHz
port map (
aclk => aclk,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tdata => m_axis_data_tdata
);
-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------
clock_gen : process
begin
aclk <= '0';
wait for CLOCK_PERIOD;
loop
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
end loop;
end process clock_gen;
-----------------------------------------------------------------------
-- Generate inputs
-----------------------------------------------------------------------
stimuli : process
-- Procedure to drive a number of input samples with specific data
-- data is the data value to drive on the tdata signal
-- samples is the number of zero-data input samples to drive
procedure drive_data ( data : std_logic_vector(15 downto 0);
samples : natural := 1 ) is
variable ip_count : integer := 0;
begin
ip_count := 0;
loop
s_axis_data_tvalid <= '1';
s_axis_data_tdata <= data;
loop
wait until rising_edge(aclk);
exit when s_axis_data_tready = '1';
end loop;
ip_count := ip_count + 1;
wait for T_HOLD;
-- Input rate is 1 input each 16 clock cycles: drive valid inputs at this rate
s_axis_data_tvalid <= '0';
wait for CLOCK_PERIOD * 15;
exit when ip_count >= samples;
end loop;
end procedure drive_data;
-- Procedure to drive a number of zero-data input samples
-- samples is the number of zero-data input samples to drive
procedure drive_zeros ( samples : natural := 1 ) is
begin
drive_data((others => '0'), samples);
end procedure drive_zeros;
-- Procedure to drive an impulse and let the impulse response emerge on the data master channel
-- samples is the number of input samples to drive; default is enough for impulse response output to emerge
procedure drive_impulse ( samples : natural := 2055 ) is
variable impulse : std_logic_vector(15 downto 0);
begin
impulse := (others => '0'); -- initialize unused bits to zero
impulse(15 downto 0) := "0100000000000000";
drive_data(impulse);
if samples > 1 then
drive_zeros(samples-1);
end if;
end procedure drive_impulse;
begin
-- Drive inputs T_HOLD time after rising edge of clock
wait until rising_edge(aclk);
wait for T_HOLD;
-- Drive a single impulse and let the impulse response emerge
drive_impulse;
-- Drive another impulse, during which demonstrate use and effect of AXI handshaking signals
drive_impulse(2); -- start of impulse; data is now zero
s_axis_data_tvalid <= '0';
wait for CLOCK_PERIOD * 80; -- provide no data for 5 input samples worth
drive_zeros(2); -- 2 normal input samples
s_axis_data_tvalid <= '1';
wait for CLOCK_PERIOD * 80; -- provide data as fast as the core can accept it for 5 input samples worth
drive_zeros(2046); -- back to normal operation
-- End of test
report "Not a real failure. Simulation finished successfully. Test completed successfully" severity failure;
wait;
end process stimuli;
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires the behavioral model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the master DATA channel:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_data_tvalid = '1' then
if is_x(m_axis_data_tdata) then
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
-----------------------------------------------------------------------
-- Assign TDATA / TUSER fields to aliases, for easy simulator waveform viewing
-----------------------------------------------------------------------
-- Data slave channel alias signals
s_axis_data_tdata_data <= s_axis_data_tdata(15 downto 0);
-- Data master channel alias signals: update these only when they are valid
m_axis_data_tdata_data <= m_axis_data_tdata(44 downto 0) when m_axis_data_tvalid = '1';
end tb;
|
architecture rtl of fifo is
alias designator is name;
signal sig1 : std_logic;
alias designator is name;
signal sig1 : std_logic;
alias designator is name;
begin
end architecture rtl;
|
--!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library unisim;
use unisim.vcomponents.all;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! "Virtual" PLL declaration.
use techmap.types_pll.all;
--! "Virtual" buffers declaration.
use techmap.types_buf.all;
--! Top-level implementaion library
library work;
--! Target dependable configuration: RTL, FPGA or ASIC.
use work.config_target.all;
--! Warning: this project wasn't verified on real FPGA (2018 Nov 18). No board is available.
entity zynq_top is port
(
io_gpio : inout std_logic_vector(11 downto 0);
--! UART1 signals:
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
--! UART2 (TAP) signals:
i_uart2_rd : in std_logic;
o_uart2_td : out std_logic;
--! JTAG
i_jtag_tck : in std_logic;
i_jtag_ntrst : in std_logic;
i_jtag_tms : in std_logic;
i_jtag_tdi : in std_logic;
o_jtag_tdo : out std_logic;
o_jtag_vref : out std_logic
);
end zynq_top;
architecture arch_zynq_top of zynq_top is
component riscv_soc is port (
i_rst : in std_logic;
i_clk : in std_logic;
--! GPIO.
i_gpio : in std_logic_vector(11 downto 0);
o_gpio : out std_logic_vector(11 downto 0);
o_gpio_dir : out std_logic_vector(11 downto 0);
--! GPTimers
o_pwm : out std_logic_vector(1 downto 0);
--! JTAG signals:
i_jtag_tck : in std_logic;
i_jtag_ntrst : in std_logic;
i_jtag_tms : in std_logic;
i_jtag_tdi : in std_logic;
o_jtag_tdo : out std_logic;
o_jtag_vref : out std_logic;
--! UART1 signals:
i_uart1_ctsn : in std_logic;
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
o_uart1_rtsn : out std_logic;
--! UART2 (debug port) signals:
i_uart2_ctsn : in std_logic;
i_uart2_rd : in std_logic;
o_uart2_td : out std_logic;
o_uart2_rtsn : out std_logic;
--! SPI Flash
i_flash_si : in std_logic;
o_flash_so : out std_logic;
o_flash_sck : out std_logic;
o_flash_csn : out std_logic;
o_flash_wpn : out std_logic;
o_flash_holdn : out std_logic;
o_flash_reset : out std_logic;
--! OTP Memory
i_otp_d : in std_logic_vector(15 downto 0);
o_otp_d : out std_logic_vector(15 downto 0);
o_otp_a : out std_logic_vector(11 downto 0);
o_otp_we : out std_logic;
o_otp_re : out std_logic;
--! Ethernet MAC PHY interface signals
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
i_eth_mdio : in std_logic;
o_eth_mdio : out std_logic;
o_eth_mdio_oe : out std_logic;
i_eth_gtx_clk : in std_logic;
i_eth_gtx_clk_90 : in std_logic;
o_erstn : out std_ulogic;
-- GNSS Sub-system signals:
i_clk_adc : in std_logic;
i_gps_I : in std_logic_vector(1 downto 0);
i_gps_Q : in std_logic_vector(1 downto 0);
i_glo_I : in std_logic_vector(1 downto 0);
i_glo_Q : in std_logic_vector(1 downto 0);
o_pps : out std_logic;
i_gps_ld : in std_logic;
i_glo_ld : in std_logic;
o_max_sclk : out std_logic;
o_max_sdata : out std_logic;
o_max_ncs : out std_logic_vector(1 downto 0);
i_antext_stat : in std_logic;
i_antext_detect : in std_logic;
o_antext_ena : out std_logic;
o_antint_contr : out std_logic
);
end component;
COMPONENT processing_system7_0
PORT (
M_AXI_GP0_ARVALID : OUT STD_LOGIC;
M_AXI_GP0_AWVALID : OUT STD_LOGIC;
M_AXI_GP0_BREADY : OUT STD_LOGIC;
M_AXI_GP0_RREADY : OUT STD_LOGIC;
M_AXI_GP0_WLAST : OUT STD_LOGIC;
M_AXI_GP0_WVALID : OUT STD_LOGIC;
M_AXI_GP0_ARID : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
M_AXI_GP0_AWID : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
M_AXI_GP0_WID : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
M_AXI_GP0_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP0_ARLOCK : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP0_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_GP0_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP0_AWLOCK : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP0_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_GP0_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_GP0_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_GP0_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_GP0_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_GP0_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_GP0_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_ACLK : IN STD_LOGIC;
M_AXI_GP0_ARREADY : IN STD_LOGIC;
M_AXI_GP0_AWREADY : IN STD_LOGIC;
M_AXI_GP0_BVALID : IN STD_LOGIC;
M_AXI_GP0_RLAST : IN STD_LOGIC;
M_AXI_GP0_RVALID : IN STD_LOGIC;
M_AXI_GP0_WREADY : IN STD_LOGIC;
M_AXI_GP0_BID : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
M_AXI_GP0_RID : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
M_AXI_GP0_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP0_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP0_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
FCLK_CLK0 : OUT STD_LOGIC;
FCLK_RESET0_N : OUT STD_LOGIC;
MIO : INOUT STD_LOGIC_VECTOR(53 DOWNTO 0);
DDR_CAS_n : INOUT STD_LOGIC;
DDR_CKE : INOUT STD_LOGIC;
DDR_Clk_n : INOUT STD_LOGIC;
DDR_Clk : INOUT STD_LOGIC;
DDR_CS_n : INOUT STD_LOGIC;
DDR_DRSTB : INOUT STD_LOGIC;
DDR_ODT : INOUT STD_LOGIC;
DDR_RAS_n : INOUT STD_LOGIC;
DDR_WEB : INOUT STD_LOGIC;
DDR_BankAddr : INOUT STD_LOGIC_VECTOR(2 DOWNTO 0);
DDR_Addr : INOUT STD_LOGIC_VECTOR(14 DOWNTO 0);
DDR_VRN : INOUT STD_LOGIC;
DDR_VRP : INOUT STD_LOGIC;
DDR_DM : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DDR_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DDR_DQS_n : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DDR_DQS : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
PS_SRSTB : INOUT STD_LOGIC;
PS_CLK : INOUT STD_LOGIC;
PS_PORB : INOUT STD_LOGIC
);
END COMPONENT;
signal FCLK_RESET0_N : std_logic;
signal FCLK_RESET0 : std_logic;
signal locked : std_logic;
signal w_ext_clk : std_logic;
signal w_ext_clk_buf : std_logic;
signal w_pll_clk : std_logic;
signal w_pll_lock : std_logic;
signal w_rst : std_logic;
signal ob_gpio_direction : std_logic_vector(11 downto 0);
signal ob_gpio_opins : std_logic_vector(11 downto 0);
signal ib_gpio_ipins : std_logic_vector(11 downto 0);
begin
procsys0 : processing_system7_0
PORT MAP (
M_AXI_GP0_ARVALID => open,
M_AXI_GP0_AWVALID => open,
M_AXI_GP0_BREADY => open,
M_AXI_GP0_RREADY => open,
M_AXI_GP0_WLAST => open,
M_AXI_GP0_WVALID => open,
M_AXI_GP0_ARID => open,
M_AXI_GP0_AWID => open,
M_AXI_GP0_WID => open,
M_AXI_GP0_ARBURST => open,
M_AXI_GP0_ARLOCK => open,
M_AXI_GP0_ARSIZE => open,
M_AXI_GP0_AWBURST => open,
M_AXI_GP0_AWLOCK => open,
M_AXI_GP0_AWSIZE => open,
M_AXI_GP0_ARPROT => open,
M_AXI_GP0_AWPROT => open,
M_AXI_GP0_ARADDR => open,
M_AXI_GP0_AWADDR => open,
M_AXI_GP0_WDATA => open,
M_AXI_GP0_ARCACHE => open,
M_AXI_GP0_ARLEN => open,
M_AXI_GP0_ARQOS => open,
M_AXI_GP0_AWCACHE => open,
M_AXI_GP0_AWLEN => open,
M_AXI_GP0_AWQOS => open,
M_AXI_GP0_WSTRB => open,
M_AXI_GP0_ACLK => w_ext_clk,
M_AXI_GP0_ARREADY => '1',
M_AXI_GP0_AWREADY => '1',
M_AXI_GP0_BVALID => '0',
M_AXI_GP0_RLAST => '0',
M_AXI_GP0_RVALID => '0',
M_AXI_GP0_WREADY => '1',
M_AXI_GP0_BID => X"000",
M_AXI_GP0_RID => X"000",
M_AXI_GP0_BRESP => "00",
M_AXI_GP0_RRESP => "00",
M_AXI_GP0_RDATA => X"00000000",
FCLK_CLK0 => w_ext_clk,
FCLK_RESET0_N => FCLK_RESET0_N,
MIO => open,
DDR_CAS_n => open,
DDR_CKE => open,
DDR_Clk_n => open,
DDR_Clk => open,
DDR_CS_n => open,
DDR_DRSTB => open,
DDR_ODT => open,
DDR_RAS_n => open,
DDR_WEB => open,
DDR_BankAddr => open,
DDR_Addr => open,
DDR_VRN => open,
DDR_VRP => open,
DDR_DM => open,
DDR_DQ => open,
DDR_DQS_n => open,
DDR_DQS => open,
PS_SRSTB => open,
PS_CLK => open,
PS_PORB => open
);
FCLK_RESET0 <= not FCLK_RESET0_N;
buf0 : BUFG port map (
I => w_ext_clk,
O => w_ext_clk_buf
);
gpiox : for i in 0 to 11 generate
iob0 : iobuf_tech generic map(zynq7000)
port map (ib_gpio_ipins(i), io_gpio(i), ob_gpio_opins(i), ob_gpio_direction(i));
end generate;
pll0 : SysPLL_tech generic map (
tech => zynq7000
) port map (
i_reset => FCLK_RESET0,
i_clk_tcxo => w_ext_clk_buf,
o_clk_bus => w_pll_clk,
o_locked => w_pll_lock
);
w_rst <= w_pll_lock;
soc0 : riscv_soc port map (
i_rst => w_rst,
i_clk => w_pll_lock,
--! GPIO.
i_gpio => ib_gpio_ipins,
o_gpio => ob_gpio_opins,
o_gpio_dir => ob_gpio_direction,
--! GPTimers
o_pwm => open,
--! JTAG signals:
i_jtag_tck => i_jtag_tck,
i_jtag_ntrst => i_jtag_ntrst,
i_jtag_tms => i_jtag_tms,
i_jtag_tdi => i_jtag_tdi,
o_jtag_tdo => o_jtag_tdo,
o_jtag_vref => o_jtag_vref,
--! UART1 signals:
i_uart1_ctsn => '0',
i_uart1_rd => i_uart1_rd,
o_uart1_td => o_uart1_td,
o_uart1_rtsn => open,
--! UART2 (debug port) signals:
i_uart2_ctsn => '0',
i_uart2_rd => i_uart2_rd,
o_uart2_td => o_uart2_td,
o_uart2_rtsn => open,
--! SPI Flash
i_flash_si => '0',
o_flash_so => open,
o_flash_sck => open,
o_flash_csn => open,
o_flash_wpn => open,
o_flash_holdn => open,
o_flash_reset => open,
--! OTP Memory
i_otp_d => X"0000",
o_otp_d => open,
o_otp_a => open,
o_otp_we => open,
o_otp_re => open,
--! Ethernet MAC PHY interface signals
i_etx_clk => '0',
i_erx_clk => '0',
i_erxd => X"0",
i_erx_dv => '0',
i_erx_er => '0',
i_erx_col => '0',
i_erx_crs => '0',
i_emdint => '0',
o_etxd => open,
o_etx_en => open,
o_etx_er => open,
o_emdc => open,
i_eth_mdio => '0',
o_eth_mdio => open,
o_eth_mdio_oe => open,
i_eth_gtx_clk => '0',
i_eth_gtx_clk_90 => '0',
o_erstn => open,
-- GNSS Sub-system signals:
i_clk_adc => '0',
i_gps_I => "00",
i_gps_Q => "00",
i_glo_I => "00",
i_glo_Q => "00",
o_pps => open,
i_gps_ld => '0',
i_glo_ld => '0',
o_max_sclk => open,
o_max_sdata => open,
o_max_ncs => open,
i_antext_stat => '0',
i_antext_detect => '0',
o_antext_ena => open,
o_antint_contr => open
);
end arch_zynq_top;
|
entity modulo_test is
port (
a : in integer;
b : out integer;
c : out integer
);
end modulo_test;
architecture rtl of modulo_test is
begin
b <= a mod 8;
c <= a rem 8;
end rtl;
|
package multiple_function_bodies_pkg is
function fun return integer;
end package;
package body multiple_function_bodies_pkg is
function fun return integer is
begin
return 0;
end function;
function fun return integer is -- Error
begin
return 1;
end function;
procedure proc(x : integer) is
begin
end procedure;
procedure proc(x : integer) is -- Error
begin
end procedure;
end package body;
|
package multiple_function_bodies_pkg is
function fun return integer;
end package;
package body multiple_function_bodies_pkg is
function fun return integer is
begin
return 0;
end function;
function fun return integer is -- Error
begin
return 1;
end function;
procedure proc(x : integer) is
begin
end procedure;
procedure proc(x : integer) is -- Error
begin
end procedure;
end package body;
|
package multiple_function_bodies_pkg is
function fun return integer;
end package;
package body multiple_function_bodies_pkg is
function fun return integer is
begin
return 0;
end function;
function fun return integer is -- Error
begin
return 1;
end function;
procedure proc(x : integer) is
begin
end procedure;
procedure proc(x : integer) is -- Error
begin
end procedure;
end package body;
|
package multiple_function_bodies_pkg is
function fun return integer;
end package;
package body multiple_function_bodies_pkg is
function fun return integer is
begin
return 0;
end function;
function fun return integer is -- Error
begin
return 1;
end function;
procedure proc(x : integer) is
begin
end procedure;
procedure proc(x : integer) is -- Error
begin
end procedure;
end package body;
|
package multiple_function_bodies_pkg is
function fun return integer;
end package;
package body multiple_function_bodies_pkg is
function fun return integer is
begin
return 0;
end function;
function fun return integer is -- Error
begin
return 1;
end function;
procedure proc(x : integer) is
begin
end procedure;
procedure proc(x : integer) is -- Error
begin
end procedure;
end package body;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity resetter is
port(
clk, rst : in std_logic;
address : out integer;
write : out std_logic
);
end resetter;
architecture Behavioral of resetter is
constant MAX_INDEX : integer := 307199;
type state is (idle, writing);
signal curr_state, next_state : state;
signal index : integer := 0;
begin
process(clk, rst)
begin
if('1' = rst) then
curr_state <= idle;
index <= 0;
elsif(rising_edge(clk)) then
curr_state <= next_state;
end if;
end process;
process(curr_state)
begin
next_state <= curr_state;
write <= '0';
case curr_state is
when idle =>
index <= 0;
-- Do nothing
when writing =>
-- increement the address to be written
index <= index + 1;
-- check if we need to keep going...
if(index > MAX_INDEX) then
next_state <= idle;
-- signal that we are still writing
write <= '1';
else
next_state <= writing;
end if;
end case;
end process;
address <= index;
end Behavioral;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Sun Jun 18 18:22:32 2017
-- Host : DESKTOP-GKPSR1F running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.vhdl
-- Design : clk_wiz_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
reset : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz is
signal clk_in1_clk_wiz_0 : STD_LOGIC;
signal clk_out1_clk_wiz_0 : STD_LOGIC;
signal clkfbout_buf_clk_wiz_0 : STD_LOGIC;
signal clkfbout_clk_wiz_0 : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_clk_wiz_0,
O => clkfbout_buf_clk_wiz_0
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_clk_wiz_0
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_clk_wiz_0,
O => clk_out1
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 10.250000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 12.500000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_clk_wiz_0,
CLKFBOUT => clkfbout_clk_wiz_0,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_clk_wiz_0,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_clk_wiz_0,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clk_out1 : out STD_LOGIC;
reset : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
locked => locked,
reset => reset
);
end STRUCTURE;
|
-------------------------------------------------------------------------------
-- Copyright (c) 1999-2006 Xilinx Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Title : ILA Core Xilinx XST Usage Example
-- Project : ChipScope
-------------------------------------------------------------------------------
-- File : dcr_ila_xst_example.vhd
-- Company : Xilinx Inc.
-- Created : 2000/10/18
-------------------------------------------------------------------------------
-- Description: Example of how to instantiate the ILA core in a VHDL design
-- for use with the Xilinx XST synthesis tool.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity dcr_ila_xst_example is
end dcr_ila_xst_example;
architecture structure of dcr_ila_xst_example is
-------------------------------------------------------------------
--
-- ILA core component declaration
--
-------------------------------------------------------------------
component dcr_ila
port
(
control : in std_logic_vector(35 downto 0);
clk : in std_logic;
data : in std_logic_vector(76 downto 0);
trig0 : in std_logic_vector(2 downto 0)
);
end component;
-------------------------------------------------------------------
--
-- ILA core signal declarations
--
-------------------------------------------------------------------
signal control : std_logic_vector(35 downto 0);
signal clk : std_logic;
signal data : std_logic_vector(76 downto 0);
signal trig0 : std_logic_vector(2 downto 0);
begin
-------------------------------------------------------------------
--
-- ILA core instance
--
-------------------------------------------------------------------
i_dcr_ila : dcr_ila
port map
(
control => control,
clk => clk,
data => data,
trig0 => trig0
);
end structure;
|
`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 99168)
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect begin_protected
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`protect begin_protected
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`protect end_protected
|
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