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`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 99168)
`protect data_block
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|
`protect begin_protected
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`protect begin_protected
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`protect begin_protected
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bMhbO2UMi82Cy40wb4Ln1c8tS4x0PUjSfI1VHKPmcV+DTVkIukmvhBYWliYv5K0fEVfhppXy34f9
SAbnnyNcnfU28tbYSeINhM3s1C3kQout/Nev0WYojZX9JO/UbUvEZKa+WSEWl0qH9i3iP6KKM4Ik
DYK1c0Gf34TDFR6pXYkNz9fqiKk7sag4v7ncXEW+ULrhpzCX1m9BwToHw6W1WjagE/C8XnIfK+dp
jfn0jzCtCDoei2VPHi4sfSi+hr6X8Wf9/JmjwVDw9s1tqaAfkNn6cXrurslmtAHfXU5FLVdMYOr4
XGXBzUURzko14r3ny9kDzbcO7jfK4RAWaMwl53iId3ih5zY2zN38jalPlyHs89QNsm6YPPfY36v7
W+Q8Kkixz6uoRL9C1Wx12aJlaicBgRK84P5+K2B3Ir4HjBdDbCVjwgqm7GlZuB30i0DIEhT4ppc/
0aD8sh6gp5GqqE4obEmxxmWOcnlb++35JscTBMIabdIOuOfIMg5+5MfZUIEueR//5ohKBVLmCIUl
V71JoESFC9pvxLrhcNaydQnT7+we+g8twwuxnjXQ3OlDtJp6rM8GMImee6xQXtAl7sN682LkGAlh
YHgXEuQC6kCG78/iIwKQ2nXgrpty040fWjo/kxvAuGw05D8sK1iNCpNrUWUSXyp9hluRkpoyjuBJ
E3pLQOAGn8Xfyq+bQWgxPuojQybpwSlXCIDZpEFCnzLQohFhJtY4YaoxJvrHsbZO1WpxqjZEg7jv
GuRQkzxKWiOzc1KqLt64zNRyIoTaRRiLTZQmzsfB6PEFC4eRVT2cuHVlsGqzHAuF2fymO0eZLR2F
8gSAERTUuvPsdgFsFttBQPf0oMW05nMjcJJk/ieDX3TFiWNCld+DDe0Khtnne3cfsOMM8PSWNOul
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4PHfqIs4pa+jYr95g8lPbYVGU5xKABe/DlxUPdvzkXaAVy7Ys/J0/COkVQbcfhkp4FYTY5oLiNG0
Ys95bB3q4QfAZJjg3K58lt1PBZ76UgrZzv8g9r0U18iI9JhMkFJRCW0PUfmS3dY22l6Z+YuVIvMq
al6KWymKN5pb69JQyW+gWvIQUCNkAwlyQ44NahfDWDvXFnZdJZcMtlBS1czNw5jvWE4pARpym9fd
D2llqogXKJxuFdbGJx76OgqDYwAHhYeKH+rUfjhcjIISJ/XOPWXeQ62HAbg2V40hzHkb852bg1k2
fWsB4evP1cKHW+Lj3ZDGJkl8L5hsXqbfpRtLlkWBOVLSb3kdi7sBnIofiCMe+QruaRoeU2JGg1Qc
tU56/gsK1fJ3S1/EPmrp9x717lpctAqIz9ToQvvMC3TuTdEE6DvPq5Y6FD//lGZmwvY5pThmcDiO
h4zfl6IdRMubiE7Q3m4NAJNXKRtfDkDml4ROoSxNGZVxfjTXpQsKq85hhTJaExqDEAkqO0I/5KDH
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0dK3w9UTuGUH0/MfpqR4C6l5DIO+kKGJyshs6JaoaYZA8q71vZ+hgdkPzoMkDo4uPKd8SUVan5++
QpMqedDHsmx+S1vbozRMkbcXM4XuVPOnj+Xt13OgW5SjdLMEYPTOgyYSeLQm9twB1tOYIkMskDF8
4nbNhohz0fOnjvwrPGuMmpZMp6qlEbEG1q5Kc1gMv9/dYIgTx/3DPFbL+H+BIhXnZyZmLiDj+Qwd
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UlahMNjbZo+12Xg+3HMG3GqtjlPNNlYdzCsSW+mTTa0uonLbEI2mCFSWn0NFfeKrVqrzx0qWLc9m
CRbL25v4AZbWXdR/PfdNw3Dj9NLKV6CzA2xSiYjYzaB09MRXOnUrF/PN9bP/5/IWh4qkqAFA8+no
VLglT0bZmFltd1W/cwvOHO7T2oxaWK35CXOPTn4RnIzV0vmsEkOLifksxKPFV2Dk+QCG73dKhgKF
mlCVEUoRHGX9aMSZFjOIl/rldwj2j6A+lJV6ldXf/hXsNya2kRFFHmyYILg/jrmIzpfADddWI/V2
s4XA+ABFvJUIE5IiWh0e/Mpk6obEzilAB7LiX7B5X0uZuzV8aRJw+3jIl8p5UiVxPtsqLFlgkUmx
6GRNEOZ97GU/wKnlyGXiwomyGpVkoiUHwa7ey3oHrZEXcXx8Ks875xnWNSNr
`protect end_protected
|
-------------------------------------------------------------------------------
-- Entity: rom
-- Author: Waj
-- Date : 11-May-13, 26-May-13
-------------------------------------------------------------------------------
-- Description: (ECS Uebung 9)
-- Program memory for simple von-Neumann MCU with registerd read data output.
-------------------------------------------------------------------------------
-- Total # of FFs: DW
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity rom is
port(clk : in std_logic;
-- ROM bus signals
bus_in : in t_bus2ros;
bus_out : out t_ros2bus
);
end rom;
architecture rtl of rom is
type t_rom is array (0 to 2**AWL-1) of std_logic_vector(DW-1 downto 0);
constant rom_table : t_rom := (
---------------------------------------------------------------------------
-- program code -----------------------------------------------------------
---------------------------------------------------------------------------
-- Opcode Rdest Rsrc1 Rsrc2 description
---------------------------------------------------------------------------
-- Prepare Ctrl to set capture flag
OPC(setil) & reg(0) & n2slv(16#01#, DW/2), -- setil r0, 0x01
OPC(setih) & reg(0) & n2slv(16#00#, DW/2), -- setih r0, 0x00
-- Prepare ctrl address
OPC(setil) & reg(1) & n2slv(16#03#, DW/2), -- setil r1, 0x03
OPC(setih) & reg(1) & n2slv(16#03#, DW/2), -- setih r1, 0x30
-- Prepare counter address
OPC(setil) & reg(2) & n2slv(16#04#, DW/2), -- setil r2, 0x04
OPC(setih) & reg(2) & n2slv(16#03#, DW/2), -- setih r2, 0x30
-- Endless loop
-- set capture flag
OPC(st) & reg(0) & reg(1) & "-----", -- st r0, r1
-- read counter
OPC(ld) & reg(3) & reg(2) & "-----", -- st r3, r2
-- End of endless loop
OPC(jmp) & "-00" & n2slv(16#06#, AW-2), -- jmp 0x006
---------------------------------------------------------------------------
others => OPC(nop) & "-----------" -- NOP
);
begin
-----------------------------------------------------------------------------
-- sequential process: ROM table with registerd output
-----------------------------------------------------------------------------
P_rom: process(clk)
begin
if rising_edge(clk) then
bus_out.data <= rom_table(to_integer(unsigned(bus_in.addr)));
end if;
end process;
end rtl;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of vgca
--
-- Generated
-- by: wig
-- on: Wed Aug 18 12:40:14 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: vgca-struct-a.vhd,v 1.3 2005/10/06 11:16:07 wig Exp $
-- $Date: 2005/10/06 11:16:07 $
-- $Log: vgca-struct-a.vhd,v $
-- Revision 1.3 2005/10/06 11:16:07 wig
-- Got testcoverage up, fixed generic problem, prepared report
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.45 2004/08/09 15:48:14 wig Exp
--
-- Generator: mix_0.pl Revision: 1.32 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture struct of vgca
--
architecture struct of vgca is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component mic32_top --
-- No Generated Generics
port (
-- Generated Port for Entity mic32_top
eic_int_src_alt_i : in std_ulogic_vector(60 downto 1);
eic_int_src_i : in std_ulogic_vector(60 downto 1)
-- End of Generated Port for Entity mic32_top
);
end component;
-- ---------
component vgca_di --
-- No Generated Generics
port (
-- Generated Port for Entity vgca_di
fmdstatusm_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
fmdstatuss_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
lbdstatusm_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
lbdstatuss_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
line_stable_m_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
line_stable_s_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
pixel_stable_m_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
pixel_stable_s_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
vaqm_vsync_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
vaqs_vsync_irq_o : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity vgca_di
);
end component;
-- ---------
component vgca_dp --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component vgca_fe --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component vgca_ga --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component vgca_peri --
-- No Generated Generics
port (
-- Generated Port for Entity vgca_peri
cadc_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
crt_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
ddc_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
gpio_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
gpt1_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
gpt2_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
gpt3_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
gpt4_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
i2c_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
i2s_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
irri_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
nvmc_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
rtc_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
ssi1_rx_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
ssi1_tx_irq_alt_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
ssi1_tx_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
ssi2_rx_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
ssi2_tx_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
uart1_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
uart2_irq_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
wdt_irq_o : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity vgca_peri
);
end component;
-- ---------
component vgca_rc --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal eic_int_src : std_ulogic_vector(60 downto 1);
signal eic_int_src_alt : std_ulogic_vector(60 downto 1);
constant eic_int_src_c : std_ulogic := '0'; -- __W_SINGLE_BIT_BUS
constant eic_int_src_c_1c : std_ulogic_vector(2 downto 0) := ( others => '0' );
constant eic_int_src_c_2c : std_ulogic := '0'; -- __W_SINGLE_BIT_BUS
constant eic_int_src_c_3c : std_ulogic := '0'; -- __W_SINGLE_BIT_BUS
constant eic_int_src_c_4c : std_ulogic := '0'; -- __W_SINGLE_BIT_BUS
constant mix_const_0 : std_ulogic := '0'; -- __W_SINGLE_BIT_BUS
constant mix_const_1 : std_ulogic := '0'; -- __W_SINGLE_BIT_BUS
constant mix_const_2 : std_ulogic := '0'; -- __W_SINGLE_BIT_BUS
constant mix_const_3 : std_ulogic := '0'; -- __W_SINGLE_BIT_BUS
constant mix_const_4 : std_ulogic_vector(2 downto 0) := ( others => '0' );
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
eic_int_src(1) <= eic_int_src_c; -- __W_SINGLE_BIT_BUS -- __W_SINGLE_BIT_BUS
eic_int_src(10) <= eic_int_src_c_2c; -- __W_SINGLE_BIT_BUS -- __W_SINGLE_BIT_BUS
eic_int_src(19) <= eic_int_src_c_3c; -- __W_SINGLE_BIT_BUS -- __W_SINGLE_BIT_BUS
eic_int_src(44) <= eic_int_src_c_4c; -- __W_SINGLE_BIT_BUS -- __W_SINGLE_BIT_BUS
eic_int_src(59 downto 57) <= eic_int_src_c_1c;
eic_int_src_alt(1) <= mix_const_0; -- __W_SINGLE_BIT_BUS -- __W_SINGLE_BIT_BUS
eic_int_src_alt(10) <= mix_const_1; -- __W_SINGLE_BIT_BUS -- __W_SINGLE_BIT_BUS
eic_int_src_alt(19) <= mix_const_2; -- __W_SINGLE_BIT_BUS -- __W_SINGLE_BIT_BUS
eic_int_src_alt(44) <= mix_const_3; -- __W_SINGLE_BIT_BUS -- __W_SINGLE_BIT_BUS
eic_int_src_alt(59 downto 57) <= mix_const_4;
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for i_mic32_top
i_mic32_top: mic32_top
port map (
eic_int_src_alt_i => eic_int_src_alt,
eic_int_src_i => eic_int_src -- Interrupt Controller (X10)
);
-- End of Generated Instance Port Map for i_mic32_top
-- Generated Instance Port Map for i_vgca_di
i_vgca_di: vgca_di
port map (
fmdstatusm_irq_o => eic_int_src(40), -- Interrupt Controller (X10)
fmdstatuss_irq_o => eic_int_src(43), -- Interrupt Controller (X10)
lbdstatusm_irq_o => eic_int_src(34), -- Interrupt Controller (X10)
lbdstatuss_irq_o => eic_int_src(37), -- Interrupt Controller (X10)
line_stable_m_irq_o => eic_int_src(2), -- Interrupt Controller (X10)
line_stable_s_irq_o => eic_int_src(3), -- Interrupt Controller (X10)
pixel_stable_m_irq_o => eic_int_src(46), -- Interrupt Controller (X10)
pixel_stable_s_irq_o => eic_int_src(47), -- Interrupt Controller (X10)
vaqm_vsync_irq_o => eic_int_src(17), -- Interrupt Controller (X10)
vaqs_vsync_irq_o => eic_int_src(18) -- Interrupt Controller (X10)
);
-- End of Generated Instance Port Map for i_vgca_di
-- Generated Instance Port Map for i_vgca_dp
i_vgca_dp: vgca_dp
;
-- End of Generated Instance Port Map for i_vgca_dp
-- Generated Instance Port Map for i_vgca_fe
i_vgca_fe: vgca_fe
;
-- End of Generated Instance Port Map for i_vgca_fe
-- Generated Instance Port Map for i_vgca_ga
i_vgca_ga: vgca_ga
;
-- End of Generated Instance Port Map for i_vgca_ga
-- Generated Instance Port Map for i_vgca_peri
i_vgca_peri: vgca_peri
port map (
cadc_irq_o => eic_int_src(30), -- Interrupt Controller (X10)
crt_irq_o => eic_int_src(54), -- Interrupt Controller (X10)
ddc_irq_o => eic_int_src(15), -- Interrupt Controller (X10)
gpio_irq_o => eic_int_src(26), -- Interrupt Controller (X10)
gpt1_irq_o => eic_int_src(48), -- Interrupt Controller (X10)
gpt2_irq_o => eic_int_src(27), -- Interrupt Controller (X10)
gpt3_irq_o => eic_int_src(28), -- Interrupt Controller (X10)
gpt4_irq_o => eic_int_src(29), -- Interrupt Controller (X10)
i2c_irq_o => eic_int_src(31), -- Interrupt Controller (X10)
i2s_irq_o => eic_int_src(16), -- Interrupt Controller (X10)
irri_irq_o => eic_int_src(51), -- Interrupt Controller (X10)
nvmc_irq_o => eic_int_src(14), -- Interrupt Controller (X10)
rtc_irq_o => eic_int_src(21), -- Interrupt Controller (X10)
ssi1_rx_irq_o => eic_int_src(22), -- Interrupt Controller (X10)
ssi1_tx_irq_alt_o => eic_int_src_alt(12),
ssi1_tx_irq_o => eic_int_src(12), -- Interrupt Controller (X10)
ssi2_rx_irq_o => eic_int_src(23), -- Interrupt Controller (X10)
ssi2_tx_irq_o => eic_int_src(13), -- Interrupt Controller (X10)
uart1_irq_o => eic_int_src(24), -- Interrupt Controller (X10)
uart2_irq_o => eic_int_src(25), -- Interrupt Controller (X10)
wdt_irq_o => eic_int_src(60) -- Interrupt Controller (X10)
);
-- End of Generated Instance Port Map for i_vgca_peri
-- Generated Instance Port Map for i_vgca_rc
i_vgca_rc: vgca_rc
;
-- End of Generated Instance Port Map for i_vgca_rc
end struct;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
lpm_add_sub0_inst : lpm_add_sub0 PORT MAP (
datab => datab_sig,
result => result_sig
);
|
package cond1 is
`if TOOL_NAME = "false" then
`error "Should not be here"
constant d : integer := 1;
`else
constant c : integer := 1;
`end if
`warning "this is a warning"
`if TOOL_NAME = "nvc" then
`warning "Using nvc"
`end if
`if not (TOOL_TYPE = "SIMULATION") then
`error "Should not be here"
`end if
`if TOOL_TYPE /= "SYNTHESIS" and TOOL_NAME = "nvc" then
`warning "correct"
`end if
`if VHDL_VERSION = "1993" then
`warning "VHDL version is correct"
`end if
end package;
package cond2 is
`if FOO = "bar" then
`end
`if TOOL_NAME = "nvc" then
-- Unterminated
end package
|
package cond1 is
`if TOOL_NAME = "false" then
`error "Should not be here"
constant d : integer := 1;
`else
constant c : integer := 1;
`end if
`warning "this is a warning"
`if TOOL_NAME = "nvc" then
`warning "Using nvc"
`end if
`if not (TOOL_TYPE = "SIMULATION") then
`error "Should not be here"
`end if
`if TOOL_TYPE /= "SYNTHESIS" and TOOL_NAME = "nvc" then
`warning "correct"
`end if
`if VHDL_VERSION = "1993" then
`warning "VHDL version is correct"
`end if
end package;
package cond2 is
`if FOO = "bar" then
`end
`if TOOL_NAME = "nvc" then
-- Unterminated
end package
|
architecture RTL of FIFO is
begin
BLOCK_LABEL : block is begin end block;
BLOCK_LABEL : block (guard_condition) is begin end block;
-- Violations below
BLOCK_LABEL : block is
begin end block;
BLOCK_LABEL : block (guard_condition) is
begin end block;
end architecture RTL;
|
-- /* -------------------------------------------------------------------------
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Copyright: Levent Ozturk [email protected]
-- https://leventozturk.com/engineering/crc/
-- Polynomial: x128+x124+x123+x122+x114+x113+x112+x109+x106+x104+x102+x100+x99+x98+x97+x96+x94+x93+x92+x88+x85+x82+x81+x80+x79+x76+x74+x73+x72+x71+x69+x68+x67+x66+x64+x60+x59+x56+x55+x54+x53+x52+x51+x50+x46+x45+x43+x42+x40+x38+x37+x36+x34+x32+x26+x23+x22+x21+x20+x19+x16+x14+x13+x10+x9+x5+x3+x1+1
-- d63 is the first data processed
-- c is internal LFSR state and the CRC output. Not needed for other modules than CRC.
-- c width is always same as polynomial width.
-- o is the output of all modules except CRC. Not needed for CRC.
-- o width is always same as data width width
-------------------------------------------------------------------------*/
-- Based on https://leventozturk.com/engineering/crc/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bch_128x64 is
generic (
SEED : in std_ulogic_vector(127 downto 0) := (others => '0')
);
port (
clk : in std_ulogic;
reset : in std_ulogic;
fd : in std_ulogic; -- First data. 1: SEED is used (initialise and calculate), 0: Previous CRC is used (continue and calculate)
nd : in std_ulogic; -- New Data. d input has a valid data. Calculate new CRC
rdy : out std_ulogic;
d : in std_ulogic_vector( 63 downto 0); -- Data in
c : out std_ulogic_vector(127 downto 0);
-- CRC output
o : out std_ulogic_vector( 63 downto 0) -- Data output
);
end entity bch_128x64;
architecture bch_128x64 of bch_128x64 is
signal nd_q : std_ulogic;
signal fd_q : std_ulogic;
signal dq : std_ulogic_vector (127 downto 0);
signal ca : std_ulogic_vector(127 downto 0);
signal oa : std_ulogic_vector( 63 downto 0);
begin
process (clk)
begin
if (rising_edge(clk)) then
nd_q <= nd;
fd_q <= fd;
dq( 0) <= d( 62) xor d( 58) xor d( 56) xor d( 53) xor d( 51) xor d( 50) xor d( 48) xor d( 47) xor d( 46) xor d( 45) xor d( 43) xor d( 37) xor d( 35) xor d( 34) xor d( 33) xor d( 28) xor d( 26) xor d( 23) xor d( 22) xor d( 21) xor d( 19) xor d( 18) xor d( 17) xor d( 14) xor d( 13) xor d( 10) xor d( 8) xor d( 6) xor d( 5) xor d( 4) xor d( 0);
dq( 1) <= d( 63) xor d( 62) xor d( 59) xor d( 58) xor d( 57) xor d( 56) xor d( 54) xor d( 53) xor d( 52) xor d( 50) xor d( 49) xor d( 45) xor d( 44) xor d( 43) xor d( 38) xor d( 37) xor d( 36) xor d( 33) xor d( 29) xor d( 28) xor d( 27) xor d( 26) xor d( 24) xor d( 21) xor d( 20) xor d( 17) xor d( 15) xor d( 13) xor d( 11) xor d( 10) xor d( 9) xor d( 8) xor d( 7) xor d( 4) xor d( 1) xor d( 0);
dq( 2) <= d( 63) xor d( 60) xor d( 59) xor d( 58) xor d( 57) xor d( 55) xor d( 54) xor d( 53) xor d( 51) xor d( 50) xor d( 46) xor d( 45) xor d( 44) xor d( 39) xor d( 38) xor d( 37) xor d( 34) xor d( 30) xor d( 29) xor d( 28) xor d( 27) xor d( 25) xor d( 22) xor d( 21) xor d( 18) xor d( 16) xor d( 14) xor d( 12) xor d( 11) xor d( 10) xor d( 9) xor d( 8) xor d( 5) xor d( 2) xor d( 1);
dq( 3) <= d( 62) xor d( 61) xor d( 60) xor d( 59) xor d( 55) xor d( 54) xor d( 53) xor d( 52) xor d( 50) xor d( 48) xor d( 43) xor d( 40) xor d( 39) xor d( 38) xor d( 37) xor d( 34) xor d( 33) xor d( 31) xor d( 30) xor d( 29) xor d( 21) xor d( 18) xor d( 15) xor d( 14) xor d( 12) xor d( 11) xor d( 9) xor d( 8) xor d( 5) xor d( 4) xor d( 3) xor d( 2) xor d( 0);
dq( 4) <= d( 63) xor d( 62) xor d( 61) xor d( 60) xor d( 56) xor d( 55) xor d( 54) xor d( 53) xor d( 51) xor d( 49) xor d( 44) xor d( 41) xor d( 40) xor d( 39) xor d( 38) xor d( 35) xor d( 34) xor d( 32) xor d( 31) xor d( 30) xor d( 22) xor d( 19) xor d( 16) xor d( 15) xor d( 13) xor d( 12) xor d( 10) xor d( 9) xor d( 6) xor d( 5) xor d( 4) xor d( 3) xor d( 1);
dq( 5) <= d( 63) xor d( 61) xor d( 58) xor d( 57) xor d( 55) xor d( 54) xor d( 53) xor d( 52) xor d( 51) xor d( 48) xor d( 47) xor d( 46) xor d( 43) xor d( 42) xor d( 41) xor d( 40) xor d( 39) xor d( 37) xor d( 36) xor d( 34) xor d( 32) xor d( 31) xor d( 28) xor d( 26) xor d( 22) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 16) xor d( 11) xor d( 8) xor d( 7) xor d( 2) xor d( 0);
dq( 6) <= d( 62) xor d( 59) xor d( 58) xor d( 56) xor d( 55) xor d( 54) xor d( 53) xor d( 52) xor d( 49) xor d( 48) xor d( 47) xor d( 44) xor d( 43) xor d( 42) xor d( 41) xor d( 40) xor d( 38) xor d( 37) xor d( 35) xor d( 33) xor d( 32) xor d( 29) xor d( 27) xor d( 23) xor d( 22) xor d( 21) xor d( 20) xor d( 19) xor d( 17) xor d( 12) xor d( 9) xor d( 8) xor d( 3) xor d( 1);
dq( 7) <= d( 63) xor d( 60) xor d( 59) xor d( 57) xor d( 56) xor d( 55) xor d( 54) xor d( 53) xor d( 50) xor d( 49) xor d( 48) xor d( 45) xor d( 44) xor d( 43) xor d( 42) xor d( 41) xor d( 39) xor d( 38) xor d( 36) xor d( 34) xor d( 33) xor d( 30) xor d( 28) xor d( 24) xor d( 23) xor d( 22) xor d( 21) xor d( 20) xor d( 18) xor d( 13) xor d( 10) xor d( 9) xor d( 4) xor d( 2);
dq( 8) <= d( 61) xor d( 60) xor d( 58) xor d( 57) xor d( 56) xor d( 55) xor d( 54) xor d( 51) xor d( 50) xor d( 49) xor d( 46) xor d( 45) xor d( 44) xor d( 43) xor d( 42) xor d( 40) xor d( 39) xor d( 37) xor d( 35) xor d( 34) xor d( 31) xor d( 29) xor d( 25) xor d( 24) xor d( 23) xor d( 22) xor d( 21) xor d( 19) xor d( 14) xor d( 11) xor d( 10) xor d( 5) xor d( 3);
dq( 9) <= d( 61) xor d( 59) xor d( 57) xor d( 55) xor d( 53) xor d( 52) xor d( 48) xor d( 44) xor d( 41) xor d( 40) xor d( 38) xor d( 37) xor d( 36) xor d( 34) xor d( 33) xor d( 32) xor d( 30) xor d( 28) xor d( 25) xor d( 24) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 17) xor d( 15) xor d( 14) xor d( 13) xor d( 12) xor d( 11) xor d( 10) xor d( 8) xor d( 5) xor d( 0);
dq( 10) <= d( 60) xor d( 54) xor d( 51) xor d( 50) xor d( 49) xor d( 48) xor d( 47) xor d( 46) xor d( 43) xor d( 42) xor d( 41) xor d( 39) xor d( 38) xor d( 31) xor d( 29) xor d( 28) xor d( 25) xor d( 23) xor d( 20) xor d( 17) xor d( 16) xor d( 15) xor d( 12) xor d( 11) xor d( 10) xor d( 9) xor d( 8) xor d( 5) xor d( 4) xor d( 1) xor d( 0);
dq( 11) <= d( 61) xor d( 55) xor d( 52) xor d( 51) xor d( 50) xor d( 49) xor d( 48) xor d( 47) xor d( 44) xor d( 43) xor d( 42) xor d( 40) xor d( 39) xor d( 32) xor d( 30) xor d( 29) xor d( 26) xor d( 24) xor d( 21) xor d( 18) xor d( 17) xor d( 16) xor d( 13) xor d( 12) xor d( 11) xor d( 10) xor d( 9) xor d( 6) xor d( 5) xor d( 2) xor d( 1);
dq( 12) <= d( 62) xor d( 56) xor d( 53) xor d( 52) xor d( 51) xor d( 50) xor d( 49) xor d( 48) xor d( 45) xor d( 44) xor d( 43) xor d( 41) xor d( 40) xor d( 33) xor d( 31) xor d( 30) xor d( 27) xor d( 25) xor d( 22) xor d( 19) xor d( 18) xor d( 17) xor d( 14) xor d( 13) xor d( 12) xor d( 11) xor d( 10) xor d( 7) xor d( 6) xor d( 3) xor d( 2);
dq( 13) <= d( 63) xor d( 62) xor d( 58) xor d( 57) xor d( 56) xor d( 54) xor d( 52) xor d( 49) xor d( 48) xor d( 47) xor d( 44) xor d( 43) xor d( 42) xor d( 41) xor d( 37) xor d( 35) xor d( 33) xor d( 32) xor d( 31) xor d( 22) xor d( 21) xor d( 20) xor d( 17) xor d( 15) xor d( 12) xor d( 11) xor d( 10) xor d( 7) xor d( 6) xor d( 5) xor d( 3) xor d( 0);
dq( 14) <= d( 63) xor d( 62) xor d( 59) xor d( 57) xor d( 56) xor d( 55) xor d( 51) xor d( 49) xor d( 47) xor d( 46) xor d( 44) xor d( 42) xor d( 38) xor d( 37) xor d( 36) xor d( 35) xor d( 32) xor d( 28) xor d( 26) xor d( 19) xor d( 17) xor d( 16) xor d( 14) xor d( 12) xor d( 11) xor d( 10) xor d( 7) xor d( 5) xor d( 1) xor d( 0);
dq( 15) <= d( 63) xor d( 60) xor d( 58) xor d( 57) xor d( 56) xor d( 52) xor d( 50) xor d( 48) xor d( 47) xor d( 45) xor d( 43) xor d( 39) xor d( 38) xor d( 37) xor d( 36) xor d( 33) xor d( 29) xor d( 27) xor d( 20) xor d( 18) xor d( 17) xor d( 15) xor d( 13) xor d( 12) xor d( 11) xor d( 8) xor d( 6) xor d( 2) xor d( 1);
dq( 16) <= d( 62) xor d( 61) xor d( 59) xor d( 57) xor d( 56) xor d( 50) xor d( 49) xor d( 47) xor d( 45) xor d( 44) xor d( 43) xor d( 40) xor d( 39) xor d( 38) xor d( 35) xor d( 33) xor d( 30) xor d( 26) xor d( 23) xor d( 22) xor d( 17) xor d( 16) xor d( 12) xor d( 10) xor d( 9) xor d( 8) xor d( 7) xor d( 6) xor d( 5) xor d( 4) xor d( 3) xor d( 2) xor d( 0);
dq( 17) <= d( 63) xor d( 62) xor d( 60) xor d( 58) xor d( 57) xor d( 51) xor d( 50) xor d( 48) xor d( 46) xor d( 45) xor d( 44) xor d( 41) xor d( 40) xor d( 39) xor d( 36) xor d( 34) xor d( 31) xor d( 27) xor d( 24) xor d( 23) xor d( 18) xor d( 17) xor d( 13) xor d( 11) xor d( 10) xor d( 9) xor d( 8) xor d( 7) xor d( 6) xor d( 5) xor d( 4) xor d( 3) xor d( 1);
dq( 18) <= d( 63) xor d( 61) xor d( 59) xor d( 58) xor d( 52) xor d( 51) xor d( 49) xor d( 47) xor d( 46) xor d( 45) xor d( 42) xor d( 41) xor d( 40) xor d( 37) xor d( 35) xor d( 32) xor d( 28) xor d( 25) xor d( 24) xor d( 19) xor d( 18) xor d( 14) xor d( 12) xor d( 11) xor d( 10) xor d( 9) xor d( 8) xor d( 7) xor d( 6) xor d( 5) xor d( 4) xor d( 2);
dq( 19) <= d( 60) xor d( 59) xor d( 58) xor d( 56) xor d( 52) xor d( 51) xor d( 45) xor d( 42) xor d( 41) xor d( 38) xor d( 37) xor d( 36) xor d( 35) xor d( 34) xor d( 29) xor d( 28) xor d( 25) xor d( 23) xor d( 22) xor d( 21) xor d( 20) xor d( 18) xor d( 17) xor d( 15) xor d( 14) xor d( 12) xor d( 11) xor d( 9) xor d( 7) xor d( 4) xor d( 3) xor d( 0);
dq( 20) <= d( 62) xor d( 61) xor d( 60) xor d( 59) xor d( 58) xor d( 57) xor d( 56) xor d( 52) xor d( 51) xor d( 50) xor d( 48) xor d( 47) xor d( 45) xor d( 42) xor d( 39) xor d( 38) xor d( 36) xor d( 34) xor d( 33) xor d( 30) xor d( 29) xor d( 28) xor d( 24) xor d( 17) xor d( 16) xor d( 15) xor d( 14) xor d( 12) xor d( 6) xor d( 1) xor d( 0);
dq( 21) <= d( 63) xor d( 61) xor d( 60) xor d( 59) xor d( 57) xor d( 56) xor d( 52) xor d( 50) xor d( 49) xor d( 47) xor d( 45) xor d( 40) xor d( 39) xor d( 33) xor d( 31) xor d( 30) xor d( 29) xor d( 28) xor d( 26) xor d( 25) xor d( 23) xor d( 22) xor d( 21) xor d( 19) xor d( 16) xor d( 15) xor d( 14) xor d( 10) xor d( 8) xor d( 7) xor d( 6) xor d( 5) xor d( 4) xor d( 2) xor d( 1) xor d( 0);
dq( 22) <= d( 61) xor d( 60) xor d( 57) xor d( 56) xor d( 47) xor d( 45) xor d( 43) xor d( 41) xor d( 40) xor d( 37) xor d( 35) xor d( 33) xor d( 32) xor d( 31) xor d( 30) xor d( 29) xor d( 28) xor d( 27) xor d( 24) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 16) xor d( 15) xor d( 14) xor d( 13) xor d( 11) xor d( 10) xor d( 9) xor d( 7) xor d( 4) xor d( 3) xor d( 2) xor d( 1) xor d( 0);
dq( 23) <= d( 61) xor d( 57) xor d( 56) xor d( 53) xor d( 51) xor d( 50) xor d( 47) xor d( 45) xor d( 44) xor d( 43) xor d( 42) xor d( 41) xor d( 38) xor d( 37) xor d( 36) xor d( 35) xor d( 32) xor d( 31) xor d( 30) xor d( 29) xor d( 26) xor d( 25) xor d( 23) xor d( 20) xor d( 18) xor d( 16) xor d( 15) xor d( 13) xor d( 12) xor d( 11) xor d( 6) xor d( 3) xor d( 2) xor d( 1) xor d( 0);
dq( 24) <= d( 62) xor d( 58) xor d( 57) xor d( 54) xor d( 52) xor d( 51) xor d( 48) xor d( 46) xor d( 45) xor d( 44) xor d( 43) xor d( 42) xor d( 39) xor d( 38) xor d( 37) xor d( 36) xor d( 33) xor d( 32) xor d( 31) xor d( 30) xor d( 27) xor d( 26) xor d( 24) xor d( 21) xor d( 19) xor d( 17) xor d( 16) xor d( 14) xor d( 13) xor d( 12) xor d( 7) xor d( 4) xor d( 3) xor d( 2) xor d( 1);
dq( 25) <= d( 63) xor d( 59) xor d( 58) xor d( 55) xor d( 53) xor d( 52) xor d( 49) xor d( 47) xor d( 46) xor d( 45) xor d( 44) xor d( 43) xor d( 40) xor d( 39) xor d( 38) xor d( 37) xor d( 34) xor d( 33) xor d( 32) xor d( 31) xor d( 28) xor d( 27) xor d( 25) xor d( 22) xor d( 20) xor d( 18) xor d( 17) xor d( 15) xor d( 14) xor d( 13) xor d( 8) xor d( 5) xor d( 4) xor d( 3) xor d( 2);
dq( 26) <= d( 62) xor d( 60) xor d( 59) xor d( 58) xor d( 54) xor d( 51) xor d( 44) xor d( 43) xor d( 41) xor d( 40) xor d( 39) xor d( 38) xor d( 37) xor d( 32) xor d( 29) xor d( 22) xor d( 17) xor d( 16) xor d( 15) xor d( 13) xor d( 10) xor d( 9) xor d( 8) xor d( 3) xor d( 0);
dq( 27) <= d( 63) xor d( 61) xor d( 60) xor d( 59) xor d( 55) xor d( 52) xor d( 45) xor d( 44) xor d( 42) xor d( 41) xor d( 40) xor d( 39) xor d( 38) xor d( 33) xor d( 30) xor d( 23) xor d( 18) xor d( 17) xor d( 16) xor d( 14) xor d( 11) xor d( 10) xor d( 9) xor d( 4) xor d( 1);
dq( 28) <= d( 62) xor d( 61) xor d( 60) xor d( 56) xor d( 53) xor d( 46) xor d( 45) xor d( 43) xor d( 42) xor d( 41) xor d( 40) xor d( 39) xor d( 34) xor d( 31) xor d( 24) xor d( 19) xor d( 18) xor d( 17) xor d( 15) xor d( 12) xor d( 11) xor d( 10) xor d( 5) xor d( 2);
dq( 29) <= d( 63) xor d( 62) xor d( 61) xor d( 57) xor d( 54) xor d( 47) xor d( 46) xor d( 44) xor d( 43) xor d( 42) xor d( 41) xor d( 40) xor d( 35) xor d( 32) xor d( 25) xor d( 20) xor d( 19) xor d( 18) xor d( 16) xor d( 13) xor d( 12) xor d( 11) xor d( 6) xor d( 3);
dq( 30) <= d( 63) xor d( 62) xor d( 58) xor d( 55) xor d( 48) xor d( 47) xor d( 45) xor d( 44) xor d( 43) xor d( 42) xor d( 41) xor d( 36) xor d( 33) xor d( 26) xor d( 21) xor d( 20) xor d( 19) xor d( 17) xor d( 14) xor d( 13) xor d( 12) xor d( 7) xor d( 4);
dq( 31) <= d( 63) xor d( 59) xor d( 56) xor d( 49) xor d( 48) xor d( 46) xor d( 45) xor d( 44) xor d( 43) xor d( 42) xor d( 37) xor d( 34) xor d( 27) xor d( 22) xor d( 21) xor d( 20) xor d( 18) xor d( 15) xor d( 14) xor d( 13) xor d( 8) xor d( 5);
dq( 32) <= d( 62) xor d( 60) xor d( 58) xor d( 57) xor d( 56) xor d( 53) xor d( 51) xor d( 49) xor d( 48) xor d( 44) xor d( 38) xor d( 37) xor d( 34) xor d( 33) xor d( 26) xor d( 18) xor d( 17) xor d( 16) xor d( 15) xor d( 13) xor d( 10) xor d( 9) xor d( 8) xor d( 5) xor d( 4) xor d( 0);
dq( 33) <= d( 63) xor d( 61) xor d( 59) xor d( 58) xor d( 57) xor d( 54) xor d( 52) xor d( 50) xor d( 49) xor d( 45) xor d( 39) xor d( 38) xor d( 35) xor d( 34) xor d( 27) xor d( 19) xor d( 18) xor d( 17) xor d( 16) xor d( 14) xor d( 11) xor d( 10) xor d( 9) xor d( 6) xor d( 5) xor d( 1);
dq( 34) <= d( 60) xor d( 59) xor d( 56) xor d( 55) xor d( 48) xor d( 47) xor d( 45) xor d( 43) xor d( 40) xor d( 39) xor d( 37) xor d( 36) xor d( 34) xor d( 33) xor d( 26) xor d( 23) xor d( 22) xor d( 21) xor d( 20) xor d( 15) xor d( 14) xor d( 13) xor d( 12) xor d( 11) xor d( 8) xor d( 7) xor d( 5) xor d( 4) xor d( 2) xor d( 0);
dq( 35) <= d( 61) xor d( 60) xor d( 57) xor d( 56) xor d( 49) xor d( 48) xor d( 46) xor d( 44) xor d( 41) xor d( 40) xor d( 38) xor d( 37) xor d( 35) xor d( 34) xor d( 27) xor d( 24) xor d( 23) xor d( 22) xor d( 21) xor d( 16) xor d( 15) xor d( 14) xor d( 13) xor d( 12) xor d( 9) xor d( 8) xor d( 6) xor d( 5) xor d( 3) xor d( 1);
dq( 36) <= d( 61) xor d( 57) xor d( 56) xor d( 53) xor d( 51) xor d( 49) xor d( 48) xor d( 46) xor d( 43) xor d( 42) xor d( 41) xor d( 39) xor d( 38) xor d( 37) xor d( 36) xor d( 34) xor d( 33) xor d( 26) xor d( 25) xor d( 24) xor d( 21) xor d( 19) xor d( 18) xor d( 16) xor d( 15) xor d( 9) xor d( 8) xor d( 7) xor d( 5) xor d( 2) xor d( 0);
dq( 37) <= d( 57) xor d( 56) xor d( 54) xor d( 53) xor d( 52) xor d( 51) xor d( 49) xor d( 48) xor d( 46) xor d( 45) xor d( 44) xor d( 42) xor d( 40) xor d( 39) xor d( 38) xor d( 33) xor d( 28) xor d( 27) xor d( 25) xor d( 23) xor d( 21) xor d( 20) xor d( 18) xor d( 16) xor d( 14) xor d( 13) xor d( 9) xor d( 5) xor d( 4) xor d( 3) xor d( 1) xor d( 0);
dq( 38) <= d( 62) xor d( 57) xor d( 56) xor d( 55) xor d( 54) xor d( 52) xor d( 51) xor d( 49) xor d( 48) xor d( 41) xor d( 40) xor d( 39) xor d( 37) xor d( 35) xor d( 33) xor d( 29) xor d( 24) xor d( 23) xor d( 18) xor d( 15) xor d( 13) xor d( 8) xor d( 2) xor d( 1) xor d( 0);
dq( 39) <= d( 63) xor d( 58) xor d( 57) xor d( 56) xor d( 55) xor d( 53) xor d( 52) xor d( 50) xor d( 49) xor d( 42) xor d( 41) xor d( 40) xor d( 38) xor d( 36) xor d( 34) xor d( 30) xor d( 25) xor d( 24) xor d( 19) xor d( 16) xor d( 14) xor d( 9) xor d( 3) xor d( 2) xor d( 1);
dq( 40) <= d( 62) xor d( 59) xor d( 57) xor d( 54) xor d( 48) xor d( 47) xor d( 46) xor d( 45) xor d( 42) xor d( 41) xor d( 39) xor d( 34) xor d( 33) xor d( 31) xor d( 28) xor d( 25) xor d( 23) xor d( 22) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 15) xor d( 14) xor d( 13) xor d( 8) xor d( 6) xor d( 5) xor d( 3) xor d( 2) xor d( 0);
dq( 41) <= d( 63) xor d( 60) xor d( 58) xor d( 55) xor d( 49) xor d( 48) xor d( 47) xor d( 46) xor d( 43) xor d( 42) xor d( 40) xor d( 35) xor d( 34) xor d( 32) xor d( 29) xor d( 26) xor d( 24) xor d( 23) xor d( 22) xor d( 21) xor d( 20) xor d( 19) xor d( 16) xor d( 15) xor d( 14) xor d( 9) xor d( 7) xor d( 6) xor d( 4) xor d( 3) xor d( 1);
dq( 42) <= d( 62) xor d( 61) xor d( 59) xor d( 58) xor d( 53) xor d( 51) xor d( 49) xor d( 46) xor d( 45) xor d( 44) xor d( 41) xor d( 37) xor d( 36) xor d( 34) xor d( 30) xor d( 28) xor d( 27) xor d( 26) xor d( 25) xor d( 24) xor d( 20) xor d( 19) xor d( 18) xor d( 16) xor d( 15) xor d( 14) xor d( 13) xor d( 7) xor d( 6) xor d( 2) xor d( 0);
dq( 43) <= d( 63) xor d( 60) xor d( 59) xor d( 58) xor d( 56) xor d( 54) xor d( 53) xor d( 52) xor d( 51) xor d( 48) xor d( 43) xor d( 42) xor d( 38) xor d( 34) xor d( 33) xor d( 31) xor d( 29) xor d( 27) xor d( 25) xor d( 23) xor d( 22) xor d( 20) xor d( 18) xor d( 16) xor d( 15) xor d( 13) xor d( 10) xor d( 7) xor d( 6) xor d( 5) xor d( 4) xor d( 3) xor d( 1) xor d( 0);
dq( 44) <= d( 61) xor d( 60) xor d( 59) xor d( 57) xor d( 55) xor d( 54) xor d( 53) xor d( 52) xor d( 49) xor d( 44) xor d( 43) xor d( 39) xor d( 35) xor d( 34) xor d( 32) xor d( 30) xor d( 28) xor d( 26) xor d( 24) xor d( 23) xor d( 21) xor d( 19) xor d( 17) xor d( 16) xor d( 14) xor d( 11) xor d( 8) xor d( 7) xor d( 6) xor d( 5) xor d( 4) xor d( 2) xor d( 1);
dq( 45) <= d( 61) xor d( 60) xor d( 55) xor d( 54) xor d( 51) xor d( 48) xor d( 47) xor d( 46) xor d( 44) xor d( 43) xor d( 40) xor d( 37) xor d( 36) xor d( 34) xor d( 31) xor d( 29) xor d( 28) xor d( 27) xor d( 26) xor d( 25) xor d( 24) xor d( 23) xor d( 21) xor d( 20) xor d( 19) xor d( 15) xor d( 14) xor d( 13) xor d( 12) xor d( 10) xor d( 9) xor d( 7) xor d( 4) xor d( 3) xor d( 2) xor d( 0);
dq( 46) <= d( 61) xor d( 58) xor d( 55) xor d( 53) xor d( 52) xor d( 51) xor d( 50) xor d( 49) xor d( 46) xor d( 44) xor d( 43) xor d( 41) xor d( 38) xor d( 34) xor d( 33) xor d( 32) xor d( 30) xor d( 29) xor d( 27) xor d( 25) xor d( 24) xor d( 23) xor d( 20) xor d( 19) xor d( 18) xor d( 17) xor d( 16) xor d( 15) xor d( 11) xor d( 6) xor d( 3) xor d( 1) xor d( 0);
dq( 47) <= d( 62) xor d( 59) xor d( 56) xor d( 54) xor d( 53) xor d( 52) xor d( 51) xor d( 50) xor d( 47) xor d( 45) xor d( 44) xor d( 42) xor d( 39) xor d( 35) xor d( 34) xor d( 33) xor d( 31) xor d( 30) xor d( 28) xor d( 26) xor d( 25) xor d( 24) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 17) xor d( 16) xor d( 12) xor d( 7) xor d( 4) xor d( 2) xor d( 1);
dq( 48) <= d( 63) xor d( 60) xor d( 57) xor d( 55) xor d( 54) xor d( 53) xor d( 52) xor d( 51) xor d( 48) xor d( 46) xor d( 45) xor d( 43) xor d( 40) xor d( 36) xor d( 35) xor d( 34) xor d( 32) xor d( 31) xor d( 29) xor d( 27) xor d( 26) xor d( 25) xor d( 22) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 17) xor d( 13) xor d( 8) xor d( 5) xor d( 3) xor d( 2);
dq( 49) <= d( 61) xor d( 58) xor d( 56) xor d( 55) xor d( 54) xor d( 53) xor d( 52) xor d( 49) xor d( 47) xor d( 46) xor d( 44) xor d( 41) xor d( 37) xor d( 36) xor d( 35) xor d( 33) xor d( 32) xor d( 30) xor d( 28) xor d( 27) xor d( 26) xor d( 23) xor d( 22) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 14) xor d( 9) xor d( 6) xor d( 4) xor d( 3);
dq( 50) <= d( 59) xor d( 58) xor d( 57) xor d( 55) xor d( 54) xor d( 51) xor d( 46) xor d( 43) xor d( 42) xor d( 38) xor d( 36) xor d( 35) xor d( 31) xor d( 29) xor d( 27) xor d( 26) xor d( 24) xor d( 20) xor d( 18) xor d( 17) xor d( 15) xor d( 14) xor d( 13) xor d( 8) xor d( 7) xor d( 6) xor d( 0);
dq( 51) <= d( 62) xor d( 60) xor d( 59) xor d( 55) xor d( 53) xor d( 52) xor d( 51) xor d( 50) xor d( 48) xor d( 46) xor d( 45) xor d( 44) xor d( 39) xor d( 36) xor d( 35) xor d( 34) xor d( 33) xor d( 32) xor d( 30) xor d( 27) xor d( 26) xor d( 25) xor d( 23) xor d( 22) xor d( 17) xor d( 16) xor d( 15) xor d( 13) xor d( 10) xor d( 9) xor d( 7) xor d( 6) xor d( 5) xor d( 4) xor d( 1) xor d( 0);
dq( 52) <= d( 63) xor d( 62) xor d( 61) xor d( 60) xor d( 58) xor d( 54) xor d( 52) xor d( 50) xor d( 49) xor d( 48) xor d( 43) xor d( 40) xor d( 36) xor d( 31) xor d( 27) xor d( 24) xor d( 22) xor d( 21) xor d( 19) xor d( 16) xor d( 13) xor d( 11) xor d( 7) xor d( 4) xor d( 2) xor d( 1) xor d( 0);
dq( 53) <= d( 63) xor d( 61) xor d( 59) xor d( 58) xor d( 56) xor d( 55) xor d( 49) xor d( 48) xor d( 47) xor d( 46) xor d( 45) xor d( 44) xor d( 43) xor d( 41) xor d( 35) xor d( 34) xor d( 33) xor d( 32) xor d( 26) xor d( 25) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 13) xor d( 12) xor d( 10) xor d( 6) xor d( 4) xor d( 3) xor d( 2) xor d( 1) xor d( 0);
dq( 54) <= d( 60) xor d( 59) xor d( 58) xor d( 57) xor d( 53) xor d( 51) xor d( 49) xor d( 44) xor d( 43) xor d( 42) xor d( 37) xor d( 36) xor d( 28) xor d( 27) xor d( 23) xor d( 20) xor d( 18) xor d( 17) xor d( 11) xor d( 10) xor d( 8) xor d( 7) xor d( 6) xor d( 3) xor d( 2) xor d( 1) xor d( 0);
dq( 55) <= d( 62) xor d( 61) xor d( 60) xor d( 59) xor d( 56) xor d( 54) xor d( 53) xor d( 52) xor d( 51) xor d( 48) xor d( 47) xor d( 46) xor d( 44) xor d( 38) xor d( 35) xor d( 34) xor d( 33) xor d( 29) xor d( 26) xor d( 24) xor d( 23) xor d( 22) xor d( 17) xor d( 14) xor d( 13) xor d( 12) xor d( 11) xor d( 10) xor d( 9) xor d( 7) xor d( 6) xor d( 5) xor d( 3) xor d( 2) xor d( 1) xor d( 0);
dq( 56) <= d( 63) xor d( 61) xor d( 60) xor d( 58) xor d( 57) xor d( 56) xor d( 55) xor d( 54) xor d( 52) xor d( 51) xor d( 50) xor d( 49) xor d( 46) xor d( 43) xor d( 39) xor d( 37) xor d( 36) xor d( 33) xor d( 30) xor d( 28) xor d( 27) xor d( 26) xor d( 25) xor d( 24) xor d( 22) xor d( 21) xor d( 19) xor d( 17) xor d( 15) xor d( 12) xor d( 11) xor d( 7) xor d( 5) xor d( 3) xor d( 2) xor d( 1) xor d( 0);
dq( 57) <= d( 62) xor d( 61) xor d( 59) xor d( 58) xor d( 57) xor d( 56) xor d( 55) xor d( 53) xor d( 52) xor d( 51) xor d( 50) xor d( 47) xor d( 44) xor d( 40) xor d( 38) xor d( 37) xor d( 34) xor d( 31) xor d( 29) xor d( 28) xor d( 27) xor d( 26) xor d( 25) xor d( 23) xor d( 22) xor d( 20) xor d( 18) xor d( 16) xor d( 13) xor d( 12) xor d( 8) xor d( 6) xor d( 4) xor d( 3) xor d( 2) xor d( 1);
dq( 58) <= d( 63) xor d( 62) xor d( 60) xor d( 59) xor d( 58) xor d( 57) xor d( 56) xor d( 54) xor d( 53) xor d( 52) xor d( 51) xor d( 48) xor d( 45) xor d( 41) xor d( 39) xor d( 38) xor d( 35) xor d( 32) xor d( 30) xor d( 29) xor d( 28) xor d( 27) xor d( 26) xor d( 24) xor d( 23) xor d( 21) xor d( 19) xor d( 17) xor d( 14) xor d( 13) xor d( 9) xor d( 7) xor d( 5) xor d( 4) xor d( 3) xor d( 2);
dq( 59) <= d( 63) xor d( 62) xor d( 61) xor d( 60) xor d( 59) xor d( 57) xor d( 56) xor d( 55) xor d( 54) xor d( 52) xor d( 51) xor d( 50) xor d( 49) xor d( 48) xor d( 47) xor d( 45) xor d( 43) xor d( 42) xor d( 40) xor d( 39) xor d( 37) xor d( 36) xor d( 35) xor d( 34) xor d( 31) xor d( 30) xor d( 29) xor d( 27) xor d( 26) xor d( 25) xor d( 24) xor d( 23) xor d( 21) xor d( 20) xor d( 19) xor d( 17) xor d( 15) xor d( 13) xor d( 3) xor d( 0);
dq( 60) <= d( 63) xor d( 61) xor d( 60) xor d( 57) xor d( 55) xor d( 52) xor d( 49) xor d( 47) xor d( 45) xor d( 44) xor d( 41) xor d( 40) xor d( 38) xor d( 36) xor d( 34) xor d( 33) xor d( 32) xor d( 31) xor d( 30) xor d( 27) xor d( 25) xor d( 24) xor d( 23) xor d( 20) xor d( 19) xor d( 17) xor d( 16) xor d( 13) xor d( 10) xor d( 8) xor d( 6) xor d( 5) xor d( 1) xor d( 0);
dq( 61) <= d( 62) xor d( 61) xor d( 58) xor d( 56) xor d( 53) xor d( 50) xor d( 48) xor d( 46) xor d( 45) xor d( 42) xor d( 41) xor d( 39) xor d( 37) xor d( 35) xor d( 34) xor d( 33) xor d( 32) xor d( 31) xor d( 28) xor d( 26) xor d( 25) xor d( 24) xor d( 21) xor d( 20) xor d( 18) xor d( 17) xor d( 14) xor d( 11) xor d( 9) xor d( 7) xor d( 6) xor d( 2) xor d( 1);
dq( 62) <= d( 63) xor d( 62) xor d( 59) xor d( 57) xor d( 54) xor d( 51) xor d( 49) xor d( 47) xor d( 46) xor d( 43) xor d( 42) xor d( 40) xor d( 38) xor d( 36) xor d( 35) xor d( 34) xor d( 33) xor d( 32) xor d( 29) xor d( 27) xor d( 26) xor d( 25) xor d( 22) xor d( 21) xor d( 19) xor d( 18) xor d( 15) xor d( 12) xor d( 10) xor d( 8) xor d( 7) xor d( 3) xor d( 2);
dq( 63) <= d( 63) xor d( 60) xor d( 58) xor d( 55) xor d( 52) xor d( 50) xor d( 48) xor d( 47) xor d( 44) xor d( 43) xor d( 41) xor d( 39) xor d( 37) xor d( 36) xor d( 35) xor d( 34) xor d( 33) xor d( 30) xor d( 28) xor d( 27) xor d( 26) xor d( 23) xor d( 22) xor d( 20) xor d( 19) xor d( 16) xor d( 13) xor d( 11) xor d( 9) xor d( 8) xor d( 4) xor d( 3);
dq( 64) <= d( 62) xor d( 61) xor d( 59) xor d( 58) xor d( 50) xor d( 49) xor d( 47) xor d( 46) xor d( 44) xor d( 43) xor d( 42) xor d( 40) xor d( 38) xor d( 36) xor d( 33) xor d( 31) xor d( 29) xor d( 27) xor d( 26) xor d( 24) xor d( 22) xor d( 20) xor d( 19) xor d( 18) xor d( 13) xor d( 12) xor d( 9) xor d( 8) xor d( 6) xor d( 0);
dq( 65) <= d( 63) xor d( 62) xor d( 60) xor d( 59) xor d( 51) xor d( 50) xor d( 48) xor d( 47) xor d( 45) xor d( 44) xor d( 43) xor d( 41) xor d( 39) xor d( 37) xor d( 34) xor d( 32) xor d( 30) xor d( 28) xor d( 27) xor d( 25) xor d( 23) xor d( 21) xor d( 20) xor d( 19) xor d( 14) xor d( 13) xor d( 10) xor d( 9) xor d( 7) xor d( 1);
dq( 66) <= d( 63) xor d( 62) xor d( 61) xor d( 60) xor d( 58) xor d( 56) xor d( 53) xor d( 52) xor d( 50) xor d( 49) xor d( 47) xor d( 44) xor d( 43) xor d( 42) xor d( 40) xor d( 38) xor d( 37) xor d( 34) xor d( 31) xor d( 29) xor d( 24) xor d( 23) xor d( 20) xor d( 19) xor d( 18) xor d( 17) xor d( 15) xor d( 13) xor d( 11) xor d( 6) xor d( 5) xor d( 4) xor d( 2) xor d( 0);
dq( 67) <= d( 63) xor d( 61) xor d( 59) xor d( 58) xor d( 57) xor d( 56) xor d( 54) xor d( 47) xor d( 46) xor d( 44) xor d( 41) xor d( 39) xor d( 38) xor d( 37) xor d( 34) xor d( 33) xor d( 32) xor d( 30) xor d( 28) xor d( 26) xor d( 25) xor d( 24) xor d( 23) xor d( 22) xor d( 20) xor d( 17) xor d( 16) xor d( 13) xor d( 12) xor d( 10) xor d( 8) xor d( 7) xor d( 4) xor d( 3) xor d( 1) xor d( 0);
dq( 68) <= d( 60) xor d( 59) xor d( 57) xor d( 56) xor d( 55) xor d( 53) xor d( 51) xor d( 50) xor d( 46) xor d( 43) xor d( 42) xor d( 40) xor d( 39) xor d( 38) xor d( 37) xor d( 31) xor d( 29) xor d( 28) xor d( 27) xor d( 25) xor d( 24) xor d( 22) xor d( 19) xor d( 11) xor d( 10) xor d( 9) xor d( 6) xor d( 2) xor d( 1) xor d( 0);
dq( 69) <= d( 62) xor d( 61) xor d( 60) xor d( 57) xor d( 54) xor d( 53) xor d( 52) xor d( 50) xor d( 48) xor d( 46) xor d( 45) xor d( 44) xor d( 41) xor d( 40) xor d( 39) xor d( 38) xor d( 37) xor d( 35) xor d( 34) xor d( 33) xor d( 32) xor d( 30) xor d( 29) xor d( 25) xor d( 22) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 17) xor d( 14) xor d( 13) xor d( 12) xor d( 11) xor d( 8) xor d( 7) xor d( 6) xor d( 5) xor d( 4) xor d( 3) xor d( 2) xor d( 1) xor d( 0);
dq( 70) <= d( 63) xor d( 62) xor d( 61) xor d( 58) xor d( 55) xor d( 54) xor d( 53) xor d( 51) xor d( 49) xor d( 47) xor d( 46) xor d( 45) xor d( 42) xor d( 41) xor d( 40) xor d( 39) xor d( 38) xor d( 36) xor d( 35) xor d( 34) xor d( 33) xor d( 31) xor d( 30) xor d( 26) xor d( 23) xor d( 22) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 15) xor d( 14) xor d( 13) xor d( 12) xor d( 9) xor d( 8) xor d( 7) xor d( 6) xor d( 5) xor d( 4) xor d( 3) xor d( 2) xor d( 1);
dq( 71) <= d( 63) xor d( 59) xor d( 58) xor d( 55) xor d( 54) xor d( 53) xor d( 52) xor d( 51) xor d( 45) xor d( 42) xor d( 41) xor d( 40) xor d( 39) xor d( 36) xor d( 33) xor d( 32) xor d( 31) xor d( 28) xor d( 27) xor d( 26) xor d( 24) xor d( 20) xor d( 18) xor d( 17) xor d( 16) xor d( 15) xor d( 9) xor d( 7) xor d( 3) xor d( 2) xor d( 0);
dq( 72) <= d( 62) xor d( 60) xor d( 59) xor d( 58) xor d( 55) xor d( 54) xor d( 52) xor d( 51) xor d( 50) xor d( 48) xor d( 47) xor d( 45) xor d( 42) xor d( 41) xor d( 40) xor d( 35) xor d( 32) xor d( 29) xor d( 27) xor d( 26) xor d( 25) xor d( 23) xor d( 22) xor d( 16) xor d( 14) xor d( 13) xor d( 6) xor d( 5) xor d( 3) xor d( 1) xor d( 0);
dq( 73) <= d( 63) xor d( 62) xor d( 61) xor d( 60) xor d( 59) xor d( 58) xor d( 55) xor d( 52) xor d( 50) xor d( 49) xor d( 47) xor d( 45) xor d( 42) xor d( 41) xor d( 37) xor d( 36) xor d( 35) xor d( 34) xor d( 30) xor d( 27) xor d( 24) xor d( 22) xor d( 21) xor d( 19) xor d( 18) xor d( 15) xor d( 13) xor d( 10) xor d( 8) xor d( 7) xor d( 5) xor d( 2) xor d( 1) xor d( 0);
dq( 74) <= d( 63) xor d( 61) xor d( 60) xor d( 59) xor d( 58) xor d( 47) xor d( 45) xor d( 42) xor d( 38) xor d( 36) xor d( 34) xor d( 33) xor d( 31) xor d( 26) xor d( 25) xor d( 21) xor d( 20) xor d( 18) xor d( 17) xor d( 16) xor d( 13) xor d( 11) xor d( 10) xor d( 9) xor d( 5) xor d( 4) xor d( 3) xor d( 2) xor d( 1) xor d( 0);
dq( 75) <= d( 62) xor d( 61) xor d( 60) xor d( 59) xor d( 48) xor d( 46) xor d( 43) xor d( 39) xor d( 37) xor d( 35) xor d( 34) xor d( 32) xor d( 27) xor d( 26) xor d( 22) xor d( 21) xor d( 19) xor d( 18) xor d( 17) xor d( 14) xor d( 12) xor d( 11) xor d( 10) xor d( 6) xor d( 5) xor d( 4) xor d( 3) xor d( 2) xor d( 1);
dq( 76) <= d( 63) xor d( 61) xor d( 60) xor d( 58) xor d( 56) xor d( 53) xor d( 51) xor d( 50) xor d( 49) xor d( 48) xor d( 46) xor d( 45) xor d( 44) xor d( 43) xor d( 40) xor d( 38) xor d( 37) xor d( 36) xor d( 34) xor d( 27) xor d( 26) xor d( 21) xor d( 20) xor d( 17) xor d( 15) xor d( 14) xor d( 12) xor d( 11) xor d( 10) xor d( 8) xor d( 7) xor d( 3) xor d( 2) xor d( 0);
dq( 77) <= d( 62) xor d( 61) xor d( 59) xor d( 57) xor d( 54) xor d( 52) xor d( 51) xor d( 50) xor d( 49) xor d( 47) xor d( 46) xor d( 45) xor d( 44) xor d( 41) xor d( 39) xor d( 38) xor d( 37) xor d( 35) xor d( 28) xor d( 27) xor d( 22) xor d( 21) xor d( 18) xor d( 16) xor d( 15) xor d( 13) xor d( 12) xor d( 11) xor d( 9) xor d( 8) xor d( 4) xor d( 3) xor d( 1);
dq( 78) <= d( 63) xor d( 62) xor d( 60) xor d( 58) xor d( 55) xor d( 53) xor d( 52) xor d( 51) xor d( 50) xor d( 48) xor d( 47) xor d( 46) xor d( 45) xor d( 42) xor d( 40) xor d( 39) xor d( 38) xor d( 36) xor d( 29) xor d( 28) xor d( 23) xor d( 22) xor d( 19) xor d( 17) xor d( 16) xor d( 14) xor d( 13) xor d( 12) xor d( 10) xor d( 9) xor d( 5) xor d( 4) xor d( 2);
dq( 79) <= d( 63) xor d( 62) xor d( 61) xor d( 59) xor d( 58) xor d( 54) xor d( 52) xor d( 50) xor d( 49) xor d( 45) xor d( 41) xor d( 40) xor d( 39) xor d( 35) xor d( 34) xor d( 33) xor d( 30) xor d( 29) xor d( 28) xor d( 26) xor d( 24) xor d( 22) xor d( 21) xor d( 20) xor d( 19) xor d( 15) xor d( 11) xor d( 8) xor d( 4) xor d( 3) xor d( 0);
dq( 80) <= d( 63) xor d( 60) xor d( 59) xor d( 58) xor d( 56) xor d( 55) xor d( 48) xor d( 47) xor d( 45) xor d( 43) xor d( 42) xor d( 41) xor d( 40) xor d( 37) xor d( 36) xor d( 33) xor d( 31) xor d( 30) xor d( 29) xor d( 28) xor d( 27) xor d( 26) xor d( 25) xor d( 20) xor d( 19) xor d( 18) xor d( 17) xor d( 16) xor d( 14) xor d( 13) xor d( 12) xor d( 10) xor d( 9) xor d( 8) xor d( 6) xor d( 1) xor d( 0);
dq( 81) <= d( 62) xor d( 61) xor d( 60) xor d( 59) xor d( 58) xor d( 57) xor d( 53) xor d( 51) xor d( 50) xor d( 49) xor d( 47) xor d( 45) xor d( 44) xor d( 42) xor d( 41) xor d( 38) xor d( 35) xor d( 33) xor d( 32) xor d( 31) xor d( 30) xor d( 29) xor d( 27) xor d( 23) xor d( 22) xor d( 20) xor d( 15) xor d( 11) xor d( 9) xor d( 8) xor d( 7) xor d( 6) xor d( 5) xor d( 4) xor d( 2) xor d( 1) xor d( 0);
dq( 82) <= d( 63) xor d( 61) xor d( 60) xor d( 59) xor d( 56) xor d( 54) xor d( 53) xor d( 52) xor d( 47) xor d( 42) xor d( 39) xor d( 37) xor d( 36) xor d( 35) xor d( 32) xor d( 31) xor d( 30) xor d( 26) xor d( 24) xor d( 22) xor d( 19) xor d( 18) xor d( 17) xor d( 16) xor d( 14) xor d( 13) xor d( 12) xor d( 9) xor d( 7) xor d( 4) xor d( 3) xor d( 2) xor d( 1) xor d( 0);
dq( 83) <= d( 62) xor d( 61) xor d( 60) xor d( 57) xor d( 55) xor d( 54) xor d( 53) xor d( 48) xor d( 43) xor d( 40) xor d( 38) xor d( 37) xor d( 36) xor d( 33) xor d( 32) xor d( 31) xor d( 27) xor d( 25) xor d( 23) xor d( 20) xor d( 19) xor d( 18) xor d( 17) xor d( 15) xor d( 14) xor d( 13) xor d( 10) xor d( 8) xor d( 5) xor d( 4) xor d( 3) xor d( 2) xor d( 1);
dq( 84) <= d( 63) xor d( 62) xor d( 61) xor d( 58) xor d( 56) xor d( 55) xor d( 54) xor d( 49) xor d( 44) xor d( 41) xor d( 39) xor d( 38) xor d( 37) xor d( 34) xor d( 33) xor d( 32) xor d( 28) xor d( 26) xor d( 24) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 16) xor d( 15) xor d( 14) xor d( 11) xor d( 9) xor d( 6) xor d( 5) xor d( 4) xor d( 3) xor d( 2);
dq( 85) <= d( 63) xor d( 59) xor d( 58) xor d( 57) xor d( 55) xor d( 53) xor d( 51) xor d( 48) xor d( 47) xor d( 46) xor d( 43) xor d( 42) xor d( 40) xor d( 39) xor d( 38) xor d( 37) xor d( 29) xor d( 28) xor d( 27) xor d( 26) xor d( 25) xor d( 23) xor d( 20) xor d( 18) xor d( 16) xor d( 15) xor d( 14) xor d( 13) xor d( 12) xor d( 8) xor d( 7) xor d( 3) xor d( 0);
dq( 86) <= d( 60) xor d( 59) xor d( 58) xor d( 56) xor d( 54) xor d( 52) xor d( 49) xor d( 48) xor d( 47) xor d( 44) xor d( 43) xor d( 41) xor d( 40) xor d( 39) xor d( 38) xor d( 30) xor d( 29) xor d( 28) xor d( 27) xor d( 26) xor d( 24) xor d( 21) xor d( 19) xor d( 17) xor d( 16) xor d( 15) xor d( 14) xor d( 13) xor d( 9) xor d( 8) xor d( 4) xor d( 1);
dq( 87) <= d( 61) xor d( 60) xor d( 59) xor d( 57) xor d( 55) xor d( 53) xor d( 50) xor d( 49) xor d( 48) xor d( 45) xor d( 44) xor d( 42) xor d( 41) xor d( 40) xor d( 39) xor d( 31) xor d( 30) xor d( 29) xor d( 28) xor d( 27) xor d( 25) xor d( 22) xor d( 20) xor d( 18) xor d( 17) xor d( 16) xor d( 15) xor d( 14) xor d( 10) xor d( 9) xor d( 5) xor d( 2);
dq( 88) <= d( 61) xor d( 60) xor d( 54) xor d( 53) xor d( 49) xor d( 48) xor d( 47) xor d( 42) xor d( 41) xor d( 40) xor d( 37) xor d( 35) xor d( 34) xor d( 33) xor d( 32) xor d( 31) xor d( 30) xor d( 29) xor d( 22) xor d( 16) xor d( 15) xor d( 14) xor d( 13) xor d( 11) xor d( 8) xor d( 5) xor d( 4) xor d( 3) xor d( 0);
dq( 89) <= d( 62) xor d( 61) xor d( 55) xor d( 54) xor d( 50) xor d( 49) xor d( 48) xor d( 43) xor d( 42) xor d( 41) xor d( 38) xor d( 36) xor d( 35) xor d( 34) xor d( 33) xor d( 32) xor d( 31) xor d( 30) xor d( 23) xor d( 17) xor d( 16) xor d( 15) xor d( 14) xor d( 12) xor d( 9) xor d( 6) xor d( 5) xor d( 4) xor d( 1);
dq( 90) <= d( 63) xor d( 62) xor d( 56) xor d( 55) xor d( 51) xor d( 50) xor d( 49) xor d( 44) xor d( 43) xor d( 42) xor d( 39) xor d( 37) xor d( 36) xor d( 35) xor d( 34) xor d( 33) xor d( 32) xor d( 31) xor d( 24) xor d( 18) xor d( 17) xor d( 16) xor d( 15) xor d( 13) xor d( 10) xor d( 7) xor d( 6) xor d( 5) xor d( 2);
dq( 91) <= d( 63) xor d( 57) xor d( 56) xor d( 52) xor d( 51) xor d( 50) xor d( 45) xor d( 44) xor d( 43) xor d( 40) xor d( 38) xor d( 37) xor d( 36) xor d( 35) xor d( 34) xor d( 33) xor d( 32) xor d( 25) xor d( 19) xor d( 18) xor d( 17) xor d( 16) xor d( 14) xor d( 11) xor d( 8) xor d( 7) xor d( 6) xor d( 3);
dq( 92) <= d( 62) xor d( 57) xor d( 56) xor d( 52) xor d( 50) xor d( 48) xor d( 47) xor d( 44) xor d( 43) xor d( 41) xor d( 39) xor d( 38) xor d( 36) xor d( 28) xor d( 23) xor d( 22) xor d( 21) xor d( 20) xor d( 15) xor d( 14) xor d( 13) xor d( 12) xor d( 10) xor d( 9) xor d( 7) xor d( 6) xor d( 5) xor d( 0);
dq( 93) <= d( 63) xor d( 62) xor d( 57) xor d( 56) xor d( 50) xor d( 49) xor d( 47) xor d( 46) xor d( 44) xor d( 43) xor d( 42) xor d( 40) xor d( 39) xor d( 35) xor d( 34) xor d( 33) xor d( 29) xor d( 28) xor d( 26) xor d( 24) xor d( 19) xor d( 18) xor d( 17) xor d( 16) xor d( 15) xor d( 11) xor d( 7) xor d( 5) xor d( 4) xor d( 1) xor d( 0);
dq( 94) <= d( 63) xor d( 62) xor d( 57) xor d( 56) xor d( 53) xor d( 46) xor d( 44) xor d( 41) xor d( 40) xor d( 37) xor d( 36) xor d( 33) xor d( 30) xor d( 29) xor d( 28) xor d( 27) xor d( 26) xor d( 25) xor d( 23) xor d( 22) xor d( 21) xor d( 20) xor d( 16) xor d( 14) xor d( 13) xor d( 12) xor d( 10) xor d( 4) xor d( 2) xor d( 1) xor d( 0);
dq( 95) <= d( 63) xor d( 58) xor d( 57) xor d( 54) xor d( 47) xor d( 45) xor d( 42) xor d( 41) xor d( 38) xor d( 37) xor d( 34) xor d( 31) xor d( 30) xor d( 29) xor d( 28) xor d( 27) xor d( 26) xor d( 24) xor d( 23) xor d( 22) xor d( 21) xor d( 17) xor d( 15) xor d( 14) xor d( 13) xor d( 11) xor d( 5) xor d( 3) xor d( 2) xor d( 1);
dq( 96) <= d( 62) xor d( 59) xor d( 56) xor d( 55) xor d( 53) xor d( 51) xor d( 50) xor d( 47) xor d( 45) xor d( 42) xor d( 39) xor d( 38) xor d( 37) xor d( 34) xor d( 33) xor d( 32) xor d( 31) xor d( 30) xor d( 29) xor d( 27) xor d( 26) xor d( 25) xor d( 24) xor d( 21) xor d( 19) xor d( 17) xor d( 16) xor d( 15) xor d( 13) xor d( 12) xor d( 10) xor d( 8) xor d( 5) xor d( 3) xor d( 2) xor d( 0);
dq( 97) <= d( 63) xor d( 62) xor d( 60) xor d( 58) xor d( 57) xor d( 54) xor d( 53) xor d( 52) xor d( 50) xor d( 47) xor d( 45) xor d( 40) xor d( 39) xor d( 38) xor d( 37) xor d( 32) xor d( 31) xor d( 30) xor d( 27) xor d( 25) xor d( 23) xor d( 21) xor d( 20) xor d( 19) xor d( 16) xor d( 11) xor d( 10) xor d( 9) xor d( 8) xor d( 5) xor d( 3) xor d( 1) xor d( 0);
dq( 98) <= d( 63) xor d( 62) xor d( 61) xor d( 59) xor d( 56) xor d( 55) xor d( 54) xor d( 50) xor d( 47) xor d( 45) xor d( 43) xor d( 41) xor d( 40) xor d( 39) xor d( 38) xor d( 37) xor d( 35) xor d( 34) xor d( 32) xor d( 31) xor d( 24) xor d( 23) xor d( 20) xor d( 19) xor d( 18) xor d( 14) xor d( 13) xor d( 12) xor d( 11) xor d( 9) xor d( 8) xor d( 5) xor d( 2) xor d( 1) xor d( 0);
dq( 99) <= d( 63) xor d( 60) xor d( 58) xor d( 57) xor d( 55) xor d( 53) xor d( 50) xor d( 47) xor d( 45) xor d( 44) xor d( 43) xor d( 42) xor d( 41) xor d( 40) xor d( 39) xor d( 38) xor d( 37) xor d( 36) xor d( 34) xor d( 32) xor d( 28) xor d( 26) xor d( 25) xor d( 24) xor d( 23) xor d( 22) xor d( 20) xor d( 18) xor d( 17) xor d( 15) xor d( 12) xor d( 9) xor d( 8) xor d( 5) xor d( 4) xor d( 3) xor d( 2) xor d( 1) xor d( 0);
dq(100) <= d( 62) xor d( 61) xor d( 59) xor d( 54) xor d( 53) xor d( 50) xor d( 47) xor d( 44) xor d( 42) xor d( 41) xor d( 40) xor d( 39) xor d( 38) xor d( 34) xor d( 29) xor d( 28) xor d( 27) xor d( 25) xor d( 24) xor d( 22) xor d( 17) xor d( 16) xor d( 14) xor d( 9) xor d( 8) xor d( 3) xor d( 2) xor d( 1) xor d( 0);
dq(101) <= d( 63) xor d( 62) xor d( 60) xor d( 55) xor d( 54) xor d( 51) xor d( 48) xor d( 45) xor d( 43) xor d( 42) xor d( 41) xor d( 40) xor d( 39) xor d( 35) xor d( 30) xor d( 29) xor d( 28) xor d( 26) xor d( 25) xor d( 23) xor d( 18) xor d( 17) xor d( 15) xor d( 10) xor d( 9) xor d( 4) xor d( 3) xor d( 2) xor d( 1);
dq(102) <= d( 63) xor d( 62) xor d( 61) xor d( 58) xor d( 55) xor d( 53) xor d( 52) xor d( 51) xor d( 50) xor d( 49) xor d( 48) xor d( 47) xor d( 45) xor d( 44) xor d( 42) xor d( 41) xor d( 40) xor d( 37) xor d( 36) xor d( 35) xor d( 34) xor d( 33) xor d( 31) xor d( 30) xor d( 29) xor d( 28) xor d( 27) xor d( 24) xor d( 23) xor d( 22) xor d( 21) xor d( 17) xor d( 16) xor d( 14) xor d( 13) xor d( 11) xor d( 8) xor d( 6) xor d( 3) xor d( 2) xor d( 0);
dq(103) <= d( 63) xor d( 62) xor d( 59) xor d( 56) xor d( 54) xor d( 53) xor d( 52) xor d( 51) xor d( 50) xor d( 49) xor d( 48) xor d( 46) xor d( 45) xor d( 43) xor d( 42) xor d( 41) xor d( 38) xor d( 37) xor d( 36) xor d( 35) xor d( 34) xor d( 32) xor d( 31) xor d( 30) xor d( 29) xor d( 28) xor d( 25) xor d( 24) xor d( 23) xor d( 22) xor d( 18) xor d( 17) xor d( 15) xor d( 14) xor d( 12) xor d( 9) xor d( 7) xor d( 4) xor d( 3) xor d( 1);
dq(104) <= d( 63) xor d( 62) xor d( 60) xor d( 58) xor d( 57) xor d( 56) xor d( 55) xor d( 54) xor d( 52) xor d( 49) xor d( 48) xor d( 45) xor d( 44) xor d( 42) xor d( 39) xor d( 38) xor d( 36) xor d( 34) xor d( 32) xor d( 31) xor d( 30) xor d( 29) xor d( 28) xor d( 25) xor d( 24) xor d( 22) xor d( 21) xor d( 17) xor d( 16) xor d( 15) xor d( 14) xor d( 6) xor d( 2) xor d( 0);
dq(105) <= d( 63) xor d( 61) xor d( 59) xor d( 58) xor d( 57) xor d( 56) xor d( 55) xor d( 53) xor d( 50) xor d( 49) xor d( 46) xor d( 45) xor d( 43) xor d( 40) xor d( 39) xor d( 37) xor d( 35) xor d( 33) xor d( 32) xor d( 31) xor d( 30) xor d( 29) xor d( 26) xor d( 25) xor d( 23) xor d( 22) xor d( 18) xor d( 17) xor d( 16) xor d( 15) xor d( 7) xor d( 3) xor d( 1);
dq(106) <= d( 60) xor d( 59) xor d( 57) xor d( 54) xor d( 53) xor d( 48) xor d( 45) xor d( 44) xor d( 43) xor d( 41) xor d( 40) xor d( 38) xor d( 37) xor d( 36) xor d( 35) xor d( 32) xor d( 31) xor d( 30) xor d( 28) xor d( 27) xor d( 24) xor d( 22) xor d( 21) xor d( 16) xor d( 14) xor d( 13) xor d( 10) xor d( 6) xor d( 5) xor d( 2) xor d( 0);
dq(107) <= d( 61) xor d( 60) xor d( 58) xor d( 55) xor d( 54) xor d( 49) xor d( 46) xor d( 45) xor d( 44) xor d( 42) xor d( 41) xor d( 39) xor d( 38) xor d( 37) xor d( 36) xor d( 33) xor d( 32) xor d( 31) xor d( 29) xor d( 28) xor d( 25) xor d( 23) xor d( 22) xor d( 17) xor d( 15) xor d( 14) xor d( 11) xor d( 7) xor d( 6) xor d( 3) xor d( 1);
dq(108) <= d( 62) xor d( 61) xor d( 59) xor d( 56) xor d( 55) xor d( 50) xor d( 47) xor d( 46) xor d( 45) xor d( 43) xor d( 42) xor d( 40) xor d( 39) xor d( 38) xor d( 37) xor d( 34) xor d( 33) xor d( 32) xor d( 30) xor d( 29) xor d( 26) xor d( 24) xor d( 23) xor d( 18) xor d( 16) xor d( 15) xor d( 12) xor d( 8) xor d( 7) xor d( 4) xor d( 2);
dq(109) <= d( 63) xor d( 60) xor d( 58) xor d( 57) xor d( 53) xor d( 50) xor d( 45) xor d( 44) xor d( 41) xor d( 40) xor d( 39) xor d( 38) xor d( 37) xor d( 31) xor d( 30) xor d( 28) xor d( 27) xor d( 26) xor d( 25) xor d( 24) xor d( 23) xor d( 22) xor d( 21) xor d( 18) xor d( 16) xor d( 14) xor d( 10) xor d( 9) xor d( 6) xor d( 4) xor d( 3) xor d( 0);
dq(110) <= d( 61) xor d( 59) xor d( 58) xor d( 54) xor d( 51) xor d( 46) xor d( 45) xor d( 42) xor d( 41) xor d( 40) xor d( 39) xor d( 38) xor d( 32) xor d( 31) xor d( 29) xor d( 28) xor d( 27) xor d( 26) xor d( 25) xor d( 24) xor d( 23) xor d( 22) xor d( 19) xor d( 17) xor d( 15) xor d( 11) xor d( 10) xor d( 7) xor d( 5) xor d( 4) xor d( 1);
dq(111) <= d( 62) xor d( 60) xor d( 59) xor d( 55) xor d( 52) xor d( 47) xor d( 46) xor d( 43) xor d( 42) xor d( 41) xor d( 40) xor d( 39) xor d( 33) xor d( 32) xor d( 30) xor d( 29) xor d( 28) xor d( 27) xor d( 26) xor d( 25) xor d( 24) xor d( 23) xor d( 20) xor d( 18) xor d( 16) xor d( 12) xor d( 11) xor d( 8) xor d( 6) xor d( 5) xor d( 2);
dq(112) <= d( 63) xor d( 62) xor d( 61) xor d( 60) xor d( 58) xor d( 51) xor d( 50) xor d( 46) xor d( 45) xor d( 44) xor d( 42) xor d( 41) xor d( 40) xor d( 37) xor d( 35) xor d( 31) xor d( 30) xor d( 29) xor d( 27) xor d( 25) xor d( 24) xor d( 23) xor d( 22) xor d( 18) xor d( 14) xor d( 12) xor d( 10) xor d( 9) xor d( 8) xor d( 7) xor d( 5) xor d( 4) xor d( 3) xor d( 0);
dq(113) <= d( 63) xor d( 61) xor d( 59) xor d( 58) xor d( 56) xor d( 53) xor d( 52) xor d( 50) xor d( 48) xor d( 42) xor d( 41) xor d( 38) xor d( 37) xor d( 36) xor d( 35) xor d( 34) xor d( 33) xor d( 32) xor d( 31) xor d( 30) xor d( 25) xor d( 24) xor d( 22) xor d( 21) xor d( 18) xor d( 17) xor d( 15) xor d( 14) xor d( 11) xor d( 9) xor d( 1) xor d( 0);
dq(114) <= d( 60) xor d( 59) xor d( 58) xor d( 57) xor d( 56) xor d( 54) xor d( 50) xor d( 49) xor d( 48) xor d( 47) xor d( 46) xor d( 45) xor d( 42) xor d( 39) xor d( 38) xor d( 36) xor d( 32) xor d( 31) xor d( 28) xor d( 25) xor d( 21) xor d( 17) xor d( 16) xor d( 15) xor d( 14) xor d( 13) xor d( 12) xor d( 8) xor d( 6) xor d( 5) xor d( 4) xor d( 2) xor d( 1) xor d( 0);
dq(115) <= d( 61) xor d( 60) xor d( 59) xor d( 58) xor d( 57) xor d( 55) xor d( 51) xor d( 50) xor d( 49) xor d( 48) xor d( 47) xor d( 46) xor d( 43) xor d( 40) xor d( 39) xor d( 37) xor d( 33) xor d( 32) xor d( 29) xor d( 26) xor d( 22) xor d( 18) xor d( 17) xor d( 16) xor d( 15) xor d( 14) xor d( 13) xor d( 9) xor d( 7) xor d( 6) xor d( 5) xor d( 3) xor d( 2) xor d( 1);
dq(116) <= d( 62) xor d( 61) xor d( 60) xor d( 59) xor d( 58) xor d( 56) xor d( 52) xor d( 51) xor d( 50) xor d( 49) xor d( 48) xor d( 47) xor d( 44) xor d( 41) xor d( 40) xor d( 38) xor d( 34) xor d( 33) xor d( 30) xor d( 27) xor d( 23) xor d( 19) xor d( 18) xor d( 17) xor d( 16) xor d( 15) xor d( 14) xor d( 10) xor d( 8) xor d( 7) xor d( 6) xor d( 4) xor d( 3) xor d( 2);
dq(117) <= d( 63) xor d( 62) xor d( 61) xor d( 60) xor d( 59) xor d( 57) xor d( 53) xor d( 52) xor d( 51) xor d( 50) xor d( 49) xor d( 48) xor d( 45) xor d( 42) xor d( 41) xor d( 39) xor d( 35) xor d( 34) xor d( 31) xor d( 28) xor d( 24) xor d( 20) xor d( 19) xor d( 18) xor d( 17) xor d( 16) xor d( 15) xor d( 11) xor d( 9) xor d( 8) xor d( 7) xor d( 5) xor d( 4) xor d( 3);
dq(118) <= d( 63) xor d( 62) xor d( 61) xor d( 60) xor d( 58) xor d( 54) xor d( 53) xor d( 52) xor d( 51) xor d( 50) xor d( 49) xor d( 46) xor d( 43) xor d( 42) xor d( 40) xor d( 36) xor d( 35) xor d( 32) xor d( 29) xor d( 25) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 17) xor d( 16) xor d( 12) xor d( 10) xor d( 9) xor d( 8) xor d( 6) xor d( 5) xor d( 4);
dq(119) <= d( 63) xor d( 62) xor d( 61) xor d( 59) xor d( 55) xor d( 54) xor d( 53) xor d( 52) xor d( 51) xor d( 50) xor d( 47) xor d( 44) xor d( 43) xor d( 41) xor d( 37) xor d( 36) xor d( 33) xor d( 30) xor d( 26) xor d( 22) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 17) xor d( 13) xor d( 11) xor d( 10) xor d( 9) xor d( 7) xor d( 6) xor d( 5);
dq(120) <= d( 63) xor d( 62) xor d( 60) xor d( 56) xor d( 55) xor d( 54) xor d( 53) xor d( 52) xor d( 51) xor d( 48) xor d( 45) xor d( 44) xor d( 42) xor d( 38) xor d( 37) xor d( 34) xor d( 31) xor d( 27) xor d( 23) xor d( 22) xor d( 21) xor d( 20) xor d( 19) xor d( 18) xor d( 14) xor d( 12) xor d( 11) xor d( 10) xor d( 8) xor d( 7) xor d( 6);
dq(121) <= d( 63) xor d( 61) xor d( 57) xor d( 56) xor d( 55) xor d( 54) xor d( 53) xor d( 52) xor d( 49) xor d( 46) xor d( 45) xor d( 43) xor d( 39) xor d( 38) xor d( 35) xor d( 32) xor d( 28) xor d( 24) xor d( 23) xor d( 22) xor d( 21) xor d( 20) xor d( 19) xor d( 15) xor d( 13) xor d( 12) xor d( 11) xor d( 9) xor d( 8) xor d( 7);
dq(122) <= d( 57) xor d( 55) xor d( 54) xor d( 51) xor d( 48) xor d( 45) xor d( 44) xor d( 43) xor d( 40) xor d( 39) xor d( 37) xor d( 36) xor d( 35) xor d( 34) xor d( 29) xor d( 28) xor d( 26) xor d( 25) xor d( 24) xor d( 20) xor d( 19) xor d( 18) xor d( 17) xor d( 16) xor d( 12) xor d( 9) xor d( 6) xor d( 5) xor d( 4) xor d( 0);
dq(123) <= d( 62) xor d( 55) xor d( 53) xor d( 52) xor d( 51) xor d( 50) xor d( 49) xor d( 48) xor d( 47) xor d( 44) xor d( 43) xor d( 41) xor d( 40) xor d( 38) xor d( 36) xor d( 34) xor d( 33) xor d( 30) xor d( 29) xor d( 28) xor d( 27) xor d( 25) xor d( 23) xor d( 22) xor d( 20) xor d( 14) xor d( 8) xor d( 7) xor d( 4) xor d( 1) xor d( 0);
dq(124) <= d( 63) xor d( 62) xor d( 58) xor d( 54) xor d( 52) xor d( 49) xor d( 47) xor d( 46) xor d( 44) xor d( 43) xor d( 42) xor d( 41) xor d( 39) xor d( 33) xor d( 31) xor d( 30) xor d( 29) xor d( 24) xor d( 22) xor d( 19) xor d( 18) xor d( 17) xor d( 15) xor d( 14) xor d( 13) xor d( 10) xor d( 9) xor d( 6) xor d( 4) xor d( 2) xor d( 1) xor d( 0);
dq(125) <= d( 63) xor d( 59) xor d( 55) xor d( 53) xor d( 50) xor d( 48) xor d( 47) xor d( 45) xor d( 44) xor d( 43) xor d( 42) xor d( 40) xor d( 34) xor d( 32) xor d( 31) xor d( 30) xor d( 25) xor d( 23) xor d( 20) xor d( 19) xor d( 18) xor d( 16) xor d( 15) xor d( 14) xor d( 11) xor d( 10) xor d( 7) xor d( 5) xor d( 3) xor d( 2) xor d( 1);
dq(126) <= d( 60) xor d( 56) xor d( 54) xor d( 51) xor d( 49) xor d( 48) xor d( 46) xor d( 45) xor d( 44) xor d( 43) xor d( 41) xor d( 35) xor d( 33) xor d( 32) xor d( 31) xor d( 26) xor d( 24) xor d( 21) xor d( 20) xor d( 19) xor d( 17) xor d( 16) xor d( 15) xor d( 12) xor d( 11) xor d( 8) xor d( 6) xor d( 4) xor d( 3) xor d( 2);
dq(127) <= d( 61) xor d( 57) xor d( 55) xor d( 52) xor d( 50) xor d( 49) xor d( 47) xor d( 46) xor d( 45) xor d( 44) xor d( 42) xor d( 36) xor d( 34) xor d( 33) xor d( 32) xor d( 27) xor d( 25) xor d( 22) xor d( 21) xor d( 20) xor d( 18) xor d( 17) xor d( 16) xor d( 13) xor d( 12) xor d( 9) xor d( 7) xor d( 5) xor d( 4) xor d( 3);
end if;
end process;
process (clk, reset)
begin
if (reset= '1') then
ca <= SEED;
rdy <= '0';
elsif (rising_edge(clk)) then
rdy <= nd_q;
if(nd_q= '1') then
if (fd_q= '1') then
ca( 0) <= SEED( 64) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 72) xor SEED( 74) xor SEED( 77) xor SEED( 78) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 90) xor SEED( 92) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(101) xor SEED(107) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(114) xor SEED(115) xor SEED(117) xor SEED(120) xor SEED(122) xor SEED(126) xor dq( 0);
ca( 1) <= SEED( 64) xor SEED( 65) xor SEED( 68) xor SEED( 71) xor SEED( 72) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 77) xor SEED( 79) xor SEED( 81) xor SEED( 84) xor SEED( 85) xor SEED( 88) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 97) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(113) xor SEED(114) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(126) xor SEED(127) xor dq( 1);
ca( 2) <= SEED( 65) xor SEED( 66) xor SEED( 69) xor SEED( 72) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 78) xor SEED( 80) xor SEED( 82) xor SEED( 85) xor SEED( 86) xor SEED( 89) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(114) xor SEED(115) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(127) xor dq( 2);
ca( 3) <= SEED( 64) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 72) xor SEED( 73) xor SEED( 75) xor SEED( 76) xor SEED( 78) xor SEED( 79) xor SEED( 82) xor SEED( 85) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 97) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(107) xor SEED(112) xor SEED(114) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(126) xor dq( 3);
ca( 4) <= SEED( 65) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 73) xor SEED( 74) xor SEED( 76) xor SEED( 77) xor SEED( 79) xor SEED( 80) xor SEED( 83) xor SEED( 86) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 98) xor SEED( 99) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(108) xor SEED(113) xor SEED(115) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(124) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 4);
ca( 5) <= SEED( 64) xor SEED( 66) xor SEED( 71) xor SEED( 72) xor SEED( 75) xor SEED( 80) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 90) xor SEED( 92) xor SEED( 95) xor SEED( 96) xor SEED( 98) xor SEED(100) xor SEED(101) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(121) xor SEED(122) xor SEED(125) xor SEED(127) xor dq( 5);
ca( 6) <= SEED( 65) xor SEED( 67) xor SEED( 72) xor SEED( 73) xor SEED( 76) xor SEED( 81) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 91) xor SEED( 93) xor SEED( 96) xor SEED( 97) xor SEED( 99) xor SEED(101) xor SEED(102) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(122) xor SEED(123) xor SEED(126) xor dq( 6);
ca( 7) <= SEED( 66) xor SEED( 68) xor SEED( 73) xor SEED( 74) xor SEED( 77) xor SEED( 82) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 92) xor SEED( 94) xor SEED( 97) xor SEED( 98) xor SEED(100) xor SEED(102) xor SEED(103) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(123) xor SEED(124) xor SEED(127) xor dq( 7);
ca( 8) <= SEED( 67) xor SEED( 69) xor SEED( 74) xor SEED( 75) xor SEED( 78) xor SEED( 83) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 93) xor SEED( 95) xor SEED( 98) xor SEED( 99) xor SEED(101) xor SEED(103) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(124) xor SEED(125) xor dq( 8);
ca( 9) <= SEED( 64) xor SEED( 69) xor SEED( 72) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 88) xor SEED( 89) xor SEED( 92) xor SEED( 94) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(104) xor SEED(105) xor SEED(108) xor SEED(112) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(121) xor SEED(123) xor SEED(125) xor dq( 9);
ca( 10) <= SEED( 64) xor SEED( 65) xor SEED( 68) xor SEED( 69) xor SEED( 72) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 84) xor SEED( 87) xor SEED( 89) xor SEED( 92) xor SEED( 93) xor SEED( 95) xor SEED(102) xor SEED(103) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(118) xor SEED(124) xor dq( 10);
ca( 11) <= SEED( 65) xor SEED( 66) xor SEED( 69) xor SEED( 70) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 77) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 85) xor SEED( 88) xor SEED( 90) xor SEED( 93) xor SEED( 94) xor SEED( 96) xor SEED(103) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(119) xor SEED(125) xor dq( 11);
ca( 12) <= SEED( 66) xor SEED( 67) xor SEED( 70) xor SEED( 71) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 86) xor SEED( 89) xor SEED( 91) xor SEED( 94) xor SEED( 95) xor SEED( 97) xor SEED(104) xor SEED(105) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(120) xor SEED(126) xor dq( 12);
ca( 13) <= SEED( 64) xor SEED( 67) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 79) xor SEED( 81) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 99) xor SEED(101) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(116) xor SEED(118) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(126) xor SEED(127) xor dq( 13);
ca( 14) <= SEED( 64) xor SEED( 65) xor SEED( 69) xor SEED( 71) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 78) xor SEED( 80) xor SEED( 81) xor SEED( 83) xor SEED( 90) xor SEED( 92) xor SEED( 96) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(106) xor SEED(108) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(115) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(123) xor SEED(126) xor SEED(127) xor dq( 14);
ca( 15) <= SEED( 65) xor SEED( 66) xor SEED( 70) xor SEED( 72) xor SEED( 75) xor SEED( 76) xor SEED( 77) xor SEED( 79) xor SEED( 81) xor SEED( 82) xor SEED( 84) xor SEED( 91) xor SEED( 93) xor SEED( 97) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(107) xor SEED(109) xor SEED(111) xor SEED(112) xor SEED(114) xor SEED(116) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(124) xor SEED(127) xor dq( 15);
ca( 16) <= SEED( 64) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 73) xor SEED( 74) xor SEED( 76) xor SEED( 80) xor SEED( 81) xor SEED( 86) xor SEED( 87) xor SEED( 90) xor SEED( 94) xor SEED( 97) xor SEED( 99) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(111) xor SEED(113) xor SEED(114) xor SEED(120) xor SEED(121) xor SEED(123) xor SEED(125) xor SEED(126) xor dq( 16);
ca( 17) <= SEED( 65) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 77) xor SEED( 81) xor SEED( 82) xor SEED( 87) xor SEED( 88) xor SEED( 91) xor SEED( 95) xor SEED( 98) xor SEED(100) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(114) xor SEED(115) xor SEED(121) xor SEED(122) xor SEED(124) xor SEED(126) xor SEED(127) xor dq( 17);
ca( 18) <= SEED( 66) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 78) xor SEED( 82) xor SEED( 83) xor SEED( 88) xor SEED( 89) xor SEED( 92) xor SEED( 96) xor SEED( 99) xor SEED(101) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(115) xor SEED(116) xor SEED(122) xor SEED(123) xor SEED(125) xor SEED(127) xor dq( 18);
ca( 19) <= SEED( 64) xor SEED( 67) xor SEED( 68) xor SEED( 71) xor SEED( 73) xor SEED( 75) xor SEED( 76) xor SEED( 78) xor SEED( 79) xor SEED( 81) xor SEED( 82) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 89) xor SEED( 92) xor SEED( 93) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(105) xor SEED(106) xor SEED(109) xor SEED(115) xor SEED(116) xor SEED(120) xor SEED(122) xor SEED(123) xor SEED(124) xor dq( 19);
ca( 20) <= SEED( 64) xor SEED( 65) xor SEED( 70) xor SEED( 76) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 88) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 97) xor SEED( 98) xor SEED(100) xor SEED(102) xor SEED(103) xor SEED(106) xor SEED(109) xor SEED(111) xor SEED(112) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(126) xor dq( 20);
ca( 21) <= SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 74) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 83) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 89) xor SEED( 90) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 97) xor SEED(103) xor SEED(104) xor SEED(109) xor SEED(111) xor SEED(113) xor SEED(114) xor SEED(116) xor SEED(120) xor SEED(121) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(127) xor dq( 21);
ca( 22) <= SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 71) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 88) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 99) xor SEED(101) xor SEED(104) xor SEED(105) xor SEED(107) xor SEED(109) xor SEED(111) xor SEED(120) xor SEED(121) xor SEED(124) xor SEED(125) xor dq( 22);
ca( 23) <= SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 70) xor SEED( 75) xor SEED( 76) xor SEED( 77) xor SEED( 79) xor SEED( 80) xor SEED( 82) xor SEED( 84) xor SEED( 87) xor SEED( 89) xor SEED( 90) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(111) xor SEED(114) xor SEED(115) xor SEED(117) xor SEED(120) xor SEED(121) xor SEED(125) xor dq( 23);
ca( 24) <= SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 71) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 80) xor SEED( 81) xor SEED( 83) xor SEED( 85) xor SEED( 88) xor SEED( 90) xor SEED( 91) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(115) xor SEED(116) xor SEED(118) xor SEED(121) xor SEED(122) xor SEED(126) xor dq( 24);
ca( 25) <= SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 72) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 81) xor SEED( 82) xor SEED( 84) xor SEED( 86) xor SEED( 89) xor SEED( 91) xor SEED( 92) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(122) xor SEED(123) xor SEED(127) xor dq( 25);
ca( 26) <= SEED( 64) xor SEED( 67) xor SEED( 72) xor SEED( 73) xor SEED( 74) xor SEED( 77) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 86) xor SEED( 93) xor SEED( 96) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(107) xor SEED(108) xor SEED(115) xor SEED(118) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(126) xor dq( 26);
ca( 27) <= SEED( 65) xor SEED( 68) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 78) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 87) xor SEED( 94) xor SEED( 97) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(108) xor SEED(109) xor SEED(116) xor SEED(119) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(127) xor dq( 27);
ca( 28) <= SEED( 66) xor SEED( 69) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 79) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 88) xor SEED( 95) xor SEED( 98) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(109) xor SEED(110) xor SEED(117) xor SEED(120) xor SEED(124) xor SEED(125) xor SEED(126) xor dq( 28);
ca( 29) <= SEED( 67) xor SEED( 70) xor SEED( 75) xor SEED( 76) xor SEED( 77) xor SEED( 80) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 89) xor SEED( 96) xor SEED( 99) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(110) xor SEED(111) xor SEED(118) xor SEED(121) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 29);
ca( 30) <= SEED( 68) xor SEED( 71) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 81) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 90) xor SEED( 97) xor SEED(100) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(111) xor SEED(112) xor SEED(119) xor SEED(122) xor SEED(126) xor SEED(127) xor dq( 30);
ca( 31) <= SEED( 69) xor SEED( 72) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 82) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 91) xor SEED( 98) xor SEED(101) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(113) xor SEED(120) xor SEED(123) xor SEED(127) xor dq( 31);
ca( 32) <= SEED( 64) xor SEED( 68) xor SEED( 69) xor SEED( 72) xor SEED( 73) xor SEED( 74) xor SEED( 77) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 90) xor SEED( 97) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(108) xor SEED(112) xor SEED(113) xor SEED(115) xor SEED(117) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(124) xor SEED(126) xor dq( 32);
ca( 33) <= SEED( 65) xor SEED( 69) xor SEED( 70) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 78) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 91) xor SEED( 98) xor SEED( 99) xor SEED(102) xor SEED(103) xor SEED(109) xor SEED(113) xor SEED(114) xor SEED(116) xor SEED(118) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(125) xor SEED(127) xor dq( 33);
ca( 34) <= SEED( 64) xor SEED( 66) xor SEED( 68) xor SEED( 69) xor SEED( 71) xor SEED( 72) xor SEED( 75) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 90) xor SEED( 97) xor SEED( 98) xor SEED(100) xor SEED(101) xor SEED(103) xor SEED(104) xor SEED(107) xor SEED(109) xor SEED(111) xor SEED(112) xor SEED(119) xor SEED(120) xor SEED(123) xor SEED(124) xor dq( 34);
ca( 35) <= SEED( 65) xor SEED( 67) xor SEED( 69) xor SEED( 70) xor SEED( 72) xor SEED( 73) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 91) xor SEED( 98) xor SEED( 99) xor SEED(101) xor SEED(102) xor SEED(104) xor SEED(105) xor SEED(108) xor SEED(110) xor SEED(112) xor SEED(113) xor SEED(120) xor SEED(121) xor SEED(124) xor SEED(125) xor dq( 35);
ca( 36) <= SEED( 64) xor SEED( 66) xor SEED( 69) xor SEED( 71) xor SEED( 72) xor SEED( 73) xor SEED( 79) xor SEED( 80) xor SEED( 82) xor SEED( 83) xor SEED( 85) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 97) xor SEED( 98) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(110) xor SEED(112) xor SEED(113) xor SEED(115) xor SEED(117) xor SEED(120) xor SEED(121) xor SEED(125) xor dq( 36);
ca( 37) <= SEED( 64) xor SEED( 65) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 73) xor SEED( 77) xor SEED( 78) xor SEED( 80) xor SEED( 82) xor SEED( 84) xor SEED( 85) xor SEED( 87) xor SEED( 89) xor SEED( 91) xor SEED( 92) xor SEED( 97) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(106) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(113) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(120) xor SEED(121) xor dq( 37);
ca( 38) <= SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 72) xor SEED( 77) xor SEED( 79) xor SEED( 82) xor SEED( 87) xor SEED( 88) xor SEED( 93) xor SEED( 97) xor SEED( 99) xor SEED(101) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(112) xor SEED(113) xor SEED(115) xor SEED(116) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(126) xor dq( 38);
ca( 39) <= SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 73) xor SEED( 78) xor SEED( 80) xor SEED( 83) xor SEED( 88) xor SEED( 89) xor SEED( 94) xor SEED( 98) xor SEED(100) xor SEED(102) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(113) xor SEED(114) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(127) xor dq( 39);
ca( 40) <= SEED( 64) xor SEED( 66) xor SEED( 67) xor SEED( 69) xor SEED( 70) xor SEED( 72) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 89) xor SEED( 92) xor SEED( 95) xor SEED( 97) xor SEED( 98) xor SEED(103) xor SEED(105) xor SEED(106) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(118) xor SEED(121) xor SEED(123) xor SEED(126) xor dq( 40);
ca( 41) <= SEED( 65) xor SEED( 67) xor SEED( 68) xor SEED( 70) xor SEED( 71) xor SEED( 73) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 90) xor SEED( 93) xor SEED( 96) xor SEED( 98) xor SEED( 99) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(119) xor SEED(122) xor SEED(124) xor SEED(127) xor dq( 41);
ca( 42) <= SEED( 64) xor SEED( 66) xor SEED( 70) xor SEED( 71) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 94) xor SEED( 98) xor SEED(100) xor SEED(101) xor SEED(105) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(113) xor SEED(115) xor SEED(117) xor SEED(122) xor SEED(123) xor SEED(125) xor SEED(126) xor dq( 42);
ca( 43) <= SEED( 64) xor SEED( 65) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 74) xor SEED( 77) xor SEED( 79) xor SEED( 80) xor SEED( 82) xor SEED( 84) xor SEED( 86) xor SEED( 87) xor SEED( 89) xor SEED( 91) xor SEED( 93) xor SEED( 95) xor SEED( 97) xor SEED( 98) xor SEED(102) xor SEED(106) xor SEED(107) xor SEED(112) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(120) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(127) xor dq( 43);
ca( 44) <= SEED( 65) xor SEED( 66) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 75) xor SEED( 78) xor SEED( 80) xor SEED( 81) xor SEED( 83) xor SEED( 85) xor SEED( 87) xor SEED( 88) xor SEED( 90) xor SEED( 92) xor SEED( 94) xor SEED( 96) xor SEED( 98) xor SEED( 99) xor SEED(103) xor SEED(107) xor SEED(108) xor SEED(113) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(121) xor SEED(123) xor SEED(124) xor SEED(125) xor dq( 44);
ca( 45) <= SEED( 64) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 71) xor SEED( 73) xor SEED( 74) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 95) xor SEED( 98) xor SEED(100) xor SEED(101) xor SEED(104) xor SEED(107) xor SEED(108) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(115) xor SEED(118) xor SEED(119) xor SEED(124) xor SEED(125) xor dq( 45);
ca( 46) <= SEED( 64) xor SEED( 65) xor SEED( 67) xor SEED( 70) xor SEED( 75) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 91) xor SEED( 93) xor SEED( 94) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED(102) xor SEED(105) xor SEED(107) xor SEED(108) xor SEED(110) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(122) xor SEED(125) xor dq( 46);
ca( 47) <= SEED( 65) xor SEED( 66) xor SEED( 68) xor SEED( 71) xor SEED( 76) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 92) xor SEED( 94) xor SEED( 95) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(103) xor SEED(106) xor SEED(108) xor SEED(109) xor SEED(111) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(120) xor SEED(123) xor SEED(126) xor dq( 47);
ca( 48) <= SEED( 66) xor SEED( 67) xor SEED( 69) xor SEED( 72) xor SEED( 77) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 93) xor SEED( 95) xor SEED( 96) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(104) xor SEED(107) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(121) xor SEED(124) xor SEED(127) xor dq( 48);
ca( 49) <= SEED( 67) xor SEED( 68) xor SEED( 70) xor SEED( 73) xor SEED( 78) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 94) xor SEED( 96) xor SEED( 97) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(105) xor SEED(108) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(122) xor SEED(125) xor dq( 49);
ca( 50) <= SEED( 64) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 81) xor SEED( 82) xor SEED( 84) xor SEED( 88) xor SEED( 90) xor SEED( 91) xor SEED( 93) xor SEED( 95) xor SEED( 99) xor SEED(100) xor SEED(102) xor SEED(106) xor SEED(107) xor SEED(110) xor SEED(115) xor SEED(118) xor SEED(119) xor SEED(121) xor SEED(122) xor SEED(123) xor dq( 50);
ca( 51) <= SEED( 64) xor SEED( 65) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 73) xor SEED( 74) xor SEED( 77) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 86) xor SEED( 87) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 94) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(103) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(123) xor SEED(124) xor SEED(126) xor dq( 51);
ca( 52) <= SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 68) xor SEED( 71) xor SEED( 75) xor SEED( 77) xor SEED( 80) xor SEED( 83) xor SEED( 85) xor SEED( 86) xor SEED( 88) xor SEED( 91) xor SEED( 95) xor SEED(100) xor SEED(104) xor SEED(107) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(116) xor SEED(118) xor SEED(122) xor SEED(124) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 52);
ca( 53) <= SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 70) xor SEED( 74) xor SEED( 76) xor SEED( 77) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 89) xor SEED( 90) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(105) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(119) xor SEED(120) xor SEED(122) xor SEED(123) xor SEED(125) xor SEED(127) xor dq( 53);
ca( 54) <= SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 74) xor SEED( 75) xor SEED( 81) xor SEED( 82) xor SEED( 84) xor SEED( 87) xor SEED( 91) xor SEED( 92) xor SEED(100) xor SEED(101) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(113) xor SEED(115) xor SEED(117) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(124) xor dq( 54);
ca( 55) <= SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 81) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 90) xor SEED( 93) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(102) xor SEED(108) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(120) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(126) xor dq( 55);
ca( 56) <= SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 69) xor SEED( 71) xor SEED( 75) xor SEED( 76) xor SEED( 79) xor SEED( 81) xor SEED( 83) xor SEED( 85) xor SEED( 86) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 94) xor SEED( 97) xor SEED(100) xor SEED(101) xor SEED(103) xor SEED(107) xor SEED(110) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(124) xor SEED(125) xor SEED(127) xor dq( 56);
ca( 57) <= SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 70) xor SEED( 72) xor SEED( 76) xor SEED( 77) xor SEED( 80) xor SEED( 82) xor SEED( 84) xor SEED( 86) xor SEED( 87) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 95) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(104) xor SEED(108) xor SEED(111) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(125) xor SEED(126) xor dq( 57);
ca( 58) <= SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 71) xor SEED( 73) xor SEED( 77) xor SEED( 78) xor SEED( 81) xor SEED( 83) xor SEED( 85) xor SEED( 87) xor SEED( 88) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 96) xor SEED( 99) xor SEED(102) xor SEED(103) xor SEED(105) xor SEED(109) xor SEED(112) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(126) xor SEED(127) xor dq( 58);
ca( 59) <= SEED( 64) xor SEED( 67) xor SEED( 77) xor SEED( 79) xor SEED( 81) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(103) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(109) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 59);
ca( 60) <= SEED( 64) xor SEED( 65) xor SEED( 69) xor SEED( 70) xor SEED( 72) xor SEED( 74) xor SEED( 77) xor SEED( 80) xor SEED( 81) xor SEED( 83) xor SEED( 84) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 91) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED(100) xor SEED(102) xor SEED(104) xor SEED(105) xor SEED(108) xor SEED(109) xor SEED(111) xor SEED(113) xor SEED(116) xor SEED(119) xor SEED(121) xor SEED(124) xor SEED(125) xor SEED(127) xor dq( 60);
ca( 61) <= SEED( 65) xor SEED( 66) xor SEED( 70) xor SEED( 71) xor SEED( 73) xor SEED( 75) xor SEED( 78) xor SEED( 81) xor SEED( 82) xor SEED( 84) xor SEED( 85) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 92) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(101) xor SEED(103) xor SEED(105) xor SEED(106) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(114) xor SEED(117) xor SEED(120) xor SEED(122) xor SEED(125) xor SEED(126) xor dq( 61);
ca( 62) <= SEED( 66) xor SEED( 67) xor SEED( 71) xor SEED( 72) xor SEED( 74) xor SEED( 76) xor SEED( 79) xor SEED( 82) xor SEED( 83) xor SEED( 85) xor SEED( 86) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 93) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(102) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(115) xor SEED(118) xor SEED(121) xor SEED(123) xor SEED(126) xor SEED(127) xor dq( 62);
ca( 63) <= SEED( 67) xor SEED( 68) xor SEED( 72) xor SEED( 73) xor SEED( 75) xor SEED( 77) xor SEED( 80) xor SEED( 83) xor SEED( 84) xor SEED( 86) xor SEED( 87) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 94) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(103) xor SEED(105) xor SEED(107) xor SEED(108) xor SEED(111) xor SEED(112) xor SEED(114) xor SEED(116) xor SEED(119) xor SEED(122) xor SEED(124) xor SEED(127) xor dq( 63);
ca( 64) <= SEED( 0) xor SEED( 64) xor SEED( 70) xor SEED( 72) xor SEED( 73) xor SEED( 76) xor SEED( 77) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 86) xor SEED( 88) xor SEED( 90) xor SEED( 91) xor SEED( 93) xor SEED( 95) xor SEED( 97) xor SEED(100) xor SEED(102) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(114) xor SEED(122) xor SEED(123) xor SEED(125) xor SEED(126) xor dq( 64);
ca( 65) <= SEED( 1) xor SEED( 65) xor SEED( 71) xor SEED( 73) xor SEED( 74) xor SEED( 77) xor SEED( 78) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 87) xor SEED( 89) xor SEED( 91) xor SEED( 92) xor SEED( 94) xor SEED( 96) xor SEED( 98) xor SEED(101) xor SEED(103) xor SEED(105) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(111) xor SEED(112) xor SEED(114) xor SEED(115) xor SEED(123) xor SEED(124) xor SEED(126) xor SEED(127) xor dq( 65);
ca( 66) <= SEED( 2) xor SEED( 64) xor SEED( 66) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 75) xor SEED( 77) xor SEED( 79) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 87) xor SEED( 88) xor SEED( 93) xor SEED( 95) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(111) xor SEED(113) xor SEED(114) xor SEED(116) xor SEED(117) xor SEED(120) xor SEED(122) xor SEED(124) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 66);
ca( 67) <= SEED( 3) xor SEED( 64) xor SEED( 65) xor SEED( 67) xor SEED( 68) xor SEED( 71) xor SEED( 72) xor SEED( 74) xor SEED( 76) xor SEED( 77) xor SEED( 80) xor SEED( 81) xor SEED( 84) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 92) xor SEED( 94) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(105) xor SEED(108) xor SEED(110) xor SEED(111) xor SEED(118) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(125) xor SEED(127) xor dq( 67);
ca( 68) <= SEED( 4) xor SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 70) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 83) xor SEED( 86) xor SEED( 88) xor SEED( 89) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 95) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(110) xor SEED(114) xor SEED(115) xor SEED(117) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(123) xor SEED(124) xor dq( 68);
ca( 69) <= SEED( 5) xor SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 75) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 89) xor SEED( 93) xor SEED( 94) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(114) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(121) xor SEED(124) xor SEED(125) xor SEED(126) xor dq( 69);
ca( 70) <= SEED( 6) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 73) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 90) xor SEED( 94) xor SEED( 95) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(115) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(122) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 70);
ca( 71) <= SEED( 7) xor SEED( 64) xor SEED( 66) xor SEED( 67) xor SEED( 71) xor SEED( 73) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 84) xor SEED( 88) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED(100) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(109) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(122) xor SEED(123) xor SEED(127) xor dq( 71);
ca( 72) <= SEED( 8) xor SEED( 64) xor SEED( 65) xor SEED( 67) xor SEED( 69) xor SEED( 70) xor SEED( 77) xor SEED( 78) xor SEED( 80) xor SEED( 86) xor SEED( 87) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 93) xor SEED( 96) xor SEED( 99) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(109) xor SEED(111) xor SEED(112) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(118) xor SEED(119) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(126) xor dq( 72);
ca( 73) <= SEED( 9) xor SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 69) xor SEED( 71) xor SEED( 72) xor SEED( 74) xor SEED( 77) xor SEED( 79) xor SEED( 82) xor SEED( 83) xor SEED( 85) xor SEED( 86) xor SEED( 88) xor SEED( 91) xor SEED( 94) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(105) xor SEED(106) xor SEED(109) xor SEED(111) xor SEED(113) xor SEED(114) xor SEED(116) xor SEED(119) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 73);
ca( 74) <= SEED( 10) xor SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 77) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 84) xor SEED( 85) xor SEED( 89) xor SEED( 90) xor SEED( 95) xor SEED( 97) xor SEED( 98) xor SEED(100) xor SEED(102) xor SEED(106) xor SEED(109) xor SEED(111) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(127) xor dq( 74);
ca( 75) <= SEED( 11) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 78) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 85) xor SEED( 86) xor SEED( 90) xor SEED( 91) xor SEED( 96) xor SEED( 98) xor SEED( 99) xor SEED(101) xor SEED(103) xor SEED(107) xor SEED(110) xor SEED(112) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(126) xor dq( 75);
ca( 76) <= SEED( 12) xor SEED( 64) xor SEED( 66) xor SEED( 67) xor SEED( 71) xor SEED( 72) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 78) xor SEED( 79) xor SEED( 81) xor SEED( 84) xor SEED( 85) xor SEED( 90) xor SEED( 91) xor SEED( 98) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(104) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(117) xor SEED(120) xor SEED(122) xor SEED(124) xor SEED(125) xor SEED(127) xor dq( 76);
ca( 77) <= SEED( 13) xor SEED( 65) xor SEED( 67) xor SEED( 68) xor SEED( 72) xor SEED( 73) xor SEED( 75) xor SEED( 76) xor SEED( 77) xor SEED( 79) xor SEED( 80) xor SEED( 82) xor SEED( 85) xor SEED( 86) xor SEED( 91) xor SEED( 92) xor SEED( 99) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(105) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(118) xor SEED(121) xor SEED(123) xor SEED(125) xor SEED(126) xor dq( 77);
ca( 78) <= SEED( 14) xor SEED( 66) xor SEED( 68) xor SEED( 69) xor SEED( 73) xor SEED( 74) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 80) xor SEED( 81) xor SEED( 83) xor SEED( 86) xor SEED( 87) xor SEED( 92) xor SEED( 93) xor SEED(100) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(106) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(122) xor SEED(124) xor SEED(126) xor SEED(127) xor dq( 78);
ca( 79) <= SEED( 15) xor SEED( 64) xor SEED( 67) xor SEED( 68) xor SEED( 72) xor SEED( 75) xor SEED( 79) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 88) xor SEED( 90) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(109) xor SEED(113) xor SEED(114) xor SEED(116) xor SEED(118) xor SEED(122) xor SEED(123) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 79);
ca( 80) <= SEED( 16) xor SEED( 64) xor SEED( 65) xor SEED( 70) xor SEED( 72) xor SEED( 73) xor SEED( 74) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 97) xor SEED(100) xor SEED(101) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(109) xor SEED(111) xor SEED(112) xor SEED(119) xor SEED(120) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(127) xor dq( 80);
ca( 81) <= SEED( 17) xor SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 73) xor SEED( 75) xor SEED( 79) xor SEED( 84) xor SEED( 86) xor SEED( 87) xor SEED( 91) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 99) xor SEED(102) xor SEED(105) xor SEED(106) xor SEED(108) xor SEED(109) xor SEED(111) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(117) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(126) xor dq( 81);
ca( 82) <= SEED( 18) xor SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 71) xor SEED( 73) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 86) xor SEED( 88) xor SEED( 90) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(103) xor SEED(106) xor SEED(111) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(120) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(127) xor dq( 82);
ca( 83) <= SEED( 19) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 72) xor SEED( 74) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 87) xor SEED( 89) xor SEED( 91) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(104) xor SEED(107) xor SEED(112) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(121) xor SEED(124) xor SEED(125) xor SEED(126) xor dq( 83);
ca( 84) <= SEED( 20) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 73) xor SEED( 75) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 88) xor SEED( 90) xor SEED( 92) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(105) xor SEED(108) xor SEED(113) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(122) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 84);
ca( 85) <= SEED( 21) xor SEED( 64) xor SEED( 67) xor SEED( 71) xor SEED( 72) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 82) xor SEED( 84) xor SEED( 87) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(115) xor SEED(117) xor SEED(119) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(127) xor dq( 85);
ca( 86) <= SEED( 22) xor SEED( 65) xor SEED( 68) xor SEED( 72) xor SEED( 73) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 83) xor SEED( 85) xor SEED( 88) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(107) xor SEED(108) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(116) xor SEED(118) xor SEED(120) xor SEED(122) xor SEED(123) xor SEED(124) xor dq( 86);
ca( 87) <= SEED( 23) xor SEED( 66) xor SEED( 69) xor SEED( 73) xor SEED( 74) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 84) xor SEED( 86) xor SEED( 89) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(108) xor SEED(109) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(117) xor SEED(119) xor SEED(121) xor SEED(123) xor SEED(124) xor SEED(125) xor dq( 87);
ca( 88) <= SEED( 24) xor SEED( 64) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 72) xor SEED( 75) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 86) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(101) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(117) xor SEED(118) xor SEED(124) xor SEED(125) xor dq( 88);
ca( 89) <= SEED( 25) xor SEED( 65) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 73) xor SEED( 76) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 87) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(102) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(118) xor SEED(119) xor SEED(125) xor SEED(126) xor dq( 89);
ca( 90) <= SEED( 26) xor SEED( 66) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 74) xor SEED( 77) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 88) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(103) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(119) xor SEED(120) xor SEED(126) xor SEED(127) xor dq( 90);
ca( 91) <= SEED( 27) xor SEED( 67) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 75) xor SEED( 78) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 89) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(104) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(120) xor SEED(121) xor SEED(127) xor dq( 91);
ca( 92) <= SEED( 28) xor SEED( 64) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 73) xor SEED( 74) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 92) xor SEED(100) xor SEED(102) xor SEED(103) xor SEED(105) xor SEED(107) xor SEED(108) xor SEED(111) xor SEED(112) xor SEED(114) xor SEED(116) xor SEED(120) xor SEED(121) xor SEED(126) xor dq( 92);
ca( 93) <= SEED( 29) xor SEED( 64) xor SEED( 65) xor SEED( 68) xor SEED( 69) xor SEED( 71) xor SEED( 75) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 88) xor SEED( 90) xor SEED( 92) xor SEED( 93) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(103) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(114) xor SEED(120) xor SEED(121) xor SEED(126) xor SEED(127) xor dq( 93);
ca( 94) <= SEED( 30) xor SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 68) xor SEED( 74) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 80) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 97) xor SEED(100) xor SEED(101) xor SEED(104) xor SEED(105) xor SEED(108) xor SEED(110) xor SEED(117) xor SEED(120) xor SEED(121) xor SEED(126) xor SEED(127) xor dq( 94);
ca( 95) <= SEED( 31) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 69) xor SEED( 75) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 81) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(105) xor SEED(106) xor SEED(109) xor SEED(111) xor SEED(118) xor SEED(121) xor SEED(122) xor SEED(127) xor dq( 95);
ca( 96) <= SEED( 32) xor SEED( 64) xor SEED( 66) xor SEED( 67) xor SEED( 69) xor SEED( 72) xor SEED( 74) xor SEED( 76) xor SEED( 77) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 83) xor SEED( 85) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(106) xor SEED(109) xor SEED(111) xor SEED(114) xor SEED(115) xor SEED(117) xor SEED(119) xor SEED(120) xor SEED(123) xor SEED(126) xor dq( 96);
ca( 97) <= SEED( 33) xor SEED( 64) xor SEED( 65) xor SEED( 67) xor SEED( 69) xor SEED( 72) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 80) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 87) xor SEED( 89) xor SEED( 91) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(109) xor SEED(111) xor SEED(114) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(121) xor SEED(122) xor SEED(124) xor SEED(126) xor SEED(127) xor dq( 97);
ca( 98) <= SEED( 34) xor SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 69) xor SEED( 72) xor SEED( 73) xor SEED( 75) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 87) xor SEED( 88) xor SEED( 95) xor SEED( 96) xor SEED( 98) xor SEED( 99) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(107) xor SEED(109) xor SEED(111) xor SEED(114) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(123) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 98);
ca( 99) <= SEED( 35) xor SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 72) xor SEED( 73) xor SEED( 76) xor SEED( 79) xor SEED( 81) xor SEED( 82) xor SEED( 84) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 92) xor SEED( 96) xor SEED( 98) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(111) xor SEED(114) xor SEED(117) xor SEED(119) xor SEED(121) xor SEED(122) xor SEED(124) xor SEED(127) xor dq( 99);
ca(100) <= SEED( 36) xor SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 72) xor SEED( 73) xor SEED( 78) xor SEED( 80) xor SEED( 81) xor SEED( 86) xor SEED( 88) xor SEED( 89) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 98) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(108) xor SEED(111) xor SEED(114) xor SEED(117) xor SEED(118) xor SEED(123) xor SEED(125) xor SEED(126) xor dq(100);
ca(101) <= SEED( 37) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 73) xor SEED( 74) xor SEED( 79) xor SEED( 81) xor SEED( 82) xor SEED( 87) xor SEED( 89) xor SEED( 90) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 99) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(109) xor SEED(112) xor SEED(115) xor SEED(118) xor SEED(119) xor SEED(124) xor SEED(126) xor SEED(127) xor dq(101);
ca(102) <= SEED( 38) xor SEED( 64) xor SEED( 66) xor SEED( 67) xor SEED( 70) xor SEED( 72) xor SEED( 75) xor SEED( 77) xor SEED( 78) xor SEED( 80) xor SEED( 81) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(108) xor SEED(109) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(122) xor SEED(125) xor SEED(126) xor SEED(127) xor dq(102);
ca(103) <= SEED( 39) xor SEED( 65) xor SEED( 67) xor SEED( 68) xor SEED( 71) xor SEED( 73) xor SEED( 76) xor SEED( 78) xor SEED( 79) xor SEED( 81) xor SEED( 82) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(120) xor SEED(123) xor SEED(126) xor SEED(127) xor dq(103);
ca(104) <= SEED( 40) xor SEED( 64) xor SEED( 66) xor SEED( 70) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 85) xor SEED( 86) xor SEED( 88) xor SEED( 89) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 98) xor SEED(100) xor SEED(102) xor SEED(103) xor SEED(106) xor SEED(108) xor SEED(109) xor SEED(112) xor SEED(113) xor SEED(116) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(124) xor SEED(126) xor SEED(127) xor dq(104);
ca(105) <= SEED( 41) xor SEED( 65) xor SEED( 67) xor SEED( 71) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 86) xor SEED( 87) xor SEED( 89) xor SEED( 90) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 99) xor SEED(101) xor SEED(103) xor SEED(104) xor SEED(107) xor SEED(109) xor SEED(110) xor SEED(113) xor SEED(114) xor SEED(117) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(125) xor SEED(127) xor dq(105);
ca(106) <= SEED( 42) xor SEED( 64) xor SEED( 66) xor SEED( 69) xor SEED( 70) xor SEED( 74) xor SEED( 77) xor SEED( 78) xor SEED( 80) xor SEED( 85) xor SEED( 86) xor SEED( 88) xor SEED( 91) xor SEED( 92) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(104) xor SEED(105) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(112) xor SEED(117) xor SEED(118) xor SEED(121) xor SEED(123) xor SEED(124) xor dq(106);
ca(107) <= SEED( 43) xor SEED( 65) xor SEED( 67) xor SEED( 70) xor SEED( 71) xor SEED( 75) xor SEED( 78) xor SEED( 79) xor SEED( 81) xor SEED( 86) xor SEED( 87) xor SEED( 89) xor SEED( 92) xor SEED( 93) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(105) xor SEED(106) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(113) xor SEED(118) xor SEED(119) xor SEED(122) xor SEED(124) xor SEED(125) xor dq(107);
ca(108) <= SEED( 44) xor SEED( 66) xor SEED( 68) xor SEED( 71) xor SEED( 72) xor SEED( 76) xor SEED( 79) xor SEED( 80) xor SEED( 82) xor SEED( 87) xor SEED( 88) xor SEED( 90) xor SEED( 93) xor SEED( 94) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(114) xor SEED(119) xor SEED(120) xor SEED(123) xor SEED(125) xor SEED(126) xor dq(108);
ca(109) <= SEED( 45) xor SEED( 64) xor SEED( 67) xor SEED( 68) xor SEED( 70) xor SEED( 73) xor SEED( 74) xor SEED( 78) xor SEED( 80) xor SEED( 82) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 94) xor SEED( 95) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(108) xor SEED(109) xor SEED(114) xor SEED(117) xor SEED(121) xor SEED(122) xor SEED(124) xor SEED(127) xor dq(109);
ca(110) <= SEED( 46) xor SEED( 65) xor SEED( 68) xor SEED( 69) xor SEED( 71) xor SEED( 74) xor SEED( 75) xor SEED( 79) xor SEED( 81) xor SEED( 83) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 95) xor SEED( 96) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(109) xor SEED(110) xor SEED(115) xor SEED(118) xor SEED(122) xor SEED(123) xor SEED(125) xor dq(110);
ca(111) <= SEED( 47) xor SEED( 66) xor SEED( 69) xor SEED( 70) xor SEED( 72) xor SEED( 75) xor SEED( 76) xor SEED( 80) xor SEED( 82) xor SEED( 84) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 96) xor SEED( 97) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(110) xor SEED(111) xor SEED(116) xor SEED(119) xor SEED(123) xor SEED(124) xor SEED(126) xor dq(111);
ca(112) <= SEED( 48) xor SEED( 64) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 71) xor SEED( 72) xor SEED( 73) xor SEED( 74) xor SEED( 76) xor SEED( 78) xor SEED( 82) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 91) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 99) xor SEED(101) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(114) xor SEED(115) xor SEED(122) xor SEED(124) xor SEED(125) xor SEED(126) xor SEED(127) xor dq(112);
ca(113) <= SEED( 49) xor SEED( 64) xor SEED( 65) xor SEED( 73) xor SEED( 75) xor SEED( 78) xor SEED( 79) xor SEED( 81) xor SEED( 82) xor SEED( 85) xor SEED( 86) xor SEED( 88) xor SEED( 89) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(105) xor SEED(106) xor SEED(112) xor SEED(114) xor SEED(116) xor SEED(117) xor SEED(120) xor SEED(122) xor SEED(123) xor SEED(125) xor SEED(127) xor dq(113);
ca(114) <= SEED( 50) xor SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 72) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 85) xor SEED( 89) xor SEED( 92) xor SEED( 95) xor SEED( 96) xor SEED(100) xor SEED(102) xor SEED(103) xor SEED(106) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(118) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(124) xor dq(114);
ca(115) <= SEED( 51) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 73) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 86) xor SEED( 90) xor SEED( 93) xor SEED( 96) xor SEED( 97) xor SEED(101) xor SEED(103) xor SEED(104) xor SEED(107) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(119) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(125) xor dq(115);
ca(116) <= SEED( 52) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 74) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 87) xor SEED( 91) xor SEED( 94) xor SEED( 97) xor SEED( 98) xor SEED(102) xor SEED(104) xor SEED(105) xor SEED(108) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(120) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(126) xor dq(116);
ca(117) <= SEED( 53) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 71) xor SEED( 72) xor SEED( 73) xor SEED( 75) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 88) xor SEED( 92) xor SEED( 95) xor SEED( 98) xor SEED( 99) xor SEED(103) xor SEED(105) xor SEED(106) xor SEED(109) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(121) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(126) xor SEED(127) xor dq(117);
ca(118) <= SEED( 54) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 72) xor SEED( 73) xor SEED( 74) xor SEED( 76) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 89) xor SEED( 93) xor SEED( 96) xor SEED( 99) xor SEED(100) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(110) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(122) xor SEED(124) xor SEED(125) xor SEED(126) xor SEED(127) xor dq(118);
ca(119) <= SEED( 55) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 77) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 90) xor SEED( 94) xor SEED( 97) xor SEED(100) xor SEED(101) xor SEED(105) xor SEED(107) xor SEED(108) xor SEED(111) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(123) xor SEED(125) xor SEED(126) xor SEED(127) xor dq(119);
ca(120) <= SEED( 56) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 78) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 91) xor SEED( 95) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(106) xor SEED(108) xor SEED(109) xor SEED(112) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(124) xor SEED(126) xor SEED(127) xor dq(120);
ca(121) <= SEED( 57) xor SEED( 71) xor SEED( 72) xor SEED( 73) xor SEED( 75) xor SEED( 76) xor SEED( 77) xor SEED( 79) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 92) xor SEED( 96) xor SEED( 99) xor SEED(102) xor SEED(103) xor SEED(107) xor SEED(109) xor SEED(110) xor SEED(113) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(125) xor SEED(127) xor dq(121);
ca(122) <= SEED( 58) xor SEED( 64) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 73) xor SEED( 76) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 92) xor SEED( 93) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(103) xor SEED(104) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(112) xor SEED(115) xor SEED(118) xor SEED(119) xor SEED(121) xor dq(122);
ca(123) <= SEED( 59) xor SEED( 64) xor SEED( 65) xor SEED( 68) xor SEED( 71) xor SEED( 72) xor SEED( 78) xor SEED( 84) xor SEED( 86) xor SEED( 87) xor SEED( 89) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 97) xor SEED( 98) xor SEED(100) xor SEED(102) xor SEED(104) xor SEED(105) xor SEED(107) xor SEED(108) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(126) xor dq(123);
ca(124) <= SEED( 60) xor SEED( 64) xor SEED( 65) xor SEED( 66) xor SEED( 68) xor SEED( 70) xor SEED( 73) xor SEED( 74) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 86) xor SEED( 88) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 97) xor SEED(103) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(116) xor SEED(118) xor SEED(122) xor SEED(126) xor SEED(127) xor dq(124);
ca(125) <= SEED( 61) xor SEED( 65) xor SEED( 66) xor SEED( 67) xor SEED( 69) xor SEED( 71) xor SEED( 74) xor SEED( 75) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 87) xor SEED( 89) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 98) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(111) xor SEED(112) xor SEED(114) xor SEED(117) xor SEED(119) xor SEED(123) xor SEED(127) xor dq(125);
ca(126) <= SEED( 62) xor SEED( 66) xor SEED( 67) xor SEED( 68) xor SEED( 70) xor SEED( 72) xor SEED( 75) xor SEED( 76) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 88) xor SEED( 90) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 99) xor SEED(105) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(113) xor SEED(115) xor SEED(118) xor SEED(120) xor SEED(124) xor dq(126);
ca(127) <= SEED( 63) xor SEED( 67) xor SEED( 68) xor SEED( 69) xor SEED( 71) xor SEED( 73) xor SEED( 76) xor SEED( 77) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 89) xor SEED( 91) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED(100) xor SEED(106) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(114) xor SEED(116) xor SEED(119) xor SEED(121) xor SEED(125) xor dq(127);
oa( 63) <= SEED(127) xor dq( 0);
oa( 62) <= SEED(126) xor dq( 1);
oa( 61) <= SEED(125) xor dq( 2);
oa( 60) <= SEED(124) xor dq( 3);
oa( 59) <= SEED(123) xor SEED(127) xor dq( 4);
oa( 58) <= SEED(122) xor SEED(126) xor SEED(127) xor dq( 5);
oa( 57) <= SEED(121) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 6);
oa( 56) <= SEED(120) xor SEED(124) xor SEED(125) xor SEED(126) xor dq( 7);
oa( 55) <= SEED(119) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(127) xor dq( 8);
oa( 54) <= SEED(118) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(126) xor dq( 9);
oa( 53) <= SEED(117) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(125) xor SEED(127) xor dq( 10);
oa( 52) <= SEED(116) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(124) xor SEED(126) xor dq( 11);
oa( 51) <= SEED(115) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(123) xor SEED(125) xor dq( 12);
oa( 50) <= SEED(114) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(122) xor SEED(124) xor SEED(127) xor dq( 13);
oa( 49) <= SEED(113) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(121) xor SEED(123) xor SEED(126) xor SEED(127) xor dq( 14);
oa( 48) <= SEED(112) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(120) xor SEED(122) xor SEED(125) xor SEED(126) xor dq( 15);
oa( 47) <= SEED(111) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(121) xor SEED(124) xor SEED(125) xor dq( 16);
oa( 46) <= SEED(110) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(118) xor SEED(120) xor SEED(123) xor SEED(124) xor SEED(127) xor dq( 17);
oa( 45) <= SEED(109) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(117) xor SEED(119) xor SEED(122) xor SEED(123) xor SEED(126) xor SEED(127) xor dq( 18);
oa( 44) <= SEED(108) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(116) xor SEED(118) xor SEED(121) xor SEED(122) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 19);
oa( 43) <= SEED(107) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(115) xor SEED(117) xor SEED(120) xor SEED(121) xor SEED(124) xor SEED(125) xor SEED(126) xor dq( 20);
oa( 42) <= SEED(106) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(114) xor SEED(116) xor SEED(119) xor SEED(120) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(127) xor dq( 21);
oa( 41) <= SEED(105) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(115) xor SEED(118) xor SEED(119) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(126) xor SEED(127) xor dq( 22);
oa( 40) <= SEED(104) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(114) xor SEED(117) xor SEED(118) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 23);
oa( 39) <= SEED(103) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(111) xor SEED(113) xor SEED(116) xor SEED(117) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(124) xor SEED(125) xor SEED(126) xor dq( 24);
oa( 38) <= SEED(102) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(110) xor SEED(112) xor SEED(115) xor SEED(116) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(123) xor SEED(124) xor SEED(125) xor dq( 25);
oa( 37) <= SEED(101) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(109) xor SEED(111) xor SEED(114) xor SEED(115) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(127) xor dq( 26);
oa( 36) <= SEED(100) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(108) xor SEED(110) xor SEED(113) xor SEED(114) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(126) xor dq( 27);
oa( 35) <= SEED( 99) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(107) xor SEED(109) xor SEED(112) xor SEED(113) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(125) xor SEED(127) xor dq( 28);
oa( 34) <= SEED( 98) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(106) xor SEED(108) xor SEED(111) xor SEED(112) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(124) xor SEED(126) xor dq( 29);
oa( 33) <= SEED( 97) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(105) xor SEED(107) xor SEED(110) xor SEED(111) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(123) xor SEED(125) xor dq( 30);
oa( 32) <= SEED( 96) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(104) xor SEED(106) xor SEED(109) xor SEED(110) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(122) xor SEED(124) xor dq( 31);
oa( 31) <= SEED( 95) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(103) xor SEED(105) xor SEED(108) xor SEED(109) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(121) xor SEED(123) xor dq( 32);
oa( 30) <= SEED( 94) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(102) xor SEED(104) xor SEED(107) xor SEED(108) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(120) xor SEED(122) xor SEED(127) xor dq( 33);
oa( 29) <= SEED( 93) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(101) xor SEED(103) xor SEED(106) xor SEED(107) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(119) xor SEED(121) xor SEED(126) xor SEED(127) xor dq( 34);
oa( 28) <= SEED( 92) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED(100) xor SEED(102) xor SEED(105) xor SEED(106) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(118) xor SEED(120) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 35);
oa( 27) <= SEED( 91) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 99) xor SEED(101) xor SEED(104) xor SEED(105) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(117) xor SEED(119) xor SEED(124) xor SEED(125) xor SEED(126) xor dq( 36);
oa( 26) <= SEED( 90) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 98) xor SEED(100) xor SEED(103) xor SEED(104) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(116) xor SEED(118) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(127) xor dq( 37);
oa( 25) <= SEED( 89) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 97) xor SEED( 99) xor SEED(102) xor SEED(103) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(115) xor SEED(117) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(126) xor dq( 38);
oa( 24) <= SEED( 88) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 96) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(114) xor SEED(116) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(125) xor dq( 39);
oa( 23) <= SEED( 87) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 95) xor SEED( 97) xor SEED(100) xor SEED(101) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(113) xor SEED(115) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(124) xor dq( 40);
oa( 22) <= SEED( 86) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 94) xor SEED( 96) xor SEED( 99) xor SEED(100) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(112) xor SEED(114) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(123) xor dq( 41);
oa( 21) <= SEED( 85) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 93) xor SEED( 95) xor SEED( 98) xor SEED( 99) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(111) xor SEED(113) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(122) xor dq( 42);
oa( 20) <= SEED( 84) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 92) xor SEED( 94) xor SEED( 97) xor SEED( 98) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(110) xor SEED(112) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(121) xor SEED(127) xor dq( 43);
oa( 19) <= SEED( 83) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 91) xor SEED( 93) xor SEED( 96) xor SEED( 97) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(109) xor SEED(111) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(120) xor SEED(126) xor dq( 44);
oa( 18) <= SEED( 82) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 90) xor SEED( 92) xor SEED( 95) xor SEED( 96) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(108) xor SEED(110) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(125) xor SEED(127) xor dq( 45);
oa( 17) <= SEED( 81) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 89) xor SEED( 91) xor SEED( 94) xor SEED( 95) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(107) xor SEED(109) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(118) xor SEED(124) xor SEED(126) xor SEED(127) xor dq( 46);
oa( 16) <= SEED( 80) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 88) xor SEED( 90) xor SEED( 93) xor SEED( 94) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(106) xor SEED(108) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(117) xor SEED(123) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 47);
oa( 15) <= SEED( 79) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 87) xor SEED( 89) xor SEED( 92) xor SEED( 93) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(105) xor SEED(107) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(116) xor SEED(122) xor SEED(124) xor SEED(125) xor SEED(126) xor SEED(127) xor dq( 48);
oa( 14) <= SEED( 78) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 86) xor SEED( 88) xor SEED( 91) xor SEED( 92) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(104) xor SEED(106) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(115) xor SEED(121) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(126) xor dq( 49);
oa( 13) <= SEED( 77) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 85) xor SEED( 87) xor SEED( 90) xor SEED( 91) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(103) xor SEED(105) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(114) xor SEED(120) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(125) xor SEED(127) xor dq( 50);
oa( 12) <= SEED( 76) xor SEED( 80) xor SEED( 81) xor SEED( 82) xor SEED( 84) xor SEED( 86) xor SEED( 89) xor SEED( 90) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(102) xor SEED(104) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(113) xor SEED(119) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(124) xor SEED(126) xor SEED(127) xor dq( 51);
oa( 11) <= SEED( 75) xor SEED( 79) xor SEED( 80) xor SEED( 81) xor SEED( 83) xor SEED( 85) xor SEED( 88) xor SEED( 89) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 96) xor SEED( 97) xor SEED( 98) xor SEED(101) xor SEED(103) xor SEED(108) xor SEED(109) xor SEED(110) xor SEED(112) xor SEED(118) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(123) xor SEED(125) xor SEED(126) xor dq( 52);
oa( 10) <= SEED( 74) xor SEED( 78) xor SEED( 79) xor SEED( 80) xor SEED( 82) xor SEED( 84) xor SEED( 87) xor SEED( 88) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 95) xor SEED( 96) xor SEED( 97) xor SEED(100) xor SEED(102) xor SEED(107) xor SEED(108) xor SEED(109) xor SEED(111) xor SEED(117) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(122) xor SEED(124) xor SEED(125) xor SEED(127) xor dq( 53);
oa( 9) <= SEED( 73) xor SEED( 77) xor SEED( 78) xor SEED( 79) xor SEED( 81) xor SEED( 83) xor SEED( 86) xor SEED( 87) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 94) xor SEED( 95) xor SEED( 96) xor SEED( 99) xor SEED(101) xor SEED(106) xor SEED(107) xor SEED(108) xor SEED(110) xor SEED(116) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(121) xor SEED(123) xor SEED(124) xor SEED(126) xor dq( 54);
oa( 8) <= SEED( 72) xor SEED( 76) xor SEED( 77) xor SEED( 78) xor SEED( 80) xor SEED( 82) xor SEED( 85) xor SEED( 86) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 93) xor SEED( 94) xor SEED( 95) xor SEED( 98) xor SEED(100) xor SEED(105) xor SEED(106) xor SEED(107) xor SEED(109) xor SEED(115) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(120) xor SEED(122) xor SEED(123) xor SEED(125) xor dq( 55);
oa( 7) <= SEED( 71) xor SEED( 75) xor SEED( 76) xor SEED( 77) xor SEED( 79) xor SEED( 81) xor SEED( 84) xor SEED( 85) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 92) xor SEED( 93) xor SEED( 94) xor SEED( 97) xor SEED( 99) xor SEED(104) xor SEED(105) xor SEED(106) xor SEED(108) xor SEED(114) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(119) xor SEED(121) xor SEED(122) xor SEED(124) xor SEED(127) xor dq( 56);
oa( 6) <= SEED( 70) xor SEED( 74) xor SEED( 75) xor SEED( 76) xor SEED( 78) xor SEED( 80) xor SEED( 83) xor SEED( 84) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 91) xor SEED( 92) xor SEED( 93) xor SEED( 96) xor SEED( 98) xor SEED(103) xor SEED(104) xor SEED(105) xor SEED(107) xor SEED(113) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(118) xor SEED(120) xor SEED(121) xor SEED(123) xor SEED(126) xor dq( 57);
oa( 5) <= SEED( 69) xor SEED( 73) xor SEED( 74) xor SEED( 75) xor SEED( 77) xor SEED( 79) xor SEED( 82) xor SEED( 83) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 90) xor SEED( 91) xor SEED( 92) xor SEED( 95) xor SEED( 97) xor SEED(102) xor SEED(103) xor SEED(104) xor SEED(106) xor SEED(112) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(120) xor SEED(122) xor SEED(125) xor SEED(127) xor dq( 58);
oa( 4) <= SEED( 68) xor SEED( 72) xor SEED( 73) xor SEED( 74) xor SEED( 76) xor SEED( 78) xor SEED( 81) xor SEED( 82) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 89) xor SEED( 90) xor SEED( 91) xor SEED( 94) xor SEED( 96) xor SEED(101) xor SEED(102) xor SEED(103) xor SEED(105) xor SEED(111) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(116) xor SEED(118) xor SEED(119) xor SEED(121) xor SEED(124) xor SEED(126) xor dq( 59);
oa( 3) <= SEED( 67) xor SEED( 71) xor SEED( 72) xor SEED( 73) xor SEED( 75) xor SEED( 77) xor SEED( 80) xor SEED( 81) xor SEED( 84) xor SEED( 85) xor SEED( 86) xor SEED( 88) xor SEED( 89) xor SEED( 90) xor SEED( 93) xor SEED( 95) xor SEED(100) xor SEED(101) xor SEED(102) xor SEED(104) xor SEED(110) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(115) xor SEED(117) xor SEED(118) xor SEED(120) xor SEED(123) xor SEED(125) xor dq( 60);
oa( 2) <= SEED( 66) xor SEED( 70) xor SEED( 71) xor SEED( 72) xor SEED( 74) xor SEED( 76) xor SEED( 79) xor SEED( 80) xor SEED( 83) xor SEED( 84) xor SEED( 85) xor SEED( 87) xor SEED( 88) xor SEED( 89) xor SEED( 92) xor SEED( 94) xor SEED( 99) xor SEED(100) xor SEED(101) xor SEED(103) xor SEED(109) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(114) xor SEED(116) xor SEED(117) xor SEED(119) xor SEED(122) xor SEED(124) xor dq( 61);
oa( 1) <= SEED( 65) xor SEED( 69) xor SEED( 70) xor SEED( 71) xor SEED( 73) xor SEED( 75) xor SEED( 78) xor SEED( 79) xor SEED( 82) xor SEED( 83) xor SEED( 84) xor SEED( 86) xor SEED( 87) xor SEED( 88) xor SEED( 91) xor SEED( 93) xor SEED( 98) xor SEED( 99) xor SEED(100) xor SEED(102) xor SEED(108) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(113) xor SEED(115) xor SEED(116) xor SEED(118) xor SEED(121) xor SEED(123) xor SEED(127) xor dq( 62);
oa( 0) <= SEED( 64) xor SEED( 68) xor SEED( 69) xor SEED( 70) xor SEED( 72) xor SEED( 74) xor SEED( 77) xor SEED( 78) xor SEED( 81) xor SEED( 82) xor SEED( 83) xor SEED( 85) xor SEED( 86) xor SEED( 87) xor SEED( 90) xor SEED( 92) xor SEED( 97) xor SEED( 98) xor SEED( 99) xor SEED(101) xor SEED(107) xor SEED(109) xor SEED(110) xor SEED(111) xor SEED(112) xor SEED(114) xor SEED(115) xor SEED(117) xor SEED(120) xor SEED(122) xor SEED(126) xor dq( 63);
else
ca( 0) <= ca( 64) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 72) xor ca( 74) xor ca( 77) xor ca( 78) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 90) xor ca( 92) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(101) xor ca(107) xor ca(109) xor ca(110) xor ca(111) xor ca(112) xor ca(114) xor ca(115) xor ca(117) xor ca(120) xor ca(122) xor ca(126) xor dq( 0);
ca( 1) <= ca( 64) xor ca( 65) xor ca( 68) xor ca( 71) xor ca( 72) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 77) xor ca( 79) xor ca( 81) xor ca( 84) xor ca( 85) xor ca( 88) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 97) xor ca(100) xor ca(101) xor ca(102) xor ca(107) xor ca(108) xor ca(109) xor ca(113) xor ca(114) xor ca(116) xor ca(117) xor ca(118) xor ca(120) xor ca(121) xor ca(122) xor ca(123) xor ca(126) xor ca(127) xor dq( 1);
ca( 2) <= ca( 65) xor ca( 66) xor ca( 69) xor ca( 72) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 78) xor ca( 80) xor ca( 82) xor ca( 85) xor ca( 86) xor ca( 89) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 98) xor ca(101) xor ca(102) xor ca(103) xor ca(108) xor ca(109) xor ca(110) xor ca(114) xor ca(115) xor ca(117) xor ca(118) xor ca(119) xor ca(121) xor ca(122) xor ca(123) xor ca(124) xor ca(127) xor dq( 2);
ca( 3) <= ca( 64) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 72) xor ca( 73) xor ca( 75) xor ca( 76) xor ca( 78) xor ca( 79) xor ca( 82) xor ca( 85) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 97) xor ca( 98) xor ca(101) xor ca(102) xor ca(103) xor ca(104) xor ca(107) xor ca(112) xor ca(114) xor ca(116) xor ca(117) xor ca(118) xor ca(119) xor ca(123) xor ca(124) xor ca(125) xor ca(126) xor dq( 3);
ca( 4) <= ca( 65) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 73) xor ca( 74) xor ca( 76) xor ca( 77) xor ca( 79) xor ca( 80) xor ca( 83) xor ca( 86) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 98) xor ca( 99) xor ca(102) xor ca(103) xor ca(104) xor ca(105) xor ca(108) xor ca(113) xor ca(115) xor ca(117) xor ca(118) xor ca(119) xor ca(120) xor ca(124) xor ca(125) xor ca(126) xor ca(127) xor dq( 4);
ca( 5) <= ca( 64) xor ca( 66) xor ca( 71) xor ca( 72) xor ca( 75) xor ca( 80) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 90) xor ca( 92) xor ca( 95) xor ca( 96) xor ca( 98) xor ca(100) xor ca(101) xor ca(103) xor ca(104) xor ca(105) xor ca(106) xor ca(107) xor ca(110) xor ca(111) xor ca(112) xor ca(115) xor ca(116) xor ca(117) xor ca(118) xor ca(119) xor ca(121) xor ca(122) xor ca(125) xor ca(127) xor dq( 5);
ca( 6) <= ca( 65) xor ca( 67) xor ca( 72) xor ca( 73) xor ca( 76) xor ca( 81) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 91) xor ca( 93) xor ca( 96) xor ca( 97) xor ca( 99) xor ca(101) xor ca(102) xor ca(104) xor ca(105) xor ca(106) xor ca(107) xor ca(108) xor ca(111) xor ca(112) xor ca(113) xor ca(116) xor ca(117) xor ca(118) xor ca(119) xor ca(120) xor ca(122) xor ca(123) xor ca(126) xor dq( 6);
ca( 7) <= ca( 66) xor ca( 68) xor ca( 73) xor ca( 74) xor ca( 77) xor ca( 82) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 92) xor ca( 94) xor ca( 97) xor ca( 98) xor ca(100) xor ca(102) xor ca(103) xor ca(105) xor ca(106) xor ca(107) xor ca(108) xor ca(109) xor ca(112) xor ca(113) xor ca(114) xor ca(117) xor ca(118) xor ca(119) xor ca(120) xor ca(121) xor ca(123) xor ca(124) xor ca(127) xor dq( 7);
ca( 8) <= ca( 67) xor ca( 69) xor ca( 74) xor ca( 75) xor ca( 78) xor ca( 83) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 93) xor ca( 95) xor ca( 98) xor ca( 99) xor ca(101) xor ca(103) xor ca(104) xor ca(106) xor ca(107) xor ca(108) xor ca(109) xor ca(110) xor ca(113) xor ca(114) xor ca(115) xor ca(118) xor ca(119) xor ca(120) xor ca(121) xor ca(122) xor ca(124) xor ca(125) xor dq( 8);
ca( 9) <= ca( 64) xor ca( 69) xor ca( 72) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 88) xor ca( 89) xor ca( 92) xor ca( 94) xor ca( 96) xor ca( 97) xor ca( 98) xor ca(100) xor ca(101) xor ca(102) xor ca(104) xor ca(105) xor ca(108) xor ca(112) xor ca(116) xor ca(117) xor ca(119) xor ca(121) xor ca(123) xor ca(125) xor dq( 9);
ca( 10) <= ca( 64) xor ca( 65) xor ca( 68) xor ca( 69) xor ca( 72) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 84) xor ca( 87) xor ca( 89) xor ca( 92) xor ca( 93) xor ca( 95) xor ca(102) xor ca(103) xor ca(105) xor ca(106) xor ca(107) xor ca(110) xor ca(111) xor ca(112) xor ca(113) xor ca(114) xor ca(115) xor ca(118) xor ca(124) xor dq( 10);
ca( 11) <= ca( 65) xor ca( 66) xor ca( 69) xor ca( 70) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 77) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 85) xor ca( 88) xor ca( 90) xor ca( 93) xor ca( 94) xor ca( 96) xor ca(103) xor ca(104) xor ca(106) xor ca(107) xor ca(108) xor ca(111) xor ca(112) xor ca(113) xor ca(114) xor ca(115) xor ca(116) xor ca(119) xor ca(125) xor dq( 11);
ca( 12) <= ca( 66) xor ca( 67) xor ca( 70) xor ca( 71) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 86) xor ca( 89) xor ca( 91) xor ca( 94) xor ca( 95) xor ca( 97) xor ca(104) xor ca(105) xor ca(107) xor ca(108) xor ca(109) xor ca(112) xor ca(113) xor ca(114) xor ca(115) xor ca(116) xor ca(117) xor ca(120) xor ca(126) xor dq( 12);
ca( 13) <= ca( 64) xor ca( 67) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 79) xor ca( 81) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 99) xor ca(101) xor ca(105) xor ca(106) xor ca(107) xor ca(108) xor ca(111) xor ca(112) xor ca(113) xor ca(116) xor ca(118) xor ca(120) xor ca(121) xor ca(122) xor ca(126) xor ca(127) xor dq( 13);
ca( 14) <= ca( 64) xor ca( 65) xor ca( 69) xor ca( 71) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 78) xor ca( 80) xor ca( 81) xor ca( 83) xor ca( 90) xor ca( 92) xor ca( 96) xor ca( 99) xor ca(100) xor ca(101) xor ca(102) xor ca(106) xor ca(108) xor ca(110) xor ca(111) xor ca(113) xor ca(115) xor ca(119) xor ca(120) xor ca(121) xor ca(123) xor ca(126) xor ca(127) xor dq( 14);
ca( 15) <= ca( 65) xor ca( 66) xor ca( 70) xor ca( 72) xor ca( 75) xor ca( 76) xor ca( 77) xor ca( 79) xor ca( 81) xor ca( 82) xor ca( 84) xor ca( 91) xor ca( 93) xor ca( 97) xor ca(100) xor ca(101) xor ca(102) xor ca(103) xor ca(107) xor ca(109) xor ca(111) xor ca(112) xor ca(114) xor ca(116) xor ca(120) xor ca(121) xor ca(122) xor ca(124) xor ca(127) xor dq( 15);
ca( 16) <= ca( 64) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 73) xor ca( 74) xor ca( 76) xor ca( 80) xor ca( 81) xor ca( 86) xor ca( 87) xor ca( 90) xor ca( 94) xor ca( 97) xor ca( 99) xor ca(102) xor ca(103) xor ca(104) xor ca(107) xor ca(108) xor ca(109) xor ca(111) xor ca(113) xor ca(114) xor ca(120) xor ca(121) xor ca(123) xor ca(125) xor ca(126) xor dq( 16);
ca( 17) <= ca( 65) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 77) xor ca( 81) xor ca( 82) xor ca( 87) xor ca( 88) xor ca( 91) xor ca( 95) xor ca( 98) xor ca(100) xor ca(103) xor ca(104) xor ca(105) xor ca(108) xor ca(109) xor ca(110) xor ca(112) xor ca(114) xor ca(115) xor ca(121) xor ca(122) xor ca(124) xor ca(126) xor ca(127) xor dq( 17);
ca( 18) <= ca( 66) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 78) xor ca( 82) xor ca( 83) xor ca( 88) xor ca( 89) xor ca( 92) xor ca( 96) xor ca( 99) xor ca(101) xor ca(104) xor ca(105) xor ca(106) xor ca(109) xor ca(110) xor ca(111) xor ca(113) xor ca(115) xor ca(116) xor ca(122) xor ca(123) xor ca(125) xor ca(127) xor dq( 18);
ca( 19) <= ca( 64) xor ca( 67) xor ca( 68) xor ca( 71) xor ca( 73) xor ca( 75) xor ca( 76) xor ca( 78) xor ca( 79) xor ca( 81) xor ca( 82) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 89) xor ca( 92) xor ca( 93) xor ca( 98) xor ca( 99) xor ca(100) xor ca(101) xor ca(102) xor ca(105) xor ca(106) xor ca(109) xor ca(115) xor ca(116) xor ca(120) xor ca(122) xor ca(123) xor ca(124) xor dq( 19);
ca( 20) <= ca( 64) xor ca( 65) xor ca( 70) xor ca( 76) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 88) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 97) xor ca( 98) xor ca(100) xor ca(102) xor ca(103) xor ca(106) xor ca(109) xor ca(111) xor ca(112) xor ca(114) xor ca(115) xor ca(116) xor ca(120) xor ca(121) xor ca(122) xor ca(123) xor ca(124) xor ca(125) xor ca(126) xor dq( 20);
ca( 21) <= ca( 64) xor ca( 65) xor ca( 66) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 74) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 83) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 89) xor ca( 90) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 97) xor ca(103) xor ca(104) xor ca(109) xor ca(111) xor ca(113) xor ca(114) xor ca(116) xor ca(120) xor ca(121) xor ca(123) xor ca(124) xor ca(125) xor ca(127) xor dq( 21);
ca( 22) <= ca( 64) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 71) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 88) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 99) xor ca(101) xor ca(104) xor ca(105) xor ca(107) xor ca(109) xor ca(111) xor ca(120) xor ca(121) xor ca(124) xor ca(125) xor dq( 22);
ca( 23) <= ca( 64) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 70) xor ca( 75) xor ca( 76) xor ca( 77) xor ca( 79) xor ca( 80) xor ca( 82) xor ca( 84) xor ca( 87) xor ca( 89) xor ca( 90) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 99) xor ca(100) xor ca(101) xor ca(102) xor ca(105) xor ca(106) xor ca(107) xor ca(108) xor ca(109) xor ca(111) xor ca(114) xor ca(115) xor ca(117) xor ca(120) xor ca(121) xor ca(125) xor dq( 23);
ca( 24) <= ca( 65) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 71) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 80) xor ca( 81) xor ca( 83) xor ca( 85) xor ca( 88) xor ca( 90) xor ca( 91) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 97) xor ca(100) xor ca(101) xor ca(102) xor ca(103) xor ca(106) xor ca(107) xor ca(108) xor ca(109) xor ca(110) xor ca(112) xor ca(115) xor ca(116) xor ca(118) xor ca(121) xor ca(122) xor ca(126) xor dq( 24);
ca( 25) <= ca( 66) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 72) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 81) xor ca( 82) xor ca( 84) xor ca( 86) xor ca( 89) xor ca( 91) xor ca( 92) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 98) xor ca(101) xor ca(102) xor ca(103) xor ca(104) xor ca(107) xor ca(108) xor ca(109) xor ca(110) xor ca(111) xor ca(113) xor ca(116) xor ca(117) xor ca(119) xor ca(122) xor ca(123) xor ca(127) xor dq( 25);
ca( 26) <= ca( 64) xor ca( 67) xor ca( 72) xor ca( 73) xor ca( 74) xor ca( 77) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 86) xor ca( 93) xor ca( 96) xor ca(101) xor ca(102) xor ca(103) xor ca(104) xor ca(105) xor ca(107) xor ca(108) xor ca(115) xor ca(118) xor ca(122) xor ca(123) xor ca(124) xor ca(126) xor dq( 26);
ca( 27) <= ca( 65) xor ca( 68) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 78) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 87) xor ca( 94) xor ca( 97) xor ca(102) xor ca(103) xor ca(104) xor ca(105) xor ca(106) xor ca(108) xor ca(109) xor ca(116) xor ca(119) xor ca(123) xor ca(124) xor ca(125) xor ca(127) xor dq( 27);
ca( 28) <= ca( 66) xor ca( 69) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 79) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 88) xor ca( 95) xor ca( 98) xor ca(103) xor ca(104) xor ca(105) xor ca(106) xor ca(107) xor ca(109) xor ca(110) xor ca(117) xor ca(120) xor ca(124) xor ca(125) xor ca(126) xor dq( 28);
ca( 29) <= ca( 67) xor ca( 70) xor ca( 75) xor ca( 76) xor ca( 77) xor ca( 80) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 89) xor ca( 96) xor ca( 99) xor ca(104) xor ca(105) xor ca(106) xor ca(107) xor ca(108) xor ca(110) xor ca(111) xor ca(118) xor ca(121) xor ca(125) xor ca(126) xor ca(127) xor dq( 29);
ca( 30) <= ca( 68) xor ca( 71) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 81) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 90) xor ca( 97) xor ca(100) xor ca(105) xor ca(106) xor ca(107) xor ca(108) xor ca(109) xor ca(111) xor ca(112) xor ca(119) xor ca(122) xor ca(126) xor ca(127) xor dq( 30);
ca( 31) <= ca( 69) xor ca( 72) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 82) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 91) xor ca( 98) xor ca(101) xor ca(106) xor ca(107) xor ca(108) xor ca(109) xor ca(110) xor ca(112) xor ca(113) xor ca(120) xor ca(123) xor ca(127) xor dq( 31);
ca( 32) <= ca( 64) xor ca( 68) xor ca( 69) xor ca( 72) xor ca( 73) xor ca( 74) xor ca( 77) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 90) xor ca( 97) xor ca( 98) xor ca(101) xor ca(102) xor ca(108) xor ca(112) xor ca(113) xor ca(115) xor ca(117) xor ca(120) xor ca(121) xor ca(122) xor ca(124) xor ca(126) xor dq( 32);
ca( 33) <= ca( 65) xor ca( 69) xor ca( 70) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 78) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 91) xor ca( 98) xor ca( 99) xor ca(102) xor ca(103) xor ca(109) xor ca(113) xor ca(114) xor ca(116) xor ca(118) xor ca(121) xor ca(122) xor ca(123) xor ca(125) xor ca(127) xor dq( 33);
ca( 34) <= ca( 64) xor ca( 66) xor ca( 68) xor ca( 69) xor ca( 71) xor ca( 72) xor ca( 75) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 90) xor ca( 97) xor ca( 98) xor ca(100) xor ca(101) xor ca(103) xor ca(104) xor ca(107) xor ca(109) xor ca(111) xor ca(112) xor ca(119) xor ca(120) xor ca(123) xor ca(124) xor dq( 34);
ca( 35) <= ca( 65) xor ca( 67) xor ca( 69) xor ca( 70) xor ca( 72) xor ca( 73) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 91) xor ca( 98) xor ca( 99) xor ca(101) xor ca(102) xor ca(104) xor ca(105) xor ca(108) xor ca(110) xor ca(112) xor ca(113) xor ca(120) xor ca(121) xor ca(124) xor ca(125) xor dq( 35);
ca( 36) <= ca( 64) xor ca( 66) xor ca( 69) xor ca( 71) xor ca( 72) xor ca( 73) xor ca( 79) xor ca( 80) xor ca( 82) xor ca( 83) xor ca( 85) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 97) xor ca( 98) xor ca(100) xor ca(101) xor ca(102) xor ca(103) xor ca(105) xor ca(106) xor ca(107) xor ca(110) xor ca(112) xor ca(113) xor ca(115) xor ca(117) xor ca(120) xor ca(121) xor ca(125) xor dq( 36);
ca( 37) <= ca( 64) xor ca( 65) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 73) xor ca( 77) xor ca( 78) xor ca( 80) xor ca( 82) xor ca( 84) xor ca( 85) xor ca( 87) xor ca( 89) xor ca( 91) xor ca( 92) xor ca( 97) xor ca(102) xor ca(103) xor ca(104) xor ca(106) xor ca(108) xor ca(109) xor ca(110) xor ca(112) xor ca(113) xor ca(115) xor ca(116) xor ca(117) xor ca(118) xor ca(120) xor ca(121) xor dq( 37);
ca( 38) <= ca( 64) xor ca( 65) xor ca( 66) xor ca( 72) xor ca( 77) xor ca( 79) xor ca( 82) xor ca( 87) xor ca( 88) xor ca( 93) xor ca( 97) xor ca( 99) xor ca(101) xor ca(103) xor ca(104) xor ca(105) xor ca(112) xor ca(113) xor ca(115) xor ca(116) xor ca(118) xor ca(119) xor ca(120) xor ca(121) xor ca(126) xor dq( 38);
ca( 39) <= ca( 65) xor ca( 66) xor ca( 67) xor ca( 73) xor ca( 78) xor ca( 80) xor ca( 83) xor ca( 88) xor ca( 89) xor ca( 94) xor ca( 98) xor ca(100) xor ca(102) xor ca(104) xor ca(105) xor ca(106) xor ca(113) xor ca(114) xor ca(116) xor ca(117) xor ca(119) xor ca(120) xor ca(121) xor ca(122) xor ca(127) xor dq( 39);
ca( 40) <= ca( 64) xor ca( 66) xor ca( 67) xor ca( 69) xor ca( 70) xor ca( 72) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 89) xor ca( 92) xor ca( 95) xor ca( 97) xor ca( 98) xor ca(103) xor ca(105) xor ca(106) xor ca(109) xor ca(110) xor ca(111) xor ca(112) xor ca(118) xor ca(121) xor ca(123) xor ca(126) xor dq( 40);
ca( 41) <= ca( 65) xor ca( 67) xor ca( 68) xor ca( 70) xor ca( 71) xor ca( 73) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 90) xor ca( 93) xor ca( 96) xor ca( 98) xor ca( 99) xor ca(104) xor ca(106) xor ca(107) xor ca(110) xor ca(111) xor ca(112) xor ca(113) xor ca(119) xor ca(122) xor ca(124) xor ca(127) xor dq( 41);
ca( 42) <= ca( 64) xor ca( 66) xor ca( 70) xor ca( 71) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 94) xor ca( 98) xor ca(100) xor ca(101) xor ca(105) xor ca(108) xor ca(109) xor ca(110) xor ca(113) xor ca(115) xor ca(117) xor ca(122) xor ca(123) xor ca(125) xor ca(126) xor dq( 42);
ca( 43) <= ca( 64) xor ca( 65) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 74) xor ca( 77) xor ca( 79) xor ca( 80) xor ca( 82) xor ca( 84) xor ca( 86) xor ca( 87) xor ca( 89) xor ca( 91) xor ca( 93) xor ca( 95) xor ca( 97) xor ca( 98) xor ca(102) xor ca(106) xor ca(107) xor ca(112) xor ca(115) xor ca(116) xor ca(117) xor ca(118) xor ca(120) xor ca(122) xor ca(123) xor ca(124) xor ca(127) xor dq( 43);
ca( 44) <= ca( 65) xor ca( 66) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 75) xor ca( 78) xor ca( 80) xor ca( 81) xor ca( 83) xor ca( 85) xor ca( 87) xor ca( 88) xor ca( 90) xor ca( 92) xor ca( 94) xor ca( 96) xor ca( 98) xor ca( 99) xor ca(103) xor ca(107) xor ca(108) xor ca(113) xor ca(116) xor ca(117) xor ca(118) xor ca(119) xor ca(121) xor ca(123) xor ca(124) xor ca(125) xor dq( 44);
ca( 45) <= ca( 64) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 71) xor ca( 73) xor ca( 74) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 95) xor ca( 98) xor ca(100) xor ca(101) xor ca(104) xor ca(107) xor ca(108) xor ca(110) xor ca(111) xor ca(112) xor ca(115) xor ca(118) xor ca(119) xor ca(124) xor ca(125) xor dq( 45);
ca( 46) <= ca( 64) xor ca( 65) xor ca( 67) xor ca( 70) xor ca( 75) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 91) xor ca( 93) xor ca( 94) xor ca( 96) xor ca( 97) xor ca( 98) xor ca(102) xor ca(105) xor ca(107) xor ca(108) xor ca(110) xor ca(113) xor ca(114) xor ca(115) xor ca(116) xor ca(117) xor ca(119) xor ca(122) xor ca(125) xor dq( 46);
ca( 47) <= ca( 65) xor ca( 66) xor ca( 68) xor ca( 71) xor ca( 76) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 92) xor ca( 94) xor ca( 95) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(103) xor ca(106) xor ca(108) xor ca(109) xor ca(111) xor ca(114) xor ca(115) xor ca(116) xor ca(117) xor ca(118) xor ca(120) xor ca(123) xor ca(126) xor dq( 47);
ca( 48) <= ca( 66) xor ca( 67) xor ca( 69) xor ca( 72) xor ca( 77) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 93) xor ca( 95) xor ca( 96) xor ca( 98) xor ca( 99) xor ca(100) xor ca(104) xor ca(107) xor ca(109) xor ca(110) xor ca(112) xor ca(115) xor ca(116) xor ca(117) xor ca(118) xor ca(119) xor ca(121) xor ca(124) xor ca(127) xor dq( 48);
ca( 49) <= ca( 67) xor ca( 68) xor ca( 70) xor ca( 73) xor ca( 78) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 94) xor ca( 96) xor ca( 97) xor ca( 99) xor ca(100) xor ca(101) xor ca(105) xor ca(108) xor ca(110) xor ca(111) xor ca(113) xor ca(116) xor ca(117) xor ca(118) xor ca(119) xor ca(120) xor ca(122) xor ca(125) xor dq( 49);
ca( 50) <= ca( 64) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 81) xor ca( 82) xor ca( 84) xor ca( 88) xor ca( 90) xor ca( 91) xor ca( 93) xor ca( 95) xor ca( 99) xor ca(100) xor ca(102) xor ca(106) xor ca(107) xor ca(110) xor ca(115) xor ca(118) xor ca(119) xor ca(121) xor ca(122) xor ca(123) xor dq( 50);
ca( 51) <= ca( 64) xor ca( 65) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 73) xor ca( 74) xor ca( 77) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 86) xor ca( 87) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 94) xor ca( 96) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(100) xor ca(103) xor ca(108) xor ca(109) xor ca(110) xor ca(112) xor ca(114) xor ca(115) xor ca(116) xor ca(117) xor ca(119) xor ca(123) xor ca(124) xor ca(126) xor dq( 51);
ca( 52) <= ca( 64) xor ca( 65) xor ca( 66) xor ca( 68) xor ca( 71) xor ca( 75) xor ca( 77) xor ca( 80) xor ca( 83) xor ca( 85) xor ca( 86) xor ca( 88) xor ca( 91) xor ca( 95) xor ca(100) xor ca(104) xor ca(107) xor ca(112) xor ca(113) xor ca(114) xor ca(116) xor ca(118) xor ca(122) xor ca(124) xor ca(125) xor ca(126) xor ca(127) xor dq( 52);
ca( 53) <= ca( 64) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 70) xor ca( 74) xor ca( 76) xor ca( 77) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 89) xor ca( 90) xor ca( 96) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(105) xor ca(107) xor ca(108) xor ca(109) xor ca(110) xor ca(111) xor ca(112) xor ca(113) xor ca(119) xor ca(120) xor ca(122) xor ca(123) xor ca(125) xor ca(127) xor dq( 53);
ca( 54) <= ca( 64) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 74) xor ca( 75) xor ca( 81) xor ca( 82) xor ca( 84) xor ca( 87) xor ca( 91) xor ca( 92) xor ca(100) xor ca(101) xor ca(106) xor ca(107) xor ca(108) xor ca(113) xor ca(115) xor ca(117) xor ca(121) xor ca(122) xor ca(123) xor ca(124) xor dq( 54);
ca( 55) <= ca( 64) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 81) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 90) xor ca( 93) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(102) xor ca(108) xor ca(110) xor ca(111) xor ca(112) xor ca(115) xor ca(116) xor ca(117) xor ca(118) xor ca(120) xor ca(123) xor ca(124) xor ca(125) xor ca(126) xor dq( 55);
ca( 56) <= ca( 64) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 69) xor ca( 71) xor ca( 75) xor ca( 76) xor ca( 79) xor ca( 81) xor ca( 83) xor ca( 85) xor ca( 86) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 94) xor ca( 97) xor ca(100) xor ca(101) xor ca(103) xor ca(107) xor ca(110) xor ca(113) xor ca(114) xor ca(115) xor ca(116) xor ca(118) xor ca(119) xor ca(120) xor ca(121) xor ca(122) xor ca(124) xor ca(125) xor ca(127) xor dq( 56);
ca( 57) <= ca( 65) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 70) xor ca( 72) xor ca( 76) xor ca( 77) xor ca( 80) xor ca( 82) xor ca( 84) xor ca( 86) xor ca( 87) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 95) xor ca( 98) xor ca(101) xor ca(102) xor ca(104) xor ca(108) xor ca(111) xor ca(114) xor ca(115) xor ca(116) xor ca(117) xor ca(119) xor ca(120) xor ca(121) xor ca(122) xor ca(123) xor ca(125) xor ca(126) xor dq( 57);
ca( 58) <= ca( 66) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 71) xor ca( 73) xor ca( 77) xor ca( 78) xor ca( 81) xor ca( 83) xor ca( 85) xor ca( 87) xor ca( 88) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 96) xor ca( 99) xor ca(102) xor ca(103) xor ca(105) xor ca(109) xor ca(112) xor ca(115) xor ca(116) xor ca(117) xor ca(118) xor ca(120) xor ca(121) xor ca(122) xor ca(123) xor ca(124) xor ca(126) xor ca(127) xor dq( 58);
ca( 59) <= ca( 64) xor ca( 67) xor ca( 77) xor ca( 79) xor ca( 81) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 98) xor ca( 99) xor ca(100) xor ca(101) xor ca(103) xor ca(104) xor ca(106) xor ca(107) xor ca(109) xor ca(111) xor ca(112) xor ca(113) xor ca(114) xor ca(115) xor ca(116) xor ca(118) xor ca(119) xor ca(120) xor ca(121) xor ca(123) xor ca(124) xor ca(125) xor ca(126) xor ca(127) xor dq( 59);
ca( 60) <= ca( 64) xor ca( 65) xor ca( 69) xor ca( 70) xor ca( 72) xor ca( 74) xor ca( 77) xor ca( 80) xor ca( 81) xor ca( 83) xor ca( 84) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 91) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 98) xor ca(100) xor ca(102) xor ca(104) xor ca(105) xor ca(108) xor ca(109) xor ca(111) xor ca(113) xor ca(116) xor ca(119) xor ca(121) xor ca(124) xor ca(125) xor ca(127) xor dq( 60);
ca( 61) <= ca( 65) xor ca( 66) xor ca( 70) xor ca( 71) xor ca( 73) xor ca( 75) xor ca( 78) xor ca( 81) xor ca( 82) xor ca( 84) xor ca( 85) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 92) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(101) xor ca(103) xor ca(105) xor ca(106) xor ca(109) xor ca(110) xor ca(112) xor ca(114) xor ca(117) xor ca(120) xor ca(122) xor ca(125) xor ca(126) xor dq( 61);
ca( 62) <= ca( 66) xor ca( 67) xor ca( 71) xor ca( 72) xor ca( 74) xor ca( 76) xor ca( 79) xor ca( 82) xor ca( 83) xor ca( 85) xor ca( 86) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 93) xor ca( 96) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(100) xor ca(102) xor ca(104) xor ca(106) xor ca(107) xor ca(110) xor ca(111) xor ca(113) xor ca(115) xor ca(118) xor ca(121) xor ca(123) xor ca(126) xor ca(127) xor dq( 62);
ca( 63) <= ca( 67) xor ca( 68) xor ca( 72) xor ca( 73) xor ca( 75) xor ca( 77) xor ca( 80) xor ca( 83) xor ca( 84) xor ca( 86) xor ca( 87) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 94) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(100) xor ca(101) xor ca(103) xor ca(105) xor ca(107) xor ca(108) xor ca(111) xor ca(112) xor ca(114) xor ca(116) xor ca(119) xor ca(122) xor ca(124) xor ca(127) xor dq( 63);
ca( 64) <= ca( 0) xor ca( 64) xor ca( 70) xor ca( 72) xor ca( 73) xor ca( 76) xor ca( 77) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 86) xor ca( 88) xor ca( 90) xor ca( 91) xor ca( 93) xor ca( 95) xor ca( 97) xor ca(100) xor ca(102) xor ca(104) xor ca(106) xor ca(107) xor ca(108) xor ca(110) xor ca(111) xor ca(113) xor ca(114) xor ca(122) xor ca(123) xor ca(125) xor ca(126) xor dq( 64);
ca( 65) <= ca( 1) xor ca( 65) xor ca( 71) xor ca( 73) xor ca( 74) xor ca( 77) xor ca( 78) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 87) xor ca( 89) xor ca( 91) xor ca( 92) xor ca( 94) xor ca( 96) xor ca( 98) xor ca(101) xor ca(103) xor ca(105) xor ca(107) xor ca(108) xor ca(109) xor ca(111) xor ca(112) xor ca(114) xor ca(115) xor ca(123) xor ca(124) xor ca(126) xor ca(127) xor dq( 65);
ca( 66) <= ca( 2) xor ca( 64) xor ca( 66) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 75) xor ca( 77) xor ca( 79) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 87) xor ca( 88) xor ca( 93) xor ca( 95) xor ca( 98) xor ca(101) xor ca(102) xor ca(104) xor ca(106) xor ca(107) xor ca(108) xor ca(111) xor ca(113) xor ca(114) xor ca(116) xor ca(117) xor ca(120) xor ca(122) xor ca(124) xor ca(125) xor ca(126) xor ca(127) xor dq( 66);
ca( 67) <= ca( 3) xor ca( 64) xor ca( 65) xor ca( 67) xor ca( 68) xor ca( 71) xor ca( 72) xor ca( 74) xor ca( 76) xor ca( 77) xor ca( 80) xor ca( 81) xor ca( 84) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 92) xor ca( 94) xor ca( 96) xor ca( 97) xor ca( 98) xor ca(101) xor ca(102) xor ca(103) xor ca(105) xor ca(108) xor ca(110) xor ca(111) xor ca(118) xor ca(120) xor ca(121) xor ca(122) xor ca(123) xor ca(125) xor ca(127) xor dq( 67);
ca( 68) <= ca( 4) xor ca( 64) xor ca( 65) xor ca( 66) xor ca( 70) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 83) xor ca( 86) xor ca( 88) xor ca( 89) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 95) xor ca(101) xor ca(102) xor ca(103) xor ca(104) xor ca(106) xor ca(107) xor ca(110) xor ca(114) xor ca(115) xor ca(117) xor ca(119) xor ca(120) xor ca(121) xor ca(123) xor ca(124) xor dq( 68);
ca( 69) <= ca( 5) xor ca( 64) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 75) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 89) xor ca( 93) xor ca( 94) xor ca( 96) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(101) xor ca(102) xor ca(103) xor ca(104) xor ca(105) xor ca(108) xor ca(109) xor ca(110) xor ca(112) xor ca(114) xor ca(116) xor ca(117) xor ca(118) xor ca(121) xor ca(124) xor ca(125) xor ca(126) xor dq( 69);
ca( 70) <= ca( 6) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 73) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 90) xor ca( 94) xor ca( 95) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(100) xor ca(102) xor ca(103) xor ca(104) xor ca(105) xor ca(106) xor ca(109) xor ca(110) xor ca(111) xor ca(113) xor ca(115) xor ca(117) xor ca(118) xor ca(119) xor ca(122) xor ca(125) xor ca(126) xor ca(127) xor dq( 70);
ca( 71) <= ca( 7) xor ca( 64) xor ca( 66) xor ca( 67) xor ca( 71) xor ca( 73) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 84) xor ca( 88) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 95) xor ca( 96) xor ca( 97) xor ca(100) xor ca(103) xor ca(104) xor ca(105) xor ca(106) xor ca(109) xor ca(115) xor ca(116) xor ca(117) xor ca(118) xor ca(119) xor ca(122) xor ca(123) xor ca(127) xor dq( 71);
ca( 72) <= ca( 8) xor ca( 64) xor ca( 65) xor ca( 67) xor ca( 69) xor ca( 70) xor ca( 77) xor ca( 78) xor ca( 80) xor ca( 86) xor ca( 87) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 93) xor ca( 96) xor ca( 99) xor ca(104) xor ca(105) xor ca(106) xor ca(109) xor ca(111) xor ca(112) xor ca(114) xor ca(115) xor ca(116) xor ca(118) xor ca(119) xor ca(122) xor ca(123) xor ca(124) xor ca(126) xor dq( 72);
ca( 73) <= ca( 9) xor ca( 64) xor ca( 65) xor ca( 66) xor ca( 69) xor ca( 71) xor ca( 72) xor ca( 74) xor ca( 77) xor ca( 79) xor ca( 82) xor ca( 83) xor ca( 85) xor ca( 86) xor ca( 88) xor ca( 91) xor ca( 94) xor ca( 98) xor ca( 99) xor ca(100) xor ca(101) xor ca(105) xor ca(106) xor ca(109) xor ca(111) xor ca(113) xor ca(114) xor ca(116) xor ca(119) xor ca(122) xor ca(123) xor ca(124) xor ca(125) xor ca(126) xor ca(127) xor dq( 73);
ca( 74) <= ca( 10) xor ca( 64) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 77) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 84) xor ca( 85) xor ca( 89) xor ca( 90) xor ca( 95) xor ca( 97) xor ca( 98) xor ca(100) xor ca(102) xor ca(106) xor ca(109) xor ca(111) xor ca(122) xor ca(123) xor ca(124) xor ca(125) xor ca(127) xor dq( 74);
ca( 75) <= ca( 11) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 78) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 85) xor ca( 86) xor ca( 90) xor ca( 91) xor ca( 96) xor ca( 98) xor ca( 99) xor ca(101) xor ca(103) xor ca(107) xor ca(110) xor ca(112) xor ca(123) xor ca(124) xor ca(125) xor ca(126) xor dq( 75);
ca( 76) <= ca( 12) xor ca( 64) xor ca( 66) xor ca( 67) xor ca( 71) xor ca( 72) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 78) xor ca( 79) xor ca( 81) xor ca( 84) xor ca( 85) xor ca( 90) xor ca( 91) xor ca( 98) xor ca(100) xor ca(101) xor ca(102) xor ca(104) xor ca(107) xor ca(108) xor ca(109) xor ca(110) xor ca(112) xor ca(113) xor ca(114) xor ca(115) xor ca(117) xor ca(120) xor ca(122) xor ca(124) xor ca(125) xor ca(127) xor dq( 76);
ca( 77) <= ca( 13) xor ca( 65) xor ca( 67) xor ca( 68) xor ca( 72) xor ca( 73) xor ca( 75) xor ca( 76) xor ca( 77) xor ca( 79) xor ca( 80) xor ca( 82) xor ca( 85) xor ca( 86) xor ca( 91) xor ca( 92) xor ca( 99) xor ca(101) xor ca(102) xor ca(103) xor ca(105) xor ca(108) xor ca(109) xor ca(110) xor ca(111) xor ca(113) xor ca(114) xor ca(115) xor ca(116) xor ca(118) xor ca(121) xor ca(123) xor ca(125) xor ca(126) xor dq( 77);
ca( 78) <= ca( 14) xor ca( 66) xor ca( 68) xor ca( 69) xor ca( 73) xor ca( 74) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 80) xor ca( 81) xor ca( 83) xor ca( 86) xor ca( 87) xor ca( 92) xor ca( 93) xor ca(100) xor ca(102) xor ca(103) xor ca(104) xor ca(106) xor ca(109) xor ca(110) xor ca(111) xor ca(112) xor ca(114) xor ca(115) xor ca(116) xor ca(117) xor ca(119) xor ca(122) xor ca(124) xor ca(126) xor ca(127) xor dq( 78);
ca( 79) <= ca( 15) xor ca( 64) xor ca( 67) xor ca( 68) xor ca( 72) xor ca( 75) xor ca( 79) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 88) xor ca( 90) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(103) xor ca(104) xor ca(105) xor ca(109) xor ca(113) xor ca(114) xor ca(116) xor ca(118) xor ca(122) xor ca(123) xor ca(125) xor ca(126) xor ca(127) xor dq( 79);
ca( 80) <= ca( 16) xor ca( 64) xor ca( 65) xor ca( 70) xor ca( 72) xor ca( 73) xor ca( 74) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 97) xor ca(100) xor ca(101) xor ca(104) xor ca(105) xor ca(106) xor ca(107) xor ca(109) xor ca(111) xor ca(112) xor ca(119) xor ca(120) xor ca(122) xor ca(123) xor ca(124) xor ca(127) xor dq( 80);
ca( 81) <= ca( 17) xor ca( 64) xor ca( 65) xor ca( 66) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 73) xor ca( 75) xor ca( 79) xor ca( 84) xor ca( 86) xor ca( 87) xor ca( 91) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 99) xor ca(102) xor ca(105) xor ca(106) xor ca(108) xor ca(109) xor ca(111) xor ca(113) xor ca(114) xor ca(115) xor ca(117) xor ca(121) xor ca(122) xor ca(123) xor ca(124) xor ca(125) xor ca(126) xor dq( 81);
ca( 82) <= ca( 18) xor ca( 64) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 71) xor ca( 73) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 86) xor ca( 88) xor ca( 90) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 99) xor ca(100) xor ca(101) xor ca(103) xor ca(106) xor ca(111) xor ca(116) xor ca(117) xor ca(118) xor ca(120) xor ca(123) xor ca(124) xor ca(125) xor ca(127) xor dq( 82);
ca( 83) <= ca( 19) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 72) xor ca( 74) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 87) xor ca( 89) xor ca( 91) xor ca( 95) xor ca( 96) xor ca( 97) xor ca(100) xor ca(101) xor ca(102) xor ca(104) xor ca(107) xor ca(112) xor ca(117) xor ca(118) xor ca(119) xor ca(121) xor ca(124) xor ca(125) xor ca(126) xor dq( 83);
ca( 84) <= ca( 20) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 73) xor ca( 75) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 88) xor ca( 90) xor ca( 92) xor ca( 96) xor ca( 97) xor ca( 98) xor ca(101) xor ca(102) xor ca(103) xor ca(105) xor ca(108) xor ca(113) xor ca(118) xor ca(119) xor ca(120) xor ca(122) xor ca(125) xor ca(126) xor ca(127) xor dq( 84);
ca( 85) <= ca( 21) xor ca( 64) xor ca( 67) xor ca( 71) xor ca( 72) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 82) xor ca( 84) xor ca( 87) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 93) xor ca(101) xor ca(102) xor ca(103) xor ca(104) xor ca(106) xor ca(107) xor ca(110) xor ca(111) xor ca(112) xor ca(115) xor ca(117) xor ca(119) xor ca(121) xor ca(122) xor ca(123) xor ca(127) xor dq( 85);
ca( 86) <= ca( 22) xor ca( 65) xor ca( 68) xor ca( 72) xor ca( 73) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 83) xor ca( 85) xor ca( 88) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 94) xor ca(102) xor ca(103) xor ca(104) xor ca(105) xor ca(107) xor ca(108) xor ca(111) xor ca(112) xor ca(113) xor ca(116) xor ca(118) xor ca(120) xor ca(122) xor ca(123) xor ca(124) xor dq( 86);
ca( 87) <= ca( 23) xor ca( 66) xor ca( 69) xor ca( 73) xor ca( 74) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 84) xor ca( 86) xor ca( 89) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 95) xor ca(103) xor ca(104) xor ca(105) xor ca(106) xor ca(108) xor ca(109) xor ca(112) xor ca(113) xor ca(114) xor ca(117) xor ca(119) xor ca(121) xor ca(123) xor ca(124) xor ca(125) xor dq( 87);
ca( 88) <= ca( 24) xor ca( 64) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 72) xor ca( 75) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 86) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(101) xor ca(104) xor ca(105) xor ca(106) xor ca(111) xor ca(112) xor ca(113) xor ca(117) xor ca(118) xor ca(124) xor ca(125) xor dq( 88);
ca( 89) <= ca( 25) xor ca( 65) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 73) xor ca( 76) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 87) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(100) xor ca(102) xor ca(105) xor ca(106) xor ca(107) xor ca(112) xor ca(113) xor ca(114) xor ca(118) xor ca(119) xor ca(125) xor ca(126) xor dq( 89);
ca( 90) <= ca( 26) xor ca( 66) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 74) xor ca( 77) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 88) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(100) xor ca(101) xor ca(103) xor ca(106) xor ca(107) xor ca(108) xor ca(113) xor ca(114) xor ca(115) xor ca(119) xor ca(120) xor ca(126) xor ca(127) xor dq( 90);
ca( 91) <= ca( 27) xor ca( 67) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 75) xor ca( 78) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 89) xor ca( 96) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(100) xor ca(101) xor ca(102) xor ca(104) xor ca(107) xor ca(108) xor ca(109) xor ca(114) xor ca(115) xor ca(116) xor ca(120) xor ca(121) xor ca(127) xor dq( 91);
ca( 92) <= ca( 28) xor ca( 64) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 73) xor ca( 74) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 92) xor ca(100) xor ca(102) xor ca(103) xor ca(105) xor ca(107) xor ca(108) xor ca(111) xor ca(112) xor ca(114) xor ca(116) xor ca(120) xor ca(121) xor ca(126) xor dq( 92);
ca( 93) <= ca( 29) xor ca( 64) xor ca( 65) xor ca( 68) xor ca( 69) xor ca( 71) xor ca( 75) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 88) xor ca( 90) xor ca( 92) xor ca( 93) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(103) xor ca(104) xor ca(106) xor ca(107) xor ca(108) xor ca(110) xor ca(111) xor ca(113) xor ca(114) xor ca(120) xor ca(121) xor ca(126) xor ca(127) xor dq( 93);
ca( 94) <= ca( 30) xor ca( 64) xor ca( 65) xor ca( 66) xor ca( 68) xor ca( 74) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 80) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 97) xor ca(100) xor ca(101) xor ca(104) xor ca(105) xor ca(108) xor ca(110) xor ca(117) xor ca(120) xor ca(121) xor ca(126) xor ca(127) xor dq( 94);
ca( 95) <= ca( 31) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 69) xor ca( 75) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 81) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 98) xor ca(101) xor ca(102) xor ca(105) xor ca(106) xor ca(109) xor ca(111) xor ca(118) xor ca(121) xor ca(122) xor ca(127) xor dq( 95);
ca( 96) <= ca( 32) xor ca( 64) xor ca( 66) xor ca( 67) xor ca( 69) xor ca( 72) xor ca( 74) xor ca( 76) xor ca( 77) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 83) xor ca( 85) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 98) xor ca(101) xor ca(102) xor ca(103) xor ca(106) xor ca(109) xor ca(111) xor ca(114) xor ca(115) xor ca(117) xor ca(119) xor ca(120) xor ca(123) xor ca(126) xor dq( 96);
ca( 97) <= ca( 33) xor ca( 64) xor ca( 65) xor ca( 67) xor ca( 69) xor ca( 72) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 80) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 87) xor ca( 89) xor ca( 91) xor ca( 94) xor ca( 95) xor ca( 96) xor ca(101) xor ca(102) xor ca(103) xor ca(104) xor ca(109) xor ca(111) xor ca(114) xor ca(116) xor ca(117) xor ca(118) xor ca(121) xor ca(122) xor ca(124) xor ca(126) xor ca(127) xor dq( 97);
ca( 98) <= ca( 34) xor ca( 64) xor ca( 65) xor ca( 66) xor ca( 69) xor ca( 72) xor ca( 73) xor ca( 75) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 87) xor ca( 88) xor ca( 95) xor ca( 96) xor ca( 98) xor ca( 99) xor ca(101) xor ca(102) xor ca(103) xor ca(104) xor ca(105) xor ca(107) xor ca(109) xor ca(111) xor ca(114) xor ca(118) xor ca(119) xor ca(120) xor ca(123) xor ca(125) xor ca(126) xor ca(127) xor dq( 98);
ca( 99) <= ca( 35) xor ca( 64) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 72) xor ca( 73) xor ca( 76) xor ca( 79) xor ca( 81) xor ca( 82) xor ca( 84) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 92) xor ca( 96) xor ca( 98) xor ca(100) xor ca(101) xor ca(102) xor ca(103) xor ca(104) xor ca(105) xor ca(106) xor ca(107) xor ca(108) xor ca(109) xor ca(111) xor ca(114) xor ca(117) xor ca(119) xor ca(121) xor ca(122) xor ca(124) xor ca(127) xor dq( 99);
ca(100) <= ca( 36) xor ca( 64) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 72) xor ca( 73) xor ca( 78) xor ca( 80) xor ca( 81) xor ca( 86) xor ca( 88) xor ca( 89) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 98) xor ca(102) xor ca(103) xor ca(104) xor ca(105) xor ca(106) xor ca(108) xor ca(111) xor ca(114) xor ca(117) xor ca(118) xor ca(123) xor ca(125) xor ca(126) xor dq(100);
ca(101) <= ca( 37) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 73) xor ca( 74) xor ca( 79) xor ca( 81) xor ca( 82) xor ca( 87) xor ca( 89) xor ca( 90) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 99) xor ca(103) xor ca(104) xor ca(105) xor ca(106) xor ca(107) xor ca(109) xor ca(112) xor ca(115) xor ca(118) xor ca(119) xor ca(124) xor ca(126) xor ca(127) xor dq(101);
ca(102) <= ca( 38) xor ca( 64) xor ca( 66) xor ca( 67) xor ca( 70) xor ca( 72) xor ca( 75) xor ca( 77) xor ca( 78) xor ca( 80) xor ca( 81) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(100) xor ca(101) xor ca(104) xor ca(105) xor ca(106) xor ca(108) xor ca(109) xor ca(111) xor ca(112) xor ca(113) xor ca(114) xor ca(115) xor ca(116) xor ca(117) xor ca(119) xor ca(122) xor ca(125) xor ca(126) xor ca(127) xor dq(102);
ca(103) <= ca( 39) xor ca( 65) xor ca( 67) xor ca( 68) xor ca( 71) xor ca( 73) xor ca( 76) xor ca( 78) xor ca( 79) xor ca( 81) xor ca( 82) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 98) xor ca( 99) xor ca(100) xor ca(101) xor ca(102) xor ca(105) xor ca(106) xor ca(107) xor ca(109) xor ca(110) xor ca(112) xor ca(113) xor ca(114) xor ca(115) xor ca(116) xor ca(117) xor ca(118) xor ca(120) xor ca(123) xor ca(126) xor ca(127) xor dq(103);
ca(104) <= ca( 40) xor ca( 64) xor ca( 66) xor ca( 70) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 85) xor ca( 86) xor ca( 88) xor ca( 89) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 98) xor ca(100) xor ca(102) xor ca(103) xor ca(106) xor ca(108) xor ca(109) xor ca(112) xor ca(113) xor ca(116) xor ca(118) xor ca(119) xor ca(120) xor ca(121) xor ca(122) xor ca(124) xor ca(126) xor ca(127) xor dq(104);
ca(105) <= ca( 41) xor ca( 65) xor ca( 67) xor ca( 71) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 86) xor ca( 87) xor ca( 89) xor ca( 90) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 99) xor ca(101) xor ca(103) xor ca(104) xor ca(107) xor ca(109) xor ca(110) xor ca(113) xor ca(114) xor ca(117) xor ca(119) xor ca(120) xor ca(121) xor ca(122) xor ca(123) xor ca(125) xor ca(127) xor dq(105);
ca(106) <= ca( 42) xor ca( 64) xor ca( 66) xor ca( 69) xor ca( 70) xor ca( 74) xor ca( 77) xor ca( 78) xor ca( 80) xor ca( 85) xor ca( 86) xor ca( 88) xor ca( 91) xor ca( 92) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 99) xor ca(100) xor ca(101) xor ca(102) xor ca(104) xor ca(105) xor ca(107) xor ca(108) xor ca(109) xor ca(112) xor ca(117) xor ca(118) xor ca(121) xor ca(123) xor ca(124) xor dq(106);
ca(107) <= ca( 43) xor ca( 65) xor ca( 67) xor ca( 70) xor ca( 71) xor ca( 75) xor ca( 78) xor ca( 79) xor ca( 81) xor ca( 86) xor ca( 87) xor ca( 89) xor ca( 92) xor ca( 93) xor ca( 95) xor ca( 96) xor ca( 97) xor ca(100) xor ca(101) xor ca(102) xor ca(103) xor ca(105) xor ca(106) xor ca(108) xor ca(109) xor ca(110) xor ca(113) xor ca(118) xor ca(119) xor ca(122) xor ca(124) xor ca(125) xor dq(107);
ca(108) <= ca( 44) xor ca( 66) xor ca( 68) xor ca( 71) xor ca( 72) xor ca( 76) xor ca( 79) xor ca( 80) xor ca( 82) xor ca( 87) xor ca( 88) xor ca( 90) xor ca( 93) xor ca( 94) xor ca( 96) xor ca( 97) xor ca( 98) xor ca(101) xor ca(102) xor ca(103) xor ca(104) xor ca(106) xor ca(107) xor ca(109) xor ca(110) xor ca(111) xor ca(114) xor ca(119) xor ca(120) xor ca(123) xor ca(125) xor ca(126) xor dq(108);
ca(109) <= ca( 45) xor ca( 64) xor ca( 67) xor ca( 68) xor ca( 70) xor ca( 73) xor ca( 74) xor ca( 78) xor ca( 80) xor ca( 82) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 94) xor ca( 95) xor ca(101) xor ca(102) xor ca(103) xor ca(104) xor ca(105) xor ca(108) xor ca(109) xor ca(114) xor ca(117) xor ca(121) xor ca(122) xor ca(124) xor ca(127) xor dq(109);
ca(110) <= ca( 46) xor ca( 65) xor ca( 68) xor ca( 69) xor ca( 71) xor ca( 74) xor ca( 75) xor ca( 79) xor ca( 81) xor ca( 83) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 95) xor ca( 96) xor ca(102) xor ca(103) xor ca(104) xor ca(105) xor ca(106) xor ca(109) xor ca(110) xor ca(115) xor ca(118) xor ca(122) xor ca(123) xor ca(125) xor dq(110);
ca(111) <= ca( 47) xor ca( 66) xor ca( 69) xor ca( 70) xor ca( 72) xor ca( 75) xor ca( 76) xor ca( 80) xor ca( 82) xor ca( 84) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 96) xor ca( 97) xor ca(103) xor ca(104) xor ca(105) xor ca(106) xor ca(107) xor ca(110) xor ca(111) xor ca(116) xor ca(119) xor ca(123) xor ca(124) xor ca(126) xor dq(111);
ca(112) <= ca( 48) xor ca( 64) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 71) xor ca( 72) xor ca( 73) xor ca( 74) xor ca( 76) xor ca( 78) xor ca( 82) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 91) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 99) xor ca(101) xor ca(104) xor ca(105) xor ca(106) xor ca(108) xor ca(109) xor ca(110) xor ca(114) xor ca(115) xor ca(122) xor ca(124) xor ca(125) xor ca(126) xor ca(127) xor dq(112);
ca(113) <= ca( 49) xor ca( 64) xor ca( 65) xor ca( 73) xor ca( 75) xor ca( 78) xor ca( 79) xor ca( 81) xor ca( 82) xor ca( 85) xor ca( 86) xor ca( 88) xor ca( 89) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(100) xor ca(101) xor ca(102) xor ca(105) xor ca(106) xor ca(112) xor ca(114) xor ca(116) xor ca(117) xor ca(120) xor ca(122) xor ca(123) xor ca(125) xor ca(127) xor dq(113);
ca(114) <= ca( 50) xor ca( 64) xor ca( 65) xor ca( 66) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 72) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 85) xor ca( 89) xor ca( 92) xor ca( 95) xor ca( 96) xor ca(100) xor ca(102) xor ca(103) xor ca(106) xor ca(109) xor ca(110) xor ca(111) xor ca(112) xor ca(113) xor ca(114) xor ca(118) xor ca(120) xor ca(121) xor ca(122) xor ca(123) xor ca(124) xor dq(114);
ca(115) <= ca( 51) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 73) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 86) xor ca( 90) xor ca( 93) xor ca( 96) xor ca( 97) xor ca(101) xor ca(103) xor ca(104) xor ca(107) xor ca(110) xor ca(111) xor ca(112) xor ca(113) xor ca(114) xor ca(115) xor ca(119) xor ca(121) xor ca(122) xor ca(123) xor ca(124) xor ca(125) xor dq(115);
ca(116) <= ca( 52) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 74) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 87) xor ca( 91) xor ca( 94) xor ca( 97) xor ca( 98) xor ca(102) xor ca(104) xor ca(105) xor ca(108) xor ca(111) xor ca(112) xor ca(113) xor ca(114) xor ca(115) xor ca(116) xor ca(120) xor ca(122) xor ca(123) xor ca(124) xor ca(125) xor ca(126) xor dq(116);
ca(117) <= ca( 53) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 71) xor ca( 72) xor ca( 73) xor ca( 75) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 88) xor ca( 92) xor ca( 95) xor ca( 98) xor ca( 99) xor ca(103) xor ca(105) xor ca(106) xor ca(109) xor ca(112) xor ca(113) xor ca(114) xor ca(115) xor ca(116) xor ca(117) xor ca(121) xor ca(123) xor ca(124) xor ca(125) xor ca(126) xor ca(127) xor dq(117);
ca(118) <= ca( 54) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 72) xor ca( 73) xor ca( 74) xor ca( 76) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 89) xor ca( 93) xor ca( 96) xor ca( 99) xor ca(100) xor ca(104) xor ca(106) xor ca(107) xor ca(110) xor ca(113) xor ca(114) xor ca(115) xor ca(116) xor ca(117) xor ca(118) xor ca(122) xor ca(124) xor ca(125) xor ca(126) xor ca(127) xor dq(118);
ca(119) <= ca( 55) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 77) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 90) xor ca( 94) xor ca( 97) xor ca(100) xor ca(101) xor ca(105) xor ca(107) xor ca(108) xor ca(111) xor ca(114) xor ca(115) xor ca(116) xor ca(117) xor ca(118) xor ca(119) xor ca(123) xor ca(125) xor ca(126) xor ca(127) xor dq(119);
ca(120) <= ca( 56) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 78) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 91) xor ca( 95) xor ca( 98) xor ca(101) xor ca(102) xor ca(106) xor ca(108) xor ca(109) xor ca(112) xor ca(115) xor ca(116) xor ca(117) xor ca(118) xor ca(119) xor ca(120) xor ca(124) xor ca(126) xor ca(127) xor dq(120);
ca(121) <= ca( 57) xor ca( 71) xor ca( 72) xor ca( 73) xor ca( 75) xor ca( 76) xor ca( 77) xor ca( 79) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 92) xor ca( 96) xor ca( 99) xor ca(102) xor ca(103) xor ca(107) xor ca(109) xor ca(110) xor ca(113) xor ca(116) xor ca(117) xor ca(118) xor ca(119) xor ca(120) xor ca(121) xor ca(125) xor ca(127) xor dq(121);
ca(122) <= ca( 58) xor ca( 64) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 73) xor ca( 76) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 92) xor ca( 93) xor ca( 98) xor ca( 99) xor ca(100) xor ca(101) xor ca(103) xor ca(104) xor ca(107) xor ca(108) xor ca(109) xor ca(112) xor ca(115) xor ca(118) xor ca(119) xor ca(121) xor dq(122);
ca(123) <= ca( 59) xor ca( 64) xor ca( 65) xor ca( 68) xor ca( 71) xor ca( 72) xor ca( 78) xor ca( 84) xor ca( 86) xor ca( 87) xor ca( 89) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 97) xor ca( 98) xor ca(100) xor ca(102) xor ca(104) xor ca(105) xor ca(107) xor ca(108) xor ca(111) xor ca(112) xor ca(113) xor ca(114) xor ca(115) xor ca(116) xor ca(117) xor ca(119) xor ca(126) xor dq(123);
ca(124) <= ca( 60) xor ca( 64) xor ca( 65) xor ca( 66) xor ca( 68) xor ca( 70) xor ca( 73) xor ca( 74) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 86) xor ca( 88) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 97) xor ca(103) xor ca(105) xor ca(106) xor ca(107) xor ca(108) xor ca(110) xor ca(111) xor ca(113) xor ca(116) xor ca(118) xor ca(122) xor ca(126) xor ca(127) xor dq(124);
ca(125) <= ca( 61) xor ca( 65) xor ca( 66) xor ca( 67) xor ca( 69) xor ca( 71) xor ca( 74) xor ca( 75) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 87) xor ca( 89) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 98) xor ca(104) xor ca(106) xor ca(107) xor ca(108) xor ca(109) xor ca(111) xor ca(112) xor ca(114) xor ca(117) xor ca(119) xor ca(123) xor ca(127) xor dq(125);
ca(126) <= ca( 62) xor ca( 66) xor ca( 67) xor ca( 68) xor ca( 70) xor ca( 72) xor ca( 75) xor ca( 76) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 88) xor ca( 90) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 99) xor ca(105) xor ca(107) xor ca(108) xor ca(109) xor ca(110) xor ca(112) xor ca(113) xor ca(115) xor ca(118) xor ca(120) xor ca(124) xor dq(126);
ca(127) <= ca( 63) xor ca( 67) xor ca( 68) xor ca( 69) xor ca( 71) xor ca( 73) xor ca( 76) xor ca( 77) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 89) xor ca( 91) xor ca( 96) xor ca( 97) xor ca( 98) xor ca(100) xor ca(106) xor ca(108) xor ca(109) xor ca(110) xor ca(111) xor ca(113) xor ca(114) xor ca(116) xor ca(119) xor ca(121) xor ca(125) xor dq(127);
oa( 63) <= ca(127) xor dq( 0);
oa( 62) <= ca(126) xor dq( 1);
oa( 61) <= ca(125) xor dq( 2);
oa( 60) <= ca(124) xor dq( 3);
oa( 59) <= ca(123) xor ca(127) xor dq( 4);
oa( 58) <= ca(122) xor ca(126) xor ca(127) xor dq( 5);
oa( 57) <= ca(121) xor ca(125) xor ca(126) xor ca(127) xor dq( 6);
oa( 56) <= ca(120) xor ca(124) xor ca(125) xor ca(126) xor dq( 7);
oa( 55) <= ca(119) xor ca(123) xor ca(124) xor ca(125) xor ca(127) xor dq( 8);
oa( 54) <= ca(118) xor ca(122) xor ca(123) xor ca(124) xor ca(126) xor dq( 9);
oa( 53) <= ca(117) xor ca(121) xor ca(122) xor ca(123) xor ca(125) xor ca(127) xor dq( 10);
oa( 52) <= ca(116) xor ca(120) xor ca(121) xor ca(122) xor ca(124) xor ca(126) xor dq( 11);
oa( 51) <= ca(115) xor ca(119) xor ca(120) xor ca(121) xor ca(123) xor ca(125) xor dq( 12);
oa( 50) <= ca(114) xor ca(118) xor ca(119) xor ca(120) xor ca(122) xor ca(124) xor ca(127) xor dq( 13);
oa( 49) <= ca(113) xor ca(117) xor ca(118) xor ca(119) xor ca(121) xor ca(123) xor ca(126) xor ca(127) xor dq( 14);
oa( 48) <= ca(112) xor ca(116) xor ca(117) xor ca(118) xor ca(120) xor ca(122) xor ca(125) xor ca(126) xor dq( 15);
oa( 47) <= ca(111) xor ca(115) xor ca(116) xor ca(117) xor ca(119) xor ca(121) xor ca(124) xor ca(125) xor dq( 16);
oa( 46) <= ca(110) xor ca(114) xor ca(115) xor ca(116) xor ca(118) xor ca(120) xor ca(123) xor ca(124) xor ca(127) xor dq( 17);
oa( 45) <= ca(109) xor ca(113) xor ca(114) xor ca(115) xor ca(117) xor ca(119) xor ca(122) xor ca(123) xor ca(126) xor ca(127) xor dq( 18);
oa( 44) <= ca(108) xor ca(112) xor ca(113) xor ca(114) xor ca(116) xor ca(118) xor ca(121) xor ca(122) xor ca(125) xor ca(126) xor ca(127) xor dq( 19);
oa( 43) <= ca(107) xor ca(111) xor ca(112) xor ca(113) xor ca(115) xor ca(117) xor ca(120) xor ca(121) xor ca(124) xor ca(125) xor ca(126) xor dq( 20);
oa( 42) <= ca(106) xor ca(110) xor ca(111) xor ca(112) xor ca(114) xor ca(116) xor ca(119) xor ca(120) xor ca(123) xor ca(124) xor ca(125) xor ca(127) xor dq( 21);
oa( 41) <= ca(105) xor ca(109) xor ca(110) xor ca(111) xor ca(113) xor ca(115) xor ca(118) xor ca(119) xor ca(122) xor ca(123) xor ca(124) xor ca(126) xor ca(127) xor dq( 22);
oa( 40) <= ca(104) xor ca(108) xor ca(109) xor ca(110) xor ca(112) xor ca(114) xor ca(117) xor ca(118) xor ca(121) xor ca(122) xor ca(123) xor ca(125) xor ca(126) xor ca(127) xor dq( 23);
oa( 39) <= ca(103) xor ca(107) xor ca(108) xor ca(109) xor ca(111) xor ca(113) xor ca(116) xor ca(117) xor ca(120) xor ca(121) xor ca(122) xor ca(124) xor ca(125) xor ca(126) xor dq( 24);
oa( 38) <= ca(102) xor ca(106) xor ca(107) xor ca(108) xor ca(110) xor ca(112) xor ca(115) xor ca(116) xor ca(119) xor ca(120) xor ca(121) xor ca(123) xor ca(124) xor ca(125) xor dq( 25);
oa( 37) <= ca(101) xor ca(105) xor ca(106) xor ca(107) xor ca(109) xor ca(111) xor ca(114) xor ca(115) xor ca(118) xor ca(119) xor ca(120) xor ca(122) xor ca(123) xor ca(124) xor ca(127) xor dq( 26);
oa( 36) <= ca(100) xor ca(104) xor ca(105) xor ca(106) xor ca(108) xor ca(110) xor ca(113) xor ca(114) xor ca(117) xor ca(118) xor ca(119) xor ca(121) xor ca(122) xor ca(123) xor ca(126) xor dq( 27);
oa( 35) <= ca( 99) xor ca(103) xor ca(104) xor ca(105) xor ca(107) xor ca(109) xor ca(112) xor ca(113) xor ca(116) xor ca(117) xor ca(118) xor ca(120) xor ca(121) xor ca(122) xor ca(125) xor ca(127) xor dq( 28);
oa( 34) <= ca( 98) xor ca(102) xor ca(103) xor ca(104) xor ca(106) xor ca(108) xor ca(111) xor ca(112) xor ca(115) xor ca(116) xor ca(117) xor ca(119) xor ca(120) xor ca(121) xor ca(124) xor ca(126) xor dq( 29);
oa( 33) <= ca( 97) xor ca(101) xor ca(102) xor ca(103) xor ca(105) xor ca(107) xor ca(110) xor ca(111) xor ca(114) xor ca(115) xor ca(116) xor ca(118) xor ca(119) xor ca(120) xor ca(123) xor ca(125) xor dq( 30);
oa( 32) <= ca( 96) xor ca(100) xor ca(101) xor ca(102) xor ca(104) xor ca(106) xor ca(109) xor ca(110) xor ca(113) xor ca(114) xor ca(115) xor ca(117) xor ca(118) xor ca(119) xor ca(122) xor ca(124) xor dq( 31);
oa( 31) <= ca( 95) xor ca( 99) xor ca(100) xor ca(101) xor ca(103) xor ca(105) xor ca(108) xor ca(109) xor ca(112) xor ca(113) xor ca(114) xor ca(116) xor ca(117) xor ca(118) xor ca(121) xor ca(123) xor dq( 32);
oa( 30) <= ca( 94) xor ca( 98) xor ca( 99) xor ca(100) xor ca(102) xor ca(104) xor ca(107) xor ca(108) xor ca(111) xor ca(112) xor ca(113) xor ca(115) xor ca(116) xor ca(117) xor ca(120) xor ca(122) xor ca(127) xor dq( 33);
oa( 29) <= ca( 93) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(101) xor ca(103) xor ca(106) xor ca(107) xor ca(110) xor ca(111) xor ca(112) xor ca(114) xor ca(115) xor ca(116) xor ca(119) xor ca(121) xor ca(126) xor ca(127) xor dq( 34);
oa( 28) <= ca( 92) xor ca( 96) xor ca( 97) xor ca( 98) xor ca(100) xor ca(102) xor ca(105) xor ca(106) xor ca(109) xor ca(110) xor ca(111) xor ca(113) xor ca(114) xor ca(115) xor ca(118) xor ca(120) xor ca(125) xor ca(126) xor ca(127) xor dq( 35);
oa( 27) <= ca( 91) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 99) xor ca(101) xor ca(104) xor ca(105) xor ca(108) xor ca(109) xor ca(110) xor ca(112) xor ca(113) xor ca(114) xor ca(117) xor ca(119) xor ca(124) xor ca(125) xor ca(126) xor dq( 36);
oa( 26) <= ca( 90) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 98) xor ca(100) xor ca(103) xor ca(104) xor ca(107) xor ca(108) xor ca(109) xor ca(111) xor ca(112) xor ca(113) xor ca(116) xor ca(118) xor ca(123) xor ca(124) xor ca(125) xor ca(127) xor dq( 37);
oa( 25) <= ca( 89) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 97) xor ca( 99) xor ca(102) xor ca(103) xor ca(106) xor ca(107) xor ca(108) xor ca(110) xor ca(111) xor ca(112) xor ca(115) xor ca(117) xor ca(122) xor ca(123) xor ca(124) xor ca(126) xor dq( 38);
oa( 24) <= ca( 88) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 96) xor ca( 98) xor ca(101) xor ca(102) xor ca(105) xor ca(106) xor ca(107) xor ca(109) xor ca(110) xor ca(111) xor ca(114) xor ca(116) xor ca(121) xor ca(122) xor ca(123) xor ca(125) xor dq( 39);
oa( 23) <= ca( 87) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 95) xor ca( 97) xor ca(100) xor ca(101) xor ca(104) xor ca(105) xor ca(106) xor ca(108) xor ca(109) xor ca(110) xor ca(113) xor ca(115) xor ca(120) xor ca(121) xor ca(122) xor ca(124) xor dq( 40);
oa( 22) <= ca( 86) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 94) xor ca( 96) xor ca( 99) xor ca(100) xor ca(103) xor ca(104) xor ca(105) xor ca(107) xor ca(108) xor ca(109) xor ca(112) xor ca(114) xor ca(119) xor ca(120) xor ca(121) xor ca(123) xor dq( 41);
oa( 21) <= ca( 85) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 93) xor ca( 95) xor ca( 98) xor ca( 99) xor ca(102) xor ca(103) xor ca(104) xor ca(106) xor ca(107) xor ca(108) xor ca(111) xor ca(113) xor ca(118) xor ca(119) xor ca(120) xor ca(122) xor dq( 42);
oa( 20) <= ca( 84) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 92) xor ca( 94) xor ca( 97) xor ca( 98) xor ca(101) xor ca(102) xor ca(103) xor ca(105) xor ca(106) xor ca(107) xor ca(110) xor ca(112) xor ca(117) xor ca(118) xor ca(119) xor ca(121) xor ca(127) xor dq( 43);
oa( 19) <= ca( 83) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 91) xor ca( 93) xor ca( 96) xor ca( 97) xor ca(100) xor ca(101) xor ca(102) xor ca(104) xor ca(105) xor ca(106) xor ca(109) xor ca(111) xor ca(116) xor ca(117) xor ca(118) xor ca(120) xor ca(126) xor dq( 44);
oa( 18) <= ca( 82) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 90) xor ca( 92) xor ca( 95) xor ca( 96) xor ca( 99) xor ca(100) xor ca(101) xor ca(103) xor ca(104) xor ca(105) xor ca(108) xor ca(110) xor ca(115) xor ca(116) xor ca(117) xor ca(119) xor ca(125) xor ca(127) xor dq( 45);
oa( 17) <= ca( 81) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 89) xor ca( 91) xor ca( 94) xor ca( 95) xor ca( 98) xor ca( 99) xor ca(100) xor ca(102) xor ca(103) xor ca(104) xor ca(107) xor ca(109) xor ca(114) xor ca(115) xor ca(116) xor ca(118) xor ca(124) xor ca(126) xor ca(127) xor dq( 46);
oa( 16) <= ca( 80) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 88) xor ca( 90) xor ca( 93) xor ca( 94) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(101) xor ca(102) xor ca(103) xor ca(106) xor ca(108) xor ca(113) xor ca(114) xor ca(115) xor ca(117) xor ca(123) xor ca(125) xor ca(126) xor ca(127) xor dq( 47);
oa( 15) <= ca( 79) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 87) xor ca( 89) xor ca( 92) xor ca( 93) xor ca( 96) xor ca( 97) xor ca( 98) xor ca(100) xor ca(101) xor ca(102) xor ca(105) xor ca(107) xor ca(112) xor ca(113) xor ca(114) xor ca(116) xor ca(122) xor ca(124) xor ca(125) xor ca(126) xor ca(127) xor dq( 48);
oa( 14) <= ca( 78) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 86) xor ca( 88) xor ca( 91) xor ca( 92) xor ca( 95) xor ca( 96) xor ca( 97) xor ca( 99) xor ca(100) xor ca(101) xor ca(104) xor ca(106) xor ca(111) xor ca(112) xor ca(113) xor ca(115) xor ca(121) xor ca(123) xor ca(124) xor ca(125) xor ca(126) xor dq( 49);
oa( 13) <= ca( 77) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 85) xor ca( 87) xor ca( 90) xor ca( 91) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 98) xor ca( 99) xor ca(100) xor ca(103) xor ca(105) xor ca(110) xor ca(111) xor ca(112) xor ca(114) xor ca(120) xor ca(122) xor ca(123) xor ca(124) xor ca(125) xor ca(127) xor dq( 50);
oa( 12) <= ca( 76) xor ca( 80) xor ca( 81) xor ca( 82) xor ca( 84) xor ca( 86) xor ca( 89) xor ca( 90) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(102) xor ca(104) xor ca(109) xor ca(110) xor ca(111) xor ca(113) xor ca(119) xor ca(121) xor ca(122) xor ca(123) xor ca(124) xor ca(126) xor ca(127) xor dq( 51);
oa( 11) <= ca( 75) xor ca( 79) xor ca( 80) xor ca( 81) xor ca( 83) xor ca( 85) xor ca( 88) xor ca( 89) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 96) xor ca( 97) xor ca( 98) xor ca(101) xor ca(103) xor ca(108) xor ca(109) xor ca(110) xor ca(112) xor ca(118) xor ca(120) xor ca(121) xor ca(122) xor ca(123) xor ca(125) xor ca(126) xor dq( 52);
oa( 10) <= ca( 74) xor ca( 78) xor ca( 79) xor ca( 80) xor ca( 82) xor ca( 84) xor ca( 87) xor ca( 88) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 95) xor ca( 96) xor ca( 97) xor ca(100) xor ca(102) xor ca(107) xor ca(108) xor ca(109) xor ca(111) xor ca(117) xor ca(119) xor ca(120) xor ca(121) xor ca(122) xor ca(124) xor ca(125) xor ca(127) xor dq( 53);
oa( 9) <= ca( 73) xor ca( 77) xor ca( 78) xor ca( 79) xor ca( 81) xor ca( 83) xor ca( 86) xor ca( 87) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 94) xor ca( 95) xor ca( 96) xor ca( 99) xor ca(101) xor ca(106) xor ca(107) xor ca(108) xor ca(110) xor ca(116) xor ca(118) xor ca(119) xor ca(120) xor ca(121) xor ca(123) xor ca(124) xor ca(126) xor dq( 54);
oa( 8) <= ca( 72) xor ca( 76) xor ca( 77) xor ca( 78) xor ca( 80) xor ca( 82) xor ca( 85) xor ca( 86) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 93) xor ca( 94) xor ca( 95) xor ca( 98) xor ca(100) xor ca(105) xor ca(106) xor ca(107) xor ca(109) xor ca(115) xor ca(117) xor ca(118) xor ca(119) xor ca(120) xor ca(122) xor ca(123) xor ca(125) xor dq( 55);
oa( 7) <= ca( 71) xor ca( 75) xor ca( 76) xor ca( 77) xor ca( 79) xor ca( 81) xor ca( 84) xor ca( 85) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 92) xor ca( 93) xor ca( 94) xor ca( 97) xor ca( 99) xor ca(104) xor ca(105) xor ca(106) xor ca(108) xor ca(114) xor ca(116) xor ca(117) xor ca(118) xor ca(119) xor ca(121) xor ca(122) xor ca(124) xor ca(127) xor dq( 56);
oa( 6) <= ca( 70) xor ca( 74) xor ca( 75) xor ca( 76) xor ca( 78) xor ca( 80) xor ca( 83) xor ca( 84) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 91) xor ca( 92) xor ca( 93) xor ca( 96) xor ca( 98) xor ca(103) xor ca(104) xor ca(105) xor ca(107) xor ca(113) xor ca(115) xor ca(116) xor ca(117) xor ca(118) xor ca(120) xor ca(121) xor ca(123) xor ca(126) xor dq( 57);
oa( 5) <= ca( 69) xor ca( 73) xor ca( 74) xor ca( 75) xor ca( 77) xor ca( 79) xor ca( 82) xor ca( 83) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 90) xor ca( 91) xor ca( 92) xor ca( 95) xor ca( 97) xor ca(102) xor ca(103) xor ca(104) xor ca(106) xor ca(112) xor ca(114) xor ca(115) xor ca(116) xor ca(117) xor ca(119) xor ca(120) xor ca(122) xor ca(125) xor ca(127) xor dq( 58);
oa( 4) <= ca( 68) xor ca( 72) xor ca( 73) xor ca( 74) xor ca( 76) xor ca( 78) xor ca( 81) xor ca( 82) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 89) xor ca( 90) xor ca( 91) xor ca( 94) xor ca( 96) xor ca(101) xor ca(102) xor ca(103) xor ca(105) xor ca(111) xor ca(113) xor ca(114) xor ca(115) xor ca(116) xor ca(118) xor ca(119) xor ca(121) xor ca(124) xor ca(126) xor dq( 59);
oa( 3) <= ca( 67) xor ca( 71) xor ca( 72) xor ca( 73) xor ca( 75) xor ca( 77) xor ca( 80) xor ca( 81) xor ca( 84) xor ca( 85) xor ca( 86) xor ca( 88) xor ca( 89) xor ca( 90) xor ca( 93) xor ca( 95) xor ca(100) xor ca(101) xor ca(102) xor ca(104) xor ca(110) xor ca(112) xor ca(113) xor ca(114) xor ca(115) xor ca(117) xor ca(118) xor ca(120) xor ca(123) xor ca(125) xor dq( 60);
oa( 2) <= ca( 66) xor ca( 70) xor ca( 71) xor ca( 72) xor ca( 74) xor ca( 76) xor ca( 79) xor ca( 80) xor ca( 83) xor ca( 84) xor ca( 85) xor ca( 87) xor ca( 88) xor ca( 89) xor ca( 92) xor ca( 94) xor ca( 99) xor ca(100) xor ca(101) xor ca(103) xor ca(109) xor ca(111) xor ca(112) xor ca(113) xor ca(114) xor ca(116) xor ca(117) xor ca(119) xor ca(122) xor ca(124) xor dq( 61);
oa( 1) <= ca( 65) xor ca( 69) xor ca( 70) xor ca( 71) xor ca( 73) xor ca( 75) xor ca( 78) xor ca( 79) xor ca( 82) xor ca( 83) xor ca( 84) xor ca( 86) xor ca( 87) xor ca( 88) xor ca( 91) xor ca( 93) xor ca( 98) xor ca( 99) xor ca(100) xor ca(102) xor ca(108) xor ca(110) xor ca(111) xor ca(112) xor ca(113) xor ca(115) xor ca(116) xor ca(118) xor ca(121) xor ca(123) xor ca(127) xor dq( 62);
oa( 0) <= ca( 64) xor ca( 68) xor ca( 69) xor ca( 70) xor ca( 72) xor ca( 74) xor ca( 77) xor ca( 78) xor ca( 81) xor ca( 82) xor ca( 83) xor ca( 85) xor ca( 86) xor ca( 87) xor ca( 90) xor ca( 92) xor ca( 97) xor ca( 98) xor ca( 99) xor ca(101) xor ca(107) xor ca(109) xor ca(110) xor ca(111) xor ca(112) xor ca(114) xor ca(115) xor ca(117) xor ca(120) xor ca(122) xor ca(126) xor dq( 63);
end if;
end if;
end if;
end process;
c <= ca;
o <= oa;
end bch_128x64;
|
library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
clk : in std_logic;
o : out std_logic
);
end;
architecture a of ent is
function inv(s : std_logic) return std_logic is
begin
return not s;
end inv;
signal test : std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
test <= inv(test);
end if;
end process;
o <= test;
end;
|
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect key_block
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|
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-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ieee754_fp_to_uint:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_ieee754_fp_to_uint_0_1 IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END affine_block_ieee754_fp_to_uint_0_1;
ARCHITECTURE affine_block_ieee754_fp_to_uint_0_1_arch OF affine_block_ieee754_fp_to_uint_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_ieee754_fp_to_uint_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT ieee754_fp_to_uint IS
GENERIC (
WIDTH : INTEGER
);
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT ieee754_fp_to_uint;
BEGIN
U0 : ieee754_fp_to_uint
GENERIC MAP (
WIDTH => 10
)
PORT MAP (
x => x,
y => y
);
END affine_block_ieee754_fp_to_uint_0_1_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ieee754_fp_to_uint:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_ieee754_fp_to_uint_0_1 IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END affine_block_ieee754_fp_to_uint_0_1;
ARCHITECTURE affine_block_ieee754_fp_to_uint_0_1_arch OF affine_block_ieee754_fp_to_uint_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_ieee754_fp_to_uint_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT ieee754_fp_to_uint IS
GENERIC (
WIDTH : INTEGER
);
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT ieee754_fp_to_uint;
BEGIN
U0 : ieee754_fp_to_uint
GENERIC MAP (
WIDTH => 10
)
PORT MAP (
x => x,
y => y
);
END affine_block_ieee754_fp_to_uint_0_1_arch;
|
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare3.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare3 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
aeb : OUT STD_LOGIC
);
END lpm_compare3;
ARCHITECTURE SYN OF lpm_compare3 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (5 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
aeb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (5 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(5 DOWNTO 0) <= "110010";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
aeb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 6
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
aeb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "1"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "50"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "6"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "6"
-- Retrieval info: USED_PORT: aeb 0 0 0 0 OUTPUT NODEFVAL "aeb"
-- Retrieval info: USED_PORT: dataa 0 0 6 0 INPUT NODEFVAL "dataa[5..0]"
-- Retrieval info: CONNECT: @dataa 0 0 6 0 dataa 0 0 6 0
-- Retrieval info: CONNECT: @datab 0 0 6 0 50 0 0 6 0
-- Retrieval info: CONNECT: aeb 0 0 0 0 @aeb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare3.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare3.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare3.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare3.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare3_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:27:52 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_vga_sync_ref_0_0 -prefix
-- system_vga_sync_ref_0_0_ system_vga_sync_ref_1_0_stub.vhdl
-- Design : system_vga_sync_ref_1_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_vga_sync_ref_0_0 is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
start : out STD_LOGIC;
active : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end system_vga_sync_ref_0_0;
architecture stub of system_vga_sync_ref_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rst,hsync,vsync,start,active,xaddr[9:0],yaddr[9:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "vga_sync_ref,Vivado 2016.4";
begin
end;
|
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use work.vga_comp.all;
entity tb is
end;
architecture rtl of tb is
component vga is
port(clk : in std_logic;
reset : in std_logic;
output : out vga_out_t);
end component;
signal clk : std_logic;
signal reset : std_logic;
signal output : vga_out_t;
begin
vga_0 : vga
port map (clk, reset, output);
clk_gen:
process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;
reset_gen:
process
begin
reset <= '1';
wait for 10 ns;
reset <= '0';
wait;
end process;
end rtl;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rd_fifo_256to64_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity rd_fifo_256to64_exdes is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(12-1 DOWNTO 0);
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end rd_fifo_256to64_exdes;
architecture xilinx of rd_fifo_256to64_exdes is
signal wr_clk_i : std_logic;
signal rd_clk_i : std_logic;
component rd_fifo_256to64 is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(12-1 DOWNTO 0);
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
exdes_inst : rd_fifo_256to64
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PSR_MOD is
Port (
alurs : in STD_LOGIC_VECTOR (31 downto 0);
ope1 : in STD_LOGIC;
ope2 : in STD_LOGIC;
aluop : in STD_LOGIC_VECTOR (5 downto 0);
nzvc : out std_logic_vector(3 downto 0)
);
end PSR_MOD;
architecture Behavioral of PSR_MOD is
begin
process(alurs,ope1,ope2,aluop)
begin
--ADDcc ADDXcc
if (aluop = "100001" or aluop = "100011") then
nzvc(3) <= alurs(31);
if(alurs = X"00000000")then
nzvc(2) <= '1';
else
nzvc(2) <= '0';
end if;
nzvc(1) <= (ope1 and ope2 and (not alurs(31))) or ((ope1) and (not ope2) and alurs(31));
nzvc(0) <= (ope1 and ope2) or ((not alurs(31)) and (ope1 or ope2));
--SUBcc SUBXcc
elsif (aluop = "100101" or aluop = "100111") then
nzvc(3) <= alurs(31);
if(alurs = X"00000000")then
nzvc(2) <= '1';
else
nzvc(2) <= '0';
end if;
nzvc(1) <= ((ope1 and (not ope2) and (not alurs(31))) or ((not ope1) and ope2 and alurs(31)));
nzvc(0) <= ((not ope1) and ope2) or (alurs(31) and ((not ope1) or ope2));
--ANDcc ANDNcc ORcc ORNcc XORcc XNORcc
elsif(aluop = "101001" or aluop = "101011" or aluop = "101101" or aluop = "101111" or aluop = "110001" or aluop = "110011")then
nzvc(3) <= alurs(31);
if(alurs = X"00000000") then
nzvc(2) <= '1';
else
nzvc(2) <= '0';
end if;
nzvc(1) <= '0';
nzvc(0) <= '0';
-- --RESTO DE OPERACIONES
-- else
-- nzvc <= "0000";
end if;
end process;
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----------------------------------------------------------------------------
-- Entity: ahbctrl
-- File: ahbctrl.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Modified: Edvin Catovic, Gaisler Research
-- Description: AMBA arbiter, decoder and multiplexer with plug&play support
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.config_types.all;
use grlib.config.all;
-- pragma translate_off
use grlib.devices.all;
use std.textio.all;
-- pragma translate_on
entity ahbctrl is
generic (
defmast : integer := 0; -- default master
split : integer := 0; -- split support
rrobin : integer := 0; -- round-robin arbitration
timeout : integer range 0 to 255 := 0; -- HREADY timeout
ioaddr : ahb_addr_type := 16#fff#; -- I/O area MSB address
iomask : ahb_addr_type := 16#fff#; -- I/O area address mask
cfgaddr : ahb_addr_type := 16#ff0#; -- config area MSB address
cfgmask : ahb_addr_type := 16#ff0#; -- config area address mask
nahbm : integer range 1 to NAHBMST := NAHBMST; -- number of masters
nahbs : integer range 1 to NAHBSLV := NAHBSLV; -- number of slaves
ioen : integer range 0 to 15 := 1; -- enable I/O area
disirq : integer range 0 to 1 := 0; -- disable interrupt routing
fixbrst : integer range 0 to 1 := 0; -- support fix-length bursts
debug : integer range 0 to 2 := 2; -- report cores to console
fpnpen : integer range 0 to 1 := 0; -- full PnP configuration decoding
icheck : integer range 0 to 1 := 1;
devid : integer := 0; -- unique device ID
enbusmon : integer range 0 to 1 := 0; --enable bus monitor
assertwarn : integer range 0 to 1 := 0; --enable assertions for warnings
asserterr : integer range 0 to 1 := 0; --enable assertions for errors
hmstdisable : integer := 0; --disable master checks
hslvdisable : integer := 0; --disable slave checks
arbdisable : integer := 0; --disable arbiter checks
mprio : integer := 0; --master with highest priority
mcheck : integer range 0 to 2 := 1; --check memory map for intersects
ccheck : integer range 0 to 1 := 1; --perform sanity checks on pnp config
acdm : integer := 0; --AMBA compliant data muxing (for hsize > word)
index : integer := 0; --Index for trace print-out
ahbtrace : integer := 0; --AHB trace enable
hwdebug : integer := 0; --Hardware debug
fourgslv : integer := 0 --1=Single slave with single 4 GB bar
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
msti : out ahb_mst_in_type;
msto : in ahb_mst_out_vector;
slvi : out ahb_slv_in_type;
slvo : in ahb_slv_out_vector;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
scanen : in std_ulogic := '0';
testoen : in std_ulogic := '1';
testsig : in std_logic_vector(1+GRLIB_CONFIG_ARRAY(grlib_techmap_testin_extra) downto 0) := (others => '0')
);
end;
architecture rtl of ahbctrl is
constant nahbmx : integer := 2**log2(nahbm);
type nmstarr is array (1 to 3) of integer range 0 to nahbmx-1;
type nvalarr is array (1 to 3) of boolean;
type reg_type is record
hmaster : integer range 0 to nahbmx -1;
hmasterd : integer range 0 to nahbmx -1;
hslave : integer range 0 to nahbs-1;
hmasterlock : std_ulogic;
hmasterlockd : std_ulogic;
hready : std_ulogic;
defslv : std_ulogic;
htrans : std_logic_vector(1 downto 0);
hsize : std_logic_vector(2 downto 0);
haddr : std_logic_vector(15 downto 2);
cfgsel : std_ulogic;
cfga11 : std_ulogic;
hrdatam : std_logic_vector(31 downto 0);
hrdatas : std_logic_vector(31 downto 0);
beat : std_logic_vector(3 downto 0);
defmst : std_ulogic;
ldefmst : std_ulogic;
lsplmst : integer range 0 to nahbmx-1;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES_r : reg_type := (
hmaster => 0, hmasterd => 0, hslave => 0, hmasterlock => '0',
hmasterlockd => '0', hready => '1', defslv => '0',
htrans => HTRANS_IDLE, hsize => (others => '0'),
haddr => (others => '0'), cfgsel => '0', cfga11 => '0',
hrdatam => (others => '0'), hrdatas => (others => '0'),
beat => (others => '0'), defmst => '0', ldefmst => '0',
lsplmst => 0);
constant RES_split : std_logic_vector(0 to nahbmx-1) := (others => '0');
constant primst : std_logic_vector(NAHBMST downto 0) := conv_std_logic_vector(mprio, NAHBMST+1);
type l0_type is array (0 to 15) of std_logic_vector(2 downto 0);
type l1_type is array (0 to 7) of std_logic_vector(3 downto 0);
type l2_type is array (0 to 3) of std_logic_vector(4 downto 0);
type l3_type is array (0 to 1) of std_logic_vector(5 downto 0);
type tztab_type is array (0 to 15) of std_logic_vector(2 downto 0);
--returns the index number of the highest priority request
--signal in the two lsb bits when indexed with a 4-bit
--request vector with the highest priority signal on the
--lsb. the returned msb bit indicates if a request was
--active ('1' = no request active corresponds to "0000")
constant tztab : tztab_type := ("100", "000", "001", "000",
"010", "000", "001", "000",
"011", "000", "001", "000",
"010", "000", "001", "000");
--calculate the number of the highest priority request signal(up to 64
--requests are supported) in vect_in using a divide and conquer
--algorithm. The lower the index in the vector the higher the priority
--of the signal. First 4-bit slices are indexed in tztab and the msb
--indicates whether there is an active request or not. Then the resulting
--3 bit vectors are compared in pairs (the one corresponding to (3:0) with
--(7:4), (11:8) with (15:12) and so on). If the least significant of the two
--contains an active signal a '0' is added to the msb side (the vector
--becomes one bit wider at each level) to the next level to indicate that
--there are active signals in the lower nibble of the two. Otherwise
--the msb is removed from the vector corresponding to the higher nibble
--and "10" is added if it does not contain active requests and "01" if
--does contain active signals. Thus the msb still indicates if the new
--slice contains active signals and a '1' is added if it is the higher
--part. This results in a 6-bit vector containing the index number
--of the highest priority master in 5:0 if bit 6 is '0' otherwise
--no master requested the bus.
function tz(vect_in : std_logic_vector) return std_logic_vector is
variable vect : std_logic_vector(63 downto 0);
variable l0 : l0_type;
variable l1 : l1_type;
variable l2 : l2_type;
variable l3 : l3_type;
variable l4 : std_logic_vector(6 downto 0);
variable bci_lsb, bci_msb : std_logic_vector(3 downto 0);
variable bco_lsb, bco_msb : std_logic_vector(2 downto 0);
variable sel : std_logic;
begin
vect := (others => '1');
vect(vect_in'length-1 downto 0) := vect_in;
-- level 0
for i in 0 to 7 loop
bci_lsb := vect(8*i+3 downto 8*i);
bci_msb := vect(8*i+7 downto 8*i+4);
--lookup the highest priority request in each nibble
bco_lsb := tztab(conv_integer(bci_lsb));
bco_msb := tztab(conv_integer(bci_msb));
--select which of two nibbles contain the highest priority ACTIVE
--signal, and forward the corresponding vector to the next level
sel := bco_lsb(2);
if sel = '0' then l1(i) := '0' & bco_lsb;
else l1(i) := bco_msb(2) & not bco_msb(2) & bco_msb(1 downto 0); end if;
end loop;
-- level 1
for i in 0 to 3 loop
sel := l1(2*i)(3);
--select which of two 8-bit vectors contain the
--highest priority ACTIVE signal. the msb set at the previous level
--for each 8-bit slice determines this
if sel = '0' then l2(i) := '0' & l1(2*i);
else
l2(i) := l1(2*i+1)(3) & not l1(2*i+1)(3) & l1(2*i+1)(2 downto 0);
end if;
end loop;
-- level 2
for i in 0 to 1 loop
--16-bit vectors, the msb set at the previous level for each 16-bit
--slice determines the higher priority slice
sel := l2(2*i)(4);
if sel = '0' then l3(i) := '0' & l2(2*i);
else
l3(i) := l2(2*i+1)(4) & not l2(2*i+1)(4) & l2(2*i+1)(3 downto 0);
end if;
end loop;
--level 3
--32-bit vectors, the msb set at the previous level for each 32-bit
--slice determines the higher priority slice
if l3(0)(5) = '0' then l4 := '0' & l3(0);
else l4 := l3(1)(5) & not l3(1)(5) & l3(1)(4 downto 0); end if;
return(l4);
end;
--invert the bit order of the hbusreq signals located in vect_in
--since the highest hbusreq has the highest priority but the
--algorithm in tz has the highest priority on lsb
function lz(vect_in : std_logic_vector) return std_logic_vector is
variable vect : std_logic_vector(vect_in'length-1 downto 0);
variable vect2 : std_logic_vector(vect_in'length-1 downto 0);
begin
vect := vect_in;
for i in vect'right to vect'left loop
vect2(i) := vect(vect'left-i);
end loop;
return(tz(vect2));
end;
-- Find next master:
-- * 2 arbitration policies: fixed priority or round-robin
-- * Fixed priority: priority is fixed, highest index has highest priority
-- * Round-robin: arbiter maintains circular queue of masters
-- * (master 0, master 1, ..., master (nahbmx-1)). First requesting master
-- * in the queue is granted access to the bus and moved to the end of the queue.
-- * splitted masters are not granted
-- * bus is re-arbited when current owner does not request the bus,
-- or when it performs non-burst accesses
-- * fix length burst transfers will not be interrupted
-- * incremental bursts should assert hbusreq until last access
procedure selmast(r : in reg_type;
msto : in ahb_mst_out_vector;
rsplit : in std_logic_vector(0 to nahbmx-1);
mast : out integer range 0 to nahbmx-1;
defmst : out std_ulogic) is
variable nmst : nmstarr;
variable nvalid : nvalarr;
variable rrvec : std_logic_vector(nahbmx*2-1 downto 0);
variable zcnt : std_logic_vector(log2(nahbmx)+1 downto 0);
variable hpvec : std_logic_vector(nahbmx-1 downto 0);
variable zcnt2 : std_logic_vector(log2(nahbmx) downto 0);
begin
nvalid(1 to 3) := (others => false); nmst(1 to 3) := (others => 0);
mast := r.hmaster;
defmst := '0';
if nahbm = 1 then
mast := 0;
elsif rrobin = 0 then
hpvec := (others => '0');
for i in 0 to nahbmx-1 loop
--masters which have received split are not granted
if ((rsplit(i) = '0') or (split = 0)) then
hpvec(i) := msto(i).hbusreq;
end if;
end loop;
--check if any bus requests are active (nvalid(2) set to true)
--and determine the index (zcnt2) of the highest priority master
zcnt2 := lz(hpvec)(log2(nahbmx) downto 0);
if zcnt2(log2(nahbmx)) = '0' then nvalid(2) := true; end if;
nmst(2) := conv_integer(not (zcnt2(log2(nahbmx)-1 downto 0)));
--find the default master number
for i in 0 to nahbmx-1 loop
if not ((nmst(3) = defmast) and nvalid(3)) then
nmst(3) := i; nvalid(3) := true;
end if;
end loop;
else
rrvec := (others => '0');
--mask requests up to and including current master. Concatenate
--an unmasked request vector above the masked vector. Otherwise
--the rules are the same as for fixed priority
for i in 0 to nahbmx-1 loop
if ((rsplit(i) = '0') or (split = 0)) then
if (i <= r.hmaster) then rrvec(i) := '0';
else rrvec(i) := msto(i).hbusreq; end if;
rrvec(nahbmx+i) := msto(i).hbusreq;
end if;
end loop;
--find the next master uzing tz which gives priority to lower
--indexes
zcnt := tz(rrvec)(log2(nahbmx)+1 downto 0);
--was there a master requesting the bus?
if zcnt(log2(nahbmx)+1) = '0' then nvalid(2) := true; end if;
nmst(2) := conv_integer(zcnt(log2(nahbmx)-1 downto 0));
--if no other master is requesting the bus select the current one
nmst(3) := r.hmaster; nvalid(3) := true;
--check if any masters configured with higher priority are requesting
--the bus
if mprio /= 0 then
for i in 0 to nahbm-1 loop
if (((rsplit(i) = '0') or (split = 0)) and (primst(i) = '1')) then
if msto(i).hbusreq = '1' then nmst(1) := i; nvalid(1) := true; end if;
end if;
end loop;
end if;
end if;
--select the next master. If for round robin a high priority master
--(mprio) requested the bus if nvalid(1) is true. Otherwise
--if nvalid(2) is true at least one master was requesting the bus
--and the one with highest priority was selected. If none of these
--were true then the default master is selected (nvalid(3) true)
for i in 1 to 3 loop
if nvalid(i) then mast := nmst(i); exit; end if;
end loop;
--if no master was requesting the bus and split is enabled
--then select builtin dummy master which only does
--idle transfers
if (not (nvalid(1) or nvalid(2))) and (split /= 0) then
defmst := orv(rsplit);
end if;
end;
constant MIMAX : integer := log2x(nahbmx) - 1;
constant SIMAX : integer := log2x(nahbs) - 1;
constant IOAREA : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(ioaddr, 12);
constant IOMSK : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(iomask, 12);
constant CFGAREA : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(cfgaddr, 12);
constant CFGMSK : std_logic_vector(11 downto 0) :=
conv_std_logic_vector(cfgmask, 12);
constant FULLPNP : boolean := (fpnpen /= 0);
signal r, rin : reg_type;
signal rsplit, rsplitin : std_logic_vector(0 to nahbmx-1);
-- pragma translate_off
signal lmsti : ahb_mst_in_type;
signal lslvi : ahb_slv_in_type;
-- pragma translate_on
begin
comb : process(rst, msto, slvo, r, rsplit, testen, testrst, scanen, testoen, testsig)
variable v : reg_type;
variable nhmaster: integer range 0 to nahbmx -1;
variable hgrant : std_logic_vector(0 to NAHBMST-1); -- bus grant
variable hsel : std_logic_vector(0 to 31); -- slave select
variable hmbsel : std_logic_vector(0 to NAHBAMR-1);
variable nslave : natural range 0 to 31;
variable vsplit : std_logic_vector(0 to nahbmx-1);
variable bnslave : std_logic_vector(3 downto 0);
variable area : std_logic_vector(1 downto 0);
variable hready : std_ulogic;
variable defslv : std_ulogic;
variable cfgsel : std_ulogic;
variable hresp : std_logic_vector(1 downto 0);
variable hrdata : std_logic_vector(AHBDW-1 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable arb : std_ulogic;
variable hconfndx : integer range 0 to 7;
variable vslvi : ahb_slv_in_type;
variable defmst : std_ulogic;
variable tmpv : std_logic_vector(0 to nahbmx-1);
begin
v := r; hgrant := (others => '0'); defmst := '0';
haddr := msto(r.hmaster).haddr;
nhmaster := r.hmaster;
--determine if bus should be rearbitrated. This is done if the current
--master is not performing a locked transfer and if not in the middle
--of burst
arb := '0';
if (r.hmasterlock or r.ldefmst) = '0' then
case msto(r.hmaster).htrans is
when HTRANS_IDLE => arb := '1';
when HTRANS_NONSEQ =>
case msto(r.hmaster).hburst is
when HBURST_SINGLE => arb := '1';
when HBURST_INCR => arb := not msto(r.hmaster).hbusreq;
when others =>
end case;
when HTRANS_SEQ =>
case msto(r.hmaster).hburst is
when HBURST_WRAP4 | HBURST_INCR4 => if (fixbrst = 1) and (r.beat(1 downto 0) = "11") then arb := '1'; end if;
when HBURST_WRAP8 | HBURST_INCR8 => if (fixbrst = 1) and (r.beat(2 downto 0) = "111") then arb := '1'; end if;
when HBURST_WRAP16 | HBURST_INCR16 => if (fixbrst = 1) and (r.beat(3 downto 0) = "1111") then arb := '1'; end if;
when HBURST_INCR => arb := not msto(r.hmaster).hbusreq;
when others =>
end case;
when others => arb := '0';
end case;
end if;
if (split /= 0) then
for i in 0 to nahbmx-1 loop
tmpv(i) := (msto(i).htrans(1) or (msto(i).hbusreq)) and not rsplit(i) and not r.ldefmst;
end loop;
if (r.defmst and orv(tmpv)) = '1' then arb := '1'; end if;
end if;
--rearbitrate bus with selmast. If not arbitrated one must
--ensure that the dummy master is selected for locked splits.
if (arb = '1') then
selmast(r, msto, rsplit, nhmaster, defmst);
elsif (split /= 0) then
defmst := r.defmst;
end if;
-- slave decoding
hsel := (others => '0'); hmbsel := (others => '0');
if fourgslv = 0 then
for i in 0 to nahbs-1 loop
for j in NAHBIR to NAHBCFG-1 loop
area := slvo(i).hconfig(j)(1 downto 0);
case area is
when "10" =>
if ((ioen = 0) or ((IOAREA and IOMSK) /= (haddr(31 downto 20) and IOMSK))) and
((slvo(i).hconfig(j)(31 downto 20) and slvo(i).hconfig(j)(15 downto 4)) =
(haddr(31 downto 20) and slvo(i).hconfig(j)(15 downto 4))) and
(slvo(i).hconfig(j)(15 downto 4) /= "000000000000")
then hsel(i) := '1'; hmbsel(j-NAHBIR) := '1'; end if;
when "11" =>
if ((ioen /= 0) and ((IOAREA and IOMSK) = (haddr(31 downto 20) and IOMSK))) and
((slvo(i).hconfig(j)(31 downto 20) and slvo(i).hconfig(j)(15 downto 4)) =
(haddr(19 downto 8) and slvo(i).hconfig(j)(15 downto 4))) and
(slvo(i).hconfig(j)(15 downto 4) /= "000000000000")
then hsel(i) := '1'; hmbsel(j-NAHBIR) := '1'; end if;
when others =>
end case;
end loop;
end loop;
else
-- There is only one slave on the bus. The slave has only one bar, which
-- maps 4 GB address space.
hsel(0) := '1'; hmbsel(0) := '1';
end if;
if r.defmst = '1' then hsel := (others => '0'); end if;
bnslave(0) := hsel(1) or hsel(3) or hsel(5) or hsel(7) or
hsel(9) or hsel(11) or hsel(13) or hsel(15);
bnslave(1) := hsel(2) or hsel(3) or hsel(6) or hsel(7) or
hsel(10) or hsel(11) or hsel(14) or hsel(15);
bnslave(2) := hsel(4) or hsel(5) or hsel(6) or hsel(7) or
hsel(12) or hsel(13) or hsel(14) or hsel(15);
bnslave(3) := hsel(8) or hsel(9) or hsel(10) or hsel(11) or
hsel(12) or hsel(13) or hsel(14) or hsel(15);
nslave := conv_integer(bnslave(SIMAX downto 0));
if ((((IOAREA and IOMSK) = (haddr(31 downto 20) and IOMSK)) and (ioen /= 0))
or ((IOAREA = haddr(31 downto 20)) and (ioen = 0))) and
((CFGAREA and CFGMSK) = (haddr(19 downto 8) and CFGMSK))
and (cfgmask /= 0)
then cfgsel := '1'; hsel := (others => '0');
else cfgsel := '0'; end if;
if (nslave = 0) and (hsel(0) = '0') and (cfgsel = '0') then defslv := '1';
else defslv := '0'; end if;
if r.defmst = '1' then
cfgsel := '0'; defslv := '1';
end if;
-- error response on undecoded area
v.hready := '0';
hready := slvo(r.hslave).hready; hresp := slvo(r.hslave).hresp;
if r.defslv = '1' then
-- default slave
if (r.htrans = HTRANS_IDLE) or (r.htrans = HTRANS_BUSY) then
hresp := HRESP_OKAY; hready := '1';
else
-- return two-cycle error in case of unimplemented slave access
hresp := HRESP_ERROR; hready := r.hready; v.hready := not r.hready;
end if;
end if;
if acdm = 0 then
hrdata := slvo(r.hslave).hrdata;
else
hrdata := ahbselectdata(slvo(r.hslave).hrdata, r.haddr(4 downto 2), r.hsize);
end if;
if cfgmask /= 0 then
-- plug&play information for masters
if FULLPNP then hconfndx := conv_integer(r.haddr(4 downto 2)); else hconfndx := 0; end if;
if (r.haddr(10 downto MIMAX+6) = zero32(10 downto MIMAX+6)) and (FULLPNP or (r.haddr(4 downto 2) = "000"))
then v.hrdatam := msto(conv_integer(r.haddr(MIMAX+5 downto 5))).hconfig(hconfndx);
else v.hrdatam := (others => '0'); end if;
-- plug&play information for slaves
if (r.haddr(10 downto SIMAX+6) = zero32(10 downto SIMAX+6)) and
(FULLPNP or (r.haddr(4 downto 2) = "000") or (r.haddr(4) = '1'))
then v.hrdatas := slvo(conv_integer(r.haddr(SIMAX+5 downto 5))).hconfig(conv_integer(r.haddr(4 downto 2)));
else v.hrdatas := (others => '0'); end if;
-- device ID, library build and potentially debug information
if r.haddr(10 downto 4) = "1111111" then
if hwdebug = 0 or r.haddr(3 downto 2) = "00" then
v.hrdatas(15 downto 0) := conv_std_logic_vector(LIBVHDL_BUILD, 16);
v.hrdatas(31 downto 16) := conv_std_logic_vector(devid, 16);
elsif r.haddr(3 downto 2) = "01" then
for i in 0 to nahbmx-1 loop v.hrdatas(i) := msto(i).hbusreq; end loop;
else
for i in 0 to nahbmx-1 loop v.hrdatas(i) := rsplit(i); end loop;
end if;
end if;
if r.cfgsel = '1' then
hrdata := (others => '0');
-- default slave
if (r.htrans = HTRANS_IDLE) or (r.htrans = HTRANS_BUSY) then
hresp := HRESP_OKAY; hready := '1';
else
-- return two-cycle read/write respons
hresp := HRESP_OKAY; hready := r.hready; v.hready := not r.hready;
end if;
if r.cfga11 = '0' then hrdata := ahbdrivedata(r.hrdatam);
else hrdata := ahbdrivedata(r.hrdatas); end if;
end if;
end if;
--degrant all masters when split occurs for locked access
if (r.hmasterlockd = '1') then
if (hresp = HRESP_RETRY) or ((split /= 0) and (hresp = HRESP_SPLIT)) then
nhmaster := r.hmaster;
end if;
if split /= 0 then
if hresp = HRESP_SPLIT then
v.ldefmst := '1'; defmst := '1';
v.lsplmst := nhmaster;
end if;
end if;
end if;
if split /= 0 and r.ldefmst = '1' then
if rsplit(r.lsplmst) = '0' then
v.ldefmst := '0'; defmst := '0';
end if;
end if;
if (split = 0) or (defmst = '0') then hgrant(nhmaster) := '1'; end if;
-- latch active master and slave
if hready = '1' then
v.hmaster := nhmaster; v.hmasterd := r.hmaster;
v.hsize := msto(r.hmaster).hsize;
v.hslave := nslave; v.defslv := defslv;
v.hmasterlockd := r.hmasterlock;
if (split = 0) or (r.defmst = '0') then v.htrans := msto(r.hmaster).htrans;
else v.htrans := HTRANS_IDLE; end if;
v.cfgsel := cfgsel;
v.cfga11 := msto(r.hmaster).haddr(11);
v.haddr := msto(r.hmaster).haddr(15 downto 2);
if (msto(r.hmaster).htrans = HTRANS_NONSEQ) or (msto(r.hmaster).htrans = HTRANS_IDLE) then
v.beat := "0001";
elsif (msto(r.hmaster).htrans = HTRANS_SEQ) then
if (fixbrst = 1) then v.beat := r.beat + 1; end if;
end if;
if (split /= 0) then v.defmst := defmst; end if;
end if;
--assign new hmasterlock, v.hmaster is used because if hready
--then master can have changed, and when not hready then the
--previous master will still be selected
v.hmasterlock := msto(v.hmaster).hlock or (r.hmasterlock and not hready);
--if the master asserting hlock received a SPLIT/RETRY response
--to the previous access then disregard the current lock request.
--the bus will otherwise be locked when the previous access is
--retried instead of treating hlock as coupled to the next access.
--use hmasterlockd to keep the bus locked for SPLIT/RETRY to locked
--accesses.
if v.hmaster = r.hmasterd and slvo(r.hslave).hresp(1) = '1' then
if r.hmasterlockd = '0' then
v.hmasterlock := '0'; v.hmasterlockd := '0';
end if;
end if;
-- split support
vsplit := (others => '0');
if SPLIT /= 0 then
vsplit := rsplit;
if slvo(r.hslave).hresp = HRESP_SPLIT then vsplit(r.hmasterd) := '1'; end if;
for i in 0 to nahbs-1 loop
for j in 0 to nahbmx-1 loop
vsplit(j) := vsplit(j) and not slvo(i).hsplit(j);
end loop;
end loop;
end if;
-- interrupt merging
hirq := (others => '0');
if disirq = 0 then
for i in 0 to nahbs-1 loop hirq := hirq or slvo(i).hirq; end loop;
for i in 0 to nahbm-1 loop hirq := hirq or msto(i).hirq; end loop;
end if;
if (split = 0) or (r.defmst = '0') then
vslvi.haddr := haddr;
vslvi.htrans := msto(r.hmaster).htrans;
vslvi.hwrite := msto(r.hmaster).hwrite;
vslvi.hsize := msto(r.hmaster).hsize;
vslvi.hburst := msto(r.hmaster).hburst;
vslvi.hready := hready;
vslvi.hprot := msto(r.hmaster).hprot;
-- vslvi.hmastlock := msto(r.hmaster).hlock;
vslvi.hmastlock := r.hmasterlock;
vslvi.hmaster := conv_std_logic_vector(r.hmaster, 4);
vslvi.hsel := hsel(0 to NAHBSLV-1);
vslvi.hmbsel := hmbsel;
vslvi.hirq := hirq;
else
vslvi := ahbs_in_none;
vslvi.hready := hready;
vslvi.hirq := hirq;
end if;
if acdm = 0 then
vslvi.hwdata := msto(r.hmasterd).hwdata;
else
vslvi.hwdata := ahbselectdata(msto(r.hmasterd).hwdata, r.haddr(4 downto 2), r.hsize);
end if;
vslvi.testen := testen;
vslvi.testrst := testrst;
vslvi.scanen := scanen and testen;
vslvi.testoen := testoen;
vslvi.testin := testen & (scanen and testen) & testsig;
-- reset operation
if (not RESET_ALL) and (rst = '0') then
v.hmaster := RES_r.hmaster; v.hmasterlock := RES_r.hmasterlock;
vsplit := (others => '0');
v.htrans := RES_r.htrans; v.defslv := RES_r.defslv;
v.hslave := RES_r.hslave; v.cfgsel := RES_r.cfgsel;
v.defmst := RES_r.defmst; v.ldefmst := RES_r.ldefmst;
end if;
-- drive master inputs
msti.hgrant <= hgrant;
msti.hready <= hready;
msti.hresp <= hresp;
msti.hrdata <= hrdata;
msti.hirq <= hirq;
msti.testen <= testen;
msti.testrst <= testrst;
msti.scanen <= scanen and testen;
msti.testoen <= testoen;
msti.testin <= testen & (scanen and testen) & testsig;
-- drive slave inputs
slvi <= vslvi;
-- pragma translate_off
--drive internal signals to bus monitor
lslvi <= vslvi;
lmsti.hgrant <= hgrant;
lmsti.hready <= hready;
lmsti.hresp <= hresp;
lmsti.hrdata <= hrdata;
lmsti.hirq <= hirq;
-- pragma translate_on
if split = 0 then v.ldefmst := '0'; v.lsplmst := 0; end if;
rin <= v; rsplitin <= vsplit;
end process;
reg0 : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and rst = '0' then
r <= RES_r;
end if;
end if;
if (split = 0) then r.defmst <= '0'; end if;
end process;
splitreg : if SPLIT /= 0 generate
reg1 : process(clk)
begin
if rising_edge(clk) then
rsplit <= rsplitin;
if RESET_ALL and rst = '0' then
rsplit <= RES_split;
end if;
end if;
end process;
end generate;
nosplitreg : if SPLIT = 0 generate
rsplit <= (others => '0');
end generate;
-- pragma translate_off
ahblog : if ahbtrace /= 0 generate
log : process (clk)
variable hwrite : std_logic;
variable hsize : std_logic_vector(2 downto 0);
variable htrans : std_logic_vector(1 downto 0);
variable hmaster : std_logic_vector(3 downto 0);
variable haddr : std_logic_vector(31 downto 0);
variable hwdata, hrdata : std_logic_vector(127 downto 0);
variable mbit, bitoffs : integer;
variable t : integer;
begin
if rising_edge(clk) then
if htrans(1)='1' and lmsti.hready='0' and (lmsti.hresp="01") then
if hwrite = '1' then
grlib.testlib.print("mst" & tost(hmaster) & ": " & tost(haddr) & " write " & tost(mbit/8) & " bytes [" & tost(lslvi.hwdata(mbit-1+bitoffs downto bitoffs)) & "] - ERROR!");
else
grlib.testlib.print("mst" & tost(hmaster) & ": " & tost(haddr) & " read " & tost(mbit/8) & " bytes [" & tost(lmsti.hrdata(mbit-1+bitoffs downto bitoffs)) & "] - ERROR!");
end if;
end if;
if ((htrans(1) and lmsti.hready) = '1') and (lmsti.hresp = "00") then
mbit := 2**conv_integer(hsize)*8;
bitoffs := 0;
if mbit < ahbdw then
bitoffs := mbit * conv_integer(haddr(log2(ahbdw/8)-1 downto conv_integer(hsize)));
bitoffs := lslvi.hwdata'length-mbit-bitoffs;
end if;
t := (now/1 ns);
if hwrite = '1' then
grlib.testlib.print("mst" & tost(hmaster) & ": " & tost(haddr) & " write " & tost(mbit/8) & " bytes [" & tost(lslvi.hwdata(mbit-1+bitoffs downto bitoffs)) & "]");
else
grlib.testlib.print("mst" & tost(hmaster) & ": " & tost(haddr) & " read " & tost(mbit/8) & " bytes [" & tost(lmsti.hrdata(mbit-1+bitoffs downto bitoffs)) & "]");
end if;
end if;
if lmsti.hready = '1' then
hwrite := lslvi.hwrite;
hsize := lslvi.hsize;
haddr := lslvi.haddr;
htrans := lslvi.htrans;
hmaster := lslvi.hmaster;
end if;
end if;
end process;
end generate;
mon0 : if enbusmon /= 0 generate
mon : ahbmon
generic map(
asserterr => asserterr,
assertwarn => assertwarn,
hmstdisable => hmstdisable,
hslvdisable => hslvdisable,
arbdisable => arbdisable,
nahbm => nahbm,
nahbs => nahbs)
port map(
rst => rst,
clk => clk,
ahbmi => lmsti,
ahbmo => msto,
ahbsi => lslvi,
ahbso => slvo,
err => open);
end generate;
diag : process
type ahbsbank_type is record
start : std_logic_vector(31 downto 8);
stop : std_logic_vector(31 downto 8);
io : std_ulogic;
end record;
type ahbsbanks_type is array (0 to 3) of ahbsbank_type;
type memmap_type is array (0 to nahbs-1) of ahbsbanks_type;
variable k : integer;
variable mask : std_logic_vector(11 downto 0);
variable device : std_logic_vector(11 downto 0);
variable devicei : integer;
variable vendor : std_logic_vector( 7 downto 0);
variable area : std_logic_vector( 1 downto 0);
variable vendori : integer;
variable iosize, tmp : integer;
variable iounit : string(1 to 5) := " byte";
variable memtype : string(1 to 9);
variable iostart : std_logic_vector(11 downto 0) := IOAREA and IOMSK;
variable cfgstart : std_logic_vector(11 downto 0) := CFGAREA and CFGMSK;
variable L1 : line := new string'("");
variable S1 : string(1 to 255);
variable memmap : memmap_type;
begin
wait for 2 ns;
if debug = 0 then wait; end if;
if debug > 0 then
k := 0; mask := IOMSK;
while (k<12) and (mask(k) = '0') loop k := k+1; end loop;
print("ahbctrl: AHB arbiter/multiplexer rev 1");
if ioen /= 0 then
print("ahbctrl: Common I/O area at " & tost(iostart) & "00000, " & tost(2**k) & " Mbyte");
else
print("ahbctrl: Common I/O area disabled");
end if;
print("ahbctrl: AHB masters: " & tost(nahbm) & ", AHB slaves: " & tost(nahbs));
if cfgmask /= 0 then
print("ahbctrl: Configuration area at " & tost(iostart & cfgstart) & "00, 4 kbyte");
else
print("ahbctrl: Configuration area disabled");
end if;
end if;
for i in 0 to nahbm-1 loop
vendor := msto(i).hconfig(0)(31 downto 24);
vendori := conv_integer(vendor);
if vendori /= 0 then
if debug > 1 then
device := msto(i).hconfig(0)(23 downto 12);
devicei := conv_integer(device);
print("ahbctrl: mst" & tost(i) & ": " & iptable(vendori).vendordesc &
iptable(vendori).device_table(devicei));
end if;
for j in 1 to NAHBIR-1 loop
assert (msto(i).hconfig(j) = zx or FULLPNP or ccheck = 0 or cfgmask = 0)
report "AHB master " & tost(i) & " propagates non-zero user defined PnP data, " &
"but AHBCTRL full PnP decoding has not been enabled (check fpnpen VHDL generic)"
severity warning;
end loop;
assert (msto(i).hindex = i) or (icheck = 0)
report "AHB master index error on master " & tost(i) &
". Detected index value " & tost(msto(i).hindex) severity failure;
else
for j in 0 to NAHBCFG-1 loop
assert (msto(i).hconfig(j) = zx or ccheck = 0)
report "AHB master " & tost(i) & " appears to be disabled, " &
"but the master config record is not driven to zero " &
"(check vendor ID or drive unused bus index with appropriate values)."
severity warning;
end loop;
end if;
end loop;
if nahbm < NAHBMST then
for i in nahbm to NAHBMST-1 loop
for j in 0 to NAHBCFG-1 loop
assert (msto(i).hconfig(j) = zx or ccheck = 0)
report "AHB master " & tost(i) & " is outside the range of " &
"decoded master indexes but the master config record is not driven to zero " &
"(check nahbm VHDL generic)."
severity warning;
end loop;
end loop;
end if;
for i in 0 to nahbs-1 loop
vendor := slvo(i).hconfig(0)(31 downto 24);
vendori := conv_integer(vendor);
if vendori /= 0 then
if debug > 1 then
device := slvo(i).hconfig(0)(23 downto 12);
devicei := conv_integer(device);
std.textio.write(L1, "ahbctrl: slv" & tost(i) & ": " & iptable(vendori).vendordesc &
iptable(vendori).device_table(devicei));
std.textio.writeline(OUTPUT, L1);
end if;
for j in 1 to NAHBIR-1 loop
assert (slvo(i).hconfig(j) = zx or FULLPNP or ccheck = 0 or cfgmask = 0)
report "AHB slave " & tost(i) & " propagates non-zero user defined PnP data, " &
"but AHBCTRL full PnP decoding has not been enabled (check fpnpen VHDL generic)."
severity warning;
end loop;
for j in NAHBIR to NAHBCFG-1 loop
area := slvo(i).hconfig(j)(1 downto 0);
mask := slvo(i).hconfig(j)(15 downto 4);
memmap(i)(j mod NAHBIR).start := (others => '0');
memmap(i)(j mod NAHBIR).stop := (others => '0');
memmap(i)(j mod NAHBIR).io := slvo(i).hconfig(j)(0);
if (mask /= "000000000000" or fourgslv = 1) then
case area is
when "01" =>
when "10" =>
k := 0;
while (k<12) and (mask(k) = '0') loop k := k+1; end loop;
if debug > 1 then
std.textio.write(L1, "ahbctrl: memory at " &
tost(slvo(i).hconfig(j)(31 downto 20) and mask) &
"00000, size "& tost(2**k) & " Mbyte");
if slvo(i).hconfig(j)(16) = '1' then
std.textio.write(L1, string'(", cacheable"));
end if;
if slvo(i).hconfig(j)(17) = '1' then
std.textio.write(L1, string'(", prefetch"));
end if;
std.textio.writeline(OUTPUT, L1);
end if;
memmap(i)(j mod NAHBIR).start(31 downto 20) := slvo(i).hconfig(j)(31 downto 20);
memmap(i)(j mod NAHBIR).start(31 downto 20) :=
(slvo(i).hconfig(j)(31 downto 20) and mask);
memmap(i)(j mod NAHBIR).start(19 downto 8) := (others => '0');
memmap(i)(j mod NAHBIR).stop := memmap(i)(j mod NAHBIR).start + 2**(k+12) - 1;
-- Be verbose if an address with bits set outside the area
-- selected by the mask is encountered
assert ((slvo(i).hconfig(j)(31 downto 20) and not mask) = zero32(11 downto 0)) report
"AHB slave " & tost(i) & " may decode an area larger than intended. Bar " &
tost(j mod NAHBIR) & " will have base address " &
tost(slvo(i).hconfig(j)(31 downto 20) and mask) &
"00000, the intended base address may have been " &
tost(slvo(i).hconfig(j)(31 downto 20)) & "00000"
severity warning;
when "11" =>
if ioen /= 0 then
k := 0;
while (k<12) and (mask(k) = '0') loop k := k+1; end loop;
memmap(i)(j mod NAHBIR).start := iostart & (slvo(i).hconfig(j)(31 downto 20) and
slvo(i).hconfig(j)(15 downto 4));
memmap(i)(j mod NAHBIR).stop := memmap(i)(j mod NAHBIR).start + 2**k - 1;
if debug > 1 then
iosize := 256 * 2**k; iounit(1) := ' ';
if (iosize > 1023) then
iosize := iosize/1024; iounit(1) := 'k';
end if;
print("ahbctrl: I/O port at " & tost(iostart &
((slvo(i).hconfig(j)(31 downto 20)) and slvo(i).hconfig(j)(15 downto 4))) &
"00, size "& tost(iosize) & iounit);
end if;
assert ((slvo(i).hconfig(j)(31 downto 20) and not mask) = zero32(11 downto 0)) report
"AHB slave " & tost(i) & " may decode an I/O area larger than intended. Bar " &
tost(j mod NAHBIR) & " will have base address " &
tost(iostart & (slvo(i).hconfig(j)(31 downto 20) and mask)) &
"00, the intended base address may have been " &
tost(iostart & slvo(i).hconfig(j)(31 downto 20)) & "00"
severity warning;
else
assert false report
"AHB slave " & tost(i) & " maps bar " & tost(j mod NAHBIR) &
" to the IO area, but this AHBCTRL has been configured with VHDL generic ioen = 0"
severity warning;
end if;
when others =>
end case;
end if;
end loop;
assert (slvo(i).hindex = i) or (icheck = 0)
report "AHB slave index error on slave " & tost(i) &
". Detected index value " & tost(slvo(i).hindex) severity failure;
if mcheck /= 0 then
for j in 0 to i loop
for k in memmap(i)'range loop
if memmap(i)(k).stop /= zero32(memmap(i)(k).stop'range) then
for l in memmap(j)'range loop
assert ((memmap(i)(k).start >= memmap(j)(l).stop) or
(memmap(i)(k).stop <= memmap(j)(l).start) or
(mcheck /= 2 and (memmap(i)(k).io xor memmap(j)(l).io) = '1') or
(i = j and k = l))
report "AHB slave " & tost(i) & " bank " & tost(k) &
" intersects with AHB slave " & tost(j) & " bank " & tost(l)
severity failure;
end loop;
end if;
end loop;
end loop;
end if;
else
for j in 0 to NAHBCFG-1 loop
assert (slvo(i).hconfig(j) = zx or ccheck = 0)
report "AHB slave " & tost(i) & " appears to be disabled, " &
"but the slave config record is not driven to zero " &
"(check vendor ID or drive unused bus index with appropriate values)."
severity warning;
end loop;
end if;
end loop;
if nahbs < NAHBSLV then
for i in nahbs to NAHBSLV-1 loop
for j in 0 to NAHBCFG-1 loop
assert (slvo(i).hconfig(j) = zx or ccheck = 0)
report "AHB slave " & tost(i) & " is outside the range of " &
"decoded slave indexes but the slave config record is not driven to zero " &
"(check nahbs VHDL generic)."
severity warning;
end loop;
end loop;
end if;
wait;
end process;
-- pragma translate_on
end;
|
entity issue134 is
end entity;
architecture test of issue134 is
function bug_function return string is
begin
return "";
return ""; -- Used to crash here
end function;
begin
end architecture;
|
entity issue134 is
end entity;
architecture test of issue134 is
function bug_function return string is
begin
return "";
return ""; -- Used to crash here
end function;
begin
end architecture;
|
entity issue134 is
end entity;
architecture test of issue134 is
function bug_function return string is
begin
return "";
return ""; -- Used to crash here
end function;
begin
end architecture;
|
entity issue134 is
end entity;
architecture test of issue134 is
function bug_function return string is
begin
return "";
return ""; -- Used to crash here
end function;
begin
end architecture;
|
entity issue134 is
end entity;
architecture test of issue134 is
function bug_function return string is
begin
return "";
return ""; -- Used to crash here
end function;
begin
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc601.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:41 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:58 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:19 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00601ent IS
END c03s04b01x00p01n01i00601ent;
ARCHITECTURE c03s04b01x00p01n01i00601arch OF c03s04b01x00p01n01i00601ent IS
type time_cons_vector is array (15 downto 0) of time;
type time_cons_vector_file is file of time_cons_vector;
constant C19 : time_cons_vector := (others => 3 ns);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : time_cons_vector_file open read_mode is "iofile.32";
variable v : time_cons_vector;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C19) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00601"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00601 - File reading operation (time_cons_vector file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00601arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc601.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:41 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:58 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:19 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00601ent IS
END c03s04b01x00p01n01i00601ent;
ARCHITECTURE c03s04b01x00p01n01i00601arch OF c03s04b01x00p01n01i00601ent IS
type time_cons_vector is array (15 downto 0) of time;
type time_cons_vector_file is file of time_cons_vector;
constant C19 : time_cons_vector := (others => 3 ns);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : time_cons_vector_file open read_mode is "iofile.32";
variable v : time_cons_vector;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C19) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00601"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00601 - File reading operation (time_cons_vector file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00601arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc601.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:41 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:25:58 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:19 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00601ent IS
END c03s04b01x00p01n01i00601ent;
ARCHITECTURE c03s04b01x00p01n01i00601arch OF c03s04b01x00p01n01i00601ent IS
type time_cons_vector is array (15 downto 0) of time;
type time_cons_vector_file is file of time_cons_vector;
constant C19 : time_cons_vector := (others => 3 ns);
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : time_cons_vector_file open read_mode is "iofile.32";
variable v : time_cons_vector;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C19) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00601"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00601 - File reading operation (time_cons_vector file type) failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00601arch;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "AddSubCmp"
-- Project :
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.tbfuncs.all;
-------------------------------------------------------------------------------
entity AddSubCmp_tb is
end AddSubCmp_tb;
-------------------------------------------------------------------------------
architecture behavior of AddSubCmp_tb is
component AddSubCmp
generic (
Width : integer
);
port (
AddOrSub_i : in std_logic;
A_i : in std_logic_vector(Width-1 downto 0);
B_i : in std_logic_vector(Width-1 downto 0);
D_o : out std_logic_vector(Width-1 downto 0);
Carry_i : in std_logic;
Carry_o : out std_logic;
Zero_o : out std_logic;
Sign_o : out std_logic;
Overflow_o : out std_logic
);
end component;
constant CheckOutputDelay : time := 20 ns;
constant SetupNextInputDelay : time := 20 ns;
-- component generics
constant Width : integer := 4;
-- component ports
signal AddOrSub_i : std_logic;
signal A_i : std_logic_vector(Width-1 downto 0);
signal B_i : std_logic_vector(Width-1 downto 0);
signal D_o : std_logic_vector(Width-1 downto 0);
signal Carry_i : std_logic;
signal Carry_o : std_logic;
signal Zero_o : std_logic;
signal Sign_o : std_logic;
signal Overflow_o : std_logic;
procedure CheckAddSubCmp (
constant A : in integer;
constant B : in integer;
constant CarryIn : in std_logic;
constant AddOrSub : in std_logic;
constant SignedCalc : in boolean;
signal A_i : out std_logic_vector(Width-1 downto 0);
signal B_i : out std_logic_vector(Width-1 downto 0);
signal Carry_i : out std_logic;
signal AddOrSub_i : out std_logic;
signal D_o : in std_logic_vector(Width-1 downto 0);
signal Carry_o : in std_logic;
signal Zero_o : in std_logic;
signal Sign_o : in std_logic;
signal Overflow_o : in std_logic
) is
variable A_s : std_logic_vector(Width+1 downto 0);
variable B_s : std_logic_vector(Width+1 downto 0);
variable A_v : integer;
variable B_v : integer;
variable D : integer;
variable D_s : std_logic_vector(Width+1 downto 0);
variable Carry : std_logic;
variable Zero : std_logic;
variable Sign : std_logic;
variable Overflow : std_logic;
variable Temp : integer;
begin -- CheckAddSubCmp
if not SignedCalc then
-- unsigned
assert A < 2**Width report "A is too large (" & integer'image(A) & " > " & integer'image(2**Width-1) severity failure;
assert A >= 0 report "A is too small (" & integer'image(A) & " < " & integer'image(0 ) severity failure;
assert B < 2**Width report "B is too large (" & integer'image(A) & " > " & integer'image(2**Width-1) severity failure;
assert B >= 0 report "B is too small (" & integer'image(A) & " < " & integer'image(0 ) severity failure;
else
-- signed
assert A < 2**(Width-1) report "A is too large (" & integer'image(A) & " > " & integer'image( 2**(Width-1)-1) severity failure;
assert A >= -2**(Width-1) report "A is too small (" & integer'image(A) & " < " & integer'image(-2**(Width-1) ) severity failure;
assert B < 2**(Width-1) report "B is too large (" & integer'image(A) & " > " & integer'image( 2**(Width-1)-1) severity failure;
assert B >= -2**(Width-1) report "B is too small (" & integer'image(A) & " < " & integer'image(-2**(Width-1) ) severity failure;
end if;
-- set defaults
Zero := '0';
Carry := '0';
-- Calculation
A_v := A;
B_v := B;
if A_v < 0 then
A_v := A_v + 2**Width;
end if;
if B_v < 0 then
B_v := B_v + 2**Width;
end if;
if CarryIn = '1' then
if AddOrSub = '0' then
-- add
A_v := A_v + 1;
else
-- sub
A_v := A_v - 1;
end if;
end if;
if AddOrSub = '1' then
B_v := 2**Width - B_v;
end if;
D := A_v + B_v;
A_s := std_logic_vector(to_signed(A,Width+2)); -- use Width+2 to avoid warnings on a truncated vector by to_signed
B_s := std_logic_vector(to_signed(B,Width+2));
D_s := std_logic_vector(to_signed(D,Width+2));
if D > 2**Width-1 then
Carry := '1';
end if;
if unsigned(D_s(Width-1 downto 0)) = 0 then
Zero := '1';
end if;
Sign := D_s(Width-1);
if AddOrSub = '0' then
Overflow := ((not A_s(Width-1)) and (not B_s(Width-1)) and D_s(Width-1) ) or
( A_s(Width-1) and B_s(Width-1) and (not D_s(Width-1)));
else
Overflow := ((not A_s(Width-1)) and B_s(Width-1) and D_s(Width-1) ) or
( A_s(Width-1) and (not B_s(Width-1)) and (not D_s(Width-1)));
end if;
-- set inputs
A_i <= A_s(Width-1 downto 0);
B_i <= B_s(Width-1 downto 0);
Carry_i <= CarryIn;
AddOrSub_i <= AddOrSub;
wait for CheckOutputDelay;
-- check outputs
assert D_o = D_s(Width-1 downto 0)
report "Wrong Result " & Vector2String(D_o) & " for A = " & integer'image(A) & ", B = " & integer'image(B) & ", should be " & Vector2String(D_s) severity error;
assert Carry_o = Carry report "Wrong Carry " & std_logic'image(Carry_o) & " for A = " & integer'image(A) & ", B = " & integer'image(B) & ", should be " & std_logic'image(Carry) severity error;
assert Zero_o = Zero report "Wrong Zero " & std_logic'image(Zero_o) & " for A = " & integer'image(A) & ", B = " & integer'image(B) & ", should be " & std_logic'image(Zero) severity error;
assert Sign_o = Sign report "Wrong Sign " & std_logic'image(Sign_o) & " for A = " & integer'image(A) & ", B = " & integer'image(B) & ", should be " & std_logic'image(Sign) severity error;
assert Overflow_o = Overflow report "Wrong Overflow " & std_logic'image(Overflow_o) & " for A = " & integer'image(A) & ", B = " & integer'image(B) & ", should be " & std_logic'image(Overflow) severity error;
wait for SetupNextInputDelay;
end CheckAddSubCmp;
begin -- behavior
-- component instantiation
DUT: AddSubCmp
generic map (
Width => Width)
port map (
AddOrSub_i => AddOrSub_i,
A_i => A_i,
B_i => B_i,
D_o => D_o,
Carry_i => Carry_i,
Carry_o => Carry_o,
Zero_o => Zero_o,
Sign_o => Sign_o,
Overflow_o => Overflow_o);
-- Check
CheckProc: process
begin
wait for 10 ns;
-- add, unsigned, CarryIn = '0'
assert false report "Add, unsigned, CarryIn = 0" severity note;
for A in 0 to 2**Width-1 loop
for B in 0 to 2**Width-1 loop
CheckAddSubCmp(A,B,'0','0',false, A_i,B_i,Carry_i,AddOrSub_i,D_o,Carry_o,Zero_o,Sign_o,Overflow_o);
end loop; -- B
end loop; -- A
-- add, unsigned, CarryIn = '1'
assert false report "Add, unsigned, CarryIn = 1" severity note;
for A in 0 to 2**Width-1 loop
for B in 0 to 2**Width-1 loop
CheckAddSubCmp(A,B,'1','0',false, A_i,B_i,Carry_i,AddOrSub_i,D_o,Carry_o,Zero_o,Sign_o,Overflow_o);
end loop; -- B
end loop; -- A
-- add, signed, CarryIn = '0'
assert false report "Add, signed, CarryIn = 0" severity note;
for A in -(2**(Width-1)) to 2**(Width-1)-1 loop
for B in -(2**(Width-1)) to 2**(Width-1)-1 loop
CheckAddSubCmp(A,B,'0','0',true, A_i,B_i,Carry_i,AddOrSub_i,D_o,Carry_o,Zero_o,Sign_o,Overflow_o);
end loop; -- B
end loop; -- A
-- add, signed, CarryIn = '1'
assert false report "Add, signed, CarryIn = 1" severity note;
for A in -(2**(Width-1)) to 2**(Width-1)-1 loop
for B in -(2**(Width-1)) to 2**(Width-1)-1 loop
CheckAddSubCmp(A,B,'1','0',true, A_i,B_i,Carry_i,AddOrSub_i,D_o,Carry_o,Zero_o,Sign_o,Overflow_o);
end loop; -- B
end loop; -- A
-- sub, unsigned, CarryIn = '0'
assert false report "Sub, unsigned, CarryIn = 0" severity note;
for A in 0 to 2**Width-1 loop
for B in 0 to 2**Width-1 loop
CheckAddSubCmp(A,B,'0','1',false, A_i,B_i,Carry_i,AddOrSub_i,D_o,Carry_o,Zero_o,Sign_o,Overflow_o);
end loop; -- B
end loop; -- A
-- sub, unsigned, CarryIn = '1'
assert false report "Sub, unsigned, CarryIn = 1" severity note;
for A in 0 to 2**Width-1 loop
for B in 0 to 2**Width-1 loop
CheckAddSubCmp(A,B,'1','1',false, A_i,B_i,Carry_i,AddOrSub_i,D_o,Carry_o,Zero_o,Sign_o,Overflow_o);
end loop; -- B
end loop; -- A
-- sub, signed, CarryIn = '0'
assert false report "Sub, signed, CarryIn = 0" severity note;
for A in -(2**(Width-1)) to 2**(Width-1)-1 loop
for B in -(2**(Width-1)) to 2**(Width-1)-1 loop
CheckAddSubCmp(A,B,'0','1',true, A_i,B_i,Carry_i,AddOrSub_i,D_o,Carry_o,Zero_o,Sign_o,Overflow_o);
end loop; -- B
end loop; -- A
-- sub, signed, CarryIn = '1'
assert false report "Sub, signed, CarryIn = 1" severity note;
for A in -(2**(Width-1)) to 2**(Width-1)-1 loop
for B in -(2**(Width-1)) to 2**(Width-1)-1 loop
CheckAddSubCmp(A,B,'1','1',true, A_i,B_i,Carry_i,AddOrSub_i,D_o,Carry_o,Zero_o,Sign_o,Overflow_o);
end loop; -- B
end loop; -- A
---------------------------------------------------------------------------
-- Simulation is finished
---------------------------------------------------------------------------
assert false
report "### simulation is finished ###"
severity failure ;
end process CheckProc;
end behavior;
configuration AddSubCmp_tb_verilog_cfg of AddSubCmp_tb is
for behavior
for DUT : AddSubCmp
use configuration work.AddSubCmpVerilog;
end for;
end for;
end AddSubCmp_tb_verilog_cfg;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo_64x512_top IS
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
library ieee;
use ieee.std_logic_1164.all;
entity ret02 is
port (di : std_logic_vector (7 downto 0);
res : out integer);
end ret02;
architecture behav of ret02 is
function sign (v : std_logic_vector (7 downto 0)) return integer is
begin
if v (7) = '1' then
return -1;
end if;
return 1;
end sign;
begin
res <= sign (di);
end behav;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_hessian:1.0
-- IP Revision: 41
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_hessian_0_0 IS
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_vga_hessian_0_0;
ARCHITECTURE system_vga_hessian_0_0_arch OF system_vga_hessian_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_hessian_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_hessian IS
GENERIC (
ROW_WIDTH : INTEGER
);
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT vga_hessian;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_hessian_0_0_arch: ARCHITECTURE IS "vga_hessian,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_hessian_0_0_arch : ARCHITECTURE IS "system_vga_hessian_0_0,vga_hessian,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_hessian_0_0_arch: ARCHITECTURE IS "system_vga_hessian_0_0,vga_hessian,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_hessian,x_ipVersion=1.0,x_ipCoreRevision=41,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,ROW_WIDTH=640}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_hessian
GENERIC MAP (
ROW_WIDTH => 640
)
PORT MAP (
clk_x16 => clk_x16,
active => active,
rst => rst,
x_addr => x_addr,
y_addr => y_addr,
g_in => g_in,
hessian_out => hessian_out
);
END system_vga_hessian_0_0_arch;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue Apr 18 23:15:19 2017
-- Host : DESKTOP-I9J3TQJ running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ bram_4096_sim_netlist.vhdl
-- Design : bram_4096
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init is
port (
DOADO : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 4 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA987654321",
INIT_01 => X"0FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA987654321",
INIT_02 => X"0FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA987654321",
INIT_03 => X"0FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA987654321",
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INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 4,
READ_WIDTH_B => 4,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 4,
WRITE_WIDTH_B => 4
)
port map (
ADDRARDADDR(13 downto 2) => addra(11 downto 0),
ADDRARDADDR(1 downto 0) => B"00",
ADDRBWRADDR(13 downto 0) => B"00000000000000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 4) => B"000000000000",
DIADI(3 downto 0) => dina(3 downto 0),
DIBDI(15 downto 0) => B"0000000000000000",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15 downto 4) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 4),
DOADO(3 downto 0) => DOADO(3 downto 0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => ena,
ENBWREN => '0',
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 0) => B"0000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
douta_array : out STD_LOGIC_VECTOR ( 8 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_04 => X"0A09090909090909090909090909090909080808080808080808080808080808",
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INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 8) => B"000000000000000000000000",
DIADI(7 downto 0) => dina(7 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 1) => B"000",
DIPADIP(0) => dina(8),
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7 downto 0) => douta_array(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => douta_array(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 6 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 6 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 9,
READ_WIDTH_B => 9,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 9,
WRITE_WIDTH_B => 9
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 3) => addra(11 downto 0),
ADDRARDADDR(2 downto 0) => B"111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 7) => B"0000000000000000000000000",
DIADI(6 downto 0) => dina(6 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\,
DOADO(6 downto 0) => DOADO(6 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1),
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => ena,
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
port (
DOADO : out STD_LOGIC_VECTOR ( 3 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 3 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init
port map (
DOADO(3 downto 0) => DOADO(3 downto 0),
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(3 downto 0) => dina(3 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
port (
douta_array : out STD_LOGIC_VECTOR ( 8 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 8 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(8 downto 0),
douta_array(8 downto 0) => douta_array(8 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ is
port (
DOADO : out STD_LOGIC_VECTOR ( 6 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 6 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
DOADO(6 downto 0) => DOADO(6 downto 0),
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(6 downto 0) => dina(6 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr is
signal douta_array : STD_LOGIC_VECTOR ( 19 downto 0 );
begin
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(0),
Q => douta(0),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(10),
Q => douta(10),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(11),
Q => douta(11),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(12),
Q => douta(12),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(13),
Q => douta(13),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(14),
Q => douta(14),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(15),
Q => douta(15),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(16),
Q => douta(16),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(17),
Q => douta(17),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(18),
Q => douta(18),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(19),
Q => douta(19),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(1),
Q => douta(1),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(2),
Q => douta(2),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(3),
Q => douta(3),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(4),
Q => douta(4),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(5),
Q => douta(5),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(6),
Q => douta(6),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(7),
Q => douta(7),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(8),
Q => douta(8),
R => '0'
);
\mux_a_wire.mux_reg.ce_pri.douta_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clka,
CE => ena,
D => douta_array(9),
Q => douta(9),
R => '0'
);
\ramloop[0].ram.r\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
port map (
DOADO(3 downto 0) => douta_array(3 downto 0),
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(3 downto 0) => dina(3 downto 0),
ena => ena,
wea(0) => wea(0)
);
\ramloop[1].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0\
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(8 downto 0) => dina(12 downto 4),
douta_array(8 downto 0) => douta_array(12 downto 4),
ena => ena,
wea(0) => wea(0)
);
\ramloop[2].ram.r\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized1\
port map (
DOADO(6 downto 0) => douta_array(19 downto 13),
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(6 downto 0) => dina(19 downto 13),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top is
begin
\valid.cstr\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clka : in STD_LOGIC;
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 11 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 19 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 19 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 11 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 19 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "2";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 6.3587 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "bram_4096.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "bram_4096.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 4096;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 4096;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 4096;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 4096;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "zynq";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(19) <= \<const0>\;
doutb(18) <= \<const0>\;
doutb(17) <= \<const0>\;
doutb(16) <= \<const0>\;
doutb(15) <= \<const0>\;
doutb(14) <= \<const0>\;
doutb(13) <= \<const0>\;
doutb(12) <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5_synth
port map (
addra(11 downto 0) => addra(11 downto 0),
clka => clka,
dina(19 downto 0) => dina(19 downto 0),
douta(19 downto 0) => douta(19 downto 0),
ena => ena,
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 11 downto 0 );
dina : in STD_LOGIC_VECTOR ( 19 downto 0 );
douta : out STD_LOGIC_VECTOR ( 19 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "bram_4096,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 19 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 12;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 12;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "2";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 6.3587 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "bram_4096.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "bram_4096.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 4096;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 4096;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 20;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 20;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 4096;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 4096;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 20;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 20;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_5
port map (
addra(11 downto 0) => addra(11 downto 0),
addrb(11 downto 0) => B"000000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(19 downto 0) => dina(19 downto 0),
dinb(19 downto 0) => B"00000000000000000000",
douta(19 downto 0) => douta(19 downto 0),
doutb(19 downto 0) => NLW_U0_doutb_UNCONNECTED(19 downto 0),
eccpipece => '0',
ena => ena,
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(11 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(11 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(11 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(11 downto 0),
s_axi_rdata(19 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(19 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(19 downto 0) => B"00000000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
|
--------------------------------------------------------------------------------
-- Copyright (c) 2016 David Banks
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : RamRom_Phill
-- /___/ /\ Timestamp : 04/07/2016
-- \ \ / \
-- \___\/\___\
--
--Design Name: RamRom_Phill
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity RamRom_Phill is
port (clock : in std_logic;
reset_n : in std_logic;
-- signals from/to 6502
cpu_addr : in std_logic_vector (15 downto 0);
cpu_we : in std_logic;
cpu_dout : in std_logic_vector (7 downto 0);
cpu_din : out std_logic_vector (7 downto 0);
-- signals from/to external memory system
ExternCE : out std_logic;
ExternWE : out std_logic;
ExternA : out std_logic_vector (18 downto 0);
ExternDin : out std_logic_vector (7 downto 0);
ExternDout : in std_logic_vector (7 downto 0)
);
end RamRom_Phill;
architecture behavioral of RamRom_Phill is
signal BFFE_Enable : std_logic;
signal BFFF_Enable : std_logic;
signal RegBFFE : std_logic_vector (7 downto 0);
signal RegBFFF : std_logic_vector (7 downto 0);
signal RamCE : std_logic;
signal RomCE : std_logic;
signal ExtRAMEN1 : std_logic; -- SwitchLatch[0] on Phill's board
signal ExtRAMEN2 : std_logic; -- SwitchLatch[1] on Phill's board
signal DskRAMEN : std_logic; -- SwitchLatch[1] on Phill's board, not currently used in AtomFPGA
signal DskROMEN : std_logic; -- SwitchLatch[2] on Phill's board
signal BeebMode : std_logic; -- SwitchLatch[3] on Phill's board
signal RomLatch : std_logic_vector (4 downto 0);
signal Addr6000RAM : std_logic;
signal Addr6000ROM : std_logic;
signal Addr7000RAM : std_logic;
signal Addr7000ROM : std_logic;
signal AddrA000RAM : std_logic;
signal AddrA000ROM : std_logic;
begin
Addr6000ROM <= '1' when cpu_addr(15 downto 12) = "0110" and (BeebMode = '1' and (RomLatch /= "00000" or ExtRAMEN1 = '0'))
else '0';
Addr6000RAM <= '1' when cpu_addr(15 downto 12) = "0110" and (BeebMode = '0' or (RomLatch = "00000" and ExtRAMEN1 = '1'))
else '0';
Addr7000ROM <= '1' when cpu_addr(15 downto 12) = "0111" and (BeebMode = '1' and ExtRAMEN2 = '0')
else '0';
Addr7000RAM <= '1' when cpu_addr(15 downto 12) = "0111" and (BeebMode = '0' or ExtRAMEN2 = '1')
else '0';
AddrA000ROM <= '1' when cpu_addr(15 downto 12) = "1010" and (BeebMode = '1' or RomLatch /= "00000" or ExtRAMEN1 = '0')
else '0';
AddrA000RAM <= '1' when cpu_addr(15 downto 12) = "1010" and (BeebMode = '0' and RomLatch = "00000" and ExtRAMEN1 = '1')
else '0';
RamCE <= '1' when cpu_addr(15 downto 12) < "0110" or Addr6000RAM = '1' or Addr7000RAM = '1' or AddrA000RAM = '1'
else '0';
RomCE <= '1' when cpu_addr(15 downto 14) = "11" or Addr6000ROM = '1' or Addr7000ROM = '1' or AddrA000ROM = '1'
else '0';
ExternCE <= RamCE or RomCE;
ExternWE <= cpu_we and RamCE;
ExternDin <= cpu_dout;
cpu_din <= RegBFFE when BFFE_Enable = '1' else
RegBFFF when BFFF_Enable = '1' else
ExternDout;
-------------------------------------------------
-- External address decoding
--
-- external address bus is 18..0 (512KB)
-- bit 18 is always zero
-- bit 17 selects between ROM (0) and RAM (1)
-- bits 16..0 select with 128KB block
-------------------------------------------------
ExternA <=
-- 0x6000 comes from ROM address 0x08000-0x0F000 in Beeb Mode (Ext ROM 1)
( "0001" & RomLatch(2 downto 0) & cpu_addr(11 downto 0)) when Addr6000ROM = '1' else
-- 0x6000 is 4K remappable RAM bank mapped to 0x6000
( "01" & ExtRAMEN1 & cpu_addr(15 downto 0)) when Addr6000RAM = '1' else
-- 0x7000 comes from ROM address 0x19000 in Beeb Mode (Ext ROM 2)
( "0011001" & cpu_addr(11 downto 0)) when Addr7000ROM = '1' else
-- 0x7000 is 4K remappable RAM bank mapped to 0x7000
( "01" & ExtRAMEN2 & cpu_addr(15 downto 0)) when Addr7000RAM = '1' else
-- 0xA000 remappable RAM bank at 0x7000 re-mapped to 0xA000
( "0100111" & cpu_addr(11 downto 0)) when AddrA000RAM = '1' else
-- 0xA000 is bank switched by ROM Latch in Atom Mode
-- 5 bits of RomLatch are used here, to allow any of the 32 pages of FLASH to A000 for in system programming
( "00" & RomLatch & cpu_addr(11 downto 0)) when AddrA000ROM = '1' and BeebMode = '0' else
-- 0xA000 comes from ROM address 0x0A000 in Beeb Mode
( "0011010" & cpu_addr(11 downto 0)) when AddrA000ROM = '1' and BeebMode = '1' else
-- 0xC000-0xFFFF comes from ROM address 0x1C000-0x1FFFF in Beeb Mode
( "001" & cpu_addr(15 downto 0)) when cpu_addr(15 downto 14) = "11" and BeebMode = '1' else
-- 0xC000-0xFFFF comes from ROM address 0x10000-0x17FFF in Atom Mode (2x 16K banks selected SwitchLatch[2])
( "0010" & DskROMEN & cpu_addr(13 downto 0)) when cpu_addr(15 downto 14) = "11" and BeebMode = '0' else
-- RAM
( "010" & cpu_addr);
-------------------------------------------------
-- RAM/ROM Board Registers
-------------------------------------------------
BFFE_Enable <= '1' when cpu_addr(15 downto 0) = "1011111111111110" else '0';
BFFF_Enable <= '1' when cpu_addr(15 downto 0) = "1011111111111111" else '0';
RomLatchProcess : process (reset_n, clock)
begin
if reset_n = '0' then
RegBFFE <= (others => '0');
RegBFFF <= (others => '0');
elsif rising_edge(clock) then
if BFFE_Enable = '1' and cpu_we = '1' then
RegBFFE <= cpu_dout;
end if;
if BFFF_Enable = '1' and cpu_we = '1' then
RegBFFF <= cpu_dout;
end if;
end if;
end process;
ExtRAMEN1 <= RegBFFE(0);
ExtRAMEN2 <= RegBFFE(1);
DskRAMEN <= RegBFFE(1); -- currently unused
DskROMEN <= RegBFFE(2);
BeebMode <= RegBFFE(3);
RomLatch <= RegBFFF(4 downto 0);
end behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:23:44 11/20/2015
-- Design Name:
-- Module Name: random_uniform - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity random_uniform is
end random_uniform;
architecture Behavioral of random_uniform is
begin
end Behavioral;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
ENTITY instructionFetchStage IS
--MIGHT NEED TO MODIFY IF STAGE TO THE WHOLE CPU PIPELINE
port(
clk : in std_logic;
muxInput0 : in std_logic_vector(31 downto 0);
selectInputs : in std_logic;
four : in INTEGER;
structuralStall : IN STD_LOGIC := '0';
pcStall : IN STD_LOGIC := '0';
selectOutput : out std_logic_vector(31 downto 0);
instructionMemoryOutput : out std_logic_vector(31 downto 0)
);
END instructionFetchStage;
architecture instructionFetchStage_arch of instructionFetchStage is
--INSTRUCTION MEMORY
component instructionMemory IS
GENERIC(
-- might need to change it
ram_size : INTEGER := 1024;
mem_delay : time := 1 ns;
clock_period : time := 1 ns
);
PORT (
clock: IN STD_LOGIC;
writedata: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
address: IN INTEGER RANGE 0 TO ram_size-1;
memwrite: IN STD_LOGIC;
memread: IN STD_LOGIC;
readdata: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
waitrequest: OUT STD_LOGIC
);
END component;
--PC
component pc is
port(clk : in std_logic;
reset : in std_logic;
counterOutput : out std_logic_vector(31 downto 0);
counterInput : in std_logic_vector(31 downto 0)
);
end component;
--MUX
component mux is
port(
input0 : in std_logic_vector(31 downto 0);
input1 : in std_logic_vector(31 downto 0);
selectInput : in std_logic;
selectOutput : out std_logic_vector(31 downto 0)
);
end component;
--ADDER
component adder is
port(
plusFour : in integer;
counterOutput : in std_logic_vector(31 downto 0);
adderOutput : out std_logic_vector(31 downto 0)
);
end component;
-- SET SIGNALS
signal rst : std_logic := '0';
signal writedata: std_logic_vector(31 downto 0);
signal address: INTEGER RANGE 0 TO 1024-1;
signal memwrite: STD_LOGIC := '0';
signal memread: STD_LOGIC := '1';
signal readdata: STD_LOGIC_VECTOR (31 DOWNTO 0);
signal waitrequest: STD_LOGIC;
signal pcOutput : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal internal_selectOutput : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal addOutput : STD_LOGIC_VECTOR(31 DOWNTO 0);
--SIGNAL FOR STALLS
signal stallValue : STD_LOGIC_VECTOR(31 DOWNTO 0) := "00000000000000000000000000100000";
signal memoryValue : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal pcInput : STD_LOGIC_VECTOR(31 DOWNTO 0);
begin
selectOutput <= internal_selectOutput;
address <= to_integer(unsigned(addOutput(9 downto 0)))/4;
pcCounter : pc
port map(
clk => clk,
reset => rst,
counterOutput => pcOutput,
counterInput => pcInput
);
add : adder
port map(
plusFour => four,
counterOutput => pcOutput,
adderOutput => addOutput
);
fetchMux : mux
port map(
input0 => addOutput,
input1 => muxInput0,
selectInput => selectInputs,
selectOutput => internal_selectOutput
);
structuralMux : mux
port map (
input0 => memoryValue,
input1 => stallValue,
selectInput => structuralStall,
selectOutput => instructionMemoryOutput
);
pcMux : mux
port map (
input0 => internal_selectOutput,
input1 => pcOutput,
selectInput => pcStall,
selectOutput => pcInput
);
iMem : instructionMemory
GENERIC MAP(
ram_size => 1024
)
PORT MAP(
clk,
writedata,
address,
memwrite,
memread,
memoryValue,
waitrequest
);
end instructionFetchStage_arch; |
-- file: clk_adc.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___250.000____236.250______50.0_______89.528_____85.928
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_____________250____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_adc is
port
(-- Clock in ports
clk_in1_p : in std_logic;
clk_in1_n : in std_logic;
-- Clock out ports
clk_250Mhz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_adc;
architecture xilinx of clk_adc is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_adc,clk_wiz_v5_1,{component_name=clk_adc,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=4.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clk_adc_clk_wiz
port
(-- Clock in ports
clk_in1_p : in std_logic;
clk_in1_n : in std_logic;
-- Clock out ports
clk_250Mhz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end component;
begin
U0: clk_adc_clk_wiz
port map (
-- Clock in ports
clk_in1_p => clk_in1_p,
clk_in1_n => clk_in1_n,
-- Clock out ports
clk_250Mhz => clk_250Mhz,
-- Status and control signals
locked => locked
);
end xilinx;
|
-- file: clk_adc.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___250.000____236.250______50.0_______89.528_____85.928
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_____________250____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_adc is
port
(-- Clock in ports
clk_in1_p : in std_logic;
clk_in1_n : in std_logic;
-- Clock out ports
clk_250Mhz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_adc;
architecture xilinx of clk_adc is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_adc,clk_wiz_v5_1,{component_name=clk_adc,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=4.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clk_adc_clk_wiz
port
(-- Clock in ports
clk_in1_p : in std_logic;
clk_in1_n : in std_logic;
-- Clock out ports
clk_250Mhz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end component;
begin
U0: clk_adc_clk_wiz
port map (
-- Clock in ports
clk_in1_p => clk_in1_p,
clk_in1_n => clk_in1_n,
-- Clock out ports
clk_250Mhz => clk_250Mhz,
-- Status and control signals
locked => locked
);
end xilinx;
|
-- file: clk_adc.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___250.000____236.250______50.0_______89.528_____85.928
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_____________250____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_adc is
port
(-- Clock in ports
clk_in1_p : in std_logic;
clk_in1_n : in std_logic;
-- Clock out ports
clk_250Mhz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_adc;
architecture xilinx of clk_adc is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_adc,clk_wiz_v5_1,{component_name=clk_adc,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=4.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clk_adc_clk_wiz
port
(-- Clock in ports
clk_in1_p : in std_logic;
clk_in1_n : in std_logic;
-- Clock out ports
clk_250Mhz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end component;
begin
U0: clk_adc_clk_wiz
port map (
-- Clock in ports
clk_in1_p => clk_in1_p,
clk_in1_n => clk_in1_n,
-- Clock out ports
clk_250Mhz => clk_250Mhz,
-- Status and control signals
locked => locked
);
end xilinx;
|
-- file: clk_adc.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___250.000____236.250______50.0_______89.528_____85.928
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_____________250____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_adc is
port
(-- Clock in ports
clk_in1_p : in std_logic;
clk_in1_n : in std_logic;
-- Clock out ports
clk_250Mhz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_adc;
architecture xilinx of clk_adc is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_adc,clk_wiz_v5_1,{component_name=clk_adc,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=4.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clk_adc_clk_wiz
port
(-- Clock in ports
clk_in1_p : in std_logic;
clk_in1_n : in std_logic;
-- Clock out ports
clk_250Mhz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end component;
begin
U0: clk_adc_clk_wiz
port map (
-- Clock in ports
clk_in1_p => clk_in1_p,
clk_in1_n => clk_in1_n,
-- Clock out ports
clk_250Mhz => clk_250Mhz,
-- Status and control signals
locked => locked
);
end xilinx;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Ram_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY Ram_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END Ram_exdes;
ARCHITECTURE xilinx OF Ram_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT Ram IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : Ram
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 9.0 Build 235 03/01/2009
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
package CYCLONEIII_COMPONENTS is
--
-- cycloneiii_ff
--
component cycloneiii_ff
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--
-- cycloneiii_ram_block
--
component cycloneiii_ram_block
generic
(
operation_mode : string := "single_port";
mixed_port_feed_through_mode : string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name : string := "ram_name";
init_file : string := "init_file.hex";
init_file_layout : string := "none";
data_interleave_width_in_bits : integer := 1;
data_interleave_offset_in_bits : integer := 1;
port_a_logical_ram_depth : integer := 0;
port_a_logical_ram_width : integer := 0;
port_a_address_clear : string := "none";
port_a_data_out_clock : string := "none";
port_a_data_out_clear : string := "none";
port_a_first_address : integer := 0;
port_a_last_address : integer := 0;
port_a_first_bit_number : integer := 0;
port_a_data_width : integer := 1;
port_a_data_in_clock : string := "clock0";
port_a_address_clock : string := "clock0";
port_a_write_enable_clock : string := "clock0";
port_a_read_enable_clock : string := "clock0";
port_a_byte_enable_clock : string := "clock0";
port_b_logical_ram_depth : integer := 0;
port_b_logical_ram_width : integer := 0;
port_b_data_in_clock : string := "clock1";
port_b_address_clock : string := "clock1";
port_b_address_clear : string := "none";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_data_out_clock : string := "none";
port_b_data_out_clear : string := "none";
port_b_first_address : integer := 0;
port_b_last_address : integer := 0;
port_b_first_bit_number : integer := 0;
port_b_data_width : integer := 1;
port_b_byte_enable_clock : string := "clock1";
port_a_address_width : integer := 1;
port_b_address_width : integer := 1;
port_a_byte_enable_mask_width : integer := 1;
port_b_byte_enable_mask_width : integer := 1;
power_up_uninitialized : string := "false";
port_a_byte_size : integer := 0;
port_b_byte_size : integer := 0;
safe_write : string := "err_on_2clk";
init_file_restructured : string := "unused";
lpm_type : string := "cycloneiii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
-- REMStratix IV -- REMArria II GX -- REMHardCopy III clock_duty_cycle_dependence : STRING := "Auto";
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
port
(
portawe : in std_logic := '0';
portare : in std_logic := '1';
portabyteenamasks : in std_logic_vector (port_a_byte_enable_mask_width - 1 DOWNTO 0) := (others => '1');
portbbyteenamasks : in std_logic_vector (port_b_byte_enable_mask_width - 1 DOWNTO 0) := (others => '1');
portbre : in std_logic := '1';
portbwe : in std_logic := '0';
clr0 : in std_logic := '0';
clr1 : in std_logic := '0';
clk0 : in std_logic := '0';
clk1 : in std_logic := '0';
ena0 : in std_logic := '1';
ena1 : in std_logic := '1';
ena2 : in std_logic := '1';
ena3 : in std_logic := '1';
portadatain : in std_logic_vector (port_a_data_width - 1 DOWNTO 0) := (others => '0');
portbdatain : in std_logic_vector (port_b_data_width - 1 DOWNTO 0) := (others => '0');
portaaddr : in std_logic_vector (port_a_address_width - 1 DOWNTO 0) := (others => '0');
portbaddr : in std_logic_vector (port_b_address_width - 1 DOWNTO 0) := (others => '0');
portaaddrstall : in std_logic := '0';
portbaddrstall : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
portadataout : out std_logic_vector (port_a_data_width - 1 DOWNTO 0);
portbdataout : out std_logic_vector (port_b_data_width - 1 DOWNTO 0)
);
end component;
--
-- CYCLONEIII_LCELL_COMB
--
component cycloneiii_lcell_comb
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
dont_touch : string := "off";
lpm_type : string := "cycloneiii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
end component;
--
-- CYCLONEIII_CLKCTRL
--
component cycloneiii_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneiii_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
end component;
--
-- CYCLONEIII_ROUTING_WIRE
--
component cycloneiii_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
end component;
--
-- CYCLONEIII_PLL
--
COMPONENT cycloneiii_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
lpm_type : string := "cycloneiii_pll";
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
auto_settings : string := "true";
--REM_MF -- VITAL generics
--REM_MF XOn : Boolean := DefGlitchXOn;
--REM_MF MsgOn : Boolean := DefGlitchMsgOn;
--REM_MF MsgOnChecks : Boolean := DefMsgOnChecks;
--REM_MF XOnChecks : Boolean := DefXOnChecks;
--REM_MF TimingChecksOn : Boolean := true;
--REM_MF InstancePath : STRING := "*";
--REM_MF tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
--REM_MF tipd_ena : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_pfdena : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_areset : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_fbin : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_scanclk : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_scandata : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_configupdate : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
--REM_MF tipd_phasestep : VitalDelayType01 := DefPropDelay01;
--REM_MF tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
--REM_MF thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
--REM_MF tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
--REM_MF thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT (
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(4 downto 0);
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END COMPONENT;
--
-- cycloneiii_mac_mult
--
component cycloneiii_mac_mult
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
end component;
--
-- cycloneiii_mac_out
--
component cycloneiii_mac_out
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
dataa_width : integer := 1;
output_clock : string := "none";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_out"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
end component;
--
-- cycloneiii_termination Model
--
COMPONENT cycloneiii_termination
GENERIC (
pullup_control_to_core: string := "false";
power_down : string := "true";
test_mode : string := "false";
left_shift_termination_code : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
clock_divide_by : integer := 32; -- 1, 4, 32
runtime_control : string := "false";
shift_vref_rup : string := "true";
shift_vref_rdn : string := "true";
shifted_vref_control : string := "true";
lpm_type : string := "cycloneiii_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1';
comparatorprobe : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
calibrationdone : OUT std_logic;
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
END COMPONENT;
--
-- CYCLONEIII_IO_IBUF
--
COMPONENT cycloneiii_io_ibuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "cycloneiii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END COMPONENT;
--
-- CYCLONEIII_IO_OBUF
--
COMPONENT cycloneiii_io_obuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- CYCLONEIII_DDIO_OE
--
COMPONENT cycloneiii_ddio_oe
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- CYCLONEIII_DDIO_OUT
--
COMPONENT cycloneiii_ddio_out
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_new_clocking_model : string := "false";
lpm_type : string := "cycloneiii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneiii_pseudo_diff_out
--
COMPONENT cycloneiii_pseudo_diff_out
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "cycloneiii_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- CYCLONEIII_IO_PAD
--
component cycloneiii_io_pad
generic (
lpm_type : STRING := "cycloneiii_io_pad"
);
PORT (
padin : in std_logic := '1';
padout: out std_logic
);
end component;
--
--
-- CYCLONEIII_RUBLOCK
--
--
component cycloneiii_rublock
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type: string := "cycloneiii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end component;
--
--
-- CYCLONEIII_APFCONTROLLER
--
--
component cycloneiii_apfcontroller
generic
(
lpm_type: string := "cycloneiii_apfcontroller"
);
port
(
usermode : out std_logic; --REM_TARPON
nceout : out std_logic
);
end component;
--
-- CYCLONEIII_JTAG
--
component cycloneiii_jtag
generic (
lpm_type : string := "cycloneiii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
--REM_CYCyclone III ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end component;
--
--
-- CYCLONEIII_CRCBLOCK
--
--
component cycloneiii_crcblock
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneiii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end component;
--
--
-- CYCLONEIII_OSCILLATOR
--
--
component cycloneiii_oscillator
generic
(
lpm_type: string := "cycloneiii_oscillator"
);
port
(
oscena : in std_logic;
clkout : out std_logic
);
end component;
end cycloneiii_components;
|
-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 9.0 Build 235 03/01/2009
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
package CYCLONEIII_COMPONENTS is
--
-- cycloneiii_ff
--
component cycloneiii_ff
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--
-- cycloneiii_ram_block
--
component cycloneiii_ram_block
generic
(
operation_mode : string := "single_port";
mixed_port_feed_through_mode : string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name : string := "ram_name";
init_file : string := "init_file.hex";
init_file_layout : string := "none";
data_interleave_width_in_bits : integer := 1;
data_interleave_offset_in_bits : integer := 1;
port_a_logical_ram_depth : integer := 0;
port_a_logical_ram_width : integer := 0;
port_a_address_clear : string := "none";
port_a_data_out_clock : string := "none";
port_a_data_out_clear : string := "none";
port_a_first_address : integer := 0;
port_a_last_address : integer := 0;
port_a_first_bit_number : integer := 0;
port_a_data_width : integer := 1;
port_a_data_in_clock : string := "clock0";
port_a_address_clock : string := "clock0";
port_a_write_enable_clock : string := "clock0";
port_a_read_enable_clock : string := "clock0";
port_a_byte_enable_clock : string := "clock0";
port_b_logical_ram_depth : integer := 0;
port_b_logical_ram_width : integer := 0;
port_b_data_in_clock : string := "clock1";
port_b_address_clock : string := "clock1";
port_b_address_clear : string := "none";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_data_out_clock : string := "none";
port_b_data_out_clear : string := "none";
port_b_first_address : integer := 0;
port_b_last_address : integer := 0;
port_b_first_bit_number : integer := 0;
port_b_data_width : integer := 1;
port_b_byte_enable_clock : string := "clock1";
port_a_address_width : integer := 1;
port_b_address_width : integer := 1;
port_a_byte_enable_mask_width : integer := 1;
port_b_byte_enable_mask_width : integer := 1;
power_up_uninitialized : string := "false";
port_a_byte_size : integer := 0;
port_b_byte_size : integer := 0;
safe_write : string := "err_on_2clk";
init_file_restructured : string := "unused";
lpm_type : string := "cycloneiii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
-- REMStratix IV -- REMArria II GX -- REMHardCopy III clock_duty_cycle_dependence : STRING := "Auto";
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
port
(
portawe : in std_logic := '0';
portare : in std_logic := '1';
portabyteenamasks : in std_logic_vector (port_a_byte_enable_mask_width - 1 DOWNTO 0) := (others => '1');
portbbyteenamasks : in std_logic_vector (port_b_byte_enable_mask_width - 1 DOWNTO 0) := (others => '1');
portbre : in std_logic := '1';
portbwe : in std_logic := '0';
clr0 : in std_logic := '0';
clr1 : in std_logic := '0';
clk0 : in std_logic := '0';
clk1 : in std_logic := '0';
ena0 : in std_logic := '1';
ena1 : in std_logic := '1';
ena2 : in std_logic := '1';
ena3 : in std_logic := '1';
portadatain : in std_logic_vector (port_a_data_width - 1 DOWNTO 0) := (others => '0');
portbdatain : in std_logic_vector (port_b_data_width - 1 DOWNTO 0) := (others => '0');
portaaddr : in std_logic_vector (port_a_address_width - 1 DOWNTO 0) := (others => '0');
portbaddr : in std_logic_vector (port_b_address_width - 1 DOWNTO 0) := (others => '0');
portaaddrstall : in std_logic := '0';
portbaddrstall : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
portadataout : out std_logic_vector (port_a_data_width - 1 DOWNTO 0);
portbdataout : out std_logic_vector (port_b_data_width - 1 DOWNTO 0)
);
end component;
--
-- CYCLONEIII_LCELL_COMB
--
component cycloneiii_lcell_comb
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
dont_touch : string := "off";
lpm_type : string := "cycloneiii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
end component;
--
-- CYCLONEIII_CLKCTRL
--
component cycloneiii_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneiii_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
end component;
--
-- CYCLONEIII_ROUTING_WIRE
--
component cycloneiii_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
end component;
--
-- CYCLONEIII_PLL
--
COMPONENT cycloneiii_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
lpm_type : string := "cycloneiii_pll";
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
auto_settings : string := "true";
--REM_MF -- VITAL generics
--REM_MF XOn : Boolean := DefGlitchXOn;
--REM_MF MsgOn : Boolean := DefGlitchMsgOn;
--REM_MF MsgOnChecks : Boolean := DefMsgOnChecks;
--REM_MF XOnChecks : Boolean := DefXOnChecks;
--REM_MF TimingChecksOn : Boolean := true;
--REM_MF InstancePath : STRING := "*";
--REM_MF tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
--REM_MF tipd_ena : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_pfdena : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_areset : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_fbin : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_scanclk : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_scandata : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_configupdate : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
--REM_MF tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
--REM_MF tipd_phasestep : VitalDelayType01 := DefPropDelay01;
--REM_MF tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
--REM_MF thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
--REM_MF tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
--REM_MF thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT (
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(4 downto 0);
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END COMPONENT;
--
-- cycloneiii_mac_mult
--
component cycloneiii_mac_mult
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
end component;
--
-- cycloneiii_mac_out
--
component cycloneiii_mac_out
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
dataa_width : integer := 1;
output_clock : string := "none";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_out"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
end component;
--
-- cycloneiii_termination Model
--
COMPONENT cycloneiii_termination
GENERIC (
pullup_control_to_core: string := "false";
power_down : string := "true";
test_mode : string := "false";
left_shift_termination_code : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
clock_divide_by : integer := 32; -- 1, 4, 32
runtime_control : string := "false";
shift_vref_rup : string := "true";
shift_vref_rdn : string := "true";
shifted_vref_control : string := "true";
lpm_type : string := "cycloneiii_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1';
comparatorprobe : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
calibrationdone : OUT std_logic;
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
END COMPONENT;
--
-- CYCLONEIII_IO_IBUF
--
COMPONENT cycloneiii_io_ibuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "cycloneiii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END COMPONENT;
--
-- CYCLONEIII_IO_OBUF
--
COMPONENT cycloneiii_io_obuf
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- CYCLONEIII_DDIO_OE
--
COMPONENT cycloneiii_ddio_oe
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- CYCLONEIII_DDIO_OUT
--
COMPONENT cycloneiii_ddio_out
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_new_clocking_model : string := "false";
lpm_type : string := "cycloneiii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- cycloneiii_pseudo_diff_out
--
COMPONENT cycloneiii_pseudo_diff_out
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "cycloneiii_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END COMPONENT;
--
-- CYCLONEIII_IO_PAD
--
component cycloneiii_io_pad
generic (
lpm_type : STRING := "cycloneiii_io_pad"
);
PORT (
padin : in std_logic := '1';
padout: out std_logic
);
end component;
--
--
-- CYCLONEIII_RUBLOCK
--
--
component cycloneiii_rublock
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type: string := "cycloneiii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end component;
--
--
-- CYCLONEIII_APFCONTROLLER
--
--
component cycloneiii_apfcontroller
generic
(
lpm_type: string := "cycloneiii_apfcontroller"
);
port
(
usermode : out std_logic; --REM_TARPON
nceout : out std_logic
);
end component;
--
-- CYCLONEIII_JTAG
--
component cycloneiii_jtag
generic (
lpm_type : string := "cycloneiii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
--REM_CYCyclone III ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end component;
--
--
-- CYCLONEIII_CRCBLOCK
--
--
component cycloneiii_crcblock
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneiii_crcblock"
);
port (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
ldsrc : in std_logic := '0';
crcerror : out std_logic;
regout : out std_logic
);
end component;
--
--
-- CYCLONEIII_OSCILLATOR
--
--
component cycloneiii_oscillator
generic
(
lpm_type: string := "cycloneiii_oscillator"
);
port
(
oscena : in std_logic;
clkout : out std_logic
);
end component;
end cycloneiii_components;
|
--------------------------------------------------------------------------------
-- file name : sip_vp680_host_if.vhd
--
-- author : P. Kortekaas
--
-- company : 4dsp
--
-- item : number
--
-- language : vhdl
--
--------------------------------------------------------------------------------
-- description
-- ===========
--
--
-- notes:
--------------------------------------------------------------------------------
--
-- disclaimer: limited warranty and disclaimer. these designs are
-- provided to you as is. 4dsp specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4dsp does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the designs
-- will be corrected. furthermore, 4dsp does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- limitation of liability. in no event will 4dsp or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. this limitation will apply even if 4dsp
-- has been advised of the possibility of such damage. this
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
----------------------------------------------
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Specify libraries
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
library std;
use std.textio.all;
library work;
use work.txt_util.all;
use work.std_logic_textio.all;
--------------------------------------------------------------------------------
-- Entity declaration
--------------------------------------------------------------------------------
entity generic_host_emu is
generic (
global_start_addr_gen : std_logic_vector(27 downto 0);
global_stop_addr_gen : std_logic_vector(27 downto 0);
private_start_addr_gen : std_logic_vector(27 downto 0);
private_stop_addr_gen : std_logic_vector(27 downto 0)
);
port (
--Wormhole 'cmdclk_out' of type 'cmdclk_out':
cmdclk_out_cmdclk : out std_logic;
--Wormhole 'cmd_in' of type 'cmd_in':
cmd_in_cmdin : in std_logic_vector(63 downto 0);
cmd_in_cmdin_val : in std_logic;
--Wormhole 'cmd_out' of type 'cmd_out':
cmd_out_cmdout : out std_logic_vector(63 downto 0);
cmd_out_cmdout_val : out std_logic;
--Wormhole 'ifpga_rst_out' of type 'ifpga_rst_out':
ifpga_rst_out_ifpga_rst : out std_logic;
--Wormhole 'clk' of type 'clkin':
clk_clkin : in std_logic_vector(31 downto 0);
--Wormhole 'rst' of type 'rst_in':
rst_rstin : in std_logic_vector(31 downto 0);
--Wormhole 'ext_vp680_host_if' of type 'ext_vp680_host_if':
sys_clk : in std_logic;
sys_reset_n : in std_logic;
--Wormhole 'in_data' of type 'wh_in':
in_data_in_stop : out std_logic;
in_data_in_dval : in std_logic;
in_data_in_data : in std_logic_vector(63 downto 0);
--Wormhole 'out_data' of type 'wh_out':
out_data_out_stop : in std_logic;
out_data_out_dval : out std_logic;
out_data_out_data : out std_logic_vector(63 downto 0)
);
end entity generic_host_emu;
--------------------------------------------------------------------------------
-- Architecture declaration
--------------------------------------------------------------------------------
architecture behavioral of generic_host_emu is
--------------------------------------------------------------------------------
-- Constant declarations
--------------------------------------------------------------------------------
type std2d_32b is array(natural range <>) of std_logic_vector(31 downto 0);
-----------------------------------------------------------------------------------
-- Signal declarations
-----------------------------------------------------------------------------------
signal clk_cmd : std_logic := '0';
signal clk125m : std_logic := '0';
signal out_cmd_val : std_logic := '0';
signal out_cmd : std_logic_vector(63 downto 0) := (others => '0');
signal in_cmd_val : std_logic;
signal in_cmd : std_logic_vector(63 downto 0);
signal write_data_val : std_logic := '0';
signal write_data : std_logic_vector(63 downto 0) := (others => '0');
signal read_data_stop : std_logic := '1';
signal read_data_val : std_logic;
signal read_data : std_logic_vector(63 downto 0);
-----------------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------
-- Clock generation
--------------------------------------------------------------------------------
clk_cmd <= sys_clk;
clk125m <= sys_clk;
--------------------------------------------------------------------------------
-- Perform SIP register read and writes
--------------------------------------------------------------------------------
process
file CMD_SCRIPT : text;
file INPUT_FILE : text;
variable BAR_array :std2d_32b(15 downto 0);
variable BAR_idx :integer range 16 downto 0 :=0;
variable textline : line;
variable sip_command : string(1 to 80);
variable char1 : string(1 to 1);
variable WaitDelay : integer := 0;
variable sip_addr : std_logic_vector(31 downto 0);
variable sip_bar_idx : std_logic_vector(3 downto 0);
variable sip_data : std_logic_vector(31 downto 0);
variable dmapush_size : std_logic_vector(31 downto 0);
variable dmapull_size : std_logic_vector(31 downto 0);
-- Procedure for writing a register
procedure cmd_write(addr : in std_logic_vector(31 downto 0); data : in std_logic_vector(31 downto 0)) is
begin
wait until clk_cmd = '0';
out_cmd_val <= '1';
out_cmd <= x"1" & addr(27 downto 0) & data;
wait until clk_cmd = '1';
wait until clk_cmd = '0';
out_cmd_val <= '0';
REPORT "CMD Write: ADDR 0x" & hstr(addr) & " DATA " & str(conv_integer(data));
end procedure cmd_write;
-- Procedure for reading a register
procedure cmd_read(addr : in std_logic_vector(31 downto 0); data : inout std_logic_vector(31 downto 0)) is
begin
wait until clk_cmd = '0';
out_cmd_val <= '1';
out_cmd <= x"2" & addr(27 downto 0) & conv_std_logic_vector(0, 32);
wait until clk_cmd = '1';
wait until clk_cmd = '0';
out_cmd_val <= '0';
wait until in_cmd_val = '1';
data := in_cmd(31 downto 0);
REPORT "CMD Read: ADDR 0x" & hstr(addr) & " DATA " & str(conv_integer(data));
end procedure cmd_read;
-- Procedure for pushing DMA to FPGA B
procedure dma_push(dma_size : in std_logic_vector(31 downto 0)) is
variable textline : line;
variable size : integer;
variable dma_data : std_logic_vector(63 downto 0);
begin
size := conv_integer(dma_size);
while (size > 0) loop
wait until clk125m = '0';
--if (in0_stop = '0') then
readline(INPUT_FILE, textline);
hread(textline, dma_data);
write_data_val <= '1';
write_data <= dma_data;
wait until clk125m = '1';
wait until clk125m = '0';
write_data_val <= '0';
size := size - 8;
--end if;
end loop;
REPORT "DMA Push, Size " & str(conv_integer(dma_size)) & " bytes";
end procedure dma_push;
-- Procedure for pulling DMA from FPGA B
procedure dma_pull(dma_size : in std_logic_vector(31 downto 0)) is
variable size : integer;
begin
-- This precedure only pulls down the stop signal for the right amount of time
-- data that comes available is written to file by the "Write data to file"
-- process elsewhere in this file.
size := conv_integer(dma_size);
-- Start reading fast, untill 8 words (64 bytes) left
while (size > 64) loop
wait until clk125m = '1';
read_data_stop <= '0';
if (read_data_val = '1') then
size := size - 8;
end if;
wait until clk125m = '0';
end loop;
-- Read the last words slowly
while (size > 0) loop
wait until clk125m = '1';
read_data_stop <= '0';
if (read_data_val = '1') then
size := size - 8;
end if;
wait until clk125m = '0';
wait until clk125m = '1';
read_data_stop <= '1';
if (read_data_val = '1') then
size := size - 8;
end if;
wait until clk125m = '0';
wait until clk125m = '1';
if (read_data_val = '1') then
size := size - 8;
end if;
wait until clk125m = '0';
end loop;
read_data_stop <= '1';
REPORT "DMA Pull, Size " & str(conv_integer(dma_size)) & " bytes";
end procedure dma_pull;
variable fstatus: file_open_status; -- declare file
variable sip_mode:std_logic:='0';
begin
--script should start with 16 BAR definitions
for i in 1 to 15 loop
BAR_array(i) := (others=>'0');
end loop;
BAR_idx :=0;
wait for 1 us;
--open advanced sip script which is not compatible with the software sip script parser
file_open(fstatus,CMD_SCRIPT, "sip_cmd.asip", read_mode);
if (fstatus=OPEN_OK) then
sip_mode :='1';
else
file_open(fstatus,CMD_SCRIPT, "sip_cmd.sip", read_mode);
sip_mode := '0';
end if;
file_open(INPUT_FILE, "input.txt", read_mode);
while not endfile(CMD_SCRIPT) loop
readline(CMD_SCRIPT, textline);
next when textline'length = 0; -- Skip empty lines
-- Reset command
for i in 1 to sip_command'length loop
sip_command(i to i) := " ";
end loop;
-- Read command
for i in 1 to sip_command'length loop
-- Exit when exeeding the number of characters on the line
exit when i > textline'length;
read(textline, sip_command(i to i));
-- Comment
if (sip_command(1 to 1) = ";") then
read(textline, sip_command(1 to textline'length));
REPORT(sip_command) SEVERITY warning;
exit;
end if;
if(sip_mode='1') then
--assign to next BAR
if (sip_command(1 to 7) = "BAR_ADR") then
-- Collect address
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, BAR_array(BAR_idx));
BAR_idx := BAR_idx + 1;
exit;
end if;
end if;
-- Write access
if (sip_command(1 to 7) = "REG_SET") then
-- Collect address
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, sip_addr);
-- Collect data
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, sip_data);
if(sip_mode='1') then
-- Collect BAR index
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, sip_bar_idx);
-- Write
cmd_write(sip_addr+BAR_array(conv_integer(sip_bar_idx)), sip_data);
else
cmd_write(sip_addr, sip_data);
end if;
exit;
end if;
-- Read access
if (sip_command(1 to 7) = "REG_GET") then
-- Collect address
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, sip_addr);
if(sip_mode='1') then
-- Collect BAR index
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, sip_bar_idx);
-- Read
cmd_read(sip_addr+BAR_array(conv_integer(sip_bar_idx)), sip_data);
else
cmd_read(sip_addr, sip_data);
end if;
exit;
end if;
-- DMA Push access (from host to card)
if (sip_command(1 to 7) = "DMAPUSH") then
-- Collect size
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, dmapush_size);
-- DMA to FPGA B
dma_push(dmapush_size);
exit;
end if;
-- DMA Pull access (from card to host)
if (sip_command(1 to 7) = "DMAPULL") then
-- Collect size
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, dmapull_size);
-- DMA from FPGA B
dma_pull(dmapull_size);
exit;
end if;
-- Wait
if (sip_command(1 to 4) = "WAIT") then
char1 := " ";
while (char1 /= "=") loop
read(textline, char1);
end loop;
read(textline, WaitDelay);
REPORT("Wait for " & str(WaitDelay) & " us");
for i in 1 to WaitDelay loop
wait for 1 us;
end loop;
exit;
end if;
end loop;
wait for 1 us;
end loop;
file_close(CMD_SCRIPT);
file_close(INPUT_FILE);
REPORT("Ready with reading SIP CMD script!");
wait for 10 us;
REPORT "Testbench ended" severity warning;
wait;
end process;
--------------------------------------------------------------------------------
-- Write data to file
--------------------------------------------------------------------------------
process
file OUTPUT_FILE : text;
variable textline : line;
begin
file_open(OUTPUT_FILE, "output.txt", write_mode);
file_close(OUTPUT_FILE);
while true loop
wait until clk125m = '1';
if (read_data_val = '1') then
file_open(OUTPUT_FILE, "output.txt", append_mode);
hwrite(textline, read_data);
writeline(OUTPUT_FILE, textline);
file_close(OUTPUT_FILE);
end if;
wait until clk125m = '0';
end loop;
wait;
end process;
--------------------------------------------------------------------------------
-- Connect entity
--------------------------------------------------------------------------------
--Wormhole 'cmdclk_out' of type 'cmdclk_out':
cmdclk_out_cmdclk <= clk_cmd;
--Wormhole 'cmd_out' of type 'cmd_out':
cmd_out_cmdout <= out_cmd;
cmd_out_cmdout_val <= out_cmd_val;
--Wormhole 'cmd_in' of type 'cmd_in':
in_cmd <= cmd_in_cmdin;
in_cmd_val <= cmd_in_cmdin_val;
--Wormhole 'ext_fc6301_host_if' of type 'ext_fc6301_host_if':
ifpga_rst_out_ifpga_rst <= not sys_reset_n;
--Wormhole 'in_data' of type 'wh_in':
in_data_in_stop <= read_data_stop;
read_data_val <= in_data_in_dval;
read_data <= in_data_in_data;
--Wormhole 'out_data' of type 'wh_out':
out_data_out_dval <= write_data_val;
out_data_out_data <= write_data;
--------------------------------------------------------------------------------
-- End
--------------------------------------------------------------------------------
end architecture behavioral;
|
--------------------------------------------------------------------------------
-- file name : sip_vp680_host_if.vhd
--
-- author : P. Kortekaas
--
-- company : 4dsp
--
-- item : number
--
-- language : vhdl
--
--------------------------------------------------------------------------------
-- description
-- ===========
--
--
-- notes:
--------------------------------------------------------------------------------
--
-- disclaimer: limited warranty and disclaimer. these designs are
-- provided to you as is. 4dsp specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4dsp does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the designs
-- will be corrected. furthermore, 4dsp does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- limitation of liability. in no event will 4dsp or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. this limitation will apply even if 4dsp
-- has been advised of the possibility of such damage. this
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
----------------------------------------------
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Specify libraries
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
library std;
use std.textio.all;
library work;
use work.txt_util.all;
use work.std_logic_textio.all;
--------------------------------------------------------------------------------
-- Entity declaration
--------------------------------------------------------------------------------
entity generic_host_emu is
generic (
global_start_addr_gen : std_logic_vector(27 downto 0);
global_stop_addr_gen : std_logic_vector(27 downto 0);
private_start_addr_gen : std_logic_vector(27 downto 0);
private_stop_addr_gen : std_logic_vector(27 downto 0)
);
port (
--Wormhole 'cmdclk_out' of type 'cmdclk_out':
cmdclk_out_cmdclk : out std_logic;
--Wormhole 'cmd_in' of type 'cmd_in':
cmd_in_cmdin : in std_logic_vector(63 downto 0);
cmd_in_cmdin_val : in std_logic;
--Wormhole 'cmd_out' of type 'cmd_out':
cmd_out_cmdout : out std_logic_vector(63 downto 0);
cmd_out_cmdout_val : out std_logic;
--Wormhole 'ifpga_rst_out' of type 'ifpga_rst_out':
ifpga_rst_out_ifpga_rst : out std_logic;
--Wormhole 'clk' of type 'clkin':
clk_clkin : in std_logic_vector(31 downto 0);
--Wormhole 'rst' of type 'rst_in':
rst_rstin : in std_logic_vector(31 downto 0);
--Wormhole 'ext_vp680_host_if' of type 'ext_vp680_host_if':
sys_clk : in std_logic;
sys_reset_n : in std_logic;
--Wormhole 'in_data' of type 'wh_in':
in_data_in_stop : out std_logic;
in_data_in_dval : in std_logic;
in_data_in_data : in std_logic_vector(63 downto 0);
--Wormhole 'out_data' of type 'wh_out':
out_data_out_stop : in std_logic;
out_data_out_dval : out std_logic;
out_data_out_data : out std_logic_vector(63 downto 0)
);
end entity generic_host_emu;
--------------------------------------------------------------------------------
-- Architecture declaration
--------------------------------------------------------------------------------
architecture behavioral of generic_host_emu is
--------------------------------------------------------------------------------
-- Constant declarations
--------------------------------------------------------------------------------
type std2d_32b is array(natural range <>) of std_logic_vector(31 downto 0);
-----------------------------------------------------------------------------------
-- Signal declarations
-----------------------------------------------------------------------------------
signal clk_cmd : std_logic := '0';
signal clk125m : std_logic := '0';
signal out_cmd_val : std_logic := '0';
signal out_cmd : std_logic_vector(63 downto 0) := (others => '0');
signal in_cmd_val : std_logic;
signal in_cmd : std_logic_vector(63 downto 0);
signal write_data_val : std_logic := '0';
signal write_data : std_logic_vector(63 downto 0) := (others => '0');
signal read_data_stop : std_logic := '1';
signal read_data_val : std_logic;
signal read_data : std_logic_vector(63 downto 0);
-----------------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------
-- Clock generation
--------------------------------------------------------------------------------
clk_cmd <= sys_clk;
clk125m <= sys_clk;
--------------------------------------------------------------------------------
-- Perform SIP register read and writes
--------------------------------------------------------------------------------
process
file CMD_SCRIPT : text;
file INPUT_FILE : text;
variable BAR_array :std2d_32b(15 downto 0);
variable BAR_idx :integer range 16 downto 0 :=0;
variable textline : line;
variable sip_command : string(1 to 80);
variable char1 : string(1 to 1);
variable WaitDelay : integer := 0;
variable sip_addr : std_logic_vector(31 downto 0);
variable sip_bar_idx : std_logic_vector(3 downto 0);
variable sip_data : std_logic_vector(31 downto 0);
variable dmapush_size : std_logic_vector(31 downto 0);
variable dmapull_size : std_logic_vector(31 downto 0);
-- Procedure for writing a register
procedure cmd_write(addr : in std_logic_vector(31 downto 0); data : in std_logic_vector(31 downto 0)) is
begin
wait until clk_cmd = '0';
out_cmd_val <= '1';
out_cmd <= x"1" & addr(27 downto 0) & data;
wait until clk_cmd = '1';
wait until clk_cmd = '0';
out_cmd_val <= '0';
REPORT "CMD Write: ADDR 0x" & hstr(addr) & " DATA " & str(conv_integer(data));
end procedure cmd_write;
-- Procedure for reading a register
procedure cmd_read(addr : in std_logic_vector(31 downto 0); data : inout std_logic_vector(31 downto 0)) is
begin
wait until clk_cmd = '0';
out_cmd_val <= '1';
out_cmd <= x"2" & addr(27 downto 0) & conv_std_logic_vector(0, 32);
wait until clk_cmd = '1';
wait until clk_cmd = '0';
out_cmd_val <= '0';
wait until in_cmd_val = '1';
data := in_cmd(31 downto 0);
REPORT "CMD Read: ADDR 0x" & hstr(addr) & " DATA " & str(conv_integer(data));
end procedure cmd_read;
-- Procedure for pushing DMA to FPGA B
procedure dma_push(dma_size : in std_logic_vector(31 downto 0)) is
variable textline : line;
variable size : integer;
variable dma_data : std_logic_vector(63 downto 0);
begin
size := conv_integer(dma_size);
while (size > 0) loop
wait until clk125m = '0';
--if (in0_stop = '0') then
readline(INPUT_FILE, textline);
hread(textline, dma_data);
write_data_val <= '1';
write_data <= dma_data;
wait until clk125m = '1';
wait until clk125m = '0';
write_data_val <= '0';
size := size - 8;
--end if;
end loop;
REPORT "DMA Push, Size " & str(conv_integer(dma_size)) & " bytes";
end procedure dma_push;
-- Procedure for pulling DMA from FPGA B
procedure dma_pull(dma_size : in std_logic_vector(31 downto 0)) is
variable size : integer;
begin
-- This precedure only pulls down the stop signal for the right amount of time
-- data that comes available is written to file by the "Write data to file"
-- process elsewhere in this file.
size := conv_integer(dma_size);
-- Start reading fast, untill 8 words (64 bytes) left
while (size > 64) loop
wait until clk125m = '1';
read_data_stop <= '0';
if (read_data_val = '1') then
size := size - 8;
end if;
wait until clk125m = '0';
end loop;
-- Read the last words slowly
while (size > 0) loop
wait until clk125m = '1';
read_data_stop <= '0';
if (read_data_val = '1') then
size := size - 8;
end if;
wait until clk125m = '0';
wait until clk125m = '1';
read_data_stop <= '1';
if (read_data_val = '1') then
size := size - 8;
end if;
wait until clk125m = '0';
wait until clk125m = '1';
if (read_data_val = '1') then
size := size - 8;
end if;
wait until clk125m = '0';
end loop;
read_data_stop <= '1';
REPORT "DMA Pull, Size " & str(conv_integer(dma_size)) & " bytes";
end procedure dma_pull;
variable fstatus: file_open_status; -- declare file
variable sip_mode:std_logic:='0';
begin
--script should start with 16 BAR definitions
for i in 1 to 15 loop
BAR_array(i) := (others=>'0');
end loop;
BAR_idx :=0;
wait for 1 us;
--open advanced sip script which is not compatible with the software sip script parser
file_open(fstatus,CMD_SCRIPT, "sip_cmd.asip", read_mode);
if (fstatus=OPEN_OK) then
sip_mode :='1';
else
file_open(fstatus,CMD_SCRIPT, "sip_cmd.sip", read_mode);
sip_mode := '0';
end if;
file_open(INPUT_FILE, "input.txt", read_mode);
while not endfile(CMD_SCRIPT) loop
readline(CMD_SCRIPT, textline);
next when textline'length = 0; -- Skip empty lines
-- Reset command
for i in 1 to sip_command'length loop
sip_command(i to i) := " ";
end loop;
-- Read command
for i in 1 to sip_command'length loop
-- Exit when exeeding the number of characters on the line
exit when i > textline'length;
read(textline, sip_command(i to i));
-- Comment
if (sip_command(1 to 1) = ";") then
read(textline, sip_command(1 to textline'length));
REPORT(sip_command) SEVERITY warning;
exit;
end if;
if(sip_mode='1') then
--assign to next BAR
if (sip_command(1 to 7) = "BAR_ADR") then
-- Collect address
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, BAR_array(BAR_idx));
BAR_idx := BAR_idx + 1;
exit;
end if;
end if;
-- Write access
if (sip_command(1 to 7) = "REG_SET") then
-- Collect address
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, sip_addr);
-- Collect data
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, sip_data);
if(sip_mode='1') then
-- Collect BAR index
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, sip_bar_idx);
-- Write
cmd_write(sip_addr+BAR_array(conv_integer(sip_bar_idx)), sip_data);
else
cmd_write(sip_addr, sip_data);
end if;
exit;
end if;
-- Read access
if (sip_command(1 to 7) = "REG_GET") then
-- Collect address
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, sip_addr);
if(sip_mode='1') then
-- Collect BAR index
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, sip_bar_idx);
-- Read
cmd_read(sip_addr+BAR_array(conv_integer(sip_bar_idx)), sip_data);
else
cmd_read(sip_addr, sip_data);
end if;
exit;
end if;
-- DMA Push access (from host to card)
if (sip_command(1 to 7) = "DMAPUSH") then
-- Collect size
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, dmapush_size);
-- DMA to FPGA B
dma_push(dmapush_size);
exit;
end if;
-- DMA Pull access (from card to host)
if (sip_command(1 to 7) = "DMAPULL") then
-- Collect size
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, dmapull_size);
-- DMA from FPGA B
dma_pull(dmapull_size);
exit;
end if;
-- Wait
if (sip_command(1 to 4) = "WAIT") then
char1 := " ";
while (char1 /= "=") loop
read(textline, char1);
end loop;
read(textline, WaitDelay);
REPORT("Wait for " & str(WaitDelay) & " us");
for i in 1 to WaitDelay loop
wait for 1 us;
end loop;
exit;
end if;
end loop;
wait for 1 us;
end loop;
file_close(CMD_SCRIPT);
file_close(INPUT_FILE);
REPORT("Ready with reading SIP CMD script!");
wait for 10 us;
REPORT "Testbench ended" severity warning;
wait;
end process;
--------------------------------------------------------------------------------
-- Write data to file
--------------------------------------------------------------------------------
process
file OUTPUT_FILE : text;
variable textline : line;
begin
file_open(OUTPUT_FILE, "output.txt", write_mode);
file_close(OUTPUT_FILE);
while true loop
wait until clk125m = '1';
if (read_data_val = '1') then
file_open(OUTPUT_FILE, "output.txt", append_mode);
hwrite(textline, read_data);
writeline(OUTPUT_FILE, textline);
file_close(OUTPUT_FILE);
end if;
wait until clk125m = '0';
end loop;
wait;
end process;
--------------------------------------------------------------------------------
-- Connect entity
--------------------------------------------------------------------------------
--Wormhole 'cmdclk_out' of type 'cmdclk_out':
cmdclk_out_cmdclk <= clk_cmd;
--Wormhole 'cmd_out' of type 'cmd_out':
cmd_out_cmdout <= out_cmd;
cmd_out_cmdout_val <= out_cmd_val;
--Wormhole 'cmd_in' of type 'cmd_in':
in_cmd <= cmd_in_cmdin;
in_cmd_val <= cmd_in_cmdin_val;
--Wormhole 'ext_fc6301_host_if' of type 'ext_fc6301_host_if':
ifpga_rst_out_ifpga_rst <= not sys_reset_n;
--Wormhole 'in_data' of type 'wh_in':
in_data_in_stop <= read_data_stop;
read_data_val <= in_data_in_dval;
read_data <= in_data_in_data;
--Wormhole 'out_data' of type 'wh_out':
out_data_out_dval <= write_data_val;
out_data_out_data <= write_data;
--------------------------------------------------------------------------------
-- End
--------------------------------------------------------------------------------
end architecture behavioral;
|
--------------------------------------------------------------------------------
-- file name : sip_vp680_host_if.vhd
--
-- author : P. Kortekaas
--
-- company : 4dsp
--
-- item : number
--
-- language : vhdl
--
--------------------------------------------------------------------------------
-- description
-- ===========
--
--
-- notes:
--------------------------------------------------------------------------------
--
-- disclaimer: limited warranty and disclaimer. these designs are
-- provided to you as is. 4dsp specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4dsp does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the designs
-- will be corrected. furthermore, 4dsp does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- limitation of liability. in no event will 4dsp or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. this limitation will apply even if 4dsp
-- has been advised of the possibility of such damage. this
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
----------------------------------------------
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Specify libraries
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
library std;
use std.textio.all;
library work;
use work.txt_util.all;
use work.std_logic_textio.all;
--------------------------------------------------------------------------------
-- Entity declaration
--------------------------------------------------------------------------------
entity generic_host_emu is
generic (
global_start_addr_gen : std_logic_vector(27 downto 0);
global_stop_addr_gen : std_logic_vector(27 downto 0);
private_start_addr_gen : std_logic_vector(27 downto 0);
private_stop_addr_gen : std_logic_vector(27 downto 0)
);
port (
--Wormhole 'cmdclk_out' of type 'cmdclk_out':
cmdclk_out_cmdclk : out std_logic;
--Wormhole 'cmd_in' of type 'cmd_in':
cmd_in_cmdin : in std_logic_vector(63 downto 0);
cmd_in_cmdin_val : in std_logic;
--Wormhole 'cmd_out' of type 'cmd_out':
cmd_out_cmdout : out std_logic_vector(63 downto 0);
cmd_out_cmdout_val : out std_logic;
--Wormhole 'ifpga_rst_out' of type 'ifpga_rst_out':
ifpga_rst_out_ifpga_rst : out std_logic;
--Wormhole 'clk' of type 'clkin':
clk_clkin : in std_logic_vector(31 downto 0);
--Wormhole 'rst' of type 'rst_in':
rst_rstin : in std_logic_vector(31 downto 0);
--Wormhole 'ext_vp680_host_if' of type 'ext_vp680_host_if':
sys_clk : in std_logic;
sys_reset_n : in std_logic;
--Wormhole 'in_data' of type 'wh_in':
in_data_in_stop : out std_logic;
in_data_in_dval : in std_logic;
in_data_in_data : in std_logic_vector(63 downto 0);
--Wormhole 'out_data' of type 'wh_out':
out_data_out_stop : in std_logic;
out_data_out_dval : out std_logic;
out_data_out_data : out std_logic_vector(63 downto 0)
);
end entity generic_host_emu;
--------------------------------------------------------------------------------
-- Architecture declaration
--------------------------------------------------------------------------------
architecture behavioral of generic_host_emu is
--------------------------------------------------------------------------------
-- Constant declarations
--------------------------------------------------------------------------------
type std2d_32b is array(natural range <>) of std_logic_vector(31 downto 0);
-----------------------------------------------------------------------------------
-- Signal declarations
-----------------------------------------------------------------------------------
signal clk_cmd : std_logic := '0';
signal clk125m : std_logic := '0';
signal out_cmd_val : std_logic := '0';
signal out_cmd : std_logic_vector(63 downto 0) := (others => '0');
signal in_cmd_val : std_logic;
signal in_cmd : std_logic_vector(63 downto 0);
signal write_data_val : std_logic := '0';
signal write_data : std_logic_vector(63 downto 0) := (others => '0');
signal read_data_stop : std_logic := '1';
signal read_data_val : std_logic;
signal read_data : std_logic_vector(63 downto 0);
-----------------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------
-- Clock generation
--------------------------------------------------------------------------------
clk_cmd <= sys_clk;
clk125m <= sys_clk;
--------------------------------------------------------------------------------
-- Perform SIP register read and writes
--------------------------------------------------------------------------------
process
file CMD_SCRIPT : text;
file INPUT_FILE : text;
variable BAR_array :std2d_32b(15 downto 0);
variable BAR_idx :integer range 16 downto 0 :=0;
variable textline : line;
variable sip_command : string(1 to 80);
variable char1 : string(1 to 1);
variable WaitDelay : integer := 0;
variable sip_addr : std_logic_vector(31 downto 0);
variable sip_bar_idx : std_logic_vector(3 downto 0);
variable sip_data : std_logic_vector(31 downto 0);
variable dmapush_size : std_logic_vector(31 downto 0);
variable dmapull_size : std_logic_vector(31 downto 0);
-- Procedure for writing a register
procedure cmd_write(addr : in std_logic_vector(31 downto 0); data : in std_logic_vector(31 downto 0)) is
begin
wait until clk_cmd = '0';
out_cmd_val <= '1';
out_cmd <= x"1" & addr(27 downto 0) & data;
wait until clk_cmd = '1';
wait until clk_cmd = '0';
out_cmd_val <= '0';
REPORT "CMD Write: ADDR 0x" & hstr(addr) & " DATA " & str(conv_integer(data));
end procedure cmd_write;
-- Procedure for reading a register
procedure cmd_read(addr : in std_logic_vector(31 downto 0); data : inout std_logic_vector(31 downto 0)) is
begin
wait until clk_cmd = '0';
out_cmd_val <= '1';
out_cmd <= x"2" & addr(27 downto 0) & conv_std_logic_vector(0, 32);
wait until clk_cmd = '1';
wait until clk_cmd = '0';
out_cmd_val <= '0';
wait until in_cmd_val = '1';
data := in_cmd(31 downto 0);
REPORT "CMD Read: ADDR 0x" & hstr(addr) & " DATA " & str(conv_integer(data));
end procedure cmd_read;
-- Procedure for pushing DMA to FPGA B
procedure dma_push(dma_size : in std_logic_vector(31 downto 0)) is
variable textline : line;
variable size : integer;
variable dma_data : std_logic_vector(63 downto 0);
begin
size := conv_integer(dma_size);
while (size > 0) loop
wait until clk125m = '0';
--if (in0_stop = '0') then
readline(INPUT_FILE, textline);
hread(textline, dma_data);
write_data_val <= '1';
write_data <= dma_data;
wait until clk125m = '1';
wait until clk125m = '0';
write_data_val <= '0';
size := size - 8;
--end if;
end loop;
REPORT "DMA Push, Size " & str(conv_integer(dma_size)) & " bytes";
end procedure dma_push;
-- Procedure for pulling DMA from FPGA B
procedure dma_pull(dma_size : in std_logic_vector(31 downto 0)) is
variable size : integer;
begin
-- This precedure only pulls down the stop signal for the right amount of time
-- data that comes available is written to file by the "Write data to file"
-- process elsewhere in this file.
size := conv_integer(dma_size);
-- Start reading fast, untill 8 words (64 bytes) left
while (size > 64) loop
wait until clk125m = '1';
read_data_stop <= '0';
if (read_data_val = '1') then
size := size - 8;
end if;
wait until clk125m = '0';
end loop;
-- Read the last words slowly
while (size > 0) loop
wait until clk125m = '1';
read_data_stop <= '0';
if (read_data_val = '1') then
size := size - 8;
end if;
wait until clk125m = '0';
wait until clk125m = '1';
read_data_stop <= '1';
if (read_data_val = '1') then
size := size - 8;
end if;
wait until clk125m = '0';
wait until clk125m = '1';
if (read_data_val = '1') then
size := size - 8;
end if;
wait until clk125m = '0';
end loop;
read_data_stop <= '1';
REPORT "DMA Pull, Size " & str(conv_integer(dma_size)) & " bytes";
end procedure dma_pull;
variable fstatus: file_open_status; -- declare file
variable sip_mode:std_logic:='0';
begin
--script should start with 16 BAR definitions
for i in 1 to 15 loop
BAR_array(i) := (others=>'0');
end loop;
BAR_idx :=0;
wait for 1 us;
--open advanced sip script which is not compatible with the software sip script parser
file_open(fstatus,CMD_SCRIPT, "sip_cmd.asip", read_mode);
if (fstatus=OPEN_OK) then
sip_mode :='1';
else
file_open(fstatus,CMD_SCRIPT, "sip_cmd.sip", read_mode);
sip_mode := '0';
end if;
file_open(INPUT_FILE, "input.txt", read_mode);
while not endfile(CMD_SCRIPT) loop
readline(CMD_SCRIPT, textline);
next when textline'length = 0; -- Skip empty lines
-- Reset command
for i in 1 to sip_command'length loop
sip_command(i to i) := " ";
end loop;
-- Read command
for i in 1 to sip_command'length loop
-- Exit when exeeding the number of characters on the line
exit when i > textline'length;
read(textline, sip_command(i to i));
-- Comment
if (sip_command(1 to 1) = ";") then
read(textline, sip_command(1 to textline'length));
REPORT(sip_command) SEVERITY warning;
exit;
end if;
if(sip_mode='1') then
--assign to next BAR
if (sip_command(1 to 7) = "BAR_ADR") then
-- Collect address
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, BAR_array(BAR_idx));
BAR_idx := BAR_idx + 1;
exit;
end if;
end if;
-- Write access
if (sip_command(1 to 7) = "REG_SET") then
-- Collect address
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, sip_addr);
-- Collect data
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, sip_data);
if(sip_mode='1') then
-- Collect BAR index
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, sip_bar_idx);
-- Write
cmd_write(sip_addr+BAR_array(conv_integer(sip_bar_idx)), sip_data);
else
cmd_write(sip_addr, sip_data);
end if;
exit;
end if;
-- Read access
if (sip_command(1 to 7) = "REG_GET") then
-- Collect address
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, sip_addr);
if(sip_mode='1') then
-- Collect BAR index
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, sip_bar_idx);
-- Read
cmd_read(sip_addr+BAR_array(conv_integer(sip_bar_idx)), sip_data);
else
cmd_read(sip_addr, sip_data);
end if;
exit;
end if;
-- DMA Push access (from host to card)
if (sip_command(1 to 7) = "DMAPUSH") then
-- Collect size
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, dmapush_size);
-- DMA to FPGA B
dma_push(dmapush_size);
exit;
end if;
-- DMA Pull access (from card to host)
if (sip_command(1 to 7) = "DMAPULL") then
-- Collect size
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, dmapull_size);
-- DMA from FPGA B
dma_pull(dmapull_size);
exit;
end if;
-- Wait
if (sip_command(1 to 4) = "WAIT") then
char1 := " ";
while (char1 /= "=") loop
read(textline, char1);
end loop;
read(textline, WaitDelay);
REPORT("Wait for " & str(WaitDelay) & " us");
for i in 1 to WaitDelay loop
wait for 1 us;
end loop;
exit;
end if;
end loop;
wait for 1 us;
end loop;
file_close(CMD_SCRIPT);
file_close(INPUT_FILE);
REPORT("Ready with reading SIP CMD script!");
wait for 10 us;
REPORT "Testbench ended" severity warning;
wait;
end process;
--------------------------------------------------------------------------------
-- Write data to file
--------------------------------------------------------------------------------
process
file OUTPUT_FILE : text;
variable textline : line;
begin
file_open(OUTPUT_FILE, "output.txt", write_mode);
file_close(OUTPUT_FILE);
while true loop
wait until clk125m = '1';
if (read_data_val = '1') then
file_open(OUTPUT_FILE, "output.txt", append_mode);
hwrite(textline, read_data);
writeline(OUTPUT_FILE, textline);
file_close(OUTPUT_FILE);
end if;
wait until clk125m = '0';
end loop;
wait;
end process;
--------------------------------------------------------------------------------
-- Connect entity
--------------------------------------------------------------------------------
--Wormhole 'cmdclk_out' of type 'cmdclk_out':
cmdclk_out_cmdclk <= clk_cmd;
--Wormhole 'cmd_out' of type 'cmd_out':
cmd_out_cmdout <= out_cmd;
cmd_out_cmdout_val <= out_cmd_val;
--Wormhole 'cmd_in' of type 'cmd_in':
in_cmd <= cmd_in_cmdin;
in_cmd_val <= cmd_in_cmdin_val;
--Wormhole 'ext_fc6301_host_if' of type 'ext_fc6301_host_if':
ifpga_rst_out_ifpga_rst <= not sys_reset_n;
--Wormhole 'in_data' of type 'wh_in':
in_data_in_stop <= read_data_stop;
read_data_val <= in_data_in_dval;
read_data <= in_data_in_data;
--Wormhole 'out_data' of type 'wh_out':
out_data_out_dval <= write_data_val;
out_data_out_data <= write_data;
--------------------------------------------------------------------------------
-- End
--------------------------------------------------------------------------------
end architecture behavioral;
|
--------------------------------------------------------------------------------
-- file name : sip_vp680_host_if.vhd
--
-- author : P. Kortekaas
--
-- company : 4dsp
--
-- item : number
--
-- language : vhdl
--
--------------------------------------------------------------------------------
-- description
-- ===========
--
--
-- notes:
--------------------------------------------------------------------------------
--
-- disclaimer: limited warranty and disclaimer. these designs are
-- provided to you as is. 4dsp specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4dsp does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the designs
-- will be corrected. furthermore, 4dsp does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- limitation of liability. in no event will 4dsp or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. this limitation will apply even if 4dsp
-- has been advised of the possibility of such damage. this
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
----------------------------------------------
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Specify libraries
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
library std;
use std.textio.all;
library work;
use work.txt_util.all;
use work.std_logic_textio.all;
--------------------------------------------------------------------------------
-- Entity declaration
--------------------------------------------------------------------------------
entity generic_host_emu is
generic (
global_start_addr_gen : std_logic_vector(27 downto 0);
global_stop_addr_gen : std_logic_vector(27 downto 0);
private_start_addr_gen : std_logic_vector(27 downto 0);
private_stop_addr_gen : std_logic_vector(27 downto 0)
);
port (
--Wormhole 'cmdclk_out' of type 'cmdclk_out':
cmdclk_out_cmdclk : out std_logic;
--Wormhole 'cmd_in' of type 'cmd_in':
cmd_in_cmdin : in std_logic_vector(63 downto 0);
cmd_in_cmdin_val : in std_logic;
--Wormhole 'cmd_out' of type 'cmd_out':
cmd_out_cmdout : out std_logic_vector(63 downto 0);
cmd_out_cmdout_val : out std_logic;
--Wormhole 'ifpga_rst_out' of type 'ifpga_rst_out':
ifpga_rst_out_ifpga_rst : out std_logic;
--Wormhole 'clk' of type 'clkin':
clk_clkin : in std_logic_vector(31 downto 0);
--Wormhole 'rst' of type 'rst_in':
rst_rstin : in std_logic_vector(31 downto 0);
--Wormhole 'ext_vp680_host_if' of type 'ext_vp680_host_if':
sys_clk : in std_logic;
sys_reset_n : in std_logic;
--Wormhole 'in_data' of type 'wh_in':
in_data_in_stop : out std_logic;
in_data_in_dval : in std_logic;
in_data_in_data : in std_logic_vector(63 downto 0);
--Wormhole 'out_data' of type 'wh_out':
out_data_out_stop : in std_logic;
out_data_out_dval : out std_logic;
out_data_out_data : out std_logic_vector(63 downto 0)
);
end entity generic_host_emu;
--------------------------------------------------------------------------------
-- Architecture declaration
--------------------------------------------------------------------------------
architecture behavioral of generic_host_emu is
--------------------------------------------------------------------------------
-- Constant declarations
--------------------------------------------------------------------------------
type std2d_32b is array(natural range <>) of std_logic_vector(31 downto 0);
-----------------------------------------------------------------------------------
-- Signal declarations
-----------------------------------------------------------------------------------
signal clk_cmd : std_logic := '0';
signal clk125m : std_logic := '0';
signal out_cmd_val : std_logic := '0';
signal out_cmd : std_logic_vector(63 downto 0) := (others => '0');
signal in_cmd_val : std_logic;
signal in_cmd : std_logic_vector(63 downto 0);
signal write_data_val : std_logic := '0';
signal write_data : std_logic_vector(63 downto 0) := (others => '0');
signal read_data_stop : std_logic := '1';
signal read_data_val : std_logic;
signal read_data : std_logic_vector(63 downto 0);
-----------------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------------
begin
--------------------------------------------------------------------------------
-- Clock generation
--------------------------------------------------------------------------------
clk_cmd <= sys_clk;
clk125m <= sys_clk;
--------------------------------------------------------------------------------
-- Perform SIP register read and writes
--------------------------------------------------------------------------------
process
file CMD_SCRIPT : text;
file INPUT_FILE : text;
variable BAR_array :std2d_32b(15 downto 0);
variable BAR_idx :integer range 16 downto 0 :=0;
variable textline : line;
variable sip_command : string(1 to 80);
variable char1 : string(1 to 1);
variable WaitDelay : integer := 0;
variable sip_addr : std_logic_vector(31 downto 0);
variable sip_bar_idx : std_logic_vector(3 downto 0);
variable sip_data : std_logic_vector(31 downto 0);
variable dmapush_size : std_logic_vector(31 downto 0);
variable dmapull_size : std_logic_vector(31 downto 0);
-- Procedure for writing a register
procedure cmd_write(addr : in std_logic_vector(31 downto 0); data : in std_logic_vector(31 downto 0)) is
begin
wait until clk_cmd = '0';
out_cmd_val <= '1';
out_cmd <= x"1" & addr(27 downto 0) & data;
wait until clk_cmd = '1';
wait until clk_cmd = '0';
out_cmd_val <= '0';
REPORT "CMD Write: ADDR 0x" & hstr(addr) & " DATA " & str(conv_integer(data));
end procedure cmd_write;
-- Procedure for reading a register
procedure cmd_read(addr : in std_logic_vector(31 downto 0); data : inout std_logic_vector(31 downto 0)) is
begin
wait until clk_cmd = '0';
out_cmd_val <= '1';
out_cmd <= x"2" & addr(27 downto 0) & conv_std_logic_vector(0, 32);
wait until clk_cmd = '1';
wait until clk_cmd = '0';
out_cmd_val <= '0';
wait until in_cmd_val = '1';
data := in_cmd(31 downto 0);
REPORT "CMD Read: ADDR 0x" & hstr(addr) & " DATA " & str(conv_integer(data));
end procedure cmd_read;
-- Procedure for pushing DMA to FPGA B
procedure dma_push(dma_size : in std_logic_vector(31 downto 0)) is
variable textline : line;
variable size : integer;
variable dma_data : std_logic_vector(63 downto 0);
begin
size := conv_integer(dma_size);
while (size > 0) loop
wait until clk125m = '0';
--if (in0_stop = '0') then
readline(INPUT_FILE, textline);
hread(textline, dma_data);
write_data_val <= '1';
write_data <= dma_data;
wait until clk125m = '1';
wait until clk125m = '0';
write_data_val <= '0';
size := size - 8;
--end if;
end loop;
REPORT "DMA Push, Size " & str(conv_integer(dma_size)) & " bytes";
end procedure dma_push;
-- Procedure for pulling DMA from FPGA B
procedure dma_pull(dma_size : in std_logic_vector(31 downto 0)) is
variable size : integer;
begin
-- This precedure only pulls down the stop signal for the right amount of time
-- data that comes available is written to file by the "Write data to file"
-- process elsewhere in this file.
size := conv_integer(dma_size);
-- Start reading fast, untill 8 words (64 bytes) left
while (size > 64) loop
wait until clk125m = '1';
read_data_stop <= '0';
if (read_data_val = '1') then
size := size - 8;
end if;
wait until clk125m = '0';
end loop;
-- Read the last words slowly
while (size > 0) loop
wait until clk125m = '1';
read_data_stop <= '0';
if (read_data_val = '1') then
size := size - 8;
end if;
wait until clk125m = '0';
wait until clk125m = '1';
read_data_stop <= '1';
if (read_data_val = '1') then
size := size - 8;
end if;
wait until clk125m = '0';
wait until clk125m = '1';
if (read_data_val = '1') then
size := size - 8;
end if;
wait until clk125m = '0';
end loop;
read_data_stop <= '1';
REPORT "DMA Pull, Size " & str(conv_integer(dma_size)) & " bytes";
end procedure dma_pull;
variable fstatus: file_open_status; -- declare file
variable sip_mode:std_logic:='0';
begin
--script should start with 16 BAR definitions
for i in 1 to 15 loop
BAR_array(i) := (others=>'0');
end loop;
BAR_idx :=0;
wait for 1 us;
--open advanced sip script which is not compatible with the software sip script parser
file_open(fstatus,CMD_SCRIPT, "sip_cmd.asip", read_mode);
if (fstatus=OPEN_OK) then
sip_mode :='1';
else
file_open(fstatus,CMD_SCRIPT, "sip_cmd.sip", read_mode);
sip_mode := '0';
end if;
file_open(INPUT_FILE, "input.txt", read_mode);
while not endfile(CMD_SCRIPT) loop
readline(CMD_SCRIPT, textline);
next when textline'length = 0; -- Skip empty lines
-- Reset command
for i in 1 to sip_command'length loop
sip_command(i to i) := " ";
end loop;
-- Read command
for i in 1 to sip_command'length loop
-- Exit when exeeding the number of characters on the line
exit when i > textline'length;
read(textline, sip_command(i to i));
-- Comment
if (sip_command(1 to 1) = ";") then
read(textline, sip_command(1 to textline'length));
REPORT(sip_command) SEVERITY warning;
exit;
end if;
if(sip_mode='1') then
--assign to next BAR
if (sip_command(1 to 7) = "BAR_ADR") then
-- Collect address
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, BAR_array(BAR_idx));
BAR_idx := BAR_idx + 1;
exit;
end if;
end if;
-- Write access
if (sip_command(1 to 7) = "REG_SET") then
-- Collect address
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, sip_addr);
-- Collect data
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, sip_data);
if(sip_mode='1') then
-- Collect BAR index
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, sip_bar_idx);
-- Write
cmd_write(sip_addr+BAR_array(conv_integer(sip_bar_idx)), sip_data);
else
cmd_write(sip_addr, sip_data);
end if;
exit;
end if;
-- Read access
if (sip_command(1 to 7) = "REG_GET") then
-- Collect address
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, sip_addr);
if(sip_mode='1') then
-- Collect BAR index
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, sip_bar_idx);
-- Read
cmd_read(sip_addr+BAR_array(conv_integer(sip_bar_idx)), sip_data);
else
cmd_read(sip_addr, sip_data);
end if;
exit;
end if;
-- DMA Push access (from host to card)
if (sip_command(1 to 7) = "DMAPUSH") then
-- Collect size
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, dmapush_size);
-- DMA to FPGA B
dma_push(dmapush_size);
exit;
end if;
-- DMA Pull access (from card to host)
if (sip_command(1 to 7) = "DMAPULL") then
-- Collect size
char1 := " ";
while (char1 /= "x") loop
read(textline, char1);
end loop;
hread(textline, dmapull_size);
-- DMA from FPGA B
dma_pull(dmapull_size);
exit;
end if;
-- Wait
if (sip_command(1 to 4) = "WAIT") then
char1 := " ";
while (char1 /= "=") loop
read(textline, char1);
end loop;
read(textline, WaitDelay);
REPORT("Wait for " & str(WaitDelay) & " us");
for i in 1 to WaitDelay loop
wait for 1 us;
end loop;
exit;
end if;
end loop;
wait for 1 us;
end loop;
file_close(CMD_SCRIPT);
file_close(INPUT_FILE);
REPORT("Ready with reading SIP CMD script!");
wait for 10 us;
REPORT "Testbench ended" severity warning;
wait;
end process;
--------------------------------------------------------------------------------
-- Write data to file
--------------------------------------------------------------------------------
process
file OUTPUT_FILE : text;
variable textline : line;
begin
file_open(OUTPUT_FILE, "output.txt", write_mode);
file_close(OUTPUT_FILE);
while true loop
wait until clk125m = '1';
if (read_data_val = '1') then
file_open(OUTPUT_FILE, "output.txt", append_mode);
hwrite(textline, read_data);
writeline(OUTPUT_FILE, textline);
file_close(OUTPUT_FILE);
end if;
wait until clk125m = '0';
end loop;
wait;
end process;
--------------------------------------------------------------------------------
-- Connect entity
--------------------------------------------------------------------------------
--Wormhole 'cmdclk_out' of type 'cmdclk_out':
cmdclk_out_cmdclk <= clk_cmd;
--Wormhole 'cmd_out' of type 'cmd_out':
cmd_out_cmdout <= out_cmd;
cmd_out_cmdout_val <= out_cmd_val;
--Wormhole 'cmd_in' of type 'cmd_in':
in_cmd <= cmd_in_cmdin;
in_cmd_val <= cmd_in_cmdin_val;
--Wormhole 'ext_fc6301_host_if' of type 'ext_fc6301_host_if':
ifpga_rst_out_ifpga_rst <= not sys_reset_n;
--Wormhole 'in_data' of type 'wh_in':
in_data_in_stop <= read_data_stop;
read_data_val <= in_data_in_dval;
read_data <= in_data_in_data;
--Wormhole 'out_data' of type 'wh_out':
out_data_out_dval <= write_data_val;
out_data_out_data <= write_data;
--------------------------------------------------------------------------------
-- End
--------------------------------------------------------------------------------
end architecture behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity reg_ctrl is
port ( reg_addr_decoded, rd, wr, io_en, cpu_clk : in std_ulogic;
reg_rd, reg_wr : out std_ulogic );
end entity reg_ctrl;
--------------------------------------------------
architecture bool_eqn of reg_ctrl is
begin
rd_ctrl : reg_rd <= reg_addr_decoded and rd and io_en;
rw_ctrl : reg_wr <= reg_addr_decoded and wr and io_en
and not cpu_clk;
end architecture bool_eqn;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity reg_ctrl is
port ( reg_addr_decoded, rd, wr, io_en, cpu_clk : in std_ulogic;
reg_rd, reg_wr : out std_ulogic );
end entity reg_ctrl;
--------------------------------------------------
architecture bool_eqn of reg_ctrl is
begin
rd_ctrl : reg_rd <= reg_addr_decoded and rd and io_en;
rw_ctrl : reg_wr <= reg_addr_decoded and wr and io_en
and not cpu_clk;
end architecture bool_eqn;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity reg_ctrl is
port ( reg_addr_decoded, rd, wr, io_en, cpu_clk : in std_ulogic;
reg_rd, reg_wr : out std_ulogic );
end entity reg_ctrl;
--------------------------------------------------
architecture bool_eqn of reg_ctrl is
begin
rd_ctrl : reg_rd <= reg_addr_decoded and rd and io_en;
rw_ctrl : reg_wr <= reg_addr_decoded and wr and io_en
and not cpu_clk;
end architecture bool_eqn;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Solving_Key_Equation_1_v2
-- Module Name: Solving_Key_Equation_1_v2
-- Project Name: McEliece QD-Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 2nd step in Goppa Code Decoding.
--
-- This circuit solves the polynomial key equation sigma with the polynomial syndrome.
-- To solve the key equation, this circuit employs a modified extended euclidean algorithm
-- The modification is made to stop the algorithm when polynomial, represented here as G, has
-- degree less or equal than the polynomial key equation sigma desired degree.
-- The syndrome is the input and expected to be of degree 2*final_degree, and after computations
-- polynomial C, will hold sigma with degree less or equal to final_degree.
--
-- This is the second circuit version. It is a non pipeline version of the algorithm,
-- each coefficient takes more than 1 cycle to be computed.
-- A more optimized version with a pipeline approach was made called solving_key_equation_2.
--
-- Parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- final_degree :
--
-- The final degree size expected for polynomial sigma to have. This parameter depends
-- of the Goppa code used.
--
-- size_final_degree :
--
-- The number of bits necessary to hold the polynomial with degree of final_degree, which
-- has final_degree + 1 coefficients. This is ceil(log2(final_degree+1)).
--
-- Dependencies:
--
-- VHDL-93
--
-- controller_solving_key_equation_1_v2 Rev 1.0
-- register_nbits Rev 1.0
-- register_rst_nbits Rev 1.0
-- counter_decrement_load_nbits Rev 1.0
-- counter_decrement_load_rst_nbits Rev 1.0
-- mult_gf_2_m Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity solving_key_equation_1_v2 is
Generic(
-- GOPPA [2048, 1751, 27, 11] --
gf_2_m : integer range 1 to 20 := 11;
final_degree : integer := 27;
size_final_degree : integer := 5
-- GOPPA [2048, 1498, 50, 11] --
-- gf_2_m : integer range 1 to 20 := 11;
-- final_degree : integer := 50;
-- size_final_degree : integer := 6
-- GOPPA [3307, 2515, 66, 12] --
-- gf_2_m : integer range 1 to 20 := 11;
-- final_degree : integer := 50;
-- size_final_degree : integer := 6
-- QD-GOPPA [2528, 2144, 32, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 32;
-- size_final_degree : integer := 5
-- QD-GOPPA [2816, 2048, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 64;
-- size_final_degree : integer := 6
-- QD-GOPPA [3328, 2560, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 64;
-- size_final_degree : integer := 6
-- QD-GOPPA [7296, 5632, 128, 13] --
-- gf_2_m : integer range 1 to 20 := 13;
-- final_degree : integer := 128;
-- size_final_degree : integer := 7
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ready_inv : in STD_LOGIC;
value_FB : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_GC : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_inv : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal_inv : out STD_LOGIC;
key_equation_found : out STD_LOGIC;
write_enable_FB : out STD_LOGIC;
write_enable_GC : out STD_LOGIC;
new_value_inv : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_FB : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_GC : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_FB : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_GC : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0)
);
end solving_key_equation_1_v2;
architecture Behavioral of solving_key_equation_1_v2 is
component controller_solving_key_equation_1_v2
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
FB_equal_zero : in STD_LOGIC;
i_equal_zero : in STD_LOGIC;
i_minus_j_less_than_zero : in STD_LOGIC;
degree_G_less_equal_final_degree : in STD_LOGIC;
degree_F_less_than_degree_G : in STD_LOGIC;
degree_B_equal_degree_C_plus_j : in STD_LOGIC;
degree_B_less_than_degree_C_plus_j : in STD_LOGIC;
reg_looking_degree_q : in STD_LOGIC_VECTOR(0 downto 0);
key_equation_found : out STD_LOGIC;
signal_inv : out STD_LOGIC;
sel_new_value_inv : out STD_LOGIC;
write_enable_FB : out STD_LOGIC;
write_enable_GC : out STD_LOGIC;
sel_base_mul : out STD_LOGIC;
reg_h_ce : out STD_LOGIC;
ctr_i_ce : out STD_LOGIC;
ctr_i_load : out STD_LOGIC;
ctr_i_rst : out STD_LOGIC;
sel_ctr_i_rst_value : out STD_LOGIC;
sel_ctr_i_d : out STD_LOGIC;
reg_j_ce : out STD_LOGIC;
reg_j_rst : out STD_LOGIC;
reg_FB_ce : out STD_LOGIC;
reg_FB_rst : out STD_LOGIC;
sel_reg_FB : out STD_LOGIC;
sel_load_new_value_FB : out STD_LOGIC;
reg_GC_ce : out STD_LOGIC;
reg_GC_rst : out STD_LOGIC;
sel_reg_GC : out STD_LOGIC;
ctr_degree_F_ce : out STD_LOGIC;
ctr_degree_F_load : out STD_LOGIC;
ctr_degree_F_rst : out STD_LOGIC;
reg_degree_G_ce : out STD_LOGIC;
reg_degree_G_rst : out STD_LOGIC;
ctr_degree_B_ce : out STD_LOGIC;
ctr_degree_B_load : out STD_LOGIC;
ctr_degree_B_rst : out STD_LOGIC;
sel_ctr_degree_B : out STD_LOGIC;
reg_degree_C_ce : out STD_LOGIC;
reg_degree_C_rst : out STD_LOGIC;
reg_looking_degree_d : out STD_LOGIC_VECTOR(0 downto 0);
reg_looking_degree_ce : out STD_LOGIC;
reg_swap_ce : out STD_LOGIC;
reg_swap_rst : out STD_LOGIC;
sel_address_FB : out STD_LOGIC;
sel_address_GC : out STD_LOGIC;
ctr_address_FB_ce : out STD_LOGIC;
ctr_address_FB_load : out STD_LOGIC;
ctr_address_GC_ce : out STD_LOGIC;
ctr_address_GC_load : out STD_LOGIC;
BC_calculation : out STD_LOGIC;
enable_external_swap : out STD_LOGIC
);
end component;
component register_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_decrement_load_rst_nbits
Generic (
size : integer;
decrement_value : integer
);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
load : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
component counter_decrement_load_nbits
Generic (
size : integer;
decrement_value : integer
);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
load : in STD_LOGIC;
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end component;
component mult_gf_2_m
Generic (gf_2_m : integer range 1 to 20 := 11);
Port (
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal base_mult_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal base_mult_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal base_mult_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_base_mul : STD_LOGIC;
signal reg_h_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_h_ce : STD_LOGIC;
signal reg_h_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_inv_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_inv_ce : STD_LOGIC;
signal reg_inv_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal ctr_i_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_i_ce : STD_LOGIC;
signal ctr_i_load : STD_LOGIC;
signal ctr_i_rst : STD_LOGIC;
signal ctr_i_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_i_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal sel_ctr_i_d : STD_LOGIC;
signal sel_ctr_i_rst_value : STD_LOGIC;
constant ctr_i_rst_value_F : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(2*final_degree - 1,size_final_degree + 2));
constant ctr_i_rst_value_B : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(final_degree,size_final_degree + 2));
signal reg_j_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_j_ce : STD_LOGIC;
signal reg_j_rst : STD_LOGIC;
signal reg_j_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(0,size_final_degree + 2));
signal reg_j_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_FB_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_FB_ce : STD_LOGIC;
signal reg_FB_rst : STD_LOGIC;
constant reg_FB_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others=> '0');
signal reg_FB_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_reg_FB : STD_LOGIC;
signal reg_GC_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_GC_ce : STD_LOGIC;
signal reg_GC_rst : STD_LOGIC;
constant reg_GC_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others=> '0');
signal reg_GC_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_reg_GC : STD_LOGIC;
signal ctr_degree_F_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_degree_F_ce : STD_LOGIC;
signal ctr_degree_F_load : STD_LOGIC;
signal ctr_degree_F_rst : STD_LOGIC;
constant ctr_degree_F_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(2*final_degree - 1,size_final_degree + 2));
signal ctr_degree_F_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_degree_G_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_degree_G_ce : STD_LOGIC;
signal reg_degree_G_rst : STD_LOGIC;
constant reg_degree_G_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(2*final_degree,size_final_degree + 2));
signal reg_degree_G_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_degree_B_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_degree_B_ce : STD_LOGIC;
signal ctr_degree_B_load : STD_LOGIC;
signal ctr_degree_B_rst : STD_LOGIC;
constant ctr_degree_B_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(0,size_final_degree + 2));
signal ctr_degree_B_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal sel_ctr_degree_B : STD_LOGIC;
signal reg_degree_C_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_degree_C_ce : STD_LOGIC;
signal reg_degree_C_rst : STD_LOGIC;
constant reg_degree_C_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(0,size_final_degree + 2));
signal reg_degree_C_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_looking_degree_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_looking_degree_ce : STD_LOGIC;
signal reg_looking_degree_q : STD_LOGIC_VECTOR(0 downto 0);
signal reg_swap_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_swap_ce : STD_LOGIC;
signal reg_swap_rst : STD_LOGIC;
constant reg_swap_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal reg_swap_q : STD_LOGIC_VECTOR(0 downto 0);
signal i_minus_j : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal degree_C_plus_j : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal int_value_FB : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal int_value_GC : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_load_new_value_FB : STD_LOGIC;
signal int_new_value_FB : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal int_new_value_GC : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal int_write_enable_FB : STD_LOGIC;
signal int_write_enable_GC : STD_LOGIC;
signal address_i_FB : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_degree_F : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_degree_G : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_i_minus_j_GC : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal sel_address_FB : STD_LOGIC;
signal sel_address_GC : STD_LOGIC;
signal ctr_address_FB_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_address_FB_ce : STD_LOGIC;
signal ctr_address_FB_load : STD_LOGIC;
signal ctr_address_FB_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_address_GC_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_address_GC_ce : STD_LOGIC;
signal ctr_address_GC_load : STD_LOGIC;
signal ctr_address_GC_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal BC_calculation : STD_LOGIC;
signal enable_external_swap : STD_LOGIC;
signal sel_new_value_inv : STD_LOGIC;
signal FB_equal_zero : STD_LOGIC;
signal i_equal_zero : STD_LOGIC;
signal i_minus_j_less_than_zero : STD_LOGIC;
signal degree_G_less_equal_final_degree : STD_LOGIC;
signal degree_F_less_than_degree_G : STD_LOGIC;
signal degree_B_equal_degree_C_plus_j : STD_LOGIC;
signal degree_B_less_than_degree_C_plus_j : STD_LOGIC;
begin
controller : controller_solving_key_equation_1_v2
Port Map(
clk => clk,
rst => rst,
FB_equal_zero => FB_equal_zero,
i_equal_zero => i_equal_zero,
i_minus_j_less_than_zero => i_minus_j_less_than_zero,
degree_G_less_equal_final_degree => degree_G_less_equal_final_degree,
degree_F_less_than_degree_G => degree_F_less_than_degree_G,
degree_B_equal_degree_C_plus_j => degree_B_equal_degree_C_plus_j,
degree_B_less_than_degree_C_plus_j => degree_B_less_than_degree_C_plus_j,
reg_looking_degree_q => reg_looking_degree_q,
key_equation_found => key_equation_found,
signal_inv => signal_inv,
sel_new_value_inv => sel_new_value_inv,
write_enable_FB => int_write_enable_FB,
write_enable_GC => int_write_enable_GC,
sel_base_mul => sel_base_mul,
reg_h_ce => reg_h_ce,
ctr_i_ce => ctr_i_ce,
ctr_i_load => ctr_i_load,
ctr_i_rst => ctr_i_rst,
sel_ctr_i_rst_value => sel_ctr_i_rst_value,
sel_ctr_i_d => sel_ctr_i_d,
reg_j_ce => reg_j_ce,
reg_j_rst => reg_j_rst,
reg_FB_ce => reg_FB_ce,
reg_FB_rst => reg_FB_rst,
sel_reg_FB => sel_reg_FB,
sel_load_new_value_FB => sel_load_new_value_FB,
reg_GC_ce => reg_GC_ce,
reg_GC_rst => reg_GC_rst,
sel_reg_GC => sel_reg_GC,
ctr_degree_F_ce => ctr_degree_F_ce,
ctr_degree_F_load => ctr_degree_F_load,
ctr_degree_F_rst => ctr_degree_F_rst,
reg_degree_G_ce => reg_degree_G_ce,
reg_degree_G_rst => reg_degree_G_rst,
ctr_degree_B_ce => ctr_degree_B_ce,
ctr_degree_B_load => ctr_degree_B_load,
ctr_degree_B_rst => ctr_degree_B_rst,
sel_ctr_degree_B => sel_ctr_degree_B,
reg_degree_C_ce => reg_degree_C_ce,
reg_degree_C_rst => reg_degree_C_rst,
reg_looking_degree_d => reg_looking_degree_d,
reg_looking_degree_ce => reg_looking_degree_ce,
reg_swap_ce => reg_swap_ce,
reg_swap_rst => reg_swap_rst,
sel_address_FB => sel_address_FB,
sel_address_GC => sel_address_GC,
ctr_address_FB_ce => ctr_address_FB_ce,
ctr_address_FB_load => ctr_address_FB_load,
ctr_address_GC_ce => ctr_address_GC_ce,
ctr_address_GC_load => ctr_address_GC_load,
BC_calculation => BC_calculation,
enable_external_swap => enable_external_swap
);
base_mult : mult_gf_2_m
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => base_mult_a,
b => base_mult_b,
o => base_mult_o
);
reg_h : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_h_d,
clk => clk,
ce => reg_h_ce,
q => reg_h_q
);
reg_inv : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_inv_d,
clk => clk,
ce => reg_inv_ce,
q => reg_inv_q
);
ctr_i : counter_decrement_load_rst_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_i_d,
clk => clk,
ce => ctr_i_ce,
load => ctr_i_load,
rst => ctr_i_rst,
rst_value => ctr_i_rst_value,
q => ctr_i_q
);
reg_j : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_j_d,
clk => clk,
ce => reg_j_ce,
rst => reg_j_rst,
rst_value => reg_j_rst_value,
q => reg_j_q
);
reg_FB : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_FB_d,
clk => clk,
rst => reg_FB_rst,
rst_value => reg_FB_rst_value,
ce => reg_FB_ce,
q => reg_FB_q
);
reg_GC : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_GC_d,
clk => clk,
rst => reg_GC_rst,
rst_value => reg_GC_rst_value,
ce => reg_GC_ce,
q => reg_GC_q
);
ctr_degree_F : counter_decrement_load_rst_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_degree_F_d,
clk => clk,
ce => ctr_degree_F_ce,
load => ctr_degree_F_load,
rst => ctr_degree_F_rst,
rst_value => ctr_degree_F_rst_value,
q => ctr_degree_F_q
);
reg_degree_G : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_degree_G_d,
clk => clk,
rst => reg_degree_G_rst,
rst_value => reg_degree_G_rst_value,
ce => reg_degree_G_ce,
q => reg_degree_G_q
);
ctr_degree_B : counter_decrement_load_rst_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_degree_B_d,
clk => clk,
ce => ctr_degree_B_ce,
load => ctr_degree_B_load,
rst => ctr_degree_B_rst,
rst_value => ctr_degree_B_rst_value,
q => ctr_degree_B_q
);
reg_degree_C : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_degree_C_d,
clk => clk,
rst => reg_degree_C_rst,
rst_value => reg_degree_C_rst_value,
ce => reg_degree_C_ce,
q => reg_degree_C_q
);
ctr_address_FB : counter_decrement_load_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_address_FB_d,
clk => clk,
ce => ctr_address_FB_ce,
load => ctr_address_FB_load,
q => ctr_address_FB_q
);
ctr_address_GC : counter_decrement_load_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
d => ctr_address_GC_d,
clk => clk,
ce => ctr_address_GC_ce,
load => ctr_address_GC_load,
q => ctr_address_GC_q
);
reg_looking_degree : register_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_looking_degree_d,
clk => clk,
ce => reg_looking_degree_ce,
q => reg_looking_degree_q
);
reg_swap : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_swap_d,
clk => clk,
ce => reg_swap_ce,
rst => reg_swap_rst,
rst_value => reg_swap_rst_value,
q => reg_swap_q
);
base_mult_a <= reg_inv_q when sel_base_mul = '1' else
reg_h_q;
base_mult_b <= reg_FB_q when sel_base_mul = '1' else
reg_GC_q;
reg_h_d <= base_mult_o;
reg_inv_d <= value_inv;
reg_inv_ce <= ready_inv;
ctr_i_d <= ctr_degree_F_q when sel_ctr_i_d = '1' else
degree_C_plus_j;
ctr_i_rst_value <= ctr_i_rst_value_F when sel_ctr_i_rst_value = '1' else
ctr_i_rst_value_B;
reg_j_d <= std_logic_vector(unsigned(ctr_degree_F_q) - unsigned(reg_degree_G_q));
reg_FB_d <= (base_mult_o xor reg_FB_q) when sel_load_new_value_FB = '1' else
std_logic_vector(to_unsigned(1, reg_FB_d'length)) when sel_reg_FB = '1' else
int_value_FB;
reg_GC_d <= std_logic_vector(to_unsigned(1, reg_GC_d'length)) when sel_reg_GC = '1' else
int_value_GC;
ctr_degree_F_d <= reg_degree_G_q;
reg_degree_G_d <= ctr_degree_F_q;
ctr_degree_B_d <= degree_C_plus_j when sel_ctr_degree_B = '1' else
reg_degree_C_q;
degree_C_plus_j <= std_logic_vector(unsigned(reg_degree_C_q) + unsigned(reg_j_q));
i_minus_j <= std_logic_vector(unsigned(ctr_i_q) - unsigned(reg_j_q));
reg_degree_C_d <= ctr_degree_B_q;
reg_swap_d <= not reg_swap_q;
int_new_value_FB <= reg_FB_q;
int_new_value_GC <= reg_GC_q;
int_value_FB <= value_GC when reg_swap_q = "1" else value_FB;
int_value_GC <= value_FB when reg_swap_q = "1" else value_GC;
new_value_inv <= int_new_value_FB when sel_new_value_inv = '1' else
int_new_value_GC;
new_value_FB <= int_new_value_GC when (reg_swap_q(0) and enable_external_swap) = '1' else int_new_value_FB;
new_value_GC <= int_new_value_FB when (reg_swap_q(0) and enable_external_swap) = '1' else int_new_value_GC;
write_enable_FB <= int_write_enable_GC when (reg_swap_q(0) and enable_external_swap) = '1' else int_write_enable_FB;
write_enable_GC <= int_write_enable_FB when (reg_swap_q(0) and enable_external_swap) = '1' else int_write_enable_GC;
address_i_FB <= std_logic_vector(to_unsigned(2*final_degree + 1, address_i_FB'length) + unsigned(ctr_i_q)) when BC_calculation = '1' else
ctr_i_q;
address_degree_F <= ctr_degree_F_q;
address_degree_G <= reg_degree_G_q;
address_i_minus_j_GC <= std_logic_vector(to_unsigned(2*final_degree + 1, address_i_minus_j_GC'length) + unsigned(i_minus_j)) when BC_calculation = '1' else
i_minus_j;
ctr_address_FB_d <= address_degree_F when sel_address_FB = '1' else
address_i_FB;
ctr_address_GC_d <= address_degree_G when sel_address_GC = '1' else
address_i_minus_j_GC;
address_FB <= ctr_address_GC_q when (reg_swap_q(0) and enable_external_swap) = '1' else ctr_address_FB_q;
address_GC <= ctr_address_FB_q when (reg_swap_q(0) and enable_external_swap) = '1' else ctr_address_GC_q;
FB_equal_zero <= '1' when (int_new_value_FB = std_logic_vector(to_unsigned(0,reg_FB_q'length))) else '0';
i_equal_zero <= '1' when (ctr_i_q = std_logic_vector(to_unsigned(0,ctr_i_q'length))) else '0';
i_minus_j_less_than_zero <= '1' when (signed(i_minus_j) < to_signed(0,i_minus_j'length)) else '0';
degree_G_less_equal_final_degree <= '1' when (unsigned(reg_degree_G_q) <= to_unsigned(final_degree-1,reg_degree_G_q'length)) else '0';
degree_F_less_than_degree_G <= '1' when (unsigned(ctr_degree_F_q) < unsigned(reg_degree_G_q)) else '0';
degree_B_equal_degree_C_plus_j <= '1' when (ctr_degree_B_q = degree_C_plus_j) else '0';
degree_B_less_than_degree_C_plus_j <= '1' when (unsigned(ctr_degree_B_q) < unsigned(degree_C_plus_j)) else '0';
end Behavioral;
|
-- -------------------------------------------------------------------
-- Design:
--
-- Package for VHDL text output
--
-- Note:
-- -----
-- This package uses the VHDL 95 standard.
-- If VHDL 95 is not supported by your simulator
-- you need to comment out the file access functions.
--
-- The package provides a means to output text and
-- manipulate strings.
--
-- The basic usage is like this: >> print(s); <<
-- (where s is any string)
-- To print something which is not a string it has to be converted
-- into a string first. For this purpose the package contains
-- conversion functions called >> str(...) <<.
-- For example a std_logic_vector slv would be printed like this:
-- >> print(str(slv)); <<. To print several items on one line the
-- items have to concatenated as strings with the "&" operator eg:
-- >> print("The value of slv is "& str(slv)); <<
-- The string functions can also be used in assert statements as shown
-- in the example below:
-- >> assert DIN = "0101" <<
-- >> report "DIN = "& str(DIN)& " expected 0101 " <<
-- >> severity Error; <<
--
--
--
-- -------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
end txt_util;
|
-- -------------------------------------------------------------------
-- Design:
--
-- Package for VHDL text output
--
-- Note:
-- -----
-- This package uses the VHDL 95 standard.
-- If VHDL 95 is not supported by your simulator
-- you need to comment out the file access functions.
--
-- The package provides a means to output text and
-- manipulate strings.
--
-- The basic usage is like this: >> print(s); <<
-- (where s is any string)
-- To print something which is not a string it has to be converted
-- into a string first. For this purpose the package contains
-- conversion functions called >> str(...) <<.
-- For example a std_logic_vector slv would be printed like this:
-- >> print(str(slv)); <<. To print several items on one line the
-- items have to concatenated as strings with the "&" operator eg:
-- >> print("The value of slv is "& str(slv)); <<
-- The string functions can also be used in assert statements as shown
-- in the example below:
-- >> assert DIN = "0101" <<
-- >> report "DIN = "& str(DIN)& " expected 0101 " <<
-- >> severity Error; <<
--
--
--
-- -------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
end txt_util;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sum_gen is
generic (
N : integer := 32);
Port ( A: In std_logic_vector(N-1 downto 0);
B: In std_logic_vector(N-1 downto 0);
Cin: In std_logic_vector(N/4 downto 0);
S: Out std_logic_vector(N-1 downto 0)
);
end sum_gen;
architecture STRUCTURAL of sum_gen is
component carry_sel_gen
generic( N : integer := 4);
Port ( A: In std_logic_vector(N-1 downto 0);
B: In std_logic_vector(N-1 downto 0);
Ci: In std_logic;
S: Out std_logic_vector(N-1 downto 0);
Co: Out std_logic);
end component;
begin
csel_gen: for i in 0 to N/4-1 generate
csel_N: carry_sel_gen port map(A((i+1)*4-1 downto i*4),B((i+1)*4-1 downto i*4),Cin(i),S((i+1)*4-1 downto i*4),open);
end generate csel_gen;
end STRUCTURAL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sum_gen is
generic (
N : integer := 32);
Port ( A: In std_logic_vector(N-1 downto 0);
B: In std_logic_vector(N-1 downto 0);
Cin: In std_logic_vector(N/4 downto 0);
S: Out std_logic_vector(N-1 downto 0)
);
end sum_gen;
architecture STRUCTURAL of sum_gen is
component carry_sel_gen
generic( N : integer := 4);
Port ( A: In std_logic_vector(N-1 downto 0);
B: In std_logic_vector(N-1 downto 0);
Ci: In std_logic;
S: Out std_logic_vector(N-1 downto 0);
Co: Out std_logic);
end component;
begin
csel_gen: for i in 0 to N/4-1 generate
csel_N: carry_sel_gen port map(A((i+1)*4-1 downto i*4),B((i+1)*4-1 downto i*4),Cin(i),S((i+1)*4-1 downto i*4),open);
end generate csel_gen;
end STRUCTURAL;
|
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Elod Gyorgy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 14:55:31 04/07/2011
-- Design Name:
-- Module Name: TWIUtils - Package
-- Project Name: TWI Master Controller Reference Design
-- Target Devices:
-- Tool versions:
-- Description: This package provides enumeration types for TWI (Two-Wire
-- Interface) bus status and error conditions.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
package TWIUtils is
type busState_type is (busUnknown, busBusy, busFree);
type error_type is (errArb, errNAck);
end TWIUtils;
package body TWIUtils is
end TWIUtils;
----------------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Author: Elod Gyorgy
-- Copyright 2014 Digilent, Inc.
----------------------------------------------------------------------------
--
-- Create Date: 14:55:31 04/07/2011
-- Design Name:
-- Module Name: TWICtl - Behavioral
-- Project Name: TWI Master Controller Reference Design
-- Target Devices:
-- Tool versions:
-- Description: TWICtl is a reusabled Master Controller implementation of the
-- TWI protocol. It uses 7-bit addressing and was tested in STANDARD I2C mode.
-- FAST mode should also be theoretically possible, although it has not been
-- tested. It adheres to arbitration rules, thus supporting multi-master TWI
-- buses. Slave-wait is also supported.
--
--
-- Dependencies: digilent.TWIUtils package - TWICtl.vhd
--
-- Revision:
-- Revision 1.02 - Added bus unblock function
-- Revision 1.01 - Bugfix: stop condition might be prevented device read
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.math_real.all;
-- Use the package defined above
use work.TWIUtils.ALL;
entity TWICtl is
----------------------------------------------------------------------------------
-- Title : Mode of operation
-- Description: The controller can be instructed to initiate/continue/stop a
-- data transfer using the strobe (STB_I, MSG_I) signals. Data flow management is
-- provided by the done (DONE_O) and error (ERR_O, ERRTYPE_O) signals. Output
-- signals are synchronous to CLK and input signals must also be synchronous to
-- CLK. Signals are active-high.
-- Fast-track instructions (single byte transfer):
-- -put the TWI address on A_I
-- -if data is written put it on D_I
-- -assert STB_I
-- -when DONE_O pulse arrives, read data is present on D_O, if any
-- -repeat, or deassert STB_I
-- Detailed data transfer flow:
-- -when DONE_O is low, the controller is ready to accept commands
-- -data transfer can be initiated by putting a TWI slave address on the A_I
-- bus and providing a strobe (STB_I)
-- -the direction of data transfer (read/write) is determined by the LSB of the
-- address (0-write, 1-read)
-- -in case of a 'write' the data byte should also be present on the D_I bus
-- prior to the arrival of the strobe (STB_I)
-- -once the data byte gets read/written, DONE_I pulses high for one CLK cycle
-- -in case of an error, ERR_O will pulse high together with DONE_I; ERR_O low
-- together with DONE_I high indicates success
-- -after DONE_I pulses high there is a 1/4 TWI period time frame when the next
-- strobe can be sent; this is useful, when multiple bytes are sent/received
-- in a single transfer packet; for ex. for write transfers, a new byte can
-- be put on the D_I and STB_I provided;
-- -if no new strobe is provided, the transfer will end
-- -if a new strobe is provided, but the address changed, the current transfer
-- will end and a new will begin
-- -starting a new transfer can be forced with the MSG_I pin; if asserted with
-- a strobe, the data byte will be written/read in a new packet; the advantage
-- of this is relevant only in multi-master buses: rather than waiting for the
-- current transfer to end and the bus to be released, a new transfer can be
-- initiated without giving up the control over the bus
----------------------------------------------------------------------------------
generic (
CLOCKFREQ : natural := 50;
ATTEMPT_SLAVE_UNBLOCK : boolean := false --setting this true will attempt
--to drive a few clock pulses for a slave to allow to finish a previous
--interrupted read transfer, otherwise the bus might remain locked up
); -- input CLK frequency in MHz
port (
MSG_I : in STD_LOGIC; --new message
STB_I : in STD_LOGIC; --strobe
A_I : in STD_LOGIC_VECTOR (7 downto 0); --address input bus
D_I : in STD_LOGIC_VECTOR (7 downto 0); --data input bus
D_O : out STD_LOGIC_VECTOR (7 downto 0); --data output bus
DONE_O : out STD_LOGIC; --done status signal
ERR_O : out STD_LOGIC; --error status
ERRTYPE_O : out error_type; --error type
CLK : in std_logic;
SRST : in std_logic;
----------------------------------------------------------------------------------
-- TWI bus signals
----------------------------------------------------------------------------------
SDA : inout std_logic; --TWI SDA
SCL : inout std_logic --TWI SCL
);
end TWICtl;
architecture Behavioral of TWICtl is
attribute fsm_encoding: string;
constant FSCL : natural := 400_000; --in Hz SCL clock frequency
constant TIMEOUT : natural := 10; --in ms TWI timeout for slave wait period
constant TSCL_CYCLES : natural :=
natural(ceil(real(CLOCKFREQ*1_000_000/FSCL)));
constant TIMEOUT_CYCLES : natural :=
natural(ceil(real(CLOCKFREQ*TIMEOUT*1_000)));
type state_type is (stIdle, stStart, stRead, stWrite, stError, stStop,
stSAck, stMAck, stMNAckStop, stMNAckStart, stStopError);
signal state, nstate : state_type;
attribute fsm_encoding of state: signal is "gray";
signal sync_sda, sync_scl : std_logic_vector(2 downto 0);
signal dSda, ddSda, dScl : std_logic;
signal fStart, fStop : std_logic;
signal busState : busState_type := busUnknown;
signal errTypeR, errType : error_type;
signal busFreeCnt, sclCnt : natural range TSCL_CYCLES downto 0 := TSCL_CYCLES;
signal timeOutCnt : natural range TIMEOUT_CYCLES downto 0 := TIMEOUT_CYCLES;
signal slaveWait, arbLost : std_logic;
signal dataByte, loadByte, currAddr : std_logic_vector(7 downto 0); --shift register and parallel load
signal rSda, rScl : std_logic := '1';
signal subState : std_logic_vector(1 downto 0) := "00";
signal latchData, latchAddr, iDone, iErr, iSda, iScl, shiftBit, dataBitOut, rwBit, addrNData : std_logic;
signal bitCount : natural range 0 to 7 := 7;
signal int_Rst : std_logic := '0';
begin
----------------------------------------------------------------------------------
--Bus State detection
----------------------------------------------------------------------------------
SYNC_FFS: process(CLK)
begin
if Rising_Edge(CLK) then
sync_sda(0) <= SDA;
sync_sda(1) <= sync_sda(0);
sync_sda(2) <= sync_sda(1);
sync_scl(0) <= SCL;
sync_scl(1) <= sync_scl(0);
sync_scl(2) <= sync_scl(1);
end if;
end process;
dSda <= sync_sda(1);
ddSda <= sync_sda(2);
dScl <= sync_scl(1);
fStart <= dScl and not dSda and ddSda; --if SCL high while SDA falling, start condition
fStop <= dScl and dSda and not ddSda; --if SCL high while SDA rising, stop condition
TWISTATE: process(CLK)
begin
if Rising_Edge(CLK) then
if (int_Rst = '1') then
busState <= busUnknown;
elsif (fStart = '1') then --If START condition detected, bus is busy
busState <= busBusy;
elsif (busFreeCnt = 0) then --We counted down tBUF, so it must be free
busState <= busFree;
end if;
end if;
end process;
TBUF_CNT: process(CLK)
begin
if Rising_Edge(CLK) then
if (dSCL = '0' or dSDA = '0' or int_Rst = '1') then
busFreeCnt <= TSCL_CYCLES;
elsif (dSCL = '1' and dSDA = '1') then
busFreeCnt <= busFreeCnt - 1; --counting down 1 SCL period on free bus
end if;
end if;
end process;
----------------------------------------------------------------------------------
--Slave devices can insert wait states by keeping SCL low
----------------------------------------------------------------------------------
slaveWait <= '1' when (dSCL = '0' and rScl = '1') else
'0';
----------------------------------------------------------------------------------
--If the SDA line does not correspond to the transmitted data while the SCL line
--is at the HIGH level the master lost an arbitration to another master.
----------------------------------------------------------------------------------
arbLost <= '1' when (dSCL = '1' and dSDA = '0' and rSda = '1') else
'0';
----------------------------------------------------------------------------------
-- Internal reset signal
----------------------------------------------------------------------------------
RST_PROC: process (CLK)
begin
if Rising_Edge(CLK) then
if (state = stIdle and SRST = '0') then
int_Rst <= '0';
elsif (SRST = '1') then
int_Rst <= '1';
end if;
end if;
end process;
----------------------------------------------------------------------------------
-- SCL period counter
----------------------------------------------------------------------------------
SCL_CNT: process (CLK)
begin
if Rising_Edge(CLK) then
if (sclCnt = 0 or state = stIdle) then
sclCnt <= TSCL_CYCLES/4;
elsif (slaveWait = '0') then -- clock synchronization with other masters
sclCnt <= sclCnt - 1;
end if;
end if;
end process;
----------------------------------------------------------------------------------
-- Slave timeout to determine a locked-up bus
----------------------------------------------------------------------------------
UnblockTimeout: if ATTEMPT_SLAVE_UNBLOCK generate
TIMEOUT_CNT: process (CLK)
begin
if Rising_Edge(CLK) then
if (state /= stIdle or busState = busFree or ((ddSda xor dSda) = '1')) then
timeOutCnt <= TIMEOUT_CYCLES;
else
timeOutCnt <= timeOutCnt - 1;
end if;
end if;
end process;
end generate;
----------------------------------------------------------------------------------
-- Title: Data byte shift register
-- Description: Stores the byte to be written or the byte read depending on the
-- transfer direction.
----------------------------------------------------------------------------------
DATABYTE_SHREG: process (CLK)
begin
if Rising_Edge(CLK) then
if ((latchData = '1' or latchAddr = '1') and sclCnt = 0) then
dataByte <= loadByte; --latch address/data
bitCount <= 7;
--set flag so that we know what is the byte we are sending
if (latchData = '1') then
addrNData <= '0';
else
addrNData <= '1';
end if;
elsif (shiftBit = '1' and sclCnt = 0) then
dataByte <= dataByte(dataByte'high-1 downto 0) & dSDA;
bitCount <= bitCount - 1;
end if;
end if;
end process;
loadByte <= A_I when latchAddr = '1' else
D_I;
dataBitOut <= dataByte(dataByte'high);
D_O <= dataByte;
----------------------------------------------------------------------------------
-- Title: Current address register
-- Description: Stores the TWI slave address
----------------------------------------------------------------------------------
CURRADDR_REG: process (CLK)
begin
if Rising_Edge(CLK) then
if (latchAddr = '1') then
currAddr <= A_I; --latch address/data
end if;
end if;
end process;
rwBit <= currAddr(0);
----------------------------------------------------------------------------------
-- Title: Substate counter
-- Description: Divides each state into 4, to respect the setup and hold times of
-- the TWI bus.
----------------------------------------------------------------------------------
SUBSTATE_CNT: process (CLK)
begin
if Rising_Edge(CLK) then
if (state = stIdle) then
subState <= "00";
elsif (sclCnt = 0) then
subState <= subState + 1;
end if;
end if;
end process;
SYNC_PROC: process (CLK)
begin
if Rising_Edge(CLK) then
state <= nstate;
rSda <= iSda;
rScl <= iScl;
if (int_Rst = '1') then
DONE_O <= '0';
ERR_O <= '0';
errTypeR <= errType;
else
DONE_O <= iDone;
ERR_O <= iErr;
errTypeR <= errType;
end if;
end if;
end process;
OUTPUT_DECODE: process (nstate, subState, state, errTypeR, dataByte(0),
sclCnt, bitCount, rSda, rScl, dataBitOut, arbLost, dSda, addrNData)
begin
iSda <= rSda; --no change by default
iScl <= rScl;
iDone <= '0';
iErr <= '0';
errType <= errTypeR; --keep error type
shiftBit <= '0';
latchAddr <= '0';
latchData <= '0';
if (state = stStart) then
case (subState) is
when "00" =>
iSda <= '1';
--keep SCL
when "01" =>
iSda <= '1';
iScl <= '1';
when "10" =>
iSda <= '0';
iScl <= '1';
when "11" =>
iSda <= '0';
iScl <= '0';
when others =>
end case;
end if;
if (state = stStop or state = stStopError) then
case (subState) is
when "00" =>
iSda <= '0';
--keep SCL
when "01" =>
iSda <= '0';
iScl <= '1';
when "10" =>
iSda <= '1';
iScl <= '1';
when "11" => --we will only reach this is there is an arbitration error
--keep SDA;
iScl <= '0'; --need to toggle clock
when others =>
end case;
end if;
if (state = stRead or state = stSAck) then
case (subState) is
when "00" =>
iSda <= '1'; --this will be 'Z' on SDA
--keep SCL
when "01" =>
--keep SDA
iScl <= '1';
when "10" =>
--keep SDA
iScl <= '1';
when "11" =>
--keep SDA
iScl <= '0';
when others =>
end case;
end if;
if (state = stWrite) then
case (subState) is
when "00" =>
iSda <= dataBitOut;
--keep SCL
when "01" =>
--keep SDA
iScl <= '1';
when "10" =>
--keep SDA
iScl <= '1';
when "11" =>
--keep SDA
iScl <= '0';
when others =>
end case;
end if;
if (state = stMAck) then
case (subState) is
when "00" =>
iSda <= '0'; -- acknowledge by writing 0
--keep SCL
when "01" =>
--keep SDA
iScl <= '1';
when "10" =>
--keep SDA
iScl <= '1';
when "11" =>
--keep SDA
iScl <= '0';
when others =>
end case;
end if;
if (state = stMNAckStop or state = stMNAckStart) then
case (subState) is
when "00" =>
iSda <= '1'; -- not acknowledge by writing 1
--keep SCL
when "01" =>
--keep SDA
iScl <= '1';
when "10" =>
--keep SDA
iScl <= '1';
when "11" =>
--keep SDA
iScl <= '0';
when others =>
end case;
end if;
if (state = stSAck and sclCnt = 0 and subState = "01") then
if (dSda = '1') then
iDone <= '1';
iErr <= '1'; --not acknowledged
errType <= errNAck;
elsif (addrNData = '0') then
--we are done only when the data is sent too after the address
iDone <= '1';
end if;
end if;
if (state = stRead and subState = "01" and sclCnt = 0 and bitCount = 0) then
iDone <= '1'; --read done
end if;
if (state = stWrite and arbLost = '1') then
iDone <= '1'; --write done
iErr <= '1'; --we lost the arbitration
errType <= errArb;
end if;
if ((state = stWrite and sclCnt = 0 and subState = "11") or --shift at end of bit
((state = stSAck or state = stRead) and subState = "01")) then --read in middle of bit
shiftBit <= '1';
end if;
if (state = stStart) then
latchAddr <= '1';
end if;
if (state = stSAck and subState = "11") then --get the data byte for the next write
latchData <= '1';
end if;
end process;
NEXT_STATE_DECODE: process (state, busState, slaveWait, arbLost, STB_I, MSG_I,
SRST, subState, bitCount, int_Rst, dataByte, A_I, currAddr, rwBit, sclCnt, addrNData)
begin
nstate <= state; --default is to stay in current state
case (state) is
when stIdle =>
if (STB_I = '1' and busState = busFree and SRST = '0') then
nstate <= stStart;
elsif (ATTEMPT_SLAVE_UNBLOCK and timeOutCnt = 0) then
nstate <= stStop;
end if;
when stStart =>
if (sclCnt = 0) then
if (int_Rst = '1') then
nstate <= stStop;
elsif (subState = "11") then
nstate <= stWrite;
end if;
end if;
when stWrite =>
if (arbLost = '1') then
nstate <= stIdle;
elsif (sclCnt = 0) then
if (int_Rst = '1') then
nstate <= stStop;
elsif (subState = "11" and bitCount = 0) then
nstate <= stSAck;
end if;
end if;
when stSAck =>
if (sclCnt = 0) then
if (int_Rst = '1' or (subState = "11" and dataByte(0) = '1')) then
nstate <= stStop;
elsif (subState = "11") then
if (addrNData = '1') then --if we have just sent the address, tx/rx the data too
if (rwBit = '1') then
nstate <= stRead;
else
nstate <= stWrite;
end if;
elsif (STB_I = '1') then
if (MSG_I = '1' or currAddr /= A_I) then
nstate <= stStart;
else
if (rwBit = '1') then
nstate <= stRead;
else
nstate <= stWrite;
end if;
end if;
else
nstate <= stStop;
end if;
end if;
end if;
when stStop =>
--bugfix: if device is driving SDA low (read transfer) we cannot send stop bit
--check the arbitration flag
if (subState = "10" and sclCnt = 0 and arbLost = '0') then
nstate <= stIdle;
end if;
--stay here, if stop bit cannot be sent, pulse clock an retry
when stRead =>
if (sclCnt = 0) then
if (int_Rst = '1') then
nstate <= stStop;
elsif (subState = "11" and bitCount = 7) then --bitCount will underflow
if (STB_I = '1') then
if (MSG_I = '1' or currAddr /= A_I) then
nstate <= stMNAckStart;
else
nstate <= stMAck;
end if;
else
nstate <= stMNAckStop;
end if;
end if;
end if;
when stMAck =>
if (sclCnt = 0) then
if (int_Rst = '1') then
nstate <= stStop;
elsif (subState = "11") then
nstate <= stRead;
end if;
end if;
when stMNAckStart =>
if (arbLost = '1') then
nstate <= stIdle; -- arbitration lost, back off, no error because we got all the data
elsif (sclCnt = 0) then
if (int_Rst = '1') then
nstate <= stStop;
elsif (subState = "11") then
nstate <= stStart;
end if;
end if;
when stMNAckStop =>
if (arbLost = '1') then
nstate <= stIdle; -- arbitration lost, back off, no error because we got all the data
elsif (sclCnt = 0) then
if (int_Rst = '1') then
nstate <= stStop;
elsif (subState = "11") then
nstate <= stStop;
end if;
end if;
when others =>
nstate <= stIdle;
end case;
end process;
----------------------------------------------------------------------------------
-- Open-drain outputs for bi-directional SDA and SCL
----------------------------------------------------------------------------------
SDA <= 'Z' when rSDA = '1' else
'0';
SCL <= 'Z' when rSCL = '1' else
'0';
end Behavioral; |
library verilog;
use verilog.vl_types.all;
entity counter741_vlg_check_tst is
port(
Qout : in vl_logic_vector(7 downto 0);
second : in vl_logic;
sampler_rx : in vl_logic
);
end counter741_vlg_check_tst;
|
library ieee;
use ieee.std_logic_1164.all;
entity encoder_behav is
port(
input : in std_logic_vector(5 downto 0);
output : out std_logic_vector(2 downto 0)
);
end entity encoder_behav;
architecture behav of encoder_behav is
begin
process(input)
begin
case input is
when "000001" => output <= "000";
when "000010" => output <= "001";
when "000100" => output <= "010";
when "001000" => output <= "011";
when "010000" => output <= "100";
when "100000" => output <= "101";
when others => output <= "XXX";
end case;
end process;
end behav;
library ieee;
use ieee.std_logic_1164.all;
entity encoder_behav_test_bench is
end encoder_behav_test_bench;
architecture behavior of encoder_behav_test_bench is
-- Component Declaration for the Encoder Behavioral Model Test Bench
component encoder_behav
port(
input : in std_logic_vector(5 downto 0);
output : out std_logic_vector(2 downto 0)
);
end component;
-- inputs
signal input : std_logic_vector(5 downto 0) := (others => '0');
-- outputs
signal output : std_logic_vector(2 downto 0);
begin
-- Instantiate the Encoder Test Bench
test_bench: encoder_behav port map (
input => input,
output => output
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 50 ns.
wait for 50 ns;
input <= "000000";
wait for 50 ns;
input <= "000001";
wait for 50 ns;
input <= "000010";
wait for 50 ns;
input <= "000011";
wait for 50 ns;
input <= "000100";
wait for 50 ns;
input <= "000101";
wait for 50 ns;
input <= "000110";
wait for 50 ns;
input <= "000111";
wait for 50 ns;
input <= "001000";
wait for 50 ns;
input <= "001001";
wait for 50 ns;
input <= "001010";
wait for 50 ns;
input <= "001011";
wait for 50 ns;
input <= "001100";
wait for 50 ns;
input <= "001101";
wait for 50 ns;
input <= "001110";
wait for 50 ns;
input <= "001111";
wait for 50 ns;
input <= "010000";
wait for 50 ns;
input <= "010001";
wait for 50 ns;
input <= "010010";
wait for 50 ns;
input <= "010011";
wait for 50 ns;
input <= "010100";
wait for 50 ns;
input <= "010101";
wait for 50 ns;
input <= "010110";
wait for 50 ns;
input <= "010111";
wait for 50 ns;
input <= "011000";
wait for 50 ns;
input <= "011001";
wait for 50 ns;
input <= "011010";
wait for 50 ns;
input <= "011011";
wait for 50 ns;
input <= "011100";
wait for 50 ns;
input <= "011101";
wait for 50 ns;
input <= "011110";
wait for 50 ns;
input <= "011111";
wait for 50 ns;
input <= "100000";
wait for 50 ns;
input <= "100001";
wait for 50 ns;
input <= "100010";
wait for 50 ns;
input <= "100011";
wait for 50 ns;
input <= "100100";
wait for 50 ns;
input <= "100101";
wait for 50 ns;
input <= "100110";
wait for 50 ns;
input <= "100111";
wait for 50 ns;
input <= "101000";
wait for 50 ns;
input <= "101001";
wait for 50 ns;
input <= "101010";
wait for 50 ns;
input <= "101011";
wait for 50 ns;
input <= "101100";
wait for 50 ns;
input <= "101101";
wait for 50 ns;
input <= "101110";
wait for 50 ns;
input <= "101111";
wait for 50 ns;
input <= "110000";
wait for 50 ns;
input <= "110001";
wait for 50 ns;
input <= "110010";
wait for 50 ns;
input <= "110011";
wait for 50 ns;
input <= "110100";
wait for 50 ns;
input <= "110101";
wait for 50 ns;
input <= "110110";
wait for 50 ns;
input <= "110111";
wait for 50 ns;
input <= "111000";
wait for 50 ns;
input <= "111001";
wait for 50 ns;
input <= "111010";
wait for 50 ns;
input <= "111011";
wait for 50 ns;
input <= "111100";
wait for 50 ns;
input <= "111101";
wait for 50 ns;
input <= "111110";
wait for 50 ns;
input <= "111111";
wait;
end process;
end; |
entity tb_rec2 is
end tb_rec2;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_rec2 is
signal clk : std_logic;
signal sl_in : std_logic;
signal slv_in : std_logic_vector(7 downto 0);
signal int_in : integer range 0 to 15;
signal usig_in : unsigned(7 downto 0);
signal sl_out : std_logic;
signal slv_out : std_logic_vector(7 downto 0);
signal int_out : integer range 0 to 15;
signal usig_out : unsigned(7 downto 0);
begin
dut: entity work.rec2
port map (
clk => clk,
sl_in => sl_in,
slv_in => slv_in,
int_in => int_in,
usig_in => usig_in,
sl_out => sl_out,
slv_out => slv_out,
int_out => int_out,
usig_out => usig_out);
process
begin
clk <= '0';
sl_in <= '1';
slv_in <= x"12";
int_in <= 13;
usig_in <= x"d5";
wait for 1 ns;
clk <= '1';
wait for 1 ns;
assert sl_out = '1' severity failure;
assert slv_out = x"12" severity failure;
assert int_out = 13 severity failure;
assert usig_out = x"d5" severity failure;
sl_in <= '0';
slv_in <= x"9b";
int_in <= 3;
usig_in <= x"72";
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
assert sl_out = '0' severity failure;
assert slv_out = x"9b" severity failure;
assert int_out = 3 severity failure;
assert usig_out = x"72" severity failure;
wait;
end process;
end behav;
|
-------------------------------------------------------------------------------
-- Title : Useful functions for testbenches
-- Project :
-------------------------------------------------------------------------------
-- File : test_pkg.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2015-05-07
-- Last update: 2015-11-30
-- Last update: 2015-07-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This package contains useful functions and procedures for
-- testbenches: clock, reset and ce generators, data reader and writer from
-- files, etc...>
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-05-07 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
package test_pkg is
-- generate basic clock signals : clock and clock enable
procedure p_clk_gen(signal clk : out std_ulogic;
constant c_FREQ : real);
procedure p_ce_gen(signal clk : in std_ulogic;
signal ce : out std_ulogic;
signal rst : in std_ulogic;
constant c_CYCLES : positive);
procedure p_rst_gen(signal clk : in std_ulogic;
signal rst : out std_ulogic;
constant c_CYCLES : positive);
procedure p_pwm_gen(signal clk : in std_ulogic;
signal rst : in std_ulogic;
signal pwm : out std_ulogic;
constant c_on_CYCLE : positive;
constant c_off_CYCLE : positive);
-- Read and write integer data from/to TSV, easily read/written by Octave:
type array_signed is array(natural range <>) of signed;
procedure p_read_tsv_file_signed (
constant c_INPUT_FILE_NAME : string;
constant c_SAMPLES_PER_LINE : positive;
constant c_OUTPUT_WIDTH : positive;
signal clk : in std_ulogic;
signal rst : in std_ulogic;
signal ce : in std_ulogic;
signal req : in std_ulogic;
signal sample : out array_signed;
signal valid : out std_ulogic;
signal end_of_file : out std_ulogic);
procedure p_write_tsv_file_signed (
constant c_OUTPUT_FILE_NAME : string;
constant c_SAMPLES_PER_LINE : positive;
constant c_OUTPUT_WIDTH : positive;
signal clk : in std_ulogic;
signal rst : in std_ulogic;
signal ce : in std_ulogic;
signal sample : in array_signed;
signal valid : in std_ulogic;
signal end_of_file : in std_ulogic);
end test_pkg;
package body test_pkg is
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- procedure: clk_gen
-- Generates clock signal, given any frequency.
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
procedure p_clk_gen(
signal clk : out std_ulogic;
constant c_FREQ : real) is
constant c_PERIOD : time := 1 sec / c_FREQ; -- Full period
constant c_HIGH_TIME : time := c_PERIOD / 2; -- High time
constant c_LOW_TIME : time := c_PERIOD - c_HIGH_TIME; -- Low time; always >= HIGH_TIME
begin
-- Check the arguments
assert (c_HIGH_TIME /= 0 fs) report "clk: High time is zero; time resolution to large for frequency" severity failure;
-- Generate a clock cycle
loop
clk <= '1';
wait for c_HIGH_TIME;
clk <= '0';
wait for c_LOW_TIME;
end loop;
end procedure;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- procedure: p_rst_gen
-- Keeps reset up until c_CYCLES clock cycles
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
procedure p_rst_gen (
signal clk : in std_ulogic;
signal rst : out std_ulogic;
constant c_CYCLES : positive) is
variable v_cycle_count : natural := c_CYCLES;
begin -- procedure p_rst_gen
loop
wait until rising_edge(clk);
if v_cycle_count = 0 then
rst <= '0';
else
v_cycle_count := v_cycle_count -1;
end if;
end loop;
end procedure p_rst_gen;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- procedure: ce_gen
-- Generates one clock enable signals every c_CYCLES number of clock periods.
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
procedure p_ce_gen (
signal clk : in std_ulogic;
signal ce : out std_ulogic;
signal rst : in std_ulogic;
constant c_CYCLES : positive) is
variable ce_count : natural := c_CYCLES;
begin -- procedure p_ce_gen
loop -- generate one ce every ce_CYCLES clocks
wait until rising_edge(clk) and rst = '0';
ce_count := ce_count - 1;
if ce_count = 0 then
ce <= '1';
ce_count := c_CYCLES;
else
ce <= '0';
end if;
end loop;
end procedure p_ce_gen;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- procedure: pwm_gen
-- Generates a clock dependent PWM signal with configurable ON and OFF cycles.
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
procedure p_pwm_gen(
signal clk : in std_ulogic;
signal rst : in std_ulogic;
signal pwm : out std_ulogic;
constant c_on_CYCLE : positive;
constant c_off_CYCLE : positive) is
variable on_count : natural := c_on_CYCLE;
variable off_count : natural := c_off_CYCLE;
begin -- procedure p_ce_gen
loop -- generate one ce every ce_CYCLES clocks
wait until rising_edge(clk) and rst = '0';
if on_count > 0 then
on_count := on_count-1;
pwm <= '1';
elsif off_count > 1 then
off_count := off_count-1;
pwm <= '0';
else
on_count := c_on_CYCLE;
off_count := c_off_CYCLE;
pwm <= '0';
end if;
end loop;
end procedure;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- procedure: p_read_tsv_file_signed
-- Given a file name and clock, output signed vectors representing stimulus
-- in the file.
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
procedure p_read_tsv_file_signed (
constant c_INPUT_FILE_NAME : string;
constant c_SAMPLES_PER_LINE : positive;
constant c_OUTPUT_WIDTH : positive;
signal clk : in std_ulogic;
signal rst : in std_ulogic;
signal ce : in std_ulogic;
signal req : in std_ulogic;
signal sample : out array_signed;
signal valid : out std_ulogic;
signal end_of_file : out std_ulogic) is
file input_file : text open read_mode is c_INPUT_FILE_NAME;
variable cur_line : line;
variable input : integer;
begin -- procedure p_read_tsv_file_signed
end_of_file <= '0';
valid <= '0';
wait until rst = '0';
loop
wait until falling_edge(clk) and ce = '1';
if endfile(input_file) then
end_of_file <= '1';
else
if req = '1' then
valid <= '1';
readline(input_file, cur_line);
for cur_sample in 0 to c_SAMPLES_PER_LINE-1 loop
read(cur_line, input);
sample(cur_sample) <= to_signed(input, c_OUTPUT_WIDTH);
end loop;
else
valid <= '0';
end if;
end if;
end loop;
end procedure p_read_tsv_file_signed;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- procedure: p_write_tsv_file_signed
-- Given a file name and clock, write data from signed vectors to an output
-- file, until end_of_file is set.
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
procedure p_write_tsv_file_signed (
constant c_OUTPUT_FILE_NAME : string;
constant c_SAMPLES_PER_LINE : positive;
constant c_OUTPUT_WIDTH : positive;
signal clk : in std_ulogic;
signal rst : in std_ulogic;
signal ce : in std_ulogic;
signal sample : in array_signed;
signal valid : in std_ulogic;
signal end_of_file : in std_ulogic) is
file output_file : text open write_mode is c_OUTPUT_FILE_NAME;
variable cur_line : line;
variable output : integer;
begin -- procedure p_write_tsv_file_signed
wait until rst = '0';
loop
wait until rising_edge(clk) and ce = '1';
if valid = '1' then
for cur_sample in 0 to c_SAMPLES_PER_LINE-1 loop
output := to_integer(sample(cur_sample));
write(cur_line, output);
write(cur_line, ht);
end loop;
writeline(output_file, cur_line);
end if;
if end_of_file = '1' then
assert(false) report "End of file signal received" severity failure;
end if;
end loop;
end procedure p_write_tsv_file_signed;
end package body test_pkg;
|
-------------------------------------------------------------------------------
-- Title : Useful functions for testbenches
-- Project :
-------------------------------------------------------------------------------
-- File : test_pkg.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2015-05-07
-- Last update: 2015-11-30
-- Last update: 2015-07-15
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: This package contains useful functions and procedures for
-- testbenches: clock, reset and ce generators, data reader and writer from
-- files, etc...>
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-05-07 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library std;
use std.textio.all;
package test_pkg is
-- generate basic clock signals : clock and clock enable
procedure p_clk_gen(signal clk : out std_ulogic;
constant c_FREQ : real);
procedure p_ce_gen(signal clk : in std_ulogic;
signal ce : out std_ulogic;
signal rst : in std_ulogic;
constant c_CYCLES : positive);
procedure p_rst_gen(signal clk : in std_ulogic;
signal rst : out std_ulogic;
constant c_CYCLES : positive);
procedure p_pwm_gen(signal clk : in std_ulogic;
signal rst : in std_ulogic;
signal pwm : out std_ulogic;
constant c_on_CYCLE : positive;
constant c_off_CYCLE : positive);
-- Read and write integer data from/to TSV, easily read/written by Octave:
type array_signed is array(natural range <>) of signed;
procedure p_read_tsv_file_signed (
constant c_INPUT_FILE_NAME : string;
constant c_SAMPLES_PER_LINE : positive;
constant c_OUTPUT_WIDTH : positive;
signal clk : in std_ulogic;
signal rst : in std_ulogic;
signal ce : in std_ulogic;
signal req : in std_ulogic;
signal sample : out array_signed;
signal valid : out std_ulogic;
signal end_of_file : out std_ulogic);
procedure p_write_tsv_file_signed (
constant c_OUTPUT_FILE_NAME : string;
constant c_SAMPLES_PER_LINE : positive;
constant c_OUTPUT_WIDTH : positive;
signal clk : in std_ulogic;
signal rst : in std_ulogic;
signal ce : in std_ulogic;
signal sample : in array_signed;
signal valid : in std_ulogic;
signal end_of_file : in std_ulogic);
end test_pkg;
package body test_pkg is
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- procedure: clk_gen
-- Generates clock signal, given any frequency.
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
procedure p_clk_gen(
signal clk : out std_ulogic;
constant c_FREQ : real) is
constant c_PERIOD : time := 1 sec / c_FREQ; -- Full period
constant c_HIGH_TIME : time := c_PERIOD / 2; -- High time
constant c_LOW_TIME : time := c_PERIOD - c_HIGH_TIME; -- Low time; always >= HIGH_TIME
begin
-- Check the arguments
assert (c_HIGH_TIME /= 0 fs) report "clk: High time is zero; time resolution to large for frequency" severity failure;
-- Generate a clock cycle
loop
clk <= '1';
wait for c_HIGH_TIME;
clk <= '0';
wait for c_LOW_TIME;
end loop;
end procedure;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- procedure: p_rst_gen
-- Keeps reset up until c_CYCLES clock cycles
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
procedure p_rst_gen (
signal clk : in std_ulogic;
signal rst : out std_ulogic;
constant c_CYCLES : positive) is
variable v_cycle_count : natural := c_CYCLES;
begin -- procedure p_rst_gen
loop
wait until rising_edge(clk);
if v_cycle_count = 0 then
rst <= '0';
else
v_cycle_count := v_cycle_count -1;
end if;
end loop;
end procedure p_rst_gen;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- procedure: ce_gen
-- Generates one clock enable signals every c_CYCLES number of clock periods.
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
procedure p_ce_gen (
signal clk : in std_ulogic;
signal ce : out std_ulogic;
signal rst : in std_ulogic;
constant c_CYCLES : positive) is
variable ce_count : natural := c_CYCLES;
begin -- procedure p_ce_gen
loop -- generate one ce every ce_CYCLES clocks
wait until rising_edge(clk) and rst = '0';
ce_count := ce_count - 1;
if ce_count = 0 then
ce <= '1';
ce_count := c_CYCLES;
else
ce <= '0';
end if;
end loop;
end procedure p_ce_gen;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- procedure: pwm_gen
-- Generates a clock dependent PWM signal with configurable ON and OFF cycles.
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
procedure p_pwm_gen(
signal clk : in std_ulogic;
signal rst : in std_ulogic;
signal pwm : out std_ulogic;
constant c_on_CYCLE : positive;
constant c_off_CYCLE : positive) is
variable on_count : natural := c_on_CYCLE;
variable off_count : natural := c_off_CYCLE;
begin -- procedure p_ce_gen
loop -- generate one ce every ce_CYCLES clocks
wait until rising_edge(clk) and rst = '0';
if on_count > 0 then
on_count := on_count-1;
pwm <= '1';
elsif off_count > 1 then
off_count := off_count-1;
pwm <= '0';
else
on_count := c_on_CYCLE;
off_count := c_off_CYCLE;
pwm <= '0';
end if;
end loop;
end procedure;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- procedure: p_read_tsv_file_signed
-- Given a file name and clock, output signed vectors representing stimulus
-- in the file.
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
procedure p_read_tsv_file_signed (
constant c_INPUT_FILE_NAME : string;
constant c_SAMPLES_PER_LINE : positive;
constant c_OUTPUT_WIDTH : positive;
signal clk : in std_ulogic;
signal rst : in std_ulogic;
signal ce : in std_ulogic;
signal req : in std_ulogic;
signal sample : out array_signed;
signal valid : out std_ulogic;
signal end_of_file : out std_ulogic) is
file input_file : text open read_mode is c_INPUT_FILE_NAME;
variable cur_line : line;
variable input : integer;
begin -- procedure p_read_tsv_file_signed
end_of_file <= '0';
valid <= '0';
wait until rst = '0';
loop
wait until falling_edge(clk) and ce = '1';
if endfile(input_file) then
end_of_file <= '1';
else
if req = '1' then
valid <= '1';
readline(input_file, cur_line);
for cur_sample in 0 to c_SAMPLES_PER_LINE-1 loop
read(cur_line, input);
sample(cur_sample) <= to_signed(input, c_OUTPUT_WIDTH);
end loop;
else
valid <= '0';
end if;
end if;
end loop;
end procedure p_read_tsv_file_signed;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- procedure: p_write_tsv_file_signed
-- Given a file name and clock, write data from signed vectors to an output
-- file, until end_of_file is set.
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
procedure p_write_tsv_file_signed (
constant c_OUTPUT_FILE_NAME : string;
constant c_SAMPLES_PER_LINE : positive;
constant c_OUTPUT_WIDTH : positive;
signal clk : in std_ulogic;
signal rst : in std_ulogic;
signal ce : in std_ulogic;
signal sample : in array_signed;
signal valid : in std_ulogic;
signal end_of_file : in std_ulogic) is
file output_file : text open write_mode is c_OUTPUT_FILE_NAME;
variable cur_line : line;
variable output : integer;
begin -- procedure p_write_tsv_file_signed
wait until rst = '0';
loop
wait until rising_edge(clk) and ce = '1';
if valid = '1' then
for cur_sample in 0 to c_SAMPLES_PER_LINE-1 loop
output := to_integer(sample(cur_sample));
write(cur_line, output);
write(cur_line, ht);
end loop;
writeline(output_file, cur_line);
end if;
if end_of_file = '1' then
assert(false) report "End of file signal received" severity failure;
end if;
end loop;
end procedure p_write_tsv_file_signed;
end package body test_pkg;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:28:34 10/04/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/procesadordefinitivo/TBALU.vhd
-- Project Name: procesadordefinitivo
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ALU
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TBALU IS
END TBALU;
ARCHITECTURE behavior OF TBALU IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU
PORT(
OPER1 : IN std_logic_vector(31 downto 0);
OPER2 : IN std_logic_vector(31 downto 0);
ALURESULT : OUT std_logic_vector(31 downto 0);
ALUOP : IN std_logic_vector(5 downto 0)
);
END COMPONENT;
--Inputs
signal OPER1 : std_logic_vector(31 downto 0) := (others => '0');
signal OPER2 : std_logic_vector(31 downto 0) := (others => '0');
signal ALUOP : std_logic_vector(5 downto 0) := (others => '0');
--Outputs
signal ALURESULT : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU PORT MAP (
OPER1 => OPER1,
OPER2 => OPER2,
ALURESULT => ALURESULT,
ALUOP => ALUOP
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
OPER1 <= "00000000000000000000000000000000";
OPER2 <= "00000000000000000000000000000011";
ALUOP <= "000000";
wait for 100 ns;
OPER1 <= "00000000000000000000000000000011";
OPER2 <= "00000000000000000000000000000011";
ALUOP <= "000000";
wait for 100 ns;
OPER1 <= "00000000000000000000000000000000";
OPER2 <= "00000000000000000000000000000011";
ALUOP <= "000010";
wait for 100 ns;
OPER1 <= "00000000000000000000000000000011";
OPER2 <= "00000000000000000000000000000011";
ALUOP <= "000100";
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:28:34 10/04/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/procesadordefinitivo/TBALU.vhd
-- Project Name: procesadordefinitivo
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ALU
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TBALU IS
END TBALU;
ARCHITECTURE behavior OF TBALU IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU
PORT(
OPER1 : IN std_logic_vector(31 downto 0);
OPER2 : IN std_logic_vector(31 downto 0);
ALURESULT : OUT std_logic_vector(31 downto 0);
ALUOP : IN std_logic_vector(5 downto 0)
);
END COMPONENT;
--Inputs
signal OPER1 : std_logic_vector(31 downto 0) := (others => '0');
signal OPER2 : std_logic_vector(31 downto 0) := (others => '0');
signal ALUOP : std_logic_vector(5 downto 0) := (others => '0');
--Outputs
signal ALURESULT : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU PORT MAP (
OPER1 => OPER1,
OPER2 => OPER2,
ALURESULT => ALURESULT,
ALUOP => ALUOP
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
OPER1 <= "00000000000000000000000000000000";
OPER2 <= "00000000000000000000000000000011";
ALUOP <= "000000";
wait for 100 ns;
OPER1 <= "00000000000000000000000000000011";
OPER2 <= "00000000000000000000000000000011";
ALUOP <= "000000";
wait for 100 ns;
OPER1 <= "00000000000000000000000000000000";
OPER2 <= "00000000000000000000000000000011";
ALUOP <= "000010";
wait for 100 ns;
OPER1 <= "00000000000000000000000000000011";
OPER2 <= "00000000000000000000000000000011";
ALUOP <= "000100";
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:28:34 10/04/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/procesadordefinitivo/TBALU.vhd
-- Project Name: procesadordefinitivo
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ALU
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TBALU IS
END TBALU;
ARCHITECTURE behavior OF TBALU IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU
PORT(
OPER1 : IN std_logic_vector(31 downto 0);
OPER2 : IN std_logic_vector(31 downto 0);
ALURESULT : OUT std_logic_vector(31 downto 0);
ALUOP : IN std_logic_vector(5 downto 0)
);
END COMPONENT;
--Inputs
signal OPER1 : std_logic_vector(31 downto 0) := (others => '0');
signal OPER2 : std_logic_vector(31 downto 0) := (others => '0');
signal ALUOP : std_logic_vector(5 downto 0) := (others => '0');
--Outputs
signal ALURESULT : std_logic_vector(31 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU PORT MAP (
OPER1 => OPER1,
OPER2 => OPER2,
ALURESULT => ALURESULT,
ALUOP => ALUOP
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
OPER1 <= "00000000000000000000000000000000";
OPER2 <= "00000000000000000000000000000011";
ALUOP <= "000000";
wait for 100 ns;
OPER1 <= "00000000000000000000000000000011";
OPER2 <= "00000000000000000000000000000011";
ALUOP <= "000000";
wait for 100 ns;
OPER1 <= "00000000000000000000000000000000";
OPER2 <= "00000000000000000000000000000011";
ALUOP <= "000010";
wait for 100 ns;
OPER1 <= "00000000000000000000000000000011";
OPER2 <= "00000000000000000000000000000011";
ALUOP <= "000100";
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
|
package uart_chipsim_pkg is
procedure uart_chipsim_init(stop_unitl_connected : boolean);
attribute foreign of uart_chipsim_init : procedure is "VHPIDIRECT uart_chipsim_init";
-- if the function returns a positive integer, it is a valid value
-- if the function returns a negative value it is either
-- TIMEOUT, meaning that nothing was read
-- or HANGUP, meaning that the client disconnected
function uart_chipsim_read(timeout_value : integer) return integer;
attribute foreign of uart_chipsim_read : function is "VHPIDIRECT uart_chipsim_read";
procedure uart_chipsim_write(x : integer);
attribute foreign of uart_chipsim_write : procedure is "VHPIDIRECT uart_chipsim_write";
procedure uart_chipsim_flush;
attribute foreign of uart_chipsim_flush : procedure is "VHPIDIRECT uart_chipsim_flush";
shared variable my_var : integer := 43;
end package;
package body uart_chipsim_pkg is
procedure uart_chipsim_init(stop_unitl_connected : boolean) is
begin
assert false report "VHPI" severity failure;
end procedure;
function uart_chipsim_read(timeout_value : integer) return integer is
begin
assert false report "VHPI" severity failure;
return 0;
end function;
procedure uart_chipsim_write(x : integer) is
begin
assert false report "VHPI" severity failure;
end procedure;
procedure uart_chipsim_flush is
begin
assert false report "VHPI" severity failure;
end procedure;
end package body;
library ieee;
use ieee.math_real.log2;
use ieee.math_real.ceil;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.uart_chipsim_pkg.all;
entity uart_chipsim is
generic (
g_wait_until_connected : boolean := true;
g_continue_after_disconnect : boolean := true;
g_baud_rate : integer := 9600
);
port (
tx_o : out std_logic;
rx_i : in std_logic
);
end entity;
architecture simulation of uart_chipsim is
signal tx : std_logic := '1';
signal clk_internal : std_logic := '1';
constant clk_internal_period : time := 100 ms / g_baud_rate;
signal value_from_file : integer := -1;
signal tx_dat, rx_dat : std_logic_vector(7 downto 0) := (others => '0');
signal tx_stb, rx_stb : std_logic := '0';
signal tx_stall : std_logic := '0';
function fix_rx_dat(rx : std_logic_vector(7 downto 0)) return std_logic_vector is
variable result : std_logic_vector(rx'range) := rx;
begin
for i in result'range loop
if result(i) /= '1' then
result(i) := '0';
end if;
end loop;
return result;
end function;
begin
-- clock generation
clk_internal <= not clk_internal after clk_internal_period/2;
-- instantiate a uart serializer
uart_tx_inst: entity work.uart_tx
generic map (
g_clk_freq => g_baud_rate*10,
g_baud_rate => g_baud_rate,
g_bits => 8)
port map (
clk_i => clk_internal,
dat_i => tx_dat,
stb_i => tx_stb,
stall_o => tx_stall,
tx_o => tx_o
);
uart_rx_inst: entity work.uart_rx
generic map (
g_clk_freq => g_baud_rate*10,
g_baud_rate => g_baud_rate,
g_bits => 8)
port map (
clk_i => clk_internal,
dat_o => rx_dat,
stb_o => rx_stb,
rx_i => rx_i
);
main: process
variable client_connected : boolean;
variable stop_until_client_connects : boolean := g_wait_until_connected;
begin
wait until rising_edge(clk_internal);
while true loop
uart_chipsim_init(stop_until_client_connects);
stop_until_client_connects := not g_continue_after_disconnect;
client_connected := true;
while client_connected loop
wait until rising_edge(clk_internal);
-- get value from device
if value_from_file < 0 then
value_from_file <= uart_chipsim_read(timeout_value=>0);
if value_from_file = -2 then
client_connected := false;
end if;
end if;
-- provide value to simulation
tx_stb <= '0';
if value_from_file >= 0 and tx_stall = '0' then
tx_dat <= std_logic_vector(to_signed(value_from_file,8));
tx_stb <= '1';
value_from_file <= -1;
end if;
if rx_stb = '1' then
uart_chipsim_write(to_integer(unsigned(fix_rx_dat(rx_dat))));
uart_chipsim_flush;
end if;
end loop;
end loop;
end process;
end architecture;
|
-------------------------------------------------------------------------------
--
-- File: tb_TestAD96xx_92xxSPI_Model_all.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 May 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Test bench used to instantiate the tb_TestAD96xx_92xxSPI_Model as multiple
-- entities so that all supported errors are inserted in the SPI transactions
-- initiated. This test bench is used to test if the tb_TestAD96xx_92xxSPI_Model
-- correctly reports the deliberately inserted errors.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_TestAD96xx_92xxSPI_Model_all is
Generic (
-- Parameter identifying the Zmod:
-- 0 -> Zmod Scope 1410 - 105 (AD9648)
-- 1 -> Zmod Scope 1010 - 40 (AD9204)
-- 2 -> Zmod Scope 1010 - 125 (AD9608)
-- 3 -> Zmod Scope 1210 - 40 (AD9231)
-- 4 -> Zmod Scope 1210 - 125 (AD9628)
-- 5 -> Zmod Scope 1410 - 40 (AD9251)
-- 6 -> Zmod Scope 1410 - 125 (AD9648)
kZmodID : integer range 0 to 6 := 0
);
end tb_TestAD96xx_92xxSPI_Model_all;
architecture Behavioral of tb_TestAD96xx_92xxSPI_Model_all is
begin
-- Test the ADI_2WireSPI_Model for a write operation and no
-- error inserted.
InstWrNoErr: entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 0,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a read operation and no
-- error inserted.
InstRdNoErr: entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 0,
kCmdRdWr => '1',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a write operation with a
-- sSDIO to sSPI_Clk Setup Time error inserted for the SPI transaction.
InstWrData2ClkSetupErr: entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 1,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a write operation with a
-- CS to sSPI_Clk and a data to sSPI_Clk setup time error inserted
-- for the SPI transaction.
InstWrCs2ClkSetupErr: entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 2,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a write operation with a
-- sSDIO to sSPI_Clk hold time error inserted for the SPI transaction.
InstWrData2ClkHoldErr: entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 3,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a write operation with a
-- sCS to sSPI_Clk hold time error inserted for the SPI transaction.
InstWrCs2ClkHoldErr: entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 4,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a write operation with a
-- pulse width errors and a SPI clock period error inserted
-- for the SPI transaction.
InstSclkPulsePeriodErr : entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 5,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a write operation with an
-- extra address bit error inserted for the SPI transaction.
InstNoBitErr : entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 6,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: tb_TestAD96xx_92xxSPI_Model_all.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 May 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Test bench used to instantiate the tb_TestAD96xx_92xxSPI_Model as multiple
-- entities so that all supported errors are inserted in the SPI transactions
-- initiated. This test bench is used to test if the tb_TestAD96xx_92xxSPI_Model
-- correctly reports the deliberately inserted errors.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_TestAD96xx_92xxSPI_Model_all is
Generic (
-- Parameter identifying the Zmod:
-- 0 -> Zmod Scope 1410 - 105 (AD9648)
-- 1 -> Zmod Scope 1010 - 40 (AD9204)
-- 2 -> Zmod Scope 1010 - 125 (AD9608)
-- 3 -> Zmod Scope 1210 - 40 (AD9231)
-- 4 -> Zmod Scope 1210 - 125 (AD9628)
-- 5 -> Zmod Scope 1410 - 40 (AD9251)
-- 6 -> Zmod Scope 1410 - 125 (AD9648)
kZmodID : integer range 0 to 6 := 0
);
end tb_TestAD96xx_92xxSPI_Model_all;
architecture Behavioral of tb_TestAD96xx_92xxSPI_Model_all is
begin
-- Test the ADI_2WireSPI_Model for a write operation and no
-- error inserted.
InstWrNoErr: entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 0,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a read operation and no
-- error inserted.
InstRdNoErr: entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 0,
kCmdRdWr => '1',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a write operation with a
-- sSDIO to sSPI_Clk Setup Time error inserted for the SPI transaction.
InstWrData2ClkSetupErr: entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 1,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a write operation with a
-- CS to sSPI_Clk and a data to sSPI_Clk setup time error inserted
-- for the SPI transaction.
InstWrCs2ClkSetupErr: entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 2,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a write operation with a
-- sSDIO to sSPI_Clk hold time error inserted for the SPI transaction.
InstWrData2ClkHoldErr: entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 3,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a write operation with a
-- sCS to sSPI_Clk hold time error inserted for the SPI transaction.
InstWrCs2ClkHoldErr: entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 4,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a write operation with a
-- pulse width errors and a SPI clock period error inserted
-- for the SPI transaction.
InstSclkPulsePeriodErr : entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 5,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
-- Test the ADI_2WireSPI_Model for a write operation with an
-- extra address bit error inserted for the SPI transaction.
InstNoBitErr : entity work.tb_TestAD96xx_92xxSPI_Model
Generic Map(
kZmodID => kZmodID,
kErrorType => 6,
kCmdRdWr => '0',
kCmdAddr => "0000000000101",
kCmdData => x"AA"
);
end Behavioral;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_1_2;
USE fifo_generator_v13_1_2.fifo_generator_v13_1_2;
ENTITY fifo_generator_rx_inst IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END fifo_generator_rx_inst;
ARCHITECTURE fifo_generator_rx_inst_arch OF fifo_generator_rx_inst IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF fifo_generator_rx_inst_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_1_2 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_1_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF fifo_generator_rx_inst_arch: ARCHITECTURE IS "fifo_generator_v13_1_2,Vivado 2016.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF fifo_generator_rx_inst_arch : ARCHITECTURE IS "fifo_generator_rx_inst,fifo_generator_v13_1_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF fifo_generator_rx_inst_arch: ARCHITECTURE IS "fifo_generator_rx_inst,fifo_generator_v13_1_2,{x_ipProduct=Vivado 2016.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=2,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=12,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=64,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=64,C_ENABLE_RLOCS=0,C_FAMILY=kintex7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_" &
"CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=4kx9,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=4094,C_" &
"PROG_FULL_THRESH_NEGATE_VAL=4093,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=12,C_RD_DEPTH=4096,C_RD_FREQ=1,C_RD_PNTR_WIDTH=12,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=12,C_WR_DEPTH=4096,C_WR_FREQ=1,C_WR_PNTR_WIDTH=12,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STA" &
"GE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_" &
"AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLE" &
"MENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TY" &
"PE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_" &
"WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSER" &
"T_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPT" &
"Y_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 core_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
BEGIN
U0 : fifo_generator_v13_1_2
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 12,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 64,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 64,
C_ENABLE_RLOCS => 0,
C_FAMILY => "kintex7",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "4kx9",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 4094,
C_PROG_FULL_THRESH_NEGATE_VAL => 4093,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 12,
C_RD_DEPTH => 4096,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 12,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 12,
C_WR_DEPTH => 4096,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 12,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 1,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 0,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => clk,
rst => rst,
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => din,
wr_en => wr_en,
rd_en => rd_en,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
empty => empty,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => '0',
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
m_axis_tready => '0',
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
);
END fifo_generator_rx_inst_arch;
|
-------------------------------------------------------------------------------
-- Title : Encoder Module
-- Project : Loa
-------------------------------------------------------------------------------
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- Description: Connectes a quadrature decoder with a 16-bit counter to
-- the internal bus system.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.encoder_module_pkg.all;
use work.quadrature_decoder_pkg.all;
use work.up_down_counter_pkg.all;
-------------------------------------------------------------------------------
entity encoder_module is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#
);
port (
encoder_p : in encoder_type;
index_p : in std_logic; -- index can be used to reset the
-- counter, set to '0' if not used
load_p : in std_logic; -- Save the current encoder value in a
-- buffer register
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic
);
end encoder_module;
-------------------------------------------------------------------------------
architecture behavioral of encoder_module is
type encoder_module_type is record
counter : std_logic_vector(15 downto 0);
data_out : std_logic_vector(15 downto 0);
end record;
signal r, rin : encoder_module_type := (data_out => (others => '0'),
counter => (others => '0'));
signal step : std_logic := '0';
signal up_down : std_logic := '0'; -- Direction for the counter ('1' = up, '0' = down)
signal decode_error : std_logic; -- Decoding Error (A and B lines changes at the same time), currently not used
signal counter : std_logic_vector(15 downto 0);
begin
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
comb_proc : process(bus_i, counter, load_p, r)
variable v : encoder_module_type;
begin
v := r;
v.data_out := (others => '0');
-- Load counter into own buffer
if load_p = '1' then
v.counter := counter;
end if;
-- Check Bus Address
if bus_i.addr = std_logic_vector(to_unsigned(BASE_ADDRESS, 15)) then
if bus_i.we = '1' then
-- TODO
elsif bus_i.re = '1' then
v.data_out := r.counter;
end if;
end if;
rin <= v;
end process comb_proc;
bus_o.data <= r.data_out;
decoder : quadrature_decoder
port map (
encoder_p => encoder_p,
step_p => step,
dir_p => up_down,
error_p => decode_error,
clk => clk);
up_down_counter_1 : up_down_counter
generic map (
WIDTH => 16)
port map (
clk_en_p => step,
up_down_p => up_down,
value_p => counter,
reset => '0',
clk => clk);
end behavioral;
|
-------------------------------------------------------------------------------
-- Title : Encoder Module
-- Project : Loa
-------------------------------------------------------------------------------
-- Platform : Spartan 3
-------------------------------------------------------------------------------
-- Description: Connectes a quadrature decoder with a 16-bit counter to
-- the internal bus system.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.bus_pkg.all;
use work.encoder_module_pkg.all;
use work.quadrature_decoder_pkg.all;
use work.up_down_counter_pkg.all;
-------------------------------------------------------------------------------
entity encoder_module is
generic (
BASE_ADDRESS : integer range 0 to 16#7FFF#
);
port (
encoder_p : in encoder_type;
index_p : in std_logic; -- index can be used to reset the
-- counter, set to '0' if not used
load_p : in std_logic; -- Save the current encoder value in a
-- buffer register
bus_o : out busdevice_out_type;
bus_i : in busdevice_in_type;
clk : in std_logic
);
end encoder_module;
-------------------------------------------------------------------------------
architecture behavioral of encoder_module is
type encoder_module_type is record
counter : std_logic_vector(15 downto 0);
data_out : std_logic_vector(15 downto 0);
end record;
signal r, rin : encoder_module_type := (data_out => (others => '0'),
counter => (others => '0'));
signal step : std_logic := '0';
signal up_down : std_logic := '0'; -- Direction for the counter ('1' = up, '0' = down)
signal decode_error : std_logic; -- Decoding Error (A and B lines changes at the same time), currently not used
signal counter : std_logic_vector(15 downto 0);
begin
seq_proc : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process seq_proc;
comb_proc : process(bus_i, counter, load_p, r)
variable v : encoder_module_type;
begin
v := r;
v.data_out := (others => '0');
-- Load counter into own buffer
if load_p = '1' then
v.counter := counter;
end if;
-- Check Bus Address
if bus_i.addr = std_logic_vector(to_unsigned(BASE_ADDRESS, 15)) then
if bus_i.we = '1' then
-- TODO
elsif bus_i.re = '1' then
v.data_out := r.counter;
end if;
end if;
rin <= v;
end process comb_proc;
bus_o.data <= r.data_out;
decoder : quadrature_decoder
port map (
encoder_p => encoder_p,
step_p => step,
dir_p => up_down,
error_p => decode_error,
clk => clk);
up_down_counter_1 : up_down_counter
generic map (
WIDTH => 16)
port map (
clk_en_p => step,
up_down_p => up_down,
value_p => counter,
reset => '0',
clk => clk);
end behavioral;
|
-- $Id$
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_avmb_core - sim
-- Description: Test bench for avmb - core device handling
--
-- To test: generic, any avmb target
--
-- Target Devices: generic
-- Tool versions: xst 13.4; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2012-02-04 ??? 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.serport.all;
use work.simbus.all;
entity tb_avmb_core is
port (
I_SWI : out slv4; -- mb switches
I_BTN : out slv1 -- mb button
);
end tb_avmb_core;
architecture sim of tb_avmb_core is
signal R_SWI : slv4 := (others=>'0');
signal R_BTN : slv1 := (others=>'0');
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
end sim;
|
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity PSR_Modifier is
Port ( oper1 : in STD_LOGIC_VECTOR (31 downto 0);
oper2 : in STD_LOGIC_VECTOR (31 downto 0);
aluop : in STD_LOGIC_VECTOR (5 downto 0);
aluResult : in STD_LOGIC_VECTOR (31 downto 0);
conditionalCodes : out STD_LOGIC_VECTOR (3 downto 0));
end PSR_Modifier;
architecture Behavioral of PSR_Modifier is
begin
process(aluop,oper1,oper2,aluResult)
begin
if (aluop="010001" or aluop="010101" or aluop="010010" or aluop="010110" or aluop="010011" or aluop="010111") then -- ANDcc,ANDNcc,ORcc,ORNcc,XORcc,XNORcc
conditionalCodes(3)<= aluResult(31); --N
if aluResult="00000000000000000000000000000000" then --Z
conditionalCodes(2)<='1';
else
conditionalCodes(2)<='0';
end if;
conditionalCodes(1)<= '0'; --V
conditionalCodes(0)<= '0'; --C
elsif (aluop="010000" or aluop="011000") then --ADDcc, ADDXcc
conditionalCodes(3)<= aluResult(31); --N
if aluResult="00000000000000000000000000000000" then --Z
conditionalCodes(2)<='1';
else
conditionalCodes(2)<='0';
end if;
conditionalCodes(1)<=(oper1(31) and oper2(31) and (not aluResult(31))) or ((not oper1(31)) and (not oper2(31)) and aluResult(31));
conditionalCodes(0)<=(oper1(31) and oper2(31)) or ((not aluResult(31)) and (oper1(31) or oper2(31)));
elsif (aluop="010100" or aluop="011100") then --SUBcc, SUBXcc
conditionalCodes(3)<= aluResult(31); --N
if aluResult="00000000000000000000000000000000" then --Z
conditionalCodes(2)<='1';
else
conditionalCodes(2)<='0';
end if;
conditionalCodes(1)<=(oper1(31) and (not oper2(31)) and (not aluResult(31))) or ((not oper1(31)) and oper2(31) and aluResult(31));
conditionalCodes(0)<=((not oper1(31)) and oper2(31)) or (aluResult(31) and ((not oper1(31)) or oper2(31)));
end if;
end process;
end Behavioral; |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity PSR_Modifier is
Port ( oper1 : in STD_LOGIC_VECTOR (31 downto 0);
oper2 : in STD_LOGIC_VECTOR (31 downto 0);
aluop : in STD_LOGIC_VECTOR (5 downto 0);
aluResult : in STD_LOGIC_VECTOR (31 downto 0);
conditionalCodes : out STD_LOGIC_VECTOR (3 downto 0));
end PSR_Modifier;
architecture Behavioral of PSR_Modifier is
begin
process(aluop,oper1,oper2,aluResult)
begin
if (aluop="010001" or aluop="010101" or aluop="010010" or aluop="010110" or aluop="010011" or aluop="010111") then -- ANDcc,ANDNcc,ORcc,ORNcc,XORcc,XNORcc
conditionalCodes(3)<= aluResult(31); --N
if aluResult="00000000000000000000000000000000" then --Z
conditionalCodes(2)<='1';
else
conditionalCodes(2)<='0';
end if;
conditionalCodes(1)<= '0'; --V
conditionalCodes(0)<= '0'; --C
elsif (aluop="010000" or aluop="011000") then --ADDcc, ADDXcc
conditionalCodes(3)<= aluResult(31); --N
if aluResult="00000000000000000000000000000000" then --Z
conditionalCodes(2)<='1';
else
conditionalCodes(2)<='0';
end if;
conditionalCodes(1)<=(oper1(31) and oper2(31) and (not aluResult(31))) or ((not oper1(31)) and (not oper2(31)) and aluResult(31));
conditionalCodes(0)<=(oper1(31) and oper2(31)) or ((not aluResult(31)) and (oper1(31) or oper2(31)));
elsif (aluop="010100" or aluop="011100") then --SUBcc, SUBXcc
conditionalCodes(3)<= aluResult(31); --N
if aluResult="00000000000000000000000000000000" then --Z
conditionalCodes(2)<='1';
else
conditionalCodes(2)<='0';
end if;
conditionalCodes(1)<=(oper1(31) and (not oper2(31)) and (not aluResult(31))) or ((not oper1(31)) and oper2(31) and aluResult(31));
conditionalCodes(0)<=((not oper1(31)) and oper2(31)) or (aluResult(31) and ((not oper1(31)) or oper2(31)));
end if;
end process;
end Behavioral; |
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity PSR_Modifier is
Port ( oper1 : in STD_LOGIC_VECTOR (31 downto 0);
oper2 : in STD_LOGIC_VECTOR (31 downto 0);
aluop : in STD_LOGIC_VECTOR (5 downto 0);
aluResult : in STD_LOGIC_VECTOR (31 downto 0);
conditionalCodes : out STD_LOGIC_VECTOR (3 downto 0));
end PSR_Modifier;
architecture Behavioral of PSR_Modifier is
begin
process(aluop,oper1,oper2,aluResult)
begin
if (aluop="010001" or aluop="010101" or aluop="010010" or aluop="010110" or aluop="010011" or aluop="010111") then -- ANDcc,ANDNcc,ORcc,ORNcc,XORcc,XNORcc
conditionalCodes(3)<= aluResult(31); --N
if aluResult="00000000000000000000000000000000" then --Z
conditionalCodes(2)<='1';
else
conditionalCodes(2)<='0';
end if;
conditionalCodes(1)<= '0'; --V
conditionalCodes(0)<= '0'; --C
elsif (aluop="010000" or aluop="011000") then --ADDcc, ADDXcc
conditionalCodes(3)<= aluResult(31); --N
if aluResult="00000000000000000000000000000000" then --Z
conditionalCodes(2)<='1';
else
conditionalCodes(2)<='0';
end if;
conditionalCodes(1)<=(oper1(31) and oper2(31) and (not aluResult(31))) or ((not oper1(31)) and (not oper2(31)) and aluResult(31));
conditionalCodes(0)<=(oper1(31) and oper2(31)) or ((not aluResult(31)) and (oper1(31) or oper2(31)));
elsif (aluop="010100" or aluop="011100") then --SUBcc, SUBXcc
conditionalCodes(3)<= aluResult(31); --N
if aluResult="00000000000000000000000000000000" then --Z
conditionalCodes(2)<='1';
else
conditionalCodes(2)<='0';
end if;
conditionalCodes(1)<=(oper1(31) and (not oper2(31)) and (not aluResult(31))) or ((not oper1(31)) and oper2(31) and aluResult(31));
conditionalCodes(0)<=((not oper1(31)) and oper2(31)) or (aluResult(31) and ((not oper1(31)) or oper2(31)));
end if;
end process;
end Behavioral; |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.component_pack.all;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic;
-- fault injector shift register with serial input signals
TCK: in std_logic;
SE: in std_logic; -- shift enable
UE: in std_logic; -- update enable
SI: in std_logic; -- serial Input
SO: out std_logic; -- serial output
-- Checker outputs
-- Functional checkers
err_empty_full, err_empty_read_en, err_full_write_en, err_state_in_onehot,
err_read_pointer_in_onehot, err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer, err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full,
err_read_pointer_increment, err_read_pointer_not_increment, err_write_en, err_not_write_en, err_not_write_en1,
err_not_write_en2, err_read_en_mismatch, err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in : out std_logic
);
end FIFO_credit_based;
architecture behavior of FIFO_credit_based is
----------------------------------------
-- Signals related to fault injection --
----------------------------------------
-- Total: 8 bits
signal FI_add_sta: std_logic_vector(7 downto 0); -- 6 bits for fault injection location address (ceil of log2(44) = 6)
-- 2 bits for type of fault (SA0 or SA1)
signal non_faulty_signals: std_logic_vector (43 downto 0); -- 44 bits for internal- and output-related signals (non-faulty)
signal faulty_signals: std_logic_vector(43 downto 0); -- 44 bits for internal- and output-related signals (with single stuck-at fault injected in one of them)
----------------------------------------
----------------------------------------
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
-- Packet Dropping FSM states encoded as one-hot (because of checkers for one-bit error detection)
CONSTANT Idle: std_logic_vector (4 downto 0) := "00001";
CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010";
CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100";
CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000";
CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000";
signal fault_info_in, fault_info_out: std_logic;
signal faulty_packet_in, faulty_packet_out: std_logic;
signal xor_all, fault_out: std_logic;
signal state_out, state_in : std_logic_vector(4 downto 0); -- : state_type;
signal fake_credit, credit_in, write_fake_flit: std_logic;
signal fake_credit_counter, fake_credit_counter_in: std_logic_vector(1 downto 0);
-- Signal(s) needed for FIFO control part checkers
signal fault_info_sig, health_info_sig : std_logic;
-- Signal(s) used for creating the chain of injected fault locations (Control Part of FIFO only)
-- Total: 44 bits ??!!
-- FIFO's control part internal-related signals
signal read_pointer_faulty, read_pointer_in_faulty : std_logic_vector(3 downto 0);
signal write_pointer_faulty, write_pointer_in_faulty : std_logic_vector(3 downto 0);
signal full_faulty, read_en_faulty, write_en_faulty : std_logic;
signal fake_credit_faulty : std_logic;
signal fake_credit_counter_faulty, fake_credit_counter_in_faulty : std_logic_vector(1 downto 0);
signal state_out_faulty, state_in_faulty : std_logic_vector (4 downto 0);
signal fault_info_out_faulty, fault_info_in_faulty : std_logic;
signal faulty_packet_out_faulty, faulty_packet_in_faulty : std_logic;
--signal flit_type_faulty : std_logic; -- ??!! (Actually, flit_type is an alias, showing RX from bits 31 downto 29, maybe we can define it as a signal for injection) (Not sure yet !)
signal fault_out_faulty, write_fake_flit_faulty : std_logic;
-- FIFO's control part output-related signals
signal credit_in_faulty : std_logic; -- ??!! (Actually, it is credit_in, which is the previous value of credit_out in FIFO)
signal empty_faulty : std_logic;
signal fault_info_sig_faulty : std_logic; -- ??!! (which goes to the fault_info output of FIFO)
signal health_info_sig_faulty : std_logic; -- ??!! (which goes to the health_info output of FIFO)
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
-- Packet drop state machine
-- +---+ No +---+ No
-- | | Flit | | Flit
-- | v | v
-- healthy +--------+ +--------+
-- +---header-->| | | |-------------------+
-- | +->| Header |---Healthy body-->| Body |------------+ |
-- | | +--------+ +--------+ | |
-- | | | ^ | Healthy | ^ Healthy |
-- | | | | | body | | Tail |
-- | | | | | +---+ | |
-- | | | | | v |
-- +--------+ | | | | +--------+ |
-- No +-->| | | | | +-----------------Healthy Tail------>| | |
-- Flit| | IDLE | | | | | Tail |--)--+
-- +---| | | | +-----------Healthy Header--------------| | | |
-- +--------+ | | +--------+ | |
-- ^ | ^ | Faulty No Faulty | |
-- | | | | Flit Flit Flit | |
-- | | | | +------------+ +---+ +---+ | |
-- | | | + --Healthy------+ | | | | | | |
-- | | | header | v | v | v | |
-- | | | +------------------+ | |
-- | | +----Healthy Tail-----| Packet | | |
-- | +-------Faulty Flit----->| Drop |<-----------------------+ |
-- | +------------------+ |
-- +-------------------------------------------------No Flit------------------+
--
------------------------------------------------------------------------------------------------
-------------------------------------
---- Related to fault injection -----
-------------------------------------
-- Total: 44 bits
-- Still not sure whether to include flit_type or not ??!!
-- credit_in is actually the previous value of credit_out in FIFO !!
-- for fault_info and health_info outputs, not sure whether to include them or the signals with _sig suffix in their names ??!!
non_faulty_signals <= read_pointer & read_pointer_in & write_pointer & write_pointer_in & full & read_en &
write_en & fake_credit & fake_credit_counter & fake_credit_counter_in & state_out &
state_in & fault_info_out & fault_info_in & faulty_packet_out & faulty_packet_in &
fault_out & write_fake_flit & credit_in & empty & fault_info_sig & health_info_sig;
-- Fault injector module instantiation
FI: fault_injector generic map(DATA_WIDTH => 44, ADDRESS_WIDTH => 6)
port map (data_in=> non_faulty_signals , address => FI_add_sta(7 downto 2), sta_0=> FI_add_sta(1), sta_1=> FI_add_sta(0), data_out=> faulty_signals
);
-- Extracting faulty values for internal- and output-related signals
-- Total: 44 bits
read_pointer_faulty <= faulty_signals (43 downto 40);
read_pointer_in_faulty <= faulty_signals (39 downto 36);
write_pointer_faulty <= faulty_signals (35 downto 32);
write_pointer_in_faulty <= faulty_signals (31 downto 28);
full_faulty <= faulty_signals (27);
read_en_faulty <= faulty_signals (26);
write_en_faulty <= faulty_signals (25);
fake_credit_faulty <= faulty_signals (24);
fake_credit_counter_faulty <= faulty_signals (23 downto 22);
fake_credit_counter_in_faulty <= faulty_signals (21 downto 20);
state_out_faulty <= faulty_signals (19 downto 15);
state_in_faulty <= faulty_signals (14 downto 10);
fault_info_out_faulty <= faulty_signals (9);
fault_info_in_faulty <= faulty_signals (8);
faulty_packet_out_faulty <= faulty_signals (7);
faulty_packet_in_faulty <= faulty_signals (6);
fault_out_faulty <= faulty_signals (5);
write_fake_flit_faulty <= faulty_signals (4);
credit_in_faulty <= faulty_signals (3);
empty_faulty <= faulty_signals (2);
fault_info_sig_faulty <= faulty_signals (1);
health_info_sig_faulty <= faulty_signals (0);
-- Total: 8 bits
-- We only use the shift register with serial in for :
-- (1) feeding the values of address width
-- (the address where the single stuck-at fault should be injected)
-- (2) feeding the values of the type of fault (stuck-at-1 (SA1) or stuck-at-0 (SA0) or no fault)
SR: shift_register_serial_in generic map(REG_WIDTH => 8)
port map ( TCK=> TCK, reset=>reset, SE=> SE, UE=> UE, SI=> SI, SO=> SO, data_out_parallel=> FI_add_sta
);
-------------------------------------
-------------------------------------
-- FIFO control part with packet drop and fault classifier support checkers instantiation
FIFO_control_part_checkers:
FIFO_credit_based_control_part_checkers
port map (
valid_in => valid_in,
read_en_N => read_en_N, read_en_E => read_en_E, read_en_W => read_en_W, read_en_S => read_en_S, read_en_L => read_en_L,
read_pointer => read_pointer_faulty, read_pointer_in => read_pointer_in_faulty,
write_pointer => write_pointer_faulty, write_pointer_in => write_pointer_in_faulty,
credit_out => credit_in_faulty, -- correct ?! (credit_in in FIFO is actually the previous value of credit_out, going to the input of a register)
empty_out => empty_faulty, full_out => full_faulty, read_en_out => read_en_faulty, write_en_out => write_en_faulty,
fake_credit => fake_credit_faulty, fake_credit_counter => fake_credit_counter_faulty,
fake_credit_counter_in => fake_credit_counter_in_faulty, state_out => state_out_faulty, state_in => state_in_faulty,
fault_info => fault_info_sig_faulty, -- connected to signal
fault_info_out => fault_info_out_faulty, fault_info_in => fault_info_in_faulty,
health_info => health_info_sig_faulty, -- connected to signal
faulty_packet_out => faulty_packet_out_faulty, faulty_packet_in => faulty_packet_in_faulty,
flit_type => RX(DATA_WIDTH-1 downto DATA_WIDTH-3), -- Behrad: Not sure about this yet ?!
fault_out => fault_out_faulty, write_fake_flit => write_fake_flit_faulty,
-- Functional checkers
err_empty_full => err_empty_full, err_empty_read_en => err_empty_read_en, err_full_write_en => err_full_write_en,
err_state_in_onehot => err_state_in_onehot, err_read_pointer_in_onehot => err_read_pointer_in_onehot,
err_write_pointer_in_onehot => err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => err_write_en_write_pointer, err_not_write_en_write_pointer => err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => err_read_pointer_write_pointer_full,
err_read_pointer_increment => err_read_pointer_increment, err_read_pointer_not_increment => err_read_pointer_not_increment,
err_write_en => err_write_en, err_not_write_en => err_not_write_en, err_not_write_en1 => err_not_write_en1,
err_not_write_en2 => err_not_write_en2, err_read_en_mismatch => err_read_en_mismatch,
err_read_en_mismatch1 => err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
-- Becuase of checkers we did this
fault_info <= fault_info_sig; -- Not sure yet ?!
health_info <= health_info_sig; -- Not sure yet ?!
-- Sequential part
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
FIFO_MEM_1 <= (others=>'0'); FIFO_MEM_2 <= (others=>'0'); FIFO_MEM_3 <= (others=>'0'); FIFO_MEM_4 <= (others=>'0');
fake_credit_counter <= (others=>'0');
faulty_packet_out <= '0';
credit_out <= '0';
state_out <= Idle;
fault_info_out <= '0';
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
state_out <= state_in;
faulty_packet_out <= faulty_packet_in;
credit_out <= credit_in;
fake_credit_counter <= fake_credit_counter_in;
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in; FIFO_MEM_2 <= FIFO_MEM_2_in; FIFO_MEM_3 <= FIFO_MEM_3_in; FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
fault_info_out <= fault_info_in;
end if;
end process;
-- Anything below here is pure combinational
-- combinatorial part
fault_info_sig <= fault_info_out;
process(fake_credit, read_en, fake_credit_counter) begin
fake_credit_counter_in <= fake_credit_counter;
credit_in <= '0';
if fake_credit = '1' and read_en = '1' then
fake_credit_counter_in <= fake_credit_counter + 1 ;
end if;
if fake_credit = '1' or read_en ='1' then
credit_in <= '1';
end if;
if fake_credit = '0' and read_en = '0' and fake_credit_counter > 0 then
fake_credit_counter_in <= fake_credit_counter - 1 ;
credit_in <= '1';
end if;
end process;
process(valid_in, RX) begin
xor_all <= '0';
if valid_in = '1' then
xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
end if;
end process;
process(valid_in, RX, xor_all)begin
fault_out <= '0';
if valid_in = '1' and xor_all /= RX(0) then
fault_out <= '1';
end if;
end process;
process(RX, faulty_packet_out, fault_out, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4, state_out, valid_in) begin
-- this is the default value of the memory!
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
end case ;
--some defaults
fault_info_in <= '0';
health_info_sig <= '0';
fake_credit <= '0';
state_in <= state_out;
faulty_packet_in <= faulty_packet_out;
write_fake_flit <= '0';
case(state_out) is
when Idle =>
if fault_out = '0' then
if valid_in = '1' then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
when Header_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
state_in <= Body_flit;
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" then
state_in <= Tail_flit;
else
-- we should not be here!
state_in <= state_out;
end if;
else -- fault_out = '1'
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
end case ;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Body_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
state_in <= state_out;
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" then
state_in <= Tail_flit;
health_info_sig <= '1';
else
-- we should not be here!
state_in <= state_out;
end if;
else -- fault_out = '1'
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
end case ;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Tail_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else -- fault_out = '1'
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= Idle;
end if;
when Packet_drop =>
state_in <= state_out;
if faulty_packet_out = '1' then
report "FIFO dropping packet at" & time'image(now) &"!" severity note;
if valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" and fault_out = '0' then
faulty_packet_in <= '0';
state_in <= Header_flit;
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
end case ;
elsif valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" and fault_out = '0' then
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
faulty_packet_in <= '0';
state_in <= Idle;
fake_credit <= '1';
else -- fault_out might have been '1'
if valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" then
fault_info_in <= '1';
end if;
if valid_in = '1' then
fake_credit <= '1';
end if;
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= state_out;
end if;
end if;
when others => state_in <= state_out;
end case;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when others => Data_out <= FIFO_MEM_4;
end case ;
end process;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
process(write_en, write_pointer)begin
write_pointer_in <= write_pointer;
if write_en = '1' then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
end if;
end process;
process(read_en, empty, read_pointer)begin
read_pointer_in <= read_pointer;
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
end if;
end process;
process(full, valid_in, write_fake_flit, faulty_packet_out, fault_out) begin
write_en <= '0';
if valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full ='0' then
write_en <= '1';
end if;
end process;
process(write_pointer, read_pointer) begin
empty <= '0';
full <= '0';
if read_pointer = write_pointer then
empty <= '1';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
end if;
end process;
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.component_pack.all;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic;
-- fault injector shift register with serial input signals
TCK: in std_logic;
SE: in std_logic; -- shift enable
UE: in std_logic; -- update enable
SI: in std_logic; -- serial Input
SO: out std_logic; -- serial output
-- Checker outputs
-- Functional checkers
err_empty_full, err_empty_read_en, err_full_write_en, err_state_in_onehot,
err_read_pointer_in_onehot, err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer, err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full,
err_read_pointer_increment, err_read_pointer_not_increment, err_write_en, err_not_write_en, err_not_write_en1,
err_not_write_en2, err_read_en_mismatch, err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in : out std_logic
);
end FIFO_credit_based;
architecture behavior of FIFO_credit_based is
----------------------------------------
-- Signals related to fault injection --
----------------------------------------
-- Total: 8 bits
signal FI_add_sta: std_logic_vector(7 downto 0); -- 6 bits for fault injection location address (ceil of log2(44) = 6)
-- 2 bits for type of fault (SA0 or SA1)
signal non_faulty_signals: std_logic_vector (43 downto 0); -- 44 bits for internal- and output-related signals (non-faulty)
signal faulty_signals: std_logic_vector(43 downto 0); -- 44 bits for internal- and output-related signals (with single stuck-at fault injected in one of them)
----------------------------------------
----------------------------------------
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
-- Packet Dropping FSM states encoded as one-hot (because of checkers for one-bit error detection)
CONSTANT Idle: std_logic_vector (4 downto 0) := "00001";
CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010";
CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100";
CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000";
CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000";
signal fault_info_in, fault_info_out: std_logic;
signal faulty_packet_in, faulty_packet_out: std_logic;
signal xor_all, fault_out: std_logic;
signal state_out, state_in : std_logic_vector(4 downto 0); -- : state_type;
signal fake_credit, credit_in, write_fake_flit: std_logic;
signal fake_credit_counter, fake_credit_counter_in: std_logic_vector(1 downto 0);
-- Signal(s) needed for FIFO control part checkers
signal fault_info_sig, health_info_sig : std_logic;
-- Signal(s) used for creating the chain of injected fault locations (Control Part of FIFO only)
-- Total: 44 bits ??!!
-- FIFO's control part internal-related signals
signal read_pointer_faulty, read_pointer_in_faulty : std_logic_vector(3 downto 0);
signal write_pointer_faulty, write_pointer_in_faulty : std_logic_vector(3 downto 0);
signal full_faulty, read_en_faulty, write_en_faulty : std_logic;
signal fake_credit_faulty : std_logic;
signal fake_credit_counter_faulty, fake_credit_counter_in_faulty : std_logic_vector(1 downto 0);
signal state_out_faulty, state_in_faulty : std_logic_vector (4 downto 0);
signal fault_info_out_faulty, fault_info_in_faulty : std_logic;
signal faulty_packet_out_faulty, faulty_packet_in_faulty : std_logic;
--signal flit_type_faulty : std_logic; -- ??!! (Actually, flit_type is an alias, showing RX from bits 31 downto 29, maybe we can define it as a signal for injection) (Not sure yet !)
signal fault_out_faulty, write_fake_flit_faulty : std_logic;
-- FIFO's control part output-related signals
signal credit_in_faulty : std_logic; -- ??!! (Actually, it is credit_in, which is the previous value of credit_out in FIFO)
signal empty_faulty : std_logic;
signal fault_info_sig_faulty : std_logic; -- ??!! (which goes to the fault_info output of FIFO)
signal health_info_sig_faulty : std_logic; -- ??!! (which goes to the health_info output of FIFO)
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
-- Packet drop state machine
-- +---+ No +---+ No
-- | | Flit | | Flit
-- | v | v
-- healthy +--------+ +--------+
-- +---header-->| | | |-------------------+
-- | +->| Header |---Healthy body-->| Body |------------+ |
-- | | +--------+ +--------+ | |
-- | | | ^ | Healthy | ^ Healthy |
-- | | | | | body | | Tail |
-- | | | | | +---+ | |
-- | | | | | v |
-- +--------+ | | | | +--------+ |
-- No +-->| | | | | +-----------------Healthy Tail------>| | |
-- Flit| | IDLE | | | | | Tail |--)--+
-- +---| | | | +-----------Healthy Header--------------| | | |
-- +--------+ | | +--------+ | |
-- ^ | ^ | Faulty No Faulty | |
-- | | | | Flit Flit Flit | |
-- | | | | +------------+ +---+ +---+ | |
-- | | | + --Healthy------+ | | | | | | |
-- | | | header | v | v | v | |
-- | | | +------------------+ | |
-- | | +----Healthy Tail-----| Packet | | |
-- | +-------Faulty Flit----->| Drop |<-----------------------+ |
-- | +------------------+ |
-- +-------------------------------------------------No Flit------------------+
--
------------------------------------------------------------------------------------------------
-------------------------------------
---- Related to fault injection -----
-------------------------------------
-- Total: 44 bits
-- Still not sure whether to include flit_type or not ??!!
-- credit_in is actually the previous value of credit_out in FIFO !!
-- for fault_info and health_info outputs, not sure whether to include them or the signals with _sig suffix in their names ??!!
non_faulty_signals <= read_pointer & read_pointer_in & write_pointer & write_pointer_in & full & read_en &
write_en & fake_credit & fake_credit_counter & fake_credit_counter_in & state_out &
state_in & fault_info_out & fault_info_in & faulty_packet_out & faulty_packet_in &
fault_out & write_fake_flit & credit_in & empty & fault_info_sig & health_info_sig;
-- Fault injector module instantiation
FI: fault_injector generic map(DATA_WIDTH => 44, ADDRESS_WIDTH => 6)
port map (data_in=> non_faulty_signals , address => FI_add_sta(7 downto 2), sta_0=> FI_add_sta(1), sta_1=> FI_add_sta(0), data_out=> faulty_signals
);
-- Extracting faulty values for internal- and output-related signals
-- Total: 44 bits
read_pointer_faulty <= faulty_signals (43 downto 40);
read_pointer_in_faulty <= faulty_signals (39 downto 36);
write_pointer_faulty <= faulty_signals (35 downto 32);
write_pointer_in_faulty <= faulty_signals (31 downto 28);
full_faulty <= faulty_signals (27);
read_en_faulty <= faulty_signals (26);
write_en_faulty <= faulty_signals (25);
fake_credit_faulty <= faulty_signals (24);
fake_credit_counter_faulty <= faulty_signals (23 downto 22);
fake_credit_counter_in_faulty <= faulty_signals (21 downto 20);
state_out_faulty <= faulty_signals (19 downto 15);
state_in_faulty <= faulty_signals (14 downto 10);
fault_info_out_faulty <= faulty_signals (9);
fault_info_in_faulty <= faulty_signals (8);
faulty_packet_out_faulty <= faulty_signals (7);
faulty_packet_in_faulty <= faulty_signals (6);
fault_out_faulty <= faulty_signals (5);
write_fake_flit_faulty <= faulty_signals (4);
credit_in_faulty <= faulty_signals (3);
empty_faulty <= faulty_signals (2);
fault_info_sig_faulty <= faulty_signals (1);
health_info_sig_faulty <= faulty_signals (0);
-- Total: 8 bits
-- We only use the shift register with serial in for :
-- (1) feeding the values of address width
-- (the address where the single stuck-at fault should be injected)
-- (2) feeding the values of the type of fault (stuck-at-1 (SA1) or stuck-at-0 (SA0) or no fault)
SR: shift_register_serial_in generic map(REG_WIDTH => 8)
port map ( TCK=> TCK, reset=>reset, SE=> SE, UE=> UE, SI=> SI, SO=> SO, data_out_parallel=> FI_add_sta
);
-------------------------------------
-------------------------------------
-- FIFO control part with packet drop and fault classifier support checkers instantiation
FIFO_control_part_checkers:
FIFO_credit_based_control_part_checkers
port map (
valid_in => valid_in,
read_en_N => read_en_N, read_en_E => read_en_E, read_en_W => read_en_W, read_en_S => read_en_S, read_en_L => read_en_L,
read_pointer => read_pointer_faulty, read_pointer_in => read_pointer_in_faulty,
write_pointer => write_pointer_faulty, write_pointer_in => write_pointer_in_faulty,
credit_out => credit_in_faulty, -- correct ?! (credit_in in FIFO is actually the previous value of credit_out, going to the input of a register)
empty_out => empty_faulty, full_out => full_faulty, read_en_out => read_en_faulty, write_en_out => write_en_faulty,
fake_credit => fake_credit_faulty, fake_credit_counter => fake_credit_counter_faulty,
fake_credit_counter_in => fake_credit_counter_in_faulty, state_out => state_out_faulty, state_in => state_in_faulty,
fault_info => fault_info_sig_faulty, -- connected to signal
fault_info_out => fault_info_out_faulty, fault_info_in => fault_info_in_faulty,
health_info => health_info_sig_faulty, -- connected to signal
faulty_packet_out => faulty_packet_out_faulty, faulty_packet_in => faulty_packet_in_faulty,
flit_type => RX(DATA_WIDTH-1 downto DATA_WIDTH-3), -- Behrad: Not sure about this yet ?!
fault_out => fault_out_faulty, write_fake_flit => write_fake_flit_faulty,
-- Functional checkers
err_empty_full => err_empty_full, err_empty_read_en => err_empty_read_en, err_full_write_en => err_full_write_en,
err_state_in_onehot => err_state_in_onehot, err_read_pointer_in_onehot => err_read_pointer_in_onehot,
err_write_pointer_in_onehot => err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => err_write_en_write_pointer, err_not_write_en_write_pointer => err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => err_read_pointer_write_pointer_full,
err_read_pointer_increment => err_read_pointer_increment, err_read_pointer_not_increment => err_read_pointer_not_increment,
err_write_en => err_write_en, err_not_write_en => err_not_write_en, err_not_write_en1 => err_not_write_en1,
err_not_write_en2 => err_not_write_en2, err_read_en_mismatch => err_read_en_mismatch,
err_read_en_mismatch1 => err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
-- Becuase of checkers we did this
fault_info <= fault_info_sig; -- Not sure yet ?!
health_info <= health_info_sig; -- Not sure yet ?!
-- Sequential part
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
FIFO_MEM_1 <= (others=>'0'); FIFO_MEM_2 <= (others=>'0'); FIFO_MEM_3 <= (others=>'0'); FIFO_MEM_4 <= (others=>'0');
fake_credit_counter <= (others=>'0');
faulty_packet_out <= '0';
credit_out <= '0';
state_out <= Idle;
fault_info_out <= '0';
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
state_out <= state_in;
faulty_packet_out <= faulty_packet_in;
credit_out <= credit_in;
fake_credit_counter <= fake_credit_counter_in;
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in; FIFO_MEM_2 <= FIFO_MEM_2_in; FIFO_MEM_3 <= FIFO_MEM_3_in; FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
fault_info_out <= fault_info_in;
end if;
end process;
-- Anything below here is pure combinational
-- combinatorial part
fault_info_sig <= fault_info_out;
process(fake_credit, read_en, fake_credit_counter) begin
fake_credit_counter_in <= fake_credit_counter;
credit_in <= '0';
if fake_credit = '1' and read_en = '1' then
fake_credit_counter_in <= fake_credit_counter + 1 ;
end if;
if fake_credit = '1' or read_en ='1' then
credit_in <= '1';
end if;
if fake_credit = '0' and read_en = '0' and fake_credit_counter > 0 then
fake_credit_counter_in <= fake_credit_counter - 1 ;
credit_in <= '1';
end if;
end process;
process(valid_in, RX) begin
xor_all <= '0';
if valid_in = '1' then
xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
end if;
end process;
process(valid_in, RX, xor_all)begin
fault_out <= '0';
if valid_in = '1' and xor_all /= RX(0) then
fault_out <= '1';
end if;
end process;
process(RX, faulty_packet_out, fault_out, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4, state_out, valid_in) begin
-- this is the default value of the memory!
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
end case ;
--some defaults
fault_info_in <= '0';
health_info_sig <= '0';
fake_credit <= '0';
state_in <= state_out;
faulty_packet_in <= faulty_packet_out;
write_fake_flit <= '0';
case(state_out) is
when Idle =>
if fault_out = '0' then
if valid_in = '1' then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
when Header_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
state_in <= Body_flit;
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" then
state_in <= Tail_flit;
else
-- we should not be here!
state_in <= state_out;
end if;
else -- fault_out = '1'
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
end case ;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Body_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
state_in <= state_out;
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" then
state_in <= Tail_flit;
health_info_sig <= '1';
else
-- we should not be here!
state_in <= state_out;
end if;
else -- fault_out = '1'
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
end case ;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Tail_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else -- fault_out = '1'
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= Idle;
end if;
when Packet_drop =>
state_in <= state_out;
if faulty_packet_out = '1' then
report "FIFO dropping packet at" & time'image(now) &"!" severity note;
if valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" and fault_out = '0' then
faulty_packet_in <= '0';
state_in <= Header_flit;
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
end case ;
elsif valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" and fault_out = '0' then
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
faulty_packet_in <= '0';
state_in <= Idle;
fake_credit <= '1';
else -- fault_out might have been '1'
if valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" then
fault_info_in <= '1';
end if;
if valid_in = '1' then
fake_credit <= '1';
end if;
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= state_out;
end if;
end if;
when others => state_in <= state_out;
end case;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when others => Data_out <= FIFO_MEM_4;
end case ;
end process;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
process(write_en, write_pointer)begin
write_pointer_in <= write_pointer;
if write_en = '1' then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
end if;
end process;
process(read_en, empty, read_pointer)begin
read_pointer_in <= read_pointer;
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
end if;
end process;
process(full, valid_in, write_fake_flit, faulty_packet_out, fault_out) begin
write_en <= '0';
if valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full ='0' then
write_en <= '1';
end if;
end process;
process(write_pointer, read_pointer) begin
empty <= '0';
full <= '0';
if read_pointer = write_pointer then
empty <= '1';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
end if;
end process;
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.component_pack.all;
entity FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic;
-- fault injector shift register with serial input signals
TCK: in std_logic;
SE: in std_logic; -- shift enable
UE: in std_logic; -- update enable
SI: in std_logic; -- serial Input
SO: out std_logic; -- serial output
-- Checker outputs
-- Functional checkers
err_empty_full, err_empty_read_en, err_full_write_en, err_state_in_onehot,
err_read_pointer_in_onehot, err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer, err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full,
err_read_pointer_increment, err_read_pointer_not_increment, err_write_en, err_not_write_en, err_not_write_en1,
err_not_write_en2, err_read_en_mismatch, err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in : out std_logic
);
end FIFO_credit_based;
architecture behavior of FIFO_credit_based is
----------------------------------------
-- Signals related to fault injection --
----------------------------------------
-- Total: 8 bits
signal FI_add_sta: std_logic_vector(7 downto 0); -- 6 bits for fault injection location address (ceil of log2(44) = 6)
-- 2 bits for type of fault (SA0 or SA1)
signal non_faulty_signals: std_logic_vector (43 downto 0); -- 44 bits for internal- and output-related signals (non-faulty)
signal faulty_signals: std_logic_vector(43 downto 0); -- 44 bits for internal- and output-related signals (with single stuck-at fault injected in one of them)
----------------------------------------
----------------------------------------
signal read_pointer, read_pointer_in, write_pointer, write_pointer_in: std_logic_vector(3 downto 0);
signal full, empty: std_logic;
signal read_en, write_en: std_logic;
signal FIFO_MEM_1, FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_2, FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_3, FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0);
signal FIFO_MEM_4, FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0);
-- Packet Dropping FSM states encoded as one-hot (because of checkers for one-bit error detection)
CONSTANT Idle: std_logic_vector (4 downto 0) := "00001";
CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010";
CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100";
CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000";
CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000";
signal fault_info_in, fault_info_out: std_logic;
signal faulty_packet_in, faulty_packet_out: std_logic;
signal xor_all, fault_out: std_logic;
signal state_out, state_in : std_logic_vector(4 downto 0); -- : state_type;
signal fake_credit, credit_in, write_fake_flit: std_logic;
signal fake_credit_counter, fake_credit_counter_in: std_logic_vector(1 downto 0);
-- Signal(s) needed for FIFO control part checkers
signal fault_info_sig, health_info_sig : std_logic;
-- Signal(s) used for creating the chain of injected fault locations (Control Part of FIFO only)
-- Total: 44 bits ??!!
-- FIFO's control part internal-related signals
signal read_pointer_faulty, read_pointer_in_faulty : std_logic_vector(3 downto 0);
signal write_pointer_faulty, write_pointer_in_faulty : std_logic_vector(3 downto 0);
signal full_faulty, read_en_faulty, write_en_faulty : std_logic;
signal fake_credit_faulty : std_logic;
signal fake_credit_counter_faulty, fake_credit_counter_in_faulty : std_logic_vector(1 downto 0);
signal state_out_faulty, state_in_faulty : std_logic_vector (4 downto 0);
signal fault_info_out_faulty, fault_info_in_faulty : std_logic;
signal faulty_packet_out_faulty, faulty_packet_in_faulty : std_logic;
--signal flit_type_faulty : std_logic; -- ??!! (Actually, flit_type is an alias, showing RX from bits 31 downto 29, maybe we can define it as a signal for injection) (Not sure yet !)
signal fault_out_faulty, write_fake_flit_faulty : std_logic;
-- FIFO's control part output-related signals
signal credit_in_faulty : std_logic; -- ??!! (Actually, it is credit_in, which is the previous value of credit_out in FIFO)
signal empty_faulty : std_logic;
signal fault_info_sig_faulty : std_logic; -- ??!! (which goes to the fault_info output of FIFO)
signal health_info_sig_faulty : std_logic; -- ??!! (which goes to the health_info output of FIFO)
begin
--------------------------------------------------------------------------------------------
-- block diagram of the FIFO!
--------------------------------------------------------------------------------------------
-- circular buffer structure
-- <--- WriteP
-- ---------------------------------
-- | 3 | 2 | 1 | 0 |
-- ---------------------------------
-- <--- readP
--------------------------------------------------------------------------------------------
-- Packet drop state machine
-- +---+ No +---+ No
-- | | Flit | | Flit
-- | v | v
-- healthy +--------+ +--------+
-- +---header-->| | | |-------------------+
-- | +->| Header |---Healthy body-->| Body |------------+ |
-- | | +--------+ +--------+ | |
-- | | | ^ | Healthy | ^ Healthy |
-- | | | | | body | | Tail |
-- | | | | | +---+ | |
-- | | | | | v |
-- +--------+ | | | | +--------+ |
-- No +-->| | | | | +-----------------Healthy Tail------>| | |
-- Flit| | IDLE | | | | | Tail |--)--+
-- +---| | | | +-----------Healthy Header--------------| | | |
-- +--------+ | | +--------+ | |
-- ^ | ^ | Faulty No Faulty | |
-- | | | | Flit Flit Flit | |
-- | | | | +------------+ +---+ +---+ | |
-- | | | + --Healthy------+ | | | | | | |
-- | | | header | v | v | v | |
-- | | | +------------------+ | |
-- | | +----Healthy Tail-----| Packet | | |
-- | +-------Faulty Flit----->| Drop |<-----------------------+ |
-- | +------------------+ |
-- +-------------------------------------------------No Flit------------------+
--
------------------------------------------------------------------------------------------------
-------------------------------------
---- Related to fault injection -----
-------------------------------------
-- Total: 44 bits
-- Still not sure whether to include flit_type or not ??!!
-- credit_in is actually the previous value of credit_out in FIFO !!
-- for fault_info and health_info outputs, not sure whether to include them or the signals with _sig suffix in their names ??!!
non_faulty_signals <= read_pointer & read_pointer_in & write_pointer & write_pointer_in & full & read_en &
write_en & fake_credit & fake_credit_counter & fake_credit_counter_in & state_out &
state_in & fault_info_out & fault_info_in & faulty_packet_out & faulty_packet_in &
fault_out & write_fake_flit & credit_in & empty & fault_info_sig & health_info_sig;
-- Fault injector module instantiation
FI: fault_injector generic map(DATA_WIDTH => 44, ADDRESS_WIDTH => 6)
port map (data_in=> non_faulty_signals , address => FI_add_sta(7 downto 2), sta_0=> FI_add_sta(1), sta_1=> FI_add_sta(0), data_out=> faulty_signals
);
-- Extracting faulty values for internal- and output-related signals
-- Total: 44 bits
read_pointer_faulty <= faulty_signals (43 downto 40);
read_pointer_in_faulty <= faulty_signals (39 downto 36);
write_pointer_faulty <= faulty_signals (35 downto 32);
write_pointer_in_faulty <= faulty_signals (31 downto 28);
full_faulty <= faulty_signals (27);
read_en_faulty <= faulty_signals (26);
write_en_faulty <= faulty_signals (25);
fake_credit_faulty <= faulty_signals (24);
fake_credit_counter_faulty <= faulty_signals (23 downto 22);
fake_credit_counter_in_faulty <= faulty_signals (21 downto 20);
state_out_faulty <= faulty_signals (19 downto 15);
state_in_faulty <= faulty_signals (14 downto 10);
fault_info_out_faulty <= faulty_signals (9);
fault_info_in_faulty <= faulty_signals (8);
faulty_packet_out_faulty <= faulty_signals (7);
faulty_packet_in_faulty <= faulty_signals (6);
fault_out_faulty <= faulty_signals (5);
write_fake_flit_faulty <= faulty_signals (4);
credit_in_faulty <= faulty_signals (3);
empty_faulty <= faulty_signals (2);
fault_info_sig_faulty <= faulty_signals (1);
health_info_sig_faulty <= faulty_signals (0);
-- Total: 8 bits
-- We only use the shift register with serial in for :
-- (1) feeding the values of address width
-- (the address where the single stuck-at fault should be injected)
-- (2) feeding the values of the type of fault (stuck-at-1 (SA1) or stuck-at-0 (SA0) or no fault)
SR: shift_register_serial_in generic map(REG_WIDTH => 8)
port map ( TCK=> TCK, reset=>reset, SE=> SE, UE=> UE, SI=> SI, SO=> SO, data_out_parallel=> FI_add_sta
);
-------------------------------------
-------------------------------------
-- FIFO control part with packet drop and fault classifier support checkers instantiation
FIFO_control_part_checkers:
FIFO_credit_based_control_part_checkers
port map (
valid_in => valid_in,
read_en_N => read_en_N, read_en_E => read_en_E, read_en_W => read_en_W, read_en_S => read_en_S, read_en_L => read_en_L,
read_pointer => read_pointer_faulty, read_pointer_in => read_pointer_in_faulty,
write_pointer => write_pointer_faulty, write_pointer_in => write_pointer_in_faulty,
credit_out => credit_in_faulty, -- correct ?! (credit_in in FIFO is actually the previous value of credit_out, going to the input of a register)
empty_out => empty_faulty, full_out => full_faulty, read_en_out => read_en_faulty, write_en_out => write_en_faulty,
fake_credit => fake_credit_faulty, fake_credit_counter => fake_credit_counter_faulty,
fake_credit_counter_in => fake_credit_counter_in_faulty, state_out => state_out_faulty, state_in => state_in_faulty,
fault_info => fault_info_sig_faulty, -- connected to signal
fault_info_out => fault_info_out_faulty, fault_info_in => fault_info_in_faulty,
health_info => health_info_sig_faulty, -- connected to signal
faulty_packet_out => faulty_packet_out_faulty, faulty_packet_in => faulty_packet_in_faulty,
flit_type => RX(DATA_WIDTH-1 downto DATA_WIDTH-3), -- Behrad: Not sure about this yet ?!
fault_out => fault_out_faulty, write_fake_flit => write_fake_flit_faulty,
-- Functional checkers
err_empty_full => err_empty_full, err_empty_read_en => err_empty_read_en, err_full_write_en => err_full_write_en,
err_state_in_onehot => err_state_in_onehot, err_read_pointer_in_onehot => err_read_pointer_in_onehot,
err_write_pointer_in_onehot => err_write_pointer_in_onehot,
-- Structural checkers
err_write_en_write_pointer => err_write_en_write_pointer, err_not_write_en_write_pointer => err_not_write_en_write_pointer,
err_read_pointer_write_pointer_not_empty => err_read_pointer_write_pointer_not_empty,
err_read_pointer_write_pointer_empty => err_read_pointer_write_pointer_empty,
err_read_pointer_write_pointer_not_full => err_read_pointer_write_pointer_not_full,
err_read_pointer_write_pointer_full => err_read_pointer_write_pointer_full,
err_read_pointer_increment => err_read_pointer_increment, err_read_pointer_not_increment => err_read_pointer_not_increment,
err_write_en => err_write_en, err_not_write_en => err_not_write_en, err_not_write_en1 => err_not_write_en1,
err_not_write_en2 => err_not_write_en2, err_read_en_mismatch => err_read_en_mismatch,
err_read_en_mismatch1 => err_read_en_mismatch1,
-- Newly added checkers for FIFO with packet drop and fault classifier support!
err_fake_credit_read_en_fake_credit_counter_in_increment => err_fake_credit_read_en_fake_credit_counter_in_increment,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement => err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement,
err_not_fake_credit_read_en_fake_credit_counter_in_not_change => err_not_fake_credit_read_en_fake_credit_counter_in_not_change,
err_fake_credit_not_read_en_fake_credit_counter_in_not_change => err_fake_credit_not_read_en_fake_credit_counter_in_not_change,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change => err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change,
err_fake_credit_read_en_credit_out => err_fake_credit_read_en_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out => err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out,
err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out => err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out,
-- Checkers for Packet Dropping FSM of FIFO
err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit => err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit,
err_state_out_Idle_not_fault_out_valid_in_state_in_not_change => err_state_out_Idle_not_fault_out_valid_in_state_in_not_change,
err_state_out_Idle_not_fault_out_not_fake_credit => err_state_out_Idle_not_fault_out_not_fake_credit,
err_state_out_Idle_not_fault_out_not_fault_info_in => err_state_out_Idle_not_fault_out_not_fault_info_in,
err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal => err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Idle_fault_out_fake_credit => err_state_out_Idle_fault_out_fake_credit,
err_state_out_Idle_fault_out_state_in_Packet_drop => err_state_out_Idle_fault_out_state_in_Packet_drop,
err_state_out_Idle_fault_out_fault_info_in => err_state_out_Idle_fault_out_fault_info_in,
err_state_out_Idle_fault_out_faulty_packet_in => err_state_out_Idle_fault_out_faulty_packet_in,
err_state_out_Idle_not_health_info => err_state_out_Idle_not_health_info,
err_state_out_Idle_not_write_fake_flit => err_state_out_Idle_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit,
err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit => err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit => err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in => err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_valid_in_fault_out_write_fake_flit => err_state_out_Header_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Header_flit_valid_in_fault_out_fault_info_in => err_state_out_Header_flit_valid_in_fault_out_fault_info_in,
err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change => err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Header_flit_not_valid_in_not_fault_info_in => err_state_out_Header_flit_not_valid_in_not_fault_info_in,
err_state_out_Header_flit_not_valid_in_not_write_fake_flit => err_state_out_Header_flit_not_valid_in_not_write_fake_flit,
err_state_out_Header_flit_or_Body_flit_not_fake_credit => err_state_out_Header_flit_or_Body_flit_not_fake_credit,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change,
err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit => err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit,
err_state_out_Body_flit_valid_in_not_fault_out_health_info => err_state_out_Body_flit_valid_in_not_fault_out_health_info,
err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit => err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit,
err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in => err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_valid_in_fault_out_write_fake_flit => err_state_out_Body_flit_valid_in_fault_out_write_fake_flit,
err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Body_flit_valid_in_fault_out_fault_info_in => err_state_out_Body_flit_valid_in_fault_out_fault_info_in,
err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change => err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change,
err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Body_flit_not_valid_in_not_fault_info_in => err_state_out_Body_flit_not_valid_in_not_fault_info_in,
err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info => err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info,
err_state_out_Body_flit_valid_in_fault_out_not_health_info => err_state_out_Body_flit_valid_in_fault_out_not_health_info,
err_state_out_Body_flit_valid_in_not_health_info => err_state_out_Body_flit_valid_in_not_health_info,
err_state_out_Body_flit_not_fake_credit => err_state_out_Body_flit_not_fake_credit,
err_state_out_Body_flit_not_valid_in_not_write_fake_flit => err_state_out_Body_flit_not_valid_in_not_write_fake_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit => err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit => err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit,
err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in => err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in,
err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Tail_flit_valid_in_fault_out_fake_credit => err_state_out_Tail_flit_valid_in_fault_out_fake_credit,
err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop => err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop,
err_state_out_Tail_flit_valid_in_fault_out_fault_info_in => err_state_out_Tail_flit_valid_in_fault_out_fault_info_in,
err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in => err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in,
err_state_out_Tail_flit_not_valid_in_state_in_Idle => err_state_out_Tail_flit_not_valid_in_state_in_Idle,
err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change => err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change,
err_state_out_Tail_flit_not_valid_in_not_fault_info_in => err_state_out_Tail_flit_not_valid_in_not_fault_info_in,
err_state_out_Tail_flit_not_valid_in_not_fake_credit => err_state_out_Tail_flit_not_valid_in_not_fake_credit,
err_state_out_Tail_flit_not_write_fake_flit => err_state_out_Tail_flit_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit,
err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change => err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change => err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change,
err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit => err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit,
err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit => err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change,
err_fault_info_fault_info_out_equal => err_fault_info_fault_info_out_equal,
err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal => err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal,
err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal => err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal,
err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in => err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in,
err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in => err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in
);
-- Becuase of checkers we did this
fault_info <= fault_info_sig; -- Not sure yet ?!
health_info <= health_info_sig; -- Not sure yet ?!
-- Sequential part
process (clk, reset)begin
if reset = '0' then
read_pointer <= "0001";
write_pointer <= "0001";
FIFO_MEM_1 <= (others=>'0'); FIFO_MEM_2 <= (others=>'0'); FIFO_MEM_3 <= (others=>'0'); FIFO_MEM_4 <= (others=>'0');
fake_credit_counter <= (others=>'0');
faulty_packet_out <= '0';
credit_out <= '0';
state_out <= Idle;
fault_info_out <= '0';
elsif clk'event and clk = '1' then
write_pointer <= write_pointer_in;
read_pointer <= read_pointer_in;
state_out <= state_in;
faulty_packet_out <= faulty_packet_in;
credit_out <= credit_in;
fake_credit_counter <= fake_credit_counter_in;
if write_en = '1' then
--write into the memory
FIFO_MEM_1 <= FIFO_MEM_1_in; FIFO_MEM_2 <= FIFO_MEM_2_in; FIFO_MEM_3 <= FIFO_MEM_3_in; FIFO_MEM_4 <= FIFO_MEM_4_in;
end if;
fault_info_out <= fault_info_in;
end if;
end process;
-- Anything below here is pure combinational
-- combinatorial part
fault_info_sig <= fault_info_out;
process(fake_credit, read_en, fake_credit_counter) begin
fake_credit_counter_in <= fake_credit_counter;
credit_in <= '0';
if fake_credit = '1' and read_en = '1' then
fake_credit_counter_in <= fake_credit_counter + 1 ;
end if;
if fake_credit = '1' or read_en ='1' then
credit_in <= '1';
end if;
if fake_credit = '0' and read_en = '0' and fake_credit_counter > 0 then
fake_credit_counter_in <= fake_credit_counter - 1 ;
credit_in <= '1';
end if;
end process;
process(valid_in, RX) begin
xor_all <= '0';
if valid_in = '1' then
xor_all <= XOR_REDUCE(RX(DATA_WIDTH-1 downto 1));
end if;
end process;
process(valid_in, RX, xor_all)begin
fault_out <= '0';
if valid_in = '1' and xor_all /= RX(0) then
fault_out <= '1';
end if;
end process;
process(RX, faulty_packet_out, fault_out, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4, state_out, valid_in) begin
-- this is the default value of the memory!
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
end case ;
--some defaults
fault_info_in <= '0';
health_info_sig <= '0';
fake_credit <= '0';
state_in <= state_out;
faulty_packet_in <= faulty_packet_out;
write_fake_flit <= '0';
case(state_out) is
when Idle =>
if fault_out = '0' then
if valid_in = '1' then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
when Header_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
state_in <= Body_flit;
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" then
state_in <= Tail_flit;
else
-- we should not be here!
state_in <= state_out;
end if;
else -- fault_out = '1'
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
end case ;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Body_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "010" then
state_in <= state_out;
elsif RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" then
state_in <= Tail_flit;
health_info_sig <= '1';
else
-- we should not be here!
state_in <= state_out;
end if;
else -- fault_out = '1'
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= fake_tail; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= fake_tail; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= fake_tail; FIFO_MEM_4_in <= FIFO_MEM_4;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= fake_tail;
end case ;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= state_out;
end if;
when Tail_flit =>
if valid_in = '1' then
if fault_out = '0' then
if RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" then
state_in <= Header_flit;
else
state_in <= state_out;
end if;
else -- fault_out = '1'
fake_credit <= '1';
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= Packet_drop;
fault_info_in <= '1';
faulty_packet_in <= '1';
end if;
else
state_in <= Idle;
end if;
when Packet_drop =>
state_in <= state_out;
if faulty_packet_out = '1' then
report "FIFO dropping packet at" & time'image(now) &"!" severity note;
if valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" and fault_out = '0' then
faulty_packet_in <= '0';
state_in <= Header_flit;
write_fake_flit <= '1';
case( write_pointer ) is
when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4;
when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX;
end case ;
elsif valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "100" and fault_out = '0' then
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
faulty_packet_in <= '0';
state_in <= Idle;
fake_credit <= '1';
else -- fault_out might have been '1'
if valid_in = '1' and RX(DATA_WIDTH-1 downto DATA_WIDTH-3) = "001" then
fault_info_in <= '1';
end if;
if valid_in = '1' then
fake_credit <= '1';
end if;
FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4;
state_in <= state_out;
end if;
end if;
when others => state_in <= state_out;
end case;
end process;
process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin
case( read_pointer ) is
when "0001" => Data_out <= FIFO_MEM_1;
when "0010" => Data_out <= FIFO_MEM_2;
when "0100" => Data_out <= FIFO_MEM_3;
when others => Data_out <= FIFO_MEM_4;
end case ;
end process;
read_en <= (read_en_N or read_en_E or read_en_W or read_en_S or read_en_L) and not empty;
empty_out <= empty;
process(write_en, write_pointer)begin
write_pointer_in <= write_pointer;
if write_en = '1' then
write_pointer_in <= write_pointer(2 downto 0)&write_pointer(3);
end if;
end process;
process(read_en, empty, read_pointer)begin
read_pointer_in <= read_pointer;
if (read_en = '1' and empty = '0') then
read_pointer_in <= read_pointer(2 downto 0)&read_pointer(3);
end if;
end process;
process(full, valid_in, write_fake_flit, faulty_packet_out, fault_out) begin
write_en <= '0';
if valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full ='0' then
write_en <= '1';
end if;
end process;
process(write_pointer, read_pointer) begin
empty <= '0';
full <= '0';
if read_pointer = write_pointer then
empty <= '1';
end if;
-- if write_pointer = read_pointer>>1 then
if write_pointer = read_pointer(0)&read_pointer(3 downto 1) then
full <= '1';
end if;
end process;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc795.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b03x00p03n01i00795ent IS
begin
generic ( constant const : boolean );
END c01s01b03x00p03n01i00795ent;
ARCHITECTURE c01s01b03x00p03n01i00795arch OF c01s01b03x00p03n01i00795ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b03x00p03n01i00795 - Generic clause is not permitted as an entity statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b03x00p03n01i00795arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc795.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b03x00p03n01i00795ent IS
begin
generic ( constant const : boolean );
END c01s01b03x00p03n01i00795ent;
ARCHITECTURE c01s01b03x00p03n01i00795arch OF c01s01b03x00p03n01i00795ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b03x00p03n01i00795 - Generic clause is not permitted as an entity statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b03x00p03n01i00795arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc795.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b03x00p03n01i00795ent IS
begin
generic ( constant const : boolean );
END c01s01b03x00p03n01i00795ent;
ARCHITECTURE c01s01b03x00p03n01i00795arch OF c01s01b03x00p03n01i00795ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b03x00p03n01i00795 - Generic clause is not permitted as an entity statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b03x00p03n01i00795arch;
|
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`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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nn1KsP+d6mOICOlOOfU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5488)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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MjHCSqbAug==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5488)
`protect data_block
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`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity struct_in is
generic (
ADDR_X : natural range 0 to 3 := 0;
ADDR_Y : natural range 0 to 3 := 0;
N_INST : boolean := true;
S_INST : boolean := true;
E_INST : boolean := true;
W_INST : boolean := true
);
port (
CLOCK : in std_logic;
RESET : in std_logic;
-- local
L_DIN : in std_logic_vector(31 downto 0);
L_VIN : in std_logic;
L_RIN : out std_logic;
L_DOUT : out std_logic_vector(31 downto 0);
L_VOUT : out std_logic;
L_ROUT : in std_logic;
L_SZ : out std_logic_vector(15 downto 0);
L_DIR : out std_logic_vector(4 downto 0); --LNSEW
-- north
N_DIN : in std_logic_vector(31 downto 0);
N_VIN : in std_logic;
N_RIN : out std_logic;
N_DOUT : out std_logic_vector(31 downto 0);
N_VOUT : out std_logic;
N_ROUT : in std_logic;
N_SZ : out std_logic_vector(15 downto 0);
N_DIR : out std_logic_vector(4 downto 0);
-- south
S_DIN : in std_logic_vector(31 downto 0);
S_VIN : in std_logic;
S_RIN : out std_logic;
S_DOUT : out std_logic_vector(31 downto 0);
S_VOUT : out std_logic;
S_ROUT : in std_logic;
S_SZ : out std_logic_vector(15 downto 0);
S_DIR : out std_logic_vector(4 downto 0);
-- east
E_DIN : in std_logic_vector(31 downto 0);
E_VIN : in std_logic;
E_RIN : out std_logic;
E_DOUT : out std_logic_vector(31 downto 0);
E_VOUT : out std_logic;
E_ROUT : in std_logic;
E_SZ : out std_logic_vector(15 downto 0);
E_DIR : out std_logic_vector(4 downto 0);
-- west
W_DIN : in std_logic_vector(31 downto 0);
W_VIN : in std_logic;
W_RIN : out std_logic;
W_DOUT : out std_logic_vector(31 downto 0);
W_VOUT : out std_logic;
W_ROUT : in std_logic;
W_SZ : out std_logic_vector(15 downto 0);
W_DIR : out std_logic_vector(4 downto 0)
);
end entity;
architecture structure of struct_in is
component fifo_in is
port (
CLOCK : in std_logic;
RESET : in std_logic;
DIN : in std_logic_vector(31 downto 0);
VIN : in std_logic;
RIN : out std_logic;
DOUT : out std_logic_vector(31 downto 0);
VOUT : out std_logic;
ROUT : in std_logic;
AX : out std_logic_vector(1 downto 0);
AY : out std_logic_vector(1 downto 0);
SZ : out std_logic_vector(15 downto 0);
HVAL : out std_logic
);
end component;
signal l_hval : std_logic;
signal n_hval : std_logic;
signal s_hval : std_logic;
signal e_hval : std_logic;
signal w_hval : std_logic;
signal l_ax : std_logic_vector(1 downto 0);
signal n_ax : std_logic_vector(1 downto 0);
signal s_ax : std_logic_vector(1 downto 0);
signal e_ax : std_logic_vector(1 downto 0);
signal w_ax : std_logic_vector(1 downto 0);
signal l_ay : std_logic_vector(1 downto 0);
signal n_ay : std_logic_vector(1 downto 0);
signal s_ay : std_logic_vector(1 downto 0);
signal e_ay : std_logic_vector(1 downto 0);
signal w_ay : std_logic_vector(1 downto 0);
begin
-- local
L_fifo: fifo_in
port map (
CLOCK => CLOCK,
RESET => RESET,
DIN => L_DIN,
VIN => L_VIN,
RIN => L_RIN,
DOUT => L_DOUT,
VOUT => L_VOUT,
ROUT => L_ROUT,
AX => l_ax,
AY => l_ay,
SZ => L_SZ,
HVAL => l_hval
);
-- north
N_fifo_gen: if N_INST = true generate
N_fifo: fifo_in
port map (
CLOCK => CLOCK,
RESET => RESET,
DIN => N_DIN,
VIN => N_VIN,
RIN => N_RIN,
DOUT => N_DOUT,
VOUT => N_VOUT,
ROUT => N_ROUT,
AX => n_ax,
AY => n_ay,
SZ => N_SZ,
HVAL => n_hval
);
end generate;
N_fifo_ngen: if N_INST = false generate
n_hval <= '0';
end generate;
-- south
S_fifo_gen: if S_INST = true generate
S_fifo: fifo_in
port map (
CLOCK => CLOCK,
RESET => RESET,
DIN => S_DIN,
VIN => S_VIN,
RIN => S_RIN,
DOUT => S_DOUT,
VOUT => S_VOUT,
ROUT => S_ROUT,
AX => s_ax,
AY => s_ay,
SZ => S_SZ,
HVAL => s_hval
);
end generate;
S_fifo_ngen: if S_INST = false generate
s_hval <= '0';
end generate;
-- east
E_fifo_gen: if E_INST = true generate
E_fifo: fifo_in
port map (
CLOCK => CLOCK,
RESET => RESET,
DIN => E_DIN,
VIN => E_VIN,
RIN => E_RIN,
DOUT => E_DOUT,
VOUT => E_VOUT,
ROUT => E_ROUT,
AX => e_ax,
AY => e_ay,
SZ => E_SZ,
HVAL => e_hval
);
end generate;
E_fifo_ngen: if E_INST = false generate
e_hval <= '0';
end generate;
-- west
W_fifo_gen: if W_INST = true generate
W_fifo: fifo_in
port map (
CLOCK => CLOCK,
RESET => RESET,
DIN => W_DIN,
VIN => W_VIN,
RIN => W_RIN,
DOUT => W_DOUT,
VOUT => W_VOUT,
ROUT => W_ROUT,
AX => w_ax,
AY => w_ay,
SZ => W_SZ,
HVAL => w_hval
);
end generate;
W_fifo_ngen: if W_INST = false generate
w_hval <= '0';
end generate;
process (
l_ax, l_ay, l_hval,
n_ax, n_ay, n_hval,
s_ax, s_ay, s_hval,
e_ax, e_ay, e_hval,
w_ax, w_ay, w_hval
)
begin
L_DIR <= (others => '0');
N_DIR <= (others => '0');
S_DIR <= (others => '0');
E_DIR <= (others => '0');
W_DIR <= (others => '0');
-- local
if l_hval = '1' then
if unsigned(l_ax) < ADDR_X then
L_DIR <= "00001"; --send west (left)
elsif unsigned(l_ax) > ADDR_X then
L_DIR <= "00010"; --send east (right)
else
if unsigned(l_ay) < ADDR_Y then
L_DIR <= "00100"; --send south (down)
elsif unsigned(l_ay) > ADDR_Y then
L_DIR <= "01000"; --send north (up)
else
L_DIR <= "10000"; --send local
end if;
end if;
end if;
-- north
if n_hval = '1' then
if unsigned(n_ax) < ADDR_X then
N_DIR <= "00001"; --send west (left)
elsif unsigned(n_ax) > ADDR_X then
N_DIR <= "00010"; --send east (right)
else
if unsigned(n_ay) < ADDR_Y then
N_DIR <= "00100"; --send south (down)
elsif unsigned(n_ay) > ADDR_Y then
N_DIR <= "01000"; --send north (up)
else
N_DIR <= "10000"; --send local
end if;
end if;
end if;
-- south
if s_hval = '1' then
if unsigned(s_ax) < ADDR_X then
S_DIR <= "00001"; --send west (left)
elsif unsigned(s_ax) > ADDR_X then
S_DIR <= "00010"; --send east (right)
else
if unsigned(s_ay) < ADDR_Y then
S_DIR <= "00100"; --send south (down)
elsif unsigned(s_ay) > ADDR_Y then
S_DIR <= "01000"; --send north (up)
else
S_DIR <= "10000"; --send local
end if;
end if;
end if;
-- east
if e_hval = '1' then
if unsigned(e_ax) < ADDR_X then
E_DIR <= "00001"; --send west (left)
elsif unsigned(e_ax) > ADDR_X then
E_DIR <= "00010"; --send east (right)
else
if unsigned(e_ay) < ADDR_Y then
E_DIR <= "00100"; --send south (down)
elsif unsigned(e_ay) > ADDR_Y then
E_DIR <= "01000"; --send north (up)
else
E_DIR <= "10000"; --send local
end if;
end if;
end if;
-- west
if w_hval = '1' then
if unsigned(w_ax) < ADDR_X then
W_DIR <= "00001"; --send west (left)
elsif unsigned(w_ax) > ADDR_X then
W_DIR <= "00010"; --send east (right)
else
if unsigned(w_ay) < ADDR_Y then
W_DIR <= "00100"; --send south (down)
elsif unsigned(w_ay) > ADDR_Y then
W_DIR <= "01000"; --send north (up)
else
W_DIR <= "10000"; --send local
end if;
end if;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity struct_in is
generic (
ADDR_X : natural range 0 to 3 := 0;
ADDR_Y : natural range 0 to 3 := 0;
N_INST : boolean := true;
S_INST : boolean := true;
E_INST : boolean := true;
W_INST : boolean := true
);
port (
CLOCK : in std_logic;
RESET : in std_logic;
-- local
L_DIN : in std_logic_vector(31 downto 0);
L_VIN : in std_logic;
L_RIN : out std_logic;
L_DOUT : out std_logic_vector(31 downto 0);
L_VOUT : out std_logic;
L_ROUT : in std_logic;
L_SZ : out std_logic_vector(15 downto 0);
L_DIR : out std_logic_vector(4 downto 0); --LNSEW
-- north
N_DIN : in std_logic_vector(31 downto 0);
N_VIN : in std_logic;
N_RIN : out std_logic;
N_DOUT : out std_logic_vector(31 downto 0);
N_VOUT : out std_logic;
N_ROUT : in std_logic;
N_SZ : out std_logic_vector(15 downto 0);
N_DIR : out std_logic_vector(4 downto 0);
-- south
S_DIN : in std_logic_vector(31 downto 0);
S_VIN : in std_logic;
S_RIN : out std_logic;
S_DOUT : out std_logic_vector(31 downto 0);
S_VOUT : out std_logic;
S_ROUT : in std_logic;
S_SZ : out std_logic_vector(15 downto 0);
S_DIR : out std_logic_vector(4 downto 0);
-- east
E_DIN : in std_logic_vector(31 downto 0);
E_VIN : in std_logic;
E_RIN : out std_logic;
E_DOUT : out std_logic_vector(31 downto 0);
E_VOUT : out std_logic;
E_ROUT : in std_logic;
E_SZ : out std_logic_vector(15 downto 0);
E_DIR : out std_logic_vector(4 downto 0);
-- west
W_DIN : in std_logic_vector(31 downto 0);
W_VIN : in std_logic;
W_RIN : out std_logic;
W_DOUT : out std_logic_vector(31 downto 0);
W_VOUT : out std_logic;
W_ROUT : in std_logic;
W_SZ : out std_logic_vector(15 downto 0);
W_DIR : out std_logic_vector(4 downto 0)
);
end entity;
architecture structure of struct_in is
component fifo_in is
port (
CLOCK : in std_logic;
RESET : in std_logic;
DIN : in std_logic_vector(31 downto 0);
VIN : in std_logic;
RIN : out std_logic;
DOUT : out std_logic_vector(31 downto 0);
VOUT : out std_logic;
ROUT : in std_logic;
AX : out std_logic_vector(1 downto 0);
AY : out std_logic_vector(1 downto 0);
SZ : out std_logic_vector(15 downto 0);
HVAL : out std_logic
);
end component;
signal l_hval : std_logic;
signal n_hval : std_logic;
signal s_hval : std_logic;
signal e_hval : std_logic;
signal w_hval : std_logic;
signal l_ax : std_logic_vector(1 downto 0);
signal n_ax : std_logic_vector(1 downto 0);
signal s_ax : std_logic_vector(1 downto 0);
signal e_ax : std_logic_vector(1 downto 0);
signal w_ax : std_logic_vector(1 downto 0);
signal l_ay : std_logic_vector(1 downto 0);
signal n_ay : std_logic_vector(1 downto 0);
signal s_ay : std_logic_vector(1 downto 0);
signal e_ay : std_logic_vector(1 downto 0);
signal w_ay : std_logic_vector(1 downto 0);
begin
-- local
L_fifo: fifo_in
port map (
CLOCK => CLOCK,
RESET => RESET,
DIN => L_DIN,
VIN => L_VIN,
RIN => L_RIN,
DOUT => L_DOUT,
VOUT => L_VOUT,
ROUT => L_ROUT,
AX => l_ax,
AY => l_ay,
SZ => L_SZ,
HVAL => l_hval
);
-- north
N_fifo_gen: if N_INST = true generate
N_fifo: fifo_in
port map (
CLOCK => CLOCK,
RESET => RESET,
DIN => N_DIN,
VIN => N_VIN,
RIN => N_RIN,
DOUT => N_DOUT,
VOUT => N_VOUT,
ROUT => N_ROUT,
AX => n_ax,
AY => n_ay,
SZ => N_SZ,
HVAL => n_hval
);
end generate;
N_fifo_ngen: if N_INST = false generate
n_hval <= '0';
end generate;
-- south
S_fifo_gen: if S_INST = true generate
S_fifo: fifo_in
port map (
CLOCK => CLOCK,
RESET => RESET,
DIN => S_DIN,
VIN => S_VIN,
RIN => S_RIN,
DOUT => S_DOUT,
VOUT => S_VOUT,
ROUT => S_ROUT,
AX => s_ax,
AY => s_ay,
SZ => S_SZ,
HVAL => s_hval
);
end generate;
S_fifo_ngen: if S_INST = false generate
s_hval <= '0';
end generate;
-- east
E_fifo_gen: if E_INST = true generate
E_fifo: fifo_in
port map (
CLOCK => CLOCK,
RESET => RESET,
DIN => E_DIN,
VIN => E_VIN,
RIN => E_RIN,
DOUT => E_DOUT,
VOUT => E_VOUT,
ROUT => E_ROUT,
AX => e_ax,
AY => e_ay,
SZ => E_SZ,
HVAL => e_hval
);
end generate;
E_fifo_ngen: if E_INST = false generate
e_hval <= '0';
end generate;
-- west
W_fifo_gen: if W_INST = true generate
W_fifo: fifo_in
port map (
CLOCK => CLOCK,
RESET => RESET,
DIN => W_DIN,
VIN => W_VIN,
RIN => W_RIN,
DOUT => W_DOUT,
VOUT => W_VOUT,
ROUT => W_ROUT,
AX => w_ax,
AY => w_ay,
SZ => W_SZ,
HVAL => w_hval
);
end generate;
W_fifo_ngen: if W_INST = false generate
w_hval <= '0';
end generate;
process (
l_ax, l_ay, l_hval,
n_ax, n_ay, n_hval,
s_ax, s_ay, s_hval,
e_ax, e_ay, e_hval,
w_ax, w_ay, w_hval
)
begin
L_DIR <= (others => '0');
N_DIR <= (others => '0');
S_DIR <= (others => '0');
E_DIR <= (others => '0');
W_DIR <= (others => '0');
-- local
if l_hval = '1' then
if unsigned(l_ax) < ADDR_X then
L_DIR <= "00001"; --send west (left)
elsif unsigned(l_ax) > ADDR_X then
L_DIR <= "00010"; --send east (right)
else
if unsigned(l_ay) < ADDR_Y then
L_DIR <= "00100"; --send south (down)
elsif unsigned(l_ay) > ADDR_Y then
L_DIR <= "01000"; --send north (up)
else
L_DIR <= "10000"; --send local
end if;
end if;
end if;
-- north
if n_hval = '1' then
if unsigned(n_ax) < ADDR_X then
N_DIR <= "00001"; --send west (left)
elsif unsigned(n_ax) > ADDR_X then
N_DIR <= "00010"; --send east (right)
else
if unsigned(n_ay) < ADDR_Y then
N_DIR <= "00100"; --send south (down)
elsif unsigned(n_ay) > ADDR_Y then
N_DIR <= "01000"; --send north (up)
else
N_DIR <= "10000"; --send local
end if;
end if;
end if;
-- south
if s_hval = '1' then
if unsigned(s_ax) < ADDR_X then
S_DIR <= "00001"; --send west (left)
elsif unsigned(s_ax) > ADDR_X then
S_DIR <= "00010"; --send east (right)
else
if unsigned(s_ay) < ADDR_Y then
S_DIR <= "00100"; --send south (down)
elsif unsigned(s_ay) > ADDR_Y then
S_DIR <= "01000"; --send north (up)
else
S_DIR <= "10000"; --send local
end if;
end if;
end if;
-- east
if e_hval = '1' then
if unsigned(e_ax) < ADDR_X then
E_DIR <= "00001"; --send west (left)
elsif unsigned(e_ax) > ADDR_X then
E_DIR <= "00010"; --send east (right)
else
if unsigned(e_ay) < ADDR_Y then
E_DIR <= "00100"; --send south (down)
elsif unsigned(e_ay) > ADDR_Y then
E_DIR <= "01000"; --send north (up)
else
E_DIR <= "10000"; --send local
end if;
end if;
end if;
-- west
if w_hval = '1' then
if unsigned(w_ax) < ADDR_X then
W_DIR <= "00001"; --send west (left)
elsif unsigned(w_ax) > ADDR_X then
W_DIR <= "00010"; --send east (right)
else
if unsigned(w_ay) < ADDR_Y then
W_DIR <= "00100"; --send south (down)
elsif unsigned(w_ay) > ADDR_Y then
W_DIR <= "01000"; --send north (up)
else
W_DIR <= "10000"; --send local
end if;
end if;
end if;
end process;
end architecture;
|
architecture RTL of FIFO is
signal a, b, c, d : std_logic;
signal a,b,c,d : std_logic;
begin
process (a, b, c, d) is
begin
end process;
process (a,b,c,d) is
begin
end process;
process (a, b, c, d) is
begin
end process;
process (a, b,c
d, e, f) is
begin end process;
end architecture RTL;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity SEU is
Port ( imm13 : in STD_LOGIC_VECTOR (12 downto 0);
seuout : out STD_LOGIC_VECTOR (31 downto 0));
end SEU;
architecture Behavioral of SEU is
begin
process( imm13)
begin
if(imm13(12) = '1') then
seuout <= "1111111111111111111" & imm13;
else
seuout <= "0000000000000000000" & imm13;
end if;
end process;
end Behavioral;
|
entity test is
constant a : b :=
foo /= bar nand baz;
end;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package cpu_l1mem_data_types_pkg is
type cpu_l1mem_data_request_code_index_type is (
cpu_l1mem_data_request_code_index_none,
cpu_l1mem_data_request_code_index_load,
cpu_l1mem_data_request_code_index_store,
cpu_l1mem_data_request_code_index_invalidate,
cpu_l1mem_data_request_code_index_flush,
cpu_l1mem_data_request_code_index_writeback,
cpu_l1mem_data_request_code_index_sync
);
type cpu_l1mem_data_request_code_type is
array (cpu_l1mem_data_request_code_index_type range
cpu_l1mem_data_request_code_index_type'high downto
cpu_l1mem_data_request_code_index_type'low) of std_ulogic;
constant cpu_l1mem_data_request_code_none : cpu_l1mem_data_request_code_type := "0000001";
constant cpu_l1mem_data_request_code_load : cpu_l1mem_data_request_code_type := "0000010";
constant cpu_l1mem_data_request_code_store : cpu_l1mem_data_request_code_type := "0000100";
constant cpu_l1mem_data_request_code_invalidate : cpu_l1mem_data_request_code_type := "0001000";
constant cpu_l1mem_data_request_code_flush : cpu_l1mem_data_request_code_type := "0010000";
constant cpu_l1mem_data_request_code_writeback : cpu_l1mem_data_request_code_type := "0100000";
constant cpu_l1mem_data_request_code_sync : cpu_l1mem_data_request_code_type := "1000000";
type cpu_l1mem_data_result_code_index_type is (
cpu_l1mem_data_result_code_index_valid,
cpu_l1mem_data_result_code_index_error,
cpu_l1mem_data_result_code_index_tlbmiss,
cpu_l1mem_data_result_code_index_pf
);
type cpu_l1mem_data_result_code_type is
array (cpu_l1mem_data_result_code_index_type range
cpu_l1mem_data_result_code_index_type'high downto
cpu_l1mem_data_result_code_index_type'low) of std_ulogic;
constant cpu_l1mem_data_result_code_valid : cpu_l1mem_data_result_code_type := "0001";
constant cpu_l1mem_data_result_code_error : cpu_l1mem_data_result_code_type := "0010";
constant cpu_l1mem_data_result_code_tlbmiss : cpu_l1mem_data_result_code_type := "0100";
constant cpu_l1mem_data_result_code_pf : cpu_l1mem_data_result_code_type := "1000";
end package;
|
----------------------------------------------------------------------------------
-- Takes 12 bit input from ADC process and triggers a logic line based on the value
-- Intended to protect devices from an unsafe source (physically, protect fiber optic cable from bad alignment)
-- Runs with the clock rate of the ADC process to check ADC values and update logic accordingly
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Physical ports to the entity
entity ADC_INTERLOCK is
port (
iLOGIC_CLK : in std_logic; -- clock rate
iADC_data : in std_logic_vector(11 downto 0);
iCH_count : in std_logic_vector(2 downto 0);
iActive : in std_logic; -- toggles if we want the threshold trigger
oLED : out std_logic_vector(1 downto 0);
oLOGIC0 : out std_logic; -- '1' deactivates device
oLOGIC1 : out std_logic -- '1' deactivates device
);
end entity;
-- Behavioral
architecture rtl of ADC_INTERLOCK is
----------------------------------------------------------------------------------
-- SIGNALS
----------------------------------------------------------------------------------
signal LOGIC0 : std_logic := '1'; -- channel 0 value
signal LOGIC1 : std_logic := '1'; -- channel 1 value
signal led : std_logic_vector(1 downto 0); -- lights for each channel
-- threshold value, measured based on ADC values at 1/3
-- might need to be different for each channel
constant ADC_THRESHOLD : std_logic_vector(11 downto 0) := "010101010101";
----------------------------------------------------------------------------------
-- BEGIN
----------------------------------------------------------------------------------
begin
-- latch outputs, "high" deactivates the physical device
oLOGIC0 <= not(LOGIC0) when iActive = '1' else '0';
oLOGIC1 <= not(LOGIC1) when iActive = '1' else '0';
oLED <= led; -- LEDs follow logic levels
-- Interpret ADC data for logic levels
process(iLOGIC_CLK)
begin
if(rising_edge(iLOGIC_CLK)) then
-- update logic to be FALSE if the ADC data is below a threshold
if(iCH_count = "000") then
if(iADC_data < ADC_THRESHOLD) then
-- flip logic to FALSE
LOGIC0 <= '0';
led(0) <= '0';
else
LOGIC0 <= '1';
led(0) <= '1';
end if;
elsif(iCH_count = "001") then
if(iADC_data < ADC_THRESHOLD) then
-- flip logic to FALSE
LOGIC1 <= '0';
led(1) <= '0';
else
LOGIC1 <= '1';
led(1) <= '1';
end if;
end if;
end if;
end process;
end rtl; |
library ieee;
use ieee.std_logic_1164.all;
package pkg is
component cmask is
generic
(mask : std_logic_vector (0 to 7));
port (d : std_logic_vector (7 downto 0);
o : out std_logic_vector (7 downto 0));
end component;
end pkg;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex4;
constant CFG_MEMTECH : integer := virtex4;
constant CFG_PADTECH : integer := virtex4;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex4;
constant CFG_CLKMUL : integer := (13);
constant CFG_CLKDIV : integer := (20);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 0 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (1);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 1;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 1;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (64);
constant CFG_DDRSP_RSKEW : integer := (0);
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 0;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0FFFE#;
constant CFG_GRGPIO_WIDTH : integer := (14);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_b3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: viv 2014.4-2018.3; ghdl 0.31-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.4.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.4 use typ for DL,PC,LP; add dz11,ibtst
-- 2018-09-22 1050 1.3.7 add sys_conf_dmpcnt
-- 2018-09-08 1043 1.3.6 add sys_conf_ibd_kw11p
-- 2017-03-04 858 1.3.5 enable deuna
-- 2017-01-29 847 1.3.4 add sys_conf_ibd_deuna
-- 2016-06-18 775 1.3.3 use PLL for clkser_gentype
-- 2016-05-28 770 1.3.2 sys_conf_mem_losize now type natural
-- 2016-05-26 768 1.3.1 set dmscnt=0 (vivado fsm issue) (@80 MHz)
-- 2016-03-28 755 1.3 use serport_2clock2 -> define clkser (@75 MHz)
-- 2016-03-22 750 1.2 add sys_conf_cache_twidth
-- 2016-03-13 742 1.1.2 add sysmon_bus; use 72 MHz, no tc otherwise
-- 2015-06-26 695 1.1.1 add sys_conf_(dmscnt|dmhbpt*|dmcmon*)
-- 2015-03-14 658 1.1 add sys_conf_ibd_* definitions
-- 2015-02-08 644 1.0 Initial version (derived from _n4 version)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- configure memory controller ---------------------------------------------
constant sys_conf_memctl_mawidth : positive := 4;
constant sys_conf_memctl_nblock : positive := 11;
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs
constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs
constant sys_conf_ibtst : boolean := true;
constant sys_conf_dmscnt : boolean := false;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 0; -- no dmcmon to save BRAMs
constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC)
-- configure w11 cpu core --------------------------------------------------
-- sys_conf_mem_losize is highest 64 byte MMU block number
-- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks
constant sys_conf_mem_losize : natural := 256*sys_conf_memctl_nblock-1;
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
-- typ for DL,DZ,PC,LP: -1->none; 0->unbuffered; 4-7 buffered (typ=AWIDTH)
constant sys_conf_ibd_dl11_0 : integer := 6; -- 1st DL11
constant sys_conf_ibd_dl11_1 : integer := 6; -- 2nd DL11
constant sys_conf_ibd_dz11 : integer := 6; -- DZ11
constant sys_conf_ibd_pc11 : integer := 6; -- PC11
constant sys_conf_ibd_lp11 : integer := 7; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := true; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := true; -- M9312
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clkser/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
|
--------------------------------------------------------------------------------
-- Copyright (c) 2019 David Banks
--
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : Z80CpuMon.vhd
-- /___/ /\ Timestamp : 14/10/2018
-- \ \ / \
-- \___\/\___\
--
--Design Name: Z80CpuMon
--Device: multiple
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity Z80CpuMon is
generic (
ClkMult : integer;
ClkDiv : integer;
ClkPer : real;
num_comparators : integer;
avr_prog_mem_size : integer
);
port (
clock : in std_logic;
-- Z80 Signals
RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
Addr : out std_logic_vector(15 downto 0);
Data : inout std_logic_vector(7 downto 0);
-- Buffer Control Signals
DIRD : out std_logic;
tristate_n : out std_logic;
tristate_ad_n : out std_logic;
-- Mode jumper, tie low to generate NOPs when paused
mode : in std_logic;
-- External trigger inputs
trig : in std_logic_vector(1 downto 0);
-- Serial Console
avr_RxD : in std_logic;
avr_TxD : out std_logic;
-- Switches
sw_reset_cpu : in std_logic;
sw_reset_avr : in std_logic;
-- LEDs
led_bkpt : out std_logic;
led_trig0 : out std_logic;
led_trig1 : out std_logic;
-- OHO_DY1 connected to test connector
tmosi : out std_logic;
tdin : out std_logic;
tcclk : out std_logic;
-- Debugging signals
test1 : out std_logic;
test2 : out std_logic;
test3 : out std_logic;
test4 : out std_logic
);
end Z80CpuMon;
architecture behavioral of Z80CpuMon is
type state_type is (idle, nop_t1, nop_t2, nop_t3, nop_t4, rd_t1, rd_wa, rd_t2, rd_t3, wr_t1, wr_wa, wr_t2, wr_t3, busack);
signal state : state_type;
signal clock_avr : std_logic;
signal cpu_reset_n : std_logic;
signal cpu_clk : std_logic;
signal cpu_clken : std_logic;
signal busmon_clk : std_logic;
signal Addr_int : std_logic_vector(15 downto 0);
signal Addr1 : std_logic_vector(15 downto 0);
signal Addr2 : std_logic_vector(15 downto 0);
signal RD_n_int : std_logic;
signal WR_n_int : std_logic;
signal MREQ_n_int : std_logic;
signal IORQ_n_int : std_logic;
signal RFSH_n_int : std_logic;
signal M1_n_int : std_logic;
signal BUSAK_n_int : std_logic;
signal BUSAK_n_comb : std_logic;
signal WAIT_n_latched : std_logic;
signal TState : std_logic_vector(2 downto 0);
signal TState1 : std_logic_vector(2 downto 0);
signal SS_Single : std_logic;
signal SS_Step : std_logic;
signal SS_Step_held : std_logic;
signal CountCycle : std_logic;
signal special : std_logic_vector(2 downto 0);
signal skipNextOpcode : std_logic;
signal Regs : std_logic_vector(255 downto 0);
signal PdcData : std_logic_vector(7 downto 0);
signal io_not_mem : std_logic;
signal io_rd : std_logic;
signal io_wr : std_logic;
signal memory_rd : std_logic;
signal memory_wr : std_logic;
signal memory_addr : std_logic_vector(15 downto 0);
signal memory_dout : std_logic_vector(7 downto 0);
signal memory_din : std_logic_vector(7 downto 0);
signal memory_done : std_logic;
signal io_rd1 : std_logic;
signal io_wr1 : std_logic;
signal memory_rd1 : std_logic;
signal memory_wr1 : std_logic;
signal mon_m1_n : std_logic;
signal mon_xx_n : std_logic; -- shorten MREQ and RD in M1 NOP cycle
signal mon_yy : std_logic; -- delay IORQ/RD/WR in IO cycle
signal mon_mreq_n : std_logic;
signal mon_iorq_n : std_logic;
signal mon_rfsh_n : std_logic;
signal mon_rd_n : std_logic;
signal mon_wr_n : std_logic;
signal mon_busak_n1 : std_logic;
signal mon_busak_n2 : std_logic;
signal mon_busak_n : std_logic;
signal BUSRQ_n_sync : std_logic;
signal INT_n_sync : std_logic;
signal NMI_n_sync : std_logic;
signal Rdy : std_logic;
signal Read_n : std_logic;
signal Read_n0 : std_logic;
signal Read_n1 : std_logic;
signal Write_n : std_logic;
signal Write_n0 : std_logic;
signal ReadIO_n : std_logic;
signal ReadIO_n0 : std_logic;
signal ReadIO_n1 : std_logic;
signal WriteIO_n : std_logic;
signal WriteIO_n0 : std_logic;
signal Sync : std_logic;
signal Sync0 : std_logic;
signal Sync1 : std_logic;
signal Mem_IO_n : std_logic;
signal MemState : std_logic_vector(2 downto 0);
signal Din : std_logic_vector(7 downto 0);
signal Dout : std_logic_vector(7 downto 0);
signal Den : std_logic;
signal ex_data : std_logic_vector(7 downto 0);
signal rd_data : std_logic_vector(7 downto 0);
signal wr_data : std_logic_vector(7 downto 0);
signal mon_data : std_logic_vector(7 downto 0);
signal avr_TxD_int : std_logic;
signal rfsh_addr : std_logic_vector(15 downto 0);
begin
--------------------------------------------------------
-- Clocking
--------------------------------------------------------
inst_dcm0 : entity work.DCM0
generic map (
ClkMult => ClkMult,
ClkDiv => ClkDiv,
ClkPer => ClkPer
)
port map(
CLKIN_IN => clock,
CLKFX_OUT => clock_avr
);
cpu_clk <= CLK_n;
busmon_clk <= CLK_n;
--------------------------------------------------------
-- BusMonCore
--------------------------------------------------------
mon : entity work.BusMonCore
generic map (
num_comparators => num_comparators,
avr_prog_mem_size => avr_prog_mem_size
)
port map (
clock_avr => clock_avr,
busmon_clk => busmon_clk,
busmon_clken => '1',
cpu_clk => cpu_clk,
cpu_clken => '1',
Addr => Addr_int,
Data => mon_data,
Rd_n => Read_n,
Wr_n => Write_n,
RdIO_n => ReadIO_n,
WrIO_n => WriteIO_n,
Sync => Sync,
Rdy => open,
nRSTin => RESET_n,
nRSTout => cpu_reset_n,
CountCycle => CountCycle,
trig => trig,
avr_RxD => avr_RxD,
avr_TxD => avr_TxD_int,
sw_reset_cpu => sw_reset_cpu,
sw_reset_avr => sw_reset_avr,
led_bkpt => led_bkpt,
led_trig0 => led_trig0,
led_trig1 => led_trig1,
tmosi => tmosi,
tdin => tdin,
tcclk => tcclk,
Regs => Regs,
PdcData => PdcData,
RdMemOut => memory_rd,
WrMemOut => memory_wr,
RdIOOut => io_rd,
WrIOOut => io_wr,
AddrOut => memory_addr,
DataOut => memory_dout,
DataIn => memory_din,
Done => memory_done,
Special => special,
SS_Single => SS_Single,
SS_Step => SS_Step
);
--------------------------------------------------------
-- T80
--------------------------------------------------------
inst_t80: entity work.T80a port map (
TS => TState,
Regs => Regs,
PdcData => PdcData,
RESET_n => cpu_reset_n,
CLK_n => cpu_clk,
CEN => cpu_clken,
WAIT_n => WAIT_n,
INT_n => INT_n_sync,
NMI_n => NMI_n_sync,
BUSRQ_n => BUSRQ_n,
M1_n => M1_n_int,
MREQ_n => MREQ_n_int,
IORQ_n => IORQ_n_int,
RD_n => RD_n_int,
WR_n => WR_n_int,
RFSH_n => RFSH_n_int,
HALT_n => HALT_n,
BUSAK_n => BUSAK_n_int,
A => Addr_int,
Din => Din,
Dout => Dout,
DEn => Den
);
--------------------------------------------------------
-- Synchronise external interrupts
--------------------------------------------------------
int_gen : process(CLK_n)
begin
if rising_edge(CLK_n) then
BUSRQ_n_sync <= BUSRQ_n;
NMI_n_sync <= NMI_n or special(1);
INT_n_sync <= INT_n or special(0);
end if;
end process;
--------------------------------------------------------
-- Z80 specific single step / breakpoint logic
--------------------------------------------------------
CountCycle <= '1' when state = idle else '0';
-- The breakpoint logic stops the Z80 in M1/T3 using cpu_clken
cpu_clken <= '0' when state = idle and SS_Single = '1' and Sync1 = '1' else
'0' when state /= idle else
'1';
-- Logic to ignore the second M1 in multi-byte opcodes
skip_opcode_latch : process(CLK_n)
begin
if rising_edge(CLK_n) then
if (M1_n_int = '0' and WAIT_n_latched = '1' and TState = "010") then
if (skipNextOpcode = '0' and (Data = x"CB" or Data = x"DD" or Data = x"ED" or Data = x"FD")) then
skipNextOpcode <= '1';
else
skipNextOpcode <= '0';
end if;
end if;
end if;
end process;
-- For instruction breakpoints, we make the monitoring decision as early as possibe
-- to allow time to stop the current instruction, which is possible because we don't
-- really care about the data (it's re-read from memory by the disassembler).
Sync0 <= '1' when WAIT_n = '1' and M1_n_int = '0' and TState = "010" and skipNextOpcode = '0' else '0';
-- For memory reads/write breakpoints we make the monitoring decision in the middle of T2
-- but only if WAIT_n is '1' so we catch the right data.
Read_n0 <= not (WAIT_n and (not RD_n_int) and (not MREQ_n_int) and (M1_n_int)) when TState = "010" else '1';
Write_n0 <= not (WAIT_n and ( RD_n_int) and (not MREQ_n_int) and (M1_n_int)) when TState = "010" else '1';
-- For IO reads/writes we make the monitoring decision in the middle of the second T2 cycle
-- but only if WAIT_n is '1' so we catch the right data.
-- This one cycle delay accounts for the forced wait state
ReadIO_n0 <= not (WAIT_n and (not RD_n_int) and (not IORQ_n_int) and (M1_n_int)) when TState1 = "010" else '1';
WriteIO_n0 <= not (WAIT_n and ( RD_n_int) and (not IORQ_n_int) and (M1_n_int)) when TState1 = "010" else '1';
-- Hold the monitoring decision so it is valid on the rising edge of the clock
-- For instruction fetches and writes, the monitor sees these at the start of T3
-- For reads, the data can arrive in the middle of T3 so delay until end of T3
watch_gen : process(CLK_n)
begin
if falling_edge(CLK_n) then
Sync <= Sync0;
Read_n1 <= Read_n0;
Read_n <= Read_n1;
Write_n <= Write_n0;
ReadIO_n1 <= ReadIO_n0;
ReadIO_n <= ReadIO_n1;
WriteIO_n <= WriteIO_n0;
-- Latch wait seen by T80 on the falling edge, for use on the next rising edge
WAIT_n_latched <= WAIT_n;
end if;
end process;
-- Register the exec data on the rising at the end of T2
ex_data_latch : process(CLK_n)
begin
if rising_edge(CLK_n) then
TState1 <= TState;
if Sync = '1' then
ex_data <= Data;
end if;
end if;
end process;
-- Register the read data on the falling edge of clock in the middle of T3
rd_data_latch : process(CLK_n)
begin
if falling_edge(CLK_n) then
if Read_n1 = '0' or ReadIO_n1 = '0' then
rd_data <= Data;
end if;
memory_din <= Data;
end if;
end process;
-- Register the write data on the falling edge in the middle of T2
wr_data_latch : process(CLK_n)
begin
if falling_edge(CLK_n) then
if Write_n0 = '0' or WriteIO_n0 = '0' then
wr_data <= Data;
end if;
end if;
end process;
-- Mux the data seen by the bus monitor appropriately
mon_data <= rd_data when Read_n = '0' or ReadIO_n = '0' else
wr_data when Write_n = '0' or WriteIO_n = '0' else
ex_data;
-- Mark the memory access as done when t3 is reached
memory_done <= '1' when state = rd_t3 or state = wr_t3 else '0';
-- Multiplex the bus control signals
-- The _int versions come from the T80
-- The mon_ versions come from the state machine below
MREQ_n <= MREQ_n_int when state = idle else mon_mreq_n and mon_xx_n;
IORQ_n <= IORQ_n_int when state = idle else (mon_iorq_n or mon_yy);
WR_n <= WR_n_int when state = idle else (mon_wr_n or mon_yy);
RD_n <= RD_n_int when state = idle else (mon_rd_n or mon_yy) and mon_xx_n;
RFSH_n <= RFSH_n_int when state = idle else mon_rfsh_n;
M1_n <= M1_n_int when state = idle else mon_m1_n;
Addr1 <= x"0000" when state = nop_t1 or state = nop_t2 else
rfsh_addr when state = nop_t3 or state = nop_t4 else
memory_addr when state /= idle else
Addr_int;
tristate_n <= BUSAK_n_int when state = idle else mon_busak_n1;
BUSAK_n <= BUSAK_n_int when state = idle else mon_busak_n;
-- Force the address and databus to tristate when reset is asserted
tristate_ad_n <= '0' when RESET_n = '0' else
BUSAK_n_int when state = idle else
mon_busak_n1;
-- The Acorn Z80 Second Processor needs ~10ns of address hold time following M1
-- and MREQ being released at the start of T3. Otherwise, the ROM switching
-- during NMI doesn't work reliably due to glitches. See:
-- https://stardot.org.uk/forums/viewtopic.php?p=212096#p212096
--
-- Reordering the above Addr expression so Addr_int is last instead of
-- first seems to fix the issue, but is clearly very dependent on how the Xilinx
-- tools route the design.
--
-- If the problem recurs, we should switch to something like:
--
addr_delay : process(clock)
begin
if rising_edge(clock) then
Addr2 <= Addr1;
Addr <= Addr2;
end if;
end process;
Data <= memory_dout when (state = wr_t1 and io_not_mem = '1') or state = wr_wa or state = wr_t2 or state = wr_t3 else
Dout when state = idle and Den = '1' else
(others => 'Z');
DIRD <= '0' when (state = wr_t1 and io_not_mem = '1') or state = wr_wa or state = wr_t2 or state = wr_t3 else
'0' when state = idle and Den = '1' else
'1';
Din <= Data;
men_access_machine_rising : process(CLK_n, cpu_reset_n)
begin
if (cpu_reset_n = '0') then
state <= idle;
memory_rd1 <= '0';
memory_wr1 <= '0';
io_rd1 <= '0';
io_wr1 <= '0';
SS_Step_held <= '0';
mon_rfsh_n <= '1';
mon_m1_n <= '1';
mon_xx_n <= '1';
mon_yy <= '0';
mon_busak_n1 <= '1';
elsif rising_edge(CLK_n) then
-- Extend the 1-cycle long request strobes from BusMonCore
-- until we are ready to generate a bus cycle
if memory_rd = '1' then
memory_rd1 <= '1';
elsif state = rd_t1 then
memory_rd1 <= '0';
end if;
if memory_wr = '1' then
memory_wr1 <= '1';
elsif state = wr_t1 then
memory_wr1 <= '0';
end if;
if io_rd = '1' then
io_rd1 <= '1';
elsif state = rd_t1 then
io_rd1 <= '0';
end if;
if io_wr = '1' then
io_wr1 <= '1';
elsif state = wr_t1 then
io_wr1 <= '0';
end if;
if SS_Step = '1' then
SS_Step_held <= '1';
elsif state = idle then
SS_Step_held <= '0';
end if;
Sync1 <= Sync;
-- Main state machine, generating refresh, read and write cycles
-- (the timing should exactly match those of the Z80)
case state is
-- Idle is when T80 is running
when idle =>
if SS_Single = '1' and Sync1 = '1' then
-- Load the initial refresh address from I/R in the T80
rfsh_addr <= Regs(199 downto 192) & Regs(207 downto 200);
-- Start genering NOP cycles
mon_rfsh_n <= '0';
state <= nop_t3;
end if;
-- NOP cycle
when nop_t1 =>
state <= nop_t2;
-- Increment the refresh address (7 bits, just like the Z80)
rfsh_addr(6 downto 0) <= rfsh_addr(6 downto 0) + 1;
mon_xx_n <= mode;
when nop_t2 =>
if WAIT_n_latched = '1' then
mon_m1_n <= '1';
mon_xx_n <= '1';
if SS_Step_held = '1' or SS_Single = '0' then
state <= idle;
else
mon_rfsh_n <= '0';
state <= nop_t3;
end if;
end if;
when nop_t3 =>
state <= nop_t4;
when nop_t4 =>
mon_rfsh_n <= '1';
-- Sample BUSRQ_n at the *start* of the final T-state
-- (hence using BUSRQ_n_sync)
if BUSRQ_n_sync = '0' then
state <= busack;
mon_busak_n1 <= '0';
elsif memory_wr1 = '1' or io_wr1 = '1' then
state <= wr_t1;
io_not_mem <= io_wr1;
mon_yy <= io_wr1;
elsif memory_rd1 = '1' or io_rd1 = '1' then
state <= rd_t1;
io_not_mem <= io_rd1;
mon_yy <= io_rd1;
else
state <= nop_t1;
mon_m1_n <= mode;
end if;
-- Read cycle
when rd_t1 =>
mon_yy <= '0';
if io_not_mem = '1' then
state <= rd_wa;
else
state <= rd_t2;
end if;
when rd_wa =>
state <= rd_t2;
when rd_t2 =>
if WAIT_n_latched = '1' then
state <= rd_t3;
end if;
when rd_t3 =>
-- Sample BUSRQ_n at the *start* of the final T-state
-- (hence using BUSRQ_n_sync)
if BUSRQ_n_sync = '0' then
state <= busack;
mon_busak_n1 <= '0';
else
state <= nop_t1;
mon_m1_n <= mode;
end if;
-- Write cycle
when wr_t1 =>
mon_yy <= '0';
if io_not_mem = '1' then
state <= wr_wa;
else
state <= wr_t2;
end if;
when wr_wa =>
state <= wr_t2;
when wr_t2 =>
if WAIT_n_latched = '1' then
state <= wr_t3;
end if;
when wr_t3 =>
-- Sample BUSRQ_n at the *start* of the final T-state
-- (hence using BUSRQ_n_sync)
if BUSRQ_n_sync = '0' then
state <= busack;
mon_busak_n1 <= '0';
else
state <= nop_t1;
mon_m1_n <= mode;
end if;
-- Bus Request/Ack cycle
when busack =>
-- Release BUSAK_n on the next rising edge after BUSRQ_n seen
-- (hence using BUSRQ_n)
if BUSRQ_n_sync = '1' then
state <= nop_t1;
mon_m1_n <= mode;
mon_busak_n1 <= '1';
end if;
end case;
end if;
end process;
men_access_machine_falling : process(CLK_n)
begin
if falling_edge(CLK_n) then
-- For memory access cycles, mreq/iorq/rd/wr all change in the middle of
-- the t state, so retime these on the falling edge of clock
if state = rd_t1 or state = rd_wa or state = rd_t2 or state = wr_t1 or state = wr_wa or state = wr_t2 then
if io_not_mem = '0' then
-- Memory cycle
mon_mreq_n <= '0';
mon_iorq_n <= '1';
else
-- IO cycle
mon_mreq_n <= '1';
mon_iorq_n <= '0';
end if;
elsif (state = nop_t1 and mode = '0') or state = nop_t3 then
-- M1 cycle
mon_mreq_n <= '0';
mon_iorq_n <= '1';
else
-- Idle cycle
mon_mreq_n <= '1';
mon_iorq_n <= '1';
end if;
-- Read strobe
if (state = nop_t1 and mode = '0') or state = rd_t1 or state = rd_wa or state = rd_t2 then
mon_rd_n <= '0';
else
mon_rd_n <= '1';
end if;
-- Write strobe
if (state = wr_t1 and io_not_mem = '1') or state = wr_wa or state = wr_t2 then
mon_wr_n <= '0';
else
mon_wr_n <= '1';
end if;
-- Half-cycle delayed version of BUSRQ_n_sync
mon_busak_n2 <= BUSRQ_n_sync;
end if;
end process;
mon_busak_n <= mon_busak_n1 or mon_busak_n2;
avr_TxD <= avr_Txd_int;
test1 <= Sync1;
test2 <= TState(0);
test3 <= TState(1);
test4 <= TState(2);
end behavioral;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Tb_Codeword Generator_n_m_v2
-- Module Name: Tb_Codeword_Generator_n_m_v2
-- Project Name: McEliece QD-Goppa Encoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Test bench for codeword_generator_n_m_v2 circuit.
--
-- The circuits parameters
--
-- PERIOD :
--
-- Input clock period to be applied on the test.
--
-- number_of_multipliers_per_acc :
--
-- The number of matrix rows and message values calculate at once in one or more accumulators.
-- On this implementation this value, must be the same of number_of_accs,
-- because of copy message. When copying message message values loaded must be same stored in codeword.
-- This value also must be power of 2.
--
-- number_of_accs :
--
-- The number of matrix columns and codeword values calculate at once.
-- On this implementation this value, must be the same of number_of_multipliers_per_acc,
-- because of copy message. When copying message message values loaded must be same stored in codeword.
-- This value also must be power of 2.
--
-- length_message :
--
-- Length in bits of message size and also part of matrix size.
--
-- size_message :
--
-- The number of bits necessary to store the message. The ceil(log2(lenght_message))
--
-- length_codeword :
--
-- Length in bits of codeword size and also part of matrix size.
--
-- size_codeword :
--
-- The number of bits necessary to store the codeword. The ceil(log2(length_codeword))
--
-- size_dyadic_matrix :
--
-- The number of bits necessary to store one row of the dyadic matrix.
-- It is also the ceil(log2(number of errors in the code))
--
-- number_dyadic_matrices :
--
-- The number of dyadic matrices present in matrix A.
--
-- size_number_dyadic_matrices :
--
-- The number of bits necessary to store the number of dyadic matrices.
-- The ceil(log2(number_dyadic_matrices))
--
-- message_memory_file :
--
-- File that holds the message to be encoded.
--
-- codeword_memory_file :
--
-- File that holds the encoded message.
-- This will be used to verify if the circuit worked correctly.
--
-- generator_matrix_memory_file :
--
-- File that holds the public key, matrix A, in a reduced form.
--
-- dump_test_codeword_file :
--
-- File that will hold the encoded message computed by the circuit.
--
--
-- Dependencies:
--
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- codeword_generator_n_m_v2 Rev 1.0
-- ram_bank Rev 1.0
-- ram_double Rev 1.0
-- ram_double_bank Rev 1.0
--
-- Revision:
-- Revision 1.00 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_codeword_generator_n_m_v2 is
Generic (
PERIOD : time := 10 ns;
-- QD-GOPPA [52, 28, 4, 6] --
-- number_of_multipliers_per_acc : integer := 1;
-- number_of_accs : integer := 1;
-- length_message : integer := 28;
-- size_message : integer := 5;
-- length_codeword : integer := 52;
-- size_codeword : integer := 6;
-- size_dyadic_matrix : integer := 2;
-- number_dyadic_matrices : integer := 42;
-- size_number_dyadic_matrices : integer := 6;
-- message_memory_file : string := "mceliece/data_tests/message_qdgoppa_52_28_4_6.dat";
-- codeword_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_52_28_4_6.dat";
-- generator_matrix_memory_file : string := "mceliece/data_tests/generator_matrix_qdgoppa_52_28_4_6.dat";
-- dump_test_codeword_file : string := "mceliece/data_tests/dump_plaintext_qdgoppa_52_28_4_6.dat"
-- QD-GOPPA [2528, 2144, 32, 12] --
number_of_multipliers_per_acc : integer := 4;
number_of_accs : integer := 4;
length_message : integer := 2144;
size_message : integer := 12;
length_codeword : integer := 2528;
size_codeword : integer := 12;
size_dyadic_matrix : integer := 5;
number_dyadic_matrices : integer := 804;
size_number_dyadic_matrices : integer := 10;
message_memory_file : string := "mceliece/data_tests/message_qdgoppa_2528_2144_32_12.dat";
codeword_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_2528_2144_32_12.dat";
generator_matrix_memory_file : string := "mceliece/data_tests/generator_matrix_qdgoppa_2528_2144_32_12.dat";
dump_test_codeword_file : string := "mceliece/data_tests/dump_plaintext_qdgoppa_2528_2144_32_12.dat"
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_multipliers_per_acc : integer := 64;
-- number_of_accs : integer := 64;
-- length_message : integer := 2048;
-- size_message : integer := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- size_dyadic_matrix : integer := 6;
-- number_dyadic_matrices : integer := 384;
-- size_number_dyadic_matrices : integer := 9;
-- message_memory_file : string := "mceliece/data_tests/message_qdgoppa_2816_2048_64_12.dat";
-- codeword_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_2816_2048_64_12.dat";
-- generator_matrix_memory_file : string := "mceliece/data_tests/generator_matrix_qdgoppa_2816_2048_64_12.dat";
-- dump_test_codeword_file : string := "mceliece/data_tests/dump_plaintext_qdgoppa_2816_2048_64_12.dat"
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_multipliers_per_acc : integer := 64;
-- number_of_accs : integer := 64;
-- length_message : integer := 2560;
-- size_message : integer := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- size_dyadic_matrix : integer := 6;
-- number_dyadic_matrices : integer := 480;
-- size_number_dyadic_matrices : integer := 9;
-- message_memory_file : string := "mceliece/data_tests/message_qdgoppa_3328_2560_64_12.dat";
-- codeword_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_3328_2560_64_12.dat";
-- generator_matrix_memory_file : string := "mceliece/data_tests/generator_matrix_qdgoppa_3328_2560_64_12.dat";
-- dump_test_codeword_file : string := "mceliece/data_tests/dump_plaintext_qdgoppa_3328_2560_64_12.dat"
-- QD-GOPPA [7296, 5632, 128, 13] --
-- number_of_multipliers_per_acc : integer := 128;
-- number_of_accs : integer := 128;
-- length_message : integer := 5632;
-- size_message : integer := 13;
-- length_codeword : integer := 7296;
-- size_codeword : integer := 13;
-- size_dyadic_matrix : integer := 7;
-- number_dyadic_matrices : integer := 572;
-- size_number_dyadic_matrices : integer := 10;
-- message_memory_file : string := "mceliece/data_tests/message_qdgoppa_7296_5632_128_13.dat";
-- codeword_memory_file : string := "mceliece/data_tests/plaintext_qdgoppa_7296_5632_128_13.dat";
-- generator_matrix_memory_file : string := "mceliece/data_tests/generator_matrix_qdgoppa_7296_5632_128_13.dat";
-- dump_test_codeword_file : string := "mceliece/data_tests/dump_plaintext_qdgoppa_7296_5632_128_13.dat"
);
end tb_codeword_generator_n_m_v2;
architecture Behavioral of tb_codeword_generator_n_m_v2 is
component codeword_generator_n_m_v2 is
Generic(
number_of_multipliers_per_acc : integer;
number_of_accs : integer;
length_message : integer;
size_message : integer;
length_codeword : integer;
size_codeword : integer;
size_dyadic_matrix : integer;
number_dyadic_matrices : integer;
size_number_dyadic_matrices : integer
);
Port(
codeword : in STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
matrix : in STD_LOGIC_VECTOR((2**size_dyadic_matrix - 1) downto 0);
message : in STD_LOGIC_VECTOR((number_of_multipliers_per_acc - 1) downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
new_codeword : out STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
write_enable_new_codeword : out STD_LOGIC;
codeword_finalized : out STD_LOGIC;
address_codeword : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_message : out STD_LOGIC_VECTOR((size_message - 1) downto 0);
address_matrix : out STD_LOGIC_VECTOR(((size_dyadic_matrix + size_number_dyadic_matrices) - 1) downto 0)
);
end component;
component ram_bank
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end component;
component ram_double
Generic (
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in_a : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
address_b : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0)
);
end component;
component ram_double_bank
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in_a : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_in_b : in STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
rw_a : in STD_LOGIC;
rw_b : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address_a : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
address_b : in STD_LOGIC_VECTOR ((ram_address_size - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR ((ram_word_size - 1) downto 0);
data_out_a : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0);
data_out_b : out STD_LOGIC_VECTOR (((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end component;
signal clk : STD_LOGIC := '0';
signal rst : STD_LOGIC;
signal codeword : STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
signal matrix : STD_LOGIC_VECTOR((2**size_dyadic_matrix - 1) downto 0);
signal message : STD_LOGIC_VECTOR((number_of_multipliers_per_acc - 1) downto 0);
signal new_codeword : STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
signal write_enable_new_codeword : STD_LOGIC;
signal codeword_finalized : STD_LOGIC;
signal address_codeword : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal address_message : STD_LOGIC_VECTOR((size_message - 1) downto 0);
signal address_matrix : STD_LOGIC_VECTOR(((size_dyadic_matrix + size_number_dyadic_matrices) - 1) downto 0);
signal test_address_acc : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal final_address_acc : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal true_codeword : STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
signal test_error : STD_LOGIC;
signal dump_test_codeword : STD_LOGIC;
signal test_bench_finish : STD_LOGIC := '0';
signal cycle_count : integer range 0 to 2000000000 := 0;
for mem_message : ram_bank use entity work.ram_bank(file_load);
for mem_test_codeword : ram_bank use entity work.ram_bank(simple);
for mem_true_codeword : ram_bank use entity work.ram_bank(file_load);
begin
test : codeword_generator_n_m_v2
Generic Map(
number_of_multipliers_per_acc => number_of_multipliers_per_acc,
number_of_accs => number_of_accs,
length_message => length_message,
size_message => size_message,
length_codeword => length_codeword,
size_codeword => size_codeword,
size_dyadic_matrix => size_dyadic_matrix,
number_dyadic_matrices => number_dyadic_matrices,
size_number_dyadic_matrices => size_number_dyadic_matrices
)
Port Map(
codeword => codeword,
matrix => matrix,
message => message,
clk => clk,
rst => rst,
new_codeword => new_codeword,
write_enable_new_codeword => write_enable_new_codeword,
codeword_finalized => codeword_finalized,
address_codeword => address_codeword,
address_message => address_message,
address_matrix => address_matrix
);
mem_generator_matrix : entity work.ram_bank(file_load)
Generic Map(
number_of_memories => 2**size_dyadic_matrix,
ram_address_size => size_dyadic_matrix + size_number_dyadic_matrices,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => generator_matrix_memory_file,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => address_matrix,
rst_value => "0",
data_out => matrix
);
mem_message : ram_bank
Generic Map(
number_of_memories => number_of_multipliers_per_acc,
ram_address_size => size_message,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => message_memory_file,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => address_message,
rst_value => "0",
data_out => message
);
mem_test_codeword : ram_bank
Generic Map(
number_of_memories => number_of_accs,
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => "",
dump_file_name => dump_test_codeword_file
)
Port Map(
data_in => new_codeword,
rw => write_enable_new_codeword,
clk => clk,
rst => rst,
dump => dump_test_codeword,
address => final_address_acc,
rst_value => "0",
data_out => codeword
);
mem_true_codeword : ram_bank
Generic Map(
number_of_memories => number_of_accs,
ram_address_size => size_codeword,
ram_word_size => 1,
file_ram_word_size => 1,
load_file_name => codeword_memory_file,
dump_file_name => ""
)
Port Map(
data_in => (others => '0'),
rw => '0',
clk => clk,
rst => rst,
dump => '0',
address => final_address_acc,
rst_value => "0",
data_out => true_codeword
);
clock : process
begin
while ( test_bench_finish /= '1') loop
clk <= not clk;
wait for PERIOD/2;
cycle_count <= cycle_count+1;
end loop;
wait;
end process;
final_address_acc <= address_codeword when codeword_finalized = '0' else test_address_acc;
process
variable i : integer;
begin
test_address_acc <= (others => '0');
rst <= '1';
test_error <= '0';
dump_test_codeword <= '0';
wait for PERIOD*2;
rst <= '0';
wait until codeword_finalized = '1';
report "Circuit finish = " & integer'image((cycle_count - 2)/2) & " cycles";
wait for PERIOD;
i := 0;
while (i < (length_codeword)) loop
test_address_acc <= std_logic_vector(to_unsigned(i, test_address_acc'Length));
wait for PERIOD*2;
if (true_codeword = codeword) then
test_error <= '0';
else
test_error <= '1';
report "Computed values do not match expected ones";
end if;
wait for PERIOD;
test_error <= '0';
wait for PERIOD;
i := i + number_of_accs;
end loop;
dump_test_codeword <= '1';
wait for PERIOD;
dump_test_codeword <= '0';
test_bench_finish <= '1';
wait;
end process;
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_apa3_gen.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Memory generators for Actel Proasic3 rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library proasic3;
use proasic3.RAM4K9;
-- pragma translate_on
entity proasic3_ram4k9 is
generic (abits : integer range 9 to 12 := 9; dbits : integer := 9);
port (
addra, addrb : in std_logic_vector(abits -1 downto 0);
clka, clkb : in std_ulogic;
dia, dib : in std_logic_vector(dbits -1 downto 0);
doa, dob : out std_logic_vector(dbits -1 downto 0);
ena, enb : in std_ulogic;
wea, web : in std_ulogic
);
end;
architecture rtl of proasic3_ram4k9 is
component RAM4K9
-- pragma translate_off
generic (abits : integer range 9 to 12 := 9);
-- pragma translate_on
port(
ADDRA0, ADDRA1, ADDRA2, ADDRA3, ADDRA4, ADDRA5, ADDRA6, ADDRA7,
ADDRA8, ADDRA9, ADDRA10, ADDRA11 : in std_logic;
ADDRB0, ADDRB1, ADDRB2, ADDRB3, ADDRB4, ADDRB5, ADDRB6, ADDRB7,
ADDRB8, ADDRB9, ADDRB10, ADDRB11 : in std_logic;
BLKA, WENA, PIPEA, WMODEA, WIDTHA0, WIDTHA1, WENB, BLKB,
PIPEB, WMODEB, WIDTHB1, WIDTHB0 : in std_logic;
DINA0, DINA1, DINA2, DINA3, DINA4, DINA5, DINA6, DINA7, DINA8 : in std_logic;
DINB0, DINB1, DINB2, DINB3, DINB4, DINB5, DINB6, DINB7, DINB8 : in std_logic;
RESET, CLKA, CLKB : in std_logic;
DOUTA0, DOUTA1, DOUTA2, DOUTA3, DOUTA4, DOUTA5, DOUTA6, DOUTA7, DOUTA8 : out std_logic;
DOUTB0, DOUTB1, DOUTB2, DOUTB3, DOUTB4, DOUTB5, DOUTB6, DOUTB7, DOUTB8 : out std_logic
);
end component;
attribute syn_black_box : boolean;
attribute syn_black_box of RAM4K9: component is true;
attribute syn_tco1 : string;
attribute syn_tco2 : string;
attribute syn_tco1 of RAM4K9 : component is
"CLKA->DOUTA0,DOUTA1,DOUTA2,DOUTA3,DOUTA4,DOUTA5,DOUTA6,DOUTA7,DOUTA8 = 3.0";
attribute syn_tco2 of RAM4K9 : component is
"CLKB->DOUTB0,DOUTB1,DOUTB2,DOUTB3,DOUTB4,DOUTB5,DOUTB6,DOUTB7,DOUTB8 = 3.0";
signal gnd, vcc : std_ulogic;
signal aa, ab : std_logic_vector(13 downto 0);
signal da, db : std_logic_vector(9 downto 0);
signal qa, qb : std_logic_vector(9 downto 0);
signal width : std_logic_vector(1 downto 0);
begin
gnd <= '0'; vcc <= '1';
width <= "11" when abits = 9 else "10" when abits = 10 else
"01" when abits = 11 else "00";
doa <= qa(dbits-1 downto 0); dob <= qb(dbits-1 downto 0);
da(dbits-1 downto 0) <= dia; da(9 downto dbits) <= (others => '0');
db(dbits-1 downto 0) <= dib; db(9 downto dbits) <= (others => '0');
aa(abits-1 downto 0) <= addra; aa(13 downto abits) <= (others => '0');
ab(abits-1 downto 0) <= addrb; ab(13 downto abits) <= (others => '0');
u0 : RAM4K9
-- pragma translate_off
generic map (abits => abits)
-- pragma translate_on
port map (
ADDRA0 => aa(0), ADDRA1 => aa(1), ADDRA2 => aa(2), ADDRA3 => aa(3),
ADDRA4 => aa(4), ADDRA5 => aa(5), ADDRA6 => aa(6), ADDRA7 => aa(7),
ADDRA8 => aa(8), ADDRA9 => aa(9), ADDRA10 => aa(10), ADDRA11 => aa(11),
ADDRB0 => ab(0), ADDRB1 => ab(1), ADDRB2 => ab(2), ADDRB3 => ab(3),
ADDRB4 => ab(4), ADDRB5 => ab(5), ADDRB6 => ab(6), ADDRB7 => ab(7),
ADDRB8 => ab(8), ADDRB9 => ab(9), ADDRB10 => ab(10), ADDRB11 => ab(11),
BLKA => ena, WENA => wea, PIPEA =>gnd, WMODEA => gnd, WIDTHA0 => width(0), WIDTHA1 => width(1),
BLKB => enb, WENB => web, PIPEB =>gnd, WMODEB => gnd, WIDTHB0 => width(0), WIDTHB1 => width(1),
DINA0 => da(0), DINA1 => da(1), DINA2 => da(2), DINA3 => da(3), DINA4 => da(4),
DINA5 => da(5), DINA6 => da(6), DINA7 => da(7), DINA8 => da(8),
DINB0 => db(0), DINB1 => db(1), DINB2 => db(2), DINB3 => db(3), DINB4 => db(4),
DINB5 => db(5), DINB6 => db(6), DINB7 => db(7), DINB8 => db(8),
RESET => vcc, CLKA => clka, CLKB => clkb,
DOUTA0 => qa(0), DOUTA1 => qa(1), DOUTA2 => qa(2), DOUTA3 => qa(3), DOUTA4 => qa(4),
DOUTA5 => qa(5), DOUTA6 => qa(6), DOUTA7 => qa(7), DOUTA8 => qa(8),
DOUTB0 => qb(0), DOUTB1 => qb(1), DOUTB2 => qb(2), DOUTB3 => qb(3), DOUTB4 => qb(4),
DOUTB5 => qb(5), DOUTB6 => qb(6), DOUTB7 => qb(7), DOUTB8 => qb(8)
);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library proasic3;
use proasic3.RAM512X18;
-- pragma translate_on
entity proasic3_ram512x18 is
port (
addra, addrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_ulogic;
di : in std_logic_vector(17 downto 0);
do : out std_logic_vector(17 downto 0);
ena, enb : in std_ulogic;
wea : in std_ulogic
);
end;
architecture rtl of proasic3_ram512x18 is
component RAM512X18
port(
RADDR8, RADDR7, RADDR6, RADDR5, RADDR4, RADDR3, RADDR2, RADDR1, RADDR0 : in std_logic;
WADDR8, WADDR7, WADDR6, WADDR5, WADDR4, WADDR3, WADDR2, WADDR1, WADDR0 : in std_logic;
WD17, WD16, WD15, WD14, WD13, WD12, WD11, WD10, WD9,
WD8, WD7, WD6, WD5, WD4, WD3, WD2, WD1, WD0 : in std_logic;
REN, WEN, RESET, RW0, RW1, WW1, WW0, PIPE, RCLK, WCLK : in std_logic;
RD17, RD16, RD15, RD14, RD13, RD12, RD11, RD10, RD9,
RD8, RD7, RD6, RD5, RD4, RD3, RD2, RD1, RD0 : out std_logic
);
end component;
attribute syn_black_box : boolean;
attribute syn_tco1 : string;
attribute syn_black_box of RAM512X18: component is true;
attribute syn_tco1 of RAM512X18 : component is
"RCLK->RD17,RD16,RD15,RD14,RD13,RD12,RD11,RD10,RD9,RD8,RD7,RD6,RD5,RD4,RD3,RD2,RD1,RD0 = 3.0";
signal gnd, vcc : std_ulogic;
signal width : std_logic_vector(1 downto 0);
begin
gnd <= '0'; vcc <= '1';
width <= "10";
u0 : RAM512X18
port map (
RADDR0 => addrb(0), RADDR1 => addrb(1), RADDR2 => addrb(2), RADDR3 => addrb(3),
RADDR4 => addrb(4), RADDR5 => addrb(5), RADDR6 => addrb(6), RADDR7 => addrb(7),
RADDR8 => addrb(8),
WADDR0 => addra(0), WADDR1 => addra(1), WADDR2 => addra(2), WADDR3 => addra(3),
WADDR4 => addra(4), WADDR5 => addra(5), WADDR6 => addra(6), WADDR7 => addra(7),
WADDR8 => addra(8),
WD17 => di(17), WD16 => di(16), WD15 => di(15), WD14 => di(14), WD13 => di(13),
WD12 => di(12), WD11 => di(11), WD10 => di(10), WD9 => di(9),
WD8 => di(8), WD7 => di(7), WD6 => di(6), WD5 => di(5), WD4 => di(4),
WD3 => di(3), WD2 => di(2), WD1 => di(1), WD0 => di(0),
WEN => ena, PIPE => gnd, WW0 => width(0), WW1 => width(1),
REN => enb, RW0 => width(0), RW1 => width(1),
RESET => vcc, WCLK => clka, RCLK => clkb,
RD17 => do(17), RD16 => do(16), RD15 => do(15), RD14 => do(14), RD13 => do(13),
RD12 => do(12), RD11 => do(11), RD10 => do(10), RD9 => do(9),
RD8 => do(8), RD7 => do(7), RD6 => do(6), RD5 => do(5), RD4 => do(4),
RD3 => do(3), RD2 => do(2), RD1 => do(1), RD0 => do(0)
);
end;
library ieee;
use ieee.std_logic_1164.all;
entity proasic3_syncram_dp is
generic ( abits : integer := 6; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end;
architecture rtl of proasic3_syncram_dp is
component proasic3_ram4k9
generic (abits : integer range 9 to 12 := 9; dbits : integer := 9);
port (
addra, addrb : in std_logic_vector(abits -1 downto 0);
clka, clkb : in std_ulogic;
dia, dib : in std_logic_vector(dbits -1 downto 0);
doa, dob : out std_logic_vector(dbits -1 downto 0);
ena, enb : in std_ulogic;
wea, web : in std_ulogic);
end component;
constant dlen : integer := dbits + 9;
signal di1, di2, q1, q2 : std_logic_vector(dlen downto 0);
signal a1, a2 : std_logic_vector(12 downto 0);
signal en1, en2, we1, we2 : std_ulogic;
begin
di1(dbits-1 downto 0) <= datain1; di1(dlen downto dbits) <= (others => '0');
di2(dbits-1 downto 0) <= datain1; di2(dlen downto dbits) <= (others => '0');
a1(abits-1 downto 0) <= address1; a1(12 downto abits) <= (others => '0');
a2(abits-1 downto 0) <= address1; a2(12 downto abits) <= (others => '0');
dataout1 <= q1(dbits-1 downto 0); q1(dlen downto dbits) <= (others => '0');
dataout2 <= q2(dbits-1 downto 0); q2(dlen downto dbits) <= (others => '0');
en1 <= not enable1; en2 <= not enable2;
we1 <= not write1; we2 <= not write2;
a9 : if (abits <= 9) generate
x : for i in 0 to (dbits-1)/9 generate
u0 : proasic3_ram4k9 generic map (9, 9) port map (
a1(8 downto 0), a2(8 downto 0), clk1, clk2,
di1(i*9+8 downto i*9), di2(i*9+8 downto i*9),
q1(i*9+8 downto i*9), q2(i*9+8 downto i*9),
en1, en2, we1, we2);
end generate;
end generate;
a10 : if (abits = 10) generate
x : for i in 0 to (dbits-1)/4 generate
u0 : proasic3_ram4k9 generic map (10, 4) port map (
a1(9 downto 0), a2(9 downto 0), clk1, clk2,
di1(i*4+3 downto i*4), di2(i*4+3 downto i*4),
q1(i*4+3 downto i*4), q2(i*4+3 downto i*4),
en1, en2, we1, we2);
end generate;
end generate;
a11 : if (abits = 11) generate
x : for i in 0 to (dbits-1)/2 generate
u0 : proasic3_ram4k9 generic map (11, 2) port map (
a1(10 downto 0), a2(10 downto 0), clk1, clk2,
di1(i*2+1 downto i*2), di2(i*2+1 downto i*2),
q1(i*2+1 downto i*2), q2(i*2+1 downto i*2),
en1, en2, we1, we2);
end generate;
end generate;
a12 : if (abits = 12) generate
x : for i in 0 to (dbits-1) generate
u0 : proasic3_ram4k9 generic map (12, 1) port map (
a1(11 downto 0), a2(11 downto 0), clk1, clk2,
di1(i*1 downto i*1), di2(i*1 downto i*1),
q1(i*1 downto i*1), q2(i*1 downto i*1),
en1, en2, we1, we2);
end generate;
end generate;
-- pragma translate_off
unsup : if abits > 12 generate
x : process
begin
assert false
report "Address depth larger than 12 not supported for ProAsic3 rams"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
entity proasic3_syncram_2p is
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end;
architecture rtl of proasic3_syncram_2p is
component proasic3_ram4k9
generic (abits : integer range 9 to 12 := 9; dbits : integer := 9);
port (
addra, addrb : in std_logic_vector(abits -1 downto 0);
clka, clkb : in std_ulogic;
dia, dib : in std_logic_vector(dbits -1 downto 0);
doa, dob : out std_logic_vector(dbits -1 downto 0);
ena, enb : in std_ulogic;
wea, web : in std_ulogic);
end component;
component proasic3_ram512x18
port (
addra, addrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_ulogic;
di : in std_logic_vector(17 downto 0);
do : out std_logic_vector(17 downto 0);
ena, enb : in std_ulogic;
wea : in std_ulogic);
end component;
constant dlen : integer := dbits + 18;
signal di1, q2, gnd : std_logic_vector(dlen downto 0);
signal a1, a2 : std_logic_vector(12 downto 0);
signal en1, en2, we1, vcc : std_ulogic;
begin
vcc <= '1'; gnd <= (others => '0');
di1(dbits-1 downto 0) <= din; di1(dlen downto dbits) <= (others => '0');
a1(abits-1 downto 0) <= waddr; a1(12 downto abits) <= (others => '0');
a2(abits-1 downto 0) <= raddr; a2(12 downto abits) <= (others => '0');
dout <= q2(dbits-1 downto 0); q2(dlen downto dbits) <= (others => '0');
en1 <= not write; en2 <= not rena; we1 <= not write;
a8 : if (abits <= 8) generate
x : for i in 0 to (dbits-1)/18 generate
u0 : proasic3_ram512x18 port map (
a1(8 downto 0), a2(8 downto 0), wclk, rclk,
di1(i*18+17 downto i*18), q2(i*18+17 downto i*18),
en1, en2, we1);
end generate;
end generate;
a9 : if (abits = 9) generate
x : for i in 0 to (dbits-1)/9 generate
u0 : proasic3_ram4k9 generic map (9, 9) port map (
a1(8 downto 0), a2(8 downto 0), wclk, rclk,
di1(i*9+8 downto i*9), gnd(8 downto 0),
open, q2(i*9+8 downto i*9),
en1, en2, we1, vcc);
end generate;
end generate;
a10 : if (abits = 10) generate
x : for i in 0 to (dbits-1)/4 generate
u0 : proasic3_ram4k9 generic map (10, 4) port map (
a1(9 downto 0), a2(9 downto 0), wclk, rclk,
di1(i*4+3 downto i*4), gnd(3 downto 0),
open, q2(i*4+3 downto i*4),
en1, en2, we1, vcc);
end generate;
end generate;
a11 : if (abits = 11) generate
x : for i in 0 to (dbits-1)/2 generate
u0 : proasic3_ram4k9 generic map (11, 2) port map (
a1(10 downto 0), a2(10 downto 0), wclk, rclk,
di1(i*2+1 downto i*2), gnd(1 downto 0),
open, q2(i*2+1 downto i*2),
en1, en2, we1, vcc);
end generate;
end generate;
a12 : if (abits = 12) generate
x : for i in 0 to (dbits-1) generate
u0 : proasic3_ram4k9 generic map (12, 1) port map (
a1(11 downto 0), a2(11 downto 0), wclk, rclk,
di1(i*1 downto i*1), gnd(0 downto 0),
open, q2(i*1 downto i*1),
en1, en2, we1, vcc);
end generate;
end generate;
-- pragma translate_off
unsup : if abits > 12 generate
x : process
begin
assert false
report "Address depth larger than 12 not supported for ProAsic3 rams"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
entity proasic3_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture rtl of proasic3_syncram is
component proasic3_syncram_dp
generic ( abits : integer := 6; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component proasic3_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
signal gnd : std_logic_vector(abits+dbits downto 0);
begin
gnd <= (others => '0');
r2p : if abits <= 8 generate
u0 : proasic3_syncram_2p generic map (abits, dbits)
port map (clk, enable, address, dataout, clk, address, datain, write);
end generate;
rdp : if abits > 8 generate
u0 : proasic3_syncram_dp generic map (abits, dbits)
port map (clk, address, datain, dataout, enable, write,
clk, gnd(abits-1 downto 0), gnd(dbits-1 downto 0), open, gnd(0), gnd(0));
end generate;
end;
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