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------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_apa3_gen.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Memory generators for Actel Proasic3 rams
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library proasic3;
use proasic3.RAM4K9;
-- pragma translate_on
entity proasic3_ram4k9 is
generic (abits : integer range 9 to 12 := 9; dbits : integer := 9);
port (
addra, addrb : in std_logic_vector(abits -1 downto 0);
clka, clkb : in std_ulogic;
dia, dib : in std_logic_vector(dbits -1 downto 0);
doa, dob : out std_logic_vector(dbits -1 downto 0);
ena, enb : in std_ulogic;
wea, web : in std_ulogic
);
end;
architecture rtl of proasic3_ram4k9 is
component RAM4K9
-- pragma translate_off
generic (abits : integer range 9 to 12 := 9);
-- pragma translate_on
port(
ADDRA0, ADDRA1, ADDRA2, ADDRA3, ADDRA4, ADDRA5, ADDRA6, ADDRA7,
ADDRA8, ADDRA9, ADDRA10, ADDRA11 : in std_logic;
ADDRB0, ADDRB1, ADDRB2, ADDRB3, ADDRB4, ADDRB5, ADDRB6, ADDRB7,
ADDRB8, ADDRB9, ADDRB10, ADDRB11 : in std_logic;
BLKA, WENA, PIPEA, WMODEA, WIDTHA0, WIDTHA1, WENB, BLKB,
PIPEB, WMODEB, WIDTHB1, WIDTHB0 : in std_logic;
DINA0, DINA1, DINA2, DINA3, DINA4, DINA5, DINA6, DINA7, DINA8 : in std_logic;
DINB0, DINB1, DINB2, DINB3, DINB4, DINB5, DINB6, DINB7, DINB8 : in std_logic;
RESET, CLKA, CLKB : in std_logic;
DOUTA0, DOUTA1, DOUTA2, DOUTA3, DOUTA4, DOUTA5, DOUTA6, DOUTA7, DOUTA8 : out std_logic;
DOUTB0, DOUTB1, DOUTB2, DOUTB3, DOUTB4, DOUTB5, DOUTB6, DOUTB7, DOUTB8 : out std_logic
);
end component;
attribute syn_black_box : boolean;
attribute syn_black_box of RAM4K9: component is true;
attribute syn_tco1 : string;
attribute syn_tco2 : string;
attribute syn_tco1 of RAM4K9 : component is
"CLKA->DOUTA0,DOUTA1,DOUTA2,DOUTA3,DOUTA4,DOUTA5,DOUTA6,DOUTA7,DOUTA8 = 3.0";
attribute syn_tco2 of RAM4K9 : component is
"CLKB->DOUTB0,DOUTB1,DOUTB2,DOUTB3,DOUTB4,DOUTB5,DOUTB6,DOUTB7,DOUTB8 = 3.0";
signal gnd, vcc : std_ulogic;
signal aa, ab : std_logic_vector(13 downto 0);
signal da, db : std_logic_vector(9 downto 0);
signal qa, qb : std_logic_vector(9 downto 0);
signal width : std_logic_vector(1 downto 0);
begin
gnd <= '0'; vcc <= '1';
width <= "11" when abits = 9 else "10" when abits = 10 else
"01" when abits = 11 else "00";
doa <= qa(dbits-1 downto 0); dob <= qb(dbits-1 downto 0);
da(dbits-1 downto 0) <= dia; da(9 downto dbits) <= (others => '0');
db(dbits-1 downto 0) <= dib; db(9 downto dbits) <= (others => '0');
aa(abits-1 downto 0) <= addra; aa(13 downto abits) <= (others => '0');
ab(abits-1 downto 0) <= addrb; ab(13 downto abits) <= (others => '0');
u0 : RAM4K9
-- pragma translate_off
generic map (abits => abits)
-- pragma translate_on
port map (
ADDRA0 => aa(0), ADDRA1 => aa(1), ADDRA2 => aa(2), ADDRA3 => aa(3),
ADDRA4 => aa(4), ADDRA5 => aa(5), ADDRA6 => aa(6), ADDRA7 => aa(7),
ADDRA8 => aa(8), ADDRA9 => aa(9), ADDRA10 => aa(10), ADDRA11 => aa(11),
ADDRB0 => ab(0), ADDRB1 => ab(1), ADDRB2 => ab(2), ADDRB3 => ab(3),
ADDRB4 => ab(4), ADDRB5 => ab(5), ADDRB6 => ab(6), ADDRB7 => ab(7),
ADDRB8 => ab(8), ADDRB9 => ab(9), ADDRB10 => ab(10), ADDRB11 => ab(11),
BLKA => ena, WENA => wea, PIPEA =>gnd, WMODEA => gnd, WIDTHA0 => width(0), WIDTHA1 => width(1),
BLKB => enb, WENB => web, PIPEB =>gnd, WMODEB => gnd, WIDTHB0 => width(0), WIDTHB1 => width(1),
DINA0 => da(0), DINA1 => da(1), DINA2 => da(2), DINA3 => da(3), DINA4 => da(4),
DINA5 => da(5), DINA6 => da(6), DINA7 => da(7), DINA8 => da(8),
DINB0 => db(0), DINB1 => db(1), DINB2 => db(2), DINB3 => db(3), DINB4 => db(4),
DINB5 => db(5), DINB6 => db(6), DINB7 => db(7), DINB8 => db(8),
RESET => vcc, CLKA => clka, CLKB => clkb,
DOUTA0 => qa(0), DOUTA1 => qa(1), DOUTA2 => qa(2), DOUTA3 => qa(3), DOUTA4 => qa(4),
DOUTA5 => qa(5), DOUTA6 => qa(6), DOUTA7 => qa(7), DOUTA8 => qa(8),
DOUTB0 => qb(0), DOUTB1 => qb(1), DOUTB2 => qb(2), DOUTB3 => qb(3), DOUTB4 => qb(4),
DOUTB5 => qb(5), DOUTB6 => qb(6), DOUTB7 => qb(7), DOUTB8 => qb(8)
);
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library proasic3;
use proasic3.RAM512X18;
-- pragma translate_on
entity proasic3_ram512x18 is
port (
addra, addrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_ulogic;
di : in std_logic_vector(17 downto 0);
do : out std_logic_vector(17 downto 0);
ena, enb : in std_ulogic;
wea : in std_ulogic
);
end;
architecture rtl of proasic3_ram512x18 is
component RAM512X18
port(
RADDR8, RADDR7, RADDR6, RADDR5, RADDR4, RADDR3, RADDR2, RADDR1, RADDR0 : in std_logic;
WADDR8, WADDR7, WADDR6, WADDR5, WADDR4, WADDR3, WADDR2, WADDR1, WADDR0 : in std_logic;
WD17, WD16, WD15, WD14, WD13, WD12, WD11, WD10, WD9,
WD8, WD7, WD6, WD5, WD4, WD3, WD2, WD1, WD0 : in std_logic;
REN, WEN, RESET, RW0, RW1, WW1, WW0, PIPE, RCLK, WCLK : in std_logic;
RD17, RD16, RD15, RD14, RD13, RD12, RD11, RD10, RD9,
RD8, RD7, RD6, RD5, RD4, RD3, RD2, RD1, RD0 : out std_logic
);
end component;
attribute syn_black_box : boolean;
attribute syn_tco1 : string;
attribute syn_black_box of RAM512X18: component is true;
attribute syn_tco1 of RAM512X18 : component is
"RCLK->RD17,RD16,RD15,RD14,RD13,RD12,RD11,RD10,RD9,RD8,RD7,RD6,RD5,RD4,RD3,RD2,RD1,RD0 = 3.0";
signal gnd, vcc : std_ulogic;
signal width : std_logic_vector(1 downto 0);
begin
gnd <= '0'; vcc <= '1';
width <= "10";
u0 : RAM512X18
port map (
RADDR0 => addrb(0), RADDR1 => addrb(1), RADDR2 => addrb(2), RADDR3 => addrb(3),
RADDR4 => addrb(4), RADDR5 => addrb(5), RADDR6 => addrb(6), RADDR7 => addrb(7),
RADDR8 => addrb(8),
WADDR0 => addra(0), WADDR1 => addra(1), WADDR2 => addra(2), WADDR3 => addra(3),
WADDR4 => addra(4), WADDR5 => addra(5), WADDR6 => addra(6), WADDR7 => addra(7),
WADDR8 => addra(8),
WD17 => di(17), WD16 => di(16), WD15 => di(15), WD14 => di(14), WD13 => di(13),
WD12 => di(12), WD11 => di(11), WD10 => di(10), WD9 => di(9),
WD8 => di(8), WD7 => di(7), WD6 => di(6), WD5 => di(5), WD4 => di(4),
WD3 => di(3), WD2 => di(2), WD1 => di(1), WD0 => di(0),
WEN => ena, PIPE => gnd, WW0 => width(0), WW1 => width(1),
REN => enb, RW0 => width(0), RW1 => width(1),
RESET => vcc, WCLK => clka, RCLK => clkb,
RD17 => do(17), RD16 => do(16), RD15 => do(15), RD14 => do(14), RD13 => do(13),
RD12 => do(12), RD11 => do(11), RD10 => do(10), RD9 => do(9),
RD8 => do(8), RD7 => do(7), RD6 => do(6), RD5 => do(5), RD4 => do(4),
RD3 => do(3), RD2 => do(2), RD1 => do(1), RD0 => do(0)
);
end;
library ieee;
use ieee.std_logic_1164.all;
entity proasic3_syncram_dp is
generic ( abits : integer := 6; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end;
architecture rtl of proasic3_syncram_dp is
component proasic3_ram4k9
generic (abits : integer range 9 to 12 := 9; dbits : integer := 9);
port (
addra, addrb : in std_logic_vector(abits -1 downto 0);
clka, clkb : in std_ulogic;
dia, dib : in std_logic_vector(dbits -1 downto 0);
doa, dob : out std_logic_vector(dbits -1 downto 0);
ena, enb : in std_ulogic;
wea, web : in std_ulogic);
end component;
constant dlen : integer := dbits + 9;
signal di1, di2, q1, q2 : std_logic_vector(dlen downto 0);
signal a1, a2 : std_logic_vector(12 downto 0);
signal en1, en2, we1, we2 : std_ulogic;
begin
di1(dbits-1 downto 0) <= datain1; di1(dlen downto dbits) <= (others => '0');
di2(dbits-1 downto 0) <= datain1; di2(dlen downto dbits) <= (others => '0');
a1(abits-1 downto 0) <= address1; a1(12 downto abits) <= (others => '0');
a2(abits-1 downto 0) <= address1; a2(12 downto abits) <= (others => '0');
dataout1 <= q1(dbits-1 downto 0); q1(dlen downto dbits) <= (others => '0');
dataout2 <= q2(dbits-1 downto 0); q2(dlen downto dbits) <= (others => '0');
en1 <= not enable1; en2 <= not enable2;
we1 <= not write1; we2 <= not write2;
a9 : if (abits <= 9) generate
x : for i in 0 to (dbits-1)/9 generate
u0 : proasic3_ram4k9 generic map (9, 9) port map (
a1(8 downto 0), a2(8 downto 0), clk1, clk2,
di1(i*9+8 downto i*9), di2(i*9+8 downto i*9),
q1(i*9+8 downto i*9), q2(i*9+8 downto i*9),
en1, en2, we1, we2);
end generate;
end generate;
a10 : if (abits = 10) generate
x : for i in 0 to (dbits-1)/4 generate
u0 : proasic3_ram4k9 generic map (10, 4) port map (
a1(9 downto 0), a2(9 downto 0), clk1, clk2,
di1(i*4+3 downto i*4), di2(i*4+3 downto i*4),
q1(i*4+3 downto i*4), q2(i*4+3 downto i*4),
en1, en2, we1, we2);
end generate;
end generate;
a11 : if (abits = 11) generate
x : for i in 0 to (dbits-1)/2 generate
u0 : proasic3_ram4k9 generic map (11, 2) port map (
a1(10 downto 0), a2(10 downto 0), clk1, clk2,
di1(i*2+1 downto i*2), di2(i*2+1 downto i*2),
q1(i*2+1 downto i*2), q2(i*2+1 downto i*2),
en1, en2, we1, we2);
end generate;
end generate;
a12 : if (abits = 12) generate
x : for i in 0 to (dbits-1) generate
u0 : proasic3_ram4k9 generic map (12, 1) port map (
a1(11 downto 0), a2(11 downto 0), clk1, clk2,
di1(i*1 downto i*1), di2(i*1 downto i*1),
q1(i*1 downto i*1), q2(i*1 downto i*1),
en1, en2, we1, we2);
end generate;
end generate;
-- pragma translate_off
unsup : if abits > 12 generate
x : process
begin
assert false
report "Address depth larger than 12 not supported for ProAsic3 rams"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
entity proasic3_syncram_2p is
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end;
architecture rtl of proasic3_syncram_2p is
component proasic3_ram4k9
generic (abits : integer range 9 to 12 := 9; dbits : integer := 9);
port (
addra, addrb : in std_logic_vector(abits -1 downto 0);
clka, clkb : in std_ulogic;
dia, dib : in std_logic_vector(dbits -1 downto 0);
doa, dob : out std_logic_vector(dbits -1 downto 0);
ena, enb : in std_ulogic;
wea, web : in std_ulogic);
end component;
component proasic3_ram512x18
port (
addra, addrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_ulogic;
di : in std_logic_vector(17 downto 0);
do : out std_logic_vector(17 downto 0);
ena, enb : in std_ulogic;
wea : in std_ulogic);
end component;
constant dlen : integer := dbits + 18;
signal di1, q2, gnd : std_logic_vector(dlen downto 0);
signal a1, a2 : std_logic_vector(12 downto 0);
signal en1, en2, we1, vcc : std_ulogic;
begin
vcc <= '1'; gnd <= (others => '0');
di1(dbits-1 downto 0) <= din; di1(dlen downto dbits) <= (others => '0');
a1(abits-1 downto 0) <= waddr; a1(12 downto abits) <= (others => '0');
a2(abits-1 downto 0) <= raddr; a2(12 downto abits) <= (others => '0');
dout <= q2(dbits-1 downto 0); q2(dlen downto dbits) <= (others => '0');
en1 <= not write; en2 <= not rena; we1 <= not write;
a8 : if (abits <= 8) generate
x : for i in 0 to (dbits-1)/18 generate
u0 : proasic3_ram512x18 port map (
a1(8 downto 0), a2(8 downto 0), wclk, rclk,
di1(i*18+17 downto i*18), q2(i*18+17 downto i*18),
en1, en2, we1);
end generate;
end generate;
a9 : if (abits = 9) generate
x : for i in 0 to (dbits-1)/9 generate
u0 : proasic3_ram4k9 generic map (9, 9) port map (
a1(8 downto 0), a2(8 downto 0), wclk, rclk,
di1(i*9+8 downto i*9), gnd(8 downto 0),
open, q2(i*9+8 downto i*9),
en1, en2, we1, vcc);
end generate;
end generate;
a10 : if (abits = 10) generate
x : for i in 0 to (dbits-1)/4 generate
u0 : proasic3_ram4k9 generic map (10, 4) port map (
a1(9 downto 0), a2(9 downto 0), wclk, rclk,
di1(i*4+3 downto i*4), gnd(3 downto 0),
open, q2(i*4+3 downto i*4),
en1, en2, we1, vcc);
end generate;
end generate;
a11 : if (abits = 11) generate
x : for i in 0 to (dbits-1)/2 generate
u0 : proasic3_ram4k9 generic map (11, 2) port map (
a1(10 downto 0), a2(10 downto 0), wclk, rclk,
di1(i*2+1 downto i*2), gnd(1 downto 0),
open, q2(i*2+1 downto i*2),
en1, en2, we1, vcc);
end generate;
end generate;
a12 : if (abits = 12) generate
x : for i in 0 to (dbits-1) generate
u0 : proasic3_ram4k9 generic map (12, 1) port map (
a1(11 downto 0), a2(11 downto 0), wclk, rclk,
di1(i*1 downto i*1), gnd(0 downto 0),
open, q2(i*1 downto i*1),
en1, en2, we1, vcc);
end generate;
end generate;
-- pragma translate_off
unsup : if abits > 12 generate
x : process
begin
assert false
report "Address depth larger than 12 not supported for ProAsic3 rams"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
entity proasic3_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture rtl of proasic3_syncram is
component proasic3_syncram_dp
generic ( abits : integer := 6; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component proasic3_syncram_2p
generic ( abits : integer := 8; dbits : integer := 32);
port (
rclk : in std_ulogic;
rena : in std_ulogic;
raddr : in std_logic_vector (abits -1 downto 0);
dout : out std_logic_vector (dbits -1 downto 0);
wclk : in std_ulogic;
waddr : in std_logic_vector (abits -1 downto 0);
din : in std_logic_vector (dbits -1 downto 0);
write : in std_ulogic);
end component;
signal gnd : std_logic_vector(abits+dbits downto 0);
begin
gnd <= (others => '0');
r2p : if abits <= 8 generate
u0 : proasic3_syncram_2p generic map (abits, dbits)
port map (clk, enable, address, dataout, clk, address, datain, write);
end generate;
rdp : if abits > 8 generate
u0 : proasic3_syncram_dp generic map (abits, dbits)
port map (clk, address, datain, dataout, enable, write,
clk, gnd(abits-1 downto 0), gnd(dbits-1 downto 0), open, gnd(0), gnd(0));
end generate;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity display is
port (
clk : in std_logic;
rst_n : in std_logic;
twochars : in std_logic_vector(15 downto 0)
);
end display;
architecture behavior of display is
signal disp_ena : std_logic;
signal column : integer;
signal row : integer;
signal col2x : unsigned(9 downto 0);
signal row2x : unsigned(9 downto 0);
signal ucol : unsigned(9 downto 0);
signal urow : unsigned(9 downto 0);
signal tileaddress : std_logic_vector(10 downto 0);
signal char : std_logic_vector(7 downto 0);
signal char_row : std_logic_vector(7 downto 0);
begin
-- 8x8 bitmap is upscaled 2x
ucol <= to_unsigned(column, 10);
urow <= to_unsigned(row, 10);
col2x <= shift_right(urow, 1);
row2x <= shift_right(ucol, 1);
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 17;
constant bytes : integer := 89996;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= romdata;
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= romdata;
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"88100000";
when 16#00001# => romdata <= X"09100031";
when 16#00002# => romdata <= X"81C12314";
when 16#00003# => romdata <= X"01000000";
when 16#00004# => romdata <= X"A1480000";
when 16#00005# => romdata <= X"A7500000";
when 16#00006# => romdata <= X"10800836";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 17;
constant bytes : integer := 89996;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= romdata;
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= romdata;
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"88100000";
when 16#00001# => romdata <= X"09100031";
when 16#00002# => romdata <= X"81C12314";
when 16#00003# => romdata <= X"01000000";
when 16#00004# => romdata <= X"A1480000";
when 16#00005# => romdata <= X"A7500000";
when 16#00006# => romdata <= X"10800836";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 17;
constant bytes : integer := 89996;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= romdata;
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= romdata;
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"88100000";
when 16#00001# => romdata <= X"09100031";
when 16#00002# => romdata <= X"81C12314";
when 16#00003# => romdata <= X"01000000";
when 16#00004# => romdata <= X"A1480000";
when 16#00005# => romdata <= X"A7500000";
when 16#00006# => romdata <= X"10800836";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 17;
constant bytes : integer := 89996;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= romdata;
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= romdata;
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"88100000";
when 16#00001# => romdata <= X"09100031";
when 16#00002# => romdata <= X"81C12314";
when 16#00003# => romdata <= X"01000000";
when 16#00004# => romdata <= X"A1480000";
when 16#00005# => romdata <= X"A7500000";
when 16#00006# => romdata <= X"10800836";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 17;
constant bytes : integer := 89996;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= romdata;
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= romdata;
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"88100000";
when 16#00001# => romdata <= X"09100031";
when 16#00002# => romdata <= X"81C12314";
when 16#00003# => romdata <= X"01000000";
when 16#00004# => romdata <= X"A1480000";
when 16#00005# => romdata <= X"A7500000";
when 16#00006# => romdata <= X"10800836";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 17;
constant bytes : integer := 89996;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= romdata;
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= romdata;
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"88100000";
when 16#00001# => romdata <= X"09100031";
when 16#00002# => romdata <= X"81C12314";
when 16#00003# => romdata <= X"01000000";
when 16#00004# => romdata <= X"A1480000";
when 16#00005# => romdata <= X"A7500000";
when 16#00006# => romdata <= X"10800836";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 22-05-2016
-- Module Name: main.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity main is
port (DDR_addr : inout STD_LOGIC_VECTOR (14 downto 0);
DDR_ba : inout STD_LOGIC_VECTOR (2 downto 0);
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR (3 downto 0);
DDR_dq : inout STD_LOGIC_VECTOR (31 downto 0);
DDR_dqs_n : inout STD_LOGIC_VECTOR (3 downto 0);
DDR_dqs_p : inout STD_LOGIC_VECTOR (3 downto 0);
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR (53 downto 0);
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FSM_clk : in std_logic);
end entity;
architecture structural of main is
component FSM is
port (start_state : in std_logic_vector(3 downto 0);
end_state : out std_logic_vector(3 downto 0);
str : in std_logic_vector(31 downto 0);
enable, clk : in std_logic;
done : out std_logic);
end component;
component base_zynq_design_wrapper
port (DDR_addr : inout STD_LOGIC_VECTOR (14 downto 0);
DDR_ba : inout STD_LOGIC_VECTOR (2 downto 0);
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR (3 downto 0);
DDR_dq : inout STD_LOGIC_VECTOR (31 downto 0);
DDR_dqs_n : inout STD_LOGIC_VECTOR (3 downto 0);
DDR_dqs_p : inout STD_LOGIC_VECTOR (3 downto 0);
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR (53 downto 0);
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
gpio_rtl_0 : out STD_LOGIC_VECTOR ( 31 downto 0 );
gpio_rtl_1_i : in STD_LOGIC_VECTOR ( 9 downto 0 );
gpio_rtl_1_o : out STD_LOGIC_VECTOR ( 9 downto 0 ));
end component;
signal gpio_rtl_1_i : std_logic_vector (9 downto 0);
signal gpio_rtl_1_o : std_logic_vector (9 downto 0);
signal gpio_rtl_0 : std_logic_vector (31 downto 0);
signal start_state, end_state : std_logic_vector (3 downto 0);
signal str : std_logic_vector (31 downto 0);
signal enable : std_logic;
signal done : std_logic;
begin
start_state <= gpio_rtl_1_o (3 downto 0);
gpio_rtl_1_i (8 downto 5) <= end_state;
str <= gpio_rtl_0;
enable <= gpio_rtl_1_o (4);
gpio_rtl_1_i (9) <= done;
FSM_i: component FSM
port map (start_state, end_state, str, enable, FSM_clk, done);
base_zynq_design_wrapper_i: component base_zynq_design_wrapper
port map (DDR_addr, DDR_ba, DDR_cas_n, DDR_ck_n, DDR_ck_p, DDR_cke, DDR_cs_n,
DDR_dm, DDR_dq, DDR_dqs_n, DDR_dqs_p, DDR_odt, DDR_ras_n,
DDR_reset_n, DDR_we_n, FIXED_IO_ddr_vrn, FIXED_IO_ddr_vrp, FIXED_IO_mio,
FIXED_IO_ps_clk, FIXED_IO_ps_porb, FIXED_IO_ps_srstb, gpio_rtl_0, gpio_rtl_1_i, gpio_rtl_1_o);
end architecture;
|
entity textio2 is
end entity;
use std.textio.all;
architecture test of textio2 is
begin
process is
file tmp : text;
variable l : line;
variable str : string(1 to 5);
variable good : boolean;
variable ch : character;
begin
file_open(tmp, "tmp.txt", WRITE_MODE);
write(l, string'("hello, world"));
writeline(tmp, l);
write(l, string'("second"));
writeline(tmp, l);
file_close(tmp);
file_open(tmp, "tmp.txt", READ_MODE);
readline(tmp, l);
read(l, str);
assert str = "hello";
read(l, str);
assert str = ", wor";
read(l, str, good);
assert not good; -- Fewer than 5 chars
readline(tmp, l);
read(l, str);
assert str = "secon";
read(l, ch);
assert ch = 'd';
read(l, ch, good);
assert not good;
file_close(tmp);
wait;
end process;
end architecture;
|
entity textio2 is
end entity;
use std.textio.all;
architecture test of textio2 is
begin
process is
file tmp : text;
variable l : line;
variable str : string(1 to 5);
variable good : boolean;
variable ch : character;
begin
file_open(tmp, "tmp.txt", WRITE_MODE);
write(l, string'("hello, world"));
writeline(tmp, l);
write(l, string'("second"));
writeline(tmp, l);
file_close(tmp);
file_open(tmp, "tmp.txt", READ_MODE);
readline(tmp, l);
read(l, str);
assert str = "hello";
read(l, str);
assert str = ", wor";
read(l, str, good);
assert not good; -- Fewer than 5 chars
readline(tmp, l);
read(l, str);
assert str = "secon";
read(l, ch);
assert ch = 'd';
read(l, ch, good);
assert not good;
file_close(tmp);
wait;
end process;
end architecture;
|
entity textio2 is
end entity;
use std.textio.all;
architecture test of textio2 is
begin
process is
file tmp : text;
variable l : line;
variable str : string(1 to 5);
variable good : boolean;
variable ch : character;
begin
file_open(tmp, "tmp.txt", WRITE_MODE);
write(l, string'("hello, world"));
writeline(tmp, l);
write(l, string'("second"));
writeline(tmp, l);
file_close(tmp);
file_open(tmp, "tmp.txt", READ_MODE);
readline(tmp, l);
read(l, str);
assert str = "hello";
read(l, str);
assert str = ", wor";
read(l, str, good);
assert not good; -- Fewer than 5 chars
readline(tmp, l);
read(l, str);
assert str = "secon";
read(l, ch);
assert ch = 'd';
read(l, ch, good);
assert not good;
file_close(tmp);
wait;
end process;
end architecture;
|
entity textio2 is
end entity;
use std.textio.all;
architecture test of textio2 is
begin
process is
file tmp : text;
variable l : line;
variable str : string(1 to 5);
variable good : boolean;
variable ch : character;
begin
file_open(tmp, "tmp.txt", WRITE_MODE);
write(l, string'("hello, world"));
writeline(tmp, l);
write(l, string'("second"));
writeline(tmp, l);
file_close(tmp);
file_open(tmp, "tmp.txt", READ_MODE);
readline(tmp, l);
read(l, str);
assert str = "hello";
read(l, str);
assert str = ", wor";
read(l, str, good);
assert not good; -- Fewer than 5 chars
readline(tmp, l);
read(l, str);
assert str = "secon";
read(l, ch);
assert ch = 'd';
read(l, ch, good);
assert not good;
file_close(tmp);
wait;
end process;
end architecture;
|
-- file: timer_exdes.vhd
--
-- (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity timer_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1)
);
end timer_exdes;
architecture xilinx of timer_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Number of counters
constant NUM_C : integer := 2;
-- Array typedef
type ctrarr is array (1 to NUM_C) of std_logic_vector(C_W-1 downto 0);
-- Reset for counters when lock status changes
signal reset_int : std_logic := '0';
-- Declare the clocks and counters
signal clk : std_logic_vector(NUM_C downto 1);
signal clk_int : std_logic_vector(NUM_C downto 1);
signal counter : ctrarr := (( others => (others => '0')));
component timer is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic
);
end component;
begin
-- Create reset for the counters
reset_int <= COUNTER_RESET;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : timer
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Clock out ports
CLK_OUT1 => clk_int(1),
CLK_OUT2 => clk_int(2));
-- Connect the output clocks to the design
-------------------------------------------
clk(1) <= clk_int(1);
clk(2) <= clk_int(2);
-- Output clock sampling
-------------------------------------
counters: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen)) begin
if (rising_edge(clk(count_gen))) then
if (reset_int = '1') then
counter(count_gen) <= (others => '0') after TCQ;
else
counter(count_gen) <= counter(count_gen) + 1 after TCQ;
end if;
end if;
end process;
-- alias the high bit of each counter to the corresponding
-- bit in the output bus
COUNT(count_gen) <= counter(count_gen)(C_W-1);
end generate counters;
end xilinx;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/RADIX22FFT_SDNF2_2_block3.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_2_block3
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/RADIX22FFT_SDNF2_2
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_2_block3 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
rotate_9 : IN std_logic; -- ufix1
dout_2_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_9_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_9_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_re_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_10_im_1 : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_2_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_2_block3;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_2_block3 IS
-- Signals
SIGNAL dout_2_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_2_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_10_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_10_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL dout_9_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_9_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_10_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_10_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
BEGIN
dout_2_re_signed <= signed(dout_2_re);
dout_2_im_signed <= signed(dout_2_im);
dout_10_re_signed <= signed(dout_10_re);
dout_10_im_signed <= signed(dout_10_im);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, dout_2_re_signed, dout_2_im_signed,
dout_10_re_signed, dout_10_im_signed, dout_1_vld, rotate_9)
VARIABLE add_cast : signed(16 DOWNTO 0);
VARIABLE add_cast_0 : signed(16 DOWNTO 0);
VARIABLE add_cast_1 : signed(16 DOWNTO 0);
VARIABLE add_cast_2 : signed(16 DOWNTO 0);
VARIABLE sub_cast : signed(16 DOWNTO 0);
VARIABLE sub_cast_0 : signed(16 DOWNTO 0);
VARIABLE sub_cast_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp : signed(16 DOWNTO 0);
VARIABLE add_cast_3 : signed(16 DOWNTO 0);
VARIABLE add_cast_4 : signed(16 DOWNTO 0);
VARIABLE add_cast_5 : signed(16 DOWNTO 0);
VARIABLE add_cast_6 : signed(16 DOWNTO 0);
VARIABLE sra_temp_0 : signed(16 DOWNTO 0);
VARIABLE sub_cast_3 : signed(16 DOWNTO 0);
VARIABLE sub_cast_4 : signed(16 DOWNTO 0);
VARIABLE sub_cast_5 : signed(16 DOWNTO 0);
VARIABLE sub_cast_6 : signed(16 DOWNTO 0);
VARIABLE sra_temp_1 : signed(16 DOWNTO 0);
VARIABLE sra_temp_2 : signed(16 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_9 /= '0' THEN
IF dout_1_vld = '1' THEN
add_cast_1 := resize(dout_2_re_signed, 17);
add_cast_2 := resize(dout_10_im_signed, 17);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(dout_2_re_signed, 17);
sub_cast_2 := resize(dout_10_im_signed, 17);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast_1 - sub_cast_2;
add_cast_5 := resize(dout_2_im_signed, 17);
add_cast_6 := resize(dout_10_re_signed, 17);
Radix22ButterflyG2_NF_btf2_im_reg_next <= add_cast_5 + add_cast_6;
sub_cast_5 := resize(dout_2_im_signed, 17);
sub_cast_6 := resize(dout_10_re_signed, 17);
Radix22ButterflyG2_NF_btf1_im_reg_next <= sub_cast_5 - sub_cast_6;
END IF;
ELSIF dout_1_vld = '1' THEN
add_cast := resize(dout_2_re_signed, 17);
add_cast_0 := resize(dout_10_re_signed, 17);
Radix22ButterflyG2_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(dout_2_re_signed, 17);
sub_cast_0 := resize(dout_10_re_signed, 17);
Radix22ButterflyG2_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_3 := resize(dout_2_im_signed, 17);
add_cast_4 := resize(dout_10_im_signed, 17);
Radix22ButterflyG2_NF_btf1_im_reg_next <= add_cast_3 + add_cast_4;
sub_cast_3 := resize(dout_2_im_signed, 17);
sub_cast_4 := resize(dout_10_im_signed, 17);
Radix22ButterflyG2_NF_btf2_im_reg_next <= sub_cast_3 - sub_cast_4;
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_re_reg, 1);
dout_9_re_tmp <= sra_temp(15 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_im_reg, 1);
dout_9_im_tmp <= sra_temp_0(15 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_re_reg, 1);
dout_10_re_tmp <= sra_temp_1(15 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_im_reg, 1);
dout_10_im_tmp <= sra_temp_2(15 DOWNTO 0);
dout_2_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_9_re <= std_logic_vector(dout_9_re_tmp);
dout_9_im <= std_logic_vector(dout_9_im_tmp);
dout_10_re_1 <= std_logic_vector(dout_10_re_tmp);
dout_10_im_1 <= std_logic_vector(dout_10_im_tmp);
END rtl;
|
----------------------------------------------------------------------------------
--
-- Commodore 64 on Zybo
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--
-- C64 ROM includes (NOT INCLUDED)
-- See python scripts for converting ROM images to VHDL files.
-- Import the generated sources into a library called "c64roms"
--
library c64roms;
use c64roms.p_char_rom.all; -- for char_rom(addr[11:0]) return byte[7:0]
use c64roms.p_basic_rom.all; -- for basic_rom(addr[12:0]) return byte[7:0]
use c64roms.p_kernal_rom.all; -- for kernal_rom(addr[12:0]) return byte[7:0]
entity chip_test is
port (
clk_125 : in std_logic;
-- audio configure
ac_scl : inout std_logic;
ac_sda : inout std_logic;
-- audio signal
ac_muten : out std_logic;
ac_mclk : out std_logic;
ac_bclk : out std_logic;
ac_pbdat : out std_logic;
ac_pblrc : out std_logic;
ac_recdat : in std_logic;
ac_reclrc : in std_logic;
-- report error in configuring audio
led : out std_logic_vector(3 downto 0);
-- to test waveforms
sw : in std_logic_vector(3 downto 0);
-- for freq/wvfm ramping tests
btn : in std_logic_vector(3 downto 0);
vga_hs : out std_logic;
vga_vs : out std_logic;
vga_r : out std_logic_vector(4 downto 0);
vga_g : out std_logic_vector(5 downto 0);
vga_b : out std_logic_vector(4 downto 0)
);
end chip_test;
architecture testing of chip_test is
component clk_wiz_0
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk160 : out std_logic;
clk20ph1 : out std_logic;
clk20ph2 : out std_logic;
clk20ph3 : out std_logic;
clk20ph4 : out std_logic;
-- Status and control signals
reset : in std_logic;
locked : out std_logic
);
end component;
component clk_wiz_1
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk12 : out std_logic;
-- Status and control signals
reset : in std_logic;
locked : out std_logic
);
end component;
signal clk12 : std_logic;
signal clk160 : std_logic;
signal clk_lk1 : std_logic;
signal clk_lk2 : std_logic;
signal clk20p000 : std_logic;
signal clk20p010 : std_logic;
signal clk20p100 : std_logic;
signal clk20p110 : std_logic;
signal clk20_ph1 : std_logic;
signal clk20_ph2 : std_logic;
component blk_ram_64k
port (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end component;
component blk_cram
port (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
end component;
subtype pair is std_logic_vector(1 downto 0);
subtype slv3 is std_logic_vector(2 downto 0);
subtype nybble is std_logic_vector(3 downto 0);
subtype slv5 is std_logic_vector(4 downto 0);
subtype u5 is unsigned(4 downto 0);
subtype slv6 is std_logic_vector(5 downto 0);
subtype slv7 is std_logic_vector(6 downto 0);
subtype byte is std_logic_vector(7 downto 0);
subtype ubyte is unsigned(7 downto 0);
subtype slv9 is std_logic_vector(8 downto 0);
subtype slv10 is std_logic_vector(9 downto 0);
subtype slv14 is std_logic_vector(13 downto 0);
subtype word is std_logic_vector(15 downto 0);
subtype u16 is unsigned(15 downto 0);
subtype s16 is signed(15 downto 0);
subtype slv20 is std_logic_vector(19 downto 0);
subtype slv24 is std_logic_vector(23 downto 0);
subtype slv27 is std_logic_vector(26 downto 0); -- I2C SSM2603 send with ACK pads
signal res0 : std_logic;
signal res1 : std_logic;
signal cpu_r1w0 : std_logic:='1';
signal cpu_r0w1 : std_logic;
component sid6581 is
port (
res0 : in std_logic;
ph2 : in std_logic;
rga : in std_logic_vector(4 downto 0);
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0);
r1w0 : in std_logic;
s16audio : out signed(15 downto 0)
);
end component;
signal bclk_cnt : pair;
alias bclk_ref : std_logic is bclk_cnt(0);--1
signal audio_frame : u5;
signal hold_sam : s16;
signal hold2 : s16;
function buf_max(frm : u5) return boolean is
begin
case frm is
when "11111" => return true;
when others => return false;
end case;
end buf_max;
function adv_frame(frm: u5) return u5 is
begin
case frm is
when "00000" => return "00001";
when "00001" => return "00010";
when "00010" => return "00011";
when "00011" => return "00100";
when "00100" => return "00101";
when "00101" => return "00110";
when "00110" => return "00111";
when "00111" => return "01000";
when "01000" => return "01001";
when "01001" => return "01010";
when "01010" => return "01011";
when "01011" => return "01100";
when "01100" => return "01101";
when "01101" => return "01110";
when "01110" => return "01111";
when "01111" => return "10000";
when "10000" => return "10001";
when "10001" => return "10010";
when "10010" => return "10011";
when "10011" => return "10100";
when "10100" => return "10101";
when "10101" => return "10110";
when "10110" => return "10111";
when "10111" => return "11000";
when "11000" => return "11001";
when "11001" => return "11010";
when "11010" => return "11011";
when "11011" => return "11100";
when "11100" => return "11101";
when "11101" => return "11110";
when "11110" => return "11111";
when "11111" => return "00000";
when others => return "00000";
end case;
end adv_frame;
signal sid1_rga : slv5;
signal sid1_dw : byte;
signal sid1_dr : byte;
signal sid1_out : s16;
signal sid1_r1w0 : std_logic;
component vic_ii is
port (
-- register access
rga : in std_logic_vector(5 downto 0);
rgdi : in std_logic_vector(7 downto 0);
rgdo : out std_logic_vector(7 downto 0);
r1w0 : in std_logic;
-- video access
va : out std_logic_vector(13 downto 0);
vd : in std_logic_vector(7 downto 0);
cd : in std_logic_vector(3 downto 0);
-- bus mastering
cpu_clk : out std_logic; -- 4 MHz CPU clock
cpu_ben : out std_logic; -- 1=CPU on buses
vic_ben : out std_logic; -- 1=VIC on buses
bus_ph0 : out std_logic; -- master PH0 clock
bus_ph1 : out std_logic; -- master PH1 clock
bus_ph2 : out std_logic; -- master PH2 clock
res0 : in std_logic; -- reset (low)
-- external signals
clk20_ph1 : in std_logic;
clk20_ph2 : in std_logic;
vhs : out std_logic;
vvs : out std_logic;
vr : out std_logic_vector(4 downto 0);
vg : out std_logic_vector(5 downto 0);
vb : out std_logic_vector(4 downto 0)
);
end component;
signal bankctl : slv5 := "11111";
alias exrom : std_logic is bankctl(4);
alias game : std_logic is bankctl(3);
alias charen : std_logic is bankctl(2);
alias hiram : std_logic is bankctl(1);
alias loram : std_logic is bankctl(0);
signal abus : word;
signal rama : word;
signal cpudo : byte;
signal cpudi : byte;
signal r1w0 : std_logic;
signal ram_clk : std_logic;
signal ramclk_init : std_logic := '0';
signal ramclk_cpu : std_logic := '0';
signal ramclk_vic : std_logic := '0';
signal ram_r1w0 : std_logic := '1';
signal ram_r0w1 : std_logic;
signal cram_r1w0 : std_logic := '1';
signal cram_r0w1 : std_logic;
signal ramdr : byte;
signal ramdw : byte;
signal ramen : std_logic := '1';
signal cramdr : nybble;
signal cramdw : nybble;
signal cramen : std_logic := '1';
signal vbank : pair := "00";
signal vic_rga : slv6;
signal vic_regw : byte;
signal vic_regr : byte;
signal vic_r1w0 : std_logic := '1';
signal cpu_ph1 : std_logic;
signal cpu_ph2 : std_logic;
signal vmem_clk : std_logic;
signal vic_ca : slv10;
signal vic_cd : nybble;
signal vic_wcd : nybble;
signal vic_va : slv14;
signal vic_vd : byte;
signal vic_wvd : byte;
signal cpu_on : std_logic;
signal vic_on : std_logic;
signal cpu_ph4x : std_logic;
function catoi(src: slv10) return integer is
begin
return to_integer(unsigned(src));
end catoi;
function vatoi(src: word) return integer is
begin
return to_integer(unsigned(src));
end vatoi;
function xtov6(src: byte) return slv6 is
begin
return src(5 downto 0);
end xtov6;
function xtov5(src: byte) return slv5 is
begin
return src(4 downto 0);
end xtov5;
type mbank_t is (
mbk_ram,
mbk_cram,
mbk_lorom,
mbk_hirom,
mbk_xio2,
mbk_xio1,
mbk_cia2,
mbk_cia1,
mbk_cgrom,
mbk_sid,
mbk_vic
);
function init_bank(addr:u16) return mbank_t is
begin
if (addr(15 downto 10) = "110110") then
return mbk_cram;
else
return mbk_ram;
end if;
end init_bank;
function cpu_bank(addr: u16; bsel: slv5) return mbank_t is
variable b3 : slv3;
variable bb0 : std_logic;
variable ce : std_logic;
variable n3 : nybble;
begin
b3 := bsel(2 downto 0);
bb0 := bsel(1) nor bsel(0);
ce := bsel(2);
n3 := nybble(addr(11 downto 8));
if (addr >= x"e000") then
if (bsel(1)='1') then
return mbk_hirom;
else
return mbk_ram;
end if;
elsif (addr >= x"d000" and addr < x"e000") then
if (bb0 = '1') then
return mbk_ram;
else
if (ce = '0') then
return mbk_cgrom;
else
case n3 is
when x"f" =>
return mbk_xio2;
when x"e" =>
return mbk_xio1;
when x"d" =>
return mbk_cia2;
when x"c" =>
return mbk_cia1;
when x"b" =>
return mbk_cram;
when x"a" =>
return mbk_cram;
when x"9" =>
return mbk_cram;
when x"8" =>
return mbk_cram;
when x"7" =>
return mbk_sid;
when x"6" =>
return mbk_sid;
when x"5" =>
return mbk_sid;
when x"4" =>
return mbk_sid;
when x"3" =>
return mbk_vic;
when x"2" =>
return mbk_vic;
when x"1" =>
return mbk_vic;
when x"0" =>
return mbk_vic;
when others =>
return mbk_ram;
end case;
end if;
end if;
elsif (addr >= x"a000" and addr < x"c000") then
if ((bsel(1) and bsel(0)) = '1') then
return mbk_lorom;
else
return mbk_ram;
end if;
else
return mbk_ram;
end if;
end cpu_bank;
function bank_is_writethru(addr:word; bsel:slv5) return std_logic is
begin
case cpu_bank(u16(addr),bsel) is
when mbk_ram => return '1';
when mbk_cram => return '1';
when mbk_lorom => return '1';
when mbk_hirom => return '1';
when others => return '0';
end case;
end bank_is_writethru;
type init_t is (
initram_wait, initram_xfer, initram_idle);
signal init_stg : init_t := initram_wait;
constant init_wait_to : u16 := x"0014";
signal init_counter : u16 := x"0000";
signal init_addr : word;
signal init_data : byte;
signal init_r1w0 : std_logic := '1';
signal init_r0w1 : std_logic;
function ram_init(lin: u16) return slv24 is
begin
case lin is
when x"0000" => return x"0400" & x"08";
when x"0001" => return x"0401" & x"05";
when x"0002" => return x"0402" & x"0c";
when x"0003" => return x"0403" & x"0c";
when x"0004" => return x"0404" & x"0f";
when x"0005" => return x"0405" & x"2c";
when x"0006" => return x"0406" & x"20";
when x"0007" => return x"0407" & x"17";
when x"0008" => return x"0408" & x"0f";
when x"0009" => return x"0409" & x"12";
when x"000a" => return x"040a" & x"0c";
when x"000b" => return x"040b" & x"04";
when x"000c" => return x"040c" & x"21";
when x"000d" => return x"040d" & x"20";
when x"000e" => return x"05f2" & x"3a";
when x"000f" => return x"05f3" & x"3a";
when x"0010" => return x"05f4" & x"3a";
when x"0011" => return x"05f5" & x"3a";
when x"0012" => return x"07de" & x"30";
when x"0013" => return x"07df" & x"31";
when x"0014" => return x"07e0" & x"32";
when x"0015" => return x"07e1" & x"33";
when x"0016" => return x"07e2" & x"34";
when x"0017" => return x"07e3" & x"35";
when x"0018" => return x"07e4" & x"36";
when x"0019" => return x"07e5" & x"37";
when x"001a" => return x"07e6" & x"38";
when x"001b" => return x"07e7" & x"39";
when x"001c" => return x"d800" & x"01";
when x"001d" => return x"d801" & x"02";
when x"001e" => return x"d802" & x"03";
when x"001f" => return x"d803" & x"04";
when x"0020" => return x"d804" & x"05";
when x"0021" => return x"d805" & x"07";
when x"0022" => return x"d806" & x"0e";
when x"0023" => return x"d807" & x"08";
when x"0024" => return x"d808" & x"09";
when x"0025" => return x"d809" & x"0a";
when x"0026" => return x"d80a" & x"0b";
when x"0027" => return x"d80b" & x"0c";
when x"0028" => return x"d80c" & x"0d";
when x"0029" => return x"d80d" & x"0e";
when x"002a" => return x"d9f2" & x"01";
when x"002b" => return x"d9f3" & x"01";
when x"002c" => return x"d9f4" & x"01";
when x"002d" => return x"d9f5" & x"01";
when x"002e" => return x"dbde" & x"05";
when x"002f" => return x"dbdf" & x"07";
when x"0030" => return x"dbe0" & x"0d";
when x"0031" => return x"dbe1" & x"09";
when x"0032" => return x"dbe2" & x"08";
when x"0033" => return x"dbe3" & x"0a";
when x"0034" => return x"dbe4" & x"0b";
when x"0035" => return x"dbe5" & x"0c";
when x"0036" => return x"dbe6" & x"0f";
when x"0037" => return x"dbe7" & x"0e";
when others => return x"0000" & x"00"; -- 0 (and 1) inaccessible on C64
end case;
end ram_init;
constant ram_init_count : u16 := x"0038";
-- for initial settings for vic/sid
signal c_cycle : ubyte := x"00";
--
-- For setting the SSM2603 via I2C
--
function dac_init(lin : ubyte) return slv20 is
begin
case lin is
when x"00" => return x"06" & x"010";
when x"01" => return x"02" & x"075";
when x"02" => return x"03" & x"075";
when x"03" => return x"04" & x"010";
when x"04" => return x"05" & x"000";
when x"05" => return x"07" & x"001";
when x"06" => return x"09" & x"001";
when x"07" => return x"06" & x"000";
when others => return x"ff" & x"fff";
end case;
end dac_init;
component i2c_xcvr port
(
-- with 1 MHz clock SSM2603 reg 9 delay step is 65.535 ms:
clk1M : in std_logic;
-- tie to system reset
res0 : in std_logic;
-- initialization line number
init_line : out unsigned(7 downto 0);
-- initialization data xRRRRRRRxxxxxxxDDDDDDDDD
init_data : in std_logic_vector(19 downto 0);
-- error status
error : out std_logic;
-- tie directly to ac_scl and ac_sda accordingly:
scl : inout std_logic;
sda : inout std_logic
);
end component;
signal ssm_init_line : ubyte;
signal ssm_init_data : slv20;
signal ssm_error : std_logic;
-- 3-bit counter for dividing 160 MHz into 8-phase 20 MHz clocks
signal clk20_ph : slv3;
function c20_next(src: slv3) return slv3 is
begin
case src is
when "000" => return "001";
when "001" => return "010";
when "010" => return "011";
when "011" => return "100";
when "100" => return "101";
when "101" => return "110";
when "110" => return "111";
when "111" => return "000";
when others => return "000";
end case;
end c20_next;
function vbk_cgrom(bk: pair; adr: slv14) return std_logic is
variable vsel : slv3;
begin
vsel := bk(0) & adr(13 downto 12);
case vsel is
when "001" => return '1';
when others => return '0';
end case;
end vbk_cgrom;
subtype u12 is unsigned(11 downto 0);
signal reset_wait : u12 := x"000";
constant reset_delay : u12 := x"0fb"; -- number of 125 MHz clocks in 2000 ns
signal cgrom_data : byte;
signal lorom_data : byte;
signal hirom_data : byte;
--
-- Architectural implementation
--
begin
--
-- Coldstart reset for 2000 ns
--
initial_reset: process(clk_125, reset_wait) is -- counts up to 2000 ns
variable not_yet : boolean;
begin
not_yet := (reset_wait < reset_delay);
if rising_edge(clk_125) then
if not_yet then
reset_wait <= reset_wait + 1;
end if;
end if;
if not_yet then -- drive reset accordingly
res0 <= '0';
else
res0 <= '1';
end if;
end process initial_reset;
pixclock: clk_wiz_0 port map (
-- Clock out ports
clk160 => clk160,
clk20ph1 => clk20p010,
clk20ph2 => clk20p100,
clk20ph3 => clk20p110,
clk20ph4 => clk20p000,
-- Status and control signals
reset => res1,
locked => clk_lk1,
-- Clock in ports
clk_in1 => clk_125
);
clk20gen: process(clk160) is
--clk20gen: process(clk20p000,clk20p010,clk20p100,clk20p110) is
variable cnext : slv3;
begin
if (rising_edge(clk160)) then
cnext := c20_next(clk20_ph);
clk20_ph <= cnext;
clk20_ph1 <= cnext(2) and (cnext(1) nor cnext(0));
clk20_ph2 <= not (cnext(2) or cnext(1) or cnext(0));
end if;
--if ( rising_edge(clk20p000)) then
-- clk20_ph <= "000";
--end if;
--if (falling_edge(clk20p000)) then
-- clk20_ph <= "001";
--end if;
--if ( rising_edge(clk20p010)) then
-- clk20_ph <= "010";
--end if;
--if (falling_edge(clk20p010)) then
-- clk20_ph <= "011";
--end if;
--if ( rising_edge(clk20p100)) then
-- clk20_ph <= "100";
--end if;
--if (falling_edge(clk20p100)) then
-- clk20_ph <= "101";
--end if;
--if ( rising_edge(clk20p110)) then
-- clk20_ph <= "110";
--end if;
--if (falling_edge(clk20p110)) then
-- clk20_ph <= "111";
--end if;
end process clk20gen;
--clk20_ph1 <= clk20p100;
--clk20_ph2 <= clk20p000;
--cgrom_latch: process(clk20_ph1,ram_clk) is
--begin
-- if rising_edge(ram_clk) then
-- cgrom_data <= char_rom(rama(11 downto 0));
-- end if;
--end process cgrom_latch;
init_ram: process(clk160,clk20_ph,init_stg) is
begin
if rising_edge(clk160) then
if (init_stg = initram_xfer and (clk20_ph >= "110" and clk20_ph <= "111")) then
init_r1w0 <= '0';
else
init_r1w0 <= '1';
end if;
if (clk20_ph = "011") then
case init_stg is
when initram_wait =>
if (init_counter = init_wait_to) then
init_counter <= x"0000";
init_stg <= initram_xfer;
init_addr <= x"ffff";
init_data <= x"ff";
else
init_counter <= init_counter + 1;
end if;
when initram_xfer =>
if (init_counter = ram_init_count) then
init_counter <= x"0000";
init_stg <= initram_idle;
else
init_addr <= ram_init(init_counter)(23 downto 8);
init_data <= ram_init(init_counter)(7 downto 0);
init_counter <= init_counter + 1;
end if;
when others =>
null;
end case;
end if;
end if;
end process init_ram;
sndclock: clk_wiz_1 port map (
-- Clock out ports
clk12 => clk12,
-- Status and control signals
reset => res1,
locked => clk_lk2,
-- Clock in ports
clk_in1 => clk_125
);
ram64: blk_ram_64k port map(
clka => ram_clk,
addra => rama,
dina => ramdw,
douta => ramdr,
wea(0) => ram_r0w1,
rsta => res1,
ena => ramen
);
color_ram: blk_cram port map(
clka => ram_clk,
addra => rama(9 downto 0),
dina => cramdw,
douta => cramdr,
wea(0) => cram_r0w1,
rsta => res1,
ena => cramen
);
res1 <= not res0;
cpu_r0w1 <= not cpu_r1w0;
ram_r0w1 <= not ram_r1w0;
cram_r0w1 <= not cram_r1w0;
init_r0w1 <= not init_r1w0;
ram_wren: process(cpu_r1w0,abus,bankctl,init_counter,init_addr,init_r1w0,init_stg,cpu_on) is
begin
if (init_stg = initram_xfer and init_counter > x"0000") then
if (init_bank(u16(init_addr)) = mbk_cram) then
cram_r1w0 <= init_r1w0;
ram_r1w0 <= '1';
else
cram_r1w0 <= '1';
ram_r1w0 <= init_r1w0;
end if;
elsif (cpu_on = '1') then
if (cpu_bank(u16(abus),bankctl) = mbk_cram) then
cram_r1w0 <= cpu_r1w0;
ram_r1w0 <= '1';
else
if (bank_is_writethru(abus,bankctl)='1') then
cram_r1w0 <= '1';
ram_r1w0 <= cpu_r1w0;
else
cram_r1w0 <= '1';
ram_r1w0 <= '1';
end if;
end if;
else
cram_r1w0 <= '1';
ram_r1w0 <= '1';
end if;
end process ram_wren;
with init_stg select ramdw <=
init_data when initram_xfer,
cpudo when others;
with init_stg select cramdw <=
init_data(3 downto 0) when initram_xfer,
cpudo(3 downto 0) when others;
abus <= x"fffc";
ram_a_sel: process(init_stg,cpu_on,init_addr,abus,vbank,vic_va) is
begin
if (init_stg = initram_xfer) then
rama <= init_addr;
elsif (cpu_on = '1') then
rama <= abus;
else
rama <= vbank & vic_va;
end if;
end process ram_a_sel;
ram_clk_sel: process(init_stg,cpu_on,ramclk_init,ramclk_cpu,ramclk_vic) is
begin
if (init_stg = initram_xfer) then
ram_clk <= ramclk_init;
elsif (cpu_on = '1') then
ram_clk <= ramclk_cpu;
else
ram_clk <= ramclk_vic;
end if;
end process ram_clk_sel;
with clk20_ph select ramclk_init <=
'1' when "110",
'1' when "000",
'0' when others;
with clk20_ph select ramclk_vic <=
'1' when "110",
'1' when "000",
'0' when others;
with clk20_ph select ramclk_cpu <=
'1' when "110",
'1' when "000",
'0' when others;
vic: vic_ii port map(
clk20_ph1 => clk20_ph1,
clk20_ph2 => clk20_ph2,
rga => vic_rga,
rgdi => vic_regw,
rgdo => vic_regr,
r1w0 => vic_r1w0,
cpu_clk => cpu_ph4x,
cpu_ben => cpu_on,
vic_ben => vic_on,
bus_ph1 => cpu_ph1,
bus_ph2 => cpu_ph2,
va => vic_va,
vd => vic_vd,
cd => vic_cd,
res0 => res0,
vhs => vga_hs,
vvs => vga_vs,
vr => vga_r,
vg => vga_g,
vb => vga_b
);
vic_vd_sel: process(vbank,vic_va,ramdr) is
begin
if (vbk_cgrom(vbank,vic_va) = '1') then
vic_wvd <= char_rom(vic_va(11 downto 0));
--vic_wvd <= cgrom_data;
else
vic_wvd <= ramdr;
end if;
end process vic_vd_sel;
vic_wcd <= cramdr;
vic_vd <= vic_wvd;
vic_cd <= vic_wcd;
vic_regs: process(cpu_on,cpu_ph2,c_cycle) is
begin
if (cpu_on = '1' and rising_edge(cpu_ph2)) then
case c_cycle is
when x"00" =>
vic_r1w0 <= '1';
sid1_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"01" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"02" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"03" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"04" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"05" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"06" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"07" =>
vic_r1w0 <= '1';
c_cycle <= c_cycle+1;
when x"08" =>
vic_rga <= xtov6(x"18");
vic_regw <= "00010100";
vic_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"09" =>
vic_rga <= xtov6(x"20");
vic_regw <= x"0e";
vic_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"0a" =>
vic_rga <= xtov6(x"21");
vic_regw <= x"06";
vic_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"0b" =>
vic_rga <= xtov6(x"11");
vic_regw <= x"1b";
--vic_regw <= x"17";
vic_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"0c" =>
vic_rga <= xtov6(x"16");
vic_regw <= x"08";
--vic_regw <= x"07";
vic_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"0d" =>
vic_rga <= xtov6(x"12");
vic_r1w0 <= '1';
sid1_rga <= xtov5(x"0e");
sid1_dw <= x"25";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"0e" =>
sid1_rga <= xtov5(x"0f");
sid1_dw <= x"11";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"0f" =>
sid1_rga <= xtov5(x"10");
sid1_dw <= x"00";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"10" =>
sid1_rga <= xtov5(x"11");
sid1_dw <= x"08";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"11" =>
sid1_rga <= xtov5(x"12");
sid1_dw <= x"11";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"12" =>
sid1_rga <= xtov5(x"13");
sid1_dw <= x"0f";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"13" =>
sid1_rga <= xtov5(x"14");
sid1_dw <= x"ff";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"14" =>
sid1_rga <= xtov5(x"07");
sid1_dw <= x"9a";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"15" =>
sid1_rga <= xtov5(x"08");
sid1_dw <= x"15";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"16" =>
sid1_rga <= xtov5(x"09");
sid1_dw <= x"00";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"17" =>
sid1_rga <= xtov5(x"0a");
sid1_dw <= x"08";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"18" =>
sid1_rga <= xtov5(x"0b");
sid1_dw <= x"11";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"19" =>
sid1_rga <= xtov5(x"0c");
sid1_dw <= x"0f";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"1a" =>
sid1_rga <= xtov5(x"0d");
sid1_dw <= x"ff";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"1b" =>
sid1_rga <= xtov5(x"00");
sid1_dw <= x"81";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"1c" =>
sid1_rga <= xtov5(x"01");
sid1_dw <= x"19";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"1d" =>
sid1_rga <= xtov5(x"02");
sid1_dw <= x"00";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"1e" =>
sid1_rga <= xtov5(x"03");
sid1_dw <= x"08";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"1f" =>
sid1_rga <= xtov5(x"04");
sid1_dw <= x"11";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"20" =>
sid1_rga <= xtov5(x"05");
sid1_dw <= x"0f";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"21" =>
sid1_rga <= xtov5(x"06");
sid1_dw <= x"ff";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when x"22" =>
sid1_rga <= xtov5(x"18");
sid1_dw <= x"0f";
sid1_r1w0 <= '0';
c_cycle <= c_cycle+1;
when others =>
vic_rga <= xtov6(x"12");
vic_r1w0 <= '1';
sid1_rga <= xtov5(x"12");
sid1_dw <= sw & x"1";
sid1_r1w0 <= '0';
end case;
end if;
end process vic_regs;
sid_1: sid6581 port map (
res0 => res0,
ph2 => cpu_ph2,
rga => sid1_rga,
din => sid1_dw,
dout => sid1_dr,
r1w0 => sid1_r1w0,
s16audio => sid1_out
);
ac_muten <= res0;
ac_mclk <= clk12;
bclk_gen : process(clk12,bclk_cnt,res1) is
variable inc_0 : std_logic;
variable inc_1 : std_logic;
begin
inc_0 := not bclk_cnt(0);
inc_1 := bclk_cnt(1) xor bclk_cnt(0);
if (res1 = '1') then
bclk_cnt <= "00";
elsif (rising_edge(clk12)) then
bclk_cnt <= inc_1 & inc_0;
end if;
end process bclk_gen;
ac_bclk <= bclk_cnt(1);
audio_send : process(bclk_cnt,res1,hold2,hold_sam,sid1_out,audio_frame) is
variable apos : nybble;
begin
if (res1 = '1') then
audio_frame <= "00000";
elsif (falling_edge(bclk_cnt(1))) then
-- flipped frame index to send MSB first
apos := not nybble(audio_frame(3 downto 0));
if (buf_max(audio_frame)) then
hold_sam <= sid1_out;
end if;
if (audio_frame(4) = '1') then
ac_pbdat <= hold2(to_integer(unsigned(apos)));
else
ac_pbdat <= '0';
--ac_pbdat <= hold_sam(to_integer(unsigned(apos)));
hold2(to_integer(unsigned(apos))) <= hold_sam(to_integer(unsigned(apos)));
end if;
ac_pblrc <= audio_frame(4);
audio_frame <= adv_frame(audio_frame);
end if;
end process audio_send;
--
-- I2C config for SSM2603
--
i2c: component i2c_xcvr port map (
clk1M => cpu_ph2,
res0 => res0,
init_line => ssm_init_line,
init_data => ssm_init_data,
error => ssm_error,
scl => ac_scl,
sda => ac_sda
);
ssm_init_data <= dac_init(ssm_init_line);
led(0) <= ssm_error;
end testing;
|
------------------------------------------------------------------------------
-- IRAM_block
-- This unit is the top-level entity which contains:
-- - MMU_in_IRAM
-- - MMU_out_IRAM
-- It is in charge for data exchange with the IRAM
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity iram_block is
port (
-- INPUTS
from_pc : in std_logic_vector(31 downto 0); -- address coming from the pc
flush : in std_logic; -- control signal for flushing the pipeline
from_iram : in std_logic_vector(31 downto 0); -- instruction from IRAM
-- OUTPUTS
to_iram : out std_logic_vector(31 downto 0); -- instruction address
to_if_id_reg : out std_logic_vector(31 downto 0) -- instruction to be decoded
);
end iram_block;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture structural of iram_block is
-- Components declaration
component mmu_in_iram is
port (
-- INPTUS
from_pc : in std_logic_vector(31 downto 0); -- address coming from the pc register
-- OUTPUTS
to_iram : out std_logic_vector(31 downto 0) -- address to the IRAM
);
end component;
component mmu_out_iram is
port (
-- INPTUS
from_iram : in std_logic_vector(31 downto 0); -- instruction to be decoded
flush : in std_logic; -- contorl singnal coming from MEM stage to fluhs the pipeline
-- OUTPUTS
to_if_id_reg : out std_logic_vector(31 downto 0) -- value propagated to the pipeline register
);
end component;
-- Internal Signals
begin
-- Components instantiation
mmu_in: mmu_in_iram port map ( from_pc => from_pc,
to_iram => to_iram);
mmu_out: mmu_out_iram port map ( from_iram => from_iram,
flush => flush,
to_if_id_reg => to_if_id_reg);
end structural;
|
library ieee;
use ieee.std_logic_1164.all;
entity adc_tb is
end adc_tb;
architecture behavior of adc_tb is
component adc
port (
ad_port : in std_logic_vector(2 downto 0);
ad_value : out std_logic_vector(11 downto 0);
ad_newvalue : out std_logic;
clk : in std_logic;
ad_dout : in std_logic;
ad_din : out std_logic;
ad_cs : out std_logic
);
end component;
--Inputs
signal ad_port : std_logic_vector(2 downto 0) := "111";
signal clk : std_logic := '0';
signal ad_dout : std_logic := '0';
--Outputs
signal ad_value : std_logic_vector(11 downto 0);
signal ad_newvalue : std_logic;
signal ad_din : std_logic;
signal ad_cs : std_logic;
signal test : std_logic := '0';
-- Clock period definitions
constant clk_period : time := 10 ns;
begin
uut: adc
port map (
ad_port => ad_port,
ad_value => ad_value,
ad_newvalue => ad_newvalue,
clk => clk,
ad_dout => ad_dout,
ad_din => ad_din,
ad_cs => ad_cs
);
-- Clock process definitions
clk_process :process
begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period * 1.5;
ad_dout <= '0';
wait for clk_period * 4;
ad_dout <= '1';
wait for clk_period * 12;
ad_dout <= '0';
wait for clk_period;
ad_dout <= '1';
wait for clk_period * 4;
ad_dout <= '0';
wait for clk_period * 12;
ad_dout <= '1';
wait for clk_period;
ad_dout <= '0';
loop
ad_dout <= '0';
wait for clk_period*10;
ad_dout <= '1';
wait for clk_period*10;
end loop;
wait;
end process;
test_proc: process
begin
-- toggling test so I can see where the asserts are in ISIM
wait for clk_period;
test <= '1';
assert ad_newvalue = '0';
assert ad_cs = '1';
wait for clk_period;
test <= '0';
assert ad_newvalue = '1';
assert ad_cs = '0';
assert ad_value = "000000000000";
wait for clk_period * 2;
test <= '1';
assert ad_newvalue = '0';
assert ad_cs = '0';
assert ad_din = '1';
wait for clk_period;
test <= '0';
assert ad_din = '1';
wait for clk_period;
test <= '1';
assert ad_din = '1';
wait for clk_period * 12;
test <= '0';
assert ad_cs = '1';
wait for clk_period;
test <= '1';
assert ad_newvalue = '1';
assert ad_value = "111111111111";
wait;
end process;
end;
|
-- generated with romgen v3.0.1r4 by MikeJ truhy and eD
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity atomkernal is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of atomkernal is
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(11 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when x"000" => DATA <= x"50";
when x"001" => DATA <= x"4C";
when x"002" => DATA <= x"4F";
when x"003" => DATA <= x"54";
when x"004" => DATA <= x"F5";
when x"005" => DATA <= x"4E";
when x"006" => DATA <= x"44";
when x"007" => DATA <= x"52";
when x"008" => DATA <= x"41";
when x"009" => DATA <= x"57";
when x"00A" => DATA <= x"F5";
when x"00B" => DATA <= x"42";
when x"00C" => DATA <= x"4D";
when x"00D" => DATA <= x"4F";
when x"00E" => DATA <= x"56";
when x"00F" => DATA <= x"45";
when x"010" => DATA <= x"F5";
when x"011" => DATA <= x"46";
when x"012" => DATA <= x"43";
when x"013" => DATA <= x"4C";
when x"014" => DATA <= x"45";
when x"015" => DATA <= x"41";
when x"016" => DATA <= x"52";
when x"017" => DATA <= x"F6";
when x"018" => DATA <= x"7B";
when x"019" => DATA <= x"44";
when x"01A" => DATA <= x"49";
when x"01B" => DATA <= x"4D";
when x"01C" => DATA <= x"F0";
when x"01D" => DATA <= x"AE";
when x"01E" => DATA <= x"5B";
when x"01F" => DATA <= x"F2";
when x"020" => DATA <= x"A1";
when x"021" => DATA <= x"4F";
when x"022" => DATA <= x"4C";
when x"023" => DATA <= x"44";
when x"024" => DATA <= x"F5";
when x"025" => DATA <= x"31";
when x"026" => DATA <= x"57";
when x"027" => DATA <= x"41";
when x"028" => DATA <= x"49";
when x"029" => DATA <= x"54";
when x"02A" => DATA <= x"F1";
when x"02B" => DATA <= x"4C";
when x"02C" => DATA <= x"C5";
when x"02D" => DATA <= x"50";
when x"02E" => DATA <= x"A4";
when x"02F" => DATA <= x"5E";
when x"030" => DATA <= x"B1";
when x"031" => DATA <= x"05";
when x"032" => DATA <= x"C9";
when x"033" => DATA <= x"40";
when x"034" => DATA <= x"90";
when x"035" => DATA <= x"12";
when x"036" => DATA <= x"C9";
when x"037" => DATA <= x"5B";
when x"038" => DATA <= x"B0";
when x"039" => DATA <= x"0E";
when x"03A" => DATA <= x"C8";
when x"03B" => DATA <= x"D1";
when x"03C" => DATA <= x"05";
when x"03D" => DATA <= x"D0";
when x"03E" => DATA <= x"09";
when x"03F" => DATA <= x"20";
when x"040" => DATA <= x"8B";
when x"041" => DATA <= x"F0";
when x"042" => DATA <= x"20";
when x"043" => DATA <= x"4F";
when x"044" => DATA <= x"C9";
when x"045" => DATA <= x"4C";
when x"046" => DATA <= x"62";
when x"047" => DATA <= x"C9";
when x"048" => DATA <= x"4C";
when x"049" => DATA <= x"24";
when x"04A" => DATA <= x"CA";
when x"04B" => DATA <= x"A2";
when x"04C" => DATA <= x"FF";
when x"04D" => DATA <= x"A4";
when x"04E" => DATA <= x"5E";
when x"04F" => DATA <= x"C6";
when x"050" => DATA <= x"5E";
when x"051" => DATA <= x"B1";
when x"052" => DATA <= x"05";
when x"053" => DATA <= x"C9";
when x"054" => DATA <= x"40";
when x"055" => DATA <= x"90";
when x"056" => DATA <= x"09";
when x"057" => DATA <= x"C9";
when x"058" => DATA <= x"5B";
when x"059" => DATA <= x"B0";
when x"05A" => DATA <= x"05";
when x"05B" => DATA <= x"C8";
when x"05C" => DATA <= x"D1";
when x"05D" => DATA <= x"05";
when x"05E" => DATA <= x"F0";
when x"05F" => DATA <= x"25";
when x"060" => DATA <= x"A4";
when x"061" => DATA <= x"5E";
when x"062" => DATA <= x"E8";
when x"063" => DATA <= x"C8";
when x"064" => DATA <= x"BD";
when x"065" => DATA <= x"00";
when x"066" => DATA <= x"F0";
when x"067" => DATA <= x"30";
when x"068" => DATA <= x"0C";
when x"069" => DATA <= x"D1";
when x"06A" => DATA <= x"05";
when x"06B" => DATA <= x"F0";
when x"06C" => DATA <= x"F5";
when x"06D" => DATA <= x"E8";
when x"06E" => DATA <= x"BD";
when x"06F" => DATA <= x"FF";
when x"070" => DATA <= x"EF";
when x"071" => DATA <= x"10";
when x"072" => DATA <= x"FA";
when x"073" => DATA <= x"D0";
when x"074" => DATA <= x"EB";
when x"075" => DATA <= x"85";
when x"076" => DATA <= x"53";
when x"077" => DATA <= x"BD";
when x"078" => DATA <= x"01";
when x"079" => DATA <= x"F0";
when x"07A" => DATA <= x"85";
when x"07B" => DATA <= x"52";
when x"07C" => DATA <= x"84";
when x"07D" => DATA <= x"03";
when x"07E" => DATA <= x"A6";
when x"07F" => DATA <= x"04";
when x"080" => DATA <= x"E6";
when x"081" => DATA <= x"5E";
when x"082" => DATA <= x"6C";
when x"083" => DATA <= x"52";
when x"084" => DATA <= x"00";
when x"085" => DATA <= x"20";
when x"086" => DATA <= x"8B";
when x"087" => DATA <= x"F0";
when x"088" => DATA <= x"4C";
when x"089" => DATA <= x"F1";
when x"08A" => DATA <= x"C3";
when x"08B" => DATA <= x"C8";
when x"08C" => DATA <= x"84";
when x"08D" => DATA <= x"03";
when x"08E" => DATA <= x"E9";
when x"08F" => DATA <= x"40";
when x"090" => DATA <= x"48";
when x"091" => DATA <= x"20";
when x"092" => DATA <= x"BC";
when x"093" => DATA <= x"C8";
when x"094" => DATA <= x"68";
when x"095" => DATA <= x"A8";
when x"096" => DATA <= x"B5";
when x"097" => DATA <= x"15";
when x"098" => DATA <= x"0A";
when x"099" => DATA <= x"36";
when x"09A" => DATA <= x"24";
when x"09B" => DATA <= x"0A";
when x"09C" => DATA <= x"36";
when x"09D" => DATA <= x"24";
when x"09E" => DATA <= x"18";
when x"09F" => DATA <= x"79";
when x"0A0" => DATA <= x"EB";
when x"0A1" => DATA <= x"02";
when x"0A2" => DATA <= x"95";
when x"0A3" => DATA <= x"15";
when x"0A4" => DATA <= x"B5";
when x"0A5" => DATA <= x"24";
when x"0A6" => DATA <= x"79";
when x"0A7" => DATA <= x"06";
when x"0A8" => DATA <= x"03";
when x"0A9" => DATA <= x"95";
when x"0AA" => DATA <= x"24";
when x"0AB" => DATA <= x"B0";
when x"0AC" => DATA <= x"D7";
when x"0AD" => DATA <= x"60";
when x"0AE" => DATA <= x"A5";
when x"0AF" => DATA <= x"01";
when x"0B0" => DATA <= x"05";
when x"0B1" => DATA <= x"02";
when x"0B2" => DATA <= x"F0";
when x"0B3" => DATA <= x"22";
when x"0B4" => DATA <= x"20";
when x"0B5" => DATA <= x"34";
when x"0B6" => DATA <= x"C4";
when x"0B7" => DATA <= x"90";
when x"0B8" => DATA <= x"1E";
when x"0B9" => DATA <= x"20";
when x"0BA" => DATA <= x"BC";
when x"0BB" => DATA <= x"C8";
when x"0BC" => DATA <= x"CA";
when x"0BD" => DATA <= x"CA";
when x"0BE" => DATA <= x"86";
when x"0BF" => DATA <= x"04";
when x"0C0" => DATA <= x"B4";
when x"0C1" => DATA <= x"16";
when x"0C2" => DATA <= x"38";
when x"0C3" => DATA <= x"A5";
when x"0C4" => DATA <= x"23";
when x"0C5" => DATA <= x"99";
when x"0C6" => DATA <= x"21";
when x"0C7" => DATA <= x"03";
when x"0C8" => DATA <= x"75";
when x"0C9" => DATA <= x"17";
when x"0CA" => DATA <= x"85";
when x"0CB" => DATA <= x"23";
when x"0CC" => DATA <= x"A5";
when x"0CD" => DATA <= x"24";
when x"0CE" => DATA <= x"99";
when x"0CF" => DATA <= x"3C";
when x"0D0" => DATA <= x"03";
when x"0D1" => DATA <= x"75";
when x"0D2" => DATA <= x"26";
when x"0D3" => DATA <= x"4C";
when x"0D4" => DATA <= x"19";
when x"0D5" => DATA <= x"F1";
when x"0D6" => DATA <= x"00";
when x"0D7" => DATA <= x"A4";
when x"0D8" => DATA <= x"03";
when x"0D9" => DATA <= x"B1";
when x"0DA" => DATA <= x"05";
when x"0DB" => DATA <= x"C9";
when x"0DC" => DATA <= x"40";
when x"0DD" => DATA <= x"90";
when x"0DE" => DATA <= x"F7";
when x"0DF" => DATA <= x"C9";
when x"0E0" => DATA <= x"5B";
when x"0E1" => DATA <= x"B0";
when x"0E2" => DATA <= x"F3";
when x"0E3" => DATA <= x"C8";
when x"0E4" => DATA <= x"D1";
when x"0E5" => DATA <= x"05";
when x"0E6" => DATA <= x"D0";
when x"0E7" => DATA <= x"EE";
when x"0E8" => DATA <= x"E9";
when x"0E9" => DATA <= x"40";
when x"0EA" => DATA <= x"48";
when x"0EB" => DATA <= x"C8";
when x"0EC" => DATA <= x"84";
when x"0ED" => DATA <= x"03";
when x"0EE" => DATA <= x"20";
when x"0EF" => DATA <= x"BC";
when x"0F0" => DATA <= x"C8";
when x"0F1" => DATA <= x"68";
when x"0F2" => DATA <= x"A8";
when x"0F3" => DATA <= x"A5";
when x"0F4" => DATA <= x"23";
when x"0F5" => DATA <= x"99";
when x"0F6" => DATA <= x"EB";
when x"0F7" => DATA <= x"02";
when x"0F8" => DATA <= x"A5";
when x"0F9" => DATA <= x"24";
when x"0FA" => DATA <= x"99";
when x"0FB" => DATA <= x"06";
when x"0FC" => DATA <= x"03";
when x"0FD" => DATA <= x"CA";
when x"0FE" => DATA <= x"86";
when x"0FF" => DATA <= x"04";
when x"100" => DATA <= x"B4";
when x"101" => DATA <= x"16";
when x"102" => DATA <= x"C8";
when x"103" => DATA <= x"D0";
when x"104" => DATA <= x"02";
when x"105" => DATA <= x"F6";
when x"106" => DATA <= x"25";
when x"107" => DATA <= x"98";
when x"108" => DATA <= x"0A";
when x"109" => DATA <= x"36";
when x"10A" => DATA <= x"25";
when x"10B" => DATA <= x"0A";
when x"10C" => DATA <= x"36";
when x"10D" => DATA <= x"25";
when x"10E" => DATA <= x"18";
when x"10F" => DATA <= x"65";
when x"110" => DATA <= x"23";
when x"111" => DATA <= x"85";
when x"112" => DATA <= x"23";
when x"113" => DATA <= x"B5";
when x"114" => DATA <= x"25";
when x"115" => DATA <= x"65";
when x"116" => DATA <= x"24";
when x"117" => DATA <= x"B0";
when x"118" => DATA <= x"BD";
when x"119" => DATA <= x"85";
when x"11A" => DATA <= x"24";
when x"11B" => DATA <= x"A0";
when x"11C" => DATA <= x"00";
when x"11D" => DATA <= x"A9";
when x"11E" => DATA <= x"AA";
when x"11F" => DATA <= x"91";
when x"120" => DATA <= x"23";
when x"121" => DATA <= x"D1";
when x"122" => DATA <= x"23";
when x"123" => DATA <= x"D0";
when x"124" => DATA <= x"F7";
when x"125" => DATA <= x"4A";
when x"126" => DATA <= x"91";
when x"127" => DATA <= x"23";
when x"128" => DATA <= x"D1";
when x"129" => DATA <= x"23";
when x"12A" => DATA <= x"D0";
when x"12B" => DATA <= x"F0";
when x"12C" => DATA <= x"20";
when x"12D" => DATA <= x"34";
when x"12E" => DATA <= x"C4";
when x"12F" => DATA <= x"B0";
when x"130" => DATA <= x"A5";
when x"131" => DATA <= x"A4";
when x"132" => DATA <= x"03";
when x"133" => DATA <= x"B1";
when x"134" => DATA <= x"05";
when x"135" => DATA <= x"C9";
when x"136" => DATA <= x"2C";
when x"137" => DATA <= x"D0";
when x"138" => DATA <= x"05";
when x"139" => DATA <= x"E6";
when x"13A" => DATA <= x"03";
when x"13B" => DATA <= x"4C";
when x"13C" => DATA <= x"AE";
when x"13D" => DATA <= x"F0";
when x"13E" => DATA <= x"4C";
when x"13F" => DATA <= x"58";
when x"140" => DATA <= x"C5";
when x"141" => DATA <= x"A5";
when x"142" => DATA <= x"0D";
when x"143" => DATA <= x"85";
when x"144" => DATA <= x"23";
when x"145" => DATA <= x"A5";
when x"146" => DATA <= x"0E";
when x"147" => DATA <= x"85";
when x"148" => DATA <= x"24";
when x"149" => DATA <= x"4C";
when x"14A" => DATA <= x"83";
when x"14B" => DATA <= x"CE";
when x"14C" => DATA <= x"20";
when x"14D" => DATA <= x"E4";
when x"14E" => DATA <= x"C4";
when x"14F" => DATA <= x"20";
when x"150" => DATA <= x"66";
when x"151" => DATA <= x"FE";
when x"152" => DATA <= x"4C";
when x"153" => DATA <= x"5B";
when x"154" => DATA <= x"C5";
when x"155" => DATA <= x"1C";
when x"156" => DATA <= x"8A";
when x"157" => DATA <= x"1C";
when x"158" => DATA <= x"23";
when x"159" => DATA <= x"5D";
when x"15A" => DATA <= x"8B";
when x"15B" => DATA <= x"1B";
when x"15C" => DATA <= x"A1";
when x"15D" => DATA <= x"9D";
when x"15E" => DATA <= x"8A";
when x"15F" => DATA <= x"1D";
when x"160" => DATA <= x"23";
when x"161" => DATA <= x"9D";
when x"162" => DATA <= x"8B";
when x"163" => DATA <= x"1D";
when x"164" => DATA <= x"A1";
when x"165" => DATA <= x"00";
when x"166" => DATA <= x"29";
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when x"168" => DATA <= x"AE";
when x"169" => DATA <= x"69";
when x"16A" => DATA <= x"A8";
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when x"16C" => DATA <= x"23";
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when x"16E" => DATA <= x"53";
when x"16F" => DATA <= x"1B";
when x"170" => DATA <= x"23";
when x"171" => DATA <= x"24";
when x"172" => DATA <= x"53";
when x"173" => DATA <= x"19";
when x"174" => DATA <= x"A1";
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when x"176" => DATA <= x"1A";
when x"177" => DATA <= x"5B";
when x"178" => DATA <= x"5B";
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when x"17A" => DATA <= x"69";
when x"17B" => DATA <= x"24";
when x"17C" => DATA <= x"24";
when x"17D" => DATA <= x"AE";
when x"17E" => DATA <= x"AE";
when x"17F" => DATA <= x"A8";
when x"180" => DATA <= x"AD";
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when x"182" => DATA <= x"00";
when x"183" => DATA <= x"7C";
when x"184" => DATA <= x"00";
when x"185" => DATA <= x"15";
when x"186" => DATA <= x"9C";
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when x"188" => DATA <= x"9C";
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when x"18A" => DATA <= x"69";
when x"18B" => DATA <= x"29";
when x"18C" => DATA <= x"53";
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when x"18E" => DATA <= x"13";
when x"18F" => DATA <= x"34";
when x"190" => DATA <= x"11";
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when x"192" => DATA <= x"69";
when x"193" => DATA <= x"23";
when x"194" => DATA <= x"A0";
when x"195" => DATA <= x"D8";
when x"196" => DATA <= x"62";
when x"197" => DATA <= x"5A";
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when x"199" => DATA <= x"26";
when x"19A" => DATA <= x"62";
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when x"19C" => DATA <= x"88";
when x"19D" => DATA <= x"54";
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when x"19F" => DATA <= x"C8";
when x"1A0" => DATA <= x"54";
when x"1A1" => DATA <= x"68";
when x"1A2" => DATA <= x"44";
when x"1A3" => DATA <= x"E8";
when x"1A4" => DATA <= x"94";
when x"1A5" => DATA <= x"00";
when x"1A6" => DATA <= x"B4";
when x"1A7" => DATA <= x"08";
when x"1A8" => DATA <= x"84";
when x"1A9" => DATA <= x"74";
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when x"1AB" => DATA <= x"28";
when x"1AC" => DATA <= x"6E";
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when x"1AE" => DATA <= x"F4";
when x"1AF" => DATA <= x"CC";
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when x"1B1" => DATA <= x"72";
when x"1B2" => DATA <= x"F2";
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when x"1B4" => DATA <= x"8A";
when x"1B5" => DATA <= x"00";
when x"1B6" => DATA <= x"AA";
when x"1B7" => DATA <= x"A2";
when x"1B8" => DATA <= x"A2";
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when x"1BA" => DATA <= x"74";
when x"1BB" => DATA <= x"74";
when x"1BC" => DATA <= x"72";
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when x"1BF" => DATA <= x"B2";
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when x"1C1" => DATA <= x"B2";
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when x"1C3" => DATA <= x"22";
when x"1C4" => DATA <= x"00";
when x"1C5" => DATA <= x"1A";
when x"1C6" => DATA <= x"1A";
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when x"1C8" => DATA <= x"26";
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when x"1CB" => DATA <= x"88";
when x"1CC" => DATA <= x"C8";
when x"1CD" => DATA <= x"C4";
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when x"1CF" => DATA <= x"26";
when x"1D0" => DATA <= x"48";
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when x"1D2" => DATA <= x"44";
when x"1D3" => DATA <= x"A2";
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when x"1D5" => DATA <= x"00";
when x"1D6" => DATA <= x"02";
when x"1D7" => DATA <= x"00";
when x"1D8" => DATA <= x"08";
when x"1D9" => DATA <= x"F2";
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when x"1DB" => DATA <= x"80";
when x"1DC" => DATA <= x"01";
when x"1DD" => DATA <= x"C0";
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when x"1DF" => DATA <= x"C0";
when x"1E0" => DATA <= x"C0";
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when x"1E2" => DATA <= x"00";
when x"1E3" => DATA <= x"00";
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when x"1E5" => DATA <= x"00";
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when x"1E7" => DATA <= x"80";
when x"1E8" => DATA <= x"40";
when x"1E9" => DATA <= x"C0";
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when x"1EB" => DATA <= x"C0";
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when x"1EE" => DATA <= x"00";
when x"1EF" => DATA <= x"00";
when x"1F0" => DATA <= x"E4";
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when x"1F2" => DATA <= x"80";
when x"1F3" => DATA <= x"00";
when x"1F4" => DATA <= x"FC";
when x"1F5" => DATA <= x"00";
when x"1F6" => DATA <= x"08";
when x"1F7" => DATA <= x"08";
when x"1F8" => DATA <= x"F8";
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when x"1FA" => DATA <= x"F4";
when x"1FB" => DATA <= x"0C";
when x"1FC" => DATA <= x"10";
when x"1FD" => DATA <= x"04";
when x"1FE" => DATA <= x"F4";
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when x"200" => DATA <= x"20";
when x"201" => DATA <= x"10";
when x"202" => DATA <= x"00";
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when x"206" => DATA <= x"01";
when x"207" => DATA <= x"01";
when x"208" => DATA <= x"11";
when x"209" => DATA <= x"11";
when x"20A" => DATA <= x"02";
when x"20B" => DATA <= x"02";
when x"20C" => DATA <= x"11";
when x"20D" => DATA <= x"11";
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when x"20F" => DATA <= x"12";
when x"210" => DATA <= x"02";
when x"211" => DATA <= x"00";
when x"212" => DATA <= x"08";
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when x"214" => DATA <= x"18";
when x"215" => DATA <= x"20";
when x"216" => DATA <= x"28";
when x"217" => DATA <= x"30";
when x"218" => DATA <= x"38";
when x"219" => DATA <= x"40";
when x"21A" => DATA <= x"48";
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when x"21C" => DATA <= x"58";
when x"21D" => DATA <= x"60";
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when x"21F" => DATA <= x"70";
when x"220" => DATA <= x"78";
when x"221" => DATA <= x"80";
when x"222" => DATA <= x"88";
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when x"224" => DATA <= x"98";
when x"225" => DATA <= x"A0";
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when x"227" => DATA <= x"B0";
when x"228" => DATA <= x"B8";
when x"229" => DATA <= x"C0";
when x"22A" => DATA <= x"C8";
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when x"22C" => DATA <= x"D8";
when x"22D" => DATA <= x"E0";
when x"22E" => DATA <= x"E8";
when x"22F" => DATA <= x"F0";
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when x"231" => DATA <= x"0C";
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when x"234" => DATA <= x"4C";
when x"235" => DATA <= x"8C";
when x"236" => DATA <= x"AC";
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when x"23B" => DATA <= x"AA";
when x"23C" => DATA <= x"BA";
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when x"240" => DATA <= x"FA";
when x"241" => DATA <= x"0E";
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when x"245" => DATA <= x"8E";
when x"246" => DATA <= x"AE";
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when x"24A" => DATA <= x"2D";
when x"24B" => DATA <= x"4D";
when x"24C" => DATA <= x"6D";
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when x"24E" => DATA <= x"AD";
when x"24F" => DATA <= x"CD";
when x"250" => DATA <= x"ED";
when x"251" => DATA <= x"0D";
when x"252" => DATA <= x"0D";
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when x"254" => DATA <= x"0D";
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when x"258" => DATA <= x"0D";
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when x"25C" => DATA <= x"0D";
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when x"25F" => DATA <= x"0C";
when x"260" => DATA <= x"0D";
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when x"262" => DATA <= x"0D";
when x"263" => DATA <= x"0C";
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when x"265" => DATA <= x"09";
when x"266" => DATA <= x"0D";
when x"267" => DATA <= x"0C";
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when x"269" => DATA <= x"08";
when x"26A" => DATA <= x"0D";
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when x"26C" => DATA <= x"0D";
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when x"26E" => DATA <= x"0D";
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when x"272" => DATA <= x"06";
when x"273" => DATA <= x"0B";
when x"274" => DATA <= x"0B";
when x"275" => DATA <= x"04";
when x"276" => DATA <= x"0A";
when x"277" => DATA <= x"08";
when x"278" => DATA <= x"08";
when x"279" => DATA <= x"0D";
when x"27A" => DATA <= x"0D";
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when x"27C" => DATA <= x"0D";
when x"27D" => DATA <= x"0D";
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when x"27F" => DATA <= x"0D";
when x"280" => DATA <= x"0F";
when x"281" => DATA <= x"07";
when x"282" => DATA <= x"07";
when x"283" => DATA <= x"07";
when x"284" => DATA <= x"07";
when x"285" => DATA <= x"05";
when x"286" => DATA <= x"09";
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when x"28A" => DATA <= x"01";
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when x"296" => DATA <= x"03";
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when x"2A1" => DATA <= x"B1";
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when x"2A3" => DATA <= x"C9";
when x"2A4" => DATA <= x"5D";
when x"2A5" => DATA <= x"F0";
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when x"2AA" => DATA <= x"C6";
when x"2AB" => DATA <= x"03";
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when x"2B0" => DATA <= x"03";
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when x"2B3" => DATA <= x"48";
when x"2B4" => DATA <= x"A5";
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when x"2B6" => DATA <= x"48";
when x"2B7" => DATA <= x"AD";
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when x"2BA" => DATA <= x"48";
when x"2BB" => DATA <= x"A9";
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when x"2C3" => DATA <= x"8D";
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when x"2C5" => DATA <= x"03";
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when x"2C8" => DATA <= x"85";
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when x"2CC" => DATA <= x"85";
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when x"2D2" => DATA <= x"79";
when x"2D3" => DATA <= x"F3";
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when x"2D5" => DATA <= x"8D";
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when x"2D7" => DATA <= x"03";
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when x"2D9" => DATA <= x"20";
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when x"2DC" => DATA <= x"68";
when x"2DD" => DATA <= x"20";
when x"2DE" => DATA <= x"76";
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when x"2E1" => DATA <= x"00";
when x"2E2" => DATA <= x"C4";
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when x"2E4" => DATA <= x"F0";
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when x"2E6" => DATA <= x"B9";
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when x"2E8" => DATA <= x"00";
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when x"2EA" => DATA <= x"76";
when x"2EB" => DATA <= x"F3";
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when x"2ED" => DATA <= x"D0";
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when x"2EF" => DATA <= x"C0";
when x"2F0" => DATA <= x"03";
when x"2F1" => DATA <= x"F0";
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when x"2F4" => DATA <= x"79";
when x"2F5" => DATA <= x"F3";
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when x"2F7" => DATA <= x"4C";
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when x"2F9" => DATA <= x"20";
when x"2FA" => DATA <= x"4C";
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when x"2FC" => DATA <= x"C8";
when x"2FD" => DATA <= x"D0";
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when x"2FF" => DATA <= x"A0";
when x"300" => DATA <= x"00";
when x"301" => DATA <= x"B1";
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when x"303" => DATA <= x"C9";
when x"304" => DATA <= x"3B";
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when x"306" => DATA <= x"0A";
when x"307" => DATA <= x"C9";
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when x"309" => DATA <= x"F0";
when x"30A" => DATA <= x"06";
when x"30B" => DATA <= x"20";
when x"30C" => DATA <= x"4C";
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when x"30E" => DATA <= x"C8";
when x"30F" => DATA <= x"D0";
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when x"311" => DATA <= x"20";
when x"312" => DATA <= x"54";
when x"313" => DATA <= x"CD";
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when x"317" => DATA <= x"88";
when x"318" => DATA <= x"B1";
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when x"31A" => DATA <= x"C8";
when x"31B" => DATA <= x"C9";
when x"31C" => DATA <= x"3B";
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when x"31E" => DATA <= x"0C";
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when x"320" => DATA <= x"06";
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when x"328" => DATA <= x"20";
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when x"32C" => DATA <= x"A1";
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when x"32E" => DATA <= x"20";
when x"32F" => DATA <= x"91";
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when x"331" => DATA <= x"85";
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when x"333" => DATA <= x"20";
when x"334" => DATA <= x"91";
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when x"336" => DATA <= x"C5";
when x"337" => DATA <= x"66";
when x"338" => DATA <= x"D0";
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when x"33A" => DATA <= x"C9";
when x"33B" => DATA <= x"40";
when x"33C" => DATA <= x"90";
when x"33D" => DATA <= x"0C";
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when x"341" => DATA <= x"08";
when x"342" => DATA <= x"38";
when x"343" => DATA <= x"20";
when x"344" => DATA <= x"8E";
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when x"346" => DATA <= x"20";
when x"347" => DATA <= x"CB";
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when x"34A" => DATA <= x"00";
when x"34B" => DATA <= x"AD";
when x"34C" => DATA <= x"31";
when x"34D" => DATA <= x"03";
when x"34E" => DATA <= x"91";
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when x"350" => DATA <= x"AD";
when x"351" => DATA <= x"4C";
when x"352" => DATA <= x"03";
when x"353" => DATA <= x"C8";
when x"354" => DATA <= x"91";
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when x"356" => DATA <= x"A9";
when x"357" => DATA <= x"00";
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when x"359" => DATA <= x"91";
when x"35A" => DATA <= x"52";
when x"35B" => DATA <= x"C8";
when x"35C" => DATA <= x"91";
when x"35D" => DATA <= x"52";
when x"35E" => DATA <= x"D0";
when x"35F" => DATA <= x"36";
when x"360" => DATA <= x"20";
when x"361" => DATA <= x"91";
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when x"363" => DATA <= x"C9";
when x"364" => DATA <= x"3B";
when x"365" => DATA <= x"F0";
when x"366" => DATA <= x"04";
when x"367" => DATA <= x"C9";
when x"368" => DATA <= x"0D";
when x"369" => DATA <= x"D0";
when x"36A" => DATA <= x"F5";
when x"36B" => DATA <= x"AD";
when x"36C" => DATA <= x"31";
when x"36D" => DATA <= x"03";
when x"36E" => DATA <= x"85";
when x"36F" => DATA <= x"52";
when x"370" => DATA <= x"AD";
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when x"372" => DATA <= x"03";
when x"373" => DATA <= x"85";
when x"374" => DATA <= x"53";
when x"375" => DATA <= x"60";
when x"376" => DATA <= x"20";
when x"377" => DATA <= x"7E";
when x"378" => DATA <= x"F3";
when x"379" => DATA <= x"A9";
when x"37A" => DATA <= x"20";
when x"37B" => DATA <= x"4C";
when x"37C" => DATA <= x"4C";
when x"37D" => DATA <= x"CA";
when x"37E" => DATA <= x"A2";
when x"37F" => DATA <= x"FF";
when x"380" => DATA <= x"48";
when x"381" => DATA <= x"4A";
when x"382" => DATA <= x"4A";
when x"383" => DATA <= x"4A";
when x"384" => DATA <= x"4A";
when x"385" => DATA <= x"20";
when x"386" => DATA <= x"F9";
when x"387" => DATA <= x"C5";
when x"388" => DATA <= x"68";
when x"389" => DATA <= x"29";
when x"38A" => DATA <= x"0F";
when x"38B" => DATA <= x"4C";
when x"38C" => DATA <= x"F9";
when x"38D" => DATA <= x"C5";
when x"38E" => DATA <= x"A2";
when x"38F" => DATA <= x"00";
when x"390" => DATA <= x"86";
when x"391" => DATA <= x"00";
when x"392" => DATA <= x"86";
when x"393" => DATA <= x"64";
when x"394" => DATA <= x"86";
when x"395" => DATA <= x"65";
when x"396" => DATA <= x"20";
when x"397" => DATA <= x"91";
when x"398" => DATA <= x"F2";
when x"399" => DATA <= x"C9";
when x"39A" => DATA <= x"3A";
when x"39B" => DATA <= x"F0";
when x"39C" => DATA <= x"91";
when x"39D" => DATA <= x"C9";
when x"39E" => DATA <= x"3B";
when x"39F" => DATA <= x"F0";
when x"3A0" => DATA <= x"CA";
when x"3A1" => DATA <= x"C9";
when x"3A2" => DATA <= x"0D";
when x"3A3" => DATA <= x"F0";
when x"3A4" => DATA <= x"C6";
when x"3A5" => DATA <= x"C9";
when x"3A6" => DATA <= x"5C";
when x"3A7" => DATA <= x"F0";
when x"3A8" => DATA <= x"B7";
when x"3A9" => DATA <= x"A0";
when x"3AA" => DATA <= x"05";
when x"3AB" => DATA <= x"38";
when x"3AC" => DATA <= x"69";
when x"3AD" => DATA <= x"00";
when x"3AE" => DATA <= x"0A";
when x"3AF" => DATA <= x"0A";
when x"3B0" => DATA <= x"0A";
when x"3B1" => DATA <= x"0A";
when x"3B2" => DATA <= x"26";
when x"3B3" => DATA <= x"6A";
when x"3B4" => DATA <= x"26";
when x"3B5" => DATA <= x"69";
when x"3B6" => DATA <= x"88";
when x"3B7" => DATA <= x"D0";
when x"3B8" => DATA <= x"F8";
when x"3B9" => DATA <= x"E8";
when x"3BA" => DATA <= x"E0";
when x"3BB" => DATA <= x"03";
when x"3BC" => DATA <= x"D0";
when x"3BD" => DATA <= x"D8";
when x"3BE" => DATA <= x"06";
when x"3BF" => DATA <= x"6A";
when x"3C0" => DATA <= x"26";
when x"3C1" => DATA <= x"69";
when x"3C2" => DATA <= x"A2";
when x"3C3" => DATA <= x"40";
when x"3C4" => DATA <= x"A5";
when x"3C5" => DATA <= x"69";
when x"3C6" => DATA <= x"DD";
when x"3C7" => DATA <= x"54";
when x"3C8" => DATA <= x"F1";
when x"3C9" => DATA <= x"F0";
when x"3CA" => DATA <= x"04";
when x"3CB" => DATA <= x"CA";
when x"3CC" => DATA <= x"D0";
when x"3CD" => DATA <= x"F8";
when x"3CE" => DATA <= x"00";
when x"3CF" => DATA <= x"BC";
when x"3D0" => DATA <= x"94";
when x"3D1" => DATA <= x"F1";
when x"3D2" => DATA <= x"C4";
when x"3D3" => DATA <= x"6A";
when x"3D4" => DATA <= x"D0";
when x"3D5" => DATA <= x"F5";
when x"3D6" => DATA <= x"BD";
when x"3D7" => DATA <= x"10";
when x"3D8" => DATA <= x"F2";
when x"3D9" => DATA <= x"85";
when x"3DA" => DATA <= x"66";
when x"3DB" => DATA <= x"BC";
when x"3DC" => DATA <= x"50";
when x"3DD" => DATA <= x"F2";
when x"3DE" => DATA <= x"84";
when x"3DF" => DATA <= x"0F";
when x"3E0" => DATA <= x"66";
when x"3E1" => DATA <= x"64";
when x"3E2" => DATA <= x"66";
when x"3E3" => DATA <= x"65";
when x"3E4" => DATA <= x"88";
when x"3E5" => DATA <= x"D0";
when x"3E6" => DATA <= x"F9";
when x"3E7" => DATA <= x"A4";
when x"3E8" => DATA <= x"0F";
when x"3E9" => DATA <= x"C0";
when x"3EA" => DATA <= x"0D";
when x"3EB" => DATA <= x"D0";
when x"3EC" => DATA <= x"05";
when x"3ED" => DATA <= x"A2";
when x"3EE" => DATA <= x"00";
when x"3EF" => DATA <= x"4C";
when x"3F0" => DATA <= x"9B";
when x"3F1" => DATA <= x"F4";
when x"3F2" => DATA <= x"20";
when x"3F3" => DATA <= x"91";
when x"3F4" => DATA <= x"F2";
when x"3F5" => DATA <= x"C9";
when x"3F6" => DATA <= x"40";
when x"3F7" => DATA <= x"F0";
when x"3F8" => DATA <= x"5B";
when x"3F9" => DATA <= x"C9";
when x"3FA" => DATA <= x"28";
when x"3FB" => DATA <= x"F0";
when x"3FC" => DATA <= x"65";
when x"3FD" => DATA <= x"A2";
when x"3FE" => DATA <= x"01";
when x"3FF" => DATA <= x"C9";
when x"400" => DATA <= x"41";
when x"401" => DATA <= x"F0";
when x"402" => DATA <= x"EC";
when x"403" => DATA <= x"C6";
when x"404" => DATA <= x"03";
when x"405" => DATA <= x"20";
when x"406" => DATA <= x"8B";
when x"407" => DATA <= x"C7";
when x"408" => DATA <= x"20";
when x"409" => DATA <= x"91";
when x"40A" => DATA <= x"F2";
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when x"40C" => DATA <= x"2C";
when x"40D" => DATA <= x"D0";
when x"40E" => DATA <= x"31";
when x"40F" => DATA <= x"20";
when x"410" => DATA <= x"91";
when x"411" => DATA <= x"F2";
when x"412" => DATA <= x"A4";
when x"413" => DATA <= x"25";
when x"414" => DATA <= x"F0";
when x"415" => DATA <= x"15";
when x"416" => DATA <= x"A2";
when x"417" => DATA <= x"09";
when x"418" => DATA <= x"C9";
when x"419" => DATA <= x"58";
when x"41A" => DATA <= x"F0";
when x"41B" => DATA <= x"7F";
when x"41C" => DATA <= x"CA";
when x"41D" => DATA <= x"C9";
when x"41E" => DATA <= x"59";
when x"41F" => DATA <= x"D0";
when x"420" => DATA <= x"79";
when x"421" => DATA <= x"A5";
when x"422" => DATA <= x"0F";
when x"423" => DATA <= x"C9";
when x"424" => DATA <= x"09";
when x"425" => DATA <= x"D0";
when x"426" => DATA <= x"74";
when x"427" => DATA <= x"A2";
when x"428" => DATA <= x"0E";
when x"429" => DATA <= x"D0";
when x"42A" => DATA <= x"70";
when x"42B" => DATA <= x"A2";
when x"42C" => DATA <= x"04";
when x"42D" => DATA <= x"C9";
when x"42E" => DATA <= x"58";
when x"42F" => DATA <= x"F0";
when x"430" => DATA <= x"6A";
when x"431" => DATA <= x"C9";
when x"432" => DATA <= x"59";
when x"433" => DATA <= x"D0";
when x"434" => DATA <= x"65";
when x"435" => DATA <= x"CA";
when x"436" => DATA <= x"A4";
when x"437" => DATA <= x"0F";
when x"438" => DATA <= x"C0";
when x"439" => DATA <= x"03";
when x"43A" => DATA <= x"B0";
when x"43B" => DATA <= x"5F";
when x"43C" => DATA <= x"A2";
when x"43D" => DATA <= x"08";
when x"43E" => DATA <= x"D0";
when x"43F" => DATA <= x"5B";
when x"440" => DATA <= x"C6";
when x"441" => DATA <= x"03";
when x"442" => DATA <= x"A2";
when x"443" => DATA <= x"02";
when x"444" => DATA <= x"A4";
when x"445" => DATA <= x"0F";
when x"446" => DATA <= x"C0";
when x"447" => DATA <= x"0C";
when x"448" => DATA <= x"F0";
when x"449" => DATA <= x"51";
when x"44A" => DATA <= x"A2";
when x"44B" => DATA <= x"05";
when x"44C" => DATA <= x"A5";
when x"44D" => DATA <= x"25";
when x"44E" => DATA <= x"F0";
when x"44F" => DATA <= x"4B";
when x"450" => DATA <= x"A2";
when x"451" => DATA <= x"0C";
when x"452" => DATA <= x"D0";
when x"453" => DATA <= x"47";
when x"454" => DATA <= x"20";
when x"455" => DATA <= x"8B";
when x"456" => DATA <= x"C7";
when x"457" => DATA <= x"A5";
when x"458" => DATA <= x"0F";
when x"459" => DATA <= x"A2";
when x"45A" => DATA <= x"06";
when x"45B" => DATA <= x"C9";
when x"45C" => DATA <= x"01";
when x"45D" => DATA <= x"F0";
when x"45E" => DATA <= x"3C";
when x"45F" => DATA <= x"E8";
when x"460" => DATA <= x"D0";
when x"461" => DATA <= x"39";
when x"462" => DATA <= x"20";
when x"463" => DATA <= x"8B";
when x"464" => DATA <= x"C7";
when x"465" => DATA <= x"20";
when x"466" => DATA <= x"91";
when x"467" => DATA <= x"F2";
when x"468" => DATA <= x"C9";
when x"469" => DATA <= x"29";
when x"46A" => DATA <= x"F0";
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when x"46C" => DATA <= x"C9";
when x"46D" => DATA <= x"2C";
when x"46E" => DATA <= x"D0";
when x"46F" => DATA <= x"2A";
when x"470" => DATA <= x"20";
when x"471" => DATA <= x"91";
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when x"473" => DATA <= x"C9";
when x"474" => DATA <= x"58";
when x"475" => DATA <= x"D0";
when x"476" => DATA <= x"23";
when x"477" => DATA <= x"20";
when x"478" => DATA <= x"91";
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when x"47A" => DATA <= x"C9";
when x"47B" => DATA <= x"29";
when x"47C" => DATA <= x"D0";
when x"47D" => DATA <= x"1C";
when x"47E" => DATA <= x"A2";
when x"47F" => DATA <= x"0B";
when x"480" => DATA <= x"D0";
when x"481" => DATA <= x"19";
when x"482" => DATA <= x"A2";
when x"483" => DATA <= x"0D";
when x"484" => DATA <= x"A5";
when x"485" => DATA <= x"0F";
when x"486" => DATA <= x"C9";
when x"487" => DATA <= x"0B";
when x"488" => DATA <= x"F0";
when x"489" => DATA <= x"11";
when x"48A" => DATA <= x"A2";
when x"48B" => DATA <= x"0A";
when x"48C" => DATA <= x"20";
when x"48D" => DATA <= x"91";
when x"48E" => DATA <= x"F2";
when x"48F" => DATA <= x"C9";
when x"490" => DATA <= x"2C";
when x"491" => DATA <= x"D0";
when x"492" => DATA <= x"07";
when x"493" => DATA <= x"20";
when x"494" => DATA <= x"91";
when x"495" => DATA <= x"F2";
when x"496" => DATA <= x"C9";
when x"497" => DATA <= x"59";
when x"498" => DATA <= x"F0";
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when x"49A" => DATA <= x"00";
when x"49B" => DATA <= x"20";
when x"49C" => DATA <= x"60";
when x"49D" => DATA <= x"F3";
when x"49E" => DATA <= x"BD";
when x"49F" => DATA <= x"D5";
when x"4A0" => DATA <= x"F1";
when x"4A1" => DATA <= x"F0";
when x"4A2" => DATA <= x"04";
when x"4A3" => DATA <= x"25";
when x"4A4" => DATA <= x"64";
when x"4A5" => DATA <= x"D0";
when x"4A6" => DATA <= x"07";
when x"4A7" => DATA <= x"BD";
when x"4A8" => DATA <= x"E4";
when x"4A9" => DATA <= x"F1";
when x"4AA" => DATA <= x"25";
when x"4AB" => DATA <= x"65";
when x"4AC" => DATA <= x"F0";
when x"4AD" => DATA <= x"EC";
when x"4AE" => DATA <= x"18";
when x"4AF" => DATA <= x"BD";
when x"4B0" => DATA <= x"F3";
when x"4B1" => DATA <= x"F1";
when x"4B2" => DATA <= x"65";
when x"4B3" => DATA <= x"66";
when x"4B4" => DATA <= x"85";
when x"4B5" => DATA <= x"66";
when x"4B6" => DATA <= x"BD";
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when x"4B8" => DATA <= x"F2";
when x"4B9" => DATA <= x"A2";
when x"4BA" => DATA <= x"00";
when x"4BB" => DATA <= x"86";
when x"4BC" => DATA <= x"04";
when x"4BD" => DATA <= x"A4";
when x"4BE" => DATA <= x"16";
when x"4BF" => DATA <= x"84";
when x"4C0" => DATA <= x"67";
when x"4C1" => DATA <= x"A4";
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when x"4C3" => DATA <= x"84";
when x"4C4" => DATA <= x"68";
when x"4C5" => DATA <= x"C9";
when x"4C6" => DATA <= x"0F";
when x"4C7" => DATA <= x"F0";
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when x"4C9" => DATA <= x"29";
when x"4CA" => DATA <= x"0F";
when x"4CB" => DATA <= x"A8";
when x"4CC" => DATA <= x"C8";
when x"4CD" => DATA <= x"84";
when x"4CE" => DATA <= x"00";
when x"4CF" => DATA <= x"C0";
when x"4D0" => DATA <= x"02";
when x"4D1" => DATA <= x"D0";
when x"4D2" => DATA <= x"04";
when x"4D3" => DATA <= x"A4";
when x"4D4" => DATA <= x"68";
when x"4D5" => DATA <= x"D0";
when x"4D6" => DATA <= x"C3";
when x"4D7" => DATA <= x"A0";
when x"4D8" => DATA <= x"00";
when x"4D9" => DATA <= x"B9";
when x"4DA" => DATA <= x"66";
when x"4DB" => DATA <= x"00";
when x"4DC" => DATA <= x"91";
when x"4DD" => DATA <= x"52";
when x"4DE" => DATA <= x"C8";
when x"4DF" => DATA <= x"EE";
when x"4E0" => DATA <= x"31";
when x"4E1" => DATA <= x"03";
when x"4E2" => DATA <= x"D0";
when x"4E3" => DATA <= x"03";
when x"4E4" => DATA <= x"EE";
when x"4E5" => DATA <= x"4C";
when x"4E6" => DATA <= x"03";
when x"4E7" => DATA <= x"C4";
when x"4E8" => DATA <= x"00";
when x"4E9" => DATA <= x"D0";
when x"4EA" => DATA <= x"EE";
when x"4EB" => DATA <= x"60";
when x"4EC" => DATA <= x"A9";
when x"4ED" => DATA <= x"02";
when x"4EE" => DATA <= x"85";
when x"4EF" => DATA <= x"00";
when x"4F0" => DATA <= x"38";
when x"4F1" => DATA <= x"A5";
when x"4F2" => DATA <= x"67";
when x"4F3" => DATA <= x"ED";
when x"4F4" => DATA <= x"31";
when x"4F5" => DATA <= x"03";
when x"4F6" => DATA <= x"85";
when x"4F7" => DATA <= x"67";
when x"4F8" => DATA <= x"A5";
when x"4F9" => DATA <= x"68";
when x"4FA" => DATA <= x"ED";
when x"4FB" => DATA <= x"4C";
when x"4FC" => DATA <= x"03";
when x"4FD" => DATA <= x"85";
when x"4FE" => DATA <= x"68";
when x"4FF" => DATA <= x"38";
when x"500" => DATA <= x"A5";
when x"501" => DATA <= x"67";
when x"502" => DATA <= x"E9";
when x"503" => DATA <= x"02";
when x"504" => DATA <= x"85";
when x"505" => DATA <= x"67";
when x"506" => DATA <= x"A8";
when x"507" => DATA <= x"A5";
when x"508" => DATA <= x"68";
when x"509" => DATA <= x"E9";
when x"50A" => DATA <= x"00";
when x"50B" => DATA <= x"F0";
when x"50C" => DATA <= x"1F";
when x"50D" => DATA <= x"C9";
when x"50E" => DATA <= x"FF";
when x"50F" => DATA <= x"F0";
when x"510" => DATA <= x"16";
when x"511" => DATA <= x"20";
when x"512" => DATA <= x"D1";
when x"513" => DATA <= x"F7";
when x"514" => DATA <= x"4F";
when x"515" => DATA <= x"55";
when x"516" => DATA <= x"54";
when x"517" => DATA <= x"20";
when x"518" => DATA <= x"4F";
when x"519" => DATA <= x"46";
when x"51A" => DATA <= x"20";
when x"51B" => DATA <= x"52";
when x"51C" => DATA <= x"41";
when x"51D" => DATA <= x"4E";
when x"51E" => DATA <= x"47";
when x"51F" => DATA <= x"45";
when x"520" => DATA <= x"3A";
when x"521" => DATA <= x"0A";
when x"522" => DATA <= x"0D";
when x"523" => DATA <= x"84";
when x"524" => DATA <= x"67";
when x"525" => DATA <= x"30";
when x"526" => DATA <= x"B0";
when x"527" => DATA <= x"98";
when x"528" => DATA <= x"30";
when x"529" => DATA <= x"AD";
when x"52A" => DATA <= x"10";
when x"52B" => DATA <= x"E5";
when x"52C" => DATA <= x"98";
when x"52D" => DATA <= x"10";
when x"52E" => DATA <= x"A8";
when x"52F" => DATA <= x"30";
when x"530" => DATA <= x"E0";
when x"531" => DATA <= x"20";
when x"532" => DATA <= x"E4";
when x"533" => DATA <= x"C4";
when x"534" => DATA <= x"88";
when x"535" => DATA <= x"84";
when x"536" => DATA <= x"52";
when x"537" => DATA <= x"A5";
when x"538" => DATA <= x"12";
when x"539" => DATA <= x"85";
when x"53A" => DATA <= x"53";
when x"53B" => DATA <= x"98";
when x"53C" => DATA <= x"C8";
when x"53D" => DATA <= x"91";
when x"53E" => DATA <= x"52";
when x"53F" => DATA <= x"4C";
when x"540" => DATA <= x"9B";
when x"541" => DATA <= x"CD";
when x"542" => DATA <= x"A2";
when x"543" => DATA <= x"05";
when x"544" => DATA <= x"D0";
when x"545" => DATA <= x"02";
when x"546" => DATA <= x"A2";
when x"547" => DATA <= x"0C";
when x"548" => DATA <= x"86";
when x"549" => DATA <= x"16";
when x"54A" => DATA <= x"E6";
when x"54B" => DATA <= x"04";
when x"54C" => DATA <= x"D0";
when x"54D" => DATA <= x"06";
when x"54E" => DATA <= x"20";
when x"54F" => DATA <= x"BC";
when x"550" => DATA <= x"C8";
when x"551" => DATA <= x"20";
when x"552" => DATA <= x"31";
when x"553" => DATA <= x"C2";
when x"554" => DATA <= x"20";
when x"555" => DATA <= x"BC";
when x"556" => DATA <= x"C8";
when x"557" => DATA <= x"20";
when x"558" => DATA <= x"31";
when x"559" => DATA <= x"C2";
when x"55A" => DATA <= x"20";
when x"55B" => DATA <= x"BC";
when x"55C" => DATA <= x"C8";
when x"55D" => DATA <= x"20";
when x"55E" => DATA <= x"E4";
when x"55F" => DATA <= x"C4";
when x"560" => DATA <= x"B5";
when x"561" => DATA <= x"15";
when x"562" => DATA <= x"85";
when x"563" => DATA <= x"5C";
when x"564" => DATA <= x"B5";
when x"565" => DATA <= x"24";
when x"566" => DATA <= x"85";
when x"567" => DATA <= x"5D";
when x"568" => DATA <= x"B5";
when x"569" => DATA <= x"14";
when x"56A" => DATA <= x"85";
when x"56B" => DATA <= x"5A";
when x"56C" => DATA <= x"B5";
when x"56D" => DATA <= x"23";
when x"56E" => DATA <= x"85";
when x"56F" => DATA <= x"5B";
when x"570" => DATA <= x"A2";
when x"571" => DATA <= x"00";
when x"572" => DATA <= x"86";
when x"573" => DATA <= x"04";
when x"574" => DATA <= x"A2";
when x"575" => DATA <= x"03";
when x"576" => DATA <= x"BD";
when x"577" => DATA <= x"C1";
when x"578" => DATA <= x"03";
when x"579" => DATA <= x"95";
when x"57A" => DATA <= x"52";
when x"57B" => DATA <= x"CA";
when x"57C" => DATA <= x"10";
when x"57D" => DATA <= x"F8";
when x"57E" => DATA <= x"A5";
when x"57F" => DATA <= x"16";
when x"580" => DATA <= x"29";
when x"581" => DATA <= x"04";
when x"582" => DATA <= x"D0";
when x"583" => DATA <= x"13";
when x"584" => DATA <= x"A2";
when x"585" => DATA <= x"02";
when x"586" => DATA <= x"18";
when x"587" => DATA <= x"B5";
when x"588" => DATA <= x"5A";
when x"589" => DATA <= x"75";
when x"58A" => DATA <= x"52";
when x"58B" => DATA <= x"95";
when x"58C" => DATA <= x"5A";
when x"58D" => DATA <= x"B5";
when x"58E" => DATA <= x"5B";
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when x"590" => DATA <= x"53";
when x"591" => DATA <= x"95";
when x"592" => DATA <= x"5B";
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when x"594" => DATA <= x"CA";
when x"595" => DATA <= x"10";
when x"596" => DATA <= x"EF";
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when x"598" => DATA <= x"03";
when x"599" => DATA <= x"B5";
when x"59A" => DATA <= x"5A";
when x"59B" => DATA <= x"9D";
when x"59C" => DATA <= x"C1";
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when x"59E" => DATA <= x"CA";
when x"59F" => DATA <= x"10";
when x"5A0" => DATA <= x"F8";
when x"5A1" => DATA <= x"A5";
when x"5A2" => DATA <= x"16";
when x"5A3" => DATA <= x"29";
when x"5A4" => DATA <= x"03";
when x"5A5" => DATA <= x"F0";
when x"5A6" => DATA <= x"0B";
when x"5A7" => DATA <= x"85";
when x"5A8" => DATA <= x"5E";
when x"5A9" => DATA <= x"A5";
when x"5AA" => DATA <= x"16";
when x"5AB" => DATA <= x"29";
when x"5AC" => DATA <= x"08";
when x"5AD" => DATA <= x"F0";
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when x"5AF" => DATA <= x"20";
when x"5B0" => DATA <= x"78";
when x"5B1" => DATA <= x"F6";
when x"5B2" => DATA <= x"4C";
when x"5B3" => DATA <= x"5B";
when x"5B4" => DATA <= x"C5";
when x"5B5" => DATA <= x"A2";
when x"5B6" => DATA <= x"02";
when x"5B7" => DATA <= x"38";
when x"5B8" => DATA <= x"B5";
when x"5B9" => DATA <= x"5A";
when x"5BA" => DATA <= x"F5";
when x"5BB" => DATA <= x"52";
when x"5BC" => DATA <= x"B4";
when x"5BD" => DATA <= x"52";
when x"5BE" => DATA <= x"94";
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when x"5C0" => DATA <= x"95";
when x"5C1" => DATA <= x"52";
when x"5C2" => DATA <= x"B4";
when x"5C3" => DATA <= x"53";
when x"5C4" => DATA <= x"B5";
when x"5C5" => DATA <= x"5B";
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when x"5C7" => DATA <= x"53";
when x"5C8" => DATA <= x"94";
when x"5C9" => DATA <= x"5B";
when x"5CA" => DATA <= x"95";
when x"5CB" => DATA <= x"53";
when x"5CC" => DATA <= x"95";
when x"5CD" => DATA <= x"56";
when x"5CE" => DATA <= x"10";
when x"5CF" => DATA <= x"0D";
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when x"5D1" => DATA <= x"00";
when x"5D2" => DATA <= x"38";
when x"5D3" => DATA <= x"F5";
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when x"5D5" => DATA <= x"95";
when x"5D6" => DATA <= x"52";
when x"5D7" => DATA <= x"A9";
when x"5D8" => DATA <= x"00";
when x"5D9" => DATA <= x"F5";
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when x"5DB" => DATA <= x"95";
when x"5DC" => DATA <= x"53";
when x"5DD" => DATA <= x"CA";
when x"5DE" => DATA <= x"CA";
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when x"5E0" => DATA <= x"D6";
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when x"5E2" => DATA <= x"54";
when x"5E3" => DATA <= x"C5";
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when x"5E5" => DATA <= x"A5";
when x"5E6" => DATA <= x"55";
when x"5E7" => DATA <= x"E5";
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when x"5E9" => DATA <= x"90";
when x"5EA" => DATA <= x"31";
when x"5EB" => DATA <= x"A9";
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when x"5EF" => DATA <= x"85";
when x"5F0" => DATA <= x"57";
when x"5F1" => DATA <= x"A9";
when x"5F2" => DATA <= x"00";
when x"5F3" => DATA <= x"E5";
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when x"5F5" => DATA <= x"38";
when x"5F6" => DATA <= x"6A";
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when x"5F8" => DATA <= x"59";
when x"5F9" => DATA <= x"66";
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when x"5FB" => DATA <= x"20";
when x"5FC" => DATA <= x"78";
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when x"600" => DATA <= x"CD";
when x"601" => DATA <= x"C3";
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when x"604" => DATA <= x"0A";
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when x"609" => DATA <= x"03";
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when x"60B" => DATA <= x"03";
when x"60C" => DATA <= x"4C";
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when x"60F" => DATA <= x"20";
when x"610" => DATA <= x"55";
when x"611" => DATA <= x"F6";
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when x"614" => DATA <= x"30";
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when x"619" => DATA <= x"4C";
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when x"61B" => DATA <= x"F5";
when x"61C" => DATA <= x"A5";
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when x"61E" => DATA <= x"4A";
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when x"620" => DATA <= x"59";
when x"621" => DATA <= x"A5";
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when x"623" => DATA <= x"6A";
when x"624" => DATA <= x"85";
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when x"626" => DATA <= x"20";
when x"627" => DATA <= x"78";
when x"628" => DATA <= x"F6";
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when x"62B" => DATA <= x"CD";
when x"62C" => DATA <= x"C1";
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when x"62E" => DATA <= x"D0";
when x"62F" => DATA <= x"07";
when x"630" => DATA <= x"A5";
when x"631" => DATA <= x"5B";
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when x"633" => DATA <= x"C2";
when x"634" => DATA <= x"03";
when x"635" => DATA <= x"F0";
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when x"638" => DATA <= x"44";
when x"639" => DATA <= x"F6";
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when x"63C" => DATA <= x"10";
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when x"63F" => DATA <= x"55";
when x"640" => DATA <= x"F6";
when x"641" => DATA <= x"4C";
when x"642" => DATA <= x"26";
when x"643" => DATA <= x"F6";
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when x"645" => DATA <= x"A5";
when x"646" => DATA <= x"57";
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when x"64A" => DATA <= x"57";
when x"64B" => DATA <= x"A5";
when x"64C" => DATA <= x"59";
when x"64D" => DATA <= x"E5";
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when x"64F" => DATA <= x"85";
when x"650" => DATA <= x"59";
when x"651" => DATA <= x"A2";
when x"652" => DATA <= x"00";
when x"653" => DATA <= x"F0";
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when x"655" => DATA <= x"18";
when x"656" => DATA <= x"A5";
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when x"65A" => DATA <= x"85";
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when x"65C" => DATA <= x"A5";
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when x"65E" => DATA <= x"65";
when x"65F" => DATA <= x"53";
when x"660" => DATA <= x"85";
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when x"662" => DATA <= x"A2";
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when x"665" => DATA <= x"56";
when x"666" => DATA <= x"10";
when x"667" => DATA <= x"09";
when x"668" => DATA <= x"B5";
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when x"66A" => DATA <= x"D0";
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when x"66C" => DATA <= x"D6";
when x"66D" => DATA <= x"5B";
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when x"66F" => DATA <= x"5A";
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when x"671" => DATA <= x"F6";
when x"672" => DATA <= x"5A";
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when x"675" => DATA <= x"F6";
when x"676" => DATA <= x"5B";
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when x"678" => DATA <= x"6C";
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when x"67D" => DATA <= x"C3";
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when x"680" => DATA <= x"A5";
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when x"686" => DATA <= x"90";
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when x"690" => DATA <= x"85";
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when x"696" => DATA <= x"A6";
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when x"699" => DATA <= x"04";
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when x"69C" => DATA <= x"B0";
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when x"69F" => DATA <= x"98";
when x"6A0" => DATA <= x"91";
when x"6A1" => DATA <= x"53";
when x"6A2" => DATA <= x"88";
when x"6A3" => DATA <= x"D0";
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when x"6A5" => DATA <= x"E6";
when x"6A6" => DATA <= x"54";
when x"6A7" => DATA <= x"E4";
when x"6A8" => DATA <= x"54";
when x"6A9" => DATA <= x"D0";
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when x"6AB" => DATA <= x"A4";
when x"6AC" => DATA <= x"52";
when x"6AD" => DATA <= x"B9";
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when x"6B2" => DATA <= x"03";
when x"6B3" => DATA <= x"B9";
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when x"6B6" => DATA <= x"8D";
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when x"6B8" => DATA <= x"03";
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when x"6BB" => DATA <= x"F6";
when x"6BC" => DATA <= x"8D";
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when x"6BE" => DATA <= x"B0";
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when x"6C0" => DATA <= x"58";
when x"6C1" => DATA <= x"C5";
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when x"6C3" => DATA <= x"40";
when x"6C4" => DATA <= x"99";
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when x"6C6" => DATA <= x"80";
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when x"6CA" => DATA <= x"88";
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when x"6D0" => DATA <= x"86";
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when x"6D3" => DATA <= x"E2";
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when x"6D6" => DATA <= x"6D";
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when x"6D8" => DATA <= x"F6";
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when x"6DB" => DATA <= x"F7";
when x"6DC" => DATA <= x"F7";
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when x"6DE" => DATA <= x"30";
when x"6DF" => DATA <= x"70";
when x"6E0" => DATA <= x"B0";
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when x"6E2" => DATA <= x"A5";
when x"6E3" => DATA <= x"5B";
when x"6E4" => DATA <= x"05";
when x"6E5" => DATA <= x"5D";
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when x"6E8" => DATA <= x"A5";
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when x"6EB" => DATA <= x"40";
when x"6EC" => DATA <= x"B0";
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when x"6EF" => DATA <= x"85";
when x"6F0" => DATA <= x"5F";
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when x"6F3" => DATA <= x"38";
when x"6F4" => DATA <= x"E5";
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when x"6F7" => DATA <= x"30";
when x"6F8" => DATA <= x"B0";
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when x"6FA" => DATA <= x"A2";
when x"6FB" => DATA <= x"FF";
when x"6FC" => DATA <= x"38";
when x"6FD" => DATA <= x"E8";
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when x"700" => DATA <= x"B0";
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when x"702" => DATA <= x"69";
when x"703" => DATA <= x"03";
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when x"705" => DATA <= x"61";
when x"706" => DATA <= x"8A";
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when x"709" => DATA <= x"0A";
when x"70A" => DATA <= x"0A";
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when x"70C" => DATA <= x"05";
when x"70D" => DATA <= x"5F";
when x"70E" => DATA <= x"85";
when x"70F" => DATA <= x"5F";
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when x"711" => DATA <= x"80";
when x"712" => DATA <= x"69";
when x"713" => DATA <= x"00";
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when x"719" => DATA <= x"A5";
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when x"71B" => DATA <= x"2A";
when x"71C" => DATA <= x"A8";
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when x"71F" => DATA <= x"F7";
when x"720" => DATA <= x"A0";
when x"721" => DATA <= x"00";
when x"722" => DATA <= x"A6";
when x"723" => DATA <= x"5E";
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when x"725" => DATA <= x"F0";
when x"726" => DATA <= x"0F";
when x"727" => DATA <= x"CA";
when x"728" => DATA <= x"F0";
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when x"72A" => DATA <= x"49";
when x"72B" => DATA <= x"FF";
when x"72C" => DATA <= x"31";
when x"72D" => DATA <= x"5F";
when x"72E" => DATA <= x"91";
when x"72F" => DATA <= x"5F";
when x"730" => DATA <= x"60";
when x"731" => DATA <= x"51";
when x"732" => DATA <= x"5F";
when x"733" => DATA <= x"91";
when x"734" => DATA <= x"5F";
when x"735" => DATA <= x"60";
when x"736" => DATA <= x"11";
when x"737" => DATA <= x"5F";
when x"738" => DATA <= x"91";
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when x"73A" => DATA <= x"60";
when x"73B" => DATA <= x"A5";
when x"73C" => DATA <= x"5B";
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when x"73E" => DATA <= x"5D";
when x"73F" => DATA <= x"D0";
when x"740" => DATA <= x"F9";
when x"741" => DATA <= x"A5";
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when x"743" => DATA <= x"30";
when x"744" => DATA <= x"F5";
when x"745" => DATA <= x"4A";
when x"746" => DATA <= x"4A";
when x"747" => DATA <= x"4A";
when x"748" => DATA <= x"85";
when x"749" => DATA <= x"5F";
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when x"74B" => DATA <= x"3F";
when x"74C" => DATA <= x"38";
when x"74D" => DATA <= x"E5";
when x"74E" => DATA <= x"5C";
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when x"750" => DATA <= x"40";
when x"751" => DATA <= x"90";
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when x"753" => DATA <= x"60";
when x"754" => DATA <= x"A5";
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when x"756" => DATA <= x"05";
when x"757" => DATA <= x"5D";
when x"758" => DATA <= x"D0";
when x"759" => DATA <= x"E0";
when x"75A" => DATA <= x"A5";
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when x"75C" => DATA <= x"30";
when x"75D" => DATA <= x"DC";
when x"75E" => DATA <= x"4A";
when x"75F" => DATA <= x"4A";
when x"760" => DATA <= x"4A";
when x"761" => DATA <= x"85";
when x"762" => DATA <= x"5F";
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when x"765" => DATA <= x"38";
when x"766" => DATA <= x"E5";
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when x"768" => DATA <= x"C9";
when x"769" => DATA <= x"60";
when x"76A" => DATA <= x"90";
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when x"76C" => DATA <= x"60";
when x"76D" => DATA <= x"A5";
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when x"770" => DATA <= x"5D";
when x"771" => DATA <= x"D0";
when x"772" => DATA <= x"C7";
when x"773" => DATA <= x"A5";
when x"774" => DATA <= x"5A";
when x"775" => DATA <= x"30";
when x"776" => DATA <= x"C3";
when x"777" => DATA <= x"4A";
when x"778" => DATA <= x"4A";
when x"779" => DATA <= x"4A";
when x"77A" => DATA <= x"85";
when x"77B" => DATA <= x"5F";
when x"77C" => DATA <= x"A9";
when x"77D" => DATA <= x"BF";
when x"77E" => DATA <= x"38";
when x"77F" => DATA <= x"E5";
when x"780" => DATA <= x"5C";
when x"781" => DATA <= x"C9";
when x"782" => DATA <= x"C0";
when x"783" => DATA <= x"B0";
when x"784" => DATA <= x"B5";
when x"785" => DATA <= x"A0";
when x"786" => DATA <= x"00";
when x"787" => DATA <= x"84";
when x"788" => DATA <= x"60";
when x"789" => DATA <= x"0A";
when x"78A" => DATA <= x"26";
when x"78B" => DATA <= x"60";
when x"78C" => DATA <= x"0A";
when x"78D" => DATA <= x"26";
when x"78E" => DATA <= x"60";
when x"78F" => DATA <= x"0A";
when x"790" => DATA <= x"26";
when x"791" => DATA <= x"60";
when x"792" => DATA <= x"0A";
when x"793" => DATA <= x"26";
when x"794" => DATA <= x"60";
when x"795" => DATA <= x"65";
when x"796" => DATA <= x"5F";
when x"797" => DATA <= x"85";
when x"798" => DATA <= x"5F";
when x"799" => DATA <= x"A5";
when x"79A" => DATA <= x"60";
when x"79B" => DATA <= x"69";
when x"79C" => DATA <= x"80";
when x"79D" => DATA <= x"85";
when x"79E" => DATA <= x"60";
when x"79F" => DATA <= x"A5";
when x"7A0" => DATA <= x"5A";
when x"7A1" => DATA <= x"29";
when x"7A2" => DATA <= x"07";
when x"7A3" => DATA <= x"A8";
when x"7A4" => DATA <= x"B9";
when x"7A5" => DATA <= x"C9";
when x"7A6" => DATA <= x"F7";
when x"7A7" => DATA <= x"4C";
when x"7A8" => DATA <= x"20";
when x"7A9" => DATA <= x"F7";
when x"7AA" => DATA <= x"A5";
when x"7AB" => DATA <= x"5B";
when x"7AC" => DATA <= x"05";
when x"7AD" => DATA <= x"5D";
when x"7AE" => DATA <= x"D0";
when x"7AF" => DATA <= x"BC";
when x"7B0" => DATA <= x"A5";
when x"7B1" => DATA <= x"5A";
when x"7B2" => DATA <= x"4A";
when x"7B3" => DATA <= x"4A";
when x"7B4" => DATA <= x"4A";
when x"7B5" => DATA <= x"85";
when x"7B6" => DATA <= x"5F";
when x"7B7" => DATA <= x"A9";
when x"7B8" => DATA <= x"BF";
when x"7B9" => DATA <= x"38";
when x"7BA" => DATA <= x"E5";
when x"7BB" => DATA <= x"5C";
when x"7BC" => DATA <= x"C9";
when x"7BD" => DATA <= x"C0";
when x"7BE" => DATA <= x"B0";
when x"7BF" => DATA <= x"AC";
when x"7C0" => DATA <= x"A0";
when x"7C1" => DATA <= x"00";
when x"7C2" => DATA <= x"84";
when x"7C3" => DATA <= x"60";
when x"7C4" => DATA <= x"0A";
when x"7C5" => DATA <= x"26";
when x"7C6" => DATA <= x"60";
when x"7C7" => DATA <= x"10";
when x"7C8" => DATA <= x"C0";
when x"7C9" => DATA <= x"80";
when x"7CA" => DATA <= x"40";
when x"7CB" => DATA <= x"20";
when x"7CC" => DATA <= x"10";
when x"7CD" => DATA <= x"08";
when x"7CE" => DATA <= x"04";
when x"7CF" => DATA <= x"02";
when x"7D0" => DATA <= x"01";
when x"7D1" => DATA <= x"68";
when x"7D2" => DATA <= x"85";
when x"7D3" => DATA <= x"E8";
when x"7D4" => DATA <= x"68";
when x"7D5" => DATA <= x"85";
when x"7D6" => DATA <= x"E9";
when x"7D7" => DATA <= x"A0";
when x"7D8" => DATA <= x"00";
when x"7D9" => DATA <= x"E6";
when x"7DA" => DATA <= x"E8";
when x"7DB" => DATA <= x"D0";
when x"7DC" => DATA <= x"02";
when x"7DD" => DATA <= x"E6";
when x"7DE" => DATA <= x"E9";
when x"7DF" => DATA <= x"B1";
when x"7E0" => DATA <= x"E8";
when x"7E1" => DATA <= x"30";
when x"7E2" => DATA <= x"06";
when x"7E3" => DATA <= x"20";
when x"7E4" => DATA <= x"F4";
when x"7E5" => DATA <= x"FF";
when x"7E6" => DATA <= x"4C";
when x"7E7" => DATA <= x"D7";
when x"7E8" => DATA <= x"F7";
when x"7E9" => DATA <= x"6C";
when x"7EA" => DATA <= x"E8";
when x"7EB" => DATA <= x"00";
when x"7EC" => DATA <= x"A2";
when x"7ED" => DATA <= x"D4";
when x"7EE" => DATA <= x"20";
when x"7EF" => DATA <= x"F1";
when x"7F0" => DATA <= x"F7";
when x"7F1" => DATA <= x"B5";
when x"7F2" => DATA <= x"01";
when x"7F3" => DATA <= x"20";
when x"7F4" => DATA <= x"02";
when x"7F5" => DATA <= x"F8";
when x"7F6" => DATA <= x"E8";
when x"7F7" => DATA <= x"E8";
when x"7F8" => DATA <= x"B5";
when x"7F9" => DATA <= x"FE";
when x"7FA" => DATA <= x"20";
when x"7FB" => DATA <= x"02";
when x"7FC" => DATA <= x"F8";
when x"7FD" => DATA <= x"A9";
when x"7FE" => DATA <= x"20";
when x"7FF" => DATA <= x"4C";
when x"800" => DATA <= x"F4";
when x"801" => DATA <= x"FF";
when x"802" => DATA <= x"48";
when x"803" => DATA <= x"4A";
when x"804" => DATA <= x"4A";
when x"805" => DATA <= x"4A";
when x"806" => DATA <= x"4A";
when x"807" => DATA <= x"20";
when x"808" => DATA <= x"0B";
when x"809" => DATA <= x"F8";
when x"80A" => DATA <= x"68";
when x"80B" => DATA <= x"29";
when x"80C" => DATA <= x"0F";
when x"80D" => DATA <= x"C9";
when x"80E" => DATA <= x"0A";
when x"80F" => DATA <= x"90";
when x"810" => DATA <= x"02";
when x"811" => DATA <= x"69";
when x"812" => DATA <= x"06";
when x"813" => DATA <= x"69";
when x"814" => DATA <= x"30";
when x"815" => DATA <= x"4C";
when x"816" => DATA <= x"F4";
when x"817" => DATA <= x"FF";
when x"818" => DATA <= x"20";
when x"819" => DATA <= x"76";
when x"81A" => DATA <= x"F8";
when x"81B" => DATA <= x"A2";
when x"81C" => DATA <= x"00";
when x"81D" => DATA <= x"C9";
when x"81E" => DATA <= x"22";
when x"81F" => DATA <= x"F0";
when x"820" => DATA <= x"06";
when x"821" => DATA <= x"E8";
when x"822" => DATA <= x"D0";
when x"823" => DATA <= x"1B";
when x"824" => DATA <= x"4C";
when x"825" => DATA <= x"7D";
when x"826" => DATA <= x"FA";
when x"827" => DATA <= x"C8";
when x"828" => DATA <= x"B9";
when x"829" => DATA <= x"00";
when x"82A" => DATA <= x"01";
when x"82B" => DATA <= x"C9";
when x"82C" => DATA <= x"0D";
when x"82D" => DATA <= x"F0";
when x"82E" => DATA <= x"F5";
when x"82F" => DATA <= x"9D";
when x"830" => DATA <= x"40";
when x"831" => DATA <= x"01";
when x"832" => DATA <= x"E8";
when x"833" => DATA <= x"C9";
when x"834" => DATA <= x"22";
when x"835" => DATA <= x"D0";
when x"836" => DATA <= x"F0";
when x"837" => DATA <= x"C8";
when x"838" => DATA <= x"B9";
when x"839" => DATA <= x"00";
when x"83A" => DATA <= x"01";
when x"83B" => DATA <= x"C9";
when x"83C" => DATA <= x"22";
when x"83D" => DATA <= x"F0";
when x"83E" => DATA <= x"E8";
when x"83F" => DATA <= x"A9";
when x"840" => DATA <= x"0D";
when x"841" => DATA <= x"9D";
when x"842" => DATA <= x"3F";
when x"843" => DATA <= x"01";
when x"844" => DATA <= x"A9";
when x"845" => DATA <= x"40";
when x"846" => DATA <= x"85";
when x"847" => DATA <= x"C9";
when x"848" => DATA <= x"A9";
when x"849" => DATA <= x"01";
when x"84A" => DATA <= x"85";
when x"84B" => DATA <= x"CA";
when x"84C" => DATA <= x"A2";
when x"84D" => DATA <= x"C9";
when x"84E" => DATA <= x"60";
when x"84F" => DATA <= x"A0";
when x"850" => DATA <= x"00";
when x"851" => DATA <= x"B5";
when x"852" => DATA <= x"00";
when x"853" => DATA <= x"99";
when x"854" => DATA <= x"C9";
when x"855" => DATA <= x"00";
when x"856" => DATA <= x"E8";
when x"857" => DATA <= x"C8";
when x"858" => DATA <= x"C0";
when x"859" => DATA <= x"0A";
when x"85A" => DATA <= x"90";
when x"85B" => DATA <= x"F5";
when x"85C" => DATA <= x"A0";
when x"85D" => DATA <= x"FF";
when x"85E" => DATA <= x"A9";
when x"85F" => DATA <= x"0D";
when x"860" => DATA <= x"C8";
when x"861" => DATA <= x"C0";
when x"862" => DATA <= x"0E";
when x"863" => DATA <= x"B0";
when x"864" => DATA <= x"07";
when x"865" => DATA <= x"D1";
when x"866" => DATA <= x"C9";
when x"867" => DATA <= x"D0";
when x"868" => DATA <= x"F7";
when x"869" => DATA <= x"C0";
when x"86A" => DATA <= x"00";
when x"86B" => DATA <= x"60";
when x"86C" => DATA <= x"20";
when x"86D" => DATA <= x"D1";
when x"86E" => DATA <= x"F7";
when x"86F" => DATA <= x"4E";
when x"870" => DATA <= x"41";
when x"871" => DATA <= x"4D";
when x"872" => DATA <= x"45";
when x"873" => DATA <= x"EA";
when x"874" => DATA <= x"00";
when x"875" => DATA <= x"C8";
when x"876" => DATA <= x"B9";
when x"877" => DATA <= x"00";
when x"878" => DATA <= x"01";
when x"879" => DATA <= x"C9";
when x"87A" => DATA <= x"20";
when x"87B" => DATA <= x"F0";
when x"87C" => DATA <= x"F8";
when x"87D" => DATA <= x"60";
when x"87E" => DATA <= x"C9";
when x"87F" => DATA <= x"30";
when x"880" => DATA <= x"90";
when x"881" => DATA <= x"0F";
when x"882" => DATA <= x"C9";
when x"883" => DATA <= x"3A";
when x"884" => DATA <= x"90";
when x"885" => DATA <= x"08";
when x"886" => DATA <= x"E9";
when x"887" => DATA <= x"07";
when x"888" => DATA <= x"90";
when x"889" => DATA <= x"07";
when x"88A" => DATA <= x"C9";
when x"88B" => DATA <= x"40";
when x"88C" => DATA <= x"B0";
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when x"88E" => DATA <= x"29";
when x"88F" => DATA <= x"0F";
when x"890" => DATA <= x"60";
when x"891" => DATA <= x"38";
when x"892" => DATA <= x"60";
when x"893" => DATA <= x"A9";
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when x"895" => DATA <= x"95";
when x"896" => DATA <= x"00";
when x"897" => DATA <= x"95";
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when x"89A" => DATA <= x"02";
when x"89B" => DATA <= x"20";
when x"89C" => DATA <= x"76";
when x"89D" => DATA <= x"F8";
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when x"89F" => DATA <= x"00";
when x"8A0" => DATA <= x"01";
when x"8A1" => DATA <= x"20";
when x"8A2" => DATA <= x"7E";
when x"8A3" => DATA <= x"F8";
when x"8A4" => DATA <= x"B0";
when x"8A5" => DATA <= x"15";
when x"8A6" => DATA <= x"0A";
when x"8A7" => DATA <= x"0A";
when x"8A8" => DATA <= x"0A";
when x"8A9" => DATA <= x"0A";
when x"8AA" => DATA <= x"94";
when x"8AB" => DATA <= x"02";
when x"8AC" => DATA <= x"A0";
when x"8AD" => DATA <= x"04";
when x"8AE" => DATA <= x"0A";
when x"8AF" => DATA <= x"36";
when x"8B0" => DATA <= x"00";
when x"8B1" => DATA <= x"36";
when x"8B2" => DATA <= x"01";
when x"8B3" => DATA <= x"88";
when x"8B4" => DATA <= x"D0";
when x"8B5" => DATA <= x"F8";
when x"8B6" => DATA <= x"B4";
when x"8B7" => DATA <= x"02";
when x"8B8" => DATA <= x"C8";
when x"8B9" => DATA <= x"D0";
when x"8BA" => DATA <= x"E3";
when x"8BB" => DATA <= x"B5";
when x"8BC" => DATA <= x"02";
when x"8BD" => DATA <= x"60";
when x"8BE" => DATA <= x"43";
when x"8BF" => DATA <= x"41";
when x"8C0" => DATA <= x"54";
when x"8C1" => DATA <= x"FA";
when x"8C2" => DATA <= x"2A";
when x"8C3" => DATA <= x"4C";
when x"8C4" => DATA <= x"4F";
when x"8C5" => DATA <= x"41";
when x"8C6" => DATA <= x"44";
when x"8C7" => DATA <= x"F9";
when x"8C8" => DATA <= x"58";
when x"8C9" => DATA <= x"53";
when x"8CA" => DATA <= x"41";
when x"8CB" => DATA <= x"56";
when x"8CC" => DATA <= x"45";
when x"8CD" => DATA <= x"FA";
when x"8CE" => DATA <= x"BB";
when x"8CF" => DATA <= x"52";
when x"8D0" => DATA <= x"55";
when x"8D1" => DATA <= x"4E";
when x"8D2" => DATA <= x"FA";
when x"8D3" => DATA <= x"20";
when x"8D4" => DATA <= x"4D";
when x"8D5" => DATA <= x"4F";
when x"8D6" => DATA <= x"4E";
when x"8D7" => DATA <= x"FA";
when x"8D8" => DATA <= x"1A";
when x"8D9" => DATA <= x"4E";
when x"8DA" => DATA <= x"4F";
when x"8DB" => DATA <= x"4D";
when x"8DC" => DATA <= x"4F";
when x"8DD" => DATA <= x"4E";
when x"8DE" => DATA <= x"FA";
when x"8DF" => DATA <= x"19";
when x"8E0" => DATA <= x"46";
when x"8E1" => DATA <= x"4C";
when x"8E2" => DATA <= x"4F";
when x"8E3" => DATA <= x"41";
when x"8E4" => DATA <= x"44";
when x"8E5" => DATA <= x"F9";
when x"8E6" => DATA <= x"55";
when x"8E7" => DATA <= x"44";
when x"8E8" => DATA <= x"4F";
when x"8E9" => DATA <= x"53";
when x"8EA" => DATA <= x"0D";
when x"8EB" => DATA <= x"E0";
when x"8EC" => DATA <= x"00";
when x"8ED" => DATA <= x"F9";
when x"8EE" => DATA <= x"26";
when x"8EF" => DATA <= x"A2";
when x"8F0" => DATA <= x"FF";
when x"8F1" => DATA <= x"D8";
when x"8F2" => DATA <= x"A0";
when x"8F3" => DATA <= x"00";
when x"8F4" => DATA <= x"84";
when x"8F5" => DATA <= x"DD";
when x"8F6" => DATA <= x"20";
when x"8F7" => DATA <= x"76";
when x"8F8" => DATA <= x"F8";
when x"8F9" => DATA <= x"88";
when x"8FA" => DATA <= x"C8";
when x"8FB" => DATA <= x"E8";
when x"8FC" => DATA <= x"BD";
when x"8FD" => DATA <= x"BE";
when x"8FE" => DATA <= x"F8";
when x"8FF" => DATA <= x"30";
when x"900" => DATA <= x"18";
when x"901" => DATA <= x"D9";
when x"902" => DATA <= x"00";
when x"903" => DATA <= x"01";
when x"904" => DATA <= x"F0";
when x"905" => DATA <= x"F4";
when x"906" => DATA <= x"CA";
when x"907" => DATA <= x"E8";
when x"908" => DATA <= x"BD";
when x"909" => DATA <= x"BE";
when x"90A" => DATA <= x"F8";
when x"90B" => DATA <= x"10";
when x"90C" => DATA <= x"FA";
when x"90D" => DATA <= x"E8";
when x"90E" => DATA <= x"B9";
when x"90F" => DATA <= x"00";
when x"910" => DATA <= x"01";
when x"911" => DATA <= x"C9";
when x"912" => DATA <= x"2E";
when x"913" => DATA <= x"D0";
when x"914" => DATA <= x"DD";
when x"915" => DATA <= x"C8";
when x"916" => DATA <= x"CA";
when x"917" => DATA <= x"B0";
when x"918" => DATA <= x"E3";
when x"919" => DATA <= x"85";
when x"91A" => DATA <= x"CA";
when x"91B" => DATA <= x"BD";
when x"91C" => DATA <= x"BF";
when x"91D" => DATA <= x"F8";
when x"91E" => DATA <= x"85";
when x"91F" => DATA <= x"C9";
when x"920" => DATA <= x"18";
when x"921" => DATA <= x"A2";
when x"922" => DATA <= x"00";
when x"923" => DATA <= x"6C";
when x"924" => DATA <= x"C9";
when x"925" => DATA <= x"00";
when x"926" => DATA <= x"20";
when x"927" => DATA <= x"D1";
when x"928" => DATA <= x"F7";
when x"929" => DATA <= x"43";
when x"92A" => DATA <= x"4F";
when x"92B" => DATA <= x"4D";
when x"92C" => DATA <= x"3F";
when x"92D" => DATA <= x"EA";
when x"92E" => DATA <= x"00";
when x"92F" => DATA <= x"20";
when x"930" => DATA <= x"8E";
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when x"932" => DATA <= x"50";
when x"933" => DATA <= x"FA";
when x"934" => DATA <= x"F0";
when x"935" => DATA <= x"F9";
when x"936" => DATA <= x"20";
when x"937" => DATA <= x"2B";
when x"938" => DATA <= x"FC";
when x"939" => DATA <= x"A0";
when x"93A" => DATA <= x"00";
when x"93B" => DATA <= x"20";
when x"93C" => DATA <= x"D4";
when x"93D" => DATA <= x"FF";
when x"93E" => DATA <= x"91";
when x"93F" => DATA <= x"CB";
when x"940" => DATA <= x"E6";
when x"941" => DATA <= x"CB";
when x"942" => DATA <= x"D0";
when x"943" => DATA <= x"02";
when x"944" => DATA <= x"E6";
when x"945" => DATA <= x"CC";
when x"946" => DATA <= x"A2";
when x"947" => DATA <= x"D4";
when x"948" => DATA <= x"20";
when x"949" => DATA <= x"08";
when x"94A" => DATA <= x"FA";
when x"94B" => DATA <= x"D0";
when x"94C" => DATA <= x"EE";
when x"94D" => DATA <= x"38";
when x"94E" => DATA <= x"66";
when x"94F" => DATA <= x"DD";
when x"950" => DATA <= x"18";
when x"951" => DATA <= x"66";
when x"952" => DATA <= x"DD";
when x"953" => DATA <= x"28";
when x"954" => DATA <= x"60";
when x"955" => DATA <= x"38";
when x"956" => DATA <= x"66";
when x"957" => DATA <= x"DD";
when x"958" => DATA <= x"20";
when x"959" => DATA <= x"18";
when x"95A" => DATA <= x"F8";
when x"95B" => DATA <= x"A2";
when x"95C" => DATA <= x"CB";
when x"95D" => DATA <= x"20";
when x"95E" => DATA <= x"93";
when x"95F" => DATA <= x"F8";
when x"960" => DATA <= x"F0";
when x"961" => DATA <= x"04";
when x"962" => DATA <= x"A9";
when x"963" => DATA <= x"FF";
when x"964" => DATA <= x"85";
when x"965" => DATA <= x"CD";
when x"966" => DATA <= x"20";
when x"967" => DATA <= x"76";
when x"968" => DATA <= x"FA";
when x"969" => DATA <= x"A2";
when x"96A" => DATA <= x"C9";
when x"96B" => DATA <= x"6C";
when x"96C" => DATA <= x"0C";
when x"96D" => DATA <= x"02";
when x"96E" => DATA <= x"08";
when x"96F" => DATA <= x"78";
when x"970" => DATA <= x"20";
when x"971" => DATA <= x"4F";
when x"972" => DATA <= x"F8";
when x"973" => DATA <= x"08";
when x"974" => DATA <= x"20";
when x"975" => DATA <= x"3E";
when x"976" => DATA <= x"FC";
when x"977" => DATA <= x"28";
when x"978" => DATA <= x"F0";
when x"979" => DATA <= x"B5";
when x"97A" => DATA <= x"A9";
when x"97B" => DATA <= x"00";
when x"97C" => DATA <= x"85";
when x"97D" => DATA <= x"D0";
when x"97E" => DATA <= x"85";
when x"97F" => DATA <= x"D1";
when x"980" => DATA <= x"20";
when x"981" => DATA <= x"A2";
when x"982" => DATA <= x"F9";
when x"983" => DATA <= x"90";
when x"984" => DATA <= x"C9";
when x"985" => DATA <= x"E6";
when x"986" => DATA <= x"D0";
when x"987" => DATA <= x"E6";
when x"988" => DATA <= x"CC";
when x"989" => DATA <= x"D0";
when x"98A" => DATA <= x"F5";
when x"98B" => DATA <= x"18";
when x"98C" => DATA <= x"90";
when x"98D" => DATA <= x"C0";
when x"98E" => DATA <= x"20";
when x"98F" => DATA <= x"F4";
when x"990" => DATA <= x"FF";
when x"991" => DATA <= x"C8";
when x"992" => DATA <= x"B9";
when x"993" => DATA <= x"ED";
when x"994" => DATA <= x"00";
when x"995" => DATA <= x"C9";
when x"996" => DATA <= x"0D";
when x"997" => DATA <= x"D0";
when x"998" => DATA <= x"F5";
when x"999" => DATA <= x"C8";
when x"99A" => DATA <= x"20";
when x"99B" => DATA <= x"FD";
when x"99C" => DATA <= x"F7";
when x"99D" => DATA <= x"C0";
when x"99E" => DATA <= x"0E";
when x"99F" => DATA <= x"90";
when x"9A0" => DATA <= x"F8";
when x"9A1" => DATA <= x"60";
when x"9A2" => DATA <= x"A9";
when x"9A3" => DATA <= x"00";
when x"9A4" => DATA <= x"85";
when x"9A5" => DATA <= x"DC";
when x"9A6" => DATA <= x"20";
when x"9A7" => DATA <= x"8E";
when x"9A8" => DATA <= x"FB";
when x"9A9" => DATA <= x"50";
when x"9AA" => DATA <= x"F8";
when x"9AB" => DATA <= x"D0";
when x"9AC" => DATA <= x"F5";
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when x"9AF" => DATA <= x"FB";
when x"9B0" => DATA <= x"08";
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when x"9B2" => DATA <= x"E2";
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when x"9B4" => DATA <= x"28";
when x"9B5" => DATA <= x"F0";
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when x"9B7" => DATA <= x"A5";
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when x"9BA" => DATA <= x"20";
when x"9BB" => DATA <= x"05";
when x"9BC" => DATA <= x"EA";
when x"9BD" => DATA <= x"D0";
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when x"9C0" => DATA <= x"92";
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when x"9C3" => DATA <= x"ED";
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when x"9C5" => DATA <= x"D0";
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when x"9C7" => DATA <= x"A2";
when x"9C8" => DATA <= x"02";
when x"9C9" => DATA <= x"A5";
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when x"9CB" => DATA <= x"30";
when x"9CC" => DATA <= x"13";
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when x"9CF" => DATA <= x"D5";
when x"9D0" => DATA <= x"D8";
when x"9D1" => DATA <= x"B0";
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when x"9D3" => DATA <= x"A9";
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when x"9D5" => DATA <= x"20";
when x"9D6" => DATA <= x"40";
when x"9D7" => DATA <= x"FC";
when x"9D8" => DATA <= x"20";
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when x"9DB" => DATA <= x"D0";
when x"9DC" => DATA <= x"C5";
when x"9DD" => DATA <= x"CA";
when x"9DE" => DATA <= x"D0";
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when x"9E0" => DATA <= x"20";
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when x"9E3" => DATA <= x"24";
when x"9E4" => DATA <= x"DB";
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when x"9E6" => DATA <= x"0B";
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when x"9EE" => DATA <= x"C4";
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when x"A00" => DATA <= x"53";
when x"A01" => DATA <= x"55";
when x"A02" => DATA <= x"4D";
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when x"A04" => DATA <= x"00";
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when x"A06" => DATA <= x"DB";
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when x"A1C" => DATA <= x"FA";
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when x"A1E" => DATA <= x"EA";
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when x"A22" => DATA <= x"F9";
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when x"A24" => DATA <= x"DD";
when x"A25" => DATA <= x"70";
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when x"A44" => DATA <= x"20";
when x"A45" => DATA <= x"C9";
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when x"A47" => DATA <= x"20";
when x"A48" => DATA <= x"E2";
when x"A49" => DATA <= x"FB";
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when x"A4B" => DATA <= x"92";
when x"A4C" => DATA <= x"F9";
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when x"A4E" => DATA <= x"EC";
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when x"A50" => DATA <= x"26";
when x"A51" => DATA <= x"DB";
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when x"A53" => DATA <= x"09";
when x"A54" => DATA <= x"E8";
when x"A55" => DATA <= x"20";
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when x"A58" => DATA <= x"B5";
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when x"A5B" => DATA <= x"02";
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when x"A5E" => DATA <= x"ED";
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when x"A60" => DATA <= x"D0";
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when x"A62" => DATA <= x"4C";
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when x"A64" => DATA <= x"FF";
when x"A65" => DATA <= x"20";
when x"A66" => DATA <= x"93";
when x"A67" => DATA <= x"F8";
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when x"A6A" => DATA <= x"60";
when x"A6B" => DATA <= x"A2";
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when x"A6E" => DATA <= x"65";
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when x"A70" => DATA <= x"20";
when x"A71" => DATA <= x"76";
when x"A72" => DATA <= x"FA";
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when x"A80" => DATA <= x"53";
when x"A81" => DATA <= x"59";
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when x"A84" => DATA <= x"EA";
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when x"A88" => DATA <= x"D1";
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when x"A8A" => DATA <= x"CF";
when x"A8B" => DATA <= x"48";
when x"A8C" => DATA <= x"A5";
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when x"A91" => DATA <= x"68";
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when x"AA4" => DATA <= x"88";
when x"AA5" => DATA <= x"D0";
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when x"AB0" => DATA <= x"E6";
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when x"AB6" => DATA <= x"FA";
when x"AB7" => DATA <= x"D0";
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when x"AB9" => DATA <= x"28";
when x"ABA" => DATA <= x"60";
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when x"ABC" => DATA <= x"18";
when x"ABD" => DATA <= x"F8";
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when x"AC0" => DATA <= x"20";
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when x"AD2" => DATA <= x"28";
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when x"AF2" => DATA <= x"20";
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when x"AF5" => DATA <= x"28";
when x"AF6" => DATA <= x"F0";
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when x"AF8" => DATA <= x"A2";
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when x"AFC" => DATA <= x"95";
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when x"B02" => DATA <= x"D0";
when x"B03" => DATA <= x"86";
when x"B04" => DATA <= x"D1";
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when x"B0E" => DATA <= x"66";
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when x"B11" => DATA <= x"A2";
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when x"B13" => DATA <= x"A5";
when x"B14" => DATA <= x"D5";
when x"B15" => DATA <= x"E5";
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when x"B17" => DATA <= x"85";
when x"B18" => DATA <= x"CF";
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when x"B1C" => DATA <= x"D4";
when x"B1D" => DATA <= x"08";
when x"B1E" => DATA <= x"66";
when x"B1F" => DATA <= x"D2";
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when x"B21" => DATA <= x"90";
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when x"B23" => DATA <= x"18";
when x"B24" => DATA <= x"F0";
when x"B25" => DATA <= x"03";
when x"B26" => DATA <= x"86";
when x"B27" => DATA <= x"CF";
when x"B28" => DATA <= x"38";
when x"B29" => DATA <= x"66";
when x"B2A" => DATA <= x"D2";
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when x"B2C" => DATA <= x"20";
when x"B2D" => DATA <= x"3B";
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when x"B2F" => DATA <= x"E6";
when x"B30" => DATA <= x"D0";
when x"B31" => DATA <= x"E6";
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when x"B35" => DATA <= x"26";
when x"B36" => DATA <= x"D2";
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when x"B39" => DATA <= x"28";
when x"B3A" => DATA <= x"60";
when x"B3B" => DATA <= x"A2";
when x"B3C" => DATA <= x"07";
when x"B3D" => DATA <= x"20";
when x"B3E" => DATA <= x"7A";
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when x"B40" => DATA <= x"86";
when x"B41" => DATA <= x"DC";
when x"B42" => DATA <= x"A0";
when x"B43" => DATA <= x"04";
when x"B44" => DATA <= x"A9";
when x"B45" => DATA <= x"2A";
when x"B46" => DATA <= x"20";
when x"B47" => DATA <= x"D1";
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when x"B49" => DATA <= x"88";
when x"B4A" => DATA <= x"D0";
when x"B4B" => DATA <= x"F8";
when x"B4C" => DATA <= x"B1";
when x"B4D" => DATA <= x"C9";
when x"B4E" => DATA <= x"20";
when x"B4F" => DATA <= x"D1";
when x"B50" => DATA <= x"FF";
when x"B51" => DATA <= x"C8";
when x"B52" => DATA <= x"C9";
when x"B53" => DATA <= x"0D";
when x"B54" => DATA <= x"D0";
when x"B55" => DATA <= x"F6";
when x"B56" => DATA <= x"A0";
when x"B57" => DATA <= x"08";
when x"B58" => DATA <= x"B9";
when x"B59" => DATA <= x"CA";
when x"B5A" => DATA <= x"00";
when x"B5B" => DATA <= x"20";
when x"B5C" => DATA <= x"D1";
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when x"B5E" => DATA <= x"88";
when x"B5F" => DATA <= x"D0";
when x"B60" => DATA <= x"F7";
when x"B61" => DATA <= x"20";
when x"B62" => DATA <= x"81";
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when x"B64" => DATA <= x"24";
when x"B65" => DATA <= x"D2";
when x"B66" => DATA <= x"50";
when x"B67" => DATA <= x"0B";
when x"B68" => DATA <= x"88";
when x"B69" => DATA <= x"C8";
when x"B6A" => DATA <= x"B1";
when x"B6B" => DATA <= x"D3";
when x"B6C" => DATA <= x"20";
when x"B6D" => DATA <= x"D1";
when x"B6E" => DATA <= x"FF";
when x"B6F" => DATA <= x"C4";
when x"B70" => DATA <= x"CF";
when x"B71" => DATA <= x"D0";
when x"B72" => DATA <= x"F6";
when x"B73" => DATA <= x"A5";
when x"B74" => DATA <= x"DC";
when x"B75" => DATA <= x"20";
when x"B76" => DATA <= x"D1";
when x"B77" => DATA <= x"FF";
when x"B78" => DATA <= x"A2";
when x"B79" => DATA <= x"04";
when x"B7A" => DATA <= x"8E";
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when x"B7C" => DATA <= x"B0";
when x"B7D" => DATA <= x"A2";
when x"B7E" => DATA <= x"78";
when x"B7F" => DATA <= x"D0";
when x"B80" => DATA <= x"02";
when x"B81" => DATA <= x"A2";
when x"B82" => DATA <= x"1E";
when x"B83" => DATA <= x"20";
when x"B84" => DATA <= x"66";
when x"B85" => DATA <= x"FE";
when x"B86" => DATA <= x"CA";
when x"B87" => DATA <= x"D0";
when x"B88" => DATA <= x"FA";
when x"B89" => DATA <= x"60";
when x"B8A" => DATA <= x"A2";
when x"B8B" => DATA <= x"06";
when x"B8C" => DATA <= x"D0";
when x"B8D" => DATA <= x"F5";
when x"B8E" => DATA <= x"2C";
when x"B8F" => DATA <= x"01";
when x"B90" => DATA <= x"B0";
when x"B91" => DATA <= x"10";
when x"B92" => DATA <= x"FB";
when x"B93" => DATA <= x"50";
when x"B94" => DATA <= x"F9";
when x"B95" => DATA <= x"A0";
when x"B96" => DATA <= x"00";
when x"B97" => DATA <= x"85";
when x"B98" => DATA <= x"C3";
when x"B99" => DATA <= x"A9";
when x"B9A" => DATA <= x"10";
when x"B9B" => DATA <= x"85";
when x"B9C" => DATA <= x"C2";
when x"B9D" => DATA <= x"2C";
when x"B9E" => DATA <= x"01";
when x"B9F" => DATA <= x"B0";
when x"BA0" => DATA <= x"10";
when x"BA1" => DATA <= x"0F";
when x"BA2" => DATA <= x"50";
when x"BA3" => DATA <= x"0D";
when x"BA4" => DATA <= x"20";
when x"BA5" => DATA <= x"BD";
when x"BA6" => DATA <= x"FC";
when x"BA7" => DATA <= x"B0";
when x"BA8" => DATA <= x"EC";
when x"BA9" => DATA <= x"C6";
when x"BAA" => DATA <= x"C3";
when x"BAB" => DATA <= x"D0";
when x"BAC" => DATA <= x"F0";
when x"BAD" => DATA <= x"C6";
when x"BAE" => DATA <= x"C2";
when x"BAF" => DATA <= x"D0";
when x"BB0" => DATA <= x"EC";
when x"BB1" => DATA <= x"70";
when x"BB2" => DATA <= x"01";
when x"BB3" => DATA <= x"60";
when x"BB4" => DATA <= x"A0";
when x"BB5" => DATA <= x"04";
when x"BB6" => DATA <= x"08";
when x"BB7" => DATA <= x"20";
when x"BB8" => DATA <= x"E4";
when x"BB9" => DATA <= x"FB";
when x"BBA" => DATA <= x"28";
when x"BBB" => DATA <= x"A0";
when x"BBC" => DATA <= x"04";
when x"BBD" => DATA <= x"A9";
when x"BBE" => DATA <= x"2A";
when x"BBF" => DATA <= x"D9";
when x"BC0" => DATA <= x"D3";
when x"BC1" => DATA <= x"00";
when x"BC2" => DATA <= x"D0";
when x"BC3" => DATA <= x"03";
when x"BC4" => DATA <= x"88";
when x"BC5" => DATA <= x"D0";
when x"BC6" => DATA <= x"F8";
when x"BC7" => DATA <= x"60";
when x"BC8" => DATA <= x"C8";
when x"BC9" => DATA <= x"20";
when x"BCA" => DATA <= x"D4";
when x"BCB" => DATA <= x"FF";
when x"BCC" => DATA <= x"99";
when x"BCD" => DATA <= x"ED";
when x"BCE" => DATA <= x"00";
when x"BCF" => DATA <= x"C9";
when x"BD0" => DATA <= x"0D";
when x"BD1" => DATA <= x"D0";
when x"BD2" => DATA <= x"F5";
when x"BD3" => DATA <= x"A0";
when x"BD4" => DATA <= x"FF";
when x"BD5" => DATA <= x"C8";
when x"BD6" => DATA <= x"B1";
when x"BD7" => DATA <= x"C9";
when x"BD8" => DATA <= x"D9";
when x"BD9" => DATA <= x"ED";
when x"BDA" => DATA <= x"00";
when x"BDB" => DATA <= x"D0";
when x"BDC" => DATA <= x"EA";
when x"BDD" => DATA <= x"C9";
when x"BDE" => DATA <= x"0D";
when x"BDF" => DATA <= x"D0";
when x"BE0" => DATA <= x"F4";
when x"BE1" => DATA <= x"60";
when x"BE2" => DATA <= x"A0";
when x"BE3" => DATA <= x"08";
when x"BE4" => DATA <= x"20";
when x"BE5" => DATA <= x"D4";
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when x"BE7" => DATA <= x"99";
when x"BE8" => DATA <= x"D3";
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when x"BEA" => DATA <= x"88";
when x"BEB" => DATA <= x"D0";
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when x"BED" => DATA <= x"60";
when x"BEE" => DATA <= x"86";
when x"BEF" => DATA <= x"EC";
when x"BF0" => DATA <= x"84";
when x"BF1" => DATA <= x"C3";
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when x"BF3" => DATA <= x"78";
when x"BF4" => DATA <= x"A9";
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when x"BF6" => DATA <= x"85";
when x"BF7" => DATA <= x"C0";
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when x"BF9" => DATA <= x"BD";
when x"BFA" => DATA <= x"FC";
when x"BFB" => DATA <= x"90";
when x"BFC" => DATA <= x"F7";
when x"BFD" => DATA <= x"E6";
when x"BFE" => DATA <= x"C0";
when x"BFF" => DATA <= x"10";
when x"C00" => DATA <= x"F7";
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when x"C02" => DATA <= x"53";
when x"C03" => DATA <= x"85";
when x"C04" => DATA <= x"C4";
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when x"C06" => DATA <= x"00";
when x"C07" => DATA <= x"AC";
when x"C08" => DATA <= x"02";
when x"C09" => DATA <= x"B0";
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when x"C0B" => DATA <= x"CD";
when x"C0C" => DATA <= x"FC";
when x"C0D" => DATA <= x"F0";
when x"C0E" => DATA <= x"00";
when x"C0F" => DATA <= x"F0";
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when x"C11" => DATA <= x"E8";
when x"C12" => DATA <= x"C6";
when x"C13" => DATA <= x"C4";
when x"C14" => DATA <= x"D0";
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when x"C18" => DATA <= x"66";
when x"C19" => DATA <= x"C0";
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when x"C1B" => DATA <= x"E5";
when x"C1C" => DATA <= x"A5";
when x"C1D" => DATA <= x"C0";
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when x"C1F" => DATA <= x"A4";
when x"C20" => DATA <= x"C3";
when x"C21" => DATA <= x"A6";
when x"C22" => DATA <= x"EC";
when x"C23" => DATA <= x"48";
when x"C24" => DATA <= x"18";
when x"C25" => DATA <= x"65";
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when x"C27" => DATA <= x"85";
when x"C28" => DATA <= x"DC";
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when x"C2A" => DATA <= x"60";
when x"C2B" => DATA <= x"A5";
when x"C2C" => DATA <= x"CD";
when x"C2D" => DATA <= x"30";
when x"C2E" => DATA <= x"08";
when x"C2F" => DATA <= x"A5";
when x"C30" => DATA <= x"D4";
when x"C31" => DATA <= x"85";
when x"C32" => DATA <= x"CB";
when x"C33" => DATA <= x"A5";
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when x"C35" => DATA <= x"85";
when x"C36" => DATA <= x"CC";
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when x"C38" => DATA <= x"B0";
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when x"C3A" => DATA <= x"A9";
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when x"C3C" => DATA <= x"D0";
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when x"C3E" => DATA <= x"A9";
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when x"C40" => DATA <= x"A2";
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when x"C42" => DATA <= x"8E";
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when x"C44" => DATA <= x"B0";
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when x"C46" => DATA <= x"EA";
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when x"C49" => DATA <= x"C9";
when x"C4A" => DATA <= x"05";
when x"C4B" => DATA <= x"F0";
when x"C4C" => DATA <= x"16";
when x"C4D" => DATA <= x"B0";
when x"C4E" => DATA <= x"09";
when x"C4F" => DATA <= x"20";
when x"C50" => DATA <= x"D1";
when x"C51" => DATA <= x"F7";
when x"C52" => DATA <= x"50";
when x"C53" => DATA <= x"4C";
when x"C54" => DATA <= x"41";
when x"C55" => DATA <= x"59";
when x"C56" => DATA <= x"D0";
when x"C57" => DATA <= x"15";
when x"C58" => DATA <= x"20";
when x"C59" => DATA <= x"D1";
when x"C5A" => DATA <= x"F7";
when x"C5B" => DATA <= x"52";
when x"C5C" => DATA <= x"45";
when x"C5D" => DATA <= x"43";
when x"C5E" => DATA <= x"4F";
when x"C5F" => DATA <= x"52";
when x"C60" => DATA <= x"44";
when x"C61" => DATA <= x"D0";
when x"C62" => DATA <= x"0A";
when x"C63" => DATA <= x"20";
when x"C64" => DATA <= x"D1";
when x"C65" => DATA <= x"F7";
when x"C66" => DATA <= x"52";
when x"C67" => DATA <= x"45";
when x"C68" => DATA <= x"57";
when x"C69" => DATA <= x"49";
when x"C6A" => DATA <= x"4E";
when x"C6B" => DATA <= x"44";
when x"C6C" => DATA <= x"EA";
when x"C6D" => DATA <= x"20";
when x"C6E" => DATA <= x"D1";
when x"C6F" => DATA <= x"F7";
when x"C70" => DATA <= x"20";
when x"C71" => DATA <= x"54";
when x"C72" => DATA <= x"41";
when x"C73" => DATA <= x"50";
when x"C74" => DATA <= x"45";
when x"C75" => DATA <= x"EA";
when x"C76" => DATA <= x"20";
when x"C77" => DATA <= x"E3";
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when x"C79" => DATA <= x"4C";
when x"C7A" => DATA <= x"ED";
when x"C7B" => DATA <= x"FF";
when x"C7C" => DATA <= x"86";
when x"C7D" => DATA <= x"EC";
when x"C7E" => DATA <= x"84";
when x"C7F" => DATA <= x"C3";
when x"C80" => DATA <= x"08";
when x"C81" => DATA <= x"78";
when x"C82" => DATA <= x"48";
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when x"C84" => DATA <= x"23";
when x"C85" => DATA <= x"FC";
when x"C86" => DATA <= x"85";
when x"C87" => DATA <= x"C0";
when x"C88" => DATA <= x"20";
when x"C89" => DATA <= x"D8";
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when x"C8C" => DATA <= x"0A";
when x"C8D" => DATA <= x"85";
when x"C8E" => DATA <= x"C1";
when x"C8F" => DATA <= x"18";
when x"C90" => DATA <= x"90";
when x"C91" => DATA <= x"0A";
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when x"C93" => DATA <= x"07";
when x"C94" => DATA <= x"8E";
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when x"C96" => DATA <= x"B0";
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when x"C98" => DATA <= x"DA";
when x"C99" => DATA <= x"FC";
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when x"C9B" => DATA <= x"13";
when x"C9C" => DATA <= x"A0";
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when x"C9E" => DATA <= x"A9";
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when x"CA0" => DATA <= x"8D";
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when x"CA2" => DATA <= x"B0";
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when x"CA4" => DATA <= x"D8";
when x"CA5" => DATA <= x"FC";
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when x"CA7" => DATA <= x"02";
when x"CA8" => DATA <= x"B0";
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when x"CAA" => DATA <= x"D8";
when x"CAB" => DATA <= x"FC";
when x"CAC" => DATA <= x"88";
when x"CAD" => DATA <= x"D0";
when x"CAE" => DATA <= x"EF";
when x"CAF" => DATA <= x"38";
when x"CB0" => DATA <= x"66";
when x"CB1" => DATA <= x"C0";
when x"CB2" => DATA <= x"C6";
when x"CB3" => DATA <= x"C1";
when x"CB4" => DATA <= x"D0";
when x"CB5" => DATA <= x"DA";
when x"CB6" => DATA <= x"A4";
when x"CB7" => DATA <= x"C3";
when x"CB8" => DATA <= x"A6";
when x"CB9" => DATA <= x"EC";
when x"CBA" => DATA <= x"68";
when x"CBB" => DATA <= x"28";
when x"CBC" => DATA <= x"60";
when x"CBD" => DATA <= x"A2";
when x"CBE" => DATA <= x"00";
when x"CBF" => DATA <= x"AC";
when x"CC0" => DATA <= x"02";
when x"CC1" => DATA <= x"B0";
when x"CC2" => DATA <= x"E8";
when x"CC3" => DATA <= x"F0";
when x"CC4" => DATA <= x"07";
when x"CC5" => DATA <= x"20";
when x"CC6" => DATA <= x"CD";
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when x"CC8" => DATA <= x"F0";
when x"CC9" => DATA <= x"F8";
when x"CCA" => DATA <= x"E0";
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when x"CCC" => DATA <= x"60";
when x"CCD" => DATA <= x"84";
when x"CCE" => DATA <= x"C5";
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when x"CD0" => DATA <= x"02";
when x"CD1" => DATA <= x"B0";
when x"CD2" => DATA <= x"A8";
when x"CD3" => DATA <= x"45";
when x"CD4" => DATA <= x"C5";
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when x"CD6" => DATA <= x"20";
when x"CD7" => DATA <= x"60";
when x"CD8" => DATA <= x"A2";
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when x"CDA" => DATA <= x"A9";
when x"CDB" => DATA <= x"10";
when x"CDC" => DATA <= x"2C";
when x"CDD" => DATA <= x"02";
when x"CDE" => DATA <= x"B0";
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when x"CE0" => DATA <= x"FB";
when x"CE1" => DATA <= x"2C";
when x"CE2" => DATA <= x"02";
when x"CE3" => DATA <= x"B0";
when x"CE4" => DATA <= x"D0";
when x"CE5" => DATA <= x"FB";
when x"CE6" => DATA <= x"CA";
when x"CE7" => DATA <= x"10";
when x"CE8" => DATA <= x"F3";
when x"CE9" => DATA <= x"60";
when x"CEA" => DATA <= x"C9";
when x"CEB" => DATA <= x"06";
when x"CEC" => DATA <= x"F0";
when x"CED" => DATA <= x"1D";
when x"CEE" => DATA <= x"C9";
when x"CEF" => DATA <= x"15";
when x"CF0" => DATA <= x"F0";
when x"CF1" => DATA <= x"1F";
when x"CF2" => DATA <= x"A4";
when x"CF3" => DATA <= x"E0";
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when x"CF5" => DATA <= x"23";
when x"CF6" => DATA <= x"C9";
when x"CF7" => DATA <= x"1B";
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when x"CF9" => DATA <= x"11";
when x"CFA" => DATA <= x"C9";
when x"CFB" => DATA <= x"07";
when x"CFC" => DATA <= x"F0";
when x"CFD" => DATA <= x"1C";
when x"CFE" => DATA <= x"20";
when x"CFF" => DATA <= x"44";
when x"D00" => DATA <= x"FD";
when x"D01" => DATA <= x"A2";
when x"D02" => DATA <= x"0A";
when x"D03" => DATA <= x"20";
when x"D04" => DATA <= x"C5";
when x"D05" => DATA <= x"FE";
when x"D06" => DATA <= x"D0";
when x"D07" => DATA <= x"21";
when x"D08" => DATA <= x"4C";
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when x"D0A" => DATA <= x"FE";
when x"D0B" => DATA <= x"18";
when x"D0C" => DATA <= x"A2";
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when x"D0E" => DATA <= x"8E";
when x"D0F" => DATA <= x"00";
when x"D10" => DATA <= x"B0";
when x"D11" => DATA <= x"A2";
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when x"D13" => DATA <= x"08";
when x"D14" => DATA <= x"16";
when x"D15" => DATA <= x"DE";
when x"D16" => DATA <= x"28";
when x"D17" => DATA <= x"76";
when x"D18" => DATA <= x"DE";
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when x"D1A" => DATA <= x"A9";
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when x"D1C" => DATA <= x"A8";
when x"D1D" => DATA <= x"8D";
when x"D1E" => DATA <= x"03";
when x"D1F" => DATA <= x"B0";
when x"D20" => DATA <= x"CA";
when x"D21" => DATA <= x"D0";
when x"D22" => DATA <= x"FD";
when x"D23" => DATA <= x"49";
when x"D24" => DATA <= x"01";
when x"D25" => DATA <= x"C8";
when x"D26" => DATA <= x"10";
when x"D27" => DATA <= x"F5";
when x"D28" => DATA <= x"60";
when x"D29" => DATA <= x"C9";
when x"D2A" => DATA <= x"20";
when x"D2B" => DATA <= x"90";
when x"D2C" => DATA <= x"17";
when x"D2D" => DATA <= x"69";
when x"D2E" => DATA <= x"1F";
when x"D2F" => DATA <= x"30";
when x"D30" => DATA <= x"02";
when x"D31" => DATA <= x"49";
when x"D32" => DATA <= x"60";
when x"D33" => DATA <= x"20";
when x"D34" => DATA <= x"6B";
when x"D35" => DATA <= x"FE";
when x"D36" => DATA <= x"91";
when x"D37" => DATA <= x"DE";
when x"D38" => DATA <= x"C8";
when x"D39" => DATA <= x"C0";
when x"D3A" => DATA <= x"20";
when x"D3B" => DATA <= x"90";
when x"D3C" => DATA <= x"05";
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when x"D3E" => DATA <= x"EC";
when x"D3F" => DATA <= x"FD";
when x"D40" => DATA <= x"A0";
when x"D41" => DATA <= x"00";
when x"D42" => DATA <= x"84";
when x"D43" => DATA <= x"E0";
when x"D44" => DATA <= x"48";
when x"D45" => DATA <= x"20";
when x"D46" => DATA <= x"6B";
when x"D47" => DATA <= x"FE";
when x"D48" => DATA <= x"B1";
when x"D49" => DATA <= x"DE";
when x"D4A" => DATA <= x"45";
when x"D4B" => DATA <= x"E1";
when x"D4C" => DATA <= x"91";
when x"D4D" => DATA <= x"DE";
when x"D4E" => DATA <= x"68";
when x"D4F" => DATA <= x"60";
when x"D50" => DATA <= x"20";
when x"D51" => DATA <= x"35";
when x"D52" => DATA <= x"FE";
when x"D53" => DATA <= x"A9";
when x"D54" => DATA <= x"20";
when x"D55" => DATA <= x"20";
when x"D56" => DATA <= x"6B";
when x"D57" => DATA <= x"FE";
when x"D58" => DATA <= x"91";
when x"D59" => DATA <= x"DE";
when x"D5A" => DATA <= x"10";
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when x"D5C" => DATA <= x"20";
when x"D5D" => DATA <= x"35";
when x"D5E" => DATA <= x"FE";
when x"D5F" => DATA <= x"4C";
when x"D60" => DATA <= x"42";
when x"D61" => DATA <= x"FD";
when x"D62" => DATA <= x"20";
when x"D63" => DATA <= x"EC";
when x"D64" => DATA <= x"FD";
when x"D65" => DATA <= x"A4";
when x"D66" => DATA <= x"E0";
when x"D67" => DATA <= x"10";
when x"D68" => DATA <= x"D9";
when x"D69" => DATA <= x"A0";
when x"D6A" => DATA <= x"80";
when x"D6B" => DATA <= x"84";
when x"D6C" => DATA <= x"E1";
when x"D6D" => DATA <= x"A0";
when x"D6E" => DATA <= x"00";
when x"D6F" => DATA <= x"8C";
when x"D70" => DATA <= x"00";
when x"D71" => DATA <= x"B0";
when x"D72" => DATA <= x"A9";
when x"D73" => DATA <= x"20";
when x"D74" => DATA <= x"99";
when x"D75" => DATA <= x"00";
when x"D76" => DATA <= x"80";
when x"D77" => DATA <= x"99";
when x"D78" => DATA <= x"00";
when x"D79" => DATA <= x"81";
when x"D7A" => DATA <= x"C8";
when x"D7B" => DATA <= x"D0";
when x"D7C" => DATA <= x"F7";
when x"D7D" => DATA <= x"A9";
when x"D7E" => DATA <= x"80";
when x"D7F" => DATA <= x"A0";
when x"D80" => DATA <= x"00";
when x"D81" => DATA <= x"85";
when x"D82" => DATA <= x"DF";
when x"D83" => DATA <= x"84";
when x"D84" => DATA <= x"DE";
when x"D85" => DATA <= x"F0";
when x"D86" => DATA <= x"BB";
when x"D87" => DATA <= x"20";
when x"D88" => DATA <= x"3A";
when x"D89" => DATA <= x"FE";
when x"D8A" => DATA <= x"4C";
when x"D8B" => DATA <= x"42";
when x"D8C" => DATA <= x"FD";
when x"D8D" => DATA <= x"18";
when x"D8E" => DATA <= x"A9";
when x"D8F" => DATA <= x"10";
when x"D90" => DATA <= x"85";
when x"D91" => DATA <= x"E6";
when x"D92" => DATA <= x"A2";
when x"D93" => DATA <= x"08";
when x"D94" => DATA <= x"20";
when x"D95" => DATA <= x"13";
when x"D96" => DATA <= x"FD";
when x"D97" => DATA <= x"4C";
when x"D98" => DATA <= x"44";
when x"D99" => DATA <= x"FD";
when x"D9A" => DATA <= x"A5";
when x"D9B" => DATA <= x"E7";
when x"D9C" => DATA <= x"49";
when x"D9D" => DATA <= x"60";
when x"D9E" => DATA <= x"85";
when x"D9F" => DATA <= x"E7";
when x"DA0" => DATA <= x"B0";
when x"DA1" => DATA <= x"09";
when x"DA2" => DATA <= x"29";
when x"DA3" => DATA <= x"05";
when x"DA4" => DATA <= x"2E";
when x"DA5" => DATA <= x"01";
when x"DA6" => DATA <= x"B0";
when x"DA7" => DATA <= x"2A";
when x"DA8" => DATA <= x"20";
when x"DA9" => DATA <= x"EA";
when x"DAA" => DATA <= x"FC";
when x"DAB" => DATA <= x"4C";
when x"DAC" => DATA <= x"9A";
when x"DAD" => DATA <= x"FE";
when x"DAE" => DATA <= x"A4";
when x"DAF" => DATA <= x"E0";
when x"DB0" => DATA <= x"20";
when x"DB1" => DATA <= x"6B";
when x"DB2" => DATA <= x"FE";
when x"DB3" => DATA <= x"B1";
when x"DB4" => DATA <= x"DE";
when x"DB5" => DATA <= x"45";
when x"DB6" => DATA <= x"E1";
when x"DB7" => DATA <= x"30";
when x"DB8" => DATA <= x"02";
when x"DB9" => DATA <= x"49";
when x"DBA" => DATA <= x"60";
when x"DBB" => DATA <= x"E9";
when x"DBC" => DATA <= x"20";
when x"DBD" => DATA <= x"4C";
when x"DBE" => DATA <= x"E9";
when x"DBF" => DATA <= x"FD";
when x"DC0" => DATA <= x"A9";
when x"DC1" => DATA <= x"5F";
when x"DC2" => DATA <= x"49";
when x"DC3" => DATA <= x"20";
when x"DC4" => DATA <= x"D0";
when x"DC5" => DATA <= x"23";
when x"DC6" => DATA <= x"45";
when x"DC7" => DATA <= x"E7";
when x"DC8" => DATA <= x"2C";
when x"DC9" => DATA <= x"01";
when x"DCA" => DATA <= x"B0";
when x"DCB" => DATA <= x"30";
when x"DCC" => DATA <= x"02";
when x"DCD" => DATA <= x"49";
when x"DCE" => DATA <= x"60";
when x"DCF" => DATA <= x"4C";
when x"DD0" => DATA <= x"DF";
when x"DD1" => DATA <= x"FD";
when x"DD2" => DATA <= x"69";
when x"DD3" => DATA <= x"39";
when x"DD4" => DATA <= x"90";
when x"DD5" => DATA <= x"F2";
when x"DD6" => DATA <= x"49";
when x"DD7" => DATA <= x"10";
when x"DD8" => DATA <= x"2C";
when x"DD9" => DATA <= x"01";
when x"DDA" => DATA <= x"B0";
when x"DDB" => DATA <= x"30";
when x"DDC" => DATA <= x"02";
when x"DDD" => DATA <= x"49";
when x"DDE" => DATA <= x"10";
when x"DDF" => DATA <= x"18";
when x"DE0" => DATA <= x"69";
when x"DE1" => DATA <= x"20";
when x"DE2" => DATA <= x"2C";
when x"DE3" => DATA <= x"01";
when x"DE4" => DATA <= x"B0";
when x"DE5" => DATA <= x"70";
when x"DE6" => DATA <= x"02";
when x"DE7" => DATA <= x"29";
when x"DE8" => DATA <= x"1F";
when x"DE9" => DATA <= x"4C";
when x"DEA" => DATA <= x"60";
when x"DEB" => DATA <= x"FE";
when x"DEC" => DATA <= x"A5";
when x"DED" => DATA <= x"DE";
when x"DEE" => DATA <= x"A4";
when x"DEF" => DATA <= x"DF";
when x"DF0" => DATA <= x"C0";
when x"DF1" => DATA <= x"81";
when x"DF2" => DATA <= x"90";
when x"DF3" => DATA <= x"38";
when x"DF4" => DATA <= x"C9";
when x"DF5" => DATA <= x"E0";
when x"DF6" => DATA <= x"90";
when x"DF7" => DATA <= x"34";
when x"DF8" => DATA <= x"A4";
when x"DF9" => DATA <= x"E6";
when x"DFA" => DATA <= x"30";
when x"DFB" => DATA <= x"0C";
when x"DFC" => DATA <= x"88";
when x"DFD" => DATA <= x"D0";
when x"DFE" => DATA <= x"07";
when x"DFF" => DATA <= x"20";
when x"E00" => DATA <= x"71";
when x"E01" => DATA <= x"FE";
when x"E02" => DATA <= x"B0";
when x"E03" => DATA <= x"FB";
when x"E04" => DATA <= x"A0";
when x"E05" => DATA <= x"10";
when x"E06" => DATA <= x"84";
when x"E07" => DATA <= x"E6";
when x"E08" => DATA <= x"A0";
when x"E09" => DATA <= x"20";
when x"E0A" => DATA <= x"20";
when x"E0B" => DATA <= x"66";
when x"E0C" => DATA <= x"FE";
when x"E0D" => DATA <= x"B9";
when x"E0E" => DATA <= x"00";
when x"E0F" => DATA <= x"80";
when x"E10" => DATA <= x"99";
when x"E11" => DATA <= x"E0";
when x"E12" => DATA <= x"7F";
when x"E13" => DATA <= x"C8";
when x"E14" => DATA <= x"D0";
when x"E15" => DATA <= x"F7";
when x"E16" => DATA <= x"20";
when x"E17" => DATA <= x"6B";
when x"E18" => DATA <= x"FE";
when x"E19" => DATA <= x"B9";
when x"E1A" => DATA <= x"00";
when x"E1B" => DATA <= x"81";
when x"E1C" => DATA <= x"99";
when x"E1D" => DATA <= x"E0";
when x"E1E" => DATA <= x"80";
when x"E1F" => DATA <= x"C8";
when x"E20" => DATA <= x"D0";
when x"E21" => DATA <= x"F7";
when x"E22" => DATA <= x"A0";
when x"E23" => DATA <= x"1F";
when x"E24" => DATA <= x"A9";
when x"E25" => DATA <= x"20";
when x"E26" => DATA <= x"91";
when x"E27" => DATA <= x"DE";
when x"E28" => DATA <= x"88";
when x"E29" => DATA <= x"10";
when x"E2A" => DATA <= x"FB";
when x"E2B" => DATA <= x"60";
when x"E2C" => DATA <= x"69";
when x"E2D" => DATA <= x"20";
when x"E2E" => DATA <= x"85";
when x"E2F" => DATA <= x"DE";
when x"E30" => DATA <= x"D0";
when x"E31" => DATA <= x"02";
when x"E32" => DATA <= x"E6";
when x"E33" => DATA <= x"DF";
when x"E34" => DATA <= x"60";
when x"E35" => DATA <= x"88";
when x"E36" => DATA <= x"10";
when x"E37" => DATA <= x"19";
when x"E38" => DATA <= x"A0";
when x"E39" => DATA <= x"1F";
when x"E3A" => DATA <= x"A5";
when x"E3B" => DATA <= x"DE";
when x"E3C" => DATA <= x"D0";
when x"E3D" => DATA <= x"0B";
when x"E3E" => DATA <= x"A6";
when x"E3F" => DATA <= x"DF";
when x"E40" => DATA <= x"E0";
when x"E41" => DATA <= x"80";
when x"E42" => DATA <= x"D0";
when x"E43" => DATA <= x"05";
when x"E44" => DATA <= x"68";
when x"E45" => DATA <= x"68";
when x"E46" => DATA <= x"4C";
when x"E47" => DATA <= x"65";
when x"E48" => DATA <= x"FD";
when x"E49" => DATA <= x"E9";
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when x"E4B" => DATA <= x"85";
when x"E4C" => DATA <= x"DE";
when x"E4D" => DATA <= x"B0";
when x"E4E" => DATA <= x"02";
when x"E4F" => DATA <= x"C6";
when x"E50" => DATA <= x"DF";
when x"E51" => DATA <= x"60";
when x"E52" => DATA <= x"20";
when x"E53" => DATA <= x"FB";
when x"E54" => DATA <= x"FE";
when x"E55" => DATA <= x"08";
when x"E56" => DATA <= x"48";
when x"E57" => DATA <= x"D8";
when x"E58" => DATA <= x"84";
when x"E59" => DATA <= x"E5";
when x"E5A" => DATA <= x"86";
when x"E5B" => DATA <= x"E4";
when x"E5C" => DATA <= x"20";
when x"E5D" => DATA <= x"EA";
when x"E5E" => DATA <= x"FC";
when x"E5F" => DATA <= x"68";
when x"E60" => DATA <= x"A6";
when x"E61" => DATA <= x"E4";
when x"E62" => DATA <= x"A4";
when x"E63" => DATA <= x"E5";
when x"E64" => DATA <= x"28";
when x"E65" => DATA <= x"60";
when x"E66" => DATA <= x"2C";
when x"E67" => DATA <= x"02";
when x"E68" => DATA <= x"B0";
when x"E69" => DATA <= x"10";
when x"E6A" => DATA <= x"FB";
when x"E6B" => DATA <= x"2C";
when x"E6C" => DATA <= x"02";
when x"E6D" => DATA <= x"B0";
when x"E6E" => DATA <= x"30";
when x"E6F" => DATA <= x"FB";
when x"E70" => DATA <= x"60";
when x"E71" => DATA <= x"A0";
when x"E72" => DATA <= x"3B";
when x"E73" => DATA <= x"18";
when x"E74" => DATA <= x"A9";
when x"E75" => DATA <= x"20";
when x"E76" => DATA <= x"A2";
when x"E77" => DATA <= x"0A";
when x"E78" => DATA <= x"2C";
when x"E79" => DATA <= x"01";
when x"E7A" => DATA <= x"B0";
when x"E7B" => DATA <= x"F0";
when x"E7C" => DATA <= x"08";
when x"E7D" => DATA <= x"EE";
when x"E7E" => DATA <= x"00";
when x"E7F" => DATA <= x"B0";
when x"E80" => DATA <= x"88";
when x"E81" => DATA <= x"CA";
when x"E82" => DATA <= x"D0";
when x"E83" => DATA <= x"F4";
when x"E84" => DATA <= x"4A";
when x"E85" => DATA <= x"08";
when x"E86" => DATA <= x"48";
when x"E87" => DATA <= x"AD";
when x"E88" => DATA <= x"00";
when x"E89" => DATA <= x"B0";
when x"E8A" => DATA <= x"29";
when x"E8B" => DATA <= x"F0";
when x"E8C" => DATA <= x"8D";
when x"E8D" => DATA <= x"00";
when x"E8E" => DATA <= x"B0";
when x"E8F" => DATA <= x"68";
when x"E90" => DATA <= x"28";
when x"E91" => DATA <= x"D0";
when x"E92" => DATA <= x"E3";
when x"E93" => DATA <= x"60";
when x"E94" => DATA <= x"08";
when x"E95" => DATA <= x"D8";
when x"E96" => DATA <= x"86";
when x"E97" => DATA <= x"E4";
when x"E98" => DATA <= x"84";
when x"E99" => DATA <= x"E5";
when x"E9A" => DATA <= x"2C";
when x"E9B" => DATA <= x"02";
when x"E9C" => DATA <= x"B0";
when x"E9D" => DATA <= x"50";
when x"E9E" => DATA <= x"05";
when x"E9F" => DATA <= x"20";
when x"EA0" => DATA <= x"71";
when x"EA1" => DATA <= x"FE";
when x"EA2" => DATA <= x"90";
when x"EA3" => DATA <= x"F6";
when x"EA4" => DATA <= x"20";
when x"EA5" => DATA <= x"8A";
when x"EA6" => DATA <= x"FB";
when x"EA7" => DATA <= x"20";
when x"EA8" => DATA <= x"71";
when x"EA9" => DATA <= x"FE";
when x"EAA" => DATA <= x"B0";
when x"EAB" => DATA <= x"FB";
when x"EAC" => DATA <= x"20";
when x"EAD" => DATA <= x"71";
when x"EAE" => DATA <= x"FE";
when x"EAF" => DATA <= x"B0";
when x"EB0" => DATA <= x"F6";
when x"EB1" => DATA <= x"98";
when x"EB2" => DATA <= x"A2";
when x"EB3" => DATA <= x"17";
when x"EB4" => DATA <= x"20";
when x"EB5" => DATA <= x"C5";
when x"EB6" => DATA <= x"FE";
when x"EB7" => DATA <= x"BD";
when x"EB8" => DATA <= x"E3";
when x"EB9" => DATA <= x"FE";
when x"EBA" => DATA <= x"85";
when x"EBB" => DATA <= x"E2";
when x"EBC" => DATA <= x"A9";
when x"EBD" => DATA <= x"FD";
when x"EBE" => DATA <= x"85";
when x"EBF" => DATA <= x"E3";
when x"EC0" => DATA <= x"98";
when x"EC1" => DATA <= x"6C";
when x"EC2" => DATA <= x"E2";
when x"EC3" => DATA <= x"00";
when x"EC4" => DATA <= x"CA";
when x"EC5" => DATA <= x"DD";
when x"EC6" => DATA <= x"CB";
when x"EC7" => DATA <= x"FE";
when x"EC8" => DATA <= x"90";
when x"EC9" => DATA <= x"FA";
when x"ECA" => DATA <= x"60";
when x"ECB" => DATA <= x"00";
when x"ECC" => DATA <= x"08";
when x"ECD" => DATA <= x"09";
when x"ECE" => DATA <= x"0A";
when x"ECF" => DATA <= x"0B";
when x"ED0" => DATA <= x"0C";
when x"ED1" => DATA <= x"0D";
when x"ED2" => DATA <= x"0E";
when x"ED3" => DATA <= x"0F";
when x"ED4" => DATA <= x"1E";
when x"ED5" => DATA <= x"7F";
when x"ED6" => DATA <= x"00";
when x"ED7" => DATA <= x"01";
when x"ED8" => DATA <= x"05";
when x"ED9" => DATA <= x"06";
when x"EDA" => DATA <= x"08";
when x"EDB" => DATA <= x"0E";
when x"EDC" => DATA <= x"0F";
when x"EDD" => DATA <= x"10";
when x"EDE" => DATA <= x"11";
when x"EDF" => DATA <= x"1C";
when x"EE0" => DATA <= x"20";
when x"EE1" => DATA <= x"21";
when x"EE2" => DATA <= x"3B";
when x"EE3" => DATA <= x"44";
when x"EE4" => DATA <= x"5C";
when x"EE5" => DATA <= x"38";
when x"EE6" => DATA <= x"62";
when x"EE7" => DATA <= x"87";
when x"EE8" => DATA <= x"69";
when x"EE9" => DATA <= x"40";
when x"EEA" => DATA <= x"8D";
when x"EEB" => DATA <= x"92";
when x"EEC" => DATA <= x"7D";
when x"EED" => DATA <= x"50";
when x"EEE" => DATA <= x"DF";
when x"EEF" => DATA <= x"D2";
when x"EF0" => DATA <= x"9A";
when x"EF1" => DATA <= x"A2";
when x"EF2" => DATA <= x"E2";
when x"EF3" => DATA <= x"AE";
when x"EF4" => DATA <= x"C0";
when x"EF5" => DATA <= x"DF";
when x"EF6" => DATA <= x"D8";
when x"EF7" => DATA <= x"D6";
when x"EF8" => DATA <= x"C8";
when x"EF9" => DATA <= x"C6";
when x"EFA" => DATA <= x"C2";
when x"EFB" => DATA <= x"48";
when x"EFC" => DATA <= x"C9";
when x"EFD" => DATA <= x"02";
when x"EFE" => DATA <= x"F0";
when x"EFF" => DATA <= x"27";
when x"F00" => DATA <= x"C9";
when x"F01" => DATA <= x"03";
when x"F02" => DATA <= x"F0";
when x"F03" => DATA <= x"34";
when x"F04" => DATA <= x"C5";
when x"F05" => DATA <= x"FE";
when x"F06" => DATA <= x"F0";
when x"F07" => DATA <= x"2E";
when x"F08" => DATA <= x"AD";
when x"F09" => DATA <= x"0C";
when x"F0A" => DATA <= x"B8";
when x"F0B" => DATA <= x"29";
when x"F0C" => DATA <= x"0E";
when x"F0D" => DATA <= x"F0";
when x"F0E" => DATA <= x"27";
when x"F0F" => DATA <= x"68";
when x"F10" => DATA <= x"2C";
when x"F11" => DATA <= x"01";
when x"F12" => DATA <= x"B8";
when x"F13" => DATA <= x"30";
when x"F14" => DATA <= x"FB";
when x"F15" => DATA <= x"8D";
when x"F16" => DATA <= x"01";
when x"F17" => DATA <= x"B8";
when x"F18" => DATA <= x"48";
when x"F19" => DATA <= x"AD";
when x"F1A" => DATA <= x"0C";
when x"F1B" => DATA <= x"B8";
when x"F1C" => DATA <= x"29";
when x"F1D" => DATA <= x"F0";
when x"F1E" => DATA <= x"09";
when x"F1F" => DATA <= x"0C";
when x"F20" => DATA <= x"8D";
when x"F21" => DATA <= x"0C";
when x"F22" => DATA <= x"B8";
when x"F23" => DATA <= x"09";
when x"F24" => DATA <= x"02";
when x"F25" => DATA <= x"D0";
when x"F26" => DATA <= x"0C";
when x"F27" => DATA <= x"A9";
when x"F28" => DATA <= x"7F";
when x"F29" => DATA <= x"8D";
when x"F2A" => DATA <= x"03";
when x"F2B" => DATA <= x"B8";
when x"F2C" => DATA <= x"AD";
when x"F2D" => DATA <= x"0C";
when x"F2E" => DATA <= x"B8";
when x"F2F" => DATA <= x"29";
when x"F30" => DATA <= x"F0";
when x"F31" => DATA <= x"09";
when x"F32" => DATA <= x"0E";
when x"F33" => DATA <= x"8D";
when x"F34" => DATA <= x"0C";
when x"F35" => DATA <= x"B8";
when x"F36" => DATA <= x"68";
when x"F37" => DATA <= x"60";
when x"F38" => DATA <= x"AD";
when x"F39" => DATA <= x"0C";
when x"F3A" => DATA <= x"B8";
when x"F3B" => DATA <= x"29";
when x"F3C" => DATA <= x"F0";
when x"F3D" => DATA <= x"B0";
when x"F3E" => DATA <= x"F4";
when x"F3F" => DATA <= x"A2";
when x"F40" => DATA <= x"17";
when x"F41" => DATA <= x"BD";
when x"F42" => DATA <= x"9A";
when x"F43" => DATA <= x"FF";
when x"F44" => DATA <= x"9D";
when x"F45" => DATA <= x"04";
when x"F46" => DATA <= x"02";
when x"F47" => DATA <= x"CA";
when x"F48" => DATA <= x"10";
when x"F49" => DATA <= x"F7";
when x"F4A" => DATA <= x"9A";
when x"F4B" => DATA <= x"8A";
when x"F4C" => DATA <= x"E8";
when x"F4D" => DATA <= x"86";
when x"F4E" => DATA <= x"EA";
when x"F4F" => DATA <= x"86";
when x"F50" => DATA <= x"E1";
when x"F51" => DATA <= x"86";
when x"F52" => DATA <= x"E7";
when x"F53" => DATA <= x"A2";
when x"F54" => DATA <= x"33";
when x"F55" => DATA <= x"9D";
when x"F56" => DATA <= x"EB";
when x"F57" => DATA <= x"02";
when x"F58" => DATA <= x"CA";
when x"F59" => DATA <= x"10";
when x"F5A" => DATA <= x"FA";
when x"F5B" => DATA <= x"A9";
when x"F5C" => DATA <= x"0A";
when x"F5D" => DATA <= x"85";
when x"F5E" => DATA <= x"FE";
when x"F5F" => DATA <= x"A9";
when x"F60" => DATA <= x"8A";
when x"F61" => DATA <= x"8D";
when x"F62" => DATA <= x"03";
when x"F63" => DATA <= x"B0";
when x"F64" => DATA <= x"A9";
when x"F65" => DATA <= x"07";
when x"F66" => DATA <= x"8D";
when x"F67" => DATA <= x"02";
when x"F68" => DATA <= x"B0";
when x"F69" => DATA <= x"20";
when x"F6A" => DATA <= x"D1";
when x"F6B" => DATA <= x"F7";
when x"F6C" => DATA <= x"06";
when x"F6D" => DATA <= x"0C";
when x"F6E" => DATA <= x"0F";
when x"F6F" => DATA <= x"41";
when x"F70" => DATA <= x"43";
when x"F71" => DATA <= x"4F";
when x"F72" => DATA <= x"52";
when x"F73" => DATA <= x"4E";
when x"F74" => DATA <= x"20";
when x"F75" => DATA <= x"41";
when x"F76" => DATA <= x"54";
when x"F77" => DATA <= x"4F";
when x"F78" => DATA <= x"4D";
when x"F79" => DATA <= x"0A";
when x"F7A" => DATA <= x"0A";
when x"F7B" => DATA <= x"0D";
when x"F7C" => DATA <= x"A9";
when x"F7D" => DATA <= x"82";
when x"F7E" => DATA <= x"85";
when x"F7F" => DATA <= x"12";
when x"F80" => DATA <= x"58";
when x"F81" => DATA <= x"A9";
when x"F82" => DATA <= x"55";
when x"F83" => DATA <= x"8D";
when x"F84" => DATA <= x"01";
when x"F85" => DATA <= x"29";
when x"F86" => DATA <= x"CD";
when x"F87" => DATA <= x"01";
when x"F88" => DATA <= x"29";
when x"F89" => DATA <= x"D0";
when x"F8A" => DATA <= x"0C";
when x"F8B" => DATA <= x"0A";
when x"F8C" => DATA <= x"8D";
when x"F8D" => DATA <= x"01";
when x"F8E" => DATA <= x"29";
when x"F8F" => DATA <= x"CD";
when x"F90" => DATA <= x"01";
when x"F91" => DATA <= x"29";
when x"F92" => DATA <= x"D0";
when x"F93" => DATA <= x"03";
when x"F94" => DATA <= x"4C";
when x"F95" => DATA <= x"B2";
when x"F96" => DATA <= x"C2";
when x"F97" => DATA <= x"4C";
when x"F98" => DATA <= x"B6";
when x"F99" => DATA <= x"C2";
when x"F9A" => DATA <= x"00";
when x"F9B" => DATA <= x"A0";
when x"F9C" => DATA <= x"EF";
when x"F9D" => DATA <= x"F8";
when x"F9E" => DATA <= x"52";
when x"F9F" => DATA <= x"FE";
when x"FA0" => DATA <= x"94";
when x"FA1" => DATA <= x"FE";
when x"FA2" => DATA <= x"6E";
when x"FA3" => DATA <= x"F9";
when x"FA4" => DATA <= x"E5";
when x"FA5" => DATA <= x"FA";
when x"FA6" => DATA <= x"AC";
when x"FA7" => DATA <= x"C2";
when x"FA8" => DATA <= x"AC";
when x"FA9" => DATA <= x"C2";
when x"FAA" => DATA <= x"EE";
when x"FAB" => DATA <= x"FB";
when x"FAC" => DATA <= x"7C";
when x"FAD" => DATA <= x"FC";
when x"FAE" => DATA <= x"38";
when x"FAF" => DATA <= x"FC";
when x"FB0" => DATA <= x"78";
when x"FB1" => DATA <= x"C2";
when x"FB2" => DATA <= x"85";
when x"FB3" => DATA <= x"FF";
when x"FB4" => DATA <= x"68";
when x"FB5" => DATA <= x"48";
when x"FB6" => DATA <= x"29";
when x"FB7" => DATA <= x"10";
when x"FB8" => DATA <= x"D0";
when x"FB9" => DATA <= x"06";
when x"FBA" => DATA <= x"A5";
when x"FBB" => DATA <= x"FF";
when x"FBC" => DATA <= x"48";
when x"FBD" => DATA <= x"6C";
when x"FBE" => DATA <= x"04";
when x"FBF" => DATA <= x"02";
when x"FC0" => DATA <= x"A5";
when x"FC1" => DATA <= x"FF";
when x"FC2" => DATA <= x"28";
when x"FC3" => DATA <= x"08";
when x"FC4" => DATA <= x"6C";
when x"FC5" => DATA <= x"02";
when x"FC6" => DATA <= x"02";
when x"FC7" => DATA <= x"48";
when x"FC8" => DATA <= x"6C";
when x"FC9" => DATA <= x"00";
when x"FCA" => DATA <= x"02";
when x"FCB" => DATA <= x"6C";
when x"FCC" => DATA <= x"1A";
when x"FCD" => DATA <= x"02";
when x"FCE" => DATA <= x"6C";
when x"FCF" => DATA <= x"18";
when x"FD0" => DATA <= x"02";
when x"FD1" => DATA <= x"6C";
when x"FD2" => DATA <= x"16";
when x"FD3" => DATA <= x"02";
when x"FD4" => DATA <= x"6C";
when x"FD5" => DATA <= x"14";
when x"FD6" => DATA <= x"02";
when x"FD7" => DATA <= x"6C";
when x"FD8" => DATA <= x"12";
when x"FD9" => DATA <= x"02";
when x"FDA" => DATA <= x"6C";
when x"FDB" => DATA <= x"10";
when x"FDC" => DATA <= x"02";
when x"FDD" => DATA <= x"6C";
when x"FDE" => DATA <= x"0E";
when x"FDF" => DATA <= x"02";
when x"FE0" => DATA <= x"6C";
when x"FE1" => DATA <= x"0C";
when x"FE2" => DATA <= x"02";
when x"FE3" => DATA <= x"6C";
when x"FE4" => DATA <= x"0A";
when x"FE5" => DATA <= x"02";
when x"FE6" => DATA <= x"20";
when x"FE7" => DATA <= x"E3";
when x"FE8" => DATA <= x"FF";
when x"FE9" => DATA <= x"C9";
when x"FEA" => DATA <= x"0D";
when x"FEB" => DATA <= x"D0";
when x"FEC" => DATA <= x"07";
when x"FED" => DATA <= x"A9";
when x"FEE" => DATA <= x"0A";
when x"FEF" => DATA <= x"20";
when x"FF0" => DATA <= x"F4";
when x"FF1" => DATA <= x"FF";
when x"FF2" => DATA <= x"A9";
when x"FF3" => DATA <= x"0D";
when x"FF4" => DATA <= x"6C";
when x"FF5" => DATA <= x"08";
when x"FF6" => DATA <= x"02";
when x"FF7" => DATA <= x"6C";
when x"FF8" => DATA <= x"06";
when x"FF9" => DATA <= x"02";
when x"FFA" => DATA <= x"C7";
when x"FFB" => DATA <= x"FF";
when x"FFC" => DATA <= x"3F";
when x"FFD" => DATA <= x"FF";
when x"FFE" => DATA <= x"B2";
when x"FFF" => DATA <= x"FF";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_LSFTPIPE64X64.VHD ***
--*** ***
--*** Function: Pipelined Left Shift ***
--*** (max 1.52 to 64.0) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_lsftpipe64x64;
ARCHITECTURE rtl of dp_lsftpipe64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 116 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 116 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 49 TO 116 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k-48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_LSFTPIPE64X64.VHD ***
--*** ***
--*** Function: Pipelined Left Shift ***
--*** (max 1.52 to 64.0) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_lsftpipe64x64;
ARCHITECTURE rtl of dp_lsftpipe64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 116 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 116 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 49 TO 116 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k-48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_LSFTPIPE64X64.VHD ***
--*** ***
--*** Function: Pipelined Left Shift ***
--*** (max 1.52 to 64.0) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_lsftpipe64x64;
ARCHITECTURE rtl of dp_lsftpipe64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 116 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 116 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 49 TO 116 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k-48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_LSFTPIPE64X64.VHD ***
--*** ***
--*** Function: Pipelined Left Shift ***
--*** (max 1.52 to 64.0) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_lsftpipe64x64;
ARCHITECTURE rtl of dp_lsftpipe64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 116 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 116 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 49 TO 116 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k-48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_LSFTPIPE64X64.VHD ***
--*** ***
--*** Function: Pipelined Left Shift ***
--*** (max 1.52 to 64.0) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_lsftpipe64x64;
ARCHITECTURE rtl of dp_lsftpipe64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 116 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 116 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 49 TO 116 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k-48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_LSFTPIPE64X64.VHD ***
--*** ***
--*** Function: Pipelined Left Shift ***
--*** (max 1.52 to 64.0) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_lsftpipe64x64;
ARCHITECTURE rtl of dp_lsftpipe64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 116 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 116 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 49 TO 116 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k-48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_LSFTPIPE64X64.VHD ***
--*** ***
--*** Function: Pipelined Left Shift ***
--*** (max 1.52 to 64.0) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_lsftpipe64x64;
ARCHITECTURE rtl of dp_lsftpipe64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 116 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 116 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 49 TO 116 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k-48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_LSFTPIPE64X64.VHD ***
--*** ***
--*** Function: Pipelined Left Shift ***
--*** (max 1.52 to 64.0) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_lsftpipe64x64;
ARCHITECTURE rtl of dp_lsftpipe64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 116 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 116 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 49 TO 116 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k-48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_LSFTPIPE64X64.VHD ***
--*** ***
--*** Function: Pipelined Left Shift ***
--*** (max 1.52 to 64.0) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_lsftpipe64x64;
ARCHITECTURE rtl of dp_lsftpipe64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 116 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 116 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 49 TO 116 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k-48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_LSFTPIPE64X64.VHD ***
--*** ***
--*** Function: Pipelined Left Shift ***
--*** (max 1.52 to 64.0) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_lsftpipe64x64;
ARCHITECTURE rtl of dp_lsftpipe64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 116 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 116 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 49 TO 116 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k-48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k-32) AND shiftff(6) AND NOT(shiftff(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k-16) AND NOT(shiftff(6)) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
-- FIFO implemented as a circular buffer
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity circbuf_fast is
generic (
DATAW : natural := 32;
DEPTH : natural := 8;
CNTW : natural := 16
);
port (
reset : in std_logic;
clk : in std_logic;
fifo_in_data : in std_logic_vector(DATAW-1 downto 0);
fifo_in_rdy : out std_logic;
fifo_in_ack : in std_logic;
fifo_in_cnt : out std_logic_vector(CNTW-1 downto 0);
fifo_out_data : out std_logic_vector(DATAW-1 downto 0);
fifo_out_rdy : out std_logic;
fifo_out_ack : in std_logic;
fifo_out_cnt : out std_logic_vector(CNTW-1 downto 0)
);
end circbuf_fast;
architecture synth of circbuf_fast is
-- Compute the minimum number of bits needed to store the input value
function storebitsnb(vin : natural) return natural is
variable r : natural := 1;
variable v : natural := vin;
begin
loop
exit when v <= 1;
r := r + 1;
v := v / 2;
end loop;
return r;
end function;
-- Compute the minimum number of bits needed to store the input value
function ispower2(vin : natural) return boolean is
begin
if storebitsnb(vin-1) /= storebitsnb(vin) then return true; end if;
return false;
end function;
-- The needed index width
constant IDXW : natural := storebitsnb(DEPTH-1);
-- Detect when the number of cells is power of 2, this enables to skip some tests
constant DEPTHISPOW2 : boolean := ispower2(DEPTH);
-- The embedded memory
type mem_type is array (0 to DEPTH-1) of std_logic_vector(DATAW-1 downto 0);
signal mem : mem_type := (others => (others => '0'));
attribute ram_style : String;
attribute ram_style of mem : signal is "distributed";
-- Internal registers
signal idx_in, idx_in_n : unsigned(IDXW-1 downto 0) := to_unsigned(0, IDXW);
signal idx_out, idx_out_n : unsigned(IDXW-1 downto 0) := to_unsigned(0, IDXW);
signal reg_cnt_in, reg_cnt_in_n : unsigned(CNTW-1 downto 0) := to_unsigned(0, CNTW);
signal reg_cnt_out, reg_cnt_out_n : unsigned(CNTW-1 downto 0) := to_unsigned(0, CNTW);
signal reg_in2out, reg_in2out_n : std_logic;
signal reg_out2in, reg_out2in_n : std_logic;
signal regout_data : std_logic_vector(DATAW-1 downto 0) := (others => '0');
signal regin_rdy, regin_rdy_n : std_logic := '1';
signal regout_rdy, regout_rdy_n : std_logic := '0';
-- Signals for mem write enable and read enable
signal sigmem_ren : std_logic := '0';
signal sigmem_wen : std_logic := '0';
-- Signals to enable update the in and out indexes
signal idx_in_we : std_logic := '0';
signal idx_out_we : std_logic := '0';
begin
---------------------------------------------
----------- Sequential processes ------------
---------------------------------------------
process (clk)
begin
if rising_edge(clk) then
if idx_in_we = '1' then
idx_in <= idx_in_n;
end if;
if idx_out_we = '1' then
idx_out <= idx_out_n;
end if;
reg_cnt_in <= reg_cnt_in_n;
reg_cnt_out <= reg_cnt_out_n;
reg_in2out <= reg_in2out_n;
reg_out2in <= reg_out2in_n;
regin_rdy <= regin_rdy_n;
regout_rdy <= regout_rdy_n;
-- Write the input value to the memory
if sigmem_wen = '1' then
mem(to_integer(idx_in)) <= fifo_in_data;
end if;
-- Read the output value from the memory
if sigmem_ren = '1' then
regout_data <= mem(to_integer(idx_out));
end if;
end if;
end process;
---------------------------------------------
--------- Combinatorial processes -----------
---------------------------------------------
process (
reset,
reg_cnt_in, reg_cnt_out,
reg_in2out, reg_out2in,
idx_in, idx_out,
regin_rdy, regout_rdy,
fifo_in_ack, fifo_out_ack
)
variable var_doin : std_logic := '0';
variable var_doout : std_logic := '0';
variable var_cnt_inc : unsigned(CNTW-1 downto 0) := to_unsigned(0, CNTW);
begin
-- Default values for the variables
var_doin := '0';
var_doout := '0';
-- Default next values for internal registers
idx_in_we <= '0';
idx_out_we <= '0';
idx_in_n <= idx_in;
idx_out_n <= idx_out;
reg_cnt_in_n <= reg_cnt_in;
reg_cnt_out_n <= reg_cnt_out;
reg_in2out_n <= '0';
reg_out2in_n <= '0';
regin_rdy_n <= regin_rdy;
regout_rdy_n <= regout_rdy;
-- Default values for internal signals
sigmem_wen <= '0';
sigmem_ren <= '0';
-- Handle FIFO input
if (regin_rdy = '1') and (fifo_in_ack = '1') then
sigmem_wen <= '1';
var_doin := '1';
idx_in_we <= '1';
reg_in2out_n <= '1';
end if;
-- Handle FIFO output
if (regout_rdy = '1') and (fifo_out_ack = '1') then
sigmem_ren <= '1';
var_doout := '1';
idx_out_we <= '1';
reg_out2in_n <= '1';
-- Don't increment index when reading the last value
if reg_cnt_out = 1 then
sigmem_ren <= '0';
idx_out_we <= '0';
end if;
end if;
-- Increment the output counter by +1 if doing only input, or -1 if doing only output
var_cnt_inc(CNTW-1 downto 1) := (others => var_doout and not reg_in2out);
var_cnt_inc(0) := var_doout xor reg_in2out;
-- Next value for the counter
reg_cnt_out_n <= reg_cnt_out + var_cnt_inc;
-- Increment the input counter by +1 if doing only output, or -1 if doing only input
var_cnt_inc(CNTW-1 downto 1) := (others => var_doin and not reg_out2in);
var_cnt_inc(0) := var_doin xor reg_out2in;
-- Next value for the counter
reg_cnt_in_n <= reg_cnt_in + var_cnt_inc;
-- Next value for the in_rdy register
if reg_cnt_in = 1 then
regin_rdy_n <= (not var_doin) or reg_out2in;
end if;
-- Next value for the out_rdy register
if reg_cnt_out = 1 then
regout_rdy_n <= not var_doout;
end if;
-- Perform one mem read to initialize the output register
if (reg_cnt_out = 1) and (regout_rdy = '0') then
sigmem_ren <= '1';
regout_rdy_n <= '1';
idx_out_we <= '1';
end if;
-- Systematically compute the next value of the in index
idx_in_n <= idx_in + 1;
if (DEPTHISPOW2 = false) and (idx_in = DEPTH-1) then
idx_in_n <= to_unsigned(0, IDXW);
end if;
-- Systematically compute the next value of the out index
idx_out_n <= idx_out + 1;
if (DEPTHISPOW2 = false) and (idx_out = DEPTH-1) then
idx_out_n <= to_unsigned(0, IDXW);
end if;
-- Handle reset
-- Note: The memory content is not affected by reset
if reset = '1' then
idx_in_n <= to_unsigned(0, IDXW);
idx_out_n <= to_unsigned(0, IDXW);
reg_cnt_in_n <= to_unsigned(DEPTH, CNTW);
reg_cnt_out_n <= to_unsigned(0, CNTW);
regin_rdy_n <= '1';
regout_rdy_n <= '0';
idx_in_we <= '1';
idx_out_we <= '1';
end if;
end process;
---------------------------------------------
----------- Ports assignements --------------
---------------------------------------------
fifo_in_rdy <= regin_rdy;
fifo_out_rdy <= regout_rdy;
fifo_out_data <= regout_data;
fifo_in_cnt <= std_logic_vector(reg_cnt_in);
fifo_out_cnt <= std_logic_vector(reg_cnt_out);
end architecture;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "double_buffering"
-------------------------------------------------------------------------------
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.reg_file_pkg.all;
-------------------------------------------------------------------------------
entity double_buffering_tb is
end entity double_buffering_tb;
-------------------------------------------------------------------------------
architecture tb of double_buffering_tb is
-- component ports
signal ready_p : std_logic := '0';
signal enable_p : std_logic := '0';
signal irq_p : std_logic := '0';
signal ack_p : std_logic := '0';
signal bank_p : std_logic := '0';
-- clock
signal clk : std_logic := '1';
begin -- architecture tb
-- component instantiation
DUT : double_buffering
port map (
ready_p => ready_p,
enable_p => enable_p,
irq_p => irq_p,
ack_p => ack_p,
bank_p => bank_p,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
wait until clk = '0';
-------------------------------------------------------------------------
-- Scenario 1: normal operation, STM acknowledges in time
-------------------------------------------------------------------------
-- app has finished:
ready_p <= '1';
wait until clk = '0';
ready_p <= '0';
-- wait until STM reacts
for ii in 0 to 5 loop
wait until clk = '0';
end loop; -- ii
-- STM acknowledges, asynchronously
wait for 3.39 ns;
ack_p <= '1';
wait for 38.3 ns;
ack_p <= '0';
-- separate test cases
for ii in 0 to 5 loop
wait until clk = '0';
end loop; -- ii
-------------------------------------------------------------------------
-- Scenario 2: ACK is still high when ready goes high again
-------------------------------------------------------------------------
-- Expected behaviour: keep IRQ high. Only rising edges of ready_p reset
-- the IRQ signal.
ack_p <= '1';
for ii in 0 to 5 loop
wait until clk = '0';
end loop; -- ii
-- app has finished:
ready_p <= '1';
wait until clk = '0';
ready_p <= '0';
-- wait until STM reacts
for ii in 0 to 5 loop
wait until clk = '0';
end loop; -- ii
ack_p <= '0';
wait until clk = '0';
ack_p <= '1';
for ii in 0 to 5 loop
wait until clk = '0';
end loop; -- ii
ack_p <= '0';
-- separate test cases
for ii in 0 to 5 loop
wait until clk = '0';
end loop; -- ii
-------------------------------------------------------------------------
-- Scenario 3: STM does not read data fast enough
-------------------------------------------------------------------------
-- Expected behaviour: IRQ is kept high, no bank change.
-- app has finished:
ready_p <= '1';
wait until clk = '0';
ready_p <= '0';
-- new data comes in 10 clock cycles
for ii in 0 to 10 loop
wait until clk = '0';
end loop; -- ii
ready_p <= '1';
wait until clk = '0';
ready_p <= '0';
-- separate test cases
for ii in 0 to 5 loop
wait until clk = '0';
end loop; -- ii
ack_p <= '1';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
ack_p <= '0';
-- separate test cases
for ii in 0 to 5 loop
wait until clk = '0';
end loop; -- ii
-------------------------------------------------------------------------
-- Scenario 4: Ready_p high very long
-------------------------------------------------------------------------
ready_p <= '0';
wait until clk = '0';
ready_p <= '1';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
ready_p <= '0';
-- do not repeat
wait for 10 ms;
end process WaveGen_Proc;
end architecture tb;
-------------------------------------------------------------------------------
configuration double_buffering_tb_tb_cfg of double_buffering_tb is
for tb
end for;
end double_buffering_tb_tb_cfg;
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "double_buffering"
-------------------------------------------------------------------------------
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.reg_file_pkg.all;
-------------------------------------------------------------------------------
entity double_buffering_tb is
end entity double_buffering_tb;
-------------------------------------------------------------------------------
architecture tb of double_buffering_tb is
-- component ports
signal ready_p : std_logic := '0';
signal enable_p : std_logic := '0';
signal irq_p : std_logic := '0';
signal ack_p : std_logic := '0';
signal bank_p : std_logic := '0';
-- clock
signal clk : std_logic := '1';
begin -- architecture tb
-- component instantiation
DUT : double_buffering
port map (
ready_p => ready_p,
enable_p => enable_p,
irq_p => irq_p,
ack_p => ack_p,
bank_p => bank_p,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
wait until clk = '0';
-------------------------------------------------------------------------
-- Scenario 1: normal operation, STM acknowledges in time
-------------------------------------------------------------------------
-- app has finished:
ready_p <= '1';
wait until clk = '0';
ready_p <= '0';
-- wait until STM reacts
for ii in 0 to 5 loop
wait until clk = '0';
end loop; -- ii
-- STM acknowledges, asynchronously
wait for 3.39 ns;
ack_p <= '1';
wait for 38.3 ns;
ack_p <= '0';
-- separate test cases
for ii in 0 to 5 loop
wait until clk = '0';
end loop; -- ii
-------------------------------------------------------------------------
-- Scenario 2: ACK is still high when ready goes high again
-------------------------------------------------------------------------
-- Expected behaviour: keep IRQ high. Only rising edges of ready_p reset
-- the IRQ signal.
ack_p <= '1';
for ii in 0 to 5 loop
wait until clk = '0';
end loop; -- ii
-- app has finished:
ready_p <= '1';
wait until clk = '0';
ready_p <= '0';
-- wait until STM reacts
for ii in 0 to 5 loop
wait until clk = '0';
end loop; -- ii
ack_p <= '0';
wait until clk = '0';
ack_p <= '1';
for ii in 0 to 5 loop
wait until clk = '0';
end loop; -- ii
ack_p <= '0';
-- separate test cases
for ii in 0 to 5 loop
wait until clk = '0';
end loop; -- ii
-------------------------------------------------------------------------
-- Scenario 3: STM does not read data fast enough
-------------------------------------------------------------------------
-- Expected behaviour: IRQ is kept high, no bank change.
-- app has finished:
ready_p <= '1';
wait until clk = '0';
ready_p <= '0';
-- new data comes in 10 clock cycles
for ii in 0 to 10 loop
wait until clk = '0';
end loop; -- ii
ready_p <= '1';
wait until clk = '0';
ready_p <= '0';
-- separate test cases
for ii in 0 to 5 loop
wait until clk = '0';
end loop; -- ii
ack_p <= '1';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
ack_p <= '0';
-- separate test cases
for ii in 0 to 5 loop
wait until clk = '0';
end loop; -- ii
-------------------------------------------------------------------------
-- Scenario 4: Ready_p high very long
-------------------------------------------------------------------------
ready_p <= '0';
wait until clk = '0';
ready_p <= '1';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
wait until clk = '0';
ready_p <= '0';
-- do not repeat
wait for 10 ms;
end process WaveGen_Proc;
end architecture tb;
-------------------------------------------------------------------------------
configuration double_buffering_tb_tb_cfg of double_buffering_tb is
for tb
end for;
end double_buffering_tb_tb_cfg;
-------------------------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity anode_selector is
port(
selector_in : in std_logic_vector (1 downto 0);
selector_out : out std_logic_vector (3 downto 0)
);
end anode_selector;
architecture anode_selector_arq of anode_selector is
begin
process (selector_in) is
begin
case selector_in is
when "00" => selector_out <= not b"0001";
when "01" => selector_out <= not b"0010";
when "10" => selector_out <= not b"0100";
when "11" => selector_out <= not b"1000";
when others => selector_out <= (others => '0');
end case;
end process;
end anode_selector_arq;
|
-------------------------------------------------------------------------------
-- axi_datamover_dre_mux8_1_x_n.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_dre_mux8_1_x_n.vhd
--
-- Description:
--
-- This VHDL file provides a 8 to 1 xn bit wide mux for the AXI Data Realignment
-- Engine (DRE).
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_datamover_dre_mux8_1_x_n.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
--
-- History:
-- DET 04/19/2011 Initial Version for EDK 13.3
--
--
---------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Start 8 to 1 xN Mux
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
Entity axi_datamover_dre_mux8_1_x_n is
generic (
C_WIDTH : Integer := 8
-- Sets the bit width of the 8x Mux slice
);
port (
Sel : In std_logic_vector(2 downto 0);
-- Mux select control
I0 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 0 input
I1 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 1 input
I2 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 2 input
I3 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 3 input
I4 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 4 input
I5 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 5 input
I6 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 6 input
I7 : In std_logic_vector(C_WIDTH-1 downto 0);
-- Select 7 input
Y : Out std_logic_vector(C_WIDTH-1 downto 0)
-- Mux output value
);
end entity axi_datamover_dre_mux8_1_x_n; --
Architecture implementation of axi_datamover_dre_mux8_1_x_n is
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: SELECT8_1
--
-- Process Description:
-- This process implements an 8 to 1 mux.
--
-------------------------------------------------------------
SELECT8_1 : process (Sel, I0, I1, I2, I3,
I4, I5, I6, I7)
begin
case Sel is
when "000" =>
Y <= I0;
when "001" =>
Y <= I1;
when "010" =>
Y <= I2;
when "011" =>
Y <= I3;
when "100" =>
Y <= I4;
when "101" =>
Y <= I5;
when "110" =>
Y <= I6;
when "111" =>
Y <= I7;
when others =>
Y <= I0;
end case;
end process SELECT8_1;
end implementation; -- axi_datamover_dre_mux8_1_x_n
-------------------------------------------------------------------------------
-- End 8 to 1 xN Mux
-------------------------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bus_interface is
generic(
BASE_ADDRESS: unsigned(23 downto 0) := x"000000"
);
port(
--bus
clk: in std_logic;
res: in std_logic;
address: in std_logic_vector(23 downto 0);
data_mosi: in std_logic_vector(31 downto 0);
data_miso: out std_logic_vector(31 downto 0);
WR: in std_logic;
RD: in std_logic;
ack: out std_logic;
--fifos
wrfifo_datain: out std_logic_vector(54 downto 0);
wrfifo_write: out std_logic;
wrfifo_wrempty: in std_logic;
rdfifo_address_datain: out std_logic_vector(22 downto 0);
rdfifo_address_we: out std_logic;
rdfifo_address_wrempty: in std_logic;
rdfifo_data_rdreq: out std_logic;
rdfifo_data_dataout: in std_logic_vector(31 downto 0);
rdfifo_data_rdempty: in std_logic
);
end entity bus_interface;
architecture bus_interface_arch of bus_interface is
signal miso_en, cs: std_logic;
type fsm_state_type is (idle, rd_state, wr_state, wait_for_data,read_data, ack_state);
signal fsm_state: fsm_state_type;
begin
wrfifo_datain <= address(22 downto 0) & data_mosi;
rdfifo_address_datain <= address(22 downto 0);
data_miso <= rdfifo_data_dataout when miso_en = '1' else (others => 'Z');
process(address) is begin
if (unsigned(address) >= BASE_ADDRESS and unsigned(address) <= (BASE_ADDRESS + (2**23)-1)) then
cs <= '1';
else
cs <= '0';
end if;
end process;
process(clk) is
begin
if rising_edge(clk) then
if res = '1' then
fsm_state <= idle;
else
case fsm_state is
when idle =>
if (RD = '1') and (cs = '1') and (rdfifo_address_wrempty = '1') then
fsm_state <= rd_state;
elsif (WR = '1') and (cs = '1') and (wrfifo_wrempty = '1') then
fsm_state <= wr_state;
else
fsm_state <= idle;
end if;
when rd_state =>
fsm_state <= wait_for_data;
when wr_state =>
fsm_state <= ack_state;
when wait_for_data =>
if rdfifo_data_rdempty = '0' then
fsm_state <= read_data;
else
fsm_state <= wait_for_data;
end if;
when read_data =>
fsm_state <= ack_state;
when ack_state =>
fsm_state <= idle;
end case;
end if;
end if;
end process;
process(fsm_state) is
begin
case fsm_state is
when idle =>
rdfifo_data_rdreq <= '0'; rdfifo_address_we <= '0'; wrfifo_write <= '0'; ack <= '0';
when rd_state =>
rdfifo_data_rdreq <= '0'; rdfifo_address_we <= '1'; wrfifo_write <= '0'; ack <= '0';
when wr_state =>
rdfifo_data_rdreq <= '0'; rdfifo_address_we <= '0'; wrfifo_write <= '1'; ack <= '0';
when wait_for_data =>
rdfifo_data_rdreq <= '0'; rdfifo_address_we <= '0'; wrfifo_write <= '0'; ack <= '0';
when read_data =>
rdfifo_data_rdreq <= '1'; rdfifo_address_we <= '0'; wrfifo_write <= '0'; ack <= '0';
when ack_state =>
rdfifo_data_rdreq <= '0'; rdfifo_address_we <= '0'; wrfifo_write <= '0'; ack <= '1';
end case;
end process;
miso_en <= '1' when (cs = '1') and (RD = '1') else '0';
end architecture bus_interface_arch;
|
-------------------------------------------------------------------------------
--
-- File: InputSERDES.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates the Xilinx 7-series primitives necessary for
-- de-serializing the TMDS data stream.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity InputSERDES is
Generic (
kIDLY_TapWidth : natural := 5; -- number of bits for IDELAYE2 tap counter
kParallelWidth : natural := 10); -- number of parallel bits
Port (
PixelClk : in std_logic; --Recovered TMDS clock x1 (CLKDIV)
SerialClk : in std_logic; --Recovered TMDS clock x5 (CLK)
--Encoded serial data
sDataIn_p : in std_logic; --TMDS data channel positive
sDataIn_n : in std_logic; --TMDS data channel negative
--Encoded parallel data (raw)
pDataIn : out STD_LOGIC_VECTOR (kParallelWidth-1 downto 0);
--Control for phase alignment
pBitslip : in STD_LOGIC; --Bitslip for ISERDESE2
pIDLY_LD : in STD_LOGIC; --IDELAYE2 Load
pIDLY_CE : in STD_LOGIC; --IDELAYE2 CE
pIDLY_INC : in STD_LOGIC; --IDELAYE2 Tap Increment
pIDLY_CNT : out std_logic_vector(kIDLY_TapWidth-1 downto 0); --IDELAYE2 Current Tap Count
aRst : in STD_LOGIC
);
end InputSERDES;
architecture Behavioral of InputSERDES is
signal sDataIn, sDataInDly, icascade1, icascade2, SerialClkInv : std_logic;
signal pDataIn_q : std_logic_vector(13 downto 0); --ISERDESE2 can do 1:14 at most
begin
-- Differential input buffer for TMDS I/O standard
InputBuffer: IBUFDS
generic map (
DIFF_TERM => FALSE,
IOSTANDARD => "TMDS_33")
port map (
I => sDataIn_p,
IB => sDataIn_n,
O => sDataIn);
-- Delay element for phase alignment of serial data
InputDelay: IDELAYE2
generic map (
CINVCTRL_SEL => "FALSE", -- TRUE, FALSE
DELAY_SRC => "IDATAIN", -- IDATAIN, DATAIN
HIGH_PERFORMANCE_MODE => "TRUE", -- TRUE, FALSE
IDELAY_TYPE => "VARIABLE", -- FIXED, VARIABLE, or VAR_LOADABLE
IDELAY_VALUE => 0, -- 0 to 31
REFCLK_FREQUENCY => 200.0,
PIPE_SEL => "FALSE",
SIGNAL_PATTERN => "DATA") -- CLOCK, DATA
port map (
DATAOUT => sDataInDly, -- Delayed signal
DATAIN => '0', -- Not used; IDATAIN instead
C => PixelClk, -- Clock for control signals (CE,INC...)
CE => pIDLY_CE,
INC => pIDLY_INC,
IDATAIN => sDataIn, -- Driven by IOB
LD => pIDLY_LD,
REGRST => '0', --not used in VARIABLE mode
LDPIPEEN => '0',
CNTVALUEIN => "00000", --not used in VARIABLE mode
CNTVALUEOUT => pIDLY_CNT, -- current tap value
CINVCTRL => '0');
--Invert locally for ISERDESE2
SerialClkInv <= not SerialClk;
-- De-serializer, 1:10 (1:5 DDR), master-slave cascaded
DeserializerMaster: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => kParallelWidth,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "MASTER")
port map (
Q1 => pDataIn_q(0),
Q2 => pDataIn_q(1),
Q3 => pDataIn_q(2),
Q4 => pDataIn_q(3),
Q5 => pDataIn_q(4),
Q6 => pDataIn_q(5),
Q7 => pDataIn_q(6),
Q8 => pDataIn_q(7),
SHIFTOUT1 => icascade1, -- Cascade connection to Slave ISERDES
SHIFTOUT2 => icascade2, -- Cascade connection to Slave ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => sDataInDly, -- 1-bit Input signal from IODELAYE1.
RST => aRst, -- 1-bit Asynchronous reset only.
SHIFTIN1 => '0',
SHIFTIN2 => '0',
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
DeserializerSlave: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 10,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "SLAVE")
port map (
Q1 => open, --not used in cascaded mode
Q2 => open, --not used in cascaded mode
Q3 => pDataIn_q(8),
Q4 => pDataIn_q(9),
Q5 => pDataIn_q(10),
Q6 => pDataIn_q(11),
Q7 => pDataIn_q(12),
Q8 => pDataIn_q(13),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTIN1 => icascade1, -- Cascade connections from Master ISERDES
SHIFTIN2 => icascade2,-- Cascade connections from Master ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => '0', -- not used in cascaded Slave mode
RST => aRst, -- 1-bit Asynchronous reset only.
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
-------------------------------------------------------------
-- Concatenate the serdes outputs together. Keep the timesliced
-- bits together, and placing the earliest bits on the right
-- ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
-- the output will be 3210, 7654, ...
-------------------------------------------------------------
SliceISERDES_q: for slice_count in 0 to kParallelWidth-1 generate begin
--DVI sends least significant bit first
-- This places the first data in time on the right
pDataIn(slice_count) <= pDataIn_q(kParallelWidth-slice_count-1);
end generate SliceISERDES_q;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: InputSERDES.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates the Xilinx 7-series primitives necessary for
-- de-serializing the TMDS data stream.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity InputSERDES is
Generic (
kIDLY_TapWidth : natural := 5; -- number of bits for IDELAYE2 tap counter
kParallelWidth : natural := 10); -- number of parallel bits
Port (
PixelClk : in std_logic; --Recovered TMDS clock x1 (CLKDIV)
SerialClk : in std_logic; --Recovered TMDS clock x5 (CLK)
--Encoded serial data
sDataIn_p : in std_logic; --TMDS data channel positive
sDataIn_n : in std_logic; --TMDS data channel negative
--Encoded parallel data (raw)
pDataIn : out STD_LOGIC_VECTOR (kParallelWidth-1 downto 0);
--Control for phase alignment
pBitslip : in STD_LOGIC; --Bitslip for ISERDESE2
pIDLY_LD : in STD_LOGIC; --IDELAYE2 Load
pIDLY_CE : in STD_LOGIC; --IDELAYE2 CE
pIDLY_INC : in STD_LOGIC; --IDELAYE2 Tap Increment
pIDLY_CNT : out std_logic_vector(kIDLY_TapWidth-1 downto 0); --IDELAYE2 Current Tap Count
aRst : in STD_LOGIC
);
end InputSERDES;
architecture Behavioral of InputSERDES is
signal sDataIn, sDataInDly, icascade1, icascade2, SerialClkInv : std_logic;
signal pDataIn_q : std_logic_vector(13 downto 0); --ISERDESE2 can do 1:14 at most
begin
-- Differential input buffer for TMDS I/O standard
InputBuffer: IBUFDS
generic map (
DIFF_TERM => FALSE,
IOSTANDARD => "TMDS_33")
port map (
I => sDataIn_p,
IB => sDataIn_n,
O => sDataIn);
-- Delay element for phase alignment of serial data
InputDelay: IDELAYE2
generic map (
CINVCTRL_SEL => "FALSE", -- TRUE, FALSE
DELAY_SRC => "IDATAIN", -- IDATAIN, DATAIN
HIGH_PERFORMANCE_MODE => "TRUE", -- TRUE, FALSE
IDELAY_TYPE => "VARIABLE", -- FIXED, VARIABLE, or VAR_LOADABLE
IDELAY_VALUE => 0, -- 0 to 31
REFCLK_FREQUENCY => 200.0,
PIPE_SEL => "FALSE",
SIGNAL_PATTERN => "DATA") -- CLOCK, DATA
port map (
DATAOUT => sDataInDly, -- Delayed signal
DATAIN => '0', -- Not used; IDATAIN instead
C => PixelClk, -- Clock for control signals (CE,INC...)
CE => pIDLY_CE,
INC => pIDLY_INC,
IDATAIN => sDataIn, -- Driven by IOB
LD => pIDLY_LD,
REGRST => '0', --not used in VARIABLE mode
LDPIPEEN => '0',
CNTVALUEIN => "00000", --not used in VARIABLE mode
CNTVALUEOUT => pIDLY_CNT, -- current tap value
CINVCTRL => '0');
--Invert locally for ISERDESE2
SerialClkInv <= not SerialClk;
-- De-serializer, 1:10 (1:5 DDR), master-slave cascaded
DeserializerMaster: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => kParallelWidth,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "MASTER")
port map (
Q1 => pDataIn_q(0),
Q2 => pDataIn_q(1),
Q3 => pDataIn_q(2),
Q4 => pDataIn_q(3),
Q5 => pDataIn_q(4),
Q6 => pDataIn_q(5),
Q7 => pDataIn_q(6),
Q8 => pDataIn_q(7),
SHIFTOUT1 => icascade1, -- Cascade connection to Slave ISERDES
SHIFTOUT2 => icascade2, -- Cascade connection to Slave ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => sDataInDly, -- 1-bit Input signal from IODELAYE1.
RST => aRst, -- 1-bit Asynchronous reset only.
SHIFTIN1 => '0',
SHIFTIN2 => '0',
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
DeserializerSlave: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 10,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "SLAVE")
port map (
Q1 => open, --not used in cascaded mode
Q2 => open, --not used in cascaded mode
Q3 => pDataIn_q(8),
Q4 => pDataIn_q(9),
Q5 => pDataIn_q(10),
Q6 => pDataIn_q(11),
Q7 => pDataIn_q(12),
Q8 => pDataIn_q(13),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTIN1 => icascade1, -- Cascade connections from Master ISERDES
SHIFTIN2 => icascade2,-- Cascade connections from Master ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => '0', -- not used in cascaded Slave mode
RST => aRst, -- 1-bit Asynchronous reset only.
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
-------------------------------------------------------------
-- Concatenate the serdes outputs together. Keep the timesliced
-- bits together, and placing the earliest bits on the right
-- ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
-- the output will be 3210, 7654, ...
-------------------------------------------------------------
SliceISERDES_q: for slice_count in 0 to kParallelWidth-1 generate begin
--DVI sends least significant bit first
-- This places the first data in time on the right
pDataIn(slice_count) <= pDataIn_q(kParallelWidth-slice_count-1);
end generate SliceISERDES_q;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: InputSERDES.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates the Xilinx 7-series primitives necessary for
-- de-serializing the TMDS data stream.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity InputSERDES is
Generic (
kIDLY_TapWidth : natural := 5; -- number of bits for IDELAYE2 tap counter
kParallelWidth : natural := 10); -- number of parallel bits
Port (
PixelClk : in std_logic; --Recovered TMDS clock x1 (CLKDIV)
SerialClk : in std_logic; --Recovered TMDS clock x5 (CLK)
--Encoded serial data
sDataIn_p : in std_logic; --TMDS data channel positive
sDataIn_n : in std_logic; --TMDS data channel negative
--Encoded parallel data (raw)
pDataIn : out STD_LOGIC_VECTOR (kParallelWidth-1 downto 0);
--Control for phase alignment
pBitslip : in STD_LOGIC; --Bitslip for ISERDESE2
pIDLY_LD : in STD_LOGIC; --IDELAYE2 Load
pIDLY_CE : in STD_LOGIC; --IDELAYE2 CE
pIDLY_INC : in STD_LOGIC; --IDELAYE2 Tap Increment
pIDLY_CNT : out std_logic_vector(kIDLY_TapWidth-1 downto 0); --IDELAYE2 Current Tap Count
aRst : in STD_LOGIC
);
end InputSERDES;
architecture Behavioral of InputSERDES is
signal sDataIn, sDataInDly, icascade1, icascade2, SerialClkInv : std_logic;
signal pDataIn_q : std_logic_vector(13 downto 0); --ISERDESE2 can do 1:14 at most
begin
-- Differential input buffer for TMDS I/O standard
InputBuffer: IBUFDS
generic map (
DIFF_TERM => FALSE,
IOSTANDARD => "TMDS_33")
port map (
I => sDataIn_p,
IB => sDataIn_n,
O => sDataIn);
-- Delay element for phase alignment of serial data
InputDelay: IDELAYE2
generic map (
CINVCTRL_SEL => "FALSE", -- TRUE, FALSE
DELAY_SRC => "IDATAIN", -- IDATAIN, DATAIN
HIGH_PERFORMANCE_MODE => "TRUE", -- TRUE, FALSE
IDELAY_TYPE => "VARIABLE", -- FIXED, VARIABLE, or VAR_LOADABLE
IDELAY_VALUE => 0, -- 0 to 31
REFCLK_FREQUENCY => 200.0,
PIPE_SEL => "FALSE",
SIGNAL_PATTERN => "DATA") -- CLOCK, DATA
port map (
DATAOUT => sDataInDly, -- Delayed signal
DATAIN => '0', -- Not used; IDATAIN instead
C => PixelClk, -- Clock for control signals (CE,INC...)
CE => pIDLY_CE,
INC => pIDLY_INC,
IDATAIN => sDataIn, -- Driven by IOB
LD => pIDLY_LD,
REGRST => '0', --not used in VARIABLE mode
LDPIPEEN => '0',
CNTVALUEIN => "00000", --not used in VARIABLE mode
CNTVALUEOUT => pIDLY_CNT, -- current tap value
CINVCTRL => '0');
--Invert locally for ISERDESE2
SerialClkInv <= not SerialClk;
-- De-serializer, 1:10 (1:5 DDR), master-slave cascaded
DeserializerMaster: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => kParallelWidth,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "MASTER")
port map (
Q1 => pDataIn_q(0),
Q2 => pDataIn_q(1),
Q3 => pDataIn_q(2),
Q4 => pDataIn_q(3),
Q5 => pDataIn_q(4),
Q6 => pDataIn_q(5),
Q7 => pDataIn_q(6),
Q8 => pDataIn_q(7),
SHIFTOUT1 => icascade1, -- Cascade connection to Slave ISERDES
SHIFTOUT2 => icascade2, -- Cascade connection to Slave ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => sDataInDly, -- 1-bit Input signal from IODELAYE1.
RST => aRst, -- 1-bit Asynchronous reset only.
SHIFTIN1 => '0',
SHIFTIN2 => '0',
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
DeserializerSlave: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 10,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "SLAVE")
port map (
Q1 => open, --not used in cascaded mode
Q2 => open, --not used in cascaded mode
Q3 => pDataIn_q(8),
Q4 => pDataIn_q(9),
Q5 => pDataIn_q(10),
Q6 => pDataIn_q(11),
Q7 => pDataIn_q(12),
Q8 => pDataIn_q(13),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTIN1 => icascade1, -- Cascade connections from Master ISERDES
SHIFTIN2 => icascade2,-- Cascade connections from Master ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => '0', -- not used in cascaded Slave mode
RST => aRst, -- 1-bit Asynchronous reset only.
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
-------------------------------------------------------------
-- Concatenate the serdes outputs together. Keep the timesliced
-- bits together, and placing the earliest bits on the right
-- ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
-- the output will be 3210, 7654, ...
-------------------------------------------------------------
SliceISERDES_q: for slice_count in 0 to kParallelWidth-1 generate begin
--DVI sends least significant bit first
-- This places the first data in time on the right
pDataIn(slice_count) <= pDataIn_q(kParallelWidth-slice_count-1);
end generate SliceISERDES_q;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: InputSERDES.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates the Xilinx 7-series primitives necessary for
-- de-serializing the TMDS data stream.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity InputSERDES is
Generic (
kIDLY_TapWidth : natural := 5; -- number of bits for IDELAYE2 tap counter
kParallelWidth : natural := 10); -- number of parallel bits
Port (
PixelClk : in std_logic; --Recovered TMDS clock x1 (CLKDIV)
SerialClk : in std_logic; --Recovered TMDS clock x5 (CLK)
--Encoded serial data
sDataIn_p : in std_logic; --TMDS data channel positive
sDataIn_n : in std_logic; --TMDS data channel negative
--Encoded parallel data (raw)
pDataIn : out STD_LOGIC_VECTOR (kParallelWidth-1 downto 0);
--Control for phase alignment
pBitslip : in STD_LOGIC; --Bitslip for ISERDESE2
pIDLY_LD : in STD_LOGIC; --IDELAYE2 Load
pIDLY_CE : in STD_LOGIC; --IDELAYE2 CE
pIDLY_INC : in STD_LOGIC; --IDELAYE2 Tap Increment
pIDLY_CNT : out std_logic_vector(kIDLY_TapWidth-1 downto 0); --IDELAYE2 Current Tap Count
aRst : in STD_LOGIC
);
end InputSERDES;
architecture Behavioral of InputSERDES is
signal sDataIn, sDataInDly, icascade1, icascade2, SerialClkInv : std_logic;
signal pDataIn_q : std_logic_vector(13 downto 0); --ISERDESE2 can do 1:14 at most
begin
-- Differential input buffer for TMDS I/O standard
InputBuffer: IBUFDS
generic map (
DIFF_TERM => FALSE,
IOSTANDARD => "TMDS_33")
port map (
I => sDataIn_p,
IB => sDataIn_n,
O => sDataIn);
-- Delay element for phase alignment of serial data
InputDelay: IDELAYE2
generic map (
CINVCTRL_SEL => "FALSE", -- TRUE, FALSE
DELAY_SRC => "IDATAIN", -- IDATAIN, DATAIN
HIGH_PERFORMANCE_MODE => "TRUE", -- TRUE, FALSE
IDELAY_TYPE => "VARIABLE", -- FIXED, VARIABLE, or VAR_LOADABLE
IDELAY_VALUE => 0, -- 0 to 31
REFCLK_FREQUENCY => 200.0,
PIPE_SEL => "FALSE",
SIGNAL_PATTERN => "DATA") -- CLOCK, DATA
port map (
DATAOUT => sDataInDly, -- Delayed signal
DATAIN => '0', -- Not used; IDATAIN instead
C => PixelClk, -- Clock for control signals (CE,INC...)
CE => pIDLY_CE,
INC => pIDLY_INC,
IDATAIN => sDataIn, -- Driven by IOB
LD => pIDLY_LD,
REGRST => '0', --not used in VARIABLE mode
LDPIPEEN => '0',
CNTVALUEIN => "00000", --not used in VARIABLE mode
CNTVALUEOUT => pIDLY_CNT, -- current tap value
CINVCTRL => '0');
--Invert locally for ISERDESE2
SerialClkInv <= not SerialClk;
-- De-serializer, 1:10 (1:5 DDR), master-slave cascaded
DeserializerMaster: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => kParallelWidth,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "MASTER")
port map (
Q1 => pDataIn_q(0),
Q2 => pDataIn_q(1),
Q3 => pDataIn_q(2),
Q4 => pDataIn_q(3),
Q5 => pDataIn_q(4),
Q6 => pDataIn_q(5),
Q7 => pDataIn_q(6),
Q8 => pDataIn_q(7),
SHIFTOUT1 => icascade1, -- Cascade connection to Slave ISERDES
SHIFTOUT2 => icascade2, -- Cascade connection to Slave ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => sDataInDly, -- 1-bit Input signal from IODELAYE1.
RST => aRst, -- 1-bit Asynchronous reset only.
SHIFTIN1 => '0',
SHIFTIN2 => '0',
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
DeserializerSlave: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 10,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "SLAVE")
port map (
Q1 => open, --not used in cascaded mode
Q2 => open, --not used in cascaded mode
Q3 => pDataIn_q(8),
Q4 => pDataIn_q(9),
Q5 => pDataIn_q(10),
Q6 => pDataIn_q(11),
Q7 => pDataIn_q(12),
Q8 => pDataIn_q(13),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTIN1 => icascade1, -- Cascade connections from Master ISERDES
SHIFTIN2 => icascade2,-- Cascade connections from Master ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => '0', -- not used in cascaded Slave mode
RST => aRst, -- 1-bit Asynchronous reset only.
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
-------------------------------------------------------------
-- Concatenate the serdes outputs together. Keep the timesliced
-- bits together, and placing the earliest bits on the right
-- ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
-- the output will be 3210, 7654, ...
-------------------------------------------------------------
SliceISERDES_q: for slice_count in 0 to kParallelWidth-1 generate begin
--DVI sends least significant bit first
-- This places the first data in time on the right
pDataIn(slice_count) <= pDataIn_q(kParallelWidth-slice_count-1);
end generate SliceISERDES_q;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: InputSERDES.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates the Xilinx 7-series primitives necessary for
-- de-serializing the TMDS data stream.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity InputSERDES is
Generic (
kIDLY_TapWidth : natural := 5; -- number of bits for IDELAYE2 tap counter
kParallelWidth : natural := 10); -- number of parallel bits
Port (
PixelClk : in std_logic; --Recovered TMDS clock x1 (CLKDIV)
SerialClk : in std_logic; --Recovered TMDS clock x5 (CLK)
--Encoded serial data
sDataIn_p : in std_logic; --TMDS data channel positive
sDataIn_n : in std_logic; --TMDS data channel negative
--Encoded parallel data (raw)
pDataIn : out STD_LOGIC_VECTOR (kParallelWidth-1 downto 0);
--Control for phase alignment
pBitslip : in STD_LOGIC; --Bitslip for ISERDESE2
pIDLY_LD : in STD_LOGIC; --IDELAYE2 Load
pIDLY_CE : in STD_LOGIC; --IDELAYE2 CE
pIDLY_INC : in STD_LOGIC; --IDELAYE2 Tap Increment
pIDLY_CNT : out std_logic_vector(kIDLY_TapWidth-1 downto 0); --IDELAYE2 Current Tap Count
aRst : in STD_LOGIC
);
end InputSERDES;
architecture Behavioral of InputSERDES is
signal sDataIn, sDataInDly, icascade1, icascade2, SerialClkInv : std_logic;
signal pDataIn_q : std_logic_vector(13 downto 0); --ISERDESE2 can do 1:14 at most
begin
-- Differential input buffer for TMDS I/O standard
InputBuffer: IBUFDS
generic map (
DIFF_TERM => FALSE,
IOSTANDARD => "TMDS_33")
port map (
I => sDataIn_p,
IB => sDataIn_n,
O => sDataIn);
-- Delay element for phase alignment of serial data
InputDelay: IDELAYE2
generic map (
CINVCTRL_SEL => "FALSE", -- TRUE, FALSE
DELAY_SRC => "IDATAIN", -- IDATAIN, DATAIN
HIGH_PERFORMANCE_MODE => "TRUE", -- TRUE, FALSE
IDELAY_TYPE => "VARIABLE", -- FIXED, VARIABLE, or VAR_LOADABLE
IDELAY_VALUE => 0, -- 0 to 31
REFCLK_FREQUENCY => 200.0,
PIPE_SEL => "FALSE",
SIGNAL_PATTERN => "DATA") -- CLOCK, DATA
port map (
DATAOUT => sDataInDly, -- Delayed signal
DATAIN => '0', -- Not used; IDATAIN instead
C => PixelClk, -- Clock for control signals (CE,INC...)
CE => pIDLY_CE,
INC => pIDLY_INC,
IDATAIN => sDataIn, -- Driven by IOB
LD => pIDLY_LD,
REGRST => '0', --not used in VARIABLE mode
LDPIPEEN => '0',
CNTVALUEIN => "00000", --not used in VARIABLE mode
CNTVALUEOUT => pIDLY_CNT, -- current tap value
CINVCTRL => '0');
--Invert locally for ISERDESE2
SerialClkInv <= not SerialClk;
-- De-serializer, 1:10 (1:5 DDR), master-slave cascaded
DeserializerMaster: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => kParallelWidth,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "MASTER")
port map (
Q1 => pDataIn_q(0),
Q2 => pDataIn_q(1),
Q3 => pDataIn_q(2),
Q4 => pDataIn_q(3),
Q5 => pDataIn_q(4),
Q6 => pDataIn_q(5),
Q7 => pDataIn_q(6),
Q8 => pDataIn_q(7),
SHIFTOUT1 => icascade1, -- Cascade connection to Slave ISERDES
SHIFTOUT2 => icascade2, -- Cascade connection to Slave ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => sDataInDly, -- 1-bit Input signal from IODELAYE1.
RST => aRst, -- 1-bit Asynchronous reset only.
SHIFTIN1 => '0',
SHIFTIN2 => '0',
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
DeserializerSlave: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 10,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "SLAVE")
port map (
Q1 => open, --not used in cascaded mode
Q2 => open, --not used in cascaded mode
Q3 => pDataIn_q(8),
Q4 => pDataIn_q(9),
Q5 => pDataIn_q(10),
Q6 => pDataIn_q(11),
Q7 => pDataIn_q(12),
Q8 => pDataIn_q(13),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTIN1 => icascade1, -- Cascade connections from Master ISERDES
SHIFTIN2 => icascade2,-- Cascade connections from Master ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => '0', -- not used in cascaded Slave mode
RST => aRst, -- 1-bit Asynchronous reset only.
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
-------------------------------------------------------------
-- Concatenate the serdes outputs together. Keep the timesliced
-- bits together, and placing the earliest bits on the right
-- ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
-- the output will be 3210, 7654, ...
-------------------------------------------------------------
SliceISERDES_q: for slice_count in 0 to kParallelWidth-1 generate begin
--DVI sends least significant bit first
-- This places the first data in time on the right
pDataIn(slice_count) <= pDataIn_q(kParallelWidth-slice_count-1);
end generate SliceISERDES_q;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: InputSERDES.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates the Xilinx 7-series primitives necessary for
-- de-serializing the TMDS data stream.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity InputSERDES is
Generic (
kIDLY_TapWidth : natural := 5; -- number of bits for IDELAYE2 tap counter
kParallelWidth : natural := 10); -- number of parallel bits
Port (
PixelClk : in std_logic; --Recovered TMDS clock x1 (CLKDIV)
SerialClk : in std_logic; --Recovered TMDS clock x5 (CLK)
--Encoded serial data
sDataIn_p : in std_logic; --TMDS data channel positive
sDataIn_n : in std_logic; --TMDS data channel negative
--Encoded parallel data (raw)
pDataIn : out STD_LOGIC_VECTOR (kParallelWidth-1 downto 0);
--Control for phase alignment
pBitslip : in STD_LOGIC; --Bitslip for ISERDESE2
pIDLY_LD : in STD_LOGIC; --IDELAYE2 Load
pIDLY_CE : in STD_LOGIC; --IDELAYE2 CE
pIDLY_INC : in STD_LOGIC; --IDELAYE2 Tap Increment
pIDLY_CNT : out std_logic_vector(kIDLY_TapWidth-1 downto 0); --IDELAYE2 Current Tap Count
aRst : in STD_LOGIC
);
end InputSERDES;
architecture Behavioral of InputSERDES is
signal sDataIn, sDataInDly, icascade1, icascade2, SerialClkInv : std_logic;
signal pDataIn_q : std_logic_vector(13 downto 0); --ISERDESE2 can do 1:14 at most
begin
-- Differential input buffer for TMDS I/O standard
InputBuffer: IBUFDS
generic map (
DIFF_TERM => FALSE,
IOSTANDARD => "TMDS_33")
port map (
I => sDataIn_p,
IB => sDataIn_n,
O => sDataIn);
-- Delay element for phase alignment of serial data
InputDelay: IDELAYE2
generic map (
CINVCTRL_SEL => "FALSE", -- TRUE, FALSE
DELAY_SRC => "IDATAIN", -- IDATAIN, DATAIN
HIGH_PERFORMANCE_MODE => "TRUE", -- TRUE, FALSE
IDELAY_TYPE => "VARIABLE", -- FIXED, VARIABLE, or VAR_LOADABLE
IDELAY_VALUE => 0, -- 0 to 31
REFCLK_FREQUENCY => 200.0,
PIPE_SEL => "FALSE",
SIGNAL_PATTERN => "DATA") -- CLOCK, DATA
port map (
DATAOUT => sDataInDly, -- Delayed signal
DATAIN => '0', -- Not used; IDATAIN instead
C => PixelClk, -- Clock for control signals (CE,INC...)
CE => pIDLY_CE,
INC => pIDLY_INC,
IDATAIN => sDataIn, -- Driven by IOB
LD => pIDLY_LD,
REGRST => '0', --not used in VARIABLE mode
LDPIPEEN => '0',
CNTVALUEIN => "00000", --not used in VARIABLE mode
CNTVALUEOUT => pIDLY_CNT, -- current tap value
CINVCTRL => '0');
--Invert locally for ISERDESE2
SerialClkInv <= not SerialClk;
-- De-serializer, 1:10 (1:5 DDR), master-slave cascaded
DeserializerMaster: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => kParallelWidth,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "MASTER")
port map (
Q1 => pDataIn_q(0),
Q2 => pDataIn_q(1),
Q3 => pDataIn_q(2),
Q4 => pDataIn_q(3),
Q5 => pDataIn_q(4),
Q6 => pDataIn_q(5),
Q7 => pDataIn_q(6),
Q8 => pDataIn_q(7),
SHIFTOUT1 => icascade1, -- Cascade connection to Slave ISERDES
SHIFTOUT2 => icascade2, -- Cascade connection to Slave ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => sDataInDly, -- 1-bit Input signal from IODELAYE1.
RST => aRst, -- 1-bit Asynchronous reset only.
SHIFTIN1 => '0',
SHIFTIN2 => '0',
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
DeserializerSlave: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 10,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "SLAVE")
port map (
Q1 => open, --not used in cascaded mode
Q2 => open, --not used in cascaded mode
Q3 => pDataIn_q(8),
Q4 => pDataIn_q(9),
Q5 => pDataIn_q(10),
Q6 => pDataIn_q(11),
Q7 => pDataIn_q(12),
Q8 => pDataIn_q(13),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTIN1 => icascade1, -- Cascade connections from Master ISERDES
SHIFTIN2 => icascade2,-- Cascade connections from Master ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => '0', -- not used in cascaded Slave mode
RST => aRst, -- 1-bit Asynchronous reset only.
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
-------------------------------------------------------------
-- Concatenate the serdes outputs together. Keep the timesliced
-- bits together, and placing the earliest bits on the right
-- ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
-- the output will be 3210, 7654, ...
-------------------------------------------------------------
SliceISERDES_q: for slice_count in 0 to kParallelWidth-1 generate begin
--DVI sends least significant bit first
-- This places the first data in time on the right
pDataIn(slice_count) <= pDataIn_q(kParallelWidth-slice_count-1);
end generate SliceISERDES_q;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: InputSERDES.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates the Xilinx 7-series primitives necessary for
-- de-serializing the TMDS data stream.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity InputSERDES is
Generic (
kIDLY_TapWidth : natural := 5; -- number of bits for IDELAYE2 tap counter
kParallelWidth : natural := 10); -- number of parallel bits
Port (
PixelClk : in std_logic; --Recovered TMDS clock x1 (CLKDIV)
SerialClk : in std_logic; --Recovered TMDS clock x5 (CLK)
--Encoded serial data
sDataIn_p : in std_logic; --TMDS data channel positive
sDataIn_n : in std_logic; --TMDS data channel negative
--Encoded parallel data (raw)
pDataIn : out STD_LOGIC_VECTOR (kParallelWidth-1 downto 0);
--Control for phase alignment
pBitslip : in STD_LOGIC; --Bitslip for ISERDESE2
pIDLY_LD : in STD_LOGIC; --IDELAYE2 Load
pIDLY_CE : in STD_LOGIC; --IDELAYE2 CE
pIDLY_INC : in STD_LOGIC; --IDELAYE2 Tap Increment
pIDLY_CNT : out std_logic_vector(kIDLY_TapWidth-1 downto 0); --IDELAYE2 Current Tap Count
aRst : in STD_LOGIC
);
end InputSERDES;
architecture Behavioral of InputSERDES is
signal sDataIn, sDataInDly, icascade1, icascade2, SerialClkInv : std_logic;
signal pDataIn_q : std_logic_vector(13 downto 0); --ISERDESE2 can do 1:14 at most
begin
-- Differential input buffer for TMDS I/O standard
InputBuffer: IBUFDS
generic map (
DIFF_TERM => FALSE,
IOSTANDARD => "TMDS_33")
port map (
I => sDataIn_p,
IB => sDataIn_n,
O => sDataIn);
-- Delay element for phase alignment of serial data
InputDelay: IDELAYE2
generic map (
CINVCTRL_SEL => "FALSE", -- TRUE, FALSE
DELAY_SRC => "IDATAIN", -- IDATAIN, DATAIN
HIGH_PERFORMANCE_MODE => "TRUE", -- TRUE, FALSE
IDELAY_TYPE => "VARIABLE", -- FIXED, VARIABLE, or VAR_LOADABLE
IDELAY_VALUE => 0, -- 0 to 31
REFCLK_FREQUENCY => 200.0,
PIPE_SEL => "FALSE",
SIGNAL_PATTERN => "DATA") -- CLOCK, DATA
port map (
DATAOUT => sDataInDly, -- Delayed signal
DATAIN => '0', -- Not used; IDATAIN instead
C => PixelClk, -- Clock for control signals (CE,INC...)
CE => pIDLY_CE,
INC => pIDLY_INC,
IDATAIN => sDataIn, -- Driven by IOB
LD => pIDLY_LD,
REGRST => '0', --not used in VARIABLE mode
LDPIPEEN => '0',
CNTVALUEIN => "00000", --not used in VARIABLE mode
CNTVALUEOUT => pIDLY_CNT, -- current tap value
CINVCTRL => '0');
--Invert locally for ISERDESE2
SerialClkInv <= not SerialClk;
-- De-serializer, 1:10 (1:5 DDR), master-slave cascaded
DeserializerMaster: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => kParallelWidth,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "MASTER")
port map (
Q1 => pDataIn_q(0),
Q2 => pDataIn_q(1),
Q3 => pDataIn_q(2),
Q4 => pDataIn_q(3),
Q5 => pDataIn_q(4),
Q6 => pDataIn_q(5),
Q7 => pDataIn_q(6),
Q8 => pDataIn_q(7),
SHIFTOUT1 => icascade1, -- Cascade connection to Slave ISERDES
SHIFTOUT2 => icascade2, -- Cascade connection to Slave ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => sDataInDly, -- 1-bit Input signal from IODELAYE1.
RST => aRst, -- 1-bit Asynchronous reset only.
SHIFTIN1 => '0',
SHIFTIN2 => '0',
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
DeserializerSlave: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 10,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "SLAVE")
port map (
Q1 => open, --not used in cascaded mode
Q2 => open, --not used in cascaded mode
Q3 => pDataIn_q(8),
Q4 => pDataIn_q(9),
Q5 => pDataIn_q(10),
Q6 => pDataIn_q(11),
Q7 => pDataIn_q(12),
Q8 => pDataIn_q(13),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTIN1 => icascade1, -- Cascade connections from Master ISERDES
SHIFTIN2 => icascade2,-- Cascade connections from Master ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => '0', -- not used in cascaded Slave mode
RST => aRst, -- 1-bit Asynchronous reset only.
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
-------------------------------------------------------------
-- Concatenate the serdes outputs together. Keep the timesliced
-- bits together, and placing the earliest bits on the right
-- ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
-- the output will be 3210, 7654, ...
-------------------------------------------------------------
SliceISERDES_q: for slice_count in 0 to kParallelWidth-1 generate begin
--DVI sends least significant bit first
-- This places the first data in time on the right
pDataIn(slice_count) <= pDataIn_q(kParallelWidth-slice_count-1);
end generate SliceISERDES_q;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: InputSERDES.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates the Xilinx 7-series primitives necessary for
-- de-serializing the TMDS data stream.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity InputSERDES is
Generic (
kIDLY_TapWidth : natural := 5; -- number of bits for IDELAYE2 tap counter
kParallelWidth : natural := 10); -- number of parallel bits
Port (
PixelClk : in std_logic; --Recovered TMDS clock x1 (CLKDIV)
SerialClk : in std_logic; --Recovered TMDS clock x5 (CLK)
--Encoded serial data
sDataIn_p : in std_logic; --TMDS data channel positive
sDataIn_n : in std_logic; --TMDS data channel negative
--Encoded parallel data (raw)
pDataIn : out STD_LOGIC_VECTOR (kParallelWidth-1 downto 0);
--Control for phase alignment
pBitslip : in STD_LOGIC; --Bitslip for ISERDESE2
pIDLY_LD : in STD_LOGIC; --IDELAYE2 Load
pIDLY_CE : in STD_LOGIC; --IDELAYE2 CE
pIDLY_INC : in STD_LOGIC; --IDELAYE2 Tap Increment
pIDLY_CNT : out std_logic_vector(kIDLY_TapWidth-1 downto 0); --IDELAYE2 Current Tap Count
aRst : in STD_LOGIC
);
end InputSERDES;
architecture Behavioral of InputSERDES is
signal sDataIn, sDataInDly, icascade1, icascade2, SerialClkInv : std_logic;
signal pDataIn_q : std_logic_vector(13 downto 0); --ISERDESE2 can do 1:14 at most
begin
-- Differential input buffer for TMDS I/O standard
InputBuffer: IBUFDS
generic map (
DIFF_TERM => FALSE,
IOSTANDARD => "TMDS_33")
port map (
I => sDataIn_p,
IB => sDataIn_n,
O => sDataIn);
-- Delay element for phase alignment of serial data
InputDelay: IDELAYE2
generic map (
CINVCTRL_SEL => "FALSE", -- TRUE, FALSE
DELAY_SRC => "IDATAIN", -- IDATAIN, DATAIN
HIGH_PERFORMANCE_MODE => "TRUE", -- TRUE, FALSE
IDELAY_TYPE => "VARIABLE", -- FIXED, VARIABLE, or VAR_LOADABLE
IDELAY_VALUE => 0, -- 0 to 31
REFCLK_FREQUENCY => 200.0,
PIPE_SEL => "FALSE",
SIGNAL_PATTERN => "DATA") -- CLOCK, DATA
port map (
DATAOUT => sDataInDly, -- Delayed signal
DATAIN => '0', -- Not used; IDATAIN instead
C => PixelClk, -- Clock for control signals (CE,INC...)
CE => pIDLY_CE,
INC => pIDLY_INC,
IDATAIN => sDataIn, -- Driven by IOB
LD => pIDLY_LD,
REGRST => '0', --not used in VARIABLE mode
LDPIPEEN => '0',
CNTVALUEIN => "00000", --not used in VARIABLE mode
CNTVALUEOUT => pIDLY_CNT, -- current tap value
CINVCTRL => '0');
--Invert locally for ISERDESE2
SerialClkInv <= not SerialClk;
-- De-serializer, 1:10 (1:5 DDR), master-slave cascaded
DeserializerMaster: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => kParallelWidth,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "MASTER")
port map (
Q1 => pDataIn_q(0),
Q2 => pDataIn_q(1),
Q3 => pDataIn_q(2),
Q4 => pDataIn_q(3),
Q5 => pDataIn_q(4),
Q6 => pDataIn_q(5),
Q7 => pDataIn_q(6),
Q8 => pDataIn_q(7),
SHIFTOUT1 => icascade1, -- Cascade connection to Slave ISERDES
SHIFTOUT2 => icascade2, -- Cascade connection to Slave ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => sDataInDly, -- 1-bit Input signal from IODELAYE1.
RST => aRst, -- 1-bit Asynchronous reset only.
SHIFTIN1 => '0',
SHIFTIN2 => '0',
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
DeserializerSlave: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 10,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "SLAVE")
port map (
Q1 => open, --not used in cascaded mode
Q2 => open, --not used in cascaded mode
Q3 => pDataIn_q(8),
Q4 => pDataIn_q(9),
Q5 => pDataIn_q(10),
Q6 => pDataIn_q(11),
Q7 => pDataIn_q(12),
Q8 => pDataIn_q(13),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTIN1 => icascade1, -- Cascade connections from Master ISERDES
SHIFTIN2 => icascade2,-- Cascade connections from Master ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => '0', -- not used in cascaded Slave mode
RST => aRst, -- 1-bit Asynchronous reset only.
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
-------------------------------------------------------------
-- Concatenate the serdes outputs together. Keep the timesliced
-- bits together, and placing the earliest bits on the right
-- ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
-- the output will be 3210, 7654, ...
-------------------------------------------------------------
SliceISERDES_q: for slice_count in 0 to kParallelWidth-1 generate begin
--DVI sends least significant bit first
-- This places the first data in time on the right
pDataIn(slice_count) <= pDataIn_q(kParallelWidth-slice_count-1);
end generate SliceISERDES_q;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: InputSERDES.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates the Xilinx 7-series primitives necessary for
-- de-serializing the TMDS data stream.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity InputSERDES is
Generic (
kIDLY_TapWidth : natural := 5; -- number of bits for IDELAYE2 tap counter
kParallelWidth : natural := 10); -- number of parallel bits
Port (
PixelClk : in std_logic; --Recovered TMDS clock x1 (CLKDIV)
SerialClk : in std_logic; --Recovered TMDS clock x5 (CLK)
--Encoded serial data
sDataIn_p : in std_logic; --TMDS data channel positive
sDataIn_n : in std_logic; --TMDS data channel negative
--Encoded parallel data (raw)
pDataIn : out STD_LOGIC_VECTOR (kParallelWidth-1 downto 0);
--Control for phase alignment
pBitslip : in STD_LOGIC; --Bitslip for ISERDESE2
pIDLY_LD : in STD_LOGIC; --IDELAYE2 Load
pIDLY_CE : in STD_LOGIC; --IDELAYE2 CE
pIDLY_INC : in STD_LOGIC; --IDELAYE2 Tap Increment
pIDLY_CNT : out std_logic_vector(kIDLY_TapWidth-1 downto 0); --IDELAYE2 Current Tap Count
aRst : in STD_LOGIC
);
end InputSERDES;
architecture Behavioral of InputSERDES is
signal sDataIn, sDataInDly, icascade1, icascade2, SerialClkInv : std_logic;
signal pDataIn_q : std_logic_vector(13 downto 0); --ISERDESE2 can do 1:14 at most
begin
-- Differential input buffer for TMDS I/O standard
InputBuffer: IBUFDS
generic map (
DIFF_TERM => FALSE,
IOSTANDARD => "TMDS_33")
port map (
I => sDataIn_p,
IB => sDataIn_n,
O => sDataIn);
-- Delay element for phase alignment of serial data
InputDelay: IDELAYE2
generic map (
CINVCTRL_SEL => "FALSE", -- TRUE, FALSE
DELAY_SRC => "IDATAIN", -- IDATAIN, DATAIN
HIGH_PERFORMANCE_MODE => "TRUE", -- TRUE, FALSE
IDELAY_TYPE => "VARIABLE", -- FIXED, VARIABLE, or VAR_LOADABLE
IDELAY_VALUE => 0, -- 0 to 31
REFCLK_FREQUENCY => 200.0,
PIPE_SEL => "FALSE",
SIGNAL_PATTERN => "DATA") -- CLOCK, DATA
port map (
DATAOUT => sDataInDly, -- Delayed signal
DATAIN => '0', -- Not used; IDATAIN instead
C => PixelClk, -- Clock for control signals (CE,INC...)
CE => pIDLY_CE,
INC => pIDLY_INC,
IDATAIN => sDataIn, -- Driven by IOB
LD => pIDLY_LD,
REGRST => '0', --not used in VARIABLE mode
LDPIPEEN => '0',
CNTVALUEIN => "00000", --not used in VARIABLE mode
CNTVALUEOUT => pIDLY_CNT, -- current tap value
CINVCTRL => '0');
--Invert locally for ISERDESE2
SerialClkInv <= not SerialClk;
-- De-serializer, 1:10 (1:5 DDR), master-slave cascaded
DeserializerMaster: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => kParallelWidth,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "MASTER")
port map (
Q1 => pDataIn_q(0),
Q2 => pDataIn_q(1),
Q3 => pDataIn_q(2),
Q4 => pDataIn_q(3),
Q5 => pDataIn_q(4),
Q6 => pDataIn_q(5),
Q7 => pDataIn_q(6),
Q8 => pDataIn_q(7),
SHIFTOUT1 => icascade1, -- Cascade connection to Slave ISERDES
SHIFTOUT2 => icascade2, -- Cascade connection to Slave ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => sDataInDly, -- 1-bit Input signal from IODELAYE1.
RST => aRst, -- 1-bit Asynchronous reset only.
SHIFTIN1 => '0',
SHIFTIN2 => '0',
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
DeserializerSlave: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 10,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "SLAVE")
port map (
Q1 => open, --not used in cascaded mode
Q2 => open, --not used in cascaded mode
Q3 => pDataIn_q(8),
Q4 => pDataIn_q(9),
Q5 => pDataIn_q(10),
Q6 => pDataIn_q(11),
Q7 => pDataIn_q(12),
Q8 => pDataIn_q(13),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTIN1 => icascade1, -- Cascade connections from Master ISERDES
SHIFTIN2 => icascade2,-- Cascade connections from Master ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => '0', -- not used in cascaded Slave mode
RST => aRst, -- 1-bit Asynchronous reset only.
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
-------------------------------------------------------------
-- Concatenate the serdes outputs together. Keep the timesliced
-- bits together, and placing the earliest bits on the right
-- ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
-- the output will be 3210, 7654, ...
-------------------------------------------------------------
SliceISERDES_q: for slice_count in 0 to kParallelWidth-1 generate begin
--DVI sends least significant bit first
-- This places the first data in time on the right
pDataIn(slice_count) <= pDataIn_q(kParallelWidth-slice_count-1);
end generate SliceISERDES_q;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: InputSERDES.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates the Xilinx 7-series primitives necessary for
-- de-serializing the TMDS data stream.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity InputSERDES is
Generic (
kIDLY_TapWidth : natural := 5; -- number of bits for IDELAYE2 tap counter
kParallelWidth : natural := 10); -- number of parallel bits
Port (
PixelClk : in std_logic; --Recovered TMDS clock x1 (CLKDIV)
SerialClk : in std_logic; --Recovered TMDS clock x5 (CLK)
--Encoded serial data
sDataIn_p : in std_logic; --TMDS data channel positive
sDataIn_n : in std_logic; --TMDS data channel negative
--Encoded parallel data (raw)
pDataIn : out STD_LOGIC_VECTOR (kParallelWidth-1 downto 0);
--Control for phase alignment
pBitslip : in STD_LOGIC; --Bitslip for ISERDESE2
pIDLY_LD : in STD_LOGIC; --IDELAYE2 Load
pIDLY_CE : in STD_LOGIC; --IDELAYE2 CE
pIDLY_INC : in STD_LOGIC; --IDELAYE2 Tap Increment
pIDLY_CNT : out std_logic_vector(kIDLY_TapWidth-1 downto 0); --IDELAYE2 Current Tap Count
aRst : in STD_LOGIC
);
end InputSERDES;
architecture Behavioral of InputSERDES is
signal sDataIn, sDataInDly, icascade1, icascade2, SerialClkInv : std_logic;
signal pDataIn_q : std_logic_vector(13 downto 0); --ISERDESE2 can do 1:14 at most
begin
-- Differential input buffer for TMDS I/O standard
InputBuffer: IBUFDS
generic map (
DIFF_TERM => FALSE,
IOSTANDARD => "TMDS_33")
port map (
I => sDataIn_p,
IB => sDataIn_n,
O => sDataIn);
-- Delay element for phase alignment of serial data
InputDelay: IDELAYE2
generic map (
CINVCTRL_SEL => "FALSE", -- TRUE, FALSE
DELAY_SRC => "IDATAIN", -- IDATAIN, DATAIN
HIGH_PERFORMANCE_MODE => "TRUE", -- TRUE, FALSE
IDELAY_TYPE => "VARIABLE", -- FIXED, VARIABLE, or VAR_LOADABLE
IDELAY_VALUE => 0, -- 0 to 31
REFCLK_FREQUENCY => 200.0,
PIPE_SEL => "FALSE",
SIGNAL_PATTERN => "DATA") -- CLOCK, DATA
port map (
DATAOUT => sDataInDly, -- Delayed signal
DATAIN => '0', -- Not used; IDATAIN instead
C => PixelClk, -- Clock for control signals (CE,INC...)
CE => pIDLY_CE,
INC => pIDLY_INC,
IDATAIN => sDataIn, -- Driven by IOB
LD => pIDLY_LD,
REGRST => '0', --not used in VARIABLE mode
LDPIPEEN => '0',
CNTVALUEIN => "00000", --not used in VARIABLE mode
CNTVALUEOUT => pIDLY_CNT, -- current tap value
CINVCTRL => '0');
--Invert locally for ISERDESE2
SerialClkInv <= not SerialClk;
-- De-serializer, 1:10 (1:5 DDR), master-slave cascaded
DeserializerMaster: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => kParallelWidth,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "MASTER")
port map (
Q1 => pDataIn_q(0),
Q2 => pDataIn_q(1),
Q3 => pDataIn_q(2),
Q4 => pDataIn_q(3),
Q5 => pDataIn_q(4),
Q6 => pDataIn_q(5),
Q7 => pDataIn_q(6),
Q8 => pDataIn_q(7),
SHIFTOUT1 => icascade1, -- Cascade connection to Slave ISERDES
SHIFTOUT2 => icascade2, -- Cascade connection to Slave ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => sDataInDly, -- 1-bit Input signal from IODELAYE1.
RST => aRst, -- 1-bit Asynchronous reset only.
SHIFTIN1 => '0',
SHIFTIN2 => '0',
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
DeserializerSlave: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 10,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "SLAVE")
port map (
Q1 => open, --not used in cascaded mode
Q2 => open, --not used in cascaded mode
Q3 => pDataIn_q(8),
Q4 => pDataIn_q(9),
Q5 => pDataIn_q(10),
Q6 => pDataIn_q(11),
Q7 => pDataIn_q(12),
Q8 => pDataIn_q(13),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTIN1 => icascade1, -- Cascade connections from Master ISERDES
SHIFTIN2 => icascade2,-- Cascade connections from Master ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => '0', -- not used in cascaded Slave mode
RST => aRst, -- 1-bit Asynchronous reset only.
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
-------------------------------------------------------------
-- Concatenate the serdes outputs together. Keep the timesliced
-- bits together, and placing the earliest bits on the right
-- ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
-- the output will be 3210, 7654, ...
-------------------------------------------------------------
SliceISERDES_q: for slice_count in 0 to kParallelWidth-1 generate begin
--DVI sends least significant bit first
-- This places the first data in time on the right
pDataIn(slice_count) <= pDataIn_q(kParallelWidth-slice_count-1);
end generate SliceISERDES_q;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: InputSERDES.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates the Xilinx 7-series primitives necessary for
-- de-serializing the TMDS data stream.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity InputSERDES is
Generic (
kIDLY_TapWidth : natural := 5; -- number of bits for IDELAYE2 tap counter
kParallelWidth : natural := 10); -- number of parallel bits
Port (
PixelClk : in std_logic; --Recovered TMDS clock x1 (CLKDIV)
SerialClk : in std_logic; --Recovered TMDS clock x5 (CLK)
--Encoded serial data
sDataIn_p : in std_logic; --TMDS data channel positive
sDataIn_n : in std_logic; --TMDS data channel negative
--Encoded parallel data (raw)
pDataIn : out STD_LOGIC_VECTOR (kParallelWidth-1 downto 0);
--Control for phase alignment
pBitslip : in STD_LOGIC; --Bitslip for ISERDESE2
pIDLY_LD : in STD_LOGIC; --IDELAYE2 Load
pIDLY_CE : in STD_LOGIC; --IDELAYE2 CE
pIDLY_INC : in STD_LOGIC; --IDELAYE2 Tap Increment
pIDLY_CNT : out std_logic_vector(kIDLY_TapWidth-1 downto 0); --IDELAYE2 Current Tap Count
aRst : in STD_LOGIC
);
end InputSERDES;
architecture Behavioral of InputSERDES is
signal sDataIn, sDataInDly, icascade1, icascade2, SerialClkInv : std_logic;
signal pDataIn_q : std_logic_vector(13 downto 0); --ISERDESE2 can do 1:14 at most
begin
-- Differential input buffer for TMDS I/O standard
InputBuffer: IBUFDS
generic map (
DIFF_TERM => FALSE,
IOSTANDARD => "TMDS_33")
port map (
I => sDataIn_p,
IB => sDataIn_n,
O => sDataIn);
-- Delay element for phase alignment of serial data
InputDelay: IDELAYE2
generic map (
CINVCTRL_SEL => "FALSE", -- TRUE, FALSE
DELAY_SRC => "IDATAIN", -- IDATAIN, DATAIN
HIGH_PERFORMANCE_MODE => "TRUE", -- TRUE, FALSE
IDELAY_TYPE => "VARIABLE", -- FIXED, VARIABLE, or VAR_LOADABLE
IDELAY_VALUE => 0, -- 0 to 31
REFCLK_FREQUENCY => 200.0,
PIPE_SEL => "FALSE",
SIGNAL_PATTERN => "DATA") -- CLOCK, DATA
port map (
DATAOUT => sDataInDly, -- Delayed signal
DATAIN => '0', -- Not used; IDATAIN instead
C => PixelClk, -- Clock for control signals (CE,INC...)
CE => pIDLY_CE,
INC => pIDLY_INC,
IDATAIN => sDataIn, -- Driven by IOB
LD => pIDLY_LD,
REGRST => '0', --not used in VARIABLE mode
LDPIPEEN => '0',
CNTVALUEIN => "00000", --not used in VARIABLE mode
CNTVALUEOUT => pIDLY_CNT, -- current tap value
CINVCTRL => '0');
--Invert locally for ISERDESE2
SerialClkInv <= not SerialClk;
-- De-serializer, 1:10 (1:5 DDR), master-slave cascaded
DeserializerMaster: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => kParallelWidth,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "MASTER")
port map (
Q1 => pDataIn_q(0),
Q2 => pDataIn_q(1),
Q3 => pDataIn_q(2),
Q4 => pDataIn_q(3),
Q5 => pDataIn_q(4),
Q6 => pDataIn_q(5),
Q7 => pDataIn_q(6),
Q8 => pDataIn_q(7),
SHIFTOUT1 => icascade1, -- Cascade connection to Slave ISERDES
SHIFTOUT2 => icascade2, -- Cascade connection to Slave ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => sDataInDly, -- 1-bit Input signal from IODELAYE1.
RST => aRst, -- 1-bit Asynchronous reset only.
SHIFTIN1 => '0',
SHIFTIN2 => '0',
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
DeserializerSlave: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 10,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "SLAVE")
port map (
Q1 => open, --not used in cascaded mode
Q2 => open, --not used in cascaded mode
Q3 => pDataIn_q(8),
Q4 => pDataIn_q(9),
Q5 => pDataIn_q(10),
Q6 => pDataIn_q(11),
Q7 => pDataIn_q(12),
Q8 => pDataIn_q(13),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTIN1 => icascade1, -- Cascade connections from Master ISERDES
SHIFTIN2 => icascade2,-- Cascade connections from Master ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => '0', -- not used in cascaded Slave mode
RST => aRst, -- 1-bit Asynchronous reset only.
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
-------------------------------------------------------------
-- Concatenate the serdes outputs together. Keep the timesliced
-- bits together, and placing the earliest bits on the right
-- ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
-- the output will be 3210, 7654, ...
-------------------------------------------------------------
SliceISERDES_q: for slice_count in 0 to kParallelWidth-1 generate begin
--DVI sends least significant bit first
-- This places the first data in time on the right
pDataIn(slice_count) <= pDataIn_q(kParallelWidth-slice_count-1);
end generate SliceISERDES_q;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: InputSERDES.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates the Xilinx 7-series primitives necessary for
-- de-serializing the TMDS data stream.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity InputSERDES is
Generic (
kIDLY_TapWidth : natural := 5; -- number of bits for IDELAYE2 tap counter
kParallelWidth : natural := 10); -- number of parallel bits
Port (
PixelClk : in std_logic; --Recovered TMDS clock x1 (CLKDIV)
SerialClk : in std_logic; --Recovered TMDS clock x5 (CLK)
--Encoded serial data
sDataIn_p : in std_logic; --TMDS data channel positive
sDataIn_n : in std_logic; --TMDS data channel negative
--Encoded parallel data (raw)
pDataIn : out STD_LOGIC_VECTOR (kParallelWidth-1 downto 0);
--Control for phase alignment
pBitslip : in STD_LOGIC; --Bitslip for ISERDESE2
pIDLY_LD : in STD_LOGIC; --IDELAYE2 Load
pIDLY_CE : in STD_LOGIC; --IDELAYE2 CE
pIDLY_INC : in STD_LOGIC; --IDELAYE2 Tap Increment
pIDLY_CNT : out std_logic_vector(kIDLY_TapWidth-1 downto 0); --IDELAYE2 Current Tap Count
aRst : in STD_LOGIC
);
end InputSERDES;
architecture Behavioral of InputSERDES is
signal sDataIn, sDataInDly, icascade1, icascade2, SerialClkInv : std_logic;
signal pDataIn_q : std_logic_vector(13 downto 0); --ISERDESE2 can do 1:14 at most
begin
-- Differential input buffer for TMDS I/O standard
InputBuffer: IBUFDS
generic map (
DIFF_TERM => FALSE,
IOSTANDARD => "TMDS_33")
port map (
I => sDataIn_p,
IB => sDataIn_n,
O => sDataIn);
-- Delay element for phase alignment of serial data
InputDelay: IDELAYE2
generic map (
CINVCTRL_SEL => "FALSE", -- TRUE, FALSE
DELAY_SRC => "IDATAIN", -- IDATAIN, DATAIN
HIGH_PERFORMANCE_MODE => "TRUE", -- TRUE, FALSE
IDELAY_TYPE => "VARIABLE", -- FIXED, VARIABLE, or VAR_LOADABLE
IDELAY_VALUE => 0, -- 0 to 31
REFCLK_FREQUENCY => 200.0,
PIPE_SEL => "FALSE",
SIGNAL_PATTERN => "DATA") -- CLOCK, DATA
port map (
DATAOUT => sDataInDly, -- Delayed signal
DATAIN => '0', -- Not used; IDATAIN instead
C => PixelClk, -- Clock for control signals (CE,INC...)
CE => pIDLY_CE,
INC => pIDLY_INC,
IDATAIN => sDataIn, -- Driven by IOB
LD => pIDLY_LD,
REGRST => '0', --not used in VARIABLE mode
LDPIPEEN => '0',
CNTVALUEIN => "00000", --not used in VARIABLE mode
CNTVALUEOUT => pIDLY_CNT, -- current tap value
CINVCTRL => '0');
--Invert locally for ISERDESE2
SerialClkInv <= not SerialClk;
-- De-serializer, 1:10 (1:5 DDR), master-slave cascaded
DeserializerMaster: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => kParallelWidth,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "MASTER")
port map (
Q1 => pDataIn_q(0),
Q2 => pDataIn_q(1),
Q3 => pDataIn_q(2),
Q4 => pDataIn_q(3),
Q5 => pDataIn_q(4),
Q6 => pDataIn_q(5),
Q7 => pDataIn_q(6),
Q8 => pDataIn_q(7),
SHIFTOUT1 => icascade1, -- Cascade connection to Slave ISERDES
SHIFTOUT2 => icascade2, -- Cascade connection to Slave ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => sDataInDly, -- 1-bit Input signal from IODELAYE1.
RST => aRst, -- 1-bit Asynchronous reset only.
SHIFTIN1 => '0',
SHIFTIN2 => '0',
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
DeserializerSlave: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 10,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "SLAVE")
port map (
Q1 => open, --not used in cascaded mode
Q2 => open, --not used in cascaded mode
Q3 => pDataIn_q(8),
Q4 => pDataIn_q(9),
Q5 => pDataIn_q(10),
Q6 => pDataIn_q(11),
Q7 => pDataIn_q(12),
Q8 => pDataIn_q(13),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTIN1 => icascade1, -- Cascade connections from Master ISERDES
SHIFTIN2 => icascade2,-- Cascade connections from Master ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => '0', -- not used in cascaded Slave mode
RST => aRst, -- 1-bit Asynchronous reset only.
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
-------------------------------------------------------------
-- Concatenate the serdes outputs together. Keep the timesliced
-- bits together, and placing the earliest bits on the right
-- ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
-- the output will be 3210, 7654, ...
-------------------------------------------------------------
SliceISERDES_q: for slice_count in 0 to kParallelWidth-1 generate begin
--DVI sends least significant bit first
-- This places the first data in time on the right
pDataIn(slice_count) <= pDataIn_q(kParallelWidth-slice_count-1);
end generate SliceISERDES_q;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: InputSERDES.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates the Xilinx 7-series primitives necessary for
-- de-serializing the TMDS data stream.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity InputSERDES is
Generic (
kIDLY_TapWidth : natural := 5; -- number of bits for IDELAYE2 tap counter
kParallelWidth : natural := 10); -- number of parallel bits
Port (
PixelClk : in std_logic; --Recovered TMDS clock x1 (CLKDIV)
SerialClk : in std_logic; --Recovered TMDS clock x5 (CLK)
--Encoded serial data
sDataIn_p : in std_logic; --TMDS data channel positive
sDataIn_n : in std_logic; --TMDS data channel negative
--Encoded parallel data (raw)
pDataIn : out STD_LOGIC_VECTOR (kParallelWidth-1 downto 0);
--Control for phase alignment
pBitslip : in STD_LOGIC; --Bitslip for ISERDESE2
pIDLY_LD : in STD_LOGIC; --IDELAYE2 Load
pIDLY_CE : in STD_LOGIC; --IDELAYE2 CE
pIDLY_INC : in STD_LOGIC; --IDELAYE2 Tap Increment
pIDLY_CNT : out std_logic_vector(kIDLY_TapWidth-1 downto 0); --IDELAYE2 Current Tap Count
aRst : in STD_LOGIC
);
end InputSERDES;
architecture Behavioral of InputSERDES is
signal sDataIn, sDataInDly, icascade1, icascade2, SerialClkInv : std_logic;
signal pDataIn_q : std_logic_vector(13 downto 0); --ISERDESE2 can do 1:14 at most
begin
-- Differential input buffer for TMDS I/O standard
InputBuffer: IBUFDS
generic map (
DIFF_TERM => FALSE,
IOSTANDARD => "TMDS_33")
port map (
I => sDataIn_p,
IB => sDataIn_n,
O => sDataIn);
-- Delay element for phase alignment of serial data
InputDelay: IDELAYE2
generic map (
CINVCTRL_SEL => "FALSE", -- TRUE, FALSE
DELAY_SRC => "IDATAIN", -- IDATAIN, DATAIN
HIGH_PERFORMANCE_MODE => "TRUE", -- TRUE, FALSE
IDELAY_TYPE => "VARIABLE", -- FIXED, VARIABLE, or VAR_LOADABLE
IDELAY_VALUE => 0, -- 0 to 31
REFCLK_FREQUENCY => 200.0,
PIPE_SEL => "FALSE",
SIGNAL_PATTERN => "DATA") -- CLOCK, DATA
port map (
DATAOUT => sDataInDly, -- Delayed signal
DATAIN => '0', -- Not used; IDATAIN instead
C => PixelClk, -- Clock for control signals (CE,INC...)
CE => pIDLY_CE,
INC => pIDLY_INC,
IDATAIN => sDataIn, -- Driven by IOB
LD => pIDLY_LD,
REGRST => '0', --not used in VARIABLE mode
LDPIPEEN => '0',
CNTVALUEIN => "00000", --not used in VARIABLE mode
CNTVALUEOUT => pIDLY_CNT, -- current tap value
CINVCTRL => '0');
--Invert locally for ISERDESE2
SerialClkInv <= not SerialClk;
-- De-serializer, 1:10 (1:5 DDR), master-slave cascaded
DeserializerMaster: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => kParallelWidth,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "MASTER")
port map (
Q1 => pDataIn_q(0),
Q2 => pDataIn_q(1),
Q3 => pDataIn_q(2),
Q4 => pDataIn_q(3),
Q5 => pDataIn_q(4),
Q6 => pDataIn_q(5),
Q7 => pDataIn_q(6),
Q8 => pDataIn_q(7),
SHIFTOUT1 => icascade1, -- Cascade connection to Slave ISERDES
SHIFTOUT2 => icascade2, -- Cascade connection to Slave ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => sDataInDly, -- 1-bit Input signal from IODELAYE1.
RST => aRst, -- 1-bit Asynchronous reset only.
SHIFTIN1 => '0',
SHIFTIN2 => '0',
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
DeserializerSlave: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 10,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "SLAVE")
port map (
Q1 => open, --not used in cascaded mode
Q2 => open, --not used in cascaded mode
Q3 => pDataIn_q(8),
Q4 => pDataIn_q(9),
Q5 => pDataIn_q(10),
Q6 => pDataIn_q(11),
Q7 => pDataIn_q(12),
Q8 => pDataIn_q(13),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTIN1 => icascade1, -- Cascade connections from Master ISERDES
SHIFTIN2 => icascade2,-- Cascade connections from Master ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => '0', -- not used in cascaded Slave mode
RST => aRst, -- 1-bit Asynchronous reset only.
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
-------------------------------------------------------------
-- Concatenate the serdes outputs together. Keep the timesliced
-- bits together, and placing the earliest bits on the right
-- ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
-- the output will be 3210, 7654, ...
-------------------------------------------------------------
SliceISERDES_q: for slice_count in 0 to kParallelWidth-1 generate begin
--DVI sends least significant bit first
-- This places the first data in time on the right
pDataIn(slice_count) <= pDataIn_q(kParallelWidth-slice_count-1);
end generate SliceISERDES_q;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: InputSERDES.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates the Xilinx 7-series primitives necessary for
-- de-serializing the TMDS data stream.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity InputSERDES is
Generic (
kIDLY_TapWidth : natural := 5; -- number of bits for IDELAYE2 tap counter
kParallelWidth : natural := 10); -- number of parallel bits
Port (
PixelClk : in std_logic; --Recovered TMDS clock x1 (CLKDIV)
SerialClk : in std_logic; --Recovered TMDS clock x5 (CLK)
--Encoded serial data
sDataIn_p : in std_logic; --TMDS data channel positive
sDataIn_n : in std_logic; --TMDS data channel negative
--Encoded parallel data (raw)
pDataIn : out STD_LOGIC_VECTOR (kParallelWidth-1 downto 0);
--Control for phase alignment
pBitslip : in STD_LOGIC; --Bitslip for ISERDESE2
pIDLY_LD : in STD_LOGIC; --IDELAYE2 Load
pIDLY_CE : in STD_LOGIC; --IDELAYE2 CE
pIDLY_INC : in STD_LOGIC; --IDELAYE2 Tap Increment
pIDLY_CNT : out std_logic_vector(kIDLY_TapWidth-1 downto 0); --IDELAYE2 Current Tap Count
aRst : in STD_LOGIC
);
end InputSERDES;
architecture Behavioral of InputSERDES is
signal sDataIn, sDataInDly, icascade1, icascade2, SerialClkInv : std_logic;
signal pDataIn_q : std_logic_vector(13 downto 0); --ISERDESE2 can do 1:14 at most
begin
-- Differential input buffer for TMDS I/O standard
InputBuffer: IBUFDS
generic map (
DIFF_TERM => FALSE,
IOSTANDARD => "TMDS_33")
port map (
I => sDataIn_p,
IB => sDataIn_n,
O => sDataIn);
-- Delay element for phase alignment of serial data
InputDelay: IDELAYE2
generic map (
CINVCTRL_SEL => "FALSE", -- TRUE, FALSE
DELAY_SRC => "IDATAIN", -- IDATAIN, DATAIN
HIGH_PERFORMANCE_MODE => "TRUE", -- TRUE, FALSE
IDELAY_TYPE => "VARIABLE", -- FIXED, VARIABLE, or VAR_LOADABLE
IDELAY_VALUE => 0, -- 0 to 31
REFCLK_FREQUENCY => 200.0,
PIPE_SEL => "FALSE",
SIGNAL_PATTERN => "DATA") -- CLOCK, DATA
port map (
DATAOUT => sDataInDly, -- Delayed signal
DATAIN => '0', -- Not used; IDATAIN instead
C => PixelClk, -- Clock for control signals (CE,INC...)
CE => pIDLY_CE,
INC => pIDLY_INC,
IDATAIN => sDataIn, -- Driven by IOB
LD => pIDLY_LD,
REGRST => '0', --not used in VARIABLE mode
LDPIPEEN => '0',
CNTVALUEIN => "00000", --not used in VARIABLE mode
CNTVALUEOUT => pIDLY_CNT, -- current tap value
CINVCTRL => '0');
--Invert locally for ISERDESE2
SerialClkInv <= not SerialClk;
-- De-serializer, 1:10 (1:5 DDR), master-slave cascaded
DeserializerMaster: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => kParallelWidth,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "MASTER")
port map (
Q1 => pDataIn_q(0),
Q2 => pDataIn_q(1),
Q3 => pDataIn_q(2),
Q4 => pDataIn_q(3),
Q5 => pDataIn_q(4),
Q6 => pDataIn_q(5),
Q7 => pDataIn_q(6),
Q8 => pDataIn_q(7),
SHIFTOUT1 => icascade1, -- Cascade connection to Slave ISERDES
SHIFTOUT2 => icascade2, -- Cascade connection to Slave ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => sDataInDly, -- 1-bit Input signal from IODELAYE1.
RST => aRst, -- 1-bit Asynchronous reset only.
SHIFTIN1 => '0',
SHIFTIN2 => '0',
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
DeserializerSlave: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 10,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "SLAVE")
port map (
Q1 => open, --not used in cascaded mode
Q2 => open, --not used in cascaded mode
Q3 => pDataIn_q(8),
Q4 => pDataIn_q(9),
Q5 => pDataIn_q(10),
Q6 => pDataIn_q(11),
Q7 => pDataIn_q(12),
Q8 => pDataIn_q(13),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTIN1 => icascade1, -- Cascade connections from Master ISERDES
SHIFTIN2 => icascade2,-- Cascade connections from Master ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => '0', -- not used in cascaded Slave mode
RST => aRst, -- 1-bit Asynchronous reset only.
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
-------------------------------------------------------------
-- Concatenate the serdes outputs together. Keep the timesliced
-- bits together, and placing the earliest bits on the right
-- ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
-- the output will be 3210, 7654, ...
-------------------------------------------------------------
SliceISERDES_q: for slice_count in 0 to kParallelWidth-1 generate begin
--DVI sends least significant bit first
-- This places the first data in time on the right
pDataIn(slice_count) <= pDataIn_q(kParallelWidth-slice_count-1);
end generate SliceISERDES_q;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: InputSERDES.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates the Xilinx 7-series primitives necessary for
-- de-serializing the TMDS data stream.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity InputSERDES is
Generic (
kIDLY_TapWidth : natural := 5; -- number of bits for IDELAYE2 tap counter
kParallelWidth : natural := 10); -- number of parallel bits
Port (
PixelClk : in std_logic; --Recovered TMDS clock x1 (CLKDIV)
SerialClk : in std_logic; --Recovered TMDS clock x5 (CLK)
--Encoded serial data
sDataIn_p : in std_logic; --TMDS data channel positive
sDataIn_n : in std_logic; --TMDS data channel negative
--Encoded parallel data (raw)
pDataIn : out STD_LOGIC_VECTOR (kParallelWidth-1 downto 0);
--Control for phase alignment
pBitslip : in STD_LOGIC; --Bitslip for ISERDESE2
pIDLY_LD : in STD_LOGIC; --IDELAYE2 Load
pIDLY_CE : in STD_LOGIC; --IDELAYE2 CE
pIDLY_INC : in STD_LOGIC; --IDELAYE2 Tap Increment
pIDLY_CNT : out std_logic_vector(kIDLY_TapWidth-1 downto 0); --IDELAYE2 Current Tap Count
aRst : in STD_LOGIC
);
end InputSERDES;
architecture Behavioral of InputSERDES is
signal sDataIn, sDataInDly, icascade1, icascade2, SerialClkInv : std_logic;
signal pDataIn_q : std_logic_vector(13 downto 0); --ISERDESE2 can do 1:14 at most
begin
-- Differential input buffer for TMDS I/O standard
InputBuffer: IBUFDS
generic map (
DIFF_TERM => FALSE,
IOSTANDARD => "TMDS_33")
port map (
I => sDataIn_p,
IB => sDataIn_n,
O => sDataIn);
-- Delay element for phase alignment of serial data
InputDelay: IDELAYE2
generic map (
CINVCTRL_SEL => "FALSE", -- TRUE, FALSE
DELAY_SRC => "IDATAIN", -- IDATAIN, DATAIN
HIGH_PERFORMANCE_MODE => "TRUE", -- TRUE, FALSE
IDELAY_TYPE => "VARIABLE", -- FIXED, VARIABLE, or VAR_LOADABLE
IDELAY_VALUE => 0, -- 0 to 31
REFCLK_FREQUENCY => 200.0,
PIPE_SEL => "FALSE",
SIGNAL_PATTERN => "DATA") -- CLOCK, DATA
port map (
DATAOUT => sDataInDly, -- Delayed signal
DATAIN => '0', -- Not used; IDATAIN instead
C => PixelClk, -- Clock for control signals (CE,INC...)
CE => pIDLY_CE,
INC => pIDLY_INC,
IDATAIN => sDataIn, -- Driven by IOB
LD => pIDLY_LD,
REGRST => '0', --not used in VARIABLE mode
LDPIPEEN => '0',
CNTVALUEIN => "00000", --not used in VARIABLE mode
CNTVALUEOUT => pIDLY_CNT, -- current tap value
CINVCTRL => '0');
--Invert locally for ISERDESE2
SerialClkInv <= not SerialClk;
-- De-serializer, 1:10 (1:5 DDR), master-slave cascaded
DeserializerMaster: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => kParallelWidth,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "MASTER")
port map (
Q1 => pDataIn_q(0),
Q2 => pDataIn_q(1),
Q3 => pDataIn_q(2),
Q4 => pDataIn_q(3),
Q5 => pDataIn_q(4),
Q6 => pDataIn_q(5),
Q7 => pDataIn_q(6),
Q8 => pDataIn_q(7),
SHIFTOUT1 => icascade1, -- Cascade connection to Slave ISERDES
SHIFTOUT2 => icascade2, -- Cascade connection to Slave ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => sDataInDly, -- 1-bit Input signal from IODELAYE1.
RST => aRst, -- 1-bit Asynchronous reset only.
SHIFTIN1 => '0',
SHIFTIN2 => '0',
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
DeserializerSlave: ISERDESE2
generic map (
DATA_RATE => "DDR",
DATA_WIDTH => 10,
INTERFACE_TYPE => "NETWORKING",
DYN_CLKDIV_INV_EN => "FALSE",
DYN_CLK_INV_EN => "FALSE",
NUM_CE => 2,
OFB_USED => "FALSE",
IOBDELAY => "IFD", -- Use input at DDLY to output the data on Q1-Q6
SERDES_MODE => "SLAVE")
port map (
Q1 => open, --not used in cascaded mode
Q2 => open, --not used in cascaded mode
Q3 => pDataIn_q(8),
Q4 => pDataIn_q(9),
Q5 => pDataIn_q(10),
Q6 => pDataIn_q(11),
Q7 => pDataIn_q(12),
Q8 => pDataIn_q(13),
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTIN1 => icascade1, -- Cascade connections from Master ISERDES
SHIFTIN2 => icascade2,-- Cascade connections from Master ISERDES
BITSLIP => pBitslip, -- 1-bit Invoke Bitslip. This can be used with any
CE1 => '1', -- 1-bit Clock enable input
CE2 => '1', -- 1-bit Clock enable input
CLK => SerialClk, -- Fast Source Synchronous SERDES clock from BUFIO
CLKB => SerialClkInv, -- Locally inverted clock
CLKDIV => PixelClk, -- Slow clock driven by BUFR
CLKDIVP => '0', --Not used here
D => '0',
DDLY => '0', -- not used in cascaded Slave mode
RST => aRst, -- 1-bit Asynchronous reset only.
-- unused connections
DYNCLKDIVSEL => '0',
DYNCLKSEL => '0',
OFB => '0',
OCLK => '0',
OCLKB => '0',
O => open); -- unregistered output of ISERDESE1
-------------------------------------------------------------
-- Concatenate the serdes outputs together. Keep the timesliced
-- bits together, and placing the earliest bits on the right
-- ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
-- the output will be 3210, 7654, ...
-------------------------------------------------------------
SliceISERDES_q: for slice_count in 0 to kParallelWidth-1 generate begin
--DVI sends least significant bit first
-- This places the first data in time on the right
pDataIn(slice_count) <= pDataIn_q(kParallelWidth-slice_count-1);
end generate SliceISERDES_q;
end Behavioral;
|
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Mon Feb 20 13:51:56 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target affine_block.bd
--Design : affine_block
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block is
port (
a00 : in STD_LOGIC_VECTOR ( 31 downto 0 );
a01 : in STD_LOGIC_VECTOR ( 31 downto 0 );
a10 : in STD_LOGIC_VECTOR ( 31 downto 0 );
a11 : in STD_LOGIC_VECTOR ( 31 downto 0 );
x_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_out : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of affine_block : entity is "affine_block,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=affine_block,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=10,numReposBlks=10,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of affine_block : entity is "affine_block.hwdef";
end affine_block;
architecture STRUCTURE of affine_block is
component affine_block_uint_to_ieee754_fp_0_0 is
port (
x : in STD_LOGIC_VECTOR ( 9 downto 0 );
y : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component affine_block_uint_to_ieee754_fp_0_0;
component affine_block_uint_to_ieee754_fp_0_1 is
port (
x : in STD_LOGIC_VECTOR ( 9 downto 0 );
y : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component affine_block_uint_to_ieee754_fp_0_1;
component affine_block_ieee754_fp_multiplier_0_0 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component affine_block_ieee754_fp_multiplier_0_0;
component affine_block_ieee754_fp_multiplier_1_0 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component affine_block_ieee754_fp_multiplier_1_0;
component affine_block_ieee754_fp_multiplier_1_1 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component affine_block_ieee754_fp_multiplier_1_1;
component affine_block_ieee754_fp_multiplier_1_2 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component affine_block_ieee754_fp_multiplier_1_2;
component affine_block_ieee754_fp_adder_subtractor_0_0 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component affine_block_ieee754_fp_adder_subtractor_0_0;
component affine_block_ieee754_fp_adder_subtractor_0_1 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component affine_block_ieee754_fp_adder_subtractor_0_1;
component affine_block_ieee754_fp_to_uint_0_0 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component affine_block_ieee754_fp_to_uint_0_0;
component affine_block_ieee754_fp_to_uint_0_1 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component affine_block_ieee754_fp_to_uint_0_1;
signal ieee754_fp_adder_subtractor_0_z : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ieee754_fp_adder_subtractor_1_z : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ieee754_fp_multiplier_0_z : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ieee754_fp_multiplier_1_z : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ieee754_fp_multiplier_2_z : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ieee754_fp_multiplier_3_z : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ieee754_fp_to_uint_0_y : STD_LOGIC_VECTOR ( 9 downto 0 );
signal ieee754_fp_to_uint_1_y : STD_LOGIC_VECTOR ( 9 downto 0 );
signal uint_to_ieee754_fp_0_y : STD_LOGIC_VECTOR ( 31 downto 0 );
signal uint_to_ieee754_fp_1_y : STD_LOGIC_VECTOR ( 31 downto 0 );
signal x_1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal x_2 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal y_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal y_2 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal y_3 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal y_4 : STD_LOGIC_VECTOR ( 31 downto 0 );
begin
x_1(9 downto 0) <= x_in(9 downto 0);
x_2(9 downto 0) <= y_in(9 downto 0);
x_out(9 downto 0) <= ieee754_fp_to_uint_0_y(9 downto 0);
y_1(31 downto 0) <= a00(31 downto 0);
y_2(31 downto 0) <= a01(31 downto 0);
y_3(31 downto 0) <= a10(31 downto 0);
y_4(31 downto 0) <= a11(31 downto 0);
y_out(9 downto 0) <= ieee754_fp_to_uint_1_y(9 downto 0);
ieee754_fp_adder_subtractor_0: component affine_block_ieee754_fp_adder_subtractor_0_0
port map (
x(31 downto 0) => ieee754_fp_multiplier_0_z(31 downto 0),
y(31 downto 0) => ieee754_fp_multiplier_1_z(31 downto 0),
z(31 downto 0) => ieee754_fp_adder_subtractor_0_z(31 downto 0)
);
ieee754_fp_adder_subtractor_1: component affine_block_ieee754_fp_adder_subtractor_0_1
port map (
x(31 downto 0) => ieee754_fp_multiplier_2_z(31 downto 0),
y(31 downto 0) => ieee754_fp_multiplier_3_z(31 downto 0),
z(31 downto 0) => ieee754_fp_adder_subtractor_1_z(31 downto 0)
);
ieee754_fp_multiplier_0: component affine_block_ieee754_fp_multiplier_0_0
port map (
x(31 downto 0) => uint_to_ieee754_fp_0_y(31 downto 0),
y(31 downto 0) => y_1(31 downto 0),
z(31 downto 0) => ieee754_fp_multiplier_0_z(31 downto 0)
);
ieee754_fp_multiplier_1: component affine_block_ieee754_fp_multiplier_1_0
port map (
x(31 downto 0) => uint_to_ieee754_fp_1_y(31 downto 0),
y(31 downto 0) => y_2(31 downto 0),
z(31 downto 0) => ieee754_fp_multiplier_1_z(31 downto 0)
);
ieee754_fp_multiplier_2: component affine_block_ieee754_fp_multiplier_1_1
port map (
x(31 downto 0) => uint_to_ieee754_fp_0_y(31 downto 0),
y(31 downto 0) => y_3(31 downto 0),
z(31 downto 0) => ieee754_fp_multiplier_2_z(31 downto 0)
);
ieee754_fp_multiplier_3: component affine_block_ieee754_fp_multiplier_1_2
port map (
x(31 downto 0) => uint_to_ieee754_fp_1_y(31 downto 0),
y(31 downto 0) => y_4(31 downto 0),
z(31 downto 0) => ieee754_fp_multiplier_3_z(31 downto 0)
);
ieee754_fp_to_uint_0: component affine_block_ieee754_fp_to_uint_0_0
port map (
x(31 downto 0) => ieee754_fp_adder_subtractor_0_z(31 downto 0),
y(9 downto 0) => ieee754_fp_to_uint_0_y(9 downto 0)
);
ieee754_fp_to_uint_1: component affine_block_ieee754_fp_to_uint_0_1
port map (
x(31 downto 0) => ieee754_fp_adder_subtractor_1_z(31 downto 0),
y(9 downto 0) => ieee754_fp_to_uint_1_y(9 downto 0)
);
uint_to_ieee754_fp_0: component affine_block_uint_to_ieee754_fp_0_0
port map (
x(9 downto 0) => x_1(9 downto 0),
y(31 downto 0) => uint_to_ieee754_fp_0_y(31 downto 0)
);
uint_to_ieee754_fp_1: component affine_block_uint_to_ieee754_fp_0_1
port map (
x(9 downto 0) => x_2(9 downto 0),
y(31 downto 0) => uint_to_ieee754_fp_1_y(31 downto 0)
);
end STRUCTURE;
|
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Mon Feb 20 13:51:56 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target affine_block.bd
--Design : affine_block
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block is
port (
a00 : in STD_LOGIC_VECTOR ( 31 downto 0 );
a01 : in STD_LOGIC_VECTOR ( 31 downto 0 );
a10 : in STD_LOGIC_VECTOR ( 31 downto 0 );
a11 : in STD_LOGIC_VECTOR ( 31 downto 0 );
x_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_out : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of affine_block : entity is "affine_block,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=affine_block,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=10,numReposBlks=10,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of affine_block : entity is "affine_block.hwdef";
end affine_block;
architecture STRUCTURE of affine_block is
component affine_block_uint_to_ieee754_fp_0_0 is
port (
x : in STD_LOGIC_VECTOR ( 9 downto 0 );
y : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component affine_block_uint_to_ieee754_fp_0_0;
component affine_block_uint_to_ieee754_fp_0_1 is
port (
x : in STD_LOGIC_VECTOR ( 9 downto 0 );
y : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component affine_block_uint_to_ieee754_fp_0_1;
component affine_block_ieee754_fp_multiplier_0_0 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component affine_block_ieee754_fp_multiplier_0_0;
component affine_block_ieee754_fp_multiplier_1_0 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component affine_block_ieee754_fp_multiplier_1_0;
component affine_block_ieee754_fp_multiplier_1_1 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component affine_block_ieee754_fp_multiplier_1_1;
component affine_block_ieee754_fp_multiplier_1_2 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component affine_block_ieee754_fp_multiplier_1_2;
component affine_block_ieee754_fp_adder_subtractor_0_0 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component affine_block_ieee754_fp_adder_subtractor_0_0;
component affine_block_ieee754_fp_adder_subtractor_0_1 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component affine_block_ieee754_fp_adder_subtractor_0_1;
component affine_block_ieee754_fp_to_uint_0_0 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component affine_block_ieee754_fp_to_uint_0_0;
component affine_block_ieee754_fp_to_uint_0_1 is
port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component affine_block_ieee754_fp_to_uint_0_1;
signal ieee754_fp_adder_subtractor_0_z : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ieee754_fp_adder_subtractor_1_z : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ieee754_fp_multiplier_0_z : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ieee754_fp_multiplier_1_z : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ieee754_fp_multiplier_2_z : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ieee754_fp_multiplier_3_z : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ieee754_fp_to_uint_0_y : STD_LOGIC_VECTOR ( 9 downto 0 );
signal ieee754_fp_to_uint_1_y : STD_LOGIC_VECTOR ( 9 downto 0 );
signal uint_to_ieee754_fp_0_y : STD_LOGIC_VECTOR ( 31 downto 0 );
signal uint_to_ieee754_fp_1_y : STD_LOGIC_VECTOR ( 31 downto 0 );
signal x_1 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal x_2 : STD_LOGIC_VECTOR ( 9 downto 0 );
signal y_1 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal y_2 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal y_3 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal y_4 : STD_LOGIC_VECTOR ( 31 downto 0 );
begin
x_1(9 downto 0) <= x_in(9 downto 0);
x_2(9 downto 0) <= y_in(9 downto 0);
x_out(9 downto 0) <= ieee754_fp_to_uint_0_y(9 downto 0);
y_1(31 downto 0) <= a00(31 downto 0);
y_2(31 downto 0) <= a01(31 downto 0);
y_3(31 downto 0) <= a10(31 downto 0);
y_4(31 downto 0) <= a11(31 downto 0);
y_out(9 downto 0) <= ieee754_fp_to_uint_1_y(9 downto 0);
ieee754_fp_adder_subtractor_0: component affine_block_ieee754_fp_adder_subtractor_0_0
port map (
x(31 downto 0) => ieee754_fp_multiplier_0_z(31 downto 0),
y(31 downto 0) => ieee754_fp_multiplier_1_z(31 downto 0),
z(31 downto 0) => ieee754_fp_adder_subtractor_0_z(31 downto 0)
);
ieee754_fp_adder_subtractor_1: component affine_block_ieee754_fp_adder_subtractor_0_1
port map (
x(31 downto 0) => ieee754_fp_multiplier_2_z(31 downto 0),
y(31 downto 0) => ieee754_fp_multiplier_3_z(31 downto 0),
z(31 downto 0) => ieee754_fp_adder_subtractor_1_z(31 downto 0)
);
ieee754_fp_multiplier_0: component affine_block_ieee754_fp_multiplier_0_0
port map (
x(31 downto 0) => uint_to_ieee754_fp_0_y(31 downto 0),
y(31 downto 0) => y_1(31 downto 0),
z(31 downto 0) => ieee754_fp_multiplier_0_z(31 downto 0)
);
ieee754_fp_multiplier_1: component affine_block_ieee754_fp_multiplier_1_0
port map (
x(31 downto 0) => uint_to_ieee754_fp_1_y(31 downto 0),
y(31 downto 0) => y_2(31 downto 0),
z(31 downto 0) => ieee754_fp_multiplier_1_z(31 downto 0)
);
ieee754_fp_multiplier_2: component affine_block_ieee754_fp_multiplier_1_1
port map (
x(31 downto 0) => uint_to_ieee754_fp_0_y(31 downto 0),
y(31 downto 0) => y_3(31 downto 0),
z(31 downto 0) => ieee754_fp_multiplier_2_z(31 downto 0)
);
ieee754_fp_multiplier_3: component affine_block_ieee754_fp_multiplier_1_2
port map (
x(31 downto 0) => uint_to_ieee754_fp_1_y(31 downto 0),
y(31 downto 0) => y_4(31 downto 0),
z(31 downto 0) => ieee754_fp_multiplier_3_z(31 downto 0)
);
ieee754_fp_to_uint_0: component affine_block_ieee754_fp_to_uint_0_0
port map (
x(31 downto 0) => ieee754_fp_adder_subtractor_0_z(31 downto 0),
y(9 downto 0) => ieee754_fp_to_uint_0_y(9 downto 0)
);
ieee754_fp_to_uint_1: component affine_block_ieee754_fp_to_uint_0_1
port map (
x(31 downto 0) => ieee754_fp_adder_subtractor_1_z(31 downto 0),
y(9 downto 0) => ieee754_fp_to_uint_1_y(9 downto 0)
);
uint_to_ieee754_fp_0: component affine_block_uint_to_ieee754_fp_0_0
port map (
x(9 downto 0) => x_1(9 downto 0),
y(31 downto 0) => uint_to_ieee754_fp_0_y(31 downto 0)
);
uint_to_ieee754_fp_1: component affine_block_uint_to_ieee754_fp_0_1
port map (
x(9 downto 0) => x_2(9 downto 0),
y(31 downto 0) => uint_to_ieee754_fp_1_y(31 downto 0)
);
end STRUCTURE;
|
entity test is
type test1 is (foo);
subtype test2 is test.test1;
begin end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity shift is
port ( mode : in std_logic_vector (1 downto 0);--0:LSLS 1:LSRS 2:ASRS 3:RORS
shift : in std_logic_vector (4 downto 0);
input : in std_logic_vector (31 downto 0);
carry : out std_logic;
output : out std_logic_vector (31 downto 0));
end shift;
architecture Behavioral of shift is
signal R1s : std_logic_vector(31 downto 0);
signal R2s : std_logic_vector(31 downto 0);
signal R4s : std_logic_vector(31 downto 0);
signal R8s : std_logic_vector(31 downto 0);
signal R16s : std_logic_vector(31 downto 0);
signal R1 : std_logic_vector(31 downto 0);
signal R2 : std_logic_vector(31 downto 0);
signal R4 : std_logic_vector(31 downto 0);
signal R8 : std_logic_vector(31 downto 0);
signal R16 : std_logic_vector(31 downto 0);
signal input1s : std_logic;
signal input2s : std_logic_vector(1 downto 0);
signal input4s : std_logic_vector(3 downto 0);
signal input8s : std_logic_vector(7 downto 0);
signal input16s : std_logic_vector(15 downto 0);
begin
carry <= '0' when shift = "0000" else '1';
--input(32 - conv_integer(shift)) when mode = "00" else
--input(conv_integer(shift) - 1);
input1s <= input(31) when mode = "10" else
input(0) when mode = "11" else
'0';
R1s <= input(30 downto 0) & input1s when mode = "00" else
input1s & input(31 downto 1);
input2s <= R1(1 downto 0) when mode = "11" else input1s & input1s;
R2s <= R1(29 downto 0) & input2s when mode = "00" else
input2s & R1(31 downto 2);
input4s <= R2(3 downto 0) when mode = "11" else input2s & input2s;
R4s <= R2(27 downto 0) & input4s when mode = "00" else
input4s & R2(31 downto 4);
input8s <= R4(7 downto 0) when mode = "11" else input4s & input4s;
R8s <= R4(23 downto 0) & input8s when mode = "00" else
input8s & R4(31 downto 8);
input16s <= R8(15 downto 0) when mode = "11" else input8s & input8s;
R16s <= R8(15 downto 0) & input16s when mode = "00" else
input16s & R8(31 downto 16);
R1 <= input when shift(0) = '0' else R1s;
R2 <= R1 when shift(1) = '0' else R2s;
R4 <= R2 when shift(2) = '0' else R4s;
R8 <= R4 when shift(3) = '0' else R8s;
output <= R8 when shift(4) = '0' else R16s;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1382.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01382ent IS
END c08s05b00x00p03n01i01382ent;
ARCHITECTURE c08s05b00x00p03n01i01382arch OF c08s05b00x00p03n01i01382ent IS
BEGIN
TESTING: PROCESS
variable v1 : integer := 0;
BEGIN
ch0805_p00301_28_ent := v1; -- illegal name target
assert FALSE
report "***FAILED TEST: c08s05b00x00p03n01i01382 - Target of a variable assignment can not be the name of a design entity."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01382arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1382.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01382ent IS
END c08s05b00x00p03n01i01382ent;
ARCHITECTURE c08s05b00x00p03n01i01382arch OF c08s05b00x00p03n01i01382ent IS
BEGIN
TESTING: PROCESS
variable v1 : integer := 0;
BEGIN
ch0805_p00301_28_ent := v1; -- illegal name target
assert FALSE
report "***FAILED TEST: c08s05b00x00p03n01i01382 - Target of a variable assignment can not be the name of a design entity."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01382arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1382.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01382ent IS
END c08s05b00x00p03n01i01382ent;
ARCHITECTURE c08s05b00x00p03n01i01382arch OF c08s05b00x00p03n01i01382ent IS
BEGIN
TESTING: PROCESS
variable v1 : integer := 0;
BEGIN
ch0805_p00301_28_ent := v1; -- illegal name target
assert FALSE
report "***FAILED TEST: c08s05b00x00p03n01i01382 - Target of a variable assignment can not be the name of a design entity."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01382arch;
|
-- VHDL Entity R6502_TC.fsm_core_V2_0.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 19:06:55 08.04.2008
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity fsm_core_V2_0 is
port(
adr_nxt_pc_i : in std_logic_vector (15 downto 0);
adr_nxt_sp_i : in std_logic_vector (15 downto 0);
adr_pc_i : in std_logic_vector (15 downto 0);
adr_sp_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic;
cout_pc_i : in std_logic;
d_alu_i : in std_logic_vector ( 7 downto 0 );
d_i : in std_logic_vector ( 7 downto 0 );
d_regs_out_i : in std_logic_vector ( 7 downto 0 );
irq_n_i : in std_logic;
nmi_i : in std_logic;
q_a_i : in std_logic_vector ( 7 downto 0 );
q_x_i : in std_logic_vector ( 7 downto 0 );
q_y_i : in std_logic_vector ( 7 downto 0 );
rdy_i : in std_logic;
reg_0flag_i : in std_logic;
reg_1flag_i : in std_logic;
reg_6flag_i : in std_logic;
reg_7flag_i : in std_logic;
rst_rst_n_i : in std_logic;
so_n_i : in std_logic;
a_o : out std_logic_vector (15 downto 0);
adr_o : out std_logic_vector (15 downto 0);
ch_a_o : out std_logic_vector ( 7 downto 0 );
ch_b_o : out std_logic_vector ( 7 downto 0 );
d_o : out std_logic_vector ( 7 downto 0 );
d_regs_in_o : out std_logic_vector ( 7 downto 0 );
ld_o : out std_logic_vector ( 1 downto 0 );
ld_pc_o : out std_logic;
ld_sp_o : out std_logic;
load_regs_o : out std_logic;
offset_o : out std_logic_vector ( 15 downto 0 );
rd_o : out std_logic;
reg_0flag_o : out std_logic;
reg_1flag_o : out std_logic;
reg_3flag_o : out std_logic;
reg_7flag_o : out std_logic;
sync_o : out std_logic;
wr_n_o : out std_logic;
wr_o : out std_logic;
sel_alu_as_o_i : inout std_logic;
sel_alu_out_o_i : inout std_logic_vector ( 2 downto 0 );
sel_pc_as_o_i : inout std_logic;
sel_pc_in_o_i : inout std_logic_vector ( 1 downto 0 );
sel_pc_val_o_i : inout std_logic_vector ( 1 downto 0 );
sel_rb_in_o_i : inout std_logic_vector ( 2 downto 0 );
sel_rb_out_o_i : inout std_logic_vector ( 2 downto 0 );
sel_reg_o_i : inout std_logic_vector ( 1 downto 0 );
sel_sp_as_o_i : inout std_logic;
sel_sp_in_o_i : inout std_logic_vector ( 1 downto 0 );
sel_sp_val_o_i : inout std_logic_vector ( 1 downto 0 )
);
-- Declarations
end fsm_core_V2_0 ;
-- Jens-D. Gutschmidt Project: R6502_TC
-- [email protected]
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- CVS Revisins History
--
-- $Log: not supported by cvs2svn $
--
-- Title: FSM for all op codes
-- Path: R6502_TC/fsm_core_V2_0/fsm
-- Edited: by eda on 08 Apr 2008
--
-- VHDL Architecture R6502_TC.fsm_core_V2_0.fsm
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 19:06:56 08.04.2008
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
architecture fsm of fsm_core_V2_0 is
-- Architecture Declarations
signal reg_F : std_logic_vector( 7 DOWNTO 0 );
signal reg_PC : std_logic_vector(15 DOWNTO 0);
signal reg_PC1 : std_logic_vector( 15 DOWNTO 0 );
signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 );
signal sig_PC : std_logic_vector(15 DOWNTO 0);
signal sig_RD : std_logic;
signal sig_RWn : std_logic;
signal sig_SYNC : std_logic;
signal sig_WR : std_logic;
signal zw_ALU : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU1 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU2 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU3 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU4 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU5 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU6 : std_logic_vector( 8 DOWNTO 0 );
signal zw_PC : std_logic_vector( 15 DOWNTO 0 );
signal zw_REG_ALU : std_logic_vector( 8 DOWNTO 0 );
signal zw_REG_NMI : std_logic;
signal zw_REG_OP : std_logic_vector( 7 DOWNTO 0 );
signal zw_REG_sig_PC : std_logic_vector(15 DOWNTO 0);
signal zw_b1 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b2 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b3 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b4 : std_logic_vector( 7 DOWNTO 0 );
signal zw_w1 : std_logic_vector( 15 DOWNTO 0 );
signal zw_w2 : std_logic_vector( 15 DOWNTO 0 );
signal zw_w3 : std_logic_vector( 15 DOWNTO 0 );
subtype state_type is
std_logic_vector(7 downto 0);
-- State vector declaration
attribute state_vector : string;
attribute state_vector of fsm : architecture is "current_state";
-- Hard encoding
constant FETCH : state_type := "00000000";
constant s1 : state_type := "00000001";
constant s2 : state_type := "00000011";
constant s5 : state_type := "00000010";
constant s3 : state_type := "00000110";
constant s4 : state_type := "00000111";
constant s12 : state_type := "00000101";
constant s16 : state_type := "00000100";
constant s17 : state_type := "00001100";
constant s24 : state_type := "00001101";
constant s25 : state_type := "00001111";
constant s271 : state_type := "00001110";
constant s273 : state_type := "00001010";
constant s304 : state_type := "00001011";
constant s307 : state_type := "00001001";
constant s177 : state_type := "00001000";
constant s180 : state_type := "00011000";
constant s181 : state_type := "00011001";
constant s182 : state_type := "00011011";
constant s183 : state_type := "00011010";
constant s184 : state_type := "00011110";
constant s185 : state_type := "00011111";
constant s186 : state_type := "00011101";
constant s187 : state_type := "00011100";
constant s188 : state_type := "00010100";
constant s189 : state_type := "00010101";
constant s190 : state_type := "00010111";
constant s191 : state_type := "00010110";
constant s192 : state_type := "00010010";
constant s193 : state_type := "00010011";
constant s377 : state_type := "00010001";
constant s381 : state_type := "00010000";
constant s378 : state_type := "00110000";
constant s382 : state_type := "00110001";
constant s379 : state_type := "00110011";
constant s383 : state_type := "00110010";
constant s384 : state_type := "00110110";
constant s380 : state_type := "00110111";
constant s385 : state_type := "00110101";
constant s386 : state_type := "00110100";
constant s387 : state_type := "00111100";
constant s388 : state_type := "00111101";
constant s389 : state_type := "00111111";
constant s391 : state_type := "00111110";
constant s392 : state_type := "00111010";
constant s390 : state_type := "00111011";
constant s393 : state_type := "00111001";
constant s394 : state_type := "00111000";
constant s395 : state_type := "00101000";
constant s396 : state_type := "00101001";
constant s397 : state_type := "00101011";
constant s398 : state_type := "00101010";
constant s399 : state_type := "00101110";
constant s400 : state_type := "00101111";
constant s401 : state_type := "00101101";
constant s526 : state_type := "00101100";
constant s527 : state_type := "00100100";
constant s528 : state_type := "00100101";
constant s529 : state_type := "00100111";
constant s530 : state_type := "00100110";
constant s531 : state_type := "00100010";
constant s544 : state_type := "00100011";
constant s545 : state_type := "00100001";
constant s546 : state_type := "00100000";
constant s547 : state_type := "01100000";
constant s549 : state_type := "01100001";
constant s550 : state_type := "01100011";
constant s404 : state_type := "01100010";
constant s556 : state_type := "01100110";
constant s557 : state_type := "01100111";
constant s579 : state_type := "01100101";
constant s201 : state_type := "01100100";
constant s202 : state_type := "01101100";
constant s210 : state_type := "01101101";
constant s211 : state_type := "01101111";
constant s215 : state_type := "01101110";
constant s217 : state_type := "01101010";
constant s218 : state_type := "01101011";
constant s222 : state_type := "01101001";
constant s223 : state_type := "01101000";
constant s224 : state_type := "01111000";
constant s225 : state_type := "01111001";
constant s226 : state_type := "01111011";
constant s243 : state_type := "01111010";
constant s244 : state_type := "01111110";
constant s247 : state_type := "01111111";
constant s344 : state_type := "01111101";
constant s343 : state_type := "01111100";
constant s250 : state_type := "01110100";
constant s251 : state_type := "01110101";
constant s351 : state_type := "01110111";
constant s361 : state_type := "01110110";
constant s360 : state_type := "01110010";
constant s403 : state_type := "01110011";
constant s406 : state_type := "01110001";
constant s407 : state_type := "01110000";
constant s409 : state_type := "01010000";
constant s412 : state_type := "01010001";
constant s413 : state_type := "01010011";
constant s416 : state_type := "01010010";
constant s418 : state_type := "01010110";
constant s510 : state_type := "01010111";
constant s553 : state_type := "01010101";
constant s555 : state_type := "01010100";
constant s558 : state_type := "01011100";
constant s560 : state_type := "01011101";
constant s561 : state_type := "01011111";
constant s563 : state_type := "01011110";
constant s564 : state_type := "01011010";
constant s565 : state_type := "01011011";
constant s566 : state_type := "01011001";
constant s266 : state_type := "01011000";
constant s301 : state_type := "01001000";
constant s302 : state_type := "01001001";
constant RES : state_type := "01001011";
constant s511 : state_type := "01001010";
constant s559 : state_type := "01001110";
constant s562 : state_type := "01001111";
constant s567 : state_type := "01001101";
constant s568 : state_type := "01001100";
constant s569 : state_type := "01000100";
constant s570 : state_type := "01000101";
constant s571 : state_type := "01000111";
constant s572 : state_type := "01000110";
constant s573 : state_type := "01000010";
constant s574 : state_type := "01000011";
constant s548 : state_type := "01000001";
constant s551 : state_type := "01000000";
constant s552 : state_type := "11000000";
constant s575 : state_type := "11000001";
constant s576 : state_type := "11000011";
constant s577 : state_type := "11000010";
constant s532 : state_type := "11000110";
constant s533 : state_type := "11000111";
constant s534 : state_type := "11000101";
constant s535 : state_type := "11000100";
constant s536 : state_type := "11001100";
constant s537 : state_type := "11001101";
-- Declare current and next state signals
signal current_state : state_type;
signal next_state : state_type;
-- Declare any pre-registered internal signals
signal d_o_cld : std_logic_vector ( 7 downto 0 );
signal rd_o_cld : std_logic ;
signal sync_o_cld : std_logic ;
signal wr_n_o_cld : std_logic ;
signal wr_o_cld : std_logic ;
signal sel_alu_as_o_i_cld : std_logic ;
signal sel_alu_out_o_i_cld : std_logic_vector ( 2 downto 0 );
signal sel_pc_as_o_i_cld : std_logic ;
signal sel_pc_in_o_i_cld : std_logic_vector ( 1 downto 0 );
signal sel_pc_val_o_i_cld : std_logic_vector ( 1 downto 0 );
signal sel_rb_in_o_i_cld : std_logic_vector ( 2 downto 0 );
signal sel_rb_out_o_i_cld : std_logic_vector ( 2 downto 0 );
signal sel_reg_o_i_cld : std_logic_vector ( 1 downto 0 );
signal sel_sp_as_o_i_cld : std_logic ;
signal sel_sp_in_o_i_cld : std_logic_vector ( 1 downto 0 );
signal sel_sp_val_o_i_cld : std_logic_vector ( 1 downto 0 );
begin
-----------------------------------------------------------------
clocked_proc : process (
clk_clk_i,
rst_rst_n_i
)
-----------------------------------------------------------------
begin
if (rst_rst_n_i = '0') then
current_state <= RES;
-- Default Reset Values
d_o_cld <= X"00";
rd_o_cld <= '0';
sync_o_cld <= '0';
wr_n_o_cld <= '1';
wr_o_cld <= '0';
sel_alu_as_o_i_cld <= '0';
sel_alu_out_o_i_cld <= "000";
sel_pc_as_o_i_cld <= '0';
sel_pc_in_o_i_cld <= "00";
sel_pc_val_o_i_cld <= "00";
sel_rb_in_o_i_cld <= "000";
sel_rb_out_o_i_cld <= "000";
sel_reg_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '0';
sel_sp_in_o_i_cld <= "00";
sel_sp_val_o_i_cld <= "00";
reg_F <= "00000100";
reg_PC <= X"0000";
reg_PC1 <= X"0000";
sig_PC <= X"0000";
zw_PC <= X"0000";
zw_REG_ALU <= '0' & X"00";
zw_REG_NMI <= '0';
zw_REG_OP <= X"00";
zw_REG_sig_PC <= X"0000";
zw_b1 <= X"00";
zw_b2 <= X"00";
zw_b3 <= X"00";
zw_b4 <= X"00";
zw_w1 <= X"0000";
zw_w2 <= X"0000";
zw_w3 <= X"0000";
elsif (clk_clk_i'event and clk_clk_i = '1') then
current_state <= next_state;
-- Default Assignment To Internals
reg_F <= reg_F or ('0' & (not so_n_i) & "000000");
reg_PC <= reg_PC;
reg_PC1 <= reg_PC1;
sig_PC <= sig_PC;
zw_PC <= zw_PC;
zw_REG_ALU <= zw_REG_ALU;
zw_REG_NMI <= zw_REG_NMI or nmi_i;
zw_REG_OP <= zw_REG_OP;
zw_REG_sig_PC <= zw_REG_sig_PC;
zw_b1 <= zw_b1;
zw_b2 <= zw_b2;
zw_b3 <= zw_b3;
zw_b4 <= zw_b4;
zw_w1 <= zw_w1;
zw_w2 <= zw_w2;
zw_w3 <= zw_w3;
d_o_cld <= sig_D_OUT;
rd_o_cld <= sig_RD;
sync_o_cld <= sig_SYNC;
wr_n_o_cld <= sig_RWn;
wr_o_cld <= sig_WR;
sel_alu_as_o_i_cld <= sel_alu_as_o_i;
sel_alu_out_o_i_cld <= sel_alu_out_o_i;
sel_pc_as_o_i_cld <= sel_pc_as_o_i;
sel_pc_in_o_i_cld <= sel_pc_in_o_i;
sel_pc_val_o_i_cld <= sel_pc_val_o_i;
sel_rb_in_o_i_cld <= sel_rb_in_o_i;
sel_rb_out_o_i_cld <= sel_rb_out_o_i;
sel_reg_o_i_cld <= sel_reg_o_i;
sel_sp_as_o_i_cld <= sel_sp_as_o_i;
sel_sp_in_o_i_cld <= sel_sp_in_o_i;
sel_sp_val_o_i_cld <= sel_sp_val_o_i;
-- Combined Actions
case current_state is
when FETCH =>
zw_REG_OP <= d_i;
if ((zw_REG_NMI = '1') and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '0';
sel_sp_val_o_i_cld <= "00";
zw_REG_NMI <= '0';
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '0';
sel_sp_val_o_i_cld <= "00";
elsif ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sel_reg_o_i_cld <= "00";
sel_rb_in_o_i_cld <= "011";
zw_b1(0) <= reg_F(7);
elsif ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
zw_b3 <= adr_nxt_pc_i (15 downto 8);
elsif ((d_i = X"24" or
d_i = X"2C") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"00") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '0';
sel_sp_val_o_i_cld <= "00";
elsif ((d_i = X"18") and (rdy_i = '1')) then
elsif ((d_i = X"D8") and (rdy_i = '1')) then
elsif ((d_i = X"58") and (rdy_i = '1')) then
elsif ((d_i = X"B8") and (rdy_i = '1')) then
elsif ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "001";
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "010";
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") and (rdy_i = '1')) then
zw_b4 <= X"FF";
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"CA") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "001";
sel_reg_o_i_cld <= "01";
sel_rb_in_o_i_cld <= "011";
zw_b4 <= X"FF";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"88") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "010";
sel_reg_o_i_cld <= "10";
sel_rb_in_o_i_cld <= "011";
zw_b4 <= X"FF";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
d_i = X"5D" or
d_i = X"59" or
d_i = X"41" or
d_i = X"51" or
d_i = X"09" or
d_i = X"05" or
d_i = X"15" or
d_i = X"0D" or
d_i = X"1D" or
d_i = X"19" or
d_i = X"01" or
d_i = X"11" or
d_i = X"29" or
d_i = X"25" or
d_i = X"35" or
d_i = X"2D" or
d_i = X"3D" or
d_i = X"39" or
d_i = X"21" or
d_i = X"31" or
d_i = X"C9" or
d_i = X"C5" or
d_i = X"D5" or
d_i = X"CD" or
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "000";
sel_reg_o_i_cld <= "00";
sel_rb_in_o_i_cld <= "011";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") and (rdy_i = '1')) then
zw_b4 <= X"01";
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"E8") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "001";
sel_reg_o_i_cld <= "01";
sel_rb_in_o_i_cld <= "011";
zw_b4 <= X"01";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"C8") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "010";
sel_reg_o_i_cld <= "10";
sel_rb_in_o_i_cld <= "011";
zw_b4 <= X"01";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"4C" or
d_i = X"6C") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"20") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") and (rdy_i = '1')) then
sel_reg_o_i_cld <= "00";
sel_rb_in_o_i_cld <= "011";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") and (rdy_i = '1')) then
sel_reg_o_i_cld <= "01";
sel_rb_in_o_i_cld <= "011";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") and (rdy_i = '1')) then
sel_reg_o_i_cld <= "10";
sel_rb_in_o_i_cld <= "011";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"EA") and (rdy_i = '1')) then
elsif ((d_i = X"48") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"08") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"68") and (rdy_i = '1')) then
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '0';
sel_sp_val_o_i_cld <= "00";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sel_reg_o_i_cld <= "00";
sel_rb_in_o_i_cld <= "011";
elsif ((d_i = X"28") and (rdy_i = '1')) then
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '0';
sel_sp_val_o_i_cld <= "00";
elsif ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"40") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"60") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '0';
sel_sp_val_o_i_cld <= "00";
elsif ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sel_reg_o_i_cld <= "00";
sel_rb_in_o_i_cld <= "011";
zw_b1(0) <= reg_F(7);
elsif ((d_i = X"38") and (rdy_i = '1')) then
elsif ((d_i = X"F8") and (rdy_i = '1')) then
elsif ((d_i = X"78") and (rdy_i = '1')) then
elsif ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91" or
d_i = X"11") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "000";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "001";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "010";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"AA") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "000";
sel_reg_o_i_cld <= "01";
sel_rb_in_o_i_cld <= "000";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sel_sp_in_o_i_cld <= "01";
sel_sp_as_o_i_cld <= '0';
sel_sp_val_o_i_cld <= "00";
elsif ((d_i = X"0A") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "000";
sel_reg_o_i_cld <= "00";
sel_rb_in_o_i_cld <= "011";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"4A") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "000";
sel_reg_o_i_cld <= "00";
sel_rb_in_o_i_cld <= "011";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"2A") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "000";
sel_reg_o_i_cld <= "00";
sel_rb_in_o_i_cld <= "011";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"6A") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "000";
sel_reg_o_i_cld <= "00";
sel_rb_in_o_i_cld <= "011";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"A8") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "000";
sel_reg_o_i_cld <= "10";
sel_rb_in_o_i_cld <= "000";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sel_sp_in_o_i_cld <= "01";
sel_sp_as_o_i_cld <= '0';
sel_sp_val_o_i_cld <= "00";
elsif ((d_i = X"98") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "010";
sel_reg_o_i_cld <= "00";
sel_rb_in_o_i_cld <= "001";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sel_sp_in_o_i_cld <= "01";
sel_sp_as_o_i_cld <= '0';
sel_sp_val_o_i_cld <= "00";
elsif ((d_i = X"BA") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "001";
sel_reg_o_i_cld <= "01";
sel_rb_in_o_i_cld <= "011";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sel_sp_in_o_i_cld <= "01";
sel_sp_as_o_i_cld <= '0';
sel_sp_val_o_i_cld <= "00";
elsif ((d_i = X"8A") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "001";
sel_reg_o_i_cld <= "00";
sel_rb_in_o_i_cld <= "010";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sel_sp_in_o_i_cld <= "01";
sel_sp_as_o_i_cld <= '0';
sel_sp_val_o_i_cld <= "00";
elsif ((d_i = X"9A") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "001";
sel_reg_o_i_cld <= "11";
sel_rb_in_o_i_cld <= "111";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sel_sp_in_o_i_cld <= "01";
sel_sp_as_o_i_cld <= '0';
sel_sp_val_o_i_cld <= "00";
end if;
when s1 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s2 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= '1';
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s5 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(3) <= '1';
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s3 =>
sig_PC <= adr_pc_i;
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(2) <= '1';
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s4 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
sig_PC <= adr_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s12 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= '0';
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s16 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(3) <= '0';
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s17 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(2) <= '0';
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s24 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(6) <= '0';
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s25 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s271 =>
if (rdy_i = '1' and
zw_REG_OP = X"4C") then
sig_PC <= adr_nxt_pc_i;
sel_pc_in_o_i_cld <= "01";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "11";
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"6C") then
sig_PC <= adr_nxt_pc_i;
sel_pc_in_o_i_cld <= "01";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
zw_b1 <= d_i;
end if;
when s273 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
end if;
when s304 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
sel_pc_in_o_i_cld <= "01";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "11";
zw_b1 <= d_i;
end if;
when s307 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s177 =>
if (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"9D") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
end if;
when s180 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s181 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s182 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s183 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s184 =>
sig_PC <= adr_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
when s185 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s186 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s187 =>
sig_PC <= adr_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
when s188 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s189 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s190 =>
sig_PC <= adr_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
when s191 =>
sig_PC <= zw_b3 & zw_b1;
when s192 =>
sig_PC <= d_i & zw_b1;
when s193 =>
sig_PC <= adr_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
when s377 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s381 =>
sig_PC <= adr_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
when s378 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s382 =>
sig_PC <= adr_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
when s383 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s384 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s385 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s386 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F <= d_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s387 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s388 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s389 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
reg_F <= d_i;
sel_pc_in_o_i_cld <= "01";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "11";
end if;
when s391 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
end if;
when s392 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s390 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s393 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s394 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
sel_pc_in_o_i_cld <= "01";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
end if;
when s395 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s396 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s397 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
end if;
when s399 =>
sig_PC <= adr_sp_i;
when s400 =>
sig_PC <= adr_pc_i;
sel_pc_in_o_i_cld <= "01";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "11";
when s401 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1 (7 downto 0);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s526 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s527 =>
sig_PC <= adr_sp_i;
when s528 =>
sig_PC <= adr_sp_i;
when s529 =>
sig_PC <= X"FFFE";
when s530 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_F(4) <= '1';
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s531 =>
if (rdy_i = '1') then
sig_PC <= X"FFFF";
zw_b1 <= d_i;
end if;
when s544 =>
sig_PC <= adr_sp_i;
when s545 =>
sig_PC <= adr_sp_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
when s546 =>
sig_PC <= adr_pc_i;
when s547 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
zw_w1 (7 downto 0) <= d_i;
sel_pc_in_o_i_cld <= "01";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "11";
end if;
when s549 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_w1 (7 downto 0);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s550 =>
sig_PC <= adr_sp_i;
sel_pc_in_o_i_cld <= "01";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
when s404 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(7);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s556 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s557 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(7);
reg_F(0) <= q_a_i(7);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s579 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s201 =>
if (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
sig_PC <= X"00" & d_i;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
zw_REG_OP = X"4D" OR
zw_REG_OP = X"0D" OR
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
end if;
when s202 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s210 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s211 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s215 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s217 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s218 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s222 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s223 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s224 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s225 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s226 =>
if (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s243 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s244 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s247 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s344 =>
if (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s343 =>
if (rdy_i = '1') then
zw_b1 <= d_alu_i;
end if;
when s251 =>
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
when s351 =>
if (rdy_i = '1' and
zw_REG_OP = X"24") then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
end if;
when s361 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= d_i(7);
reg_F(6) <= d_i(6);
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s360 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s403 =>
if (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
end if;
when s406 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s407 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s409 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s412 =>
if (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s416 =>
if (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) then
zw_b1 <= d_i(6 downto 0) & '0';
zw_b2(0) <= d_i(7);
elsif (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) then
zw_b1 <= '0' & d_i(7 downto 1);
zw_b2(0) <= d_i(0);
elsif (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) then
zw_b1 <= d_i(6 downto 0) & reg_F(0);
zw_b2(0) <= d_i(7);
elsif (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) then
zw_b1 <= reg_F(0) & d_i(7 downto 1);
zw_b2(0) <= d_i(0);
end if;
when s418 =>
sig_PC <= adr_pc_i;
reg_F(0) <= zw_b2(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
when s510 =>
if (rdy_i = '1' and
zw_REG_OP = X"65") then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s553 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s555 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s558 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s560 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s561 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s563 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s564 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s565 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s566 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s266 =>
if (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
(reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) then
sig_PC <= adr_nxt_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1') then
sig_PC <= adr_nxt_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "10";
zw_b2 <= d_i;
end if;
when s301 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
sig_PC <= adr_nxt_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0);
end if;
when s302 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when RES =>
sel_pc_in_o_i_cld <= "00";
sel_pc_val_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sig_PC <= adr_nxt_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
when s511 =>
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU2(4);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s559 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s562 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s567 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s568 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s569 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s570 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s571 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s572 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s573 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU2(4);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s574 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU2(4);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s548 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s551 =>
sig_PC <= adr_sp_i;
when s552 =>
sig_PC <= adr_sp_i;
when s575 =>
if (rdy_i = '1') then
sig_PC <= X"FFFF";
zw_b1 <= d_i;
end if;
when s576 =>
sig_PC <= X"FFFE";
when s577 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_F(2) <= '1';
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s532 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s533 =>
sig_PC <= adr_sp_i;
when s534 =>
sig_PC <= adr_sp_i;
when s535 =>
if (rdy_i = '1') then
sig_PC <= X"FFFB";
zw_b1 <= d_i;
end if;
when s536 =>
sig_PC <= X"FFFA";
when s537 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when others =>
null;
end case;
end if;
end process clocked_proc;
-----------------------------------------------------------------
nextstate_proc : process (
adr_nxt_pc_i,
current_state,
d_i,
irq_n_i,
rdy_i,
reg_F,
zw_REG_NMI,
zw_REG_OP,
zw_b2,
zw_b3
)
-----------------------------------------------------------------
begin
case current_state is
when FETCH =>
if ((zw_REG_NMI = '1') and (rdy_i = '1')) then
next_state <= s532;
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
next_state <= s548;
elsif ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") and (rdy_i = '1')) then
next_state <= s510;
elsif ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") and (rdy_i = '1')) then
next_state <= s403;
elsif ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") and (rdy_i = '1')) then
next_state <= s266;
elsif ((d_i = X"24" or
d_i = X"2C") and (rdy_i = '1')) then
next_state <= s351;
elsif ((d_i = X"00") and (rdy_i = '1')) then
next_state <= s526;
elsif ((d_i = X"18") and (rdy_i = '1')) then
next_state <= s12;
elsif ((d_i = X"D8") and (rdy_i = '1')) then
next_state <= s16;
elsif ((d_i = X"58") and (rdy_i = '1')) then
next_state <= s17;
elsif ((d_i = X"B8") and (rdy_i = '1')) then
next_state <= s24;
elsif ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") and (rdy_i = '1')) then
next_state <= s201;
elsif ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") and (rdy_i = '1')) then
next_state <= s201;
elsif ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") and (rdy_i = '1')) then
next_state <= s226;
elsif ((d_i = X"CA") and (rdy_i = '1')) then
next_state <= s25;
elsif ((d_i = X"88") and (rdy_i = '1')) then
next_state <= s25;
elsif ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
d_i = X"5D" or
d_i = X"59" or
d_i = X"41" or
d_i = X"51" or
d_i = X"09" or
d_i = X"05" or
d_i = X"15" or
d_i = X"0D" or
d_i = X"1D" or
d_i = X"19" or
d_i = X"01" or
d_i = X"11" or
d_i = X"29" or
d_i = X"25" or
d_i = X"35" or
d_i = X"2D" or
d_i = X"3D" or
d_i = X"39" or
d_i = X"21" or
d_i = X"31" or
d_i = X"C9" or
d_i = X"C5" or
d_i = X"D5" or
d_i = X"CD" or
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") and (rdy_i = '1')) then
next_state <= s201;
elsif ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") and (rdy_i = '1')) then
next_state <= s226;
elsif ((d_i = X"E8") and (rdy_i = '1')) then
next_state <= s25;
elsif ((d_i = X"C8") and (rdy_i = '1')) then
next_state <= s25;
elsif ((d_i = X"4C" or
d_i = X"6C") and (rdy_i = '1')) then
next_state <= s271;
elsif ((d_i = X"20") and (rdy_i = '1')) then
next_state <= s397;
elsif ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") and (rdy_i = '1')) then
next_state <= s201;
elsif ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") and (rdy_i = '1')) then
next_state <= s201;
elsif ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") and (rdy_i = '1')) then
next_state <= s201;
elsif ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") and (rdy_i = '1')) then
next_state <= s403;
elsif ((d_i = X"EA") and (rdy_i = '1')) then
next_state <= s1;
elsif ((d_i = X"48") and (rdy_i = '1')) then
next_state <= s377;
elsif ((d_i = X"08") and (rdy_i = '1')) then
next_state <= s378;
elsif ((d_i = X"68") and (rdy_i = '1')) then
next_state <= s379;
elsif ((d_i = X"28") and (rdy_i = '1')) then
next_state <= s380;
elsif ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") and (rdy_i = '1')) then
next_state <= s403;
elsif ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") and (rdy_i = '1')) then
next_state <= s403;
elsif ((d_i = X"40") and (rdy_i = '1')) then
next_state <= s387;
elsif ((d_i = X"60") and (rdy_i = '1')) then
next_state <= s390;
elsif ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") and (rdy_i = '1')) then
next_state <= s511;
elsif ((d_i = X"38") and (rdy_i = '1')) then
next_state <= s2;
elsif ((d_i = X"F8") and (rdy_i = '1')) then
next_state <= s5;
elsif ((d_i = X"78") and (rdy_i = '1')) then
next_state <= s3;
elsif ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91" or
d_i = X"11") and (rdy_i = '1')) then
next_state <= s177;
elsif ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") and (rdy_i = '1')) then
next_state <= s177;
elsif ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") and (rdy_i = '1')) then
next_state <= s177;
elsif ((d_i = X"AA") and (rdy_i = '1')) then
next_state <= s4;
elsif ((d_i = X"0A") and (rdy_i = '1')) then
next_state <= s404;
elsif ((d_i = X"4A") and (rdy_i = '1')) then
next_state <= s556;
elsif ((d_i = X"2A") and (rdy_i = '1')) then
next_state <= s557;
elsif ((d_i = X"6A") and (rdy_i = '1')) then
next_state <= s579;
elsif ((d_i = X"A8") and (rdy_i = '1')) then
next_state <= s4;
elsif ((d_i = X"98") and (rdy_i = '1')) then
next_state <= s4;
elsif ((d_i = X"BA") and (rdy_i = '1')) then
next_state <= s4;
elsif ((d_i = X"8A") and (rdy_i = '1')) then
next_state <= s4;
elsif ((d_i = X"9A") and (rdy_i = '1')) then
next_state <= s4;
elsif (rdy_i = '1') then
next_state <= s1;
else
next_state <= FETCH;
end if;
when s1 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s1;
end if;
when s2 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s2;
end if;
when s5 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s5;
end if;
when s3 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s3;
end if;
when s4 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
next_state <= FETCH;
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s4;
end if;
when s12 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s12;
end if;
when s16 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s16;
end if;
when s17 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s17;
end if;
when s24 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s24;
end if;
when s25 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s25;
end if;
when s271 =>
if (rdy_i = '1' and
zw_REG_OP = X"4C") then
next_state <= s307;
elsif (rdy_i = '1' and
zw_REG_OP = X"6C") then
next_state <= s273;
else
next_state <= s271;
end if;
when s273 =>
if (rdy_i = '1') then
next_state <= s304;
else
next_state <= s273;
end if;
when s304 =>
if (rdy_i = '1') then
next_state <= s307;
else
next_state <= s304;
end if;
when s307 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s307;
end if;
when s177 =>
if (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) then
next_state <= s184;
elsif (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) then
next_state <= s185;
elsif (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) then
next_state <= s183;
elsif (rdy_i = '1' and
zw_REG_OP = X"9D") then
next_state <= s182;
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
next_state <= s180;
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
next_state <= s181;
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
next_state <= s186;
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
next_state <= s185;
else
next_state <= s177;
end if;
when s180 =>
if (rdy_i = '1') then
next_state <= s191;
else
next_state <= s180;
end if;
when s181 =>
if (rdy_i = '1') then
next_state <= s189;
else
next_state <= s181;
end if;
when s182 =>
if (rdy_i = '1') then
next_state <= s191;
else
next_state <= s182;
end if;
when s183 =>
if (rdy_i = '1') then
next_state <= s187;
else
next_state <= s183;
end if;
when s184 =>
next_state <= FETCH;
when s185 =>
if (rdy_i = '1') then
next_state <= s190;
else
next_state <= s185;
end if;
when s186 =>
if (rdy_i = '1') then
next_state <= s188;
else
next_state <= s186;
end if;
when s187 =>
next_state <= FETCH;
when s188 =>
if (rdy_i = '1') then
next_state <= s192;
else
next_state <= s188;
end if;
when s189 =>
if (rdy_i = '1') then
next_state <= s191;
else
next_state <= s189;
end if;
when s190 =>
next_state <= FETCH;
when s191 =>
next_state <= s193;
when s192 =>
next_state <= s193;
when s193 =>
next_state <= FETCH;
when s377 =>
if (rdy_i = '1') then
next_state <= s381;
else
next_state <= s377;
end if;
when s381 =>
next_state <= FETCH;
when s378 =>
if (rdy_i = '1') then
next_state <= s382;
else
next_state <= s378;
end if;
when s382 =>
next_state <= FETCH;
when s379 =>
if (rdy_i = '1') then
next_state <= s383;
else
next_state <= s379;
end if;
when s383 =>
if (rdy_i = '1') then
next_state <= s384;
else
next_state <= s383;
end if;
when s384 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s384;
end if;
when s380 =>
if (rdy_i = '1') then
next_state <= s385;
else
next_state <= s380;
end if;
when s385 =>
if (rdy_i = '1') then
next_state <= s386;
else
next_state <= s385;
end if;
when s386 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s386;
end if;
when s387 =>
if (rdy_i = '1') then
next_state <= s388;
else
next_state <= s387;
end if;
when s388 =>
if (rdy_i = '1') then
next_state <= s389;
else
next_state <= s388;
end if;
when s389 =>
if (rdy_i = '1') then
next_state <= s391;
else
next_state <= s389;
end if;
when s391 =>
if (rdy_i = '1') then
next_state <= s392;
else
next_state <= s391;
end if;
when s392 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s392;
end if;
when s390 =>
if (rdy_i = '1') then
next_state <= s393;
else
next_state <= s390;
end if;
when s393 =>
if (rdy_i = '1') then
next_state <= s394;
else
next_state <= s393;
end if;
when s394 =>
if (rdy_i = '1') then
next_state <= s395;
else
next_state <= s394;
end if;
when s395 =>
if (rdy_i = '1') then
next_state <= s396;
else
next_state <= s395;
end if;
when s396 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s396;
end if;
when s397 =>
if (rdy_i = '1') then
next_state <= s398;
else
next_state <= s397;
end if;
when s398 =>
if (rdy_i = '1') then
next_state <= s399;
else
next_state <= s398;
end if;
when s399 =>
next_state <= s400;
when s400 =>
next_state <= s401;
when s401 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s401;
end if;
when s526 =>
if (rdy_i = '1') then
next_state <= s527;
else
next_state <= s526;
end if;
when s527 =>
next_state <= s528;
when s528 =>
next_state <= s529;
when s529 =>
next_state <= s531;
when s530 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s530;
end if;
when s531 =>
if (rdy_i = '1') then
next_state <= s530;
else
next_state <= s531;
end if;
when s544 =>
next_state <= s550;
when s545 =>
next_state <= s546;
when s546 =>
next_state <= s547;
when s547 =>
if (rdy_i = '1') then
next_state <= s549;
else
next_state <= s547;
end if;
when s549 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s549;
end if;
when s550 =>
next_state <= s545;
when s404 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s404;
end if;
when s556 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s556;
end if;
when s557 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s557;
end if;
when s579 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s579;
end if;
when s201 =>
if (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
next_state <= s224;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
next_state <= FETCH;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
next_state <= FETCH;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
next_state <= FETCH;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
next_state <= FETCH;
elsif (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
next_state <= FETCH;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) then
next_state <= s217;
elsif (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
zw_REG_OP = X"4D" OR
zw_REG_OP = X"0D" OR
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) then
next_state <= s202;
elsif (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) then
next_state <= s210;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) then
next_state <= s211;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) then
next_state <= s215;
elsif (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) then
next_state <= s218;
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
next_state <= s217;
else
next_state <= s201;
end if;
when s202 =>
if (rdy_i = '1') then
next_state <= s224;
else
next_state <= s202;
end if;
when s210 =>
if (rdy_i = '1') then
next_state <= s225;
else
next_state <= s210;
end if;
when s211 =>
if (rdy_i = '1') then
next_state <= s225;
else
next_state <= s211;
end if;
when s215 =>
if (rdy_i = '1') then
next_state <= s223;
else
next_state <= s215;
end if;
when s217 =>
if (rdy_i = '1') then
next_state <= s224;
else
next_state <= s217;
end if;
when s218 =>
if (rdy_i = '1') then
next_state <= s222;
else
next_state <= s218;
end if;
when s222 =>
if (rdy_i = '1') then
next_state <= s202;
else
next_state <= s222;
end if;
when s223 =>
if (rdy_i = '1') then
next_state <= s225;
else
next_state <= s223;
end if;
when s224 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
next_state <= FETCH;
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
next_state <= FETCH;
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
next_state <= FETCH;
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s224;
end if;
when s225 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
next_state <= FETCH;
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
next_state <= FETCH;
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
next_state <= FETCH;
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
next_state <= FETCH;
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s224;
else
next_state <= s225;
end if;
when s226 =>
if (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) then
next_state <= s343;
elsif (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) then
next_state <= s247;
elsif (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) then
next_state <= s243;
elsif (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) then
next_state <= s244;
else
next_state <= s226;
end if;
when s243 =>
if (rdy_i = '1') then
next_state <= s343;
else
next_state <= s243;
end if;
when s244 =>
if (rdy_i = '1') then
next_state <= s344;
else
next_state <= s244;
end if;
when s247 =>
if (rdy_i = '1') then
next_state <= s343;
else
next_state <= s247;
end if;
when s344 =>
if (rdy_i = '1') then
next_state <= s343;
else
next_state <= s344;
end if;
when s343 =>
if (rdy_i = '1') then
next_state <= s250;
else
next_state <= s343;
end if;
when s250 =>
if (rdy_i = '1') then
next_state <= s251;
else
next_state <= s250;
end if;
when s251 =>
next_state <= FETCH;
when s351 =>
if (rdy_i = '1' and
zw_REG_OP = X"24") then
next_state <= s361;
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
next_state <= s360;
else
next_state <= s351;
end if;
when s361 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s361;
end if;
when s360 =>
if (rdy_i = '1') then
next_state <= s361;
else
next_state <= s360;
end if;
when s403 =>
if (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) then
next_state <= s407;
elsif (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) then
next_state <= s413;
elsif (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) then
next_state <= s409;
elsif (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) then
next_state <= s406;
else
next_state <= s403;
end if;
when s406 =>
if (rdy_i = '1') then
next_state <= s413;
else
next_state <= s406;
end if;
when s407 =>
if (rdy_i = '1') then
next_state <= s412;
else
next_state <= s407;
end if;
when s409 =>
if (rdy_i = '1') then
next_state <= s413;
else
next_state <= s409;
end if;
when s412 =>
if (rdy_i = '1') then
next_state <= s413;
else
next_state <= s412;
end if;
when s413 =>
if (rdy_i = '1') then
next_state <= s416;
else
next_state <= s413;
end if;
when s416 =>
if (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) then
next_state <= s418;
elsif (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) then
next_state <= s418;
elsif (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) then
next_state <= s418;
elsif (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) then
next_state <= s418;
else
next_state <= s416;
end if;
when s418 =>
next_state <= FETCH;
when s510 =>
if (rdy_i = '1' and
zw_REG_OP = X"65") then
next_state <= s565;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
next_state <= s560;
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
next_state <= s553;
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
next_state <= s555;
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
next_state <= s555;
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
next_state <= s558;
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
next_state <= s561;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') then
next_state <= FETCH;
else
next_state <= s510;
end if;
when s553 =>
if (rdy_i = '1') then
next_state <= s565;
else
next_state <= s553;
end if;
when s555 =>
if (rdy_i = '1') then
next_state <= s564;
else
next_state <= s555;
end if;
when s558 =>
if (rdy_i = '1') then
next_state <= s566;
else
next_state <= s558;
end if;
when s560 =>
if (rdy_i = '1') then
next_state <= s565;
else
next_state <= s560;
end if;
when s561 =>
if (rdy_i = '1') then
next_state <= s563;
else
next_state <= s561;
end if;
when s563 =>
if (rdy_i = '1') then
next_state <= s553;
else
next_state <= s563;
end if;
when s564 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s565;
else
next_state <= s564;
end if;
when s565 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' and
reg_F(3) = '1') then
next_state <= FETCH;
else
next_state <= s565;
end if;
when s566 =>
if (rdy_i = '1') then
next_state <= s564;
else
next_state <= s566;
end if;
when s266 =>
if (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
(reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s301;
else
next_state <= s266;
end if;
when s301 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s302;
else
next_state <= s301;
end if;
when s302 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s302;
end if;
when RES =>
next_state <= s544;
when s511 =>
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
next_state <= s574;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
next_state <= s569;
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
next_state <= s559;
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
next_state <= s562;
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
next_state <= s567;
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
next_state <= s568;
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
next_state <= s570;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') then
next_state <= FETCH;
else
next_state <= s511;
end if;
when s559 =>
if (rdy_i = '1') then
next_state <= s574;
else
next_state <= s559;
end if;
when s562 =>
if (rdy_i = '1') then
next_state <= s573;
else
next_state <= s562;
end if;
when s567 =>
if (rdy_i = '1') then
next_state <= s573;
else
next_state <= s567;
end if;
when s568 =>
if (rdy_i = '1') then
next_state <= s571;
else
next_state <= s568;
end if;
when s569 =>
if (rdy_i = '1') then
next_state <= s574;
else
next_state <= s569;
end if;
when s570 =>
if (rdy_i = '1') then
next_state <= s572;
else
next_state <= s570;
end if;
when s571 =>
if (rdy_i = '1') then
next_state <= s573;
else
next_state <= s571;
end if;
when s572 =>
if (rdy_i = '1') then
next_state <= s559;
else
next_state <= s572;
end if;
when s573 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s574;
else
next_state <= s573;
end if;
when s574 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' and
reg_F(3) = '1') then
next_state <= FETCH;
else
next_state <= s574;
end if;
when s548 =>
if (rdy_i = '1') then
next_state <= s551;
else
next_state <= s548;
end if;
when s551 =>
next_state <= s552;
when s552 =>
next_state <= s576;
when s575 =>
if (rdy_i = '1') then
next_state <= s577;
else
next_state <= s575;
end if;
when s576 =>
next_state <= s575;
when s577 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s577;
end if;
when s532 =>
if (rdy_i = '1') then
next_state <= s533;
else
next_state <= s532;
end if;
when s533 =>
next_state <= s534;
when s534 =>
next_state <= s536;
when s535 =>
if (rdy_i = '1') then
next_state <= s537;
else
next_state <= s535;
end if;
when s536 =>
next_state <= s535;
when s537 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s537;
end if;
when others =>
next_state <= RES;
end case;
end process nextstate_proc;
-----------------------------------------------------------------
output_proc : process (
adr_nxt_pc_i,
adr_pc_i,
adr_sp_i,
current_state,
d_alu_i,
d_i,
d_regs_out_i,
irq_n_i,
q_a_i,
q_x_i,
q_y_i,
rdy_i,
reg_F,
sig_PC,
zw_ALU,
zw_ALU1,
zw_ALU2,
zw_ALU3,
zw_ALU4,
zw_ALU5,
zw_ALU6,
zw_REG_NMI,
zw_REG_OP,
zw_b1,
zw_b2,
zw_b3,
zw_b4,
zw_w1
)
-----------------------------------------------------------------
begin
-- Default Assignment
a_o <= sig_PC;
adr_o <= X"0000";
ch_a_o <= X"00";
ch_b_o <= X"00";
d_regs_in_o <= X"00";
ld_o <= "00";
ld_pc_o <= '0';
ld_sp_o <= '0';
load_regs_o <= '0';
offset_o <= X"0000";
reg_0flag_o <= reg_F(0);
reg_1flag_o <= reg_F(1);
reg_3flag_o <= reg_F(3);
reg_7flag_o <= reg_F(7);
-- Default Assignment To Internals
sig_D_OUT <= X"00";
sig_RD <= '0';
sig_RWn <= '1';
sig_SYNC <= '0';
sig_WR <= '0';
zw_ALU <= '0' & X"00";
zw_ALU1 <= '0' & X"00";
zw_ALU2 <= '0' & X"00";
zw_ALU3 <= '0' & X"00";
zw_ALU4 <= '0' & X"00";
zw_ALU5 <= '0' & X"00";
zw_ALU6 <= '0' & X"00";
-- Combined Actions
case current_state is
when FETCH =>
sig_RWn <= '1';
sig_RD <= '1';
sig_SYNC <= NOT (rdy_i);
if ((zw_REG_NMI = '1') and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"24" or
d_i = X"2C") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"00") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"18") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"D8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"58") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"B8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"CA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"88") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
d_i = X"5D" or
d_i = X"59" or
d_i = X"41" or
d_i = X"51" or
d_i = X"09" or
d_i = X"05" or
d_i = X"15" or
d_i = X"0D" or
d_i = X"1D" or
d_i = X"19" or
d_i = X"01" or
d_i = X"11" or
d_i = X"29" or
d_i = X"25" or
d_i = X"35" or
d_i = X"2D" or
d_i = X"3D" or
d_i = X"39" or
d_i = X"21" or
d_i = X"31" or
d_i = X"C9" or
d_i = X"C5" or
d_i = X"D5" or
d_i = X"CD" or
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"E8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"C8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"4C" or
d_i = X"6C") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"20") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"EA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"48") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"08") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"68") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"28") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"40") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"60") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"38") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"F8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"78") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91" or
d_i = X"11") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"AA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"0A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"4A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"2A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"6A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"A8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"98") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"BA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"8A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"9A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s1 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s2 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s5 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s3 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s4 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
adr_o <= X"01" & d_regs_out_i;
ld_o <= "11";
ld_sp_o <= '1';
sig_SYNC <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
d_regs_in_o <= adr_sp_i (7 downto 0);
ch_a_o <= adr_sp_i (7 downto 0);
ch_b_o <= X"00";
load_regs_o <= '1';
sig_SYNC <= '1';
elsif (rdy_i = '1') then
ch_a_o <= d_regs_out_i;
ch_b_o <= X"00";
load_regs_o <= '1';
sig_SYNC <= '1';
end if;
when s12 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s16 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s17 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s24 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s25 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
d_regs_in_o <= d_alu_i;
ch_a_o <= d_regs_out_i;
ch_b_o <= zw_b4;
load_regs_o <= '1';
sig_SYNC <= '1';
end if;
when s271 =>
sig_RWn <= '1';
sig_RD <= '1';
when s273 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s304 =>
sig_RWn <= '1';
sig_RD <= '1';
when s307 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
end if;
when s177 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"9D") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s180 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s181 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s182 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s183 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s184 =>
sig_RWn <= '1';
sig_RD <= '1';
sig_SYNC <= '1';
when s185 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s186 =>
sig_RWn <= '1';
sig_RD <= '1';
when s187 =>
sig_RWn <= '1';
sig_RD <= '1';
sig_SYNC <= '1';
when s188 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s189 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s190 =>
sig_RWn <= '1';
sig_RD <= '1';
sig_SYNC <= '1';
when s191 =>
sig_RWn <= '1';
sig_RD <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
when s192 =>
sig_RWn <= '1';
sig_RD <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
when s193 =>
sig_RWn <= '1';
sig_RD <= '1';
sig_SYNC <= '1';
when s377 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= q_a_i;
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s381 =>
sig_RWn <= '1';
sig_RD <= '1';
sig_SYNC <= '1';
when s378 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F;
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s382 =>
sig_RWn <= '1';
sig_RD <= '1';
sig_SYNC <= '1';
when s379 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s383 =>
sig_RWn <= '1';
sig_RD <= '1';
when s384 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
end if;
when s380 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s385 =>
sig_RWn <= '1';
sig_RD <= '1';
when s386 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s387 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s388 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s389 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s391 =>
sig_RWn <= '1';
sig_RD <= '1';
when s392 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
end if;
when s390 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s393 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s394 =>
sig_RWn <= '1';
sig_RD <= '1';
when s395 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s396 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s397 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
end if;
when s398 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
end if;
when s399 =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
when s400 =>
sig_RWn <= '1';
sig_RD <= '1';
when s401 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
end if;
when s526 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
end if;
when s527 =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
when s528 =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
when s529 =>
sig_RWn <= '1';
sig_RD <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F;
when s530 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s531 =>
sig_RWn <= '1';
sig_RD <= '1';
when s544 =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
ld_sp_o <= '1';
when s545 =>
sig_RWn <= '1';
sig_RD <= '1';
adr_o <= X"FFFB";
ld_o <= "11";
ld_pc_o <= '1';
when s546 =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
ld_pc_o <= '1';
when s547 =>
sig_RWn <= '1';
sig_RD <= '1';
when s549 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_w1 (7 downto 0);
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
end if;
when s550 =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
ld_sp_o <= '1';
when s404 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= q_a_i (6 downto 0) & '0';
ch_b_o <= X"00";
d_regs_in_o <= q_a_i (6 downto 0) & '0';
load_regs_o <= '1';
sig_SYNC <= '1';
end if;
when s556 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= '0' & q_a_i (7 downto 1);
ch_b_o <= X"00";
d_regs_in_o <= '0' & q_a_i (7 downto 1);
load_regs_o <= '1';
sig_SYNC <= '1';
end if;
when s557 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= q_a_i (6 downto 0) & reg_F(0);
ch_b_o <= X"00";
d_regs_in_o <= q_a_i (6 downto 0) & reg_F(0);
load_regs_o <= '1';
sig_SYNC <= '1';
end if;
when s579 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= reg_F(0) & q_a_i (7 downto 1);
ch_b_o <= X"00";
d_regs_in_o <= reg_F(0) & q_a_i (7 downto 1);
load_regs_o <= '1';
sig_SYNC <= '1';
end if;
when s201 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
ld_o <= "11";
ld_pc_o <= '1';
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
zw_REG_OP = X"4D" OR
zw_REG_OP = X"0D" OR
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) then
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s202 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s210 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s211 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s215 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s217 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s218 =>
sig_RWn <= '1';
sig_RD <= '1';
when s222 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s223 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s224 =>
sig_RWn <= '1';
sig_RD <= '1';
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
elsif (rdy_i = '1') then
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
end if;
when s225 =>
sig_RWn <= '1';
sig_RD <= '1';
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
end if;
when s226 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end if;
when s243 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s244 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s247 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s344 =>
sig_RWn <= '1';
sig_RD <= '1';
when s343 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= zw_b4;
end if;
when s250 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= zw_b1;
end if;
when s251 =>
sig_RWn <= '1';
sig_RD <= '1';
ch_a_o <= zw_b1;
ch_b_o <= X"00";
sig_SYNC <= '1';
when s351 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' and
zw_REG_OP = X"24") then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s361 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= q_a_i AND d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
end if;
when s360 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s403 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s406 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s407 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s409 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s412 =>
sig_RWn <= '1';
sig_RD <= '1';
when s413 =>
sig_RWn <= '1';
sig_RD <= '1';
when s416 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) then
sig_D_OUT <= d_i(6 downto 0) & '0';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) then
sig_D_OUT <= '0' & d_i(7 downto 1);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) then
sig_D_OUT <= d_i(6 downto 0) & reg_F(0);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) then
sig_D_OUT <= reg_F(0) & d_i(7 downto 1);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
end if;
when s418 =>
sig_RWn <= '1';
sig_RD <= '1';
ch_a_o <= zw_b1;
ch_b_o <= X"00";
sig_SYNC <= '1';
when s510 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' and
zw_REG_OP = X"65") then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(7 downto 5));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(7 downto 5));
zw_ALU6(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0';
zw_ALU5(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0';
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
end if;
when s553 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s555 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s558 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s560 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s561 =>
sig_RWn <= '1';
sig_RD <= '1';
when s563 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s564 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(7 downto 5));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(7 downto 5));
zw_ALU6(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0';
zw_ALU5(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0';
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
end if;
when s565 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(7 downto 5));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(7 downto 5));
zw_ALU6(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0';
zw_ALU5(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0';
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
end if;
when s566 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s266 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
(reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) then
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
elsif (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s301 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
elsif (rdy_i = '1') then
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s302 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when RES =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
ld_pc_o <= '1';
ld_sp_o <= '1';
sig_RWn <= '1';
sig_RD <= '1';
when s511 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) +
unsigned ((zw_ALU6(8 downto 5)));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) +
unsigned ((zw_ALU5(8 downto 5)));
zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' &
(zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' &
(zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
end if;
when s559 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s562 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s567 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s568 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s569 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s570 =>
sig_RWn <= '1';
sig_RD <= '1';
when s571 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s572 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s573 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) +
unsigned ((zw_ALU6(8 downto 5)));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) +
unsigned ((zw_ALU5(8 downto 5)));
zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' &
(zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' &
(zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
end if;
when s574 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) +
unsigned ((zw_ALU6(8 downto 5)));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) +
unsigned ((zw_ALU5(8 downto 5)));
zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' &
(zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' &
(zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
end if;
when s548 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
end if;
when s551 =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
when s552 =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
when s575 =>
sig_RWn <= '1';
sig_RD <= '1';
when s576 =>
sig_RWn <= '1';
sig_RD <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F;
when s577 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s532 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
end if;
when s533 =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
when s534 =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
when s535 =>
sig_RWn <= '1';
sig_RD <= '1';
when s536 =>
sig_RWn <= '1';
sig_RD <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F;
when s537 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when others =>
null;
end case;
end process output_proc;
-- Concurrent Statements
-- Clocked output assignments
d_o <= d_o_cld;
rd_o <= rd_o_cld;
sync_o <= sync_o_cld;
wr_n_o <= wr_n_o_cld;
wr_o <= wr_o_cld;
sel_alu_as_o_i <= sel_alu_as_o_i_cld;
sel_alu_out_o_i <= sel_alu_out_o_i_cld;
sel_pc_as_o_i <= sel_pc_as_o_i_cld;
sel_pc_in_o_i <= sel_pc_in_o_i_cld;
sel_pc_val_o_i <= sel_pc_val_o_i_cld;
sel_rb_in_o_i <= sel_rb_in_o_i_cld;
sel_rb_out_o_i <= sel_rb_out_o_i_cld;
sel_reg_o_i <= sel_reg_o_i_cld;
sel_sp_as_o_i <= sel_sp_as_o_i_cld;
sel_sp_in_o_i <= sel_sp_in_o_i_cld;
sel_sp_val_o_i <= sel_sp_val_o_i_cld;
end fsm;
|
-- VHDL Entity R6502_TC.fsm_core_V2_0.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 19:06:55 08.04.2008
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity fsm_core_V2_0 is
port(
adr_nxt_pc_i : in std_logic_vector (15 downto 0);
adr_nxt_sp_i : in std_logic_vector (15 downto 0);
adr_pc_i : in std_logic_vector (15 downto 0);
adr_sp_i : in std_logic_vector (15 downto 0);
clk_clk_i : in std_logic;
cout_pc_i : in std_logic;
d_alu_i : in std_logic_vector ( 7 downto 0 );
d_i : in std_logic_vector ( 7 downto 0 );
d_regs_out_i : in std_logic_vector ( 7 downto 0 );
irq_n_i : in std_logic;
nmi_i : in std_logic;
q_a_i : in std_logic_vector ( 7 downto 0 );
q_x_i : in std_logic_vector ( 7 downto 0 );
q_y_i : in std_logic_vector ( 7 downto 0 );
rdy_i : in std_logic;
reg_0flag_i : in std_logic;
reg_1flag_i : in std_logic;
reg_6flag_i : in std_logic;
reg_7flag_i : in std_logic;
rst_rst_n_i : in std_logic;
so_n_i : in std_logic;
a_o : out std_logic_vector (15 downto 0);
adr_o : out std_logic_vector (15 downto 0);
ch_a_o : out std_logic_vector ( 7 downto 0 );
ch_b_o : out std_logic_vector ( 7 downto 0 );
d_o : out std_logic_vector ( 7 downto 0 );
d_regs_in_o : out std_logic_vector ( 7 downto 0 );
ld_o : out std_logic_vector ( 1 downto 0 );
ld_pc_o : out std_logic;
ld_sp_o : out std_logic;
load_regs_o : out std_logic;
offset_o : out std_logic_vector ( 15 downto 0 );
rd_o : out std_logic;
reg_0flag_o : out std_logic;
reg_1flag_o : out std_logic;
reg_3flag_o : out std_logic;
reg_7flag_o : out std_logic;
sync_o : out std_logic;
wr_n_o : out std_logic;
wr_o : out std_logic;
sel_alu_as_o_i : inout std_logic;
sel_alu_out_o_i : inout std_logic_vector ( 2 downto 0 );
sel_pc_as_o_i : inout std_logic;
sel_pc_in_o_i : inout std_logic_vector ( 1 downto 0 );
sel_pc_val_o_i : inout std_logic_vector ( 1 downto 0 );
sel_rb_in_o_i : inout std_logic_vector ( 2 downto 0 );
sel_rb_out_o_i : inout std_logic_vector ( 2 downto 0 );
sel_reg_o_i : inout std_logic_vector ( 1 downto 0 );
sel_sp_as_o_i : inout std_logic;
sel_sp_in_o_i : inout std_logic_vector ( 1 downto 0 );
sel_sp_val_o_i : inout std_logic_vector ( 1 downto 0 )
);
-- Declarations
end fsm_core_V2_0 ;
-- Jens-D. Gutschmidt Project: R6502_TC
-- [email protected]
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- CVS Revisins History
--
-- $Log: not supported by cvs2svn $
--
-- Title: FSM for all op codes
-- Path: R6502_TC/fsm_core_V2_0/fsm
-- Edited: by eda on 08 Apr 2008
--
-- VHDL Architecture R6502_TC.fsm_core_V2_0.fsm
--
-- Created:
-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
-- at - 19:06:56 08.04.2008
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
architecture fsm of fsm_core_V2_0 is
-- Architecture Declarations
signal reg_F : std_logic_vector( 7 DOWNTO 0 );
signal reg_PC : std_logic_vector(15 DOWNTO 0);
signal reg_PC1 : std_logic_vector( 15 DOWNTO 0 );
signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 );
signal sig_PC : std_logic_vector(15 DOWNTO 0);
signal sig_RD : std_logic;
signal sig_RWn : std_logic;
signal sig_SYNC : std_logic;
signal sig_WR : std_logic;
signal zw_ALU : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU1 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU2 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU3 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU4 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU5 : std_logic_vector( 8 DOWNTO 0 );
signal zw_ALU6 : std_logic_vector( 8 DOWNTO 0 );
signal zw_PC : std_logic_vector( 15 DOWNTO 0 );
signal zw_REG_ALU : std_logic_vector( 8 DOWNTO 0 );
signal zw_REG_NMI : std_logic;
signal zw_REG_OP : std_logic_vector( 7 DOWNTO 0 );
signal zw_REG_sig_PC : std_logic_vector(15 DOWNTO 0);
signal zw_b1 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b2 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b3 : std_logic_vector( 7 DOWNTO 0 );
signal zw_b4 : std_logic_vector( 7 DOWNTO 0 );
signal zw_w1 : std_logic_vector( 15 DOWNTO 0 );
signal zw_w2 : std_logic_vector( 15 DOWNTO 0 );
signal zw_w3 : std_logic_vector( 15 DOWNTO 0 );
subtype state_type is
std_logic_vector(7 downto 0);
-- State vector declaration
attribute state_vector : string;
attribute state_vector of fsm : architecture is "current_state";
-- Hard encoding
constant FETCH : state_type := "00000000";
constant s1 : state_type := "00000001";
constant s2 : state_type := "00000011";
constant s5 : state_type := "00000010";
constant s3 : state_type := "00000110";
constant s4 : state_type := "00000111";
constant s12 : state_type := "00000101";
constant s16 : state_type := "00000100";
constant s17 : state_type := "00001100";
constant s24 : state_type := "00001101";
constant s25 : state_type := "00001111";
constant s271 : state_type := "00001110";
constant s273 : state_type := "00001010";
constant s304 : state_type := "00001011";
constant s307 : state_type := "00001001";
constant s177 : state_type := "00001000";
constant s180 : state_type := "00011000";
constant s181 : state_type := "00011001";
constant s182 : state_type := "00011011";
constant s183 : state_type := "00011010";
constant s184 : state_type := "00011110";
constant s185 : state_type := "00011111";
constant s186 : state_type := "00011101";
constant s187 : state_type := "00011100";
constant s188 : state_type := "00010100";
constant s189 : state_type := "00010101";
constant s190 : state_type := "00010111";
constant s191 : state_type := "00010110";
constant s192 : state_type := "00010010";
constant s193 : state_type := "00010011";
constant s377 : state_type := "00010001";
constant s381 : state_type := "00010000";
constant s378 : state_type := "00110000";
constant s382 : state_type := "00110001";
constant s379 : state_type := "00110011";
constant s383 : state_type := "00110010";
constant s384 : state_type := "00110110";
constant s380 : state_type := "00110111";
constant s385 : state_type := "00110101";
constant s386 : state_type := "00110100";
constant s387 : state_type := "00111100";
constant s388 : state_type := "00111101";
constant s389 : state_type := "00111111";
constant s391 : state_type := "00111110";
constant s392 : state_type := "00111010";
constant s390 : state_type := "00111011";
constant s393 : state_type := "00111001";
constant s394 : state_type := "00111000";
constant s395 : state_type := "00101000";
constant s396 : state_type := "00101001";
constant s397 : state_type := "00101011";
constant s398 : state_type := "00101010";
constant s399 : state_type := "00101110";
constant s400 : state_type := "00101111";
constant s401 : state_type := "00101101";
constant s526 : state_type := "00101100";
constant s527 : state_type := "00100100";
constant s528 : state_type := "00100101";
constant s529 : state_type := "00100111";
constant s530 : state_type := "00100110";
constant s531 : state_type := "00100010";
constant s544 : state_type := "00100011";
constant s545 : state_type := "00100001";
constant s546 : state_type := "00100000";
constant s547 : state_type := "01100000";
constant s549 : state_type := "01100001";
constant s550 : state_type := "01100011";
constant s404 : state_type := "01100010";
constant s556 : state_type := "01100110";
constant s557 : state_type := "01100111";
constant s579 : state_type := "01100101";
constant s201 : state_type := "01100100";
constant s202 : state_type := "01101100";
constant s210 : state_type := "01101101";
constant s211 : state_type := "01101111";
constant s215 : state_type := "01101110";
constant s217 : state_type := "01101010";
constant s218 : state_type := "01101011";
constant s222 : state_type := "01101001";
constant s223 : state_type := "01101000";
constant s224 : state_type := "01111000";
constant s225 : state_type := "01111001";
constant s226 : state_type := "01111011";
constant s243 : state_type := "01111010";
constant s244 : state_type := "01111110";
constant s247 : state_type := "01111111";
constant s344 : state_type := "01111101";
constant s343 : state_type := "01111100";
constant s250 : state_type := "01110100";
constant s251 : state_type := "01110101";
constant s351 : state_type := "01110111";
constant s361 : state_type := "01110110";
constant s360 : state_type := "01110010";
constant s403 : state_type := "01110011";
constant s406 : state_type := "01110001";
constant s407 : state_type := "01110000";
constant s409 : state_type := "01010000";
constant s412 : state_type := "01010001";
constant s413 : state_type := "01010011";
constant s416 : state_type := "01010010";
constant s418 : state_type := "01010110";
constant s510 : state_type := "01010111";
constant s553 : state_type := "01010101";
constant s555 : state_type := "01010100";
constant s558 : state_type := "01011100";
constant s560 : state_type := "01011101";
constant s561 : state_type := "01011111";
constant s563 : state_type := "01011110";
constant s564 : state_type := "01011010";
constant s565 : state_type := "01011011";
constant s566 : state_type := "01011001";
constant s266 : state_type := "01011000";
constant s301 : state_type := "01001000";
constant s302 : state_type := "01001001";
constant RES : state_type := "01001011";
constant s511 : state_type := "01001010";
constant s559 : state_type := "01001110";
constant s562 : state_type := "01001111";
constant s567 : state_type := "01001101";
constant s568 : state_type := "01001100";
constant s569 : state_type := "01000100";
constant s570 : state_type := "01000101";
constant s571 : state_type := "01000111";
constant s572 : state_type := "01000110";
constant s573 : state_type := "01000010";
constant s574 : state_type := "01000011";
constant s548 : state_type := "01000001";
constant s551 : state_type := "01000000";
constant s552 : state_type := "11000000";
constant s575 : state_type := "11000001";
constant s576 : state_type := "11000011";
constant s577 : state_type := "11000010";
constant s532 : state_type := "11000110";
constant s533 : state_type := "11000111";
constant s534 : state_type := "11000101";
constant s535 : state_type := "11000100";
constant s536 : state_type := "11001100";
constant s537 : state_type := "11001101";
-- Declare current and next state signals
signal current_state : state_type;
signal next_state : state_type;
-- Declare any pre-registered internal signals
signal d_o_cld : std_logic_vector ( 7 downto 0 );
signal rd_o_cld : std_logic ;
signal sync_o_cld : std_logic ;
signal wr_n_o_cld : std_logic ;
signal wr_o_cld : std_logic ;
signal sel_alu_as_o_i_cld : std_logic ;
signal sel_alu_out_o_i_cld : std_logic_vector ( 2 downto 0 );
signal sel_pc_as_o_i_cld : std_logic ;
signal sel_pc_in_o_i_cld : std_logic_vector ( 1 downto 0 );
signal sel_pc_val_o_i_cld : std_logic_vector ( 1 downto 0 );
signal sel_rb_in_o_i_cld : std_logic_vector ( 2 downto 0 );
signal sel_rb_out_o_i_cld : std_logic_vector ( 2 downto 0 );
signal sel_reg_o_i_cld : std_logic_vector ( 1 downto 0 );
signal sel_sp_as_o_i_cld : std_logic ;
signal sel_sp_in_o_i_cld : std_logic_vector ( 1 downto 0 );
signal sel_sp_val_o_i_cld : std_logic_vector ( 1 downto 0 );
begin
-----------------------------------------------------------------
clocked_proc : process (
clk_clk_i,
rst_rst_n_i
)
-----------------------------------------------------------------
begin
if (rst_rst_n_i = '0') then
current_state <= RES;
-- Default Reset Values
d_o_cld <= X"00";
rd_o_cld <= '0';
sync_o_cld <= '0';
wr_n_o_cld <= '1';
wr_o_cld <= '0';
sel_alu_as_o_i_cld <= '0';
sel_alu_out_o_i_cld <= "000";
sel_pc_as_o_i_cld <= '0';
sel_pc_in_o_i_cld <= "00";
sel_pc_val_o_i_cld <= "00";
sel_rb_in_o_i_cld <= "000";
sel_rb_out_o_i_cld <= "000";
sel_reg_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '0';
sel_sp_in_o_i_cld <= "00";
sel_sp_val_o_i_cld <= "00";
reg_F <= "00000100";
reg_PC <= X"0000";
reg_PC1 <= X"0000";
sig_PC <= X"0000";
zw_PC <= X"0000";
zw_REG_ALU <= '0' & X"00";
zw_REG_NMI <= '0';
zw_REG_OP <= X"00";
zw_REG_sig_PC <= X"0000";
zw_b1 <= X"00";
zw_b2 <= X"00";
zw_b3 <= X"00";
zw_b4 <= X"00";
zw_w1 <= X"0000";
zw_w2 <= X"0000";
zw_w3 <= X"0000";
elsif (clk_clk_i'event and clk_clk_i = '1') then
current_state <= next_state;
-- Default Assignment To Internals
reg_F <= reg_F or ('0' & (not so_n_i) & "000000");
reg_PC <= reg_PC;
reg_PC1 <= reg_PC1;
sig_PC <= sig_PC;
zw_PC <= zw_PC;
zw_REG_ALU <= zw_REG_ALU;
zw_REG_NMI <= zw_REG_NMI or nmi_i;
zw_REG_OP <= zw_REG_OP;
zw_REG_sig_PC <= zw_REG_sig_PC;
zw_b1 <= zw_b1;
zw_b2 <= zw_b2;
zw_b3 <= zw_b3;
zw_b4 <= zw_b4;
zw_w1 <= zw_w1;
zw_w2 <= zw_w2;
zw_w3 <= zw_w3;
d_o_cld <= sig_D_OUT;
rd_o_cld <= sig_RD;
sync_o_cld <= sig_SYNC;
wr_n_o_cld <= sig_RWn;
wr_o_cld <= sig_WR;
sel_alu_as_o_i_cld <= sel_alu_as_o_i;
sel_alu_out_o_i_cld <= sel_alu_out_o_i;
sel_pc_as_o_i_cld <= sel_pc_as_o_i;
sel_pc_in_o_i_cld <= sel_pc_in_o_i;
sel_pc_val_o_i_cld <= sel_pc_val_o_i;
sel_rb_in_o_i_cld <= sel_rb_in_o_i;
sel_rb_out_o_i_cld <= sel_rb_out_o_i;
sel_reg_o_i_cld <= sel_reg_o_i;
sel_sp_as_o_i_cld <= sel_sp_as_o_i;
sel_sp_in_o_i_cld <= sel_sp_in_o_i;
sel_sp_val_o_i_cld <= sel_sp_val_o_i;
-- Combined Actions
case current_state is
when FETCH =>
zw_REG_OP <= d_i;
if ((zw_REG_NMI = '1') and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '0';
sel_sp_val_o_i_cld <= "00";
zw_REG_NMI <= '0';
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '0';
sel_sp_val_o_i_cld <= "00";
elsif ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sel_reg_o_i_cld <= "00";
sel_rb_in_o_i_cld <= "011";
zw_b1(0) <= reg_F(7);
elsif ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
zw_b3 <= adr_nxt_pc_i (15 downto 8);
elsif ((d_i = X"24" or
d_i = X"2C") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"00") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '0';
sel_sp_val_o_i_cld <= "00";
elsif ((d_i = X"18") and (rdy_i = '1')) then
elsif ((d_i = X"D8") and (rdy_i = '1')) then
elsif ((d_i = X"58") and (rdy_i = '1')) then
elsif ((d_i = X"B8") and (rdy_i = '1')) then
elsif ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "001";
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "010";
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") and (rdy_i = '1')) then
zw_b4 <= X"FF";
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"CA") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "001";
sel_reg_o_i_cld <= "01";
sel_rb_in_o_i_cld <= "011";
zw_b4 <= X"FF";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"88") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "010";
sel_reg_o_i_cld <= "10";
sel_rb_in_o_i_cld <= "011";
zw_b4 <= X"FF";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
d_i = X"5D" or
d_i = X"59" or
d_i = X"41" or
d_i = X"51" or
d_i = X"09" or
d_i = X"05" or
d_i = X"15" or
d_i = X"0D" or
d_i = X"1D" or
d_i = X"19" or
d_i = X"01" or
d_i = X"11" or
d_i = X"29" or
d_i = X"25" or
d_i = X"35" or
d_i = X"2D" or
d_i = X"3D" or
d_i = X"39" or
d_i = X"21" or
d_i = X"31" or
d_i = X"C9" or
d_i = X"C5" or
d_i = X"D5" or
d_i = X"CD" or
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "000";
sel_reg_o_i_cld <= "00";
sel_rb_in_o_i_cld <= "011";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") and (rdy_i = '1')) then
zw_b4 <= X"01";
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"E8") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "001";
sel_reg_o_i_cld <= "01";
sel_rb_in_o_i_cld <= "011";
zw_b4 <= X"01";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"C8") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "010";
sel_reg_o_i_cld <= "10";
sel_rb_in_o_i_cld <= "011";
zw_b4 <= X"01";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"4C" or
d_i = X"6C") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"20") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") and (rdy_i = '1')) then
sel_reg_o_i_cld <= "00";
sel_rb_in_o_i_cld <= "011";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") and (rdy_i = '1')) then
sel_reg_o_i_cld <= "01";
sel_rb_in_o_i_cld <= "011";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") and (rdy_i = '1')) then
sel_reg_o_i_cld <= "10";
sel_rb_in_o_i_cld <= "011";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"EA") and (rdy_i = '1')) then
elsif ((d_i = X"48") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"08") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"68") and (rdy_i = '1')) then
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '0';
sel_sp_val_o_i_cld <= "00";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sel_reg_o_i_cld <= "00";
sel_rb_in_o_i_cld <= "011";
elsif ((d_i = X"28") and (rdy_i = '1')) then
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '0';
sel_sp_val_o_i_cld <= "00";
elsif ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"40") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
elsif ((d_i = X"60") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '0';
sel_sp_val_o_i_cld <= "00";
elsif ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") and (rdy_i = '1')) then
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sel_reg_o_i_cld <= "00";
sel_rb_in_o_i_cld <= "011";
zw_b1(0) <= reg_F(7);
elsif ((d_i = X"38") and (rdy_i = '1')) then
elsif ((d_i = X"F8") and (rdy_i = '1')) then
elsif ((d_i = X"78") and (rdy_i = '1')) then
elsif ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91" or
d_i = X"11") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "000";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "001";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "010";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sig_PC <= adr_nxt_pc_i;
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"AA") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "000";
sel_reg_o_i_cld <= "01";
sel_rb_in_o_i_cld <= "000";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sel_sp_in_o_i_cld <= "01";
sel_sp_as_o_i_cld <= '0';
sel_sp_val_o_i_cld <= "00";
elsif ((d_i = X"0A") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "000";
sel_reg_o_i_cld <= "00";
sel_rb_in_o_i_cld <= "011";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"4A") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "000";
sel_reg_o_i_cld <= "00";
sel_rb_in_o_i_cld <= "011";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"2A") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "000";
sel_reg_o_i_cld <= "00";
sel_rb_in_o_i_cld <= "011";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"6A") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "000";
sel_reg_o_i_cld <= "00";
sel_rb_in_o_i_cld <= "011";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
elsif ((d_i = X"A8") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "000";
sel_reg_o_i_cld <= "10";
sel_rb_in_o_i_cld <= "000";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sel_sp_in_o_i_cld <= "01";
sel_sp_as_o_i_cld <= '0';
sel_sp_val_o_i_cld <= "00";
elsif ((d_i = X"98") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "010";
sel_reg_o_i_cld <= "00";
sel_rb_in_o_i_cld <= "001";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sel_sp_in_o_i_cld <= "01";
sel_sp_as_o_i_cld <= '0';
sel_sp_val_o_i_cld <= "00";
elsif ((d_i = X"BA") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "001";
sel_reg_o_i_cld <= "01";
sel_rb_in_o_i_cld <= "011";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sel_sp_in_o_i_cld <= "01";
sel_sp_as_o_i_cld <= '0';
sel_sp_val_o_i_cld <= "00";
elsif ((d_i = X"8A") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "001";
sel_reg_o_i_cld <= "00";
sel_rb_in_o_i_cld <= "010";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sel_sp_in_o_i_cld <= "01";
sel_sp_as_o_i_cld <= '0';
sel_sp_val_o_i_cld <= "00";
elsif ((d_i = X"9A") and (rdy_i = '1')) then
sel_rb_out_o_i_cld <= "001";
sel_reg_o_i_cld <= "11";
sel_rb_in_o_i_cld <= "111";
sel_alu_out_o_i_cld <= "110";
sel_alu_as_o_i_cld <= '0';
sel_sp_in_o_i_cld <= "01";
sel_sp_as_o_i_cld <= '0';
sel_sp_val_o_i_cld <= "00";
end if;
when s1 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s2 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= '1';
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s5 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(3) <= '1';
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s3 =>
sig_PC <= adr_pc_i;
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(2) <= '1';
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s4 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
sig_PC <= adr_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s12 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= '0';
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s16 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(3) <= '0';
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s17 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(2) <= '0';
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s24 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(6) <= '0';
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s25 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s271 =>
if (rdy_i = '1' and
zw_REG_OP = X"4C") then
sig_PC <= adr_nxt_pc_i;
sel_pc_in_o_i_cld <= "01";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "11";
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"6C") then
sig_PC <= adr_nxt_pc_i;
sel_pc_in_o_i_cld <= "01";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
zw_b1 <= d_i;
end if;
when s273 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
end if;
when s304 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
sel_pc_in_o_i_cld <= "01";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "11";
zw_b1 <= d_i;
end if;
when s307 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s177 =>
if (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"9D") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
end if;
when s180 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s181 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s182 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s183 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s184 =>
sig_PC <= adr_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
when s185 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s186 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s187 =>
sig_PC <= adr_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
when s188 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s189 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s190 =>
sig_PC <= adr_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
when s191 =>
sig_PC <= zw_b3 & zw_b1;
when s192 =>
sig_PC <= d_i & zw_b1;
when s193 =>
sig_PC <= adr_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
when s377 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s381 =>
sig_PC <= adr_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
when s378 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s382 =>
sig_PC <= adr_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
when s383 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s384 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s385 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s386 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F <= d_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s387 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s388 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s389 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
reg_F <= d_i;
sel_pc_in_o_i_cld <= "01";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "11";
end if;
when s391 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
end if;
when s392 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s390 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s393 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s394 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
sel_pc_in_o_i_cld <= "01";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
end if;
when s395 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s396 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s397 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
zw_b1 <= d_i;
end if;
when s399 =>
sig_PC <= adr_sp_i;
when s400 =>
sig_PC <= adr_pc_i;
sel_pc_in_o_i_cld <= "01";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "11";
when s401 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1 (7 downto 0);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s526 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s527 =>
sig_PC <= adr_sp_i;
when s528 =>
sig_PC <= adr_sp_i;
when s529 =>
sig_PC <= X"FFFE";
when s530 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_F(4) <= '1';
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s531 =>
if (rdy_i = '1') then
sig_PC <= X"FFFF";
zw_b1 <= d_i;
end if;
when s544 =>
sig_PC <= adr_sp_i;
when s545 =>
sig_PC <= adr_sp_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
when s546 =>
sig_PC <= adr_pc_i;
when s547 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
zw_w1 (7 downto 0) <= d_i;
sel_pc_in_o_i_cld <= "01";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "11";
end if;
when s549 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_w1 (7 downto 0);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s550 =>
sig_PC <= adr_sp_i;
sel_pc_in_o_i_cld <= "01";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
when s404 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(7);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s556 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s557 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(7);
reg_F(0) <= q_a_i(7);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s579 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(0) <= q_a_i(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s201 =>
if (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
sig_PC <= X"00" & d_i;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
zw_REG_OP = X"4D" OR
zw_REG_OP = X"0D" OR
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
end if;
when s202 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s210 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s211 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s215 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s217 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s218 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s222 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s223 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s224 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s225 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(0) <= zw_ALU(8);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s226 =>
if (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s243 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s244 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s247 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s344 =>
if (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s343 =>
if (rdy_i = '1') then
zw_b1 <= d_alu_i;
end if;
when s251 =>
sig_PC <= adr_pc_i;
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
when s351 =>
if (rdy_i = '1' and
zw_REG_OP = X"24") then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
end if;
when s361 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= d_i(7);
reg_F(6) <= d_i(6);
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s360 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s403 =>
if (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
end if;
when s406 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s407 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s409 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s412 =>
if (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s416 =>
if (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) then
zw_b1 <= d_i(6 downto 0) & '0';
zw_b2(0) <= d_i(7);
elsif (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) then
zw_b1 <= '0' & d_i(7 downto 1);
zw_b2(0) <= d_i(0);
elsif (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) then
zw_b1 <= d_i(6 downto 0) & reg_F(0);
zw_b2(0) <= d_i(7);
elsif (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) then
zw_b1 <= reg_F(0) & d_i(7 downto 1);
zw_b2(0) <= d_i(0);
end if;
when s418 =>
sig_PC <= adr_pc_i;
reg_F(0) <= zw_b2(0);
reg_F(7) <= reg_7flag_i;
reg_F(1) <= reg_1flag_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
when s510 =>
if (rdy_i = '1' and
zw_REG_OP = X"65") then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s553 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s555 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s558 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s560 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s561 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s563 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s564 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s565 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU4(4);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s566 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s266 =>
if (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
(reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) then
sig_PC <= adr_nxt_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1') then
sig_PC <= adr_nxt_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "10";
zw_b2 <= d_i;
end if;
when s301 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
sig_PC <= adr_nxt_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0);
end if;
when s302 =>
if (rdy_i = '1') then
sig_PC <= adr_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when RES =>
sel_pc_in_o_i_cld <= "00";
sel_pc_val_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sig_PC <= adr_nxt_pc_i;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
when s511 =>
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
sig_PC <= X"00" & d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
sig_PC <= adr_nxt_pc_i;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
sig_PC <= X"00" & d_i;
zw_b1 <= d_alu_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') then
sig_PC <= adr_nxt_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU2(4);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s559 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
end if;
when s562 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s567 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s568 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
zw_b1 <= d_alu_i;
zw_b2(0) <= reg_0flag_i;
end if;
when s569 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s570 =>
if (rdy_i = '1') then
sig_PC <= X"00" & zw_b1;
end if;
when s571 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
zw_b3 <= d_alu_i;
end if;
when s572 =>
if (rdy_i = '1') then
sig_PC <= X"00" & d_alu_i;
zw_b1 <= d_i;
end if;
when s573 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU2(4);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1') then
sig_PC <= zw_b3 & zw_b1;
end if;
when s574 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU(8);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
elsif (rdy_i = '1' and
reg_F(3) = '1') then
sig_PC <= adr_pc_i;
reg_F(7) <= zw_ALU(7);
reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
(zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
(zw_ALU(0)));
reg_F(0) <= zw_ALU2(4);
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s548 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s551 =>
sig_PC <= adr_sp_i;
when s552 =>
sig_PC <= adr_sp_i;
when s575 =>
if (rdy_i = '1') then
sig_PC <= X"FFFF";
zw_b1 <= d_i;
end if;
when s576 =>
sig_PC <= X"FFFE";
when s577 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
reg_F(2) <= '1';
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when s532 =>
if (rdy_i = '1') then
sig_PC <= adr_sp_i;
end if;
when s533 =>
sig_PC <= adr_sp_i;
when s534 =>
sig_PC <= adr_sp_i;
when s535 =>
if (rdy_i = '1') then
sig_PC <= X"FFFB";
zw_b1 <= d_i;
end if;
when s536 =>
sig_PC <= X"FFFA";
when s537 =>
if (rdy_i = '1') then
sig_PC <= d_i & zw_b1;
sel_pc_in_o_i_cld <= "00";
sel_pc_as_o_i_cld <= '0';
sel_pc_val_o_i_cld <= "00";
sel_sp_in_o_i_cld <= "00";
sel_sp_as_o_i_cld <= '1';
sel_sp_val_o_i_cld <= "00";
end if;
when others =>
null;
end case;
end if;
end process clocked_proc;
-----------------------------------------------------------------
nextstate_proc : process (
adr_nxt_pc_i,
current_state,
d_i,
irq_n_i,
rdy_i,
reg_F,
zw_REG_NMI,
zw_REG_OP,
zw_b2,
zw_b3
)
-----------------------------------------------------------------
begin
case current_state is
when FETCH =>
if ((zw_REG_NMI = '1') and (rdy_i = '1')) then
next_state <= s532;
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
next_state <= s548;
elsif ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") and (rdy_i = '1')) then
next_state <= s510;
elsif ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") and (rdy_i = '1')) then
next_state <= s403;
elsif ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") and (rdy_i = '1')) then
next_state <= s266;
elsif ((d_i = X"24" or
d_i = X"2C") and (rdy_i = '1')) then
next_state <= s351;
elsif ((d_i = X"00") and (rdy_i = '1')) then
next_state <= s526;
elsif ((d_i = X"18") and (rdy_i = '1')) then
next_state <= s12;
elsif ((d_i = X"D8") and (rdy_i = '1')) then
next_state <= s16;
elsif ((d_i = X"58") and (rdy_i = '1')) then
next_state <= s17;
elsif ((d_i = X"B8") and (rdy_i = '1')) then
next_state <= s24;
elsif ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") and (rdy_i = '1')) then
next_state <= s201;
elsif ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") and (rdy_i = '1')) then
next_state <= s201;
elsif ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") and (rdy_i = '1')) then
next_state <= s226;
elsif ((d_i = X"CA") and (rdy_i = '1')) then
next_state <= s25;
elsif ((d_i = X"88") and (rdy_i = '1')) then
next_state <= s25;
elsif ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
d_i = X"5D" or
d_i = X"59" or
d_i = X"41" or
d_i = X"51" or
d_i = X"09" or
d_i = X"05" or
d_i = X"15" or
d_i = X"0D" or
d_i = X"1D" or
d_i = X"19" or
d_i = X"01" or
d_i = X"11" or
d_i = X"29" or
d_i = X"25" or
d_i = X"35" or
d_i = X"2D" or
d_i = X"3D" or
d_i = X"39" or
d_i = X"21" or
d_i = X"31" or
d_i = X"C9" or
d_i = X"C5" or
d_i = X"D5" or
d_i = X"CD" or
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") and (rdy_i = '1')) then
next_state <= s201;
elsif ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") and (rdy_i = '1')) then
next_state <= s226;
elsif ((d_i = X"E8") and (rdy_i = '1')) then
next_state <= s25;
elsif ((d_i = X"C8") and (rdy_i = '1')) then
next_state <= s25;
elsif ((d_i = X"4C" or
d_i = X"6C") and (rdy_i = '1')) then
next_state <= s271;
elsif ((d_i = X"20") and (rdy_i = '1')) then
next_state <= s397;
elsif ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") and (rdy_i = '1')) then
next_state <= s201;
elsif ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") and (rdy_i = '1')) then
next_state <= s201;
elsif ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") and (rdy_i = '1')) then
next_state <= s201;
elsif ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") and (rdy_i = '1')) then
next_state <= s403;
elsif ((d_i = X"EA") and (rdy_i = '1')) then
next_state <= s1;
elsif ((d_i = X"48") and (rdy_i = '1')) then
next_state <= s377;
elsif ((d_i = X"08") and (rdy_i = '1')) then
next_state <= s378;
elsif ((d_i = X"68") and (rdy_i = '1')) then
next_state <= s379;
elsif ((d_i = X"28") and (rdy_i = '1')) then
next_state <= s380;
elsif ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") and (rdy_i = '1')) then
next_state <= s403;
elsif ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") and (rdy_i = '1')) then
next_state <= s403;
elsif ((d_i = X"40") and (rdy_i = '1')) then
next_state <= s387;
elsif ((d_i = X"60") and (rdy_i = '1')) then
next_state <= s390;
elsif ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") and (rdy_i = '1')) then
next_state <= s511;
elsif ((d_i = X"38") and (rdy_i = '1')) then
next_state <= s2;
elsif ((d_i = X"F8") and (rdy_i = '1')) then
next_state <= s5;
elsif ((d_i = X"78") and (rdy_i = '1')) then
next_state <= s3;
elsif ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91" or
d_i = X"11") and (rdy_i = '1')) then
next_state <= s177;
elsif ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") and (rdy_i = '1')) then
next_state <= s177;
elsif ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") and (rdy_i = '1')) then
next_state <= s177;
elsif ((d_i = X"AA") and (rdy_i = '1')) then
next_state <= s4;
elsif ((d_i = X"0A") and (rdy_i = '1')) then
next_state <= s404;
elsif ((d_i = X"4A") and (rdy_i = '1')) then
next_state <= s556;
elsif ((d_i = X"2A") and (rdy_i = '1')) then
next_state <= s557;
elsif ((d_i = X"6A") and (rdy_i = '1')) then
next_state <= s579;
elsif ((d_i = X"A8") and (rdy_i = '1')) then
next_state <= s4;
elsif ((d_i = X"98") and (rdy_i = '1')) then
next_state <= s4;
elsif ((d_i = X"BA") and (rdy_i = '1')) then
next_state <= s4;
elsif ((d_i = X"8A") and (rdy_i = '1')) then
next_state <= s4;
elsif ((d_i = X"9A") and (rdy_i = '1')) then
next_state <= s4;
elsif (rdy_i = '1') then
next_state <= s1;
else
next_state <= FETCH;
end if;
when s1 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s1;
end if;
when s2 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s2;
end if;
when s5 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s5;
end if;
when s3 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s3;
end if;
when s4 =>
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
next_state <= FETCH;
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s4;
end if;
when s12 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s12;
end if;
when s16 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s16;
end if;
when s17 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s17;
end if;
when s24 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s24;
end if;
when s25 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s25;
end if;
when s271 =>
if (rdy_i = '1' and
zw_REG_OP = X"4C") then
next_state <= s307;
elsif (rdy_i = '1' and
zw_REG_OP = X"6C") then
next_state <= s273;
else
next_state <= s271;
end if;
when s273 =>
if (rdy_i = '1') then
next_state <= s304;
else
next_state <= s273;
end if;
when s304 =>
if (rdy_i = '1') then
next_state <= s307;
else
next_state <= s304;
end if;
when s307 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s307;
end if;
when s177 =>
if (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) then
next_state <= s184;
elsif (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) then
next_state <= s185;
elsif (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) then
next_state <= s183;
elsif (rdy_i = '1' and
zw_REG_OP = X"9D") then
next_state <= s182;
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
next_state <= s180;
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
next_state <= s181;
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
next_state <= s186;
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
next_state <= s185;
else
next_state <= s177;
end if;
when s180 =>
if (rdy_i = '1') then
next_state <= s191;
else
next_state <= s180;
end if;
when s181 =>
if (rdy_i = '1') then
next_state <= s189;
else
next_state <= s181;
end if;
when s182 =>
if (rdy_i = '1') then
next_state <= s191;
else
next_state <= s182;
end if;
when s183 =>
if (rdy_i = '1') then
next_state <= s187;
else
next_state <= s183;
end if;
when s184 =>
next_state <= FETCH;
when s185 =>
if (rdy_i = '1') then
next_state <= s190;
else
next_state <= s185;
end if;
when s186 =>
if (rdy_i = '1') then
next_state <= s188;
else
next_state <= s186;
end if;
when s187 =>
next_state <= FETCH;
when s188 =>
if (rdy_i = '1') then
next_state <= s192;
else
next_state <= s188;
end if;
when s189 =>
if (rdy_i = '1') then
next_state <= s191;
else
next_state <= s189;
end if;
when s190 =>
next_state <= FETCH;
when s191 =>
next_state <= s193;
when s192 =>
next_state <= s193;
when s193 =>
next_state <= FETCH;
when s377 =>
if (rdy_i = '1') then
next_state <= s381;
else
next_state <= s377;
end if;
when s381 =>
next_state <= FETCH;
when s378 =>
if (rdy_i = '1') then
next_state <= s382;
else
next_state <= s378;
end if;
when s382 =>
next_state <= FETCH;
when s379 =>
if (rdy_i = '1') then
next_state <= s383;
else
next_state <= s379;
end if;
when s383 =>
if (rdy_i = '1') then
next_state <= s384;
else
next_state <= s383;
end if;
when s384 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s384;
end if;
when s380 =>
if (rdy_i = '1') then
next_state <= s385;
else
next_state <= s380;
end if;
when s385 =>
if (rdy_i = '1') then
next_state <= s386;
else
next_state <= s385;
end if;
when s386 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s386;
end if;
when s387 =>
if (rdy_i = '1') then
next_state <= s388;
else
next_state <= s387;
end if;
when s388 =>
if (rdy_i = '1') then
next_state <= s389;
else
next_state <= s388;
end if;
when s389 =>
if (rdy_i = '1') then
next_state <= s391;
else
next_state <= s389;
end if;
when s391 =>
if (rdy_i = '1') then
next_state <= s392;
else
next_state <= s391;
end if;
when s392 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s392;
end if;
when s390 =>
if (rdy_i = '1') then
next_state <= s393;
else
next_state <= s390;
end if;
when s393 =>
if (rdy_i = '1') then
next_state <= s394;
else
next_state <= s393;
end if;
when s394 =>
if (rdy_i = '1') then
next_state <= s395;
else
next_state <= s394;
end if;
when s395 =>
if (rdy_i = '1') then
next_state <= s396;
else
next_state <= s395;
end if;
when s396 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s396;
end if;
when s397 =>
if (rdy_i = '1') then
next_state <= s398;
else
next_state <= s397;
end if;
when s398 =>
if (rdy_i = '1') then
next_state <= s399;
else
next_state <= s398;
end if;
when s399 =>
next_state <= s400;
when s400 =>
next_state <= s401;
when s401 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s401;
end if;
when s526 =>
if (rdy_i = '1') then
next_state <= s527;
else
next_state <= s526;
end if;
when s527 =>
next_state <= s528;
when s528 =>
next_state <= s529;
when s529 =>
next_state <= s531;
when s530 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s530;
end if;
when s531 =>
if (rdy_i = '1') then
next_state <= s530;
else
next_state <= s531;
end if;
when s544 =>
next_state <= s550;
when s545 =>
next_state <= s546;
when s546 =>
next_state <= s547;
when s547 =>
if (rdy_i = '1') then
next_state <= s549;
else
next_state <= s547;
end if;
when s549 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s549;
end if;
when s550 =>
next_state <= s545;
when s404 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s404;
end if;
when s556 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s556;
end if;
when s557 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s557;
end if;
when s579 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s579;
end if;
when s201 =>
if (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
next_state <= s224;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
next_state <= FETCH;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
next_state <= FETCH;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
next_state <= FETCH;
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
next_state <= FETCH;
elsif (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
next_state <= FETCH;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) then
next_state <= s217;
elsif (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
zw_REG_OP = X"4D" OR
zw_REG_OP = X"0D" OR
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) then
next_state <= s202;
elsif (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) then
next_state <= s210;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) then
next_state <= s211;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) then
next_state <= s215;
elsif (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) then
next_state <= s218;
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
next_state <= s217;
else
next_state <= s201;
end if;
when s202 =>
if (rdy_i = '1') then
next_state <= s224;
else
next_state <= s202;
end if;
when s210 =>
if (rdy_i = '1') then
next_state <= s225;
else
next_state <= s210;
end if;
when s211 =>
if (rdy_i = '1') then
next_state <= s225;
else
next_state <= s211;
end if;
when s215 =>
if (rdy_i = '1') then
next_state <= s223;
else
next_state <= s215;
end if;
when s217 =>
if (rdy_i = '1') then
next_state <= s224;
else
next_state <= s217;
end if;
when s218 =>
if (rdy_i = '1') then
next_state <= s222;
else
next_state <= s218;
end if;
when s222 =>
if (rdy_i = '1') then
next_state <= s202;
else
next_state <= s222;
end if;
when s223 =>
if (rdy_i = '1') then
next_state <= s225;
else
next_state <= s223;
end if;
when s224 =>
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
next_state <= FETCH;
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
next_state <= FETCH;
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
next_state <= FETCH;
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s224;
end if;
when s225 =>
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
next_state <= FETCH;
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
next_state <= FETCH;
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
next_state <= FETCH;
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
next_state <= FETCH;
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s224;
else
next_state <= s225;
end if;
when s226 =>
if (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) then
next_state <= s343;
elsif (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) then
next_state <= s247;
elsif (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) then
next_state <= s243;
elsif (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) then
next_state <= s244;
else
next_state <= s226;
end if;
when s243 =>
if (rdy_i = '1') then
next_state <= s343;
else
next_state <= s243;
end if;
when s244 =>
if (rdy_i = '1') then
next_state <= s344;
else
next_state <= s244;
end if;
when s247 =>
if (rdy_i = '1') then
next_state <= s343;
else
next_state <= s247;
end if;
when s344 =>
if (rdy_i = '1') then
next_state <= s343;
else
next_state <= s344;
end if;
when s343 =>
if (rdy_i = '1') then
next_state <= s250;
else
next_state <= s343;
end if;
when s250 =>
if (rdy_i = '1') then
next_state <= s251;
else
next_state <= s250;
end if;
when s251 =>
next_state <= FETCH;
when s351 =>
if (rdy_i = '1' and
zw_REG_OP = X"24") then
next_state <= s361;
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
next_state <= s360;
else
next_state <= s351;
end if;
when s361 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s361;
end if;
when s360 =>
if (rdy_i = '1') then
next_state <= s361;
else
next_state <= s360;
end if;
when s403 =>
if (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) then
next_state <= s407;
elsif (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) then
next_state <= s413;
elsif (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) then
next_state <= s409;
elsif (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) then
next_state <= s406;
else
next_state <= s403;
end if;
when s406 =>
if (rdy_i = '1') then
next_state <= s413;
else
next_state <= s406;
end if;
when s407 =>
if (rdy_i = '1') then
next_state <= s412;
else
next_state <= s407;
end if;
when s409 =>
if (rdy_i = '1') then
next_state <= s413;
else
next_state <= s409;
end if;
when s412 =>
if (rdy_i = '1') then
next_state <= s413;
else
next_state <= s412;
end if;
when s413 =>
if (rdy_i = '1') then
next_state <= s416;
else
next_state <= s413;
end if;
when s416 =>
if (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) then
next_state <= s418;
elsif (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) then
next_state <= s418;
elsif (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) then
next_state <= s418;
elsif (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) then
next_state <= s418;
else
next_state <= s416;
end if;
when s418 =>
next_state <= FETCH;
when s510 =>
if (rdy_i = '1' and
zw_REG_OP = X"65") then
next_state <= s565;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
next_state <= s560;
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
next_state <= s553;
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
next_state <= s555;
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
next_state <= s555;
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
next_state <= s558;
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
next_state <= s561;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') then
next_state <= FETCH;
else
next_state <= s510;
end if;
when s553 =>
if (rdy_i = '1') then
next_state <= s565;
else
next_state <= s553;
end if;
when s555 =>
if (rdy_i = '1') then
next_state <= s564;
else
next_state <= s555;
end if;
when s558 =>
if (rdy_i = '1') then
next_state <= s566;
else
next_state <= s558;
end if;
when s560 =>
if (rdy_i = '1') then
next_state <= s565;
else
next_state <= s560;
end if;
when s561 =>
if (rdy_i = '1') then
next_state <= s563;
else
next_state <= s561;
end if;
when s563 =>
if (rdy_i = '1') then
next_state <= s553;
else
next_state <= s563;
end if;
when s564 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s565;
else
next_state <= s564;
end if;
when s565 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' and
reg_F(3) = '1') then
next_state <= FETCH;
else
next_state <= s565;
end if;
when s566 =>
if (rdy_i = '1') then
next_state <= s564;
else
next_state <= s566;
end if;
when s266 =>
if (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
(reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s301;
else
next_state <= s266;
end if;
when s301 =>
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s302;
else
next_state <= s301;
end if;
when s302 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s302;
end if;
when RES =>
next_state <= s544;
when s511 =>
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
next_state <= s574;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
next_state <= s569;
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
next_state <= s559;
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
next_state <= s562;
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
next_state <= s567;
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
next_state <= s568;
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
next_state <= s570;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') then
next_state <= FETCH;
else
next_state <= s511;
end if;
when s559 =>
if (rdy_i = '1') then
next_state <= s574;
else
next_state <= s559;
end if;
when s562 =>
if (rdy_i = '1') then
next_state <= s573;
else
next_state <= s562;
end if;
when s567 =>
if (rdy_i = '1') then
next_state <= s573;
else
next_state <= s567;
end if;
when s568 =>
if (rdy_i = '1') then
next_state <= s571;
else
next_state <= s568;
end if;
when s569 =>
if (rdy_i = '1') then
next_state <= s574;
else
next_state <= s569;
end if;
when s570 =>
if (rdy_i = '1') then
next_state <= s572;
else
next_state <= s570;
end if;
when s571 =>
if (rdy_i = '1') then
next_state <= s573;
else
next_state <= s571;
end if;
when s572 =>
if (rdy_i = '1') then
next_state <= s559;
else
next_state <= s572;
end if;
when s573 =>
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
next_state <= FETCH;
elsif (rdy_i = '1') then
next_state <= s574;
else
next_state <= s573;
end if;
when s574 =>
if (rdy_i = '1' and
reg_F(3) = '0') then
next_state <= FETCH;
elsif (rdy_i = '1' and
reg_F(3) = '1') then
next_state <= FETCH;
else
next_state <= s574;
end if;
when s548 =>
if (rdy_i = '1') then
next_state <= s551;
else
next_state <= s548;
end if;
when s551 =>
next_state <= s552;
when s552 =>
next_state <= s576;
when s575 =>
if (rdy_i = '1') then
next_state <= s577;
else
next_state <= s575;
end if;
when s576 =>
next_state <= s575;
when s577 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s577;
end if;
when s532 =>
if (rdy_i = '1') then
next_state <= s533;
else
next_state <= s532;
end if;
when s533 =>
next_state <= s534;
when s534 =>
next_state <= s536;
when s535 =>
if (rdy_i = '1') then
next_state <= s537;
else
next_state <= s535;
end if;
when s536 =>
next_state <= s535;
when s537 =>
if (rdy_i = '1') then
next_state <= FETCH;
else
next_state <= s537;
end if;
when others =>
next_state <= RES;
end case;
end process nextstate_proc;
-----------------------------------------------------------------
output_proc : process (
adr_nxt_pc_i,
adr_pc_i,
adr_sp_i,
current_state,
d_alu_i,
d_i,
d_regs_out_i,
irq_n_i,
q_a_i,
q_x_i,
q_y_i,
rdy_i,
reg_F,
sig_PC,
zw_ALU,
zw_ALU1,
zw_ALU2,
zw_ALU3,
zw_ALU4,
zw_ALU5,
zw_ALU6,
zw_REG_NMI,
zw_REG_OP,
zw_b1,
zw_b2,
zw_b3,
zw_b4,
zw_w1
)
-----------------------------------------------------------------
begin
-- Default Assignment
a_o <= sig_PC;
adr_o <= X"0000";
ch_a_o <= X"00";
ch_b_o <= X"00";
d_regs_in_o <= X"00";
ld_o <= "00";
ld_pc_o <= '0';
ld_sp_o <= '0';
load_regs_o <= '0';
offset_o <= X"0000";
reg_0flag_o <= reg_F(0);
reg_1flag_o <= reg_F(1);
reg_3flag_o <= reg_F(3);
reg_7flag_o <= reg_F(7);
-- Default Assignment To Internals
sig_D_OUT <= X"00";
sig_RD <= '0';
sig_RWn <= '1';
sig_SYNC <= '0';
sig_WR <= '0';
zw_ALU <= '0' & X"00";
zw_ALU1 <= '0' & X"00";
zw_ALU2 <= '0' & X"00";
zw_ALU3 <= '0' & X"00";
zw_ALU4 <= '0' & X"00";
zw_ALU5 <= '0' & X"00";
zw_ALU6 <= '0' & X"00";
-- Combined Actions
case current_state is
when FETCH =>
sig_RWn <= '1';
sig_RD <= '1';
sig_SYNC <= NOT (rdy_i);
if ((zw_REG_NMI = '1') and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((irq_n_i = '0' and
reg_F(2) = '0') and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"69" or
d_i = X"65" or
d_i = X"75" or
d_i = X"6D" or
d_i = X"7D" or
d_i = X"79" or
d_i = X"61" or
d_i = X"71") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"06" or
d_i = X"16" or
d_i = X"0E" or
d_i = X"1E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"90" or
d_i = X"B0" or
d_i = X"F0" or
d_i = X"30" or
d_i = X"D0" or
d_i = X"10" or
d_i = X"50" or
d_i = X"70") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"24" or
d_i = X"2C") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"00") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"18") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"D8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"58") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"B8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"E0" or
d_i = X"E4" or
d_i = X"EC") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"C0" or
d_i = X"C4" or
d_i = X"CC") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"C6" or
d_i = X"D6" or
d_i = X"CE" or
d_i = X"DE") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"CA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"88") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"49" or
d_i = X"45" or
d_i = X"55" or
d_i = X"4D" or
d_i = X"5D" or
d_i = X"59" or
d_i = X"41" or
d_i = X"51" or
d_i = X"09" or
d_i = X"05" or
d_i = X"15" or
d_i = X"0D" or
d_i = X"1D" or
d_i = X"19" or
d_i = X"01" or
d_i = X"11" or
d_i = X"29" or
d_i = X"25" or
d_i = X"35" or
d_i = X"2D" or
d_i = X"3D" or
d_i = X"39" or
d_i = X"21" or
d_i = X"31" or
d_i = X"C9" or
d_i = X"C5" or
d_i = X"D5" or
d_i = X"CD" or
d_i = X"DD" or
d_i = X"D9" or
d_i = X"C1" or
d_i = X"D1") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"E6" or
d_i = X"F6" or
d_i = X"EE" or
d_i = X"FE") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"E8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"C8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"4C" or
d_i = X"6C") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"20") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"A9" or
d_i = X"A5" or
d_i = X"B5" or
d_i = X"AD" or
d_i = X"BD" or
d_i = X"B9" or
d_i = X"A1" or
d_i = X"B1") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"A2" or
d_i = X"A6" or
d_i = X"B6" or
d_i = X"AE" or
d_i = X"BE") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"A0" or
d_i = X"A4" or
d_i = X"B4" or
d_i = X"AC" or
d_i = X"BC") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"46" or
d_i = X"56" or
d_i = X"4E" or
d_i = X"5E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"EA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"48") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"08") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"68") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"28") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"26" or
d_i = X"36" or
d_i = X"2E" or
d_i = X"3E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"66" or
d_i = X"76" or
d_i = X"6E" or
d_i = X"7E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"40") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"60") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"E9" or
d_i = X"E5" or
d_i = X"F5" or
d_i = X"ED" or
d_i = X"FD" or
d_i = X"F9" or
d_i = X"E1" or
d_i = X"F1") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"38") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"F8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"78") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"85" or
d_i = X"95" or
d_i = X"8D" or
d_i = X"9D" or
d_i = X"99" or
d_i = X"81" or
d_i = X"91" or
d_i = X"11") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"86" or
d_i = X"96" or
d_i = X"8E") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"84" or
d_i = X"94" or
d_i = X"8C") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"AA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"0A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"4A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"2A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"6A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"A8") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"98") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"BA") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"8A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((d_i = X"9A") and (rdy_i = '1')) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s1 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s2 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s5 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s3 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s4 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' and
zw_REG_OP = X"9A") then
adr_o <= X"01" & d_regs_out_i;
ld_o <= "11";
ld_sp_o <= '1';
sig_SYNC <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"BA") then
d_regs_in_o <= adr_sp_i (7 downto 0);
ch_a_o <= adr_sp_i (7 downto 0);
ch_b_o <= X"00";
load_regs_o <= '1';
sig_SYNC <= '1';
elsif (rdy_i = '1') then
ch_a_o <= d_regs_out_i;
ch_b_o <= X"00";
load_regs_o <= '1';
sig_SYNC <= '1';
end if;
when s12 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s16 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s17 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s24 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s25 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
d_regs_in_o <= d_alu_i;
ch_a_o <= d_regs_out_i;
ch_b_o <= zw_b4;
load_regs_o <= '1';
sig_SYNC <= '1';
end if;
when s271 =>
sig_RWn <= '1';
sig_RD <= '1';
when s273 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s304 =>
sig_RWn <= '1';
sig_RD <= '1';
when s307 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
end if;
when s177 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' and
(zw_REG_OP = X"85" OR
zw_REG_OP = X"86" OR
zw_REG_OP = X"84")) then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"95" OR
zw_REG_OP = X"94")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"8D" OR
zw_REG_OP = X"8E" OR
zw_REG_OP = X"8C")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"9D") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"99") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"91") then
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
zw_REG_OP = X"81") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"96") then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s180 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s181 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s182 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s183 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s184 =>
sig_RWn <= '1';
sig_RD <= '1';
sig_SYNC <= '1';
when s185 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s186 =>
sig_RWn <= '1';
sig_RD <= '1';
when s187 =>
sig_RWn <= '1';
sig_RD <= '1';
sig_SYNC <= '1';
when s188 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s189 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s190 =>
sig_RWn <= '1';
sig_RD <= '1';
sig_SYNC <= '1';
when s191 =>
sig_RWn <= '1';
sig_RD <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
when s192 =>
sig_RWn <= '1';
sig_RD <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= d_regs_out_i;
ld_o <= "11";
ld_pc_o <= '1';
when s193 =>
sig_RWn <= '1';
sig_RD <= '1';
sig_SYNC <= '1';
when s377 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= q_a_i;
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s381 =>
sig_RWn <= '1';
sig_RD <= '1';
sig_SYNC <= '1';
when s378 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F;
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s382 =>
sig_RWn <= '1';
sig_RD <= '1';
sig_SYNC <= '1';
when s379 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s383 =>
sig_RWn <= '1';
sig_RD <= '1';
when s384 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
end if;
when s380 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s385 =>
sig_RWn <= '1';
sig_RD <= '1';
when s386 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s387 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s388 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s389 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s391 =>
sig_RWn <= '1';
sig_RD <= '1';
when s392 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
end if;
when s390 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s393 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
end if;
when s394 =>
sig_RWn <= '1';
sig_RD <= '1';
when s395 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s396 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s397 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
end if;
when s398 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
end if;
when s399 =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
when s400 =>
sig_RWn <= '1';
sig_RD <= '1';
when s401 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_b1;
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
end if;
when s526 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
end if;
when s527 =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
when s528 =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
when s529 =>
sig_RWn <= '1';
sig_RD <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F;
when s530 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s531 =>
sig_RWn <= '1';
sig_RD <= '1';
when s544 =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
ld_sp_o <= '1';
when s545 =>
sig_RWn <= '1';
sig_RD <= '1';
adr_o <= X"FFFB";
ld_o <= "11";
ld_pc_o <= '1';
when s546 =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
ld_pc_o <= '1';
when s547 =>
sig_RWn <= '1';
sig_RD <= '1';
when s549 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
adr_o <= d_i & zw_w1 (7 downto 0);
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
end if;
when s550 =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
ld_sp_o <= '1';
when s404 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= q_a_i (6 downto 0) & '0';
ch_b_o <= X"00";
d_regs_in_o <= q_a_i (6 downto 0) & '0';
load_regs_o <= '1';
sig_SYNC <= '1';
end if;
when s556 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= '0' & q_a_i (7 downto 1);
ch_b_o <= X"00";
d_regs_in_o <= '0' & q_a_i (7 downto 1);
load_regs_o <= '1';
sig_SYNC <= '1';
end if;
when s557 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= q_a_i (6 downto 0) & reg_F(0);
ch_b_o <= X"00";
d_regs_in_o <= q_a_i (6 downto 0) & reg_F(0);
load_regs_o <= '1';
sig_SYNC <= '1';
end if;
when s579 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= reg_F(0) & q_a_i (7 downto 1);
ch_b_o <= X"00";
d_regs_in_o <= reg_F(0) & q_a_i (7 downto 1);
load_regs_o <= '1';
sig_SYNC <= '1';
end if;
when s201 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' and
(zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
ld_o <= "11";
ld_pc_o <= '1';
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"B5" OR
zw_REG_OP = X"B4" OR
zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
zw_REG_OP = X"35" OR
zw_REG_OP = X"D5")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"AD" OR
zw_REG_OP = X"AE" OR
zw_REG_OP = X"AC" OR
zw_REG_OP = X"4D" OR
zw_REG_OP = X"0D" OR
zw_REG_OP = X"2D" OR
zw_REG_OP = X"CD" OR
zw_REG_OP = X"EC" OR
zw_REG_OP = X"CC")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"BD" OR
zw_REG_OP = X"BC" OR
zw_REG_OP = X"5D" OR
zw_REG_OP = X"1D" OR
zw_REG_OP = X"3D" OR
zw_REG_OP = X"DD")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B9" OR
zw_REG_OP = X"BE" OR
zw_REG_OP = X"59" OR
zw_REG_OP = X"19" OR
zw_REG_OP = X"39" OR
zw_REG_OP = X"D9")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"B1" OR
zw_REG_OP = X"51" OR
zw_REG_OP = X"11" OR
zw_REG_OP = X"31" OR
zw_REG_OP = X"D1")) then
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
(zw_REG_OP = X"A1" OR
zw_REG_OP = X"41" OR
zw_REG_OP = X"01" OR
zw_REG_OP = X"21" OR
zw_REG_OP = X"C1")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"B6") then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s202 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s210 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s211 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s215 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s217 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s218 =>
sig_RWn <= '1';
sig_RD <= '1';
when s222 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s223 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s224 =>
sig_RWn <= '1';
sig_RD <= '1';
if ((rdy_i = '1') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
elsif (rdy_i = '1') then
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
end if;
when s225 =>
sig_RWn <= '1';
sig_RD <= '1';
if ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
zw_REG_OP = X"01" or zw_REG_OP = X"11")) then
d_regs_in_o <= d_i OR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i OR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
zw_REG_OP = X"41" or zw_REG_OP = X"51")) then
d_regs_in_o <= d_i XOR q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i XOR q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
zw_REG_OP = X"21" or zw_REG_OP = X"31")) then
d_regs_in_o <= d_i AND q_a_i;
load_regs_o <= '1';
ch_a_o <= d_i AND q_a_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
elsif ((rdy_i = '1' AND
zw_b2(0) = '0') and (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) then
zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
sig_SYNC <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0') then
d_regs_in_o <= d_i;
load_regs_o <= '1';
ch_a_o <= d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
end if;
when s226 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' and
(zw_REG_OP = X"C6" OR
zw_REG_OP = X"E6")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"D6" OR
zw_REG_OP = X"F6")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"CE" OR
zw_REG_OP = X"EE")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"DE" OR
zw_REG_OP = X"FE")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
end if;
when s243 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s244 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s247 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s344 =>
sig_RWn <= '1';
sig_RD <= '1';
when s343 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= zw_b4;
end if;
when s250 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= zw_b1;
end if;
when s251 =>
sig_RWn <= '1';
sig_RD <= '1';
ch_a_o <= zw_b1;
ch_b_o <= X"00";
sig_SYNC <= '1';
when s351 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' and
zw_REG_OP = X"24") then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"2C") then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s361 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= q_a_i AND d_i;
ch_b_o <= X"00";
sig_SYNC <= '1';
end if;
when s360 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s403 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' and
(zw_REG_OP = X"1E" or
zw_REG_OP = X"7E" or
zw_REG_OP = X"3E" or
zw_REG_OP = X"5E")) then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"66" or
zw_REG_OP = X"26" or
zw_REG_OP = X"46")) then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"16" or
zw_REG_OP = X"76" or
zw_REG_OP = X"36" or
zw_REG_OP = X"56")) then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
(zw_REG_OP = X"0E" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"4E")) then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s406 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s407 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= "0000000" & zw_b2(0);
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s409 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s412 =>
sig_RWn <= '1';
sig_RD <= '1';
when s413 =>
sig_RWn <= '1';
sig_RD <= '1';
when s416 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' and
(zw_REG_OP = X"06" or
zw_REG_OP = X"16" or
zw_REG_OP = X"0E" or
zw_REG_OP = X"1E")) then
sig_D_OUT <= d_i(6 downto 0) & '0';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"46" or
zw_REG_OP = X"56" or
zw_REG_OP = X"4E" or
zw_REG_OP = X"5E")) then
sig_D_OUT <= '0' & d_i(7 downto 1);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"26" or
zw_REG_OP = X"36" or
zw_REG_OP = X"2E" or
zw_REG_OP = X"3E")) then
sig_D_OUT <= d_i(6 downto 0) & reg_F(0);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
elsif (rdy_i = '1' and
(zw_REG_OP = X"66" or
zw_REG_OP = X"76" or
zw_REG_OP = X"6E" or
zw_REG_OP = X"7E")) then
sig_D_OUT <= reg_F(0) & d_i(7 downto 1);
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
end if;
when s418 =>
sig_RWn <= '1';
sig_RD <= '1';
ch_a_o <= zw_b1;
ch_b_o <= X"00";
sig_SYNC <= '1';
when s510 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' and
zw_REG_OP = X"65") then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '0') then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"75") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"6D") then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"7D") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"79") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"71") then
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
zw_REG_OP = X"61") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"69" and
reg_F(3) = '1') then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(7 downto 5));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(7 downto 5));
zw_ALU6(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0';
zw_ALU5(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0';
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
end if;
when s553 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s555 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s558 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s560 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s561 =>
sig_RWn <= '1';
sig_RD <= '1';
when s563 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s564 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(7 downto 5));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(7 downto 5));
zw_ALU6(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0';
zw_ALU5(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0';
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
end if;
when s565 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
sig_SYNC <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(7 downto 5));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(7 downto 5));
zw_ALU6(7 downto 5) <= (zw_ALU2(4) OR zw_ALU4(4)) & (zw_ALU2(4) OR zw_ALU4(4)) & '0';
zw_ALU5(7 downto 5) <= (zw_ALU1(4) OR zw_ALU3(4)) & (zw_ALU1(4) OR zw_ALU3(4)) & '0';
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & d_i(3 downto 0)) + reg_F(0);
sig_SYNC <= '1';
end if;
when s566 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s266 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' and (
(reg_F(0) = '1' and zw_REG_OP = X"90") or
(reg_F(0) = '0' and zw_REG_OP = X"B0") or
(reg_F(1) = '0' and zw_REG_OP = X"F0") or
(reg_F(7) = '0' and zw_REG_OP = X"30") or
(reg_F(1) = '1' and zw_REG_OP = X"D0") or
(reg_F(7) = '1' and zw_REG_OP = X"10") or
(reg_F(6) = '1' and zw_REG_OP = X"50") or
(reg_F(6) = '0' and zw_REG_OP = X"70"))) then
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
elsif (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s301 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' and
zw_b3 = adr_nxt_pc_i (15 downto 8)) then
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
ld_o <= "11";
ld_pc_o <= '1';
sig_SYNC <= '1';
elsif (rdy_i = '1') then
offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s302 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when RES =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
ld_pc_o <= '1';
ld_sp_o <= '1';
sig_RWn <= '1';
sig_RD <= '1';
when s511 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' and
zw_REG_OP = X"E5") then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '0') then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"F5") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"ED") then
ld_o <= "11";
ld_pc_o <= '1';
elsif (rdy_i = '1' and
zw_REG_OP = X"FD") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F9") then
ld_o <= "11";
ld_pc_o <= '1';
ch_a_o <= d_i;
ch_b_o <= q_y_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"F1") then
ch_a_o <= d_i;
ch_b_o <= X"01";
elsif (rdy_i = '1' and
zw_REG_OP = X"E1") then
ch_a_o <= d_i;
ch_b_o <= q_x_i;
elsif (rdy_i = '1' and
zw_REG_OP = X"E9" and
reg_F(3) = '1') then
ld_o <= "11";
ld_pc_o <= '1';
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) +
unsigned ((zw_ALU6(8 downto 5)));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) +
unsigned ((zw_ALU5(8 downto 5)));
zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' &
(zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' &
(zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
end if;
when s559 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s562 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s567 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s568 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= q_y_i;
end if;
when s569 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s570 =>
sig_RWn <= '1';
sig_RD <= '1';
when s571 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= d_i;
ch_b_o <= X"01";
ld_o <= "11";
ld_pc_o <= '1';
end if;
when s572 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ch_a_o <= zw_b1;
ch_b_o <= X"01";
end if;
when s573 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
elsif (rdy_i = '1' AND
zw_b2(0) = '0' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) +
unsigned ((zw_ALU6(8 downto 5)));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) +
unsigned ((zw_ALU5(8 downto 5)));
zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' &
(zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' &
(zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
end if;
when s574 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1' and
reg_F(3) = '0') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
sig_SYNC <= '1';
elsif (rdy_i = '1' and
reg_F(3) = '1') then
d_regs_in_o <= zw_ALU(7 downto 0);
load_regs_o <= '1';
zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) +
unsigned ((zw_ALU6(8 downto 5)));
zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) +
unsigned ((zw_ALU5(8 downto 5)));
zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' &
(zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' &
(zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
zw_ALU2(4 downto 0) <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned
('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
zw_ALU1(4 downto 0) <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned
('0' & NOT (d_i(3 downto 0))) + reg_F(0);
sig_SYNC <= '1';
end if;
when s548 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
end if;
when s551 =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
when s552 =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
when s575 =>
sig_RWn <= '1';
sig_RD <= '1';
when s576 =>
sig_RWn <= '1';
sig_RD <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F;
when s577 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when s532 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
ld_o <= "11";
ld_sp_o <= '1';
ld_pc_o <= '1';
end if;
when s533 =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (15 downto 8);
when s534 =>
sig_RWn <= '1';
sig_RD <= '1';
ld_o <= "11";
ld_sp_o <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= adr_pc_i (7 downto 0);
when s535 =>
sig_RWn <= '1';
sig_RD <= '1';
when s536 =>
sig_RWn <= '1';
sig_RD <= '1';
sig_RWn <= '0';
sig_RD <= '0';
sig_WR <= '1';
sig_D_OUT <= reg_F;
when s537 =>
sig_RWn <= '1';
sig_RD <= '1';
if (rdy_i = '1') then
sig_SYNC <= '1';
end if;
when others =>
null;
end case;
end process output_proc;
-- Concurrent Statements
-- Clocked output assignments
d_o <= d_o_cld;
rd_o <= rd_o_cld;
sync_o <= sync_o_cld;
wr_n_o <= wr_n_o_cld;
wr_o <= wr_o_cld;
sel_alu_as_o_i <= sel_alu_as_o_i_cld;
sel_alu_out_o_i <= sel_alu_out_o_i_cld;
sel_pc_as_o_i <= sel_pc_as_o_i_cld;
sel_pc_in_o_i <= sel_pc_in_o_i_cld;
sel_pc_val_o_i <= sel_pc_val_o_i_cld;
sel_rb_in_o_i <= sel_rb_in_o_i_cld;
sel_rb_out_o_i <= sel_rb_out_o_i_cld;
sel_reg_o_i <= sel_reg_o_i_cld;
sel_sp_as_o_i <= sel_sp_as_o_i_cld;
sel_sp_in_o_i <= sel_sp_in_o_i_cld;
sel_sp_val_o_i <= sel_sp_val_o_i_cld;
end fsm;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_398 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_398;
architecture augh of cmp_398 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_398 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_398;
architecture augh of cmp_398 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2978.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b01x00p07n01i02978ent IS
END c02s03b01x00p07n01i02978ent;
ARCHITECTURE c02s03b01x00p07n01i02978arch OF c02s03b01x00p07n01i02978ent IS
type newt is (one,two,three,four);
function "abs" (constant c1 : in integer) return newt is
begin
assert (c1=10)
report "Error in association of right operator"
severity failure;
return one;
end;
BEGIN
TESTING: PROCESS
variable n1 : newt;
BEGIN
wait for 5 ns;
n1:= "abs"(10);
assert (n1=one)
report "Error in call to operloaded operator"
severity failure;
assert NOT( n1=one )
report "***PASSED TEST: c02s03b01x00p07n01i02978"
severity NOTE;
assert ( n1=one )
report "***FAILED TEST: c02s03b01x00p07n01i02978 - Error in call to operloaded operator."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b01x00p07n01i02978arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2978.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b01x00p07n01i02978ent IS
END c02s03b01x00p07n01i02978ent;
ARCHITECTURE c02s03b01x00p07n01i02978arch OF c02s03b01x00p07n01i02978ent IS
type newt is (one,two,three,four);
function "abs" (constant c1 : in integer) return newt is
begin
assert (c1=10)
report "Error in association of right operator"
severity failure;
return one;
end;
BEGIN
TESTING: PROCESS
variable n1 : newt;
BEGIN
wait for 5 ns;
n1:= "abs"(10);
assert (n1=one)
report "Error in call to operloaded operator"
severity failure;
assert NOT( n1=one )
report "***PASSED TEST: c02s03b01x00p07n01i02978"
severity NOTE;
assert ( n1=one )
report "***FAILED TEST: c02s03b01x00p07n01i02978 - Error in call to operloaded operator."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b01x00p07n01i02978arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2978.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b01x00p07n01i02978ent IS
END c02s03b01x00p07n01i02978ent;
ARCHITECTURE c02s03b01x00p07n01i02978arch OF c02s03b01x00p07n01i02978ent IS
type newt is (one,two,three,four);
function "abs" (constant c1 : in integer) return newt is
begin
assert (c1=10)
report "Error in association of right operator"
severity failure;
return one;
end;
BEGIN
TESTING: PROCESS
variable n1 : newt;
BEGIN
wait for 5 ns;
n1:= "abs"(10);
assert (n1=one)
report "Error in call to operloaded operator"
severity failure;
assert NOT( n1=one )
report "***PASSED TEST: c02s03b01x00p07n01i02978"
severity NOTE;
assert ( n1=one )
report "***FAILED TEST: c02s03b01x00p07n01i02978 - Error in call to operloaded operator."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b01x00p07n01i02978arch;
|
-- Raster_Laser_Projector_Video_In.vhd
-- Generated using ACDS version 16.1 200
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Raster_Laser_Projector_Video_In is
port (
clk_clk : in std_logic := '0'; -- clk.clk
reset_reset_n : in std_logic := '0'; -- reset.reset_n
video_in_dma_address : out std_logic_vector(31 downto 0); -- video_in_dma.address
video_in_dma_waitrequest : in std_logic := '0'; -- .waitrequest
video_in_dma_write : out std_logic; -- .write
video_in_dma_writedata : out std_logic_vector(7 downto 0); -- .writedata
video_in_external_interface_TD_CLK27 : in std_logic := '0'; -- video_in_external_interface.TD_CLK27
video_in_external_interface_TD_DATA : in std_logic_vector(7 downto 0) := (others => '0'); -- .TD_DATA
video_in_external_interface_TD_HS : in std_logic := '0'; -- .TD_HS
video_in_external_interface_TD_VS : in std_logic := '0'; -- .TD_VS
video_in_external_interface_clk27_reset : in std_logic := '0'; -- .clk27_reset
video_in_external_interface_TD_RESET : out std_logic; -- .TD_RESET
video_in_external_interface_overflow_flag : out std_logic -- .overflow_flag
);
end entity Raster_Laser_Projector_Video_In;
architecture rtl of Raster_Laser_Projector_Video_In is
component Raster_Laser_Projector_Video_In_video_chroma_resampler_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_in_startofpacket : in std_logic := 'X'; -- startofpacket
stream_in_endofpacket : in std_logic := 'X'; -- endofpacket
stream_in_valid : in std_logic := 'X'; -- valid
stream_in_ready : out std_logic; -- ready
stream_in_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic; -- valid
stream_out_data : out std_logic_vector(23 downto 0) -- data
);
end component Raster_Laser_Projector_Video_In_video_chroma_resampler_0;
component Raster_Laser_Projector_Video_In_video_clipper_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_in_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
stream_in_startofpacket : in std_logic := 'X'; -- startofpacket
stream_in_endofpacket : in std_logic := 'X'; -- endofpacket
stream_in_valid : in std_logic := 'X'; -- valid
stream_in_ready : out std_logic; -- ready
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_data : out std_logic_vector(7 downto 0); -- data
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic -- valid
);
end component Raster_Laser_Projector_Video_In_video_clipper_0;
component Raster_Laser_Projector_Video_In_video_csc is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_in_startofpacket : in std_logic := 'X'; -- startofpacket
stream_in_endofpacket : in std_logic := 'X'; -- endofpacket
stream_in_valid : in std_logic := 'X'; -- valid
stream_in_ready : out std_logic; -- ready
stream_in_data : in std_logic_vector(23 downto 0) := (others => 'X'); -- data
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic; -- valid
stream_out_data : out std_logic_vector(23 downto 0) -- data
);
end component Raster_Laser_Projector_Video_In_video_csc;
component Raster_Laser_Projector_Video_In_video_decoder_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic; -- valid
stream_out_data : out std_logic_vector(15 downto 0); -- data
TD_CLK27 : in std_logic := 'X'; -- export
TD_DATA : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
TD_HS : in std_logic := 'X'; -- export
TD_VS : in std_logic := 'X'; -- export
clk27_reset : in std_logic := 'X'; -- export
TD_RESET : out std_logic; -- export
overflow_flag : out std_logic -- export
);
end component Raster_Laser_Projector_Video_In_video_decoder_0;
component Raster_Laser_Projector_Video_In_video_dma_controller_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
stream_startofpacket : in std_logic := 'X'; -- startofpacket
stream_endofpacket : in std_logic := 'X'; -- endofpacket
stream_valid : in std_logic := 'X'; -- valid
stream_ready : out std_logic; -- ready
slave_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
slave_read : in std_logic := 'X'; -- read
slave_write : in std_logic := 'X'; -- write
slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
slave_readdata : out std_logic_vector(31 downto 0); -- readdata
master_address : out std_logic_vector(31 downto 0); -- address
master_waitrequest : in std_logic := 'X'; -- waitrequest
master_write : out std_logic; -- write
master_writedata : out std_logic_vector(7 downto 0) -- writedata
);
end component Raster_Laser_Projector_Video_In_video_dma_controller_0;
component Raster_Laser_Projector_Video_In_video_rgb_resampler_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_in_startofpacket : in std_logic := 'X'; -- startofpacket
stream_in_endofpacket : in std_logic := 'X'; -- endofpacket
stream_in_valid : in std_logic := 'X'; -- valid
stream_in_ready : out std_logic; -- ready
stream_in_data : in std_logic_vector(23 downto 0) := (others => 'X'); -- data
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic; -- valid
stream_out_data : out std_logic_vector(7 downto 0) -- data
);
end component Raster_Laser_Projector_Video_In_video_rgb_resampler_0;
component Raster_Laser_Projector_Video_In_video_scaler_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_in_startofpacket : in std_logic := 'X'; -- startofpacket
stream_in_endofpacket : in std_logic := 'X'; -- endofpacket
stream_in_valid : in std_logic := 'X'; -- valid
stream_in_ready : out std_logic; -- ready
stream_in_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic; -- valid
stream_out_data : out std_logic_vector(7 downto 0); -- data
stream_out_channel : out std_logic -- channel
);
end component Raster_Laser_Projector_Video_In_video_scaler_0;
component Raster_Laser_Projector_Video_In_avalon_st_adapter is
generic (
inBitsPerSymbol : integer := 8;
inUsePackets : integer := 0;
inDataWidth : integer := 8;
inChannelWidth : integer := 3;
inErrorWidth : integer := 2;
inUseEmptyPort : integer := 0;
inUseValid : integer := 1;
inUseReady : integer := 1;
inReadyLatency : integer := 0;
outDataWidth : integer := 32;
outChannelWidth : integer := 3;
outErrorWidth : integer := 2;
outUseEmptyPort : integer := 0;
outUseValid : integer := 1;
outUseReady : integer := 1;
outReadyLatency : integer := 0
);
port (
in_clk_0_clk : in std_logic := 'X'; -- clk
in_rst_0_reset : in std_logic := 'X'; -- reset
in_0_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
in_0_valid : in std_logic := 'X'; -- valid
in_0_ready : out std_logic; -- ready
in_0_startofpacket : in std_logic := 'X'; -- startofpacket
in_0_endofpacket : in std_logic := 'X'; -- endofpacket
in_0_channel : in std_logic := 'X'; -- channel
out_0_data : out std_logic_vector(7 downto 0); -- data
out_0_valid : out std_logic; -- valid
out_0_ready : in std_logic := 'X'; -- ready
out_0_startofpacket : out std_logic; -- startofpacket
out_0_endofpacket : out std_logic -- endofpacket
);
end component Raster_Laser_Projector_Video_In_avalon_st_adapter;
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
signal video_clipper_0_avalon_clipper_source_valid : std_logic; -- video_clipper_0:stream_out_valid -> video_scaler_0:stream_in_valid
signal video_clipper_0_avalon_clipper_source_data : std_logic_vector(7 downto 0); -- video_clipper_0:stream_out_data -> video_scaler_0:stream_in_data
signal video_clipper_0_avalon_clipper_source_ready : std_logic; -- video_scaler_0:stream_in_ready -> video_clipper_0:stream_out_ready
signal video_clipper_0_avalon_clipper_source_startofpacket : std_logic; -- video_clipper_0:stream_out_startofpacket -> video_scaler_0:stream_in_startofpacket
signal video_clipper_0_avalon_clipper_source_endofpacket : std_logic; -- video_clipper_0:stream_out_endofpacket -> video_scaler_0:stream_in_endofpacket
signal video_csc_avalon_csc_source_valid : std_logic; -- video_csc:stream_out_valid -> video_rgb_resampler_0:stream_in_valid
signal video_csc_avalon_csc_source_data : std_logic_vector(23 downto 0); -- video_csc:stream_out_data -> video_rgb_resampler_0:stream_in_data
signal video_csc_avalon_csc_source_ready : std_logic; -- video_rgb_resampler_0:stream_in_ready -> video_csc:stream_out_ready
signal video_csc_avalon_csc_source_startofpacket : std_logic; -- video_csc:stream_out_startofpacket -> video_rgb_resampler_0:stream_in_startofpacket
signal video_csc_avalon_csc_source_endofpacket : std_logic; -- video_csc:stream_out_endofpacket -> video_rgb_resampler_0:stream_in_endofpacket
signal video_decoder_0_avalon_decoder_source_valid : std_logic; -- video_decoder_0:stream_out_valid -> video_chroma_resampler_0:stream_in_valid
signal video_decoder_0_avalon_decoder_source_data : std_logic_vector(15 downto 0); -- video_decoder_0:stream_out_data -> video_chroma_resampler_0:stream_in_data
signal video_decoder_0_avalon_decoder_source_ready : std_logic; -- video_chroma_resampler_0:stream_in_ready -> video_decoder_0:stream_out_ready
signal video_decoder_0_avalon_decoder_source_startofpacket : std_logic; -- video_decoder_0:stream_out_startofpacket -> video_chroma_resampler_0:stream_in_startofpacket
signal video_decoder_0_avalon_decoder_source_endofpacket : std_logic; -- video_decoder_0:stream_out_endofpacket -> video_chroma_resampler_0:stream_in_endofpacket
signal video_rgb_resampler_0_avalon_rgb_source_valid : std_logic; -- video_rgb_resampler_0:stream_out_valid -> video_clipper_0:stream_in_valid
signal video_rgb_resampler_0_avalon_rgb_source_data : std_logic_vector(7 downto 0); -- video_rgb_resampler_0:stream_out_data -> video_clipper_0:stream_in_data
signal video_rgb_resampler_0_avalon_rgb_source_ready : std_logic; -- video_clipper_0:stream_in_ready -> video_rgb_resampler_0:stream_out_ready
signal video_rgb_resampler_0_avalon_rgb_source_startofpacket : std_logic; -- video_rgb_resampler_0:stream_out_startofpacket -> video_clipper_0:stream_in_startofpacket
signal video_rgb_resampler_0_avalon_rgb_source_endofpacket : std_logic; -- video_rgb_resampler_0:stream_out_endofpacket -> video_clipper_0:stream_in_endofpacket
signal video_scaler_0_avalon_scaler_source_valid : std_logic; -- video_scaler_0:stream_out_valid -> avalon_st_adapter:in_0_valid
signal video_scaler_0_avalon_scaler_source_data : std_logic_vector(7 downto 0); -- video_scaler_0:stream_out_data -> avalon_st_adapter:in_0_data
signal video_scaler_0_avalon_scaler_source_ready : std_logic; -- avalon_st_adapter:in_0_ready -> video_scaler_0:stream_out_ready
signal video_scaler_0_avalon_scaler_source_channel : std_logic; -- video_scaler_0:stream_out_channel -> avalon_st_adapter:in_0_channel
signal video_scaler_0_avalon_scaler_source_startofpacket : std_logic; -- video_scaler_0:stream_out_startofpacket -> avalon_st_adapter:in_0_startofpacket
signal video_scaler_0_avalon_scaler_source_endofpacket : std_logic; -- video_scaler_0:stream_out_endofpacket -> avalon_st_adapter:in_0_endofpacket
signal avalon_st_adapter_out_0_valid : std_logic; -- avalon_st_adapter:out_0_valid -> video_dma_controller_0:stream_valid
signal avalon_st_adapter_out_0_data : std_logic_vector(7 downto 0); -- avalon_st_adapter:out_0_data -> video_dma_controller_0:stream_data
signal avalon_st_adapter_out_0_ready : std_logic; -- video_dma_controller_0:stream_ready -> avalon_st_adapter:out_0_ready
signal avalon_st_adapter_out_0_startofpacket : std_logic; -- avalon_st_adapter:out_0_startofpacket -> video_dma_controller_0:stream_startofpacket
signal avalon_st_adapter_out_0_endofpacket : std_logic; -- avalon_st_adapter:out_0_endofpacket -> video_dma_controller_0:stream_endofpacket
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [avalon_st_adapter:in_rst_0_reset, video_chroma_resampler_0:reset, video_clipper_0:reset, video_csc:reset, video_decoder_0:reset, video_dma_controller_0:reset, video_rgb_resampler_0:reset, video_scaler_0:reset]
signal reset_reset_n_ports_inv : std_logic; -- reset_reset_n:inv -> rst_controller:reset_in0
begin
video_chroma_resampler_0 : component Raster_Laser_Projector_Video_In_video_chroma_resampler_0
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
stream_in_startofpacket => video_decoder_0_avalon_decoder_source_startofpacket, -- avalon_chroma_sink.startofpacket
stream_in_endofpacket => video_decoder_0_avalon_decoder_source_endofpacket, -- .endofpacket
stream_in_valid => video_decoder_0_avalon_decoder_source_valid, -- .valid
stream_in_ready => video_decoder_0_avalon_decoder_source_ready, -- .ready
stream_in_data => video_decoder_0_avalon_decoder_source_data, -- .data
stream_out_ready => open, -- avalon_chroma_source.ready
stream_out_startofpacket => open, -- .startofpacket
stream_out_endofpacket => open, -- .endofpacket
stream_out_valid => open, -- .valid
stream_out_data => open -- .data
);
video_clipper_0 : component Raster_Laser_Projector_Video_In_video_clipper_0
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
stream_in_data => video_rgb_resampler_0_avalon_rgb_source_data, -- avalon_clipper_sink.data
stream_in_startofpacket => video_rgb_resampler_0_avalon_rgb_source_startofpacket, -- .startofpacket
stream_in_endofpacket => video_rgb_resampler_0_avalon_rgb_source_endofpacket, -- .endofpacket
stream_in_valid => video_rgb_resampler_0_avalon_rgb_source_valid, -- .valid
stream_in_ready => video_rgb_resampler_0_avalon_rgb_source_ready, -- .ready
stream_out_ready => video_clipper_0_avalon_clipper_source_ready, -- avalon_clipper_source.ready
stream_out_data => video_clipper_0_avalon_clipper_source_data, -- .data
stream_out_startofpacket => video_clipper_0_avalon_clipper_source_startofpacket, -- .startofpacket
stream_out_endofpacket => video_clipper_0_avalon_clipper_source_endofpacket, -- .endofpacket
stream_out_valid => video_clipper_0_avalon_clipper_source_valid -- .valid
);
video_csc : component Raster_Laser_Projector_Video_In_video_csc
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
stream_in_startofpacket => open, -- avalon_csc_sink.startofpacket
stream_in_endofpacket => open, -- .endofpacket
stream_in_valid => open, -- .valid
stream_in_ready => open, -- .ready
stream_in_data => open, -- .data
stream_out_ready => video_csc_avalon_csc_source_ready, -- avalon_csc_source.ready
stream_out_startofpacket => video_csc_avalon_csc_source_startofpacket, -- .startofpacket
stream_out_endofpacket => video_csc_avalon_csc_source_endofpacket, -- .endofpacket
stream_out_valid => video_csc_avalon_csc_source_valid, -- .valid
stream_out_data => video_csc_avalon_csc_source_data -- .data
);
video_decoder_0 : component Raster_Laser_Projector_Video_In_video_decoder_0
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
stream_out_ready => video_decoder_0_avalon_decoder_source_ready, -- avalon_decoder_source.ready
stream_out_startofpacket => video_decoder_0_avalon_decoder_source_startofpacket, -- .startofpacket
stream_out_endofpacket => video_decoder_0_avalon_decoder_source_endofpacket, -- .endofpacket
stream_out_valid => video_decoder_0_avalon_decoder_source_valid, -- .valid
stream_out_data => video_decoder_0_avalon_decoder_source_data, -- .data
TD_CLK27 => video_in_external_interface_TD_CLK27, -- external_interface.export
TD_DATA => video_in_external_interface_TD_DATA, -- .export
TD_HS => video_in_external_interface_TD_HS, -- .export
TD_VS => video_in_external_interface_TD_VS, -- .export
clk27_reset => video_in_external_interface_clk27_reset, -- .export
TD_RESET => video_in_external_interface_TD_RESET, -- .export
overflow_flag => video_in_external_interface_overflow_flag -- .export
);
video_dma_controller_0 : component Raster_Laser_Projector_Video_In_video_dma_controller_0
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
stream_data => avalon_st_adapter_out_0_data, -- avalon_dma_sink.data
stream_startofpacket => avalon_st_adapter_out_0_startofpacket, -- .startofpacket
stream_endofpacket => avalon_st_adapter_out_0_endofpacket, -- .endofpacket
stream_valid => avalon_st_adapter_out_0_valid, -- .valid
stream_ready => avalon_st_adapter_out_0_ready, -- .ready
slave_address => open, -- avalon_dma_control_slave.address
slave_byteenable => open, -- .byteenable
slave_read => open, -- .read
slave_write => open, -- .write
slave_writedata => open, -- .writedata
slave_readdata => open, -- .readdata
master_address => video_in_dma_address, -- avalon_dma_master.address
master_waitrequest => video_in_dma_waitrequest, -- .waitrequest
master_write => video_in_dma_write, -- .write
master_writedata => video_in_dma_writedata -- .writedata
);
video_rgb_resampler_0 : component Raster_Laser_Projector_Video_In_video_rgb_resampler_0
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
stream_in_startofpacket => video_csc_avalon_csc_source_startofpacket, -- avalon_rgb_sink.startofpacket
stream_in_endofpacket => video_csc_avalon_csc_source_endofpacket, -- .endofpacket
stream_in_valid => video_csc_avalon_csc_source_valid, -- .valid
stream_in_ready => video_csc_avalon_csc_source_ready, -- .ready
stream_in_data => video_csc_avalon_csc_source_data, -- .data
stream_out_ready => video_rgb_resampler_0_avalon_rgb_source_ready, -- avalon_rgb_source.ready
stream_out_startofpacket => video_rgb_resampler_0_avalon_rgb_source_startofpacket, -- .startofpacket
stream_out_endofpacket => video_rgb_resampler_0_avalon_rgb_source_endofpacket, -- .endofpacket
stream_out_valid => video_rgb_resampler_0_avalon_rgb_source_valid, -- .valid
stream_out_data => video_rgb_resampler_0_avalon_rgb_source_data -- .data
);
video_scaler_0 : component Raster_Laser_Projector_Video_In_video_scaler_0
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
stream_in_startofpacket => video_clipper_0_avalon_clipper_source_startofpacket, -- avalon_scaler_sink.startofpacket
stream_in_endofpacket => video_clipper_0_avalon_clipper_source_endofpacket, -- .endofpacket
stream_in_valid => video_clipper_0_avalon_clipper_source_valid, -- .valid
stream_in_ready => video_clipper_0_avalon_clipper_source_ready, -- .ready
stream_in_data => video_clipper_0_avalon_clipper_source_data, -- .data
stream_out_ready => video_scaler_0_avalon_scaler_source_ready, -- avalon_scaler_source.ready
stream_out_startofpacket => video_scaler_0_avalon_scaler_source_startofpacket, -- .startofpacket
stream_out_endofpacket => video_scaler_0_avalon_scaler_source_endofpacket, -- .endofpacket
stream_out_valid => video_scaler_0_avalon_scaler_source_valid, -- .valid
stream_out_data => video_scaler_0_avalon_scaler_source_data, -- .data
stream_out_channel => video_scaler_0_avalon_scaler_source_channel -- .channel
);
avalon_st_adapter : component Raster_Laser_Projector_Video_In_avalon_st_adapter
generic map (
inBitsPerSymbol => 8,
inUsePackets => 1,
inDataWidth => 8,
inChannelWidth => 1,
inErrorWidth => 0,
inUseEmptyPort => 0,
inUseValid => 1,
inUseReady => 1,
inReadyLatency => 0,
outDataWidth => 8,
outChannelWidth => 0,
outErrorWidth => 0,
outUseEmptyPort => 0,
outUseValid => 1,
outUseReady => 1,
outReadyLatency => 0
)
port map (
in_clk_0_clk => clk_clk, -- in_clk_0.clk
in_rst_0_reset => rst_controller_reset_out_reset, -- in_rst_0.reset
in_0_data => video_scaler_0_avalon_scaler_source_data, -- in_0.data
in_0_valid => video_scaler_0_avalon_scaler_source_valid, -- .valid
in_0_ready => video_scaler_0_avalon_scaler_source_ready, -- .ready
in_0_startofpacket => video_scaler_0_avalon_scaler_source_startofpacket, -- .startofpacket
in_0_endofpacket => video_scaler_0_avalon_scaler_source_endofpacket, -- .endofpacket
in_0_channel => video_scaler_0_avalon_scaler_source_channel, -- .channel
out_0_data => avalon_st_adapter_out_0_data, -- out_0.data
out_0_valid => avalon_st_adapter_out_0_valid, -- .valid
out_0_ready => avalon_st_adapter_out_0_ready, -- .ready
out_0_startofpacket => avalon_st_adapter_out_0_startofpacket, -- .startofpacket
out_0_endofpacket => avalon_st_adapter_out_0_endofpacket -- .endofpacket
);
rst_controller : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => clk_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
reset_reset_n_ports_inv <= not reset_reset_n;
end architecture rtl; -- of Raster_Laser_Projector_Video_In
|
-- Raster_Laser_Projector_Video_In.vhd
-- Generated using ACDS version 16.1 200
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Raster_Laser_Projector_Video_In is
port (
clk_clk : in std_logic := '0'; -- clk.clk
reset_reset_n : in std_logic := '0'; -- reset.reset_n
video_in_dma_address : out std_logic_vector(31 downto 0); -- video_in_dma.address
video_in_dma_waitrequest : in std_logic := '0'; -- .waitrequest
video_in_dma_write : out std_logic; -- .write
video_in_dma_writedata : out std_logic_vector(7 downto 0); -- .writedata
video_in_external_interface_TD_CLK27 : in std_logic := '0'; -- video_in_external_interface.TD_CLK27
video_in_external_interface_TD_DATA : in std_logic_vector(7 downto 0) := (others => '0'); -- .TD_DATA
video_in_external_interface_TD_HS : in std_logic := '0'; -- .TD_HS
video_in_external_interface_TD_VS : in std_logic := '0'; -- .TD_VS
video_in_external_interface_clk27_reset : in std_logic := '0'; -- .clk27_reset
video_in_external_interface_TD_RESET : out std_logic; -- .TD_RESET
video_in_external_interface_overflow_flag : out std_logic -- .overflow_flag
);
end entity Raster_Laser_Projector_Video_In;
architecture rtl of Raster_Laser_Projector_Video_In is
component Raster_Laser_Projector_Video_In_video_chroma_resampler_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_in_startofpacket : in std_logic := 'X'; -- startofpacket
stream_in_endofpacket : in std_logic := 'X'; -- endofpacket
stream_in_valid : in std_logic := 'X'; -- valid
stream_in_ready : out std_logic; -- ready
stream_in_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- data
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic; -- valid
stream_out_data : out std_logic_vector(23 downto 0) -- data
);
end component Raster_Laser_Projector_Video_In_video_chroma_resampler_0;
component Raster_Laser_Projector_Video_In_video_clipper_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_in_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
stream_in_startofpacket : in std_logic := 'X'; -- startofpacket
stream_in_endofpacket : in std_logic := 'X'; -- endofpacket
stream_in_valid : in std_logic := 'X'; -- valid
stream_in_ready : out std_logic; -- ready
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_data : out std_logic_vector(7 downto 0); -- data
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic -- valid
);
end component Raster_Laser_Projector_Video_In_video_clipper_0;
component Raster_Laser_Projector_Video_In_video_csc is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_in_startofpacket : in std_logic := 'X'; -- startofpacket
stream_in_endofpacket : in std_logic := 'X'; -- endofpacket
stream_in_valid : in std_logic := 'X'; -- valid
stream_in_ready : out std_logic; -- ready
stream_in_data : in std_logic_vector(23 downto 0) := (others => 'X'); -- data
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic; -- valid
stream_out_data : out std_logic_vector(23 downto 0) -- data
);
end component Raster_Laser_Projector_Video_In_video_csc;
component Raster_Laser_Projector_Video_In_video_decoder_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic; -- valid
stream_out_data : out std_logic_vector(15 downto 0); -- data
TD_CLK27 : in std_logic := 'X'; -- export
TD_DATA : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
TD_HS : in std_logic := 'X'; -- export
TD_VS : in std_logic := 'X'; -- export
clk27_reset : in std_logic := 'X'; -- export
TD_RESET : out std_logic; -- export
overflow_flag : out std_logic -- export
);
end component Raster_Laser_Projector_Video_In_video_decoder_0;
component Raster_Laser_Projector_Video_In_video_dma_controller_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
stream_startofpacket : in std_logic := 'X'; -- startofpacket
stream_endofpacket : in std_logic := 'X'; -- endofpacket
stream_valid : in std_logic := 'X'; -- valid
stream_ready : out std_logic; -- ready
slave_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
slave_read : in std_logic := 'X'; -- read
slave_write : in std_logic := 'X'; -- write
slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
slave_readdata : out std_logic_vector(31 downto 0); -- readdata
master_address : out std_logic_vector(31 downto 0); -- address
master_waitrequest : in std_logic := 'X'; -- waitrequest
master_write : out std_logic; -- write
master_writedata : out std_logic_vector(7 downto 0) -- writedata
);
end component Raster_Laser_Projector_Video_In_video_dma_controller_0;
component Raster_Laser_Projector_Video_In_video_rgb_resampler_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_in_startofpacket : in std_logic := 'X'; -- startofpacket
stream_in_endofpacket : in std_logic := 'X'; -- endofpacket
stream_in_valid : in std_logic := 'X'; -- valid
stream_in_ready : out std_logic; -- ready
stream_in_data : in std_logic_vector(23 downto 0) := (others => 'X'); -- data
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic; -- valid
stream_out_data : out std_logic_vector(7 downto 0) -- data
);
end component Raster_Laser_Projector_Video_In_video_rgb_resampler_0;
component Raster_Laser_Projector_Video_In_video_scaler_0 is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
stream_in_startofpacket : in std_logic := 'X'; -- startofpacket
stream_in_endofpacket : in std_logic := 'X'; -- endofpacket
stream_in_valid : in std_logic := 'X'; -- valid
stream_in_ready : out std_logic; -- ready
stream_in_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
stream_out_ready : in std_logic := 'X'; -- ready
stream_out_startofpacket : out std_logic; -- startofpacket
stream_out_endofpacket : out std_logic; -- endofpacket
stream_out_valid : out std_logic; -- valid
stream_out_data : out std_logic_vector(7 downto 0); -- data
stream_out_channel : out std_logic -- channel
);
end component Raster_Laser_Projector_Video_In_video_scaler_0;
component Raster_Laser_Projector_Video_In_avalon_st_adapter is
generic (
inBitsPerSymbol : integer := 8;
inUsePackets : integer := 0;
inDataWidth : integer := 8;
inChannelWidth : integer := 3;
inErrorWidth : integer := 2;
inUseEmptyPort : integer := 0;
inUseValid : integer := 1;
inUseReady : integer := 1;
inReadyLatency : integer := 0;
outDataWidth : integer := 32;
outChannelWidth : integer := 3;
outErrorWidth : integer := 2;
outUseEmptyPort : integer := 0;
outUseValid : integer := 1;
outUseReady : integer := 1;
outReadyLatency : integer := 0
);
port (
in_clk_0_clk : in std_logic := 'X'; -- clk
in_rst_0_reset : in std_logic := 'X'; -- reset
in_0_data : in std_logic_vector(7 downto 0) := (others => 'X'); -- data
in_0_valid : in std_logic := 'X'; -- valid
in_0_ready : out std_logic; -- ready
in_0_startofpacket : in std_logic := 'X'; -- startofpacket
in_0_endofpacket : in std_logic := 'X'; -- endofpacket
in_0_channel : in std_logic := 'X'; -- channel
out_0_data : out std_logic_vector(7 downto 0); -- data
out_0_valid : out std_logic; -- valid
out_0_ready : in std_logic := 'X'; -- ready
out_0_startofpacket : out std_logic; -- startofpacket
out_0_endofpacket : out std_logic -- endofpacket
);
end component Raster_Laser_Projector_Video_In_avalon_st_adapter;
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
signal video_clipper_0_avalon_clipper_source_valid : std_logic; -- video_clipper_0:stream_out_valid -> video_scaler_0:stream_in_valid
signal video_clipper_0_avalon_clipper_source_data : std_logic_vector(7 downto 0); -- video_clipper_0:stream_out_data -> video_scaler_0:stream_in_data
signal video_clipper_0_avalon_clipper_source_ready : std_logic; -- video_scaler_0:stream_in_ready -> video_clipper_0:stream_out_ready
signal video_clipper_0_avalon_clipper_source_startofpacket : std_logic; -- video_clipper_0:stream_out_startofpacket -> video_scaler_0:stream_in_startofpacket
signal video_clipper_0_avalon_clipper_source_endofpacket : std_logic; -- video_clipper_0:stream_out_endofpacket -> video_scaler_0:stream_in_endofpacket
signal video_csc_avalon_csc_source_valid : std_logic; -- video_csc:stream_out_valid -> video_rgb_resampler_0:stream_in_valid
signal video_csc_avalon_csc_source_data : std_logic_vector(23 downto 0); -- video_csc:stream_out_data -> video_rgb_resampler_0:stream_in_data
signal video_csc_avalon_csc_source_ready : std_logic; -- video_rgb_resampler_0:stream_in_ready -> video_csc:stream_out_ready
signal video_csc_avalon_csc_source_startofpacket : std_logic; -- video_csc:stream_out_startofpacket -> video_rgb_resampler_0:stream_in_startofpacket
signal video_csc_avalon_csc_source_endofpacket : std_logic; -- video_csc:stream_out_endofpacket -> video_rgb_resampler_0:stream_in_endofpacket
signal video_decoder_0_avalon_decoder_source_valid : std_logic; -- video_decoder_0:stream_out_valid -> video_chroma_resampler_0:stream_in_valid
signal video_decoder_0_avalon_decoder_source_data : std_logic_vector(15 downto 0); -- video_decoder_0:stream_out_data -> video_chroma_resampler_0:stream_in_data
signal video_decoder_0_avalon_decoder_source_ready : std_logic; -- video_chroma_resampler_0:stream_in_ready -> video_decoder_0:stream_out_ready
signal video_decoder_0_avalon_decoder_source_startofpacket : std_logic; -- video_decoder_0:stream_out_startofpacket -> video_chroma_resampler_0:stream_in_startofpacket
signal video_decoder_0_avalon_decoder_source_endofpacket : std_logic; -- video_decoder_0:stream_out_endofpacket -> video_chroma_resampler_0:stream_in_endofpacket
signal video_rgb_resampler_0_avalon_rgb_source_valid : std_logic; -- video_rgb_resampler_0:stream_out_valid -> video_clipper_0:stream_in_valid
signal video_rgb_resampler_0_avalon_rgb_source_data : std_logic_vector(7 downto 0); -- video_rgb_resampler_0:stream_out_data -> video_clipper_0:stream_in_data
signal video_rgb_resampler_0_avalon_rgb_source_ready : std_logic; -- video_clipper_0:stream_in_ready -> video_rgb_resampler_0:stream_out_ready
signal video_rgb_resampler_0_avalon_rgb_source_startofpacket : std_logic; -- video_rgb_resampler_0:stream_out_startofpacket -> video_clipper_0:stream_in_startofpacket
signal video_rgb_resampler_0_avalon_rgb_source_endofpacket : std_logic; -- video_rgb_resampler_0:stream_out_endofpacket -> video_clipper_0:stream_in_endofpacket
signal video_scaler_0_avalon_scaler_source_valid : std_logic; -- video_scaler_0:stream_out_valid -> avalon_st_adapter:in_0_valid
signal video_scaler_0_avalon_scaler_source_data : std_logic_vector(7 downto 0); -- video_scaler_0:stream_out_data -> avalon_st_adapter:in_0_data
signal video_scaler_0_avalon_scaler_source_ready : std_logic; -- avalon_st_adapter:in_0_ready -> video_scaler_0:stream_out_ready
signal video_scaler_0_avalon_scaler_source_channel : std_logic; -- video_scaler_0:stream_out_channel -> avalon_st_adapter:in_0_channel
signal video_scaler_0_avalon_scaler_source_startofpacket : std_logic; -- video_scaler_0:stream_out_startofpacket -> avalon_st_adapter:in_0_startofpacket
signal video_scaler_0_avalon_scaler_source_endofpacket : std_logic; -- video_scaler_0:stream_out_endofpacket -> avalon_st_adapter:in_0_endofpacket
signal avalon_st_adapter_out_0_valid : std_logic; -- avalon_st_adapter:out_0_valid -> video_dma_controller_0:stream_valid
signal avalon_st_adapter_out_0_data : std_logic_vector(7 downto 0); -- avalon_st_adapter:out_0_data -> video_dma_controller_0:stream_data
signal avalon_st_adapter_out_0_ready : std_logic; -- video_dma_controller_0:stream_ready -> avalon_st_adapter:out_0_ready
signal avalon_st_adapter_out_0_startofpacket : std_logic; -- avalon_st_adapter:out_0_startofpacket -> video_dma_controller_0:stream_startofpacket
signal avalon_st_adapter_out_0_endofpacket : std_logic; -- avalon_st_adapter:out_0_endofpacket -> video_dma_controller_0:stream_endofpacket
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [avalon_st_adapter:in_rst_0_reset, video_chroma_resampler_0:reset, video_clipper_0:reset, video_csc:reset, video_decoder_0:reset, video_dma_controller_0:reset, video_rgb_resampler_0:reset, video_scaler_0:reset]
signal reset_reset_n_ports_inv : std_logic; -- reset_reset_n:inv -> rst_controller:reset_in0
begin
video_chroma_resampler_0 : component Raster_Laser_Projector_Video_In_video_chroma_resampler_0
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
stream_in_startofpacket => video_decoder_0_avalon_decoder_source_startofpacket, -- avalon_chroma_sink.startofpacket
stream_in_endofpacket => video_decoder_0_avalon_decoder_source_endofpacket, -- .endofpacket
stream_in_valid => video_decoder_0_avalon_decoder_source_valid, -- .valid
stream_in_ready => video_decoder_0_avalon_decoder_source_ready, -- .ready
stream_in_data => video_decoder_0_avalon_decoder_source_data, -- .data
stream_out_ready => open, -- avalon_chroma_source.ready
stream_out_startofpacket => open, -- .startofpacket
stream_out_endofpacket => open, -- .endofpacket
stream_out_valid => open, -- .valid
stream_out_data => open -- .data
);
video_clipper_0 : component Raster_Laser_Projector_Video_In_video_clipper_0
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
stream_in_data => video_rgb_resampler_0_avalon_rgb_source_data, -- avalon_clipper_sink.data
stream_in_startofpacket => video_rgb_resampler_0_avalon_rgb_source_startofpacket, -- .startofpacket
stream_in_endofpacket => video_rgb_resampler_0_avalon_rgb_source_endofpacket, -- .endofpacket
stream_in_valid => video_rgb_resampler_0_avalon_rgb_source_valid, -- .valid
stream_in_ready => video_rgb_resampler_0_avalon_rgb_source_ready, -- .ready
stream_out_ready => video_clipper_0_avalon_clipper_source_ready, -- avalon_clipper_source.ready
stream_out_data => video_clipper_0_avalon_clipper_source_data, -- .data
stream_out_startofpacket => video_clipper_0_avalon_clipper_source_startofpacket, -- .startofpacket
stream_out_endofpacket => video_clipper_0_avalon_clipper_source_endofpacket, -- .endofpacket
stream_out_valid => video_clipper_0_avalon_clipper_source_valid -- .valid
);
video_csc : component Raster_Laser_Projector_Video_In_video_csc
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
stream_in_startofpacket => open, -- avalon_csc_sink.startofpacket
stream_in_endofpacket => open, -- .endofpacket
stream_in_valid => open, -- .valid
stream_in_ready => open, -- .ready
stream_in_data => open, -- .data
stream_out_ready => video_csc_avalon_csc_source_ready, -- avalon_csc_source.ready
stream_out_startofpacket => video_csc_avalon_csc_source_startofpacket, -- .startofpacket
stream_out_endofpacket => video_csc_avalon_csc_source_endofpacket, -- .endofpacket
stream_out_valid => video_csc_avalon_csc_source_valid, -- .valid
stream_out_data => video_csc_avalon_csc_source_data -- .data
);
video_decoder_0 : component Raster_Laser_Projector_Video_In_video_decoder_0
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
stream_out_ready => video_decoder_0_avalon_decoder_source_ready, -- avalon_decoder_source.ready
stream_out_startofpacket => video_decoder_0_avalon_decoder_source_startofpacket, -- .startofpacket
stream_out_endofpacket => video_decoder_0_avalon_decoder_source_endofpacket, -- .endofpacket
stream_out_valid => video_decoder_0_avalon_decoder_source_valid, -- .valid
stream_out_data => video_decoder_0_avalon_decoder_source_data, -- .data
TD_CLK27 => video_in_external_interface_TD_CLK27, -- external_interface.export
TD_DATA => video_in_external_interface_TD_DATA, -- .export
TD_HS => video_in_external_interface_TD_HS, -- .export
TD_VS => video_in_external_interface_TD_VS, -- .export
clk27_reset => video_in_external_interface_clk27_reset, -- .export
TD_RESET => video_in_external_interface_TD_RESET, -- .export
overflow_flag => video_in_external_interface_overflow_flag -- .export
);
video_dma_controller_0 : component Raster_Laser_Projector_Video_In_video_dma_controller_0
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
stream_data => avalon_st_adapter_out_0_data, -- avalon_dma_sink.data
stream_startofpacket => avalon_st_adapter_out_0_startofpacket, -- .startofpacket
stream_endofpacket => avalon_st_adapter_out_0_endofpacket, -- .endofpacket
stream_valid => avalon_st_adapter_out_0_valid, -- .valid
stream_ready => avalon_st_adapter_out_0_ready, -- .ready
slave_address => open, -- avalon_dma_control_slave.address
slave_byteenable => open, -- .byteenable
slave_read => open, -- .read
slave_write => open, -- .write
slave_writedata => open, -- .writedata
slave_readdata => open, -- .readdata
master_address => video_in_dma_address, -- avalon_dma_master.address
master_waitrequest => video_in_dma_waitrequest, -- .waitrequest
master_write => video_in_dma_write, -- .write
master_writedata => video_in_dma_writedata -- .writedata
);
video_rgb_resampler_0 : component Raster_Laser_Projector_Video_In_video_rgb_resampler_0
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
stream_in_startofpacket => video_csc_avalon_csc_source_startofpacket, -- avalon_rgb_sink.startofpacket
stream_in_endofpacket => video_csc_avalon_csc_source_endofpacket, -- .endofpacket
stream_in_valid => video_csc_avalon_csc_source_valid, -- .valid
stream_in_ready => video_csc_avalon_csc_source_ready, -- .ready
stream_in_data => video_csc_avalon_csc_source_data, -- .data
stream_out_ready => video_rgb_resampler_0_avalon_rgb_source_ready, -- avalon_rgb_source.ready
stream_out_startofpacket => video_rgb_resampler_0_avalon_rgb_source_startofpacket, -- .startofpacket
stream_out_endofpacket => video_rgb_resampler_0_avalon_rgb_source_endofpacket, -- .endofpacket
stream_out_valid => video_rgb_resampler_0_avalon_rgb_source_valid, -- .valid
stream_out_data => video_rgb_resampler_0_avalon_rgb_source_data -- .data
);
video_scaler_0 : component Raster_Laser_Projector_Video_In_video_scaler_0
port map (
clk => clk_clk, -- clk.clk
reset => rst_controller_reset_out_reset, -- reset.reset
stream_in_startofpacket => video_clipper_0_avalon_clipper_source_startofpacket, -- avalon_scaler_sink.startofpacket
stream_in_endofpacket => video_clipper_0_avalon_clipper_source_endofpacket, -- .endofpacket
stream_in_valid => video_clipper_0_avalon_clipper_source_valid, -- .valid
stream_in_ready => video_clipper_0_avalon_clipper_source_ready, -- .ready
stream_in_data => video_clipper_0_avalon_clipper_source_data, -- .data
stream_out_ready => video_scaler_0_avalon_scaler_source_ready, -- avalon_scaler_source.ready
stream_out_startofpacket => video_scaler_0_avalon_scaler_source_startofpacket, -- .startofpacket
stream_out_endofpacket => video_scaler_0_avalon_scaler_source_endofpacket, -- .endofpacket
stream_out_valid => video_scaler_0_avalon_scaler_source_valid, -- .valid
stream_out_data => video_scaler_0_avalon_scaler_source_data, -- .data
stream_out_channel => video_scaler_0_avalon_scaler_source_channel -- .channel
);
avalon_st_adapter : component Raster_Laser_Projector_Video_In_avalon_st_adapter
generic map (
inBitsPerSymbol => 8,
inUsePackets => 1,
inDataWidth => 8,
inChannelWidth => 1,
inErrorWidth => 0,
inUseEmptyPort => 0,
inUseValid => 1,
inUseReady => 1,
inReadyLatency => 0,
outDataWidth => 8,
outChannelWidth => 0,
outErrorWidth => 0,
outUseEmptyPort => 0,
outUseValid => 1,
outUseReady => 1,
outReadyLatency => 0
)
port map (
in_clk_0_clk => clk_clk, -- in_clk_0.clk
in_rst_0_reset => rst_controller_reset_out_reset, -- in_rst_0.reset
in_0_data => video_scaler_0_avalon_scaler_source_data, -- in_0.data
in_0_valid => video_scaler_0_avalon_scaler_source_valid, -- .valid
in_0_ready => video_scaler_0_avalon_scaler_source_ready, -- .ready
in_0_startofpacket => video_scaler_0_avalon_scaler_source_startofpacket, -- .startofpacket
in_0_endofpacket => video_scaler_0_avalon_scaler_source_endofpacket, -- .endofpacket
in_0_channel => video_scaler_0_avalon_scaler_source_channel, -- .channel
out_0_data => avalon_st_adapter_out_0_data, -- out_0.data
out_0_valid => avalon_st_adapter_out_0_valid, -- .valid
out_0_ready => avalon_st_adapter_out_0_ready, -- .ready
out_0_startofpacket => avalon_st_adapter_out_0_startofpacket, -- .startofpacket
out_0_endofpacket => avalon_st_adapter_out_0_endofpacket -- .endofpacket
);
rst_controller : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => clk_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
reset_reset_n_ports_inv <= not reset_reset_n;
end architecture rtl; -- of Raster_Laser_Projector_Video_In
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:mult_gen:12.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY mult_gen_v12_0_12;
USE mult_gen_v12_0_12.mult_gen_v12_0_12;
ENTITY mul16_16 IS
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
P : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END mul16_16;
ARCHITECTURE mul16_16_arch OF mul16_16 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF mul16_16_arch: ARCHITECTURE IS "yes";
COMPONENT mult_gen_v12_0_12 IS
GENERIC (
C_VERBOSITY : INTEGER;
C_MODEL_TYPE : INTEGER;
C_OPTIMIZE_GOAL : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_CE : INTEGER;
C_HAS_SCLR : INTEGER;
C_LATENCY : INTEGER;
C_A_WIDTH : INTEGER;
C_A_TYPE : INTEGER;
C_B_WIDTH : INTEGER;
C_B_TYPE : INTEGER;
C_OUT_HIGH : INTEGER;
C_OUT_LOW : INTEGER;
C_MULT_TYPE : INTEGER;
C_CE_OVERRIDES_SCLR : INTEGER;
C_CCM_IMP : INTEGER;
C_B_VALUE : STRING;
C_HAS_ZERO_DETECT : INTEGER;
C_ROUND_OUTPUT : INTEGER;
C_ROUND_PT : INTEGER
);
PORT (
CLK : IN STD_LOGIC;
A : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CE : IN STD_LOGIC;
SCLR : IN STD_LOGIC;
P : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT mult_gen_v12_0_12;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLK: SIGNAL IS "xilinx.com:signal:clock:1.0 clk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF A: SIGNAL IS "xilinx.com:signal:data:1.0 a_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF B: SIGNAL IS "xilinx.com:signal:data:1.0 b_intf DATA";
ATTRIBUTE X_INTERFACE_INFO OF P: SIGNAL IS "xilinx.com:signal:data:1.0 p_intf DATA";
BEGIN
U0 : mult_gen_v12_0_12
GENERIC MAP (
C_VERBOSITY => 0,
C_MODEL_TYPE => 0,
C_OPTIMIZE_GOAL => 1,
C_XDEVICEFAMILY => "kintexu",
C_HAS_CE => 0,
C_HAS_SCLR => 0,
C_LATENCY => 4,
C_A_WIDTH => 16,
C_A_TYPE => 1,
C_B_WIDTH => 16,
C_B_TYPE => 1,
C_OUT_HIGH => 31,
C_OUT_LOW => 16,
C_MULT_TYPE => 0,
C_CE_OVERRIDES_SCLR => 0,
C_CCM_IMP => 0,
C_B_VALUE => "10000001",
C_HAS_ZERO_DETECT => 0,
C_ROUND_OUTPUT => 0,
C_ROUND_PT => 0
)
PORT MAP (
CLK => CLK,
A => A,
B => B,
CE => '1',
SCLR => '0',
P => P
);
END mul16_16_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc752.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x01p05n02i00752ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level := note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "shishir";
C11 : bit_vector := B"0011"
);
END c01s01b01x01p05n02i00752ent;
ARCHITECTURE c01s01b01x01p05n02i00752arch OF c01s01b01x01p05n02i00752ent IS
subtype hi_to_low_range is integer range zero to seven;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(zero to fifteen);
subtype severity_level_vector_st is severity_level_vector(zero to fifteen);
subtype integer_vector_st is integer_vector(zero to fifteen);
subtype real_vector_st is real_vector(zero to fifteen);
subtype time_vector_st is time_vector(zero to fifteen);
subtype natural_vector_st is natural_vector(zero to fifteen);
subtype positive_vector_st is positive_vector(zero to fifteen);
type boolean_cons_vector is array (fifteen downto zero) of boolean;
type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
type integer_cons_vector is array (fifteen downto zero) of integer;
type real_cons_vector is array (fifteen downto zero) of real;
type time_cons_vector is array (fifteen downto zero) of time;
type natural_cons_vector is array (fifteen downto zero) of natural;
type positive_cons_vector is array (fifteen downto zero) of positive;
type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector
;
type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;
type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(one to seven);
k:bit_vector(zero to three);
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_new is record
a:boolean_vector(zero to fifteen);
b:severity_level_vector(zero to fifteen);
c:integer_vector(zero to fifteen);
d:real_vector(zero to fifteen);
e:time_vector(zero to fifteen);
f:natural_vector(zero to fifteen);
g:positive_vector(zero to fifteen);
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
j: record_array_new;
end record;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
subtype integer_vector_range is integer_vector(hi_to_low_range);
subtype real_vector_range is real_vector(hi_to_low_range);
subtype time_vector_range is time_vector(hi_to_low_range);
subtype natural_vector_range is natural_vector(hi_to_low_range);
subtype positive_vector_range is positive_vector(hi_to_low_range);
type array_rec_std is array (integer range <>) of record_std_package;
type array_rec_cons is array (integer range <>) of record_cons_array;
type array_rec_rec is array (integer range <>) of record_of_records;
subtype array_rec_std_st is array_rec_std (hi_to_low_range);
subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
type record_of_arr_of_record is record
a: array_rec_std(zero to seven);
b: array_rec_cons(zero to seven);
c: array_rec_rec(zero to seven);
end record;
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type current_vector is array (natural range <>) of current;
subtype current_vector_range is current_vector(hi_to_low_range);
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_vector is array (natural range <>) of resistance;
subtype resistance_vector_range is resistance_vector(hi_to_low_range);
type byte is array(zero to seven) of bit;
subtype word is bit_vector(zero to fifteen); --constrained array
constant size :integer := seven;
type primary_memory is array(zero to size) of word; --array of an array
type primary_memory_module is --record with field
record --as an array
enable:bit;
memory_number:primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module; --array of a complex record
subtype delay is integer range one to 10;
constant C12 : boolean_vector := (C1,false);
constant C13 : severity_level_vector := (C4,error);
constant C14 : integer_vector := (one,two,three,four);
constant C15 : real_vector := (1.0,2.0,C6,4.0);
constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
constant C17 : natural_vector := (one,2,3,4);
constant C18 : positive_vector := (one,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st:= (others => C4);
constant C72 : integer_vector_st:=(others => C5);
constant C73 : real_vector_st:=(others => C6);
constant C74 : time_vector_st:=(others => C7);
constant C75 : natural_vector_st:=(others => C8);
constant C76 : positive_vector_st:=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54b: record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records := (C50,C51,C53,C77,C54b);
constant C60 : byte := (others => '0');
constant C61 : word := (others =>'0' );
constant C64 : primary_memory := (others => C61);
constant C65 : primary_memory_module := ('1',C64);
constant C66 : whole_memory := (others => C65);
constant C67 : current := 1 A;
constant C68 : resistance := 1 Ohm;
constant C69 : delay := 2;
constant C78: boolean_vector_range := (others => C1);
constant C79: severity_level_vector_range := (others => C4) ;
constant C80: integer_vector_range :=(others => C5) ;
constant C81: real_vector_range :=(others => C6);
constant C82: time_vector_range :=(others => C7);
constant C83: natural_vector_range :=(others => C8);
constant C84: positive_vector_range :=(others => C9);
constant C85: array_rec_std(0 to 7) :=(others => C50) ;
constant C86: array_rec_cons (0 to 7) :=(others => C51);
constant C88: array_rec_rec(0 to 7) :=(others => C55);
constant C102: record_of_arr_of_record:= (C85,C86,C88);
BEGIN
TESTING: PROCESS
variable V1 : boolean_vector(zero to fifteen) := (zero to fifteen => C1);
variable V2 : severity_level_vector(zero to fifteen):= (zero to fifteen => C4);
variable V3 : integer_vector(zero to fifteen) := (zero to fifteen => C5);
variable V4 : real_vector(zero to fifteen) := (zero to fifteen => C6);
variable V5 : time_vector (zero to fifteen) := (zero to fifteen => C7);
variable V6 : natural_vector(zero to fifteen):= (zero to fifteen => C8);
variable V7 : positive_vector(zero to fifteen):= (zero to fifteen => C9);
variable V8 : boolean_cons_vector:= C19;
variable V9 : severity_level_cons_vector := C20;
variable V10 : integer_cons_vector:= C21;
variable V11 : real_cons_vector:= C22;
variable V12 : time_cons_vector := C23;
variable V13 : natural_cons_vector := C24;
variable V14 : positive_cons_vector := C25;
variable V15 : boolean_cons_vectorofvector := C26;
variable V16 : severity_level_cons_vectorofvector:= C27;
variable V17 : integer_cons_vectorofvector:= C28;
variable V18 : real_cons_vectorofvector:= C29;
variable V19 : time_cons_vectorofvector:= C30;
variable V20 : natural_cons_vectorofvector:= C31;
variable V21 : positive_cons_vectorofvector:= C32;
variable V22 : record_std_package:= C50;
variable V23 : record_cons_array := C51;
variable V24 : record_cons_arrayofarray := C53 ;
variable V25 : boolean_vector_st:= C70 ;
variable V26 : severity_level_vector_st := C71;
variable V27 : integer_vector_st:= C72;
variable V28 : real_vector_st := C73;
variable V29 : time_vector_st := C74;
variable V30 : natural_vector_st:= C75;
variable V31 : positive_vector_st := C76;
variable V32 : record_array_st := C54a;
variable V33 : record_array_st := C54a;
variable V34 : record_array_new:= C54b;
variable V35 : record_of_records := C55;
variable V36 : byte := C60;
variable V37 : word := C61;
variable V41 : boolean_vector_range := C78;
variable V42 : severity_level_vector_range := C79;
variable V43 : integer_vector_range := C80;
variable V44 : real_vector_range:= C81 ;
variable V45 : time_vector_range := C82;
variable V46 : natural_vector_range := C83;
variable V47 : positive_vector_range := C84;
variable V48 : array_rec_std(zero to seven) := C85;
variable V49 : array_rec_cons(zero to seven) := C86;
variable V50 : array_rec_rec(zero to seven) := C88;
variable V51 : record_of_arr_of_record := C102;
BEGIN
assert (V1(0) = C1) report " error in initializing S1" severity error;
assert (V2(0) = C4) report " error in initializing S2" severity error;
assert (V3(0) = C5) report " error in initializing S3" severity error;
assert (V4(0) = C6) report " error in initializing S4" severity error;
assert (V5(0) = C7) report " error in initializing S5" severity error;
assert (V6(0) = C8) report " error in initializing S6" severity error;
assert (V7(0) = C9) report " error in initializing S7" severity error;
assert V8 = C19 report " error in initializing S8" severity error;
assert V9 = C20 report " error in initializing S9" severity error;
assert V10 = C21 report " error in initializing S10" severity error;
assert V11 = C22 report " error in initializing S11" severity error;
assert V12 = C23 report " error in initializing S12" severity error;
assert V13 = C24 report " error in initializing S13" severity error;
assert V14 = C25 report " error in initializing S14" severity error;
assert V15 = C26 report " error in initializing S15" severity error;
assert V16 = C27 report " error in initializing S16" severity error;
assert V17 = C28 report " error in initializing S17" severity error;
assert V18 = C29 report " error in initializing S18" severity error;
assert V19 = C30 report " error in initializing S19" severity error;
assert V20 = C31 report " error in initializing S20" severity error;
assert V21 = C32 report " error in initializing S21" severity error;
assert V22 = C50 report " error in initializing S22" severity error;
assert V23 = C51 report " error in initializing S23" severity error;
assert V24 = C53 report " error in initializing S24" severity error;
assert V25 = C70 report " error in initializing S25" severity error;
assert V26 = C71 report " error in initializing S26" severity error;
assert V27 = C72 report " error in initializing S27" severity error;
assert V28 = C73 report " error in initializing S28" severity error;
assert V29 = C74 report " error in initializing S29" severity error;
assert V30 = C75 report " error in initializing S30" severity error;
assert V31 = C76 report " error in initializing S31" severity error;
assert V32 = C54a report " error in initializing S32" severity error;
assert V33 = C54a report " error in initializing S33" severity error;
assert V34 = C54b report " error in initializing S34" severity error;
assert V35 = C55 report " error in initializing S35" severity error;
assert V36 = C60 report " error in initializing S36" severity error;
assert V37 = C61 report " error in initializing S37" severity error;
assert V41= C78 report " error in initializing S41" severity error;
assert V42= C79 report " error in initializing S42" severity error;
assert V43= C80 report " error in initializing S43" severity error;
assert V44= C81 report " error in initializing S44" severity error;
assert V45= C82 report " error in initializing S45" severity error;
assert V46= C83 report " error in initializing S46" severity error;
assert V47= C84 report " error in initializing S47" severity error;
assert V48= C85 report " error in initializing S48" severity error;
assert V49= C86 report " error in initializing S49" severity error;
assert V50= C88 report " error in initializing S50" severity error;
assert V51= C102 report " error in initializing S51" severity error;
assert NOT( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***PASSED TEST: c01s01b01x01p05n02i00752"
severity NOTE;
assert ( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***FAILED TEST: c01s01b01x01p05n02i00752 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00752arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc752.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x01p05n02i00752ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level := note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "shishir";
C11 : bit_vector := B"0011"
);
END c01s01b01x01p05n02i00752ent;
ARCHITECTURE c01s01b01x01p05n02i00752arch OF c01s01b01x01p05n02i00752ent IS
subtype hi_to_low_range is integer range zero to seven;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(zero to fifteen);
subtype severity_level_vector_st is severity_level_vector(zero to fifteen);
subtype integer_vector_st is integer_vector(zero to fifteen);
subtype real_vector_st is real_vector(zero to fifteen);
subtype time_vector_st is time_vector(zero to fifteen);
subtype natural_vector_st is natural_vector(zero to fifteen);
subtype positive_vector_st is positive_vector(zero to fifteen);
type boolean_cons_vector is array (fifteen downto zero) of boolean;
type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
type integer_cons_vector is array (fifteen downto zero) of integer;
type real_cons_vector is array (fifteen downto zero) of real;
type time_cons_vector is array (fifteen downto zero) of time;
type natural_cons_vector is array (fifteen downto zero) of natural;
type positive_cons_vector is array (fifteen downto zero) of positive;
type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector
;
type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;
type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(one to seven);
k:bit_vector(zero to three);
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_new is record
a:boolean_vector(zero to fifteen);
b:severity_level_vector(zero to fifteen);
c:integer_vector(zero to fifteen);
d:real_vector(zero to fifteen);
e:time_vector(zero to fifteen);
f:natural_vector(zero to fifteen);
g:positive_vector(zero to fifteen);
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
j: record_array_new;
end record;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
subtype integer_vector_range is integer_vector(hi_to_low_range);
subtype real_vector_range is real_vector(hi_to_low_range);
subtype time_vector_range is time_vector(hi_to_low_range);
subtype natural_vector_range is natural_vector(hi_to_low_range);
subtype positive_vector_range is positive_vector(hi_to_low_range);
type array_rec_std is array (integer range <>) of record_std_package;
type array_rec_cons is array (integer range <>) of record_cons_array;
type array_rec_rec is array (integer range <>) of record_of_records;
subtype array_rec_std_st is array_rec_std (hi_to_low_range);
subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
type record_of_arr_of_record is record
a: array_rec_std(zero to seven);
b: array_rec_cons(zero to seven);
c: array_rec_rec(zero to seven);
end record;
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type current_vector is array (natural range <>) of current;
subtype current_vector_range is current_vector(hi_to_low_range);
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_vector is array (natural range <>) of resistance;
subtype resistance_vector_range is resistance_vector(hi_to_low_range);
type byte is array(zero to seven) of bit;
subtype word is bit_vector(zero to fifteen); --constrained array
constant size :integer := seven;
type primary_memory is array(zero to size) of word; --array of an array
type primary_memory_module is --record with field
record --as an array
enable:bit;
memory_number:primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module; --array of a complex record
subtype delay is integer range one to 10;
constant C12 : boolean_vector := (C1,false);
constant C13 : severity_level_vector := (C4,error);
constant C14 : integer_vector := (one,two,three,four);
constant C15 : real_vector := (1.0,2.0,C6,4.0);
constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
constant C17 : natural_vector := (one,2,3,4);
constant C18 : positive_vector := (one,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st:= (others => C4);
constant C72 : integer_vector_st:=(others => C5);
constant C73 : real_vector_st:=(others => C6);
constant C74 : time_vector_st:=(others => C7);
constant C75 : natural_vector_st:=(others => C8);
constant C76 : positive_vector_st:=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54b: record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records := (C50,C51,C53,C77,C54b);
constant C60 : byte := (others => '0');
constant C61 : word := (others =>'0' );
constant C64 : primary_memory := (others => C61);
constant C65 : primary_memory_module := ('1',C64);
constant C66 : whole_memory := (others => C65);
constant C67 : current := 1 A;
constant C68 : resistance := 1 Ohm;
constant C69 : delay := 2;
constant C78: boolean_vector_range := (others => C1);
constant C79: severity_level_vector_range := (others => C4) ;
constant C80: integer_vector_range :=(others => C5) ;
constant C81: real_vector_range :=(others => C6);
constant C82: time_vector_range :=(others => C7);
constant C83: natural_vector_range :=(others => C8);
constant C84: positive_vector_range :=(others => C9);
constant C85: array_rec_std(0 to 7) :=(others => C50) ;
constant C86: array_rec_cons (0 to 7) :=(others => C51);
constant C88: array_rec_rec(0 to 7) :=(others => C55);
constant C102: record_of_arr_of_record:= (C85,C86,C88);
BEGIN
TESTING: PROCESS
variable V1 : boolean_vector(zero to fifteen) := (zero to fifteen => C1);
variable V2 : severity_level_vector(zero to fifteen):= (zero to fifteen => C4);
variable V3 : integer_vector(zero to fifteen) := (zero to fifteen => C5);
variable V4 : real_vector(zero to fifteen) := (zero to fifteen => C6);
variable V5 : time_vector (zero to fifteen) := (zero to fifteen => C7);
variable V6 : natural_vector(zero to fifteen):= (zero to fifteen => C8);
variable V7 : positive_vector(zero to fifteen):= (zero to fifteen => C9);
variable V8 : boolean_cons_vector:= C19;
variable V9 : severity_level_cons_vector := C20;
variable V10 : integer_cons_vector:= C21;
variable V11 : real_cons_vector:= C22;
variable V12 : time_cons_vector := C23;
variable V13 : natural_cons_vector := C24;
variable V14 : positive_cons_vector := C25;
variable V15 : boolean_cons_vectorofvector := C26;
variable V16 : severity_level_cons_vectorofvector:= C27;
variable V17 : integer_cons_vectorofvector:= C28;
variable V18 : real_cons_vectorofvector:= C29;
variable V19 : time_cons_vectorofvector:= C30;
variable V20 : natural_cons_vectorofvector:= C31;
variable V21 : positive_cons_vectorofvector:= C32;
variable V22 : record_std_package:= C50;
variable V23 : record_cons_array := C51;
variable V24 : record_cons_arrayofarray := C53 ;
variable V25 : boolean_vector_st:= C70 ;
variable V26 : severity_level_vector_st := C71;
variable V27 : integer_vector_st:= C72;
variable V28 : real_vector_st := C73;
variable V29 : time_vector_st := C74;
variable V30 : natural_vector_st:= C75;
variable V31 : positive_vector_st := C76;
variable V32 : record_array_st := C54a;
variable V33 : record_array_st := C54a;
variable V34 : record_array_new:= C54b;
variable V35 : record_of_records := C55;
variable V36 : byte := C60;
variable V37 : word := C61;
variable V41 : boolean_vector_range := C78;
variable V42 : severity_level_vector_range := C79;
variable V43 : integer_vector_range := C80;
variable V44 : real_vector_range:= C81 ;
variable V45 : time_vector_range := C82;
variable V46 : natural_vector_range := C83;
variable V47 : positive_vector_range := C84;
variable V48 : array_rec_std(zero to seven) := C85;
variable V49 : array_rec_cons(zero to seven) := C86;
variable V50 : array_rec_rec(zero to seven) := C88;
variable V51 : record_of_arr_of_record := C102;
BEGIN
assert (V1(0) = C1) report " error in initializing S1" severity error;
assert (V2(0) = C4) report " error in initializing S2" severity error;
assert (V3(0) = C5) report " error in initializing S3" severity error;
assert (V4(0) = C6) report " error in initializing S4" severity error;
assert (V5(0) = C7) report " error in initializing S5" severity error;
assert (V6(0) = C8) report " error in initializing S6" severity error;
assert (V7(0) = C9) report " error in initializing S7" severity error;
assert V8 = C19 report " error in initializing S8" severity error;
assert V9 = C20 report " error in initializing S9" severity error;
assert V10 = C21 report " error in initializing S10" severity error;
assert V11 = C22 report " error in initializing S11" severity error;
assert V12 = C23 report " error in initializing S12" severity error;
assert V13 = C24 report " error in initializing S13" severity error;
assert V14 = C25 report " error in initializing S14" severity error;
assert V15 = C26 report " error in initializing S15" severity error;
assert V16 = C27 report " error in initializing S16" severity error;
assert V17 = C28 report " error in initializing S17" severity error;
assert V18 = C29 report " error in initializing S18" severity error;
assert V19 = C30 report " error in initializing S19" severity error;
assert V20 = C31 report " error in initializing S20" severity error;
assert V21 = C32 report " error in initializing S21" severity error;
assert V22 = C50 report " error in initializing S22" severity error;
assert V23 = C51 report " error in initializing S23" severity error;
assert V24 = C53 report " error in initializing S24" severity error;
assert V25 = C70 report " error in initializing S25" severity error;
assert V26 = C71 report " error in initializing S26" severity error;
assert V27 = C72 report " error in initializing S27" severity error;
assert V28 = C73 report " error in initializing S28" severity error;
assert V29 = C74 report " error in initializing S29" severity error;
assert V30 = C75 report " error in initializing S30" severity error;
assert V31 = C76 report " error in initializing S31" severity error;
assert V32 = C54a report " error in initializing S32" severity error;
assert V33 = C54a report " error in initializing S33" severity error;
assert V34 = C54b report " error in initializing S34" severity error;
assert V35 = C55 report " error in initializing S35" severity error;
assert V36 = C60 report " error in initializing S36" severity error;
assert V37 = C61 report " error in initializing S37" severity error;
assert V41= C78 report " error in initializing S41" severity error;
assert V42= C79 report " error in initializing S42" severity error;
assert V43= C80 report " error in initializing S43" severity error;
assert V44= C81 report " error in initializing S44" severity error;
assert V45= C82 report " error in initializing S45" severity error;
assert V46= C83 report " error in initializing S46" severity error;
assert V47= C84 report " error in initializing S47" severity error;
assert V48= C85 report " error in initializing S48" severity error;
assert V49= C86 report " error in initializing S49" severity error;
assert V50= C88 report " error in initializing S50" severity error;
assert V51= C102 report " error in initializing S51" severity error;
assert NOT( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***PASSED TEST: c01s01b01x01p05n02i00752"
severity NOTE;
assert ( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***FAILED TEST: c01s01b01x01p05n02i00752 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00752arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc752.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x01p05n02i00752ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
C1 : boolean := true;
C2 : bit := '1';
C3 : character := 's';
C4 : severity_level := note;
C5 : integer := 3;
C6 : real := 3.0;
C7 : time := 3 ns;
C8 : natural := 1;
C9 : positive := 1;
C10 : string := "shishir";
C11 : bit_vector := B"0011"
);
END c01s01b01x01p05n02i00752ent;
ARCHITECTURE c01s01b01x01p05n02i00752arch OF c01s01b01x01p05n02i00752ent IS
subtype hi_to_low_range is integer range zero to seven;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(zero to fifteen);
subtype severity_level_vector_st is severity_level_vector(zero to fifteen);
subtype integer_vector_st is integer_vector(zero to fifteen);
subtype real_vector_st is real_vector(zero to fifteen);
subtype time_vector_st is time_vector(zero to fifteen);
subtype natural_vector_st is natural_vector(zero to fifteen);
subtype positive_vector_st is positive_vector(zero to fifteen);
type boolean_cons_vector is array (fifteen downto zero) of boolean;
type severity_level_cons_vector is array (fifteen downto zero) of severity_level;
type integer_cons_vector is array (fifteen downto zero) of integer;
type real_cons_vector is array (fifteen downto zero) of real;
type time_cons_vector is array (fifteen downto zero) of time;
type natural_cons_vector is array (fifteen downto zero) of natural;
type positive_cons_vector is array (fifteen downto zero) of positive;
type boolean_cons_vectorofvector is array (zero to fifteen) of boolean_cons_vector;
type severity_level_cons_vectorofvector is array (zero to fifteen) of severity_level_cons_vector;
type integer_cons_vectorofvector is array (zero to fifteen) of integer_cons_vector
;
type real_cons_vectorofvector is array (zero to fifteen) of real_cons_vector;
type time_cons_vectorofvector is array (zero to fifteen) of time_cons_vector;
type natural_cons_vectorofvector is array (zero to fifteen) of natural_cons_vector;
type positive_cons_vectorofvector is array (zero to fifteen) of positive_cons_vector;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
j:string(one to seven);
k:bit_vector(zero to three);
end record;
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_cons_arrayofarray is record
a:boolean_cons_vectorofvector;
b:severity_level_cons_vectorofvector;
c:integer_cons_vectorofvector;
d:real_cons_vectorofvector;
e:time_cons_vectorofvector;
f:natural_cons_vectorofvector;
g:positive_cons_vectorofvector;
end record;
type record_array_new is record
a:boolean_vector(zero to fifteen);
b:severity_level_vector(zero to fifteen);
c:integer_vector(zero to fifteen);
d:real_vector(zero to fifteen);
e:time_vector(zero to fifteen);
f:natural_vector(zero to fifteen);
g:positive_vector(zero to fifteen);
end record;
type record_of_records is record
a: record_std_package;
c: record_cons_array;
g: record_cons_arrayofarray;
i: record_array_st;
j: record_array_new;
end record;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
subtype integer_vector_range is integer_vector(hi_to_low_range);
subtype real_vector_range is real_vector(hi_to_low_range);
subtype time_vector_range is time_vector(hi_to_low_range);
subtype natural_vector_range is natural_vector(hi_to_low_range);
subtype positive_vector_range is positive_vector(hi_to_low_range);
type array_rec_std is array (integer range <>) of record_std_package;
type array_rec_cons is array (integer range <>) of record_cons_array;
type array_rec_rec is array (integer range <>) of record_of_records;
subtype array_rec_std_st is array_rec_std (hi_to_low_range);
subtype array_rec_cons_st is array_rec_cons (hi_to_low_range);
subtype array_rec_rec_st is array_rec_rec (hi_to_low_range);
type record_of_arr_of_record is record
a: array_rec_std(zero to seven);
b: array_rec_cons(zero to seven);
c: array_rec_rec(zero to seven);
end record;
type current is range -2147483647 to +2147483647
units
nA;
uA = 1000 nA;
mA = 1000 uA;
A = 1000 mA;
end units;
type current_vector is array (natural range <>) of current;
subtype current_vector_range is current_vector(hi_to_low_range);
type resistance is range -2147483647 to +2147483647
units
uOhm;
mOhm = 1000 uOhm;
Ohm = 1000 mOhm;
KOhm = 1000 Ohm;
end units;
type resistance_vector is array (natural range <>) of resistance;
subtype resistance_vector_range is resistance_vector(hi_to_low_range);
type byte is array(zero to seven) of bit;
subtype word is bit_vector(zero to fifteen); --constrained array
constant size :integer := seven;
type primary_memory is array(zero to size) of word; --array of an array
type primary_memory_module is --record with field
record --as an array
enable:bit;
memory_number:primary_memory;
end record;
type whole_memory is array(0 to size) of primary_memory_module; --array of a complex record
subtype delay is integer range one to 10;
constant C12 : boolean_vector := (C1,false);
constant C13 : severity_level_vector := (C4,error);
constant C14 : integer_vector := (one,two,three,four);
constant C15 : real_vector := (1.0,2.0,C6,4.0);
constant C16 : time_vector := (1 ns, 2 ns,C7, 4 ns);
constant C17 : natural_vector := (one,2,3,4);
constant C18 : positive_vector := (one,2,3,4);
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
constant C26 : boolean_cons_vectorofvector := (others => (others => C1));
constant C27 : severity_level_cons_vectorofvector := (others => (others => C4));
constant C28 : integer_cons_vectorofvector := (others => (others => C5));
constant C29 : real_cons_vectorofvector := (others => (others => C6));
constant C30 : time_cons_vectorofvector := (others => (others => C7));
constant C31 : natural_cons_vectorofvector := (others => (others => C8));
constant C32 : positive_cons_vectorofvector := (others => (others => C9));
constant C50 : record_std_package := (C1,C2,C3,C4,C5,C6,C7,C8,C9,C10,C11);
constant C51 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
constant C53 : record_cons_arrayofarray := (C26,C27,C28,C29,C30,C31,C32);
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st:= (others => C4);
constant C72 : integer_vector_st:=(others => C5);
constant C73 : real_vector_st:=(others => C6);
constant C74 : time_vector_st:=(others => C7);
constant C75 : natural_vector_st:=(others => C8);
constant C76 : positive_vector_st:=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54a : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
constant C54b: record_array_new:= (C70,C71,C72,C73,C74,C75,C76);
constant C55 : record_of_records := (C50,C51,C53,C77,C54b);
constant C60 : byte := (others => '0');
constant C61 : word := (others =>'0' );
constant C64 : primary_memory := (others => C61);
constant C65 : primary_memory_module := ('1',C64);
constant C66 : whole_memory := (others => C65);
constant C67 : current := 1 A;
constant C68 : resistance := 1 Ohm;
constant C69 : delay := 2;
constant C78: boolean_vector_range := (others => C1);
constant C79: severity_level_vector_range := (others => C4) ;
constant C80: integer_vector_range :=(others => C5) ;
constant C81: real_vector_range :=(others => C6);
constant C82: time_vector_range :=(others => C7);
constant C83: natural_vector_range :=(others => C8);
constant C84: positive_vector_range :=(others => C9);
constant C85: array_rec_std(0 to 7) :=(others => C50) ;
constant C86: array_rec_cons (0 to 7) :=(others => C51);
constant C88: array_rec_rec(0 to 7) :=(others => C55);
constant C102: record_of_arr_of_record:= (C85,C86,C88);
BEGIN
TESTING: PROCESS
variable V1 : boolean_vector(zero to fifteen) := (zero to fifteen => C1);
variable V2 : severity_level_vector(zero to fifteen):= (zero to fifteen => C4);
variable V3 : integer_vector(zero to fifteen) := (zero to fifteen => C5);
variable V4 : real_vector(zero to fifteen) := (zero to fifteen => C6);
variable V5 : time_vector (zero to fifteen) := (zero to fifteen => C7);
variable V6 : natural_vector(zero to fifteen):= (zero to fifteen => C8);
variable V7 : positive_vector(zero to fifteen):= (zero to fifteen => C9);
variable V8 : boolean_cons_vector:= C19;
variable V9 : severity_level_cons_vector := C20;
variable V10 : integer_cons_vector:= C21;
variable V11 : real_cons_vector:= C22;
variable V12 : time_cons_vector := C23;
variable V13 : natural_cons_vector := C24;
variable V14 : positive_cons_vector := C25;
variable V15 : boolean_cons_vectorofvector := C26;
variable V16 : severity_level_cons_vectorofvector:= C27;
variable V17 : integer_cons_vectorofvector:= C28;
variable V18 : real_cons_vectorofvector:= C29;
variable V19 : time_cons_vectorofvector:= C30;
variable V20 : natural_cons_vectorofvector:= C31;
variable V21 : positive_cons_vectorofvector:= C32;
variable V22 : record_std_package:= C50;
variable V23 : record_cons_array := C51;
variable V24 : record_cons_arrayofarray := C53 ;
variable V25 : boolean_vector_st:= C70 ;
variable V26 : severity_level_vector_st := C71;
variable V27 : integer_vector_st:= C72;
variable V28 : real_vector_st := C73;
variable V29 : time_vector_st := C74;
variable V30 : natural_vector_st:= C75;
variable V31 : positive_vector_st := C76;
variable V32 : record_array_st := C54a;
variable V33 : record_array_st := C54a;
variable V34 : record_array_new:= C54b;
variable V35 : record_of_records := C55;
variable V36 : byte := C60;
variable V37 : word := C61;
variable V41 : boolean_vector_range := C78;
variable V42 : severity_level_vector_range := C79;
variable V43 : integer_vector_range := C80;
variable V44 : real_vector_range:= C81 ;
variable V45 : time_vector_range := C82;
variable V46 : natural_vector_range := C83;
variable V47 : positive_vector_range := C84;
variable V48 : array_rec_std(zero to seven) := C85;
variable V49 : array_rec_cons(zero to seven) := C86;
variable V50 : array_rec_rec(zero to seven) := C88;
variable V51 : record_of_arr_of_record := C102;
BEGIN
assert (V1(0) = C1) report " error in initializing S1" severity error;
assert (V2(0) = C4) report " error in initializing S2" severity error;
assert (V3(0) = C5) report " error in initializing S3" severity error;
assert (V4(0) = C6) report " error in initializing S4" severity error;
assert (V5(0) = C7) report " error in initializing S5" severity error;
assert (V6(0) = C8) report " error in initializing S6" severity error;
assert (V7(0) = C9) report " error in initializing S7" severity error;
assert V8 = C19 report " error in initializing S8" severity error;
assert V9 = C20 report " error in initializing S9" severity error;
assert V10 = C21 report " error in initializing S10" severity error;
assert V11 = C22 report " error in initializing S11" severity error;
assert V12 = C23 report " error in initializing S12" severity error;
assert V13 = C24 report " error in initializing S13" severity error;
assert V14 = C25 report " error in initializing S14" severity error;
assert V15 = C26 report " error in initializing S15" severity error;
assert V16 = C27 report " error in initializing S16" severity error;
assert V17 = C28 report " error in initializing S17" severity error;
assert V18 = C29 report " error in initializing S18" severity error;
assert V19 = C30 report " error in initializing S19" severity error;
assert V20 = C31 report " error in initializing S20" severity error;
assert V21 = C32 report " error in initializing S21" severity error;
assert V22 = C50 report " error in initializing S22" severity error;
assert V23 = C51 report " error in initializing S23" severity error;
assert V24 = C53 report " error in initializing S24" severity error;
assert V25 = C70 report " error in initializing S25" severity error;
assert V26 = C71 report " error in initializing S26" severity error;
assert V27 = C72 report " error in initializing S27" severity error;
assert V28 = C73 report " error in initializing S28" severity error;
assert V29 = C74 report " error in initializing S29" severity error;
assert V30 = C75 report " error in initializing S30" severity error;
assert V31 = C76 report " error in initializing S31" severity error;
assert V32 = C54a report " error in initializing S32" severity error;
assert V33 = C54a report " error in initializing S33" severity error;
assert V34 = C54b report " error in initializing S34" severity error;
assert V35 = C55 report " error in initializing S35" severity error;
assert V36 = C60 report " error in initializing S36" severity error;
assert V37 = C61 report " error in initializing S37" severity error;
assert V41= C78 report " error in initializing S41" severity error;
assert V42= C79 report " error in initializing S42" severity error;
assert V43= C80 report " error in initializing S43" severity error;
assert V44= C81 report " error in initializing S44" severity error;
assert V45= C82 report " error in initializing S45" severity error;
assert V46= C83 report " error in initializing S46" severity error;
assert V47= C84 report " error in initializing S47" severity error;
assert V48= C85 report " error in initializing S48" severity error;
assert V49= C86 report " error in initializing S49" severity error;
assert V50= C88 report " error in initializing S50" severity error;
assert V51= C102 report " error in initializing S51" severity error;
assert NOT( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***PASSED TEST: c01s01b01x01p05n02i00752"
severity NOTE;
assert ( (V1(0) = C1) and
(V2(0) = C4) and
(V3(0) = C5) and
(V4(0) = C6) and
(V5(0) = C7) and
(V6(0) = C8) and
(V7(0) = C9) and
V8 = C19 and
V9 = C20 and
V10 = C21 and
V11 = C22 and
V12 = C23 and
V13 = C24 and
V14 = C25 and
V15 = C26 and
V16 = C27 and
V17 = C28 and
V18 = C29 and
V19 = C30 and
V20 = C31 and
V21 = C32 and
V22 = C50 and
V23 = C51 and
V24 = C53 and
V25 = C70 and
V26 = C71 and
V27 = C72 and
V28 = C73 and
V29 = C74 and
V30 = C75 and
V31 = C76 and
V32 = C54a and
V33 = C54a and
V34= C54b and
V35 = C55 and
V36 = C60 and
V37 = C61 and
V41= C78 and
V42= C79 and
V43= C80 and
V44= C81 and
V45= C82 and
V46= C83 and
V47= C84 and
V48= C85 and
V49= C86 and
V50= C88 and
V51= C102 )
report "***FAILED TEST: c01s01b01x01p05n02i00752 - Generic can be used to specify the size of ports."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p05n02i00752arch;
|
-------------------------------------------------------------------------------
-- Title : Strobe generator
-- Project :
-------------------------------------------------------------------------------
-- File : decimation_strober.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2016-05-05
-- Last update:
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Generates one strobe every ratio_i times valid_i is asserted
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-05 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.dsp_cores_pkg.all;
-------------------------------------------------------------------------------
entity decimation_strober is
generic (
g_maxrate : natural := 2048;
g_bus_width : natural := 11
);
port (
clk_i : in std_logic;
rst_i : in std_logic;
ce_i : in std_logic;
valid_i : in std_logic;
ratio_i : in std_logic_vector(g_bus_width-1 downto 0);
strobe_o : out std_logic
);
end entity decimation_strober;
-------------------------------------------------------------------------------
architecture str of decimation_strober is
signal count : unsigned(g_bus_width-1 downto 0) := to_unsigned(0, g_bus_width);
signal strobe : std_logic := '0';
signal count_all : std_logic := '0';
begin -- architecture str
p_counting : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
count <= to_unsigned(0, count'length);
count_all <= '0';
else
if ce_i = '1' then
if valid_i = '1' then
count <= count + 1;
count_all <= '0';
if count = to_integer(unsigned(ratio_i))-1 then
count <= to_unsigned(0, count'length);
count_all <= '1';
end if;
-- count_all must be asserted for 1 CE cycle only
else
count_all <= '0';
end if; -- valid_i
end if; -- ce
end if; -- reset
end if; -- rising_edge
end process;
strobe_o <= count_all;
end architecture str;
-------------------------------------------------------------------------------
|
entity toplevel4 is
generic ( config : string; r : real; t : time );
end entity;
architecture test of toplevel4 is
begin
assert config = "hello";
assert r = 2.5;
assert t = 5 ms;
end architecture;
|
--
-- File Increment: TbNamesPkg.vhd
-- Design Unit Increment: TbNamesPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis SynthWorks
--
--
-- Package Defines
-- Data structure for Increment.
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
--
-- Revision History:
-- Date Version Description
-- 05/2015 2015.06 Added input to Get to return when not initialized
--
--
-- Copyright (c) 2010 - 2016 by SynthWorks Design Inc. All rights reserved.
--
package TbNamesPkg is
type IncrementPType is protected
procedure Inc ;
impure function Get return integer ;
end protected IncrementPType ;
procedure PrintNames ;
procedure CallPrintNames ;
end package TbNamesPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body TbNamesPkg is
type IncrementPType is protected body
variable IncrementVar : integer := 0 ;
impure function PrintNamesFun(S : string) return integer is
begin
report "IncrementVar'INSTANCE_NAME as a parameter: " & S ;
report "IncrementVar: INSTANCE_NAME " & IncrementVar'INSTANCE_NAME ;
report "IncrementVar: PATH_NAME " & IncrementVar'PATH_NAME ;
report "function PrintNamesFun: INSTANCE_NAME " & PrintNamesFun'INSTANCE_NAME ;
report "function PrintNamesFun: PATH_NAME " & PrintNamesFun'PATH_NAME ;
return 0 ;
end function PrintNamesFun ;
variable Temp : integer := PrintNamesFun(IncrementVar'INSTANCE_NAME) ;
------------------------------------------------------------
procedure Inc is
------------------------------------------------------------
begin
IncrementVar := IncrementVar + 1 ;
end procedure Inc ;
------------------------------------------------------------
impure function Get return integer is
------------------------------------------------------------
begin
report "IncrementVar: INSTANCE_NAME " & IncrementVar'INSTANCE_NAME ;
report "IncrementVar: PATH_NAME " & IncrementVar'PATH_NAME ;
report "Method Get: INSTANCE_NAME " & Get'INSTANCE_NAME ;
report "Method Get: PATH_NAME " & Get'PATH_NAME ;
return IncrementVar ;
end function Get ;
end protected body IncrementPType ;
procedure PrintNames is
begin
report "procedure PrintNames: INSTANCE_NAME " & PrintNames'INSTANCE_NAME ;
report "procedure PrintNames: PATH_NAME " & PrintNames'PATH_NAME ;
end procedure PrintNames ;
procedure CallPrintNames is
begin
PrintNames ;
end procedure CallPrintNames ;
end package body TbNamesPkg ;
|
--
-- File Increment: TbNamesPkg.vhd
-- Design Unit Increment: TbNamesPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis SynthWorks
--
--
-- Package Defines
-- Data structure for Increment.
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
--
-- Revision History:
-- Date Version Description
-- 05/2015 2015.06 Added input to Get to return when not initialized
--
--
-- Copyright (c) 2010 - 2016 by SynthWorks Design Inc. All rights reserved.
--
package TbNamesPkg is
type IncrementPType is protected
procedure Inc ;
impure function Get return integer ;
end protected IncrementPType ;
procedure PrintNames ;
procedure CallPrintNames ;
end package TbNamesPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body TbNamesPkg is
type IncrementPType is protected body
variable IncrementVar : integer := 0 ;
impure function PrintNamesFun(S : string) return integer is
begin
report "IncrementVar'INSTANCE_NAME as a parameter: " & S ;
report "IncrementVar: INSTANCE_NAME " & IncrementVar'INSTANCE_NAME ;
report "IncrementVar: PATH_NAME " & IncrementVar'PATH_NAME ;
report "function PrintNamesFun: INSTANCE_NAME " & PrintNamesFun'INSTANCE_NAME ;
report "function PrintNamesFun: PATH_NAME " & PrintNamesFun'PATH_NAME ;
return 0 ;
end function PrintNamesFun ;
variable Temp : integer := PrintNamesFun(IncrementVar'INSTANCE_NAME) ;
------------------------------------------------------------
procedure Inc is
------------------------------------------------------------
begin
IncrementVar := IncrementVar + 1 ;
end procedure Inc ;
------------------------------------------------------------
impure function Get return integer is
------------------------------------------------------------
begin
report "IncrementVar: INSTANCE_NAME " & IncrementVar'INSTANCE_NAME ;
report "IncrementVar: PATH_NAME " & IncrementVar'PATH_NAME ;
report "Method Get: INSTANCE_NAME " & Get'INSTANCE_NAME ;
report "Method Get: PATH_NAME " & Get'PATH_NAME ;
return IncrementVar ;
end function Get ;
end protected body IncrementPType ;
procedure PrintNames is
begin
report "procedure PrintNames: INSTANCE_NAME " & PrintNames'INSTANCE_NAME ;
report "procedure PrintNames: PATH_NAME " & PrintNames'PATH_NAME ;
end procedure PrintNames ;
procedure CallPrintNames is
begin
PrintNames ;
end procedure CallPrintNames ;
end package body TbNamesPkg ;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Package: Simulation constants, functions and utilities.
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
use STD.TextIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
-- use PoC.utils.all;
-- use PoC.strings.all;
use PoC.vectors.all;
-- use PoC.physical.all;
package sim_types is
-- Simulation Task and Status Management
-- ===========================================================================
subtype T_SIM_PROCESS_ID is NATURAL range 0 to 1023;
subtype T_SIM_PROCESS_NAME is STRING(1 to 64);
subtype T_SIM_PROCESS_INSTNAME is STRING(1 to 256);
type T_SIM_PROCESS_STATUS is (
SIM_PROCESS_STATUS_ACTIVE,
SIM_PROCESS_STATUS_ENDED
);
type T_SIM_PROCESS is record
ID : T_SIM_PROCESS_ID;
Name : T_SIM_PROCESS_NAME;
InstanceName : T_SIM_PROCESS_INSTNAME;
Status : T_SIM_PROCESS_STATUS;
end record;
type T_SIM_PROCESS_VECTOR is array(NATURAL range <>) of T_SIM_PROCESS;
subtype T_SIM_TEST_ID is NATURAL range 0 to 1023;
subtype T_SIM_TEST_NAME is STRING(1 to 256);
type T_SIM_TEST_STATUS is (
SIM_TEST_STATUS_ACTIVE,
SIM_TEST_STATUS_ENDED
);
type T_SIM_TEST is record
ID : T_SIM_TEST_ID;
Name : T_SIM_TEST_NAME;
Status : T_SIM_TEST_STATUS;
end record;
type T_SIM_TEST_VECTOR is array(NATURAL range <>) of T_SIM_TEST;
-- clock generation
-- ===========================================================================
-- type T_PERCENT is INTEGER'range units
type T_PERCENT is range INTEGER'low to INTEGER'high units
ppb;
ppm = 1000 ppb;
permil = 1000 ppm;
percent = 10 permil;
one = 100 percent;
end units;
subtype T_WANDER is T_PERCENT range -1 one to 1 one;
subtype T_DUTYCYCLE is T_PERCENT range 0 ppb to 1 one;
type T_DEGREE is range INTEGER'low to INTEGER'high units
second;
minute = 60 second;
deg = 60 minute;
end units;
subtype T_PHASE is T_DEGREE range -360 deg to 360 deg;
function ite(cond : BOOLEAN; value1 : T_DEGREE; value2 : T_DEGREE) return T_DEGREE;
-- waveform generation
-- ===========================================================================
type T_SIM_WAVEFORM_TUPLE_SL is record
Delay : TIME;
Value : STD_LOGIC;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_8 is record
Delay : TIME;
Value : T_SLV_8;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_16 is record
Delay : TIME;
Value : T_SLV_16;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_24 is record
Delay : TIME;
Value : T_SLV_24;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_32 is record
Delay : TIME;
Value : T_SLV_32;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_48 is record
Delay : TIME;
Value : T_SLV_48;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_64 is record
Delay : TIME;
Value : T_SLV_64;
end record;
type T_SIM_WAVEFORM_SL is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SL;
type T_SIM_WAVEFORM_SLV_8 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_8;
type T_SIM_WAVEFORM_SLV_16 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_16;
type T_SIM_WAVEFORM_SLV_24 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_24;
type T_SIM_WAVEFORM_SLV_32 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_32;
type T_SIM_WAVEFORM_SLV_48 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_48;
type T_SIM_WAVEFORM_SLV_64 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_64;
end package;
package body sim_types is
function ite(cond : BOOLEAN; value1 : T_DEGREE; value2 : T_DEGREE) return T_DEGREE is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
end package body;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Thomas B. Preusser
--
-- Package: Simulation constants, functions and utilities.
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
use STD.TextIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library PoC;
-- use PoC.utils.all;
-- use PoC.strings.all;
use PoC.vectors.all;
-- use PoC.physical.all;
package sim_types is
-- Simulation Task and Status Management
-- ===========================================================================
subtype T_SIM_PROCESS_ID is NATURAL range 0 to 1023;
subtype T_SIM_PROCESS_NAME is STRING(1 to 64);
subtype T_SIM_PROCESS_INSTNAME is STRING(1 to 256);
type T_SIM_PROCESS_STATUS is (
SIM_PROCESS_STATUS_ACTIVE,
SIM_PROCESS_STATUS_ENDED
);
type T_SIM_PROCESS is record
ID : T_SIM_PROCESS_ID;
Name : T_SIM_PROCESS_NAME;
InstanceName : T_SIM_PROCESS_INSTNAME;
Status : T_SIM_PROCESS_STATUS;
end record;
type T_SIM_PROCESS_VECTOR is array(NATURAL range <>) of T_SIM_PROCESS;
subtype T_SIM_TEST_ID is NATURAL range 0 to 1023;
subtype T_SIM_TEST_NAME is STRING(1 to 256);
type T_SIM_TEST_STATUS is (
SIM_TEST_STATUS_ACTIVE,
SIM_TEST_STATUS_ENDED
);
type T_SIM_TEST is record
ID : T_SIM_TEST_ID;
Name : T_SIM_TEST_NAME;
Status : T_SIM_TEST_STATUS;
end record;
type T_SIM_TEST_VECTOR is array(NATURAL range <>) of T_SIM_TEST;
-- clock generation
-- ===========================================================================
-- type T_PERCENT is INTEGER'range units
type T_PERCENT is range INTEGER'low to INTEGER'high units
ppb;
ppm = 1000 ppb;
permil = 1000 ppm;
percent = 10 permil;
one = 100 percent;
end units;
subtype T_WANDER is T_PERCENT range -1 one to 1 one;
subtype T_DUTYCYCLE is T_PERCENT range 0 ppb to 1 one;
type T_DEGREE is range INTEGER'low to INTEGER'high units
second;
minute = 60 second;
deg = 60 minute;
end units;
subtype T_PHASE is T_DEGREE range -360 deg to 360 deg;
function ite(cond : BOOLEAN; value1 : T_DEGREE; value2 : T_DEGREE) return T_DEGREE;
-- waveform generation
-- ===========================================================================
type T_SIM_WAVEFORM_TUPLE_SL is record
Delay : TIME;
Value : STD_LOGIC;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_8 is record
Delay : TIME;
Value : T_SLV_8;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_16 is record
Delay : TIME;
Value : T_SLV_16;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_24 is record
Delay : TIME;
Value : T_SLV_24;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_32 is record
Delay : TIME;
Value : T_SLV_32;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_48 is record
Delay : TIME;
Value : T_SLV_48;
end record;
type T_SIM_WAVEFORM_TUPLE_SLV_64 is record
Delay : TIME;
Value : T_SLV_64;
end record;
type T_SIM_WAVEFORM_SL is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SL;
type T_SIM_WAVEFORM_SLV_8 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_8;
type T_SIM_WAVEFORM_SLV_16 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_16;
type T_SIM_WAVEFORM_SLV_24 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_24;
type T_SIM_WAVEFORM_SLV_32 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_32;
type T_SIM_WAVEFORM_SLV_48 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_48;
type T_SIM_WAVEFORM_SLV_64 is array(NATURAL range <>) of T_SIM_WAVEFORM_TUPLE_SLV_64;
end package;
package body sim_types is
function ite(cond : BOOLEAN; value1 : T_DEGREE; value2 : T_DEGREE) return T_DEGREE is
begin
if cond then
return value1;
else
return value2;
end if;
end function;
end package body;
|
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|
`protect begin_protected
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|
`protect begin_protected
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|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.3.1 (lin64) Build 1056140 Thu Oct 30 16:30:39 MDT 2014
-- Date : Wed Apr 8 23:17:41 2015
-- Host : parallella running 64-bit Ubuntu 14.04.2 LTS
-- Command : write_vhdl -force -mode funcsim
-- /home/aolofsson/Work_all/parallella-hw/fpga/ip/xilinx/fifo_async_103x32/fifo_async_103x32_funcsim.vhdl
-- Design : fifo_async_103x32
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_dmem is
port (
Q : out STD_LOGIC_VECTOR ( 102 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
I1 : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
I2 : in STD_LOGIC_VECTOR ( 0 to 0 );
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
O2 : in STD_LOGIC_VECTOR ( 4 downto 0 );
O1 : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_dmem : entity is "dmem";
end fifo_async_103x32_dmem;
architecture STRUCTURE of fifo_async_103x32_dmem is
signal p_0_out : STD_LOGIC_VECTOR ( 102 downto 0 );
signal NLW_RAM_reg_0_31_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_102_102_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_RAM_reg_0_31_102_102_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_102_102_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_102_102_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_60_65_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_66_71_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_72_77_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_78_83_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_84_89_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_90_95_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_31_96_101_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
RAM_reg_0_31_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(1 downto 0),
DIB(1 downto 0) => din(3 downto 2),
DIC(1 downto 0) => din(5 downto 4),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(1 downto 0),
DOB(1 downto 0) => p_0_out(3 downto 2),
DOC(1 downto 0) => p_0_out(5 downto 4),
DOD(1 downto 0) => NLW_RAM_reg_0_31_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_102_102: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1) => '0',
DIA(0) => din(102),
DIB(1) => '0',
DIB(0) => '0',
DIC(1) => '0',
DIC(0) => '0',
DID(1) => '0',
DID(0) => '0',
DOA(1) => NLW_RAM_reg_0_31_102_102_DOA_UNCONNECTED(1),
DOA(0) => p_0_out(102),
DOB(1 downto 0) => NLW_RAM_reg_0_31_102_102_DOB_UNCONNECTED(1 downto 0),
DOC(1 downto 0) => NLW_RAM_reg_0_31_102_102_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_31_102_102_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(13 downto 12),
DIB(1 downto 0) => din(15 downto 14),
DIC(1 downto 0) => din(17 downto 16),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(13 downto 12),
DOB(1 downto 0) => p_0_out(15 downto 14),
DOC(1 downto 0) => p_0_out(17 downto 16),
DOD(1 downto 0) => NLW_RAM_reg_0_31_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(19 downto 18),
DIB(1 downto 0) => din(21 downto 20),
DIC(1 downto 0) => din(23 downto 22),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(19 downto 18),
DOB(1 downto 0) => p_0_out(21 downto 20),
DOC(1 downto 0) => p_0_out(23 downto 22),
DOD(1 downto 0) => NLW_RAM_reg_0_31_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(25 downto 24),
DIB(1 downto 0) => din(27 downto 26),
DIC(1 downto 0) => din(29 downto 28),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(25 downto 24),
DOB(1 downto 0) => p_0_out(27 downto 26),
DOC(1 downto 0) => p_0_out(29 downto 28),
DOD(1 downto 0) => NLW_RAM_reg_0_31_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(31 downto 30),
DIB(1 downto 0) => din(33 downto 32),
DIC(1 downto 0) => din(35 downto 34),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(31 downto 30),
DOB(1 downto 0) => p_0_out(33 downto 32),
DOC(1 downto 0) => p_0_out(35 downto 34),
DOD(1 downto 0) => NLW_RAM_reg_0_31_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_36_41: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(37 downto 36),
DIB(1 downto 0) => din(39 downto 38),
DIC(1 downto 0) => din(41 downto 40),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(37 downto 36),
DOB(1 downto 0) => p_0_out(39 downto 38),
DOC(1 downto 0) => p_0_out(41 downto 40),
DOD(1 downto 0) => NLW_RAM_reg_0_31_36_41_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_42_47: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(43 downto 42),
DIB(1 downto 0) => din(45 downto 44),
DIC(1 downto 0) => din(47 downto 46),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(43 downto 42),
DOB(1 downto 0) => p_0_out(45 downto 44),
DOC(1 downto 0) => p_0_out(47 downto 46),
DOD(1 downto 0) => NLW_RAM_reg_0_31_42_47_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_48_53: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(49 downto 48),
DIB(1 downto 0) => din(51 downto 50),
DIC(1 downto 0) => din(53 downto 52),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(49 downto 48),
DOB(1 downto 0) => p_0_out(51 downto 50),
DOC(1 downto 0) => p_0_out(53 downto 52),
DOD(1 downto 0) => NLW_RAM_reg_0_31_48_53_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_54_59: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(55 downto 54),
DIB(1 downto 0) => din(57 downto 56),
DIC(1 downto 0) => din(59 downto 58),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(55 downto 54),
DOB(1 downto 0) => p_0_out(57 downto 56),
DOC(1 downto 0) => p_0_out(59 downto 58),
DOD(1 downto 0) => NLW_RAM_reg_0_31_54_59_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_60_65: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(61 downto 60),
DIB(1 downto 0) => din(63 downto 62),
DIC(1 downto 0) => din(65 downto 64),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(61 downto 60),
DOB(1 downto 0) => p_0_out(63 downto 62),
DOC(1 downto 0) => p_0_out(65 downto 64),
DOD(1 downto 0) => NLW_RAM_reg_0_31_60_65_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_66_71: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(67 downto 66),
DIB(1 downto 0) => din(69 downto 68),
DIC(1 downto 0) => din(71 downto 70),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(67 downto 66),
DOB(1 downto 0) => p_0_out(69 downto 68),
DOC(1 downto 0) => p_0_out(71 downto 70),
DOD(1 downto 0) => NLW_RAM_reg_0_31_66_71_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(7 downto 6),
DIB(1 downto 0) => din(9 downto 8),
DIC(1 downto 0) => din(11 downto 10),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(7 downto 6),
DOB(1 downto 0) => p_0_out(9 downto 8),
DOC(1 downto 0) => p_0_out(11 downto 10),
DOD(1 downto 0) => NLW_RAM_reg_0_31_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_72_77: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(73 downto 72),
DIB(1 downto 0) => din(75 downto 74),
DIC(1 downto 0) => din(77 downto 76),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(73 downto 72),
DOB(1 downto 0) => p_0_out(75 downto 74),
DOC(1 downto 0) => p_0_out(77 downto 76),
DOD(1 downto 0) => NLW_RAM_reg_0_31_72_77_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_78_83: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(79 downto 78),
DIB(1 downto 0) => din(81 downto 80),
DIC(1 downto 0) => din(83 downto 82),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(79 downto 78),
DOB(1 downto 0) => p_0_out(81 downto 80),
DOC(1 downto 0) => p_0_out(83 downto 82),
DOD(1 downto 0) => NLW_RAM_reg_0_31_78_83_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_84_89: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(85 downto 84),
DIB(1 downto 0) => din(87 downto 86),
DIC(1 downto 0) => din(89 downto 88),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(85 downto 84),
DOB(1 downto 0) => p_0_out(87 downto 86),
DOC(1 downto 0) => p_0_out(89 downto 88),
DOD(1 downto 0) => NLW_RAM_reg_0_31_84_89_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_90_95: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(91 downto 90),
DIB(1 downto 0) => din(93 downto 92),
DIC(1 downto 0) => din(95 downto 94),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(91 downto 90),
DOB(1 downto 0) => p_0_out(93 downto 92),
DOC(1 downto 0) => p_0_out(95 downto 94),
DOD(1 downto 0) => NLW_RAM_reg_0_31_90_95_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
RAM_reg_0_31_96_101: unisim.vcomponents.RAM32M
port map (
ADDRA(4 downto 0) => O2(4 downto 0),
ADDRB(4 downto 0) => O2(4 downto 0),
ADDRC(4 downto 0) => O2(4 downto 0),
ADDRD(4 downto 0) => O1(4 downto 0),
DIA(1 downto 0) => din(97 downto 96),
DIB(1 downto 0) => din(99 downto 98),
DIC(1 downto 0) => din(101 downto 100),
DID(1) => '0',
DID(0) => '0',
DOA(1 downto 0) => p_0_out(97 downto 96),
DOB(1 downto 0) => p_0_out(99 downto 98),
DOC(1 downto 0) => p_0_out(101 downto 100),
DOD(1 downto 0) => NLW_RAM_reg_0_31_96_101_DOD_UNCONNECTED(1 downto 0),
WCLK => wr_clk,
WE => I2(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(0),
Q => Q(0)
);
\gpr1.dout_i_reg[100]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(100),
Q => Q(100)
);
\gpr1.dout_i_reg[101]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(101),
Q => Q(101)
);
\gpr1.dout_i_reg[102]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(102),
Q => Q(102)
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(10),
Q => Q(10)
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(11),
Q => Q(11)
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(12),
Q => Q(12)
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(13),
Q => Q(13)
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(14),
Q => Q(14)
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(15),
Q => Q(15)
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(16),
Q => Q(16)
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(17),
Q => Q(17)
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(18),
Q => Q(18)
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(19),
Q => Q(19)
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(1),
Q => Q(1)
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(20),
Q => Q(20)
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(21),
Q => Q(21)
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(22),
Q => Q(22)
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(23),
Q => Q(23)
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(24),
Q => Q(24)
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(25),
Q => Q(25)
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(26),
Q => Q(26)
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(27),
Q => Q(27)
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(28),
Q => Q(28)
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(29),
Q => Q(29)
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(2),
Q => Q(2)
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(30),
Q => Q(30)
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(31),
Q => Q(31)
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(32),
Q => Q(32)
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(33),
Q => Q(33)
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(34),
Q => Q(34)
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(35),
Q => Q(35)
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(36),
Q => Q(36)
);
\gpr1.dout_i_reg[37]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(37),
Q => Q(37)
);
\gpr1.dout_i_reg[38]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(38),
Q => Q(38)
);
\gpr1.dout_i_reg[39]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(39),
Q => Q(39)
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(3),
Q => Q(3)
);
\gpr1.dout_i_reg[40]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(40),
Q => Q(40)
);
\gpr1.dout_i_reg[41]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(41),
Q => Q(41)
);
\gpr1.dout_i_reg[42]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(42),
Q => Q(42)
);
\gpr1.dout_i_reg[43]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(43),
Q => Q(43)
);
\gpr1.dout_i_reg[44]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(44),
Q => Q(44)
);
\gpr1.dout_i_reg[45]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(45),
Q => Q(45)
);
\gpr1.dout_i_reg[46]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(46),
Q => Q(46)
);
\gpr1.dout_i_reg[47]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(47),
Q => Q(47)
);
\gpr1.dout_i_reg[48]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(48),
Q => Q(48)
);
\gpr1.dout_i_reg[49]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(49),
Q => Q(49)
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(4),
Q => Q(4)
);
\gpr1.dout_i_reg[50]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(50),
Q => Q(50)
);
\gpr1.dout_i_reg[51]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(51),
Q => Q(51)
);
\gpr1.dout_i_reg[52]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(52),
Q => Q(52)
);
\gpr1.dout_i_reg[53]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(53),
Q => Q(53)
);
\gpr1.dout_i_reg[54]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(54),
Q => Q(54)
);
\gpr1.dout_i_reg[55]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(55),
Q => Q(55)
);
\gpr1.dout_i_reg[56]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(56),
Q => Q(56)
);
\gpr1.dout_i_reg[57]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(57),
Q => Q(57)
);
\gpr1.dout_i_reg[58]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(58),
Q => Q(58)
);
\gpr1.dout_i_reg[59]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(59),
Q => Q(59)
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(5),
Q => Q(5)
);
\gpr1.dout_i_reg[60]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(60),
Q => Q(60)
);
\gpr1.dout_i_reg[61]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(61),
Q => Q(61)
);
\gpr1.dout_i_reg[62]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(62),
Q => Q(62)
);
\gpr1.dout_i_reg[63]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(63),
Q => Q(63)
);
\gpr1.dout_i_reg[64]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(64),
Q => Q(64)
);
\gpr1.dout_i_reg[65]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(65),
Q => Q(65)
);
\gpr1.dout_i_reg[66]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(66),
Q => Q(66)
);
\gpr1.dout_i_reg[67]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(67),
Q => Q(67)
);
\gpr1.dout_i_reg[68]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(68),
Q => Q(68)
);
\gpr1.dout_i_reg[69]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(69),
Q => Q(69)
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(6),
Q => Q(6)
);
\gpr1.dout_i_reg[70]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(70),
Q => Q(70)
);
\gpr1.dout_i_reg[71]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(71),
Q => Q(71)
);
\gpr1.dout_i_reg[72]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(72),
Q => Q(72)
);
\gpr1.dout_i_reg[73]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(73),
Q => Q(73)
);
\gpr1.dout_i_reg[74]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(74),
Q => Q(74)
);
\gpr1.dout_i_reg[75]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(75),
Q => Q(75)
);
\gpr1.dout_i_reg[76]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(76),
Q => Q(76)
);
\gpr1.dout_i_reg[77]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(77),
Q => Q(77)
);
\gpr1.dout_i_reg[78]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(78),
Q => Q(78)
);
\gpr1.dout_i_reg[79]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(79),
Q => Q(79)
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(7),
Q => Q(7)
);
\gpr1.dout_i_reg[80]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(80),
Q => Q(80)
);
\gpr1.dout_i_reg[81]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(81),
Q => Q(81)
);
\gpr1.dout_i_reg[82]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(82),
Q => Q(82)
);
\gpr1.dout_i_reg[83]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(83),
Q => Q(83)
);
\gpr1.dout_i_reg[84]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(84),
Q => Q(84)
);
\gpr1.dout_i_reg[85]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(85),
Q => Q(85)
);
\gpr1.dout_i_reg[86]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(86),
Q => Q(86)
);
\gpr1.dout_i_reg[87]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(87),
Q => Q(87)
);
\gpr1.dout_i_reg[88]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(88),
Q => Q(88)
);
\gpr1.dout_i_reg[89]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(89),
Q => Q(89)
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(8),
Q => Q(8)
);
\gpr1.dout_i_reg[90]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(90),
Q => Q(90)
);
\gpr1.dout_i_reg[91]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(91),
Q => Q(91)
);
\gpr1.dout_i_reg[92]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(92),
Q => Q(92)
);
\gpr1.dout_i_reg[93]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(93),
Q => Q(93)
);
\gpr1.dout_i_reg[94]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(94),
Q => Q(94)
);
\gpr1.dout_i_reg[95]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(95),
Q => Q(95)
);
\gpr1.dout_i_reg[96]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(96),
Q => Q(96)
);
\gpr1.dout_i_reg[97]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(97),
Q => Q(97)
);
\gpr1.dout_i_reg[98]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(98),
Q => Q(98)
);
\gpr1.dout_i_reg[99]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(99),
Q => Q(99)
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I1(0),
D => p_0_out(9),
Q => Q(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
O1 : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
O2 : out STD_LOGIC_VECTOR ( 4 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I2 : in STD_LOGIC;
I3 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
I4 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_rd_bin_cntr : entity is "rd_bin_cntr";
end fifo_async_103x32_rd_bin_cntr;
architecture STRUCTURE of fifo_async_103x32_rd_bin_cntr is
signal \^o2\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal n_0_ram_empty_fb_i_i_2 : STD_LOGIC;
signal n_0_ram_empty_fb_i_i_4 : STD_LOGIC;
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 4 downto 1 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[1]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gc0.count[4]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of ram_empty_fb_i_i_4 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \rd_pntr_gc[1]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \rd_pntr_gc[2]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \rd_pntr_gc[3]_i_1\ : label is "soft_lutpair10";
begin
O2(4 downto 0) <= \^o2\(4 downto 0);
Q(0) <= \^q\(0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => rd_pntr_plus1(1),
O => \plusOp__0\(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => rd_pntr_plus1(1),
I1 => \^q\(0),
I2 => rd_pntr_plus1(2),
O => \plusOp__0\(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => rd_pntr_plus1(2),
I1 => \^q\(0),
I2 => rd_pntr_plus1(1),
I3 => rd_pntr_plus1(3),
O => \plusOp__0\(3)
);
\gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => rd_pntr_plus1(3),
I1 => rd_pntr_plus1(1),
I2 => \^q\(0),
I3 => rd_pntr_plus1(2),
I4 => rd_pntr_plus1(4),
O => \plusOp__0\(4)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I4(0),
D => \^q\(0),
Q => \^o2\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I4(0),
D => rd_pntr_plus1(1),
Q => \^o2\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I4(0),
D => rd_pntr_plus1(2),
Q => \^o2\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I4(0),
D => rd_pntr_plus1(3),
Q => \^o2\(3)
);
\gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I4(0),
D => rd_pntr_plus1(4),
Q => \^o2\(4)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => \plusOp__0\(0),
PRE => I4(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I4(0),
D => \plusOp__0\(1),
Q => rd_pntr_plus1(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I4(0),
D => \plusOp__0\(2),
Q => rd_pntr_plus1(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I4(0),
D => \plusOp__0\(3),
Q => rd_pntr_plus1(3)
);
\gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => I4(0),
D => \plusOp__0\(4),
Q => rd_pntr_plus1(4)
);
ram_empty_fb_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF800880088008"
)
port map (
I0 => n_0_ram_empty_fb_i_i_2,
I1 => I2,
I2 => I1(3),
I3 => rd_pntr_plus1(4),
I4 => n_0_ram_empty_fb_i_i_4,
I5 => I3,
O => O1
);
ram_empty_fb_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => rd_pntr_plus1(2),
I1 => I1(1),
I2 => I1(0),
I3 => rd_pntr_plus1(1),
I4 => I1(2),
I5 => rd_pntr_plus1(3),
O => n_0_ram_empty_fb_i_i_2
);
ram_empty_fb_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^o2\(3),
I1 => I1(2),
I2 => \^o2\(4),
I3 => I1(3),
O => n_0_ram_empty_fb_i_i_4
);
\rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o2\(0),
I1 => \^o2\(1),
O => D(0)
);
\rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o2\(1),
I1 => \^o2\(2),
O => D(1)
);
\rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o2\(2),
I1 => \^o2\(3),
O => D(2)
);
\rd_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o2\(3),
I1 => \^o2\(4),
O => D(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_rd_fwft is
port (
empty : out STD_LOGIC;
O1 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
O2 : out STD_LOGIC_VECTOR ( 0 to 0 );
O3 : out STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
I1 : in STD_LOGIC_VECTOR ( 0 to 0 );
I2 : in STD_LOGIC_VECTOR ( 0 to 0 );
p_18_out : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_rd_fwft : entity is "rd_fwft";
end fifo_async_103x32_rd_fwft;
architecture STRUCTURE of fifo_async_103x32_rd_fwft is
signal curr_fwft_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal empty_fwft_fb : STD_LOGIC;
signal empty_fwft_i0 : STD_LOGIC;
signal \n_0_gpregsm1.curr_fwft_state_reg[1]\ : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of empty_fwft_fb_reg : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of empty_fwft_i_i_1 : label is "soft_lutpair8";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute SOFT_HLUTNM of \gc0.count_d1[4]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \goreg_dm.dout_i[102]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gpr1.dout_i[102]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[0]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gpregsm1.curr_fwft_state[1]_i_1\ : label is "soft_lutpair6";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
begin
empty_fwft_fb_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(0),
Q => empty_fwft_fb
);
empty_fwft_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F540"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => empty_fwft_fb,
O => empty_fwft_i0
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => empty_fwft_i0,
PRE => Q(0),
Q => empty
);
\gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => p_18_out,
O => O2(0)
);
\goreg_dm.dout_i[102]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => curr_fwft_state(0),
I1 => rd_en,
I2 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
O => E(0)
);
\gpr1.dout_i[102]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => p_18_out,
O => O3(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => curr_fwft_state(0),
I2 => rd_en,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
I1 => rd_en,
I2 => curr_fwft_state(0),
I3 => p_18_out,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => Q(0),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => Q(0),
D => next_fwft_state(1),
Q => \n_0_gpregsm1.curr_fwft_state_reg[1]\
);
ram_empty_fb_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0909000909090909"
)
port map (
I0 => I1(0),
I1 => I2(0),
I2 => p_18_out,
I3 => curr_fwft_state(0),
I4 => rd_en,
I5 => \n_0_gpregsm1.curr_fwft_state_reg[1]\,
O => O1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_rd_status_flags_as is
port (
p_18_out : out STD_LOGIC;
I1 : in STD_LOGIC;
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_rd_status_flags_as : entity is "rd_status_flags_as";
end fifo_async_103x32_rd_status_flags_as;
architecture STRUCTURE of fifo_async_103x32_rd_status_flags_as is
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
begin
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => I1,
PRE => Q(0),
Q => p_18_out
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_reset_blk_ramfifo is
port (
rst_d2 : out STD_LOGIC;
rst_full_gen_i : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
O1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
rd_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end fifo_async_103x32_reset_blk_ramfifo;
architecture STRUCTURE of fifo_async_103x32_reset_blk_ramfifo is
signal \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\ : STD_LOGIC;
signal \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\ : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_asreg_d1 : STD_LOGIC;
signal rd_rst_asreg_d2 : STD_LOGIC;
signal rst_d1 : STD_LOGIC;
signal \^rst_d2\ : STD_LOGIC;
signal rst_d3 : STD_LOGIC;
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_asreg_d1 : STD_LOGIC;
signal wr_rst_asreg_d2 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\ : label is "true";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\ : label is "true";
attribute ASYNC_REG of \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : label is std.standard.true;
attribute msgon of \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\ : label is "true";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
begin
rst_d2 <= \^rst_d2\;
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => rst,
D => rst_d3,
Q => rst_full_gen_i
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => rst,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1,
PRE => rst,
Q => \^rst_d2\
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \^rst_d2\,
PRE => rst,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rd_rst_asreg,
Q => rd_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
D => rd_rst_asreg_d1,
Q => rd_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
port map (
C => rd_clk,
CE => rd_rst_asreg_d1,
D => '0',
PRE => rst,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_rst_asreg,
I1 => rd_rst_asreg_d2,
O => \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\,
Q => Q(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\,
Q => Q(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\,
Q => Q(2)
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => wr_rst_asreg,
Q => wr_rst_asreg_d1,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
D => wr_rst_asreg_d1,
Q => wr_rst_asreg_d2,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
port map (
C => wr_clk,
CE => wr_rst_asreg_d1,
D => '0',
PRE => rst,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_rst_asreg,
I1 => wr_rst_asreg_d2,
O => \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\,
Q => O1(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => \n_0_ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1\,
Q => O1(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_synchronizer_ff is
port (
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
I5 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_synchronizer_ff : entity is "synchronizer_ff";
end fifo_async_103x32_synchronizer_ff;
architecture STRUCTURE of fifo_async_103x32_synchronizer_ff is
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[4]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I1(0),
Q => Q(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I1(1),
Q => Q(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I1(2),
Q => Q(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I1(3),
Q => Q(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I1(4),
Q => Q(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_synchronizer_ff_0 is
port (
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_clk : in STD_LOGIC;
I4 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_synchronizer_ff_0 : entity is "synchronizer_ff";
end fifo_async_103x32_synchronizer_ff_0;
architecture STRUCTURE of fifo_async_103x32_synchronizer_ff_0 is
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[4]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => I1(0),
Q => Q(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => I1(1),
Q => Q(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => I1(2),
Q => Q(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => I1(3),
Q => Q(3)
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => I1(4),
Q => Q(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_synchronizer_ff_1 is
port (
p_0_in : out STD_LOGIC_VECTOR ( 4 downto 0 );
D : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
I5 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_synchronizer_ff_1 : entity is "synchronizer_ff";
end fifo_async_103x32_synchronizer_ff_1;
architecture STRUCTURE of fifo_async_103x32_synchronizer_ff_1 is
signal \n_0_Q_reg_reg[0]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[1]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[2]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[3]\ : STD_LOGIC;
signal \^p_0_in\ : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \wr_pntr_bin[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_bin[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_bin[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wr_pntr_bin[3]_i_1\ : label is "soft_lutpair1";
begin
p_0_in(4 downto 0) <= \^p_0_in\(4 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => D(0),
Q => \n_0_Q_reg_reg[0]\
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => D(1),
Q => \n_0_Q_reg_reg[1]\
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => D(2),
Q => \n_0_Q_reg_reg[2]\
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => D(3),
Q => \n_0_Q_reg_reg[3]\
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => D(4),
Q => \^p_0_in\(4)
);
\wr_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \n_0_Q_reg_reg[2]\,
I1 => \n_0_Q_reg_reg[0]\,
I2 => \n_0_Q_reg_reg[1]\,
I3 => \^p_0_in\(4),
I4 => \n_0_Q_reg_reg[3]\,
O => \^p_0_in\(0)
);
\wr_pntr_bin[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \n_0_Q_reg_reg[2]\,
I1 => \n_0_Q_reg_reg[1]\,
I2 => \^p_0_in\(4),
I3 => \n_0_Q_reg_reg[3]\,
O => \^p_0_in\(1)
);
\wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \n_0_Q_reg_reg[3]\,
I1 => \n_0_Q_reg_reg[2]\,
I2 => \^p_0_in\(4),
O => \^p_0_in\(2)
);
\wr_pntr_bin[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_0_Q_reg_reg[3]\,
I1 => \^p_0_in\(4),
O => \^p_0_in\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_synchronizer_ff_2 is
port (
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
O1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_clk : in STD_LOGIC;
I4 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_synchronizer_ff_2 : entity is "synchronizer_ff";
end fifo_async_103x32_synchronizer_ff_2;
architecture STRUCTURE of fifo_async_103x32_synchronizer_ff_2 is
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \n_0_Q_reg_reg[0]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[1]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[2]\ : STD_LOGIC;
signal \n_0_Q_reg_reg[3]\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[4]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[4]\ : label is "true";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rd_pntr_bin[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rd_pntr_bin[1]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \rd_pntr_bin[2]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \rd_pntr_bin[3]_i_1\ : label is "soft_lutpair3";
begin
Q(0) <= \^q\(0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => D(0),
Q => \n_0_Q_reg_reg[0]\
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => D(1),
Q => \n_0_Q_reg_reg[1]\
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => D(2),
Q => \n_0_Q_reg_reg[2]\
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => D(3),
Q => \n_0_Q_reg_reg[3]\
);
\Q_reg_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => D(4),
Q => \^q\(0)
);
\rd_pntr_bin[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \n_0_Q_reg_reg[2]\,
I1 => \n_0_Q_reg_reg[0]\,
I2 => \n_0_Q_reg_reg[1]\,
I3 => \^q\(0),
I4 => \n_0_Q_reg_reg[3]\,
O => O1(0)
);
\rd_pntr_bin[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \n_0_Q_reg_reg[2]\,
I1 => \n_0_Q_reg_reg[1]\,
I2 => \^q\(0),
I3 => \n_0_Q_reg_reg[3]\,
O => O1(1)
);
\rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \n_0_Q_reg_reg[3]\,
I1 => \n_0_Q_reg_reg[2]\,
I2 => \^q\(0),
O => O1(2)
);
\rd_pntr_bin[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \n_0_Q_reg_reg[3]\,
I1 => \^q\(0),
O => O1(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_wr_bin_cntr is
port (
O1 : out STD_LOGIC;
O2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 2 downto 0 );
O4 : out STD_LOGIC_VECTOR ( 3 downto 0 );
O5 : out STD_LOGIC_VECTOR ( 4 downto 0 );
rst_full_gen_i : in STD_LOGIC;
I1 : in STD_LOGIC;
I2 : in STD_LOGIC;
O3 : in STD_LOGIC_VECTOR ( 4 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
I3 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_wr_bin_cntr : entity is "wr_bin_cntr";
end fifo_async_103x32_wr_bin_cntr;
architecture STRUCTURE of fifo_async_103x32_wr_bin_cntr is
signal \^o4\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal n_0_ram_full_i_i_2 : STD_LOGIC;
signal n_0_ram_full_i_i_5 : STD_LOGIC;
signal p_8_out : STD_LOGIC_VECTOR ( 4 to 4 );
signal \plusOp__1\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[0]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gic0.gc0.count[4]_i_1\ : label is "soft_lutpair13";
begin
O4(3 downto 0) <= \^o4\(3 downto 0);
Q(3 downto 0) <= \^q\(3 downto 0);
\gdiff.diff_pntr_pad[3]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(2),
I1 => O3(2),
O => S(2)
);
\gdiff.diff_pntr_pad[3]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(1),
I1 => O3(1),
O => S(1)
);
\gdiff.diff_pntr_pad[3]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(0),
I1 => O3(0),
O => S(0)
);
\gdiff.diff_pntr_pad[5]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => p_8_out(4),
I1 => O3(4),
O => O2(1)
);
\gdiff.diff_pntr_pad[5]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(3),
I1 => O3(3),
O => O2(0)
);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^o4\(0),
O => \plusOp__1\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o4\(0),
I1 => \^o4\(1),
O => \plusOp__1\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^o4\(0),
I1 => \^o4\(1),
I2 => \^o4\(2),
O => \plusOp__1\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => wr_pntr_plus2(3),
I1 => \^o4\(0),
I2 => \^o4\(1),
I3 => \^o4\(2),
O => \plusOp__1\(3)
);
\gic0.gc0.count[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^o4\(3),
I1 => \^o4\(2),
I2 => \^o4\(1),
I3 => \^o4\(0),
I4 => wr_pntr_plus2(3),
O => \plusOp__1\(4)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \^o4\(0),
PRE => I3(0),
Q => \^q\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \^o4\(1),
Q => \^q\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \^o4\(2),
Q => \^q\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => wr_pntr_plus2(3),
Q => \^q\(3)
);
\gic0.gc0.count_d1_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \^o4\(3),
Q => p_8_out(4)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \^q\(0),
Q => O5(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \^q\(1),
Q => O5(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \^q\(2),
Q => O5(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \^q\(3),
Q => O5(3)
);
\gic0.gc0.count_d2_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => p_8_out(4),
Q => O5(4)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \plusOp__1\(0),
Q => \^o4\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__1\(1),
PRE => I3(0),
Q => \^o4\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \plusOp__1\(2),
Q => \^o4\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \plusOp__1\(3),
Q => wr_pntr_plus2(3)
);
\gic0.gc0.count_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => I3(0),
D => \plusOp__1\(4),
Q => \^o4\(3)
);
ram_full_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"4445444444444445"
)
port map (
I0 => rst_full_gen_i,
I1 => n_0_ram_full_i_i_2,
I2 => I1,
I3 => I2,
I4 => wr_pntr_plus2(3),
I5 => O3(3),
O => O1
);
ram_full_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00009009"
)
port map (
I0 => \^q\(2),
I1 => O3(2),
I2 => \^q\(3),
I3 => O3(3),
I4 => n_0_ram_full_i_i_5,
O => n_0_ram_full_i_i_2
);
ram_full_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \^q\(1),
I1 => O3(1),
I2 => \^q\(0),
I3 => O3(0),
I4 => O3(4),
I5 => p_8_out(4),
O => n_0_ram_full_i_i_5
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_wr_pf_as is
port (
prog_full : out STD_LOGIC;
wr_clk : in STD_LOGIC;
rst_d2 : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC;
p_1_out : in STD_LOGIC;
I2 : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_pntr_plus1_pad : in STD_LOGIC_VECTOR ( 4 downto 0 );
S : in STD_LOGIC_VECTOR ( 2 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_wr_pf_as : entity is "wr_pf_as";
end fifo_async_103x32_wr_pf_as;
architecture STRUCTURE of fifo_async_103x32_wr_pf_as is
signal diff_pntr : STD_LOGIC_VECTOR ( 4 downto 1 );
signal \n_0_gdiff.diff_pntr_pad_reg[3]_i_1\ : STD_LOGIC;
signal \n_0_gpf1.prog_full_i_i_1\ : STD_LOGIC;
signal \n_0_gpf1.prog_full_i_i_2\ : STD_LOGIC;
signal \n_1_gdiff.diff_pntr_pad_reg[3]_i_1\ : STD_LOGIC;
signal \n_2_gdiff.diff_pntr_pad_reg[3]_i_1\ : STD_LOGIC;
signal \n_3_gdiff.diff_pntr_pad_reg[3]_i_1\ : STD_LOGIC;
signal \n_3_gdiff.diff_pntr_pad_reg[5]_i_1\ : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^prog_full\ : STD_LOGIC;
signal \NLW_gdiff.diff_pntr_pad_reg[5]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_gdiff.diff_pntr_pad_reg[5]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
begin
prog_full <= \^prog_full\;
\gdiff.diff_pntr_pad_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => plusOp(2),
Q => diff_pntr(1)
);
\gdiff.diff_pntr_pad_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => plusOp(3),
Q => diff_pntr(2)
);
\gdiff.diff_pntr_pad_reg[3]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \n_0_gdiff.diff_pntr_pad_reg[3]_i_1\,
CO(2) => \n_1_gdiff.diff_pntr_pad_reg[3]_i_1\,
CO(1) => \n_2_gdiff.diff_pntr_pad_reg[3]_i_1\,
CO(0) => \n_3_gdiff.diff_pntr_pad_reg[3]_i_1\,
CYINIT => '0',
DI(3 downto 0) => wr_pntr_plus1_pad(3 downto 0),
O(3 downto 0) => plusOp(3 downto 0),
S(3 downto 1) => S(2 downto 0),
S(0) => '0'
);
\gdiff.diff_pntr_pad_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => plusOp(4),
Q => diff_pntr(3)
);
\gdiff.diff_pntr_pad_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I2(0),
D => plusOp(5),
Q => diff_pntr(4)
);
\gdiff.diff_pntr_pad_reg[5]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \n_0_gdiff.diff_pntr_pad_reg[3]_i_1\,
CO(3 downto 1) => \NLW_gdiff.diff_pntr_pad_reg[5]_i_1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \n_3_gdiff.diff_pntr_pad_reg[5]_i_1\,
CYINIT => '0',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => wr_pntr_plus1_pad(4),
O(3 downto 2) => \NLW_gdiff.diff_pntr_pad_reg[5]_i_1_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => plusOp(5 downto 4),
S(3) => '0',
S(2) => '0',
S(1 downto 0) => I1(1 downto 0)
);
\gpf1.prog_full_i_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => \n_0_gpf1.prog_full_i_i_2\,
I1 => rst_full_gen_i,
I2 => p_1_out,
I3 => \^prog_full\,
O => \n_0_gpf1.prog_full_i_i_1\
);
\gpf1.prog_full_i_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"54444444"
)
port map (
I0 => rst_full_gen_i,
I1 => diff_pntr(4),
I2 => diff_pntr(3),
I3 => diff_pntr(1),
I4 => diff_pntr(2),
O => \n_0_gpf1.prog_full_i_i_2\
);
\gpf1.prog_full_i_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \n_0_gpf1.prog_full_i_i_1\,
PRE => rst_d2,
Q => \^prog_full\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_wr_status_flags_as is
port (
full : out STD_LOGIC;
p_1_out : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
O1 : out STD_LOGIC;
wr_pntr_plus1_pad : out STD_LOGIC_VECTOR ( 0 to 0 );
I1 : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst_d2 : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_wr_status_flags_as : entity is "wr_status_flags_as";
end fifo_async_103x32_wr_status_flags_as;
architecture STRUCTURE of fifo_async_103x32_wr_status_flags_as is
signal \^p_1_out\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
p_1_out <= \^p_1_out\;
\gdiff.diff_pntr_pad[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => \^p_1_out\,
O => wr_pntr_plus1_pad(0)
);
\gic0.gc0.count_d1[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => \^p_1_out\,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => I1,
PRE => rst_d2,
Q => \^p_1_out\
);
ram_full_i_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^p_1_out\,
I1 => wr_en,
O => O1
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => I1,
PRE => rst_d2,
Q => full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_clk_x_pntrs is
port (
O1 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
O2 : out STD_LOGIC;
O3 : out STD_LOGIC_VECTOR ( 4 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I2 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I3 : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_clk : in STD_LOGIC;
I4 : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
I5 : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_clk_x_pntrs : entity is "clk_x_pntrs";
end fifo_async_103x32_clk_x_pntrs;
architecture STRUCTURE of fifo_async_103x32_clk_x_pntrs is
signal \^o3\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \n_0_gsync_stage[1].rd_stg_inst\ : STD_LOGIC;
signal \n_0_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_0_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal n_0_ram_full_i_i_6 : STD_LOGIC;
signal \n_1_gsync_stage[1].rd_stg_inst\ : STD_LOGIC;
signal \n_1_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_1_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_2_gsync_stage[1].rd_stg_inst\ : STD_LOGIC;
signal \n_2_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_2_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_3_gsync_stage[1].rd_stg_inst\ : STD_LOGIC;
signal \n_3_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_3_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_4_gsync_stage[1].rd_stg_inst\ : STD_LOGIC;
signal \n_4_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_4_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_0_in3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 4 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \wr_pntr_gc[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \wr_pntr_gc[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \wr_pntr_gc[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \wr_pntr_gc[3]_i_1\ : label is "soft_lutpair5";
begin
O3(4 downto 0) <= \^o3\(4 downto 0);
Q(4 downto 0) <= \^q\(4 downto 0);
\gsync_stage[1].rd_stg_inst\: entity work.fifo_async_103x32_synchronizer_ff
port map (
I1(4 downto 0) => wr_pntr_gc(4 downto 0),
I5(0) => I5(0),
Q(4) => \n_0_gsync_stage[1].rd_stg_inst\,
Q(3) => \n_1_gsync_stage[1].rd_stg_inst\,
Q(2) => \n_2_gsync_stage[1].rd_stg_inst\,
Q(1) => \n_3_gsync_stage[1].rd_stg_inst\,
Q(0) => \n_4_gsync_stage[1].rd_stg_inst\,
rd_clk => rd_clk
);
\gsync_stage[1].wr_stg_inst\: entity work.fifo_async_103x32_synchronizer_ff_0
port map (
I1(4 downto 0) => rd_pntr_gc(4 downto 0),
I4(0) => I4(0),
Q(4) => \n_0_gsync_stage[1].wr_stg_inst\,
Q(3) => \n_1_gsync_stage[1].wr_stg_inst\,
Q(2) => \n_2_gsync_stage[1].wr_stg_inst\,
Q(1) => \n_3_gsync_stage[1].wr_stg_inst\,
Q(0) => \n_4_gsync_stage[1].wr_stg_inst\,
wr_clk => wr_clk
);
\gsync_stage[2].rd_stg_inst\: entity work.fifo_async_103x32_synchronizer_ff_1
port map (
D(4) => \n_0_gsync_stage[1].rd_stg_inst\,
D(3) => \n_1_gsync_stage[1].rd_stg_inst\,
D(2) => \n_2_gsync_stage[1].rd_stg_inst\,
D(1) => \n_3_gsync_stage[1].rd_stg_inst\,
D(0) => \n_4_gsync_stage[1].rd_stg_inst\,
I5(0) => I5(0),
p_0_in(4 downto 0) => p_0_in(4 downto 0),
rd_clk => rd_clk
);
\gsync_stage[2].wr_stg_inst\: entity work.fifo_async_103x32_synchronizer_ff_2
port map (
D(4) => \n_0_gsync_stage[1].wr_stg_inst\,
D(3) => \n_1_gsync_stage[1].wr_stg_inst\,
D(2) => \n_2_gsync_stage[1].wr_stg_inst\,
D(1) => \n_3_gsync_stage[1].wr_stg_inst\,
D(0) => \n_4_gsync_stage[1].wr_stg_inst\,
I4(0) => I4(0),
O1(3) => \n_1_gsync_stage[2].wr_stg_inst\,
O1(2) => \n_2_gsync_stage[2].wr_stg_inst\,
O1(1) => \n_3_gsync_stage[2].wr_stg_inst\,
O1(0) => \n_4_gsync_stage[2].wr_stg_inst\,
Q(0) => \n_0_gsync_stage[2].wr_stg_inst\,
wr_clk => wr_clk
);
ram_empty_fb_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(2),
I1 => I1(2),
I2 => \^q\(1),
I3 => I1(1),
I4 => I1(0),
I5 => \^q\(0),
O => O1
);
ram_full_i_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF6FF6"
)
port map (
I0 => I2(0),
I1 => \^o3\(0),
I2 => I2(1),
I3 => \^o3\(1),
I4 => n_0_ram_full_i_i_6,
O => O2
);
ram_full_i_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => \^o3\(2),
I1 => I2(2),
I2 => \^o3\(4),
I3 => I2(3),
O => n_0_ram_full_i_i_6
);
\rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => \n_4_gsync_stage[2].wr_stg_inst\,
Q => \^o3\(0)
);
\rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => \n_3_gsync_stage[2].wr_stg_inst\,
Q => \^o3\(1)
);
\rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => \n_2_gsync_stage[2].wr_stg_inst\,
Q => \^o3\(2)
);
\rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => \n_1_gsync_stage[2].wr_stg_inst\,
Q => \^o3\(3)
);
\rd_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => \n_0_gsync_stage[2].wr_stg_inst\,
Q => \^o3\(4)
);
\rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => D(0),
Q => rd_pntr_gc(0)
);
\rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => D(1),
Q => rd_pntr_gc(1)
);
\rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => D(2),
Q => rd_pntr_gc(2)
);
\rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => D(3),
Q => rd_pntr_gc(3)
);
\rd_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => I1(3),
Q => rd_pntr_gc(4)
);
\wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => p_0_in(0),
Q => \^q\(0)
);
\wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => p_0_in(1),
Q => \^q\(1)
);
\wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => p_0_in(2),
Q => \^q\(2)
);
\wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => p_0_in(3),
Q => \^q\(3)
);
\wr_pntr_bin_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => I5(0),
D => p_0_in(4),
Q => \^q\(4)
);
\wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I3(0),
I1 => I3(1),
O => p_0_in3_out(0)
);
\wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I3(1),
I1 => I3(2),
O => p_0_in3_out(1)
);
\wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I3(2),
I1 => I3(3),
O => p_0_in3_out(2)
);
\wr_pntr_gc[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I3(3),
I1 => I3(4),
O => p_0_in3_out(3)
);
\wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => p_0_in3_out(0),
Q => wr_pntr_gc(0)
);
\wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => p_0_in3_out(1),
Q => wr_pntr_gc(1)
);
\wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => p_0_in3_out(2),
Q => wr_pntr_gc(2)
);
\wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => p_0_in3_out(3),
Q => wr_pntr_gc(3)
);
\wr_pntr_gc_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => I4(0),
D => I3(4),
Q => wr_pntr_gc(4)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_memory is
port (
dout : out STD_LOGIC_VECTOR ( 102 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
I1 : in STD_LOGIC_VECTOR ( 0 to 0 );
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
O2 : in STD_LOGIC_VECTOR ( 4 downto 0 );
O1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
I2 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_memory : entity is "memory";
end fifo_async_103x32_memory;
architecture STRUCTURE of fifo_async_103x32_memory is
signal p_0_out : STD_LOGIC_VECTOR ( 102 downto 0 );
begin
\gdm.dm\: entity work.fifo_async_103x32_dmem
port map (
E(0) => E(0),
I1(0) => Q(0),
I2(0) => I1(0),
O1(4 downto 0) => O1(4 downto 0),
O2(4 downto 0) => O2(4 downto 0),
Q(102 downto 0) => p_0_out(102 downto 0),
din(102 downto 0) => din(102 downto 0),
rd_clk => rd_clk,
wr_clk => wr_clk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(0),
Q => dout(0)
);
\goreg_dm.dout_i_reg[100]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(100),
Q => dout(100)
);
\goreg_dm.dout_i_reg[101]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(101),
Q => dout(101)
);
\goreg_dm.dout_i_reg[102]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(102),
Q => dout(102)
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(10),
Q => dout(10)
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(11),
Q => dout(11)
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(12),
Q => dout(12)
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(13),
Q => dout(13)
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(14),
Q => dout(14)
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(15),
Q => dout(15)
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(16),
Q => dout(16)
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(17),
Q => dout(17)
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(18),
Q => dout(18)
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(19),
Q => dout(19)
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(1),
Q => dout(1)
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(20),
Q => dout(20)
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(21),
Q => dout(21)
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(22),
Q => dout(22)
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(23),
Q => dout(23)
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(24),
Q => dout(24)
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(25),
Q => dout(25)
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(26),
Q => dout(26)
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(27),
Q => dout(27)
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(28),
Q => dout(28)
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(29),
Q => dout(29)
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(2),
Q => dout(2)
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(30),
Q => dout(30)
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(31),
Q => dout(31)
);
\goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(32),
Q => dout(32)
);
\goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(33),
Q => dout(33)
);
\goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(34),
Q => dout(34)
);
\goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(35),
Q => dout(35)
);
\goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(36),
Q => dout(36)
);
\goreg_dm.dout_i_reg[37]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(37),
Q => dout(37)
);
\goreg_dm.dout_i_reg[38]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(38),
Q => dout(38)
);
\goreg_dm.dout_i_reg[39]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(39),
Q => dout(39)
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(3),
Q => dout(3)
);
\goreg_dm.dout_i_reg[40]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(40),
Q => dout(40)
);
\goreg_dm.dout_i_reg[41]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(41),
Q => dout(41)
);
\goreg_dm.dout_i_reg[42]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(42),
Q => dout(42)
);
\goreg_dm.dout_i_reg[43]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(43),
Q => dout(43)
);
\goreg_dm.dout_i_reg[44]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(44),
Q => dout(44)
);
\goreg_dm.dout_i_reg[45]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(45),
Q => dout(45)
);
\goreg_dm.dout_i_reg[46]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(46),
Q => dout(46)
);
\goreg_dm.dout_i_reg[47]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(47),
Q => dout(47)
);
\goreg_dm.dout_i_reg[48]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(48),
Q => dout(48)
);
\goreg_dm.dout_i_reg[49]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(49),
Q => dout(49)
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(4),
Q => dout(4)
);
\goreg_dm.dout_i_reg[50]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(50),
Q => dout(50)
);
\goreg_dm.dout_i_reg[51]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(51),
Q => dout(51)
);
\goreg_dm.dout_i_reg[52]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(52),
Q => dout(52)
);
\goreg_dm.dout_i_reg[53]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(53),
Q => dout(53)
);
\goreg_dm.dout_i_reg[54]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(54),
Q => dout(54)
);
\goreg_dm.dout_i_reg[55]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(55),
Q => dout(55)
);
\goreg_dm.dout_i_reg[56]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(56),
Q => dout(56)
);
\goreg_dm.dout_i_reg[57]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(57),
Q => dout(57)
);
\goreg_dm.dout_i_reg[58]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(58),
Q => dout(58)
);
\goreg_dm.dout_i_reg[59]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(59),
Q => dout(59)
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(5),
Q => dout(5)
);
\goreg_dm.dout_i_reg[60]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(60),
Q => dout(60)
);
\goreg_dm.dout_i_reg[61]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(61),
Q => dout(61)
);
\goreg_dm.dout_i_reg[62]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(62),
Q => dout(62)
);
\goreg_dm.dout_i_reg[63]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(63),
Q => dout(63)
);
\goreg_dm.dout_i_reg[64]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(64),
Q => dout(64)
);
\goreg_dm.dout_i_reg[65]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(65),
Q => dout(65)
);
\goreg_dm.dout_i_reg[66]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(66),
Q => dout(66)
);
\goreg_dm.dout_i_reg[67]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(67),
Q => dout(67)
);
\goreg_dm.dout_i_reg[68]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(68),
Q => dout(68)
);
\goreg_dm.dout_i_reg[69]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(69),
Q => dout(69)
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(6),
Q => dout(6)
);
\goreg_dm.dout_i_reg[70]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(70),
Q => dout(70)
);
\goreg_dm.dout_i_reg[71]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(71),
Q => dout(71)
);
\goreg_dm.dout_i_reg[72]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(72),
Q => dout(72)
);
\goreg_dm.dout_i_reg[73]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(73),
Q => dout(73)
);
\goreg_dm.dout_i_reg[74]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(74),
Q => dout(74)
);
\goreg_dm.dout_i_reg[75]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(75),
Q => dout(75)
);
\goreg_dm.dout_i_reg[76]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(76),
Q => dout(76)
);
\goreg_dm.dout_i_reg[77]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(77),
Q => dout(77)
);
\goreg_dm.dout_i_reg[78]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(78),
Q => dout(78)
);
\goreg_dm.dout_i_reg[79]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(79),
Q => dout(79)
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(7),
Q => dout(7)
);
\goreg_dm.dout_i_reg[80]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(80),
Q => dout(80)
);
\goreg_dm.dout_i_reg[81]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(81),
Q => dout(81)
);
\goreg_dm.dout_i_reg[82]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(82),
Q => dout(82)
);
\goreg_dm.dout_i_reg[83]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(83),
Q => dout(83)
);
\goreg_dm.dout_i_reg[84]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(84),
Q => dout(84)
);
\goreg_dm.dout_i_reg[85]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(85),
Q => dout(85)
);
\goreg_dm.dout_i_reg[86]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(86),
Q => dout(86)
);
\goreg_dm.dout_i_reg[87]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(87),
Q => dout(87)
);
\goreg_dm.dout_i_reg[88]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(88),
Q => dout(88)
);
\goreg_dm.dout_i_reg[89]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(89),
Q => dout(89)
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(8),
Q => dout(8)
);
\goreg_dm.dout_i_reg[90]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(90),
Q => dout(90)
);
\goreg_dm.dout_i_reg[91]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(91),
Q => dout(91)
);
\goreg_dm.dout_i_reg[92]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(92),
Q => dout(92)
);
\goreg_dm.dout_i_reg[93]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(93),
Q => dout(93)
);
\goreg_dm.dout_i_reg[94]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(94),
Q => dout(94)
);
\goreg_dm.dout_i_reg[95]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(95),
Q => dout(95)
);
\goreg_dm.dout_i_reg[96]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(96),
Q => dout(96)
);
\goreg_dm.dout_i_reg[97]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(97),
Q => dout(97)
);
\goreg_dm.dout_i_reg[98]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(98),
Q => dout(98)
);
\goreg_dm.dout_i_reg[99]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(99),
Q => dout(99)
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => I2(0),
CLR => Q(0),
D => p_0_out(9),
Q => dout(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_rd_logic is
port (
empty : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
O1 : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
O2 : out STD_LOGIC_VECTOR ( 4 downto 0 );
rd_clk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
I1 : in STD_LOGIC_VECTOR ( 4 downto 0 );
rd_en : in STD_LOGIC;
I2 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_rd_logic : entity is "rd_logic";
end fifo_async_103x32_rd_logic;
architecture STRUCTURE of fifo_async_103x32_rd_logic is
signal \n_1_gr1.rfwft\ : STD_LOGIC;
signal n_1_rpntr : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 0 to 0 );
begin
\gr1.rfwft\: entity work.fifo_async_103x32_rd_fwft
port map (
E(0) => E(0),
I1(0) => rd_pntr_plus1(0),
I2(0) => I1(0),
O1 => \n_1_gr1.rfwft\,
O2(0) => p_14_out,
O3(0) => O1(0),
Q(0) => Q(0),
empty => empty,
p_18_out => p_18_out,
rd_clk => rd_clk,
rd_en => rd_en
);
\gras.rsts\: entity work.fifo_async_103x32_rd_status_flags_as
port map (
I1 => n_1_rpntr,
Q(0) => Q(0),
p_18_out => p_18_out,
rd_clk => rd_clk
);
rpntr: entity work.fifo_async_103x32_rd_bin_cntr
port map (
D(3 downto 0) => D(3 downto 0),
E(0) => p_14_out,
I1(3 downto 0) => I1(4 downto 1),
I2 => \n_1_gr1.rfwft\,
I3 => I2,
I4(0) => Q(0),
O1 => n_1_rpntr,
O2(4 downto 0) => O2(4 downto 0),
Q(0) => rd_pntr_plus1(0),
rd_clk => rd_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_wr_logic is
port (
full : out STD_LOGIC;
prog_full : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
O1 : out STD_LOGIC_VECTOR ( 4 downto 0 );
wr_clk : in STD_LOGIC;
rst_d2 : in STD_LOGIC;
rst_full_gen_i : in STD_LOGIC;
I1 : in STD_LOGIC;
O3 : in STD_LOGIC_VECTOR ( 4 downto 0 );
wr_en : in STD_LOGIC;
I2 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_wr_logic : entity is "wr_logic";
end fifo_async_103x32_wr_logic;
architecture STRUCTURE of fifo_async_103x32_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal n_0_wpntr : STD_LOGIC;
signal n_1_wpntr : STD_LOGIC;
signal n_2_wpntr : STD_LOGIC;
signal \n_3_gwas.wsts\ : STD_LOGIC;
signal \n_4_gwas.wsts\ : STD_LOGIC;
signal n_7_wpntr : STD_LOGIC;
signal n_8_wpntr : STD_LOGIC;
signal n_9_wpntr : STD_LOGIC;
signal p_1_out : STD_LOGIC;
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
E(0) <= \^e\(0);
\gwas.gpf.wrpf\: entity work.fifo_async_103x32_wr_pf_as
port map (
I1(1) => n_1_wpntr,
I1(0) => n_2_wpntr,
I2(0) => I2(0),
S(2) => n_7_wpntr,
S(1) => n_8_wpntr,
S(0) => n_9_wpntr,
p_1_out => p_1_out,
prog_full => prog_full,
rst_d2 => rst_d2,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk,
wr_pntr_plus1_pad(4 downto 1) => p_8_out(3 downto 0),
wr_pntr_plus1_pad(0) => \n_4_gwas.wsts\
);
\gwas.wsts\: entity work.fifo_async_103x32_wr_status_flags_as
port map (
E(0) => \^e\(0),
I1 => n_0_wpntr,
O1 => \n_3_gwas.wsts\,
full => full,
p_1_out => p_1_out,
rst_d2 => rst_d2,
wr_clk => wr_clk,
wr_en => wr_en,
wr_pntr_plus1_pad(0) => \n_4_gwas.wsts\
);
wpntr: entity work.fifo_async_103x32_wr_bin_cntr
port map (
E(0) => \^e\(0),
I1 => \n_3_gwas.wsts\,
I2 => I1,
I3(0) => I2(0),
O1 => n_0_wpntr,
O2(1) => n_1_wpntr,
O2(0) => n_2_wpntr,
O3(4 downto 0) => O3(4 downto 0),
O4(3 downto 0) => Q(3 downto 0),
O5(4 downto 0) => O1(4 downto 0),
Q(3 downto 0) => p_8_out(3 downto 0),
S(2) => n_7_wpntr,
S(1) => n_8_wpntr,
S(0) => n_9_wpntr,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 102 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
prog_full : out STD_LOGIC;
rd_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end fifo_async_103x32_fifo_generator_ramfifo;
architecture STRUCTURE of fifo_async_103x32_fifo_generator_ramfifo is
signal RD_RST : STD_LOGIC;
signal \^rst\ : STD_LOGIC;
signal WR_RST : STD_LOGIC;
signal \n_0_gntv_or_sync_fifo.gcx.clkx\ : STD_LOGIC;
signal n_2_rstblk : STD_LOGIC;
signal \n_3_gntv_or_sync_fifo.gl0.rd\ : STD_LOGIC;
signal \n_4_gntv_or_sync_fifo.gl0.rd\ : STD_LOGIC;
signal \n_5_gntv_or_sync_fifo.gl0.rd\ : STD_LOGIC;
signal \n_6_gntv_or_sync_fifo.gcx.clkx\ : STD_LOGIC;
signal \n_6_gntv_or_sync_fifo.gl0.rd\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_15_out : STD_LOGIC;
signal p_1_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_20_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_3_out : STD_LOGIC;
signal p_9_out : STD_LOGIC_VECTOR ( 4 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_rst_i : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_d2 : STD_LOGIC;
signal rst_full_gen_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 4 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.fifo_async_103x32_clk_x_pntrs
port map (
D(3) => \n_3_gntv_or_sync_fifo.gl0.rd\,
D(2) => \n_4_gntv_or_sync_fifo.gl0.rd\,
D(1) => \n_5_gntv_or_sync_fifo.gl0.rd\,
D(0) => \n_6_gntv_or_sync_fifo.gl0.rd\,
I1(3) => p_20_out(4),
I1(2 downto 0) => p_20_out(2 downto 0),
I2(3) => wr_pntr_plus2(4),
I2(2 downto 0) => wr_pntr_plus2(2 downto 0),
I3(4 downto 0) => p_9_out(4 downto 0),
I4(0) => \^rst\,
I5(0) => RD_RST,
O1 => \n_0_gntv_or_sync_fifo.gcx.clkx\,
O2 => \n_6_gntv_or_sync_fifo.gcx.clkx\,
O3(4 downto 0) => p_0_out(4 downto 0),
Q(4 downto 0) => p_1_out(4 downto 0),
rd_clk => rd_clk,
wr_clk => wr_clk
);
\gntv_or_sync_fifo.gl0.rd\: entity work.fifo_async_103x32_rd_logic
port map (
D(3) => \n_3_gntv_or_sync_fifo.gl0.rd\,
D(2) => \n_4_gntv_or_sync_fifo.gl0.rd\,
D(1) => \n_5_gntv_or_sync_fifo.gl0.rd\,
D(0) => \n_6_gntv_or_sync_fifo.gl0.rd\,
E(0) => p_15_out,
I1(4 downto 0) => p_1_out(4 downto 0),
I2 => \n_0_gntv_or_sync_fifo.gcx.clkx\,
O1(0) => ram_rd_en_i,
O2(4 downto 0) => p_20_out(4 downto 0),
Q(0) => n_2_rstblk,
empty => empty,
rd_clk => rd_clk,
rd_en => rd_en
);
\gntv_or_sync_fifo.gl0.wr\: entity work.fifo_async_103x32_wr_logic
port map (
E(0) => p_3_out,
I1 => \n_6_gntv_or_sync_fifo.gcx.clkx\,
I2(0) => WR_RST,
O1(4 downto 0) => p_9_out(4 downto 0),
O3(4 downto 0) => p_0_out(4 downto 0),
Q(3) => wr_pntr_plus2(4),
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
full => full,
prog_full => prog_full,
rst_d2 => rst_d2,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk,
wr_en => wr_en
);
\gntv_or_sync_fifo.mem\: entity work.fifo_async_103x32_memory
port map (
E(0) => ram_rd_en_i,
I1(0) => p_3_out,
I2(0) => p_15_out,
O1(4 downto 0) => p_9_out(4 downto 0),
O2(4 downto 0) => p_20_out(4 downto 0),
Q(0) => rd_rst_i(0),
din(102 downto 0) => din(102 downto 0),
dout(102 downto 0) => dout(102 downto 0),
rd_clk => rd_clk,
wr_clk => wr_clk
);
rstblk: entity work.fifo_async_103x32_reset_blk_ramfifo
port map (
O1(1) => WR_RST,
O1(0) => \^rst\,
Q(2) => n_2_rstblk,
Q(1) => RD_RST,
Q(0) => rd_rst_i(0),
rd_clk => rd_clk,
rst => rst,
rst_d2 => rst_d2,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 102 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
prog_full : out STD_LOGIC;
rd_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_fifo_generator_top : entity is "fifo_generator_top";
end fifo_async_103x32_fifo_generator_top;
architecture STRUCTURE of fifo_async_103x32_fifo_generator_top is
begin
\grf.rf\: entity work.fifo_async_103x32_fifo_generator_ramfifo
port map (
din(102 downto 0) => din(102 downto 0),
dout(102 downto 0) => dout(102 downto 0),
empty => empty,
full => full,
prog_full => prog_full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32_fifo_generator_v12_0_synth is
port (
dout : out STD_LOGIC_VECTOR ( 102 downto 0 );
empty : out STD_LOGIC;
full : out STD_LOGIC;
prog_full : out STD_LOGIC;
rd_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_async_103x32_fifo_generator_v12_0_synth : entity is "fifo_generator_v12_0_synth";
end fifo_async_103x32_fifo_generator_v12_0_synth;
architecture STRUCTURE of fifo_async_103x32_fifo_generator_v12_0_synth is
begin
\gconvfifo.rf\: entity work.fifo_async_103x32_fifo_generator_top
port map (
din(102 downto 0) => din(102 downto 0),
dout(102 downto 0) => dout(102 downto 0),
empty => empty,
full => full,
prog_full => prog_full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 4 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 102 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is "fifo_generator_v12_0";
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 5;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 103;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 103;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is "BlankString";
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is "512x72";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 15;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 5;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 5;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 5;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 5;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 8;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is "1kx36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is "1kx18";
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ : entity is 0;
end \fifo_async_103x32_fifo_generator_v12_0__parameterized0\;
architecture STRUCTURE of \fifo_async_103x32_fifo_generator_v12_0__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.fifo_async_103x32_fifo_generator_v12_0_synth
port map (
din(102 downto 0) => din(102 downto 0),
dout(102 downto 0) => dout(102 downto 0),
empty => empty,
full => full,
prog_full => prog_full,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_async_103x32 is
port (
rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_clk : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 102 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 102 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
prog_full : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of fifo_async_103x32 : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of fifo_async_103x32 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of fifo_async_103x32 : entity is "fifo_generator_v12_0,Vivado 2014.3.1";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of fifo_async_103x32 : entity is "fifo_async_103x32,fifo_generator_v12_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of fifo_async_103x32 : entity is "fifo_async_103x32,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.3.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=2,x_ipLanguage=VERILOG,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=5,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=103,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=103,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=2,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=512x72,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=16,C_PROG_FULL_THRESH_NEGATE_VAL=15,C_PROG_FULL_TYPE=1,C_RD_DATA_COUNT_WIDTH=5,C_RD_DEPTH=32,C_RD_FREQ=1,C_RD_PNTR_WIDTH=5,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=5,C_WR_DEPTH=32,C_WR_FREQ=1,C_WR_PNTR_WIDTH=5,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
end fifo_async_103x32;
architecture STRUCTURE of fifo_async_103x32 is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_valid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 5;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 103;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 103;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 1;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 1;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 1;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 2;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 0;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 1;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x72";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 4;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 5;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 16;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 15;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 1;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 5;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 32;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 5;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 5;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 32;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 5;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.\fifo_async_103x32_fifo_generator_v12_0__parameterized0\
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3) => '0',
axi_ar_prog_empty_thresh(2) => '0',
axi_ar_prog_empty_thresh(1) => '0',
axi_ar_prog_empty_thresh(0) => '0',
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3) => '0',
axi_ar_prog_full_thresh(2) => '0',
axi_ar_prog_full_thresh(1) => '0',
axi_ar_prog_full_thresh(0) => '0',
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3) => '0',
axi_aw_prog_empty_thresh(2) => '0',
axi_aw_prog_empty_thresh(1) => '0',
axi_aw_prog_empty_thresh(0) => '0',
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3) => '0',
axi_aw_prog_full_thresh(2) => '0',
axi_aw_prog_full_thresh(1) => '0',
axi_aw_prog_full_thresh(0) => '0',
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3) => '0',
axi_b_prog_empty_thresh(2) => '0',
axi_b_prog_empty_thresh(1) => '0',
axi_b_prog_empty_thresh(0) => '0',
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3) => '0',
axi_b_prog_full_thresh(2) => '0',
axi_b_prog_full_thresh(1) => '0',
axi_b_prog_full_thresh(0) => '0',
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9) => '0',
axi_r_prog_empty_thresh(8) => '0',
axi_r_prog_empty_thresh(7) => '0',
axi_r_prog_empty_thresh(6) => '0',
axi_r_prog_empty_thresh(5) => '0',
axi_r_prog_empty_thresh(4) => '0',
axi_r_prog_empty_thresh(3) => '0',
axi_r_prog_empty_thresh(2) => '0',
axi_r_prog_empty_thresh(1) => '0',
axi_r_prog_empty_thresh(0) => '0',
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9) => '0',
axi_r_prog_full_thresh(8) => '0',
axi_r_prog_full_thresh(7) => '0',
axi_r_prog_full_thresh(6) => '0',
axi_r_prog_full_thresh(5) => '0',
axi_r_prog_full_thresh(4) => '0',
axi_r_prog_full_thresh(3) => '0',
axi_r_prog_full_thresh(2) => '0',
axi_r_prog_full_thresh(1) => '0',
axi_r_prog_full_thresh(0) => '0',
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9) => '0',
axi_w_prog_empty_thresh(8) => '0',
axi_w_prog_empty_thresh(7) => '0',
axi_w_prog_empty_thresh(6) => '0',
axi_w_prog_empty_thresh(5) => '0',
axi_w_prog_empty_thresh(4) => '0',
axi_w_prog_empty_thresh(3) => '0',
axi_w_prog_empty_thresh(2) => '0',
axi_w_prog_empty_thresh(1) => '0',
axi_w_prog_empty_thresh(0) => '0',
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9) => '0',
axi_w_prog_full_thresh(8) => '0',
axi_w_prog_full_thresh(7) => '0',
axi_w_prog_full_thresh(6) => '0',
axi_w_prog_full_thresh(5) => '0',
axi_w_prog_full_thresh(4) => '0',
axi_w_prog_full_thresh(3) => '0',
axi_w_prog_full_thresh(2) => '0',
axi_w_prog_full_thresh(1) => '0',
axi_w_prog_full_thresh(0) => '0',
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9) => '0',
axis_prog_empty_thresh(8) => '0',
axis_prog_empty_thresh(7) => '0',
axis_prog_empty_thresh(6) => '0',
axis_prog_empty_thresh(5) => '0',
axis_prog_empty_thresh(4) => '0',
axis_prog_empty_thresh(3) => '0',
axis_prog_empty_thresh(2) => '0',
axis_prog_empty_thresh(1) => '0',
axis_prog_empty_thresh(0) => '0',
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9) => '0',
axis_prog_full_thresh(8) => '0',
axis_prog_full_thresh(7) => '0',
axis_prog_full_thresh(6) => '0',
axis_prog_full_thresh(5) => '0',
axis_prog_full_thresh(4) => '0',
axis_prog_full_thresh(3) => '0',
axis_prog_full_thresh(2) => '0',
axis_prog_full_thresh(1) => '0',
axis_prog_full_thresh(0) => '0',
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(4 downto 0) => NLW_U0_data_count_UNCONNECTED(4 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(102 downto 0) => din(102 downto 0),
dout(102 downto 0) => dout(102 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1) => '0',
m_axi_bresp(0) => '0',
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63) => '0',
m_axi_rdata(62) => '0',
m_axi_rdata(61) => '0',
m_axi_rdata(60) => '0',
m_axi_rdata(59) => '0',
m_axi_rdata(58) => '0',
m_axi_rdata(57) => '0',
m_axi_rdata(56) => '0',
m_axi_rdata(55) => '0',
m_axi_rdata(54) => '0',
m_axi_rdata(53) => '0',
m_axi_rdata(52) => '0',
m_axi_rdata(51) => '0',
m_axi_rdata(50) => '0',
m_axi_rdata(49) => '0',
m_axi_rdata(48) => '0',
m_axi_rdata(47) => '0',
m_axi_rdata(46) => '0',
m_axi_rdata(45) => '0',
m_axi_rdata(44) => '0',
m_axi_rdata(43) => '0',
m_axi_rdata(42) => '0',
m_axi_rdata(41) => '0',
m_axi_rdata(40) => '0',
m_axi_rdata(39) => '0',
m_axi_rdata(38) => '0',
m_axi_rdata(37) => '0',
m_axi_rdata(36) => '0',
m_axi_rdata(35) => '0',
m_axi_rdata(34) => '0',
m_axi_rdata(33) => '0',
m_axi_rdata(32) => '0',
m_axi_rdata(31) => '0',
m_axi_rdata(30) => '0',
m_axi_rdata(29) => '0',
m_axi_rdata(28) => '0',
m_axi_rdata(27) => '0',
m_axi_rdata(26) => '0',
m_axi_rdata(25) => '0',
m_axi_rdata(24) => '0',
m_axi_rdata(23) => '0',
m_axi_rdata(22) => '0',
m_axi_rdata(21) => '0',
m_axi_rdata(20) => '0',
m_axi_rdata(19) => '0',
m_axi_rdata(18) => '0',
m_axi_rdata(17) => '0',
m_axi_rdata(16) => '0',
m_axi_rdata(15) => '0',
m_axi_rdata(14) => '0',
m_axi_rdata(13) => '0',
m_axi_rdata(12) => '0',
m_axi_rdata(11) => '0',
m_axi_rdata(10) => '0',
m_axi_rdata(9) => '0',
m_axi_rdata(8) => '0',
m_axi_rdata(7) => '0',
m_axi_rdata(6) => '0',
m_axi_rdata(5) => '0',
m_axi_rdata(4) => '0',
m_axi_rdata(3) => '0',
m_axi_rdata(2) => '0',
m_axi_rdata(1) => '0',
m_axi_rdata(0) => '0',
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1) => '0',
m_axi_rresp(0) => '0',
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(7 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(7 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(0) => NLW_U0_m_axis_tkeep_UNCONNECTED(0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(0) => NLW_U0_m_axis_tstrb_UNCONNECTED(0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(4) => '0',
prog_empty_thresh(3) => '0',
prog_empty_thresh(2) => '0',
prog_empty_thresh(1) => '0',
prog_empty_thresh(0) => '0',
prog_empty_thresh_assert(4) => '0',
prog_empty_thresh_assert(3) => '0',
prog_empty_thresh_assert(2) => '0',
prog_empty_thresh_assert(1) => '0',
prog_empty_thresh_assert(0) => '0',
prog_empty_thresh_negate(4) => '0',
prog_empty_thresh_negate(3) => '0',
prog_empty_thresh_negate(2) => '0',
prog_empty_thresh_negate(1) => '0',
prog_empty_thresh_negate(0) => '0',
prog_full => prog_full,
prog_full_thresh(4) => '0',
prog_full_thresh(3) => '0',
prog_full_thresh(2) => '0',
prog_full_thresh(1) => '0',
prog_full_thresh(0) => '0',
prog_full_thresh_assert(4) => '0',
prog_full_thresh_assert(3) => '0',
prog_full_thresh_assert(2) => '0',
prog_full_thresh_assert(1) => '0',
prog_full_thresh_assert(0) => '0',
prog_full_thresh_negate(4) => '0',
prog_full_thresh_negate(3) => '0',
prog_full_thresh_negate(2) => '0',
prog_full_thresh_negate(1) => '0',
prog_full_thresh_negate(0) => '0',
rd_clk => rd_clk,
rd_data_count(4 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(4 downto 0),
rd_en => rd_en,
rd_rst => '0',
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => rst,
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arcache(3) => '0',
s_axi_arcache(2) => '0',
s_axi_arcache(1) => '0',
s_axi_arcache(0) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arlock(0) => '0',
s_axi_arprot(2) => '0',
s_axi_arprot(1) => '0',
s_axi_arprot(0) => '0',
s_axi_arqos(3) => '0',
s_axi_arqos(2) => '0',
s_axi_arqos(1) => '0',
s_axi_arqos(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3) => '0',
s_axi_arregion(2) => '0',
s_axi_arregion(1) => '0',
s_axi_arregion(0) => '0',
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awcache(3) => '0',
s_axi_awcache(2) => '0',
s_axi_awcache(1) => '0',
s_axi_awcache(0) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awlock(0) => '0',
s_axi_awprot(2) => '0',
s_axi_awprot(1) => '0',
s_axi_awprot(0) => '0',
s_axi_awqos(3) => '0',
s_axi_awqos(2) => '0',
s_axi_awqos(1) => '0',
s_axi_awqos(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3) => '0',
s_axi_awregion(2) => '0',
s_axi_awregion(1) => '0',
s_axi_awregion(0) => '0',
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63) => '0',
s_axi_wdata(62) => '0',
s_axi_wdata(61) => '0',
s_axi_wdata(60) => '0',
s_axi_wdata(59) => '0',
s_axi_wdata(58) => '0',
s_axi_wdata(57) => '0',
s_axi_wdata(56) => '0',
s_axi_wdata(55) => '0',
s_axi_wdata(54) => '0',
s_axi_wdata(53) => '0',
s_axi_wdata(52) => '0',
s_axi_wdata(51) => '0',
s_axi_wdata(50) => '0',
s_axi_wdata(49) => '0',
s_axi_wdata(48) => '0',
s_axi_wdata(47) => '0',
s_axi_wdata(46) => '0',
s_axi_wdata(45) => '0',
s_axi_wdata(44) => '0',
s_axi_wdata(43) => '0',
s_axi_wdata(42) => '0',
s_axi_wdata(41) => '0',
s_axi_wdata(40) => '0',
s_axi_wdata(39) => '0',
s_axi_wdata(38) => '0',
s_axi_wdata(37) => '0',
s_axi_wdata(36) => '0',
s_axi_wdata(35) => '0',
s_axi_wdata(34) => '0',
s_axi_wdata(33) => '0',
s_axi_wdata(32) => '0',
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7) => '0',
s_axi_wstrb(6) => '0',
s_axi_wstrb(5) => '0',
s_axi_wstrb(4) => '0',
s_axi_wstrb(3) => '0',
s_axi_wstrb(2) => '0',
s_axi_wstrb(1) => '0',
s_axi_wstrb(0) => '0',
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(7) => '0',
s_axis_tdata(6) => '0',
s_axis_tdata(5) => '0',
s_axis_tdata(4) => '0',
s_axis_tdata(3) => '0',
s_axis_tdata(2) => '0',
s_axis_tdata(1) => '0',
s_axis_tdata(0) => '0',
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(0) => '0',
s_axis_tuser(3) => '0',
s_axis_tuser(2) => '0',
s_axis_tuser(1) => '0',
s_axis_tuser(0) => '0',
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => NLW_U0_valid_UNCONNECTED,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(4 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(4 downto 0),
wr_en => wr_en,
wr_rst => '0',
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2906.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p03n01i02906ent IS
END c02s01b01x02p03n01i02906ent;
ARCHITECTURE c02s01b01x02p03n01i02906arch OF c02s01b01x02p03n01i02906ent IS
procedure proc1 (signal S1: in bit) is
variable V2 : boolean;
begin
-- Failure_here : attribute STABLE may not be read within a procedure
V2 := S1'stable;
end proc1;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x02p03n01i02906 - The attribute STABLE of formal signal parameters can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p03n01i02906arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2906.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p03n01i02906ent IS
END c02s01b01x02p03n01i02906ent;
ARCHITECTURE c02s01b01x02p03n01i02906arch OF c02s01b01x02p03n01i02906ent IS
procedure proc1 (signal S1: in bit) is
variable V2 : boolean;
begin
-- Failure_here : attribute STABLE may not be read within a procedure
V2 := S1'stable;
end proc1;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x02p03n01i02906 - The attribute STABLE of formal signal parameters can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p03n01i02906arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2906.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p03n01i02906ent IS
END c02s01b01x02p03n01i02906ent;
ARCHITECTURE c02s01b01x02p03n01i02906arch OF c02s01b01x02p03n01i02906ent IS
procedure proc1 (signal S1: in bit) is
variable V2 : boolean;
begin
-- Failure_here : attribute STABLE may not be read within a procedure
V2 := S1'stable;
end proc1;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x02p03n01i02906 - The attribute STABLE of formal signal parameters can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p03n01i02906arch;
|
-- $Id: tb_s3_sram_memctl.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_s3_sram_memctl - sim
-- Description: Test bench for s3_sram_memctl
--
-- Dependencies: vlib/simlib/simclk
-- vlib/simlib/simclkcnt
-- bplib/issi/is61lv25616al
-- s3_sram_memctl [UUT]
--
-- To test: s3_sram_memctl
--
-- Verified (with tb_s3_sram_memctl_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2007-12-16 101 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok
-- 2007-12-16 101 - 0.26 - - c:ok
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.31
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclk/simclkcnt
-- 2011-11-21 432 1.0.6 now numeric_std clean
-- 2010-05-23 293 1.0.5 output # busy cycles; change CHK pipeline logic
-- 2010-05-16 291 1.0.4 rename tb_memctl_s3sram->tb_s3_sram_memctl
-- 2008-03-24 129 1.0.3 CLK_CYCLE now 31 bits
-- 2008-02-17 117 1.0.2 use req,we rather req_r,req_w interface
-- 2008-01-20 113 1.0.1 rename memdrv -> memctl_s3sram
-- 2007-12-15 101 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.s3boardlib.all;
use work.simlib.all;
entity tb_s3_sram_memctl is
end tb_s3_sram_memctl;
architecture sim of tb_s3_sram_memctl is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal REQ : slbit := '0';
signal WE : slbit := '0';
signal BUSY : slbit := '0';
signal ACK_R : slbit := '0';
signal ACK_W : slbit := '0';
signal ACT_R : slbit := '0';
signal ACT_W : slbit := '0';
signal ADDR : slv18 := (others=>'0');
signal BE : slv4 := (others=>'0');
signal DI : slv32 := (others=>'0');
signal DO : slv32 := (others=>'0');
signal O_MEM_CE_N : slv2 := (others=>'0');
signal O_MEM_BE_N : slv4 := (others=>'0');
signal O_MEM_WE_N : slbit := '0';
signal O_MEM_OE_N : slbit := '0';
signal O_MEM_ADDR : slv18 := (others=>'0');
signal IO_MEM_DATA : slv32 := (others=>'0');
signal R_MEMON : slbit := '0';
signal N_CHK_DATA : slbit := '0';
signal N_REF_DATA : slv32 := (others=>'0');
signal N_REF_ADDR : slv18 := (others=>'0');
signal R_CHK_DATA_AL : slbit := '0';
signal R_REF_DATA_AL : slv32 := (others=>'0');
signal R_REF_ADDR_AL : slv18 := (others=>'0');
signal R_CHK_DATA_DL : slbit := '0';
signal R_REF_DATA_DL : slv32 := (others=>'0');
signal R_REF_ADDR_DL : slv18 := (others=>'0');
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
constant clock_period : Delay_length := 20 ns;
constant clock_offset : Delay_length := 200 ns;
constant setup_time : Delay_length := 5 ns;
constant c2out_time : Delay_length := 10 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
MEM_L : entity work.is61lv25616al
port map (
CE_N => O_MEM_CE_N(0),
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(1),
LB_N => O_MEM_BE_N(0),
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA(15 downto 0)
);
MEM_U : entity work.is61lv25616al
port map (
CE_N => O_MEM_CE_N(1),
OE_N => O_MEM_OE_N,
WE_N => O_MEM_WE_N,
UB_N => O_MEM_BE_N(3),
LB_N => O_MEM_BE_N(2),
ADDR => O_MEM_ADDR,
DATA => IO_MEM_DATA(31 downto 16)
);
UUT : s3_sram_memctl
port map (
CLK => CLK,
RESET => RESET,
REQ => REQ,
WE => WE,
BUSY => BUSY,
ACK_R => ACK_R,
ACK_W => ACK_W,
ACT_R => ACT_R,
ACT_W => ACT_W,
ADDR => ADDR,
BE => BE,
DI => DI,
DO => DO,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
proc_stim: process
file fstim : text open read_mode is "tb_s3_sram_memctl_stim";
variable iline : line;
variable oline : line;
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable idelta : integer := 0;
variable iaddr : slv18 := (others=>'0');
variable idata : slv32 := (others=>'0');
variable ibe : slv4 := (others=>'0');
variable ival : slbit := '0';
variable nbusy : integer := 0;
begin
wait for clock_offset - setup_time;
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".memon" => -- .memon
read_ea(iline, ival);
R_MEMON <= ival;
wait for 2*clock_period;
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when "read " => -- read
readgen_ea(iline, iaddr, 16);
readgen_ea(iline, idata, 16);
ADDR <= iaddr;
REQ <= '1';
WE <= '0';
writetimestamp(oline, CLK_CYCLE, ": stim read ");
writegen(oline, iaddr, right, 6, 16);
write(oline, string'(" "));
writegen(oline, idata, right, 9, 16);
nbusy := 0;
while BUSY = '1' loop
nbusy := nbusy + 1;
wait for clock_period;
end loop;
write(oline, string'(" nbusy="));
write(oline, nbusy, right, 2);
writeline(output, oline);
N_CHK_DATA <= '1', '0' after clock_period;
N_REF_DATA <= idata;
N_REF_ADDR <= iaddr;
wait for clock_period;
REQ <= '0';
when "write " => -- write
readgen_ea(iline, iaddr, 16);
read_ea(iline, ibe);
readgen_ea(iline, idata, 16);
ADDR <= iaddr;
BE <= ibe;
DI <= idata;
REQ <= '1';
WE <= '1';
writetimestamp(oline, CLK_CYCLE, ": stim write");
writegen(oline, iaddr, right, 6, 16);
writegen(oline, ibe , right, 5, 2);
writegen(oline, idata, right, 9, 16);
nbusy := 0;
while BUSY = '1' loop
nbusy := nbusy + 1;
wait for clock_period;
end loop;
write(oline, string'(" nbusy="));
write(oline, nbusy, right, 2);
writeline(output, oline);
wait for clock_period;
REQ <= '0';
when others => -- bad directive
write(oline, string'("?? unknown directive: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file fstim
wait for 10*clock_period;
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if ACK_R = '1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
writegen(oline, DO, right, 9, 16);
if R_CHK_DATA_DL = '1' then
write(oline, string'(" CHECK"));
if R_REF_DATA_DL = DO then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL, exp="));
writegen(oline, R_REF_DATA_DL, right, 9, 16);
write(oline, string'(" for a="));
writegen(oline, R_REF_ADDR_DL, right, 5, 16);
end if;
R_CHK_DATA_DL <= '0';
end if;
writeline(output, oline);
end if;
if R_CHK_DATA_AL = '1' then
R_CHK_DATA_DL <= R_CHK_DATA_AL;
R_REF_DATA_DL <= R_REF_DATA_AL;
R_REF_ADDR_DL <= R_REF_ADDR_AL;
R_CHK_DATA_AL <= '0';
end if;
if N_CHK_DATA = '1' then
R_CHK_DATA_AL <= N_CHK_DATA;
R_REF_DATA_AL <= N_REF_DATA;
R_REF_ADDR_AL <= N_REF_ADDR;
end if;
end loop;
end process proc_moni;
proc_memon: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if R_MEMON = '1' then
writetimestamp(oline, CLK_CYCLE, ": mem ");
write(oline, string'(" ce="));
write(oline, not O_MEM_CE_N, right, 2);
write(oline, string'(" be="));
write(oline, not O_MEM_BE_N, right, 4);
write(oline, string'(" we="));
write(oline, not O_MEM_WE_N, right);
write(oline, string'(" oe="));
write(oline, not O_MEM_OE_N, right);
write(oline, string'(" a="));
writegen(oline, O_MEM_ADDR, right, 5, 16);
write(oline, string'(" d="));
writegen(oline, IO_MEM_DATA, right, 8, 16);
writeline(output, oline);
end if;
end loop;
end process proc_memon;
end sim;
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2011-2012, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- KCPSM6 reference design using 'uart_tx6' and 'uart_rx6'macros.
--
-- Target platform - ATLYS Spartan-6 Board (www.digilentinc.com).
-- To be used in conjunction with the PicoTerm terminal.
--
--
-- Ken Chapman - Xilinx Ltd.
--
-- 6th September 2012 - Initial version
--
--
-- This reference design primarily provides an example of UART communication. It also
-- includes some simple I/O ports (switches and LEDs) together with a simple example of
-- a KCPSM6 interrupt. The KCPSM6 program provided with this hardware design demonstrates
-- each of these KCPSM6 features together with features of PicoTerm.
--
-- Please see 'UART6_User_Guide_30Sept12.pdf' for more descriptions.
--
-- The code in this example is set to implement a 115200 UART baud rate and generates
-- interrupts at one second intervals based on a 100MHz clock.
--
-- Whilst the design is presented as a working example for the XC6SLX45-2CSG324 device on
-- the ATLYS Spartan-6 Board (www.digilentinc.com), it is a simple reference design that
-- is easily adapted or incorporated into a design for use with any hardware platform.
--
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
--
-------------------------------------------------------------------------------------------
--
--
entity uart6_atlys is
Port ( uart_rx : in std_logic;
uart_tx : out std_logic;
led : out std_logic_vector(7 downto 0);
switch : in std_logic_vector(7 downto 0);
reset_b : in std_logic;
clk : in std_logic);
end uart6_atlys;
--
-------------------------------------------------------------------------------------------
--
-- Start of test architecture
--
architecture Behavioral of uart6_atlys is
--
-------------------------------------------------------------------------------------------
--
-- Components
--
-------------------------------------------------------------------------------------------
--
--
-- declaration of KCPSM6
--
component kcpsm6
generic( hwbuild : std_logic_vector(7 downto 0) := X"00";
interrupt_vector : std_logic_vector(11 downto 0) := X"3FF";
scratch_pad_memory_size : integer := 64);
port ( address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
bram_enable : out std_logic;
in_port : in std_logic_vector(7 downto 0);
out_port : out std_logic_vector(7 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
k_write_strobe : out std_logic;
read_strobe : out std_logic;
interrupt : in std_logic;
interrupt_ack : out std_logic;
sleep : in std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
--
-- Development Program Memory
--
component atlys_real_time_clock
generic( C_FAMILY : string := "S6";
C_RAM_SIZE_KWORDS : integer := 1;
C_JTAG_LOADER_ENABLE : integer := 0);
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
clk : in std_logic);
end component;
--
-- UART Transmitter with integral 16 byte FIFO buffer
--
component uart_tx6
Port ( data_in : in std_logic_vector(7 downto 0);
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_write : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
buffer_reset : in std_logic;
clk : in std_logic);
end component;
--
-- UART Receiver with integral 16 byte FIFO buffer
--
component uart_rx6
Port ( serial_in : in std_logic;
en_16_x_baud : in std_logic;
data_out : out std_logic_vector(7 downto 0);
buffer_read : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
buffer_reset : in std_logic;
clk : in std_logic);
end component;
--
--
-------------------------------------------------------------------------------------------
--
-- Signals
--
-------------------------------------------------------------------------------------------
--
--
-- Signals used to connect KCPSM6
--
signal address : std_logic_vector(11 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal bram_enable : std_logic;
signal in_port : std_logic_vector(7 downto 0);
signal out_port : std_logic_vector(7 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal k_write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt : std_logic := '0';
signal interrupt_ack : std_logic;
signal kcpsm6_sleep : std_logic;
signal kcpsm6_reset : std_logic;
signal rdl : std_logic;
--
-- Signals used to connect UART_TX6
--
signal uart_tx_data_in : std_logic_vector(7 downto 0);
signal write_to_uart_tx : std_logic;
signal uart_tx_data_present : std_logic;
signal uart_tx_half_full : std_logic;
signal uart_tx_full : std_logic;
signal uart_tx_reset : std_logic;
--
-- Signals used to connect UART_RX6
--
signal uart_rx_data_out : std_logic_vector(7 downto 0);
signal read_from_uart_rx : std_logic;
signal uart_rx_data_present : std_logic;
signal uart_rx_half_full : std_logic;
signal uart_rx_full : std_logic;
signal uart_rx_reset : std_logic;
--
-- Signals used to define baud rate
--
signal baud_count : integer range 0 to 53 := 0;
signal en_16_x_baud : std_logic := '0';
--
--
-- Signals used to generate interrupt at one second intervals
--
signal int_count : integer range 0 to 99999999 := 0;
signal event_1hz : std_logic := '0';
--
--
-------------------------------------------------------------------------------------------
--
-- Start of circuit description
--
-------------------------------------------------------------------------------------------
--
begin
--
-----------------------------------------------------------------------------------------
-- Instantiate KCPSM6 and connect to program ROM
-----------------------------------------------------------------------------------------
--
-- The generics can be defined as required. In this case the 'hwbuild' value is used to
-- define a version using the ASCII code for the desired letter and the interrupt vector
-- has been set to 3C0 to provide 64 instructions for an Interrupt Service Routine (ISR)
-- before reaching the end of a 1K memory
--
--
processor: kcpsm6
generic map ( hwbuild => X"41", -- 41 hex is ASCII character "A"
interrupt_vector => X"3C0",
scratch_pad_memory_size => 64)
port map( address => address,
instruction => instruction,
bram_enable => bram_enable,
port_id => port_id,
write_strobe => write_strobe,
k_write_strobe => k_write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
sleep => kcpsm6_sleep,
reset => kcpsm6_reset,
clk => clk);
--
-- Reset by press button (active Low) or JTAG Loader enabled Program Memory
--
kcpsm6_reset <= rdl or not(reset_b);
--
-- Unused signals tied off until required.
-- Tying to other signals used to minimise warning messages.
--
kcpsm6_sleep <= write_strobe and k_write_strobe; -- Always '0'
--
-- Development Program Memory
-- JTAG Loader enabled for rapid code development.
--
program_rom: atlys_real_time_clock
generic map( C_FAMILY => "S6",
C_RAM_SIZE_KWORDS => 1,
C_JTAG_LOADER_ENABLE => 1)
port map( address => address,
instruction => instruction,
enable => bram_enable,
rdl => rdl,
clk => clk);
--
-----------------------------------------------------------------------------------------
-- Interrupt control
-----------------------------------------------------------------------------------------
--
-- Interrupt is used to provide a 1 second time reference.
--
-- A simple binary counter is used to divide the 100MHz clock and provide
-- interrupt pulses that remain active until acknowledged by KCPSM6.
--
interrupt_control: process(clk)
begin
if clk'event and clk='1' then
--divide 100MHz by 100,000,000 to form 1Hz pulses
if int_count=99999999 then
int_count <= 0;
event_1hz <= '1';
else
int_count <= int_count + 1;
event_1hz <= '0';
end if;
-- Interrupt becomes active each second and remains active until acknowledged
if interrupt_ack = '1' then
interrupt <= '0';
else
if event_1hz = '1' then
interrupt <= '1';
else
interrupt <= interrupt;
end if;
end if;
end if;
end process interrupt_control;
--
-----------------------------------------------------------------------------------------
-- UART Transmitter with integral 16 byte FIFO buffer
-----------------------------------------------------------------------------------------
--
-- Write to buffer in UART Transmitter at port address 01 hex
--
tx: uart_tx6
port map ( data_in => uart_tx_data_in,
en_16_x_baud => en_16_x_baud,
serial_out => uart_tx,
buffer_write => write_to_uart_tx,
buffer_data_present => uart_tx_data_present,
buffer_half_full => uart_tx_half_full,
buffer_full => uart_tx_full,
buffer_reset => uart_tx_reset,
clk => clk);
--
-----------------------------------------------------------------------------------------
-- UART Receiver with integral 16 byte FIFO buffer
-----------------------------------------------------------------------------------------
--
-- Read from buffer in UART Receiver at port address 01 hex.
--
-- When KCPMS6 reads data from the receiver a pulse must be generated so that the
-- FIFO buffer presents the next character to be read and updates the buffer flags.
--
rx: uart_rx6
port map ( serial_in => uart_rx,
en_16_x_baud => en_16_x_baud,
data_out => uart_rx_data_out,
buffer_read => read_from_uart_rx,
buffer_data_present => uart_rx_data_present,
buffer_half_full => uart_rx_half_full,
buffer_full => uart_rx_full,
buffer_reset => uart_rx_reset,
clk => clk);
--
-----------------------------------------------------------------------------------------
-- RS232 (UART) baud rate
-----------------------------------------------------------------------------------------
--
-- To set serial communication baud rate to 115,200 then en_16_x_baud must pulse
-- High at 1,843,200Hz which is every 54.28 cycles at 100MHz. In this implementation
-- a pulse is generated every 54 cycles resulting is a baud rate of 115,741 baud which
-- is only 0.5% high and well within limits.
--
baud_rate: process(clk)
begin
if clk'event and clk = '1' then
if baud_count = 53 then -- counts 54 states including zero
baud_count <= 0;
en_16_x_baud <= '1'; -- single cycle enable pulse
else
baud_count <= baud_count + 1;
en_16_x_baud <= '0';
end if;
end if;
end process baud_rate;
--
-----------------------------------------------------------------------------------------
-- General Purpose Input Ports.
-----------------------------------------------------------------------------------------
--
-- Two input ports are used with the UART macros. The first is used to monitor the flags
-- on both the UART transmitter and receiver. The second is used to read the data from
-- the UART receiver. Note that the read also requires a 'buffer_read' pulse to be
-- generated.
--
-- This design includes a third input port to read 8 general purpose switches.
--
input_ports: process(clk)
begin
if clk'event and clk = '1' then
case port_id(1 downto 0) is
-- Read UART status at port address 00 hex
when "00" => in_port(0) <= uart_tx_data_present;
in_port(1) <= uart_tx_half_full;
in_port(2) <= uart_tx_full;
in_port(3) <= uart_rx_data_present;
in_port(4) <= uart_rx_half_full;
in_port(5) <= uart_rx_full;
-- Read UART_RX6 data at port address 01 hex
-- (see 'buffer_read' pulse generation below)
when "01" => in_port <= uart_rx_data_out;
-- Read 8 general purpose switches at port address 02 hex
when "10" => in_port <= switch;
-- Don't Care for unused case(s) ensures minimum logic implementation
when others => in_port <= "XXXXXXXX";
end case;
-- Generate 'buffer_read' pulse following read from port address 01
if (read_strobe = '1') and (port_id(1 downto 0) = "01") then
read_from_uart_rx <= '1';
else
read_from_uart_rx <= '0';
end if;
end if;
end process input_ports;
--
-----------------------------------------------------------------------------------------
-- General Purpose Output Ports
-----------------------------------------------------------------------------------------
--
-- In this simple example there are two output ports.
-- A simple output port used to control a set of 8 general purpose LEDs.
-- A port used to write data directly to the FIFO buffer within 'uart_tx6' macro.
--
--
-- LEDs are connected to a typical KCPSM6 output port.
-- i.e. A register and associated decode logic to enable data capture.
--
output_ports: process(clk)
begin
if clk'event and clk = '1' then
-- 'write_strobe' is used to qualify all writes to general output ports.
if write_strobe = '1' then
-- Write to LEDs at port address 02 hex
if port_id(1) = '1' then
led <= out_port;
end if;
end if;
end if;
end process output_ports;
--
-- Write directly to the FIFO buffer within 'uart_tx6' macro at port address 01 hex.
-- Note the direct connection of 'out_port' to the UART transmitter macro and the
-- way that a single clock cycle write pulse is generated to capture the data.
--
uart_tx_data_in <= out_port;
write_to_uart_tx <= '1' when (write_strobe = '1') and (port_id(0) = '1')
else '0';
--
-----------------------------------------------------------------------------------------
-- Constant-Optimised Output Ports
-----------------------------------------------------------------------------------------
--
-- One constant-optimised output port is used to facilitate resetting of the UART macros.
--
constant_output_ports: process(clk)
begin
if clk'event and clk = '1' then
if k_write_strobe = '1' then
if port_id(0) = '1' then
uart_tx_reset <= out_port(0);
uart_rx_reset <= out_port(1);
end if;
end if;
end if;
end process constant_output_ports;
--
-----------------------------------------------------------------------------------------
--
end Behavioral;
-------------------------------------------------------------------------------------------
--
-- END OF FILE uart6_atlys.vhd
--
-------------------------------------------------------------------------------------------
|
-- Manually adapted from ../../../../../reconfmodule/chll/out/chip-e.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity chip is
port (
Reset_i : in std_logic;
Clk_i : in std_logic;
Dbg_En_i : in std_logic;
Dbg_SCL_i : in std_logic;
Dbg_SDA_b : inout std_logic;
P1_b : inout std_logic_vector(7 downto 0);
P2_b : inout std_logic_vector(7 downto 0);
UartRxD_i : in std_logic;
UartTxD_o : out std_logic;
MISO_i : in std_logic;
MOSI_o : out std_logic;
SCK_o : out std_logic;
Inputs_i : in std_logic_vector(7 downto 0);
Outputs_o : out std_logic_vector(7 downto 0);
SPIMISO_i : in std_logic;
SPIMOSI_o : out std_logic;
SPISCK_o : out std_logic;
I2CSCL_b : out std_logic;
I2CSDA_b : inout std_logic;
AdcConvComplete_i : in std_logic;
AdcDoConvert_o : out std_logic;
AdcValue_i : in std_logic_vector(9 downto 0)
);
end chip;
|
-- Reciever
--
-- Part of MARK II project. For informations about license, please
-- see file /LICENSE .
--
-- author: Vladislav Mlejnecký
-- email: [email protected]
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reciever is
port(
en: in std_logic;
clk: in std_logic;
res: in std_logic;
rx: in std_logic;
baud16_clk_en: in std_logic;
rx_data: out unsigned(7 downto 0);
rx_done: out std_logic
);
end entity reciever;
architecture reciever_arch of reciever is
type rx_state_type is (idle, start_sync, wait_for_sync, sync, wait_b0, get_b0, wait_b1, get_b1,wait_b2, get_b2,
wait_b3, get_b3,wait_b4, get_b4,wait_b5, get_b5,wait_b6, get_b6,wait_b7, get_b7,
wait_stopbit, store_data_0, store_data_1);
signal state: rx_state_type; -- state for RX FSM
signal sipo_val: unsigned(7 downto 0);
signal rx_rec_com, res_counter, shift_sipo_reg: std_logic; -- control signals for RX FSM
signal baud_clk_en: std_logic; -- this is an baud clock
signal count: unsigned(3 downto 0); -- this is rx counter value
begin
sipo_reg:
process(res, clk, rx, shift_sipo_reg) is
variable sipo_var: unsigned(7 downto 0);
begin
if rising_edge(clk) then
if res = '1' then
sipo_var := (others => '0');
elsif shift_sipo_reg = '1' then
sipo_var(6 downto 0) := sipo_var(7 downto 1);
sipo_var(7) := rx;
end if;
end if;
sipo_val <= sipo_var;
end process;
rx_out_reg:
process(res, clk, rx_rec_com) is
variable out_reg: unsigned(7 downto 0);
begin
if rising_edge(clk) then
if(res = '1') then
out_reg := (others => '0');
elsif rx_rec_com = '1' then
out_reg := sipo_val;
end if;
end if;
rx_data <= out_reg;
end process;
rxcounter:
process(clk, res) is
variable counter: unsigned(3 downto 0);
begin
if rising_edge(clk) then
if res = '1' then
counter := (others => '0');
elsif res_counter = '1' then
counter := (others => '0');
elsif baud16_clk_en = '1' then
counter := counter + 1;
end if;
end if;
count <= counter;
end process;
process(count, baud16_clk_en) is
begin
if count = x"F" then
baud_clk_en <= baud16_clk_en;
else
baud_clk_en <= '0';
end if;
end process;
process(clk, res, count, baud_clk_en, rx) is
begin
if rising_edge(clk) then
if res = '1' then
state <= idle;
else
case state is
when idle =>
if ((rx = '0') and (en = '1')) then
state <= start_sync;
else
state <= idle;
end if;
when start_sync => state <= wait_for_sync;
when wait_for_sync =>
if count = "0111" then
state <= sync;
else
state <= wait_for_sync;
end if;
when sync => state <= wait_b0;
when wait_b0 =>
if baud_clk_en = '1' then
state <= get_b0;
else
state <= wait_b0;
end if;
when get_b0 => state <= wait_b1;
when wait_b1 =>
if baud_clk_en = '1' then
state <= get_b1;
else
state <= wait_b1;
end if;
when get_b1 => state <= wait_b2;
when wait_b2 =>
if baud_clk_en = '1' then
state <= get_b2;
else
state <= wait_b2;
end if;
when get_b2 => state <= wait_b3;
when wait_b3 =>
if baud_clk_en = '1' then
state <= get_b3;
else
state <= wait_b3;
end if;
when get_b3 => state <= wait_b4;
when wait_b4 =>
if baud_clk_en = '1' then
state <= get_b4;
else
state <= wait_b4;
end if;
when get_b4 => state <= wait_b5;
when wait_b5 =>
if baud_clk_en = '1' then
state <= get_b5;
else
state <= wait_b5;
end if;
when get_b5 => state <= wait_b6;
when wait_b6 =>
if baud_clk_en = '1' then
state <= get_b6;
else
state <= wait_b6;
end if;
when get_b6 => state <= wait_b7;
when wait_b7 =>
if baud_clk_en = '1' then
state <= get_b7;
else
state <= wait_b7;
end if;
when get_b7 => state <= wait_stopbit;
when wait_stopbit =>
if baud_clk_en = '1' then
state <= store_data_0;
else
state <= wait_stopbit;
end if;
when store_data_0 => state <= store_data_1;
when store_data_1 => state <= idle;
end case;
end if;
end if;
end process;
process(state) is
begin
case state is
when idle => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when start_sync => rx_rec_com <= '0'; res_counter <= '1'; shift_sipo_reg <= '0'; rx_done <= '0';
when wait_for_sync => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when sync => rx_rec_com <= '0'; res_counter <= '1'; shift_sipo_reg <= '0'; rx_done <= '0';
when wait_b0 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b0 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b1 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b1 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b2 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b2 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b3 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b3 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b4 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b4 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b5 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b5 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b6 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b6 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_b7 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when get_b7 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '1'; rx_done <= '0';
when wait_stopbit => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when store_data_0 => rx_rec_com <= '1'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '0';
when store_data_1 => rx_rec_com <= '0'; res_counter <= '0'; shift_sipo_reg <= '0'; rx_done <= '1';
end case;
end process;
end architecture reciever_arch;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
-- Module Name: vga_hdmi - Behavioral
--
-- Description: A test of the Zedboard's VGA & HDMI interface
--
-- Feel free to use this how you see fit, and fix any errors you find :-)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity vga_hdmi is
port(
clk100 : in std_logic;
clk25 : in std_logic;
rgb888 : in std_logic_vector(23 downto 0);
vsync : in std_logic;
hsync : in std_logic;
active : in std_logic;
hdmi_clk : out std_logic;
hdmi_hsync : out std_logic;
hdmi_vsync : out std_logic;
hdmi_d : out std_logic_vector(15 downto 0);
hdmi_de : out std_logic;
hdmi_scl : out std_logic;
hdmi_sda : inout std_logic);
end vga_hdmi;
architecture Behavioral of vga_hdmi is
COMPONENT convert_444_422
PORT( clk : IN std_logic;
r_in : IN std_logic_vector(7 downto 0);
g_in : IN std_logic_vector(7 downto 0);
b_in : IN std_logic_vector(7 downto 0);
hsync_in : IN std_logic;
vsync_in : IN std_logic;
de_in : IN std_logic;
r1_out : OUT std_logic_vector(8 downto 0);
g1_out : OUT std_logic_vector(8 downto 0);
b1_out : OUT std_logic_vector(8 downto 0);
r2_out : OUT std_logic_vector(8 downto 0);
g2_out : OUT std_logic_vector(8 downto 0);
b2_out : OUT std_logic_vector(8 downto 0);
pair_start_out: OUT std_logic;
hsync_out : OUT std_logic;
vsync_out : OUT std_logic;
de_out : OUT std_logic
);
END COMPONENT;
COMPONENT colour_space_conversion
PORT( clk : IN std_logic;
r1_in : IN std_logic_vector(8 downto 0);
g1_in : IN std_logic_vector(8 downto 0);
b1_in : IN std_logic_vector(8 downto 0);
r2_in : IN std_logic_vector(8 downto 0);
g2_in : IN std_logic_vector(8 downto 0);
b2_in : IN std_logic_vector(8 downto 0);
pair_start_in: IN std_logic;
de_in : IN std_logic;
vsync_in : IN std_logic;
hsync_in : IN std_logic;
y_out : OUT std_logic_vector(7 downto 0);
c_out : OUT std_logic_vector(7 downto 0);
de_out : OUT std_logic;
hsync_out : OUT std_logic;
vsync_out : OUT std_logic
);
END COMPONENT;
COMPONENT hdmi_ddr_output
PORT(
clk : IN std_logic;
clk90 : IN std_logic;
y : IN std_logic_vector(7 downto 0);
c : IN std_logic_vector(7 downto 0);
hsync_in : IN std_logic;
vsync_in : IN std_logic;
de_in : IN std_logic;
hdmi_sda : INOUT std_logic;
hdmi_clk : OUT std_logic;
hdmi_hsync : OUT std_logic;
hdmi_vsync : OUT std_logic;
hdmi_d : OUT std_logic_vector(15 downto 0);
hdmi_de : OUT std_logic;
hdmi_scl : OUT std_logic
);
END COMPONENT;
-- Clocking
signal clk0 : std_logic;
signal clk90 : std_logic;
signal clkfb : std_logic;
-- Signals from the pixel pair convertor
signal c422_r1 : std_logic_vector(8 downto 0);
signal c422_g1 : std_logic_vector(8 downto 0);
signal c422_b1 : std_logic_vector(8 downto 0);
signal c422_r2 : std_logic_vector(8 downto 0);
signal c422_g2 : std_logic_vector(8 downto 0);
signal c422_b2 : std_logic_vector(8 downto 0);
signal c422_pair_start : std_logic;
signal c422_hsync : std_logic;
signal c422_vsync : std_logic;
signal c422_de : std_logic;
-- Signals from the colour space convertor
signal csc_y : std_logic_vector(7 downto 0);
signal csc_c : std_logic_vector(7 downto 0);
signal csc_hsync : std_logic;
signal csc_vsync : std_logic;
signal csc_de : std_logic;
-- signals from the output range clampler
signal clamper_c : std_logic_vector(7 downto 0);
signal clamper_y : std_logic_vector(7 downto 0);
signal clamper_hsync : std_logic;
signal clamper_vsync : std_logic;
signal clamper_de : std_logic;
begin
i_convert_444_422: convert_444_422 PORT MAP(
clk => clk25,
r_in => rgb888(23 downto 16),
g_in => rgb888(15 downto 8),
b_in => rgb888(7 downto 0),
hsync_in => hsync,
vsync_in => vsync,
de_in => active,
r1_out => c422_r1,
g1_out => c422_g1,
b1_out => c422_b1,
r2_out => c422_r2,
g2_out => c422_g2,
b2_out => c422_b2,
pair_start_out => c422_pair_start,
hsync_out => c422_hsync,
vsync_out => c422_vsync,
de_out => c422_de
);
i_csc: colour_space_conversion PORT MAP(
clk => clk25,
r1_in => c422_r1,
g1_in => c422_g1,
b1_in => c422_b1,
r2_in => c422_r2,
g2_in => c422_g2,
b2_in => c422_b2,
pair_start_in => c422_pair_start,
vsync_in => c422_vsync,
hsync_in => c422_hsync,
de_in => c422_de,
y_out => csc_y,
c_out => csc_c,
hsync_out => csc_hsync,
vsync_out => csc_vsync,
de_out => csc_de
);
clamper_y <= csc_y;
clamper_c <= csc_c;
clamper_de <= csc_de;
clamper_hsync <= csc_hsync;
clamper_vsync <= csc_vsync;
i_hdmi_ddr_output: hdmi_ddr_output PORT MAP(
clk => clk25,
clk90 => clk90,
y => clamper_y,
c => clamper_c,
hsync_in => clamper_hsync,
vsync_in => clamper_vsync,
de_in => clamper_de,
hdmi_clk => hdmi_clk,
hdmi_hsync => hdmi_hsync,
hdmi_vsync => hdmi_vsync,
hdmi_d => hdmi_d,
hdmi_de => hdmi_de,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda
);
-- Generate a 75MHz pixel clock and one with 90 degree phase shift from the 100MHz system clock.
PLLE2_BASE_inst : PLLE2_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => 9, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
CLKIN1_PERIOD => 10.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT0_DIVIDE => 9,
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 12,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 135.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
DIVCLK_DIVIDE => 1, -- Master division value, (1-56)
REF_JITTER1 => 0.0, -- Reference input jitter in UI, (0.000-0.999).
STARTUP_WAIT => "FALSE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => clk0,
CLKOUT1 => open,
CLKOUT2 => clk90,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKFBOUT => clkfb, -- 1-bit output: Feedback clock
LOCKED => open, -- 1-bit output: LOCK
CLKIN1 => clk100, -- 1-bit input: Input clock
PWRDWN => '0', -- 1-bit input: Power-down
RST => '0', -- 1-bit input: Reset
CLKFBIN => clkfb -- 1-bit input: Feedback clock
);
end Behavioral;
|
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
IF a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
IF x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2201.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02201ent IS
END c07s02b06x00p01n01i02201ent;
ARCHITECTURE c07s02b06x00p01n01i02201arch OF c07s02b06x00p01n01i02201ent IS
BEGIN
TESTING: PROCESS
type array_one is array (1 to 10) of boolean;
type array_two is array (1 to 20) of boolean;
variable x : array_one;
variable y : array_two;
variable z : integer;
BEGIN
z := x * y; -- Failure_here
-- multiplying operator cannot operate on array types.
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02201 - Multiplying operators are predefined only for integer and floating point types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02201arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2201.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02201ent IS
END c07s02b06x00p01n01i02201ent;
ARCHITECTURE c07s02b06x00p01n01i02201arch OF c07s02b06x00p01n01i02201ent IS
BEGIN
TESTING: PROCESS
type array_one is array (1 to 10) of boolean;
type array_two is array (1 to 20) of boolean;
variable x : array_one;
variable y : array_two;
variable z : integer;
BEGIN
z := x * y; -- Failure_here
-- multiplying operator cannot operate on array types.
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02201 - Multiplying operators are predefined only for integer and floating point types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02201arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2201.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02201ent IS
END c07s02b06x00p01n01i02201ent;
ARCHITECTURE c07s02b06x00p01n01i02201arch OF c07s02b06x00p01n01i02201ent IS
BEGIN
TESTING: PROCESS
type array_one is array (1 to 10) of boolean;
type array_two is array (1 to 20) of boolean;
variable x : array_one;
variable y : array_two;
variable z : integer;
BEGIN
z := x * y; -- Failure_here
-- multiplying operator cannot operate on array types.
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02201 - Multiplying operators are predefined only for integer and floating point types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02201arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:51:50 11/19/2013
-- Design Name:
-- Module Name: My_16bit4x1Mux_948282 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity My_16bit4x1Mux_948282 is
Port ( S_1 : in STD_LOGIC;
S_2 : in STD_LOGIC;
A_mux : in STD_LOGIC_VECTOR (15 downto 0);
B_mux : in STD_LOGIC_VECTOR (15 downto 0);
C_mux : in STD_LOGIC_VECTOR (15 downto 0);
D_mux : in STD_LOGIC_VECTOR (15 downto 0);
Result : out STD_LOGIC_VECTOR (15 downto 0));
end My_16bit4x1Mux_948282;
architecture Behavioral of My_16bit4x1Mux_948282 is
component My_4bit4x1Mux_948282 is
Port ( S1 : in STD_LOGIC;
S2 : in STD_LOGIC;
A_in : in STD_LOGIC_VECTOR (3 downto 0);
B_in : in STD_LOGIC_VECTOR (3 downto 0);
C_in : in STD_LOGIC_VECTOR (3 downto 0);
D_in : in STD_LOGIC_VECTOR (3 downto 0);
Decision : out STD_LOGIC_VECTOR (3 downto 0));
end component;
signal sig1: std_logic;
signal sig2, sig3: std_logic;
begin
u0: My_4bit4x1Mux_948282 port map (S1=>S_1, S2=>S_2, A_in=>A_mux(3 downto 0), B_in=>B_mux(3 downto 0), C_in=>C_mux(3 downto 0), D_in=>D_mux(3 downto 0), Decision=>Result(3 downto 0));
u1: My_4bit4x1Mux_948282 port map (S1=>S_1, S2=>S_2, A_in=>A_mux(7 downto 4), B_in=>B_mux(7 downto 4), C_in=>C_mux(7 downto 4), D_in=>D_mux(7 downto 4), Decision=>Result(7 downto 4));
u2: My_4bit4x1Mux_948282 port map (S1=>S_1, S2=>S_2, A_in=>A_mux(11 downto 8), B_in=>B_mux(11 downto 8), C_in=>C_mux(11 downto 8), D_in=>D_mux(11 downto 8), Decision=>Result(11 downto 8));
u3: My_4bit4x1Mux_948282 port map (S1=>S_1, S2=>S_2, A_in=>A_mux(15 downto 12), B_in=>B_mux(15 downto 12), C_in=>C_mux(15 downto 12), D_in=>D_mux(15 downto 12), Decision=>Result(15 downto 12));
end Behavioral;
|
-- $Id: tb_nexys2_fusp.vhd 433 2011-11-27 22:04:39Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys2_fusp - sim
-- Description: Test bench for nexys2 (base+fusp)
--
-- Dependencies: vlib/rlink/tb/tbcore_rlink_dcm
-- tb_nexys2_core
-- vlib/serport/serport_uart_rxtx
-- nexys2_fusp_aif [UUT]
--
-- To test: generic, any nexys2_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 11.4, 12.1, 13.1; ghdl 0.26-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-26 433 3.1.1 remove O_FLA_CE_N from tb_nexys2_core
-- 2011-11-21 432 3.1 update O_FLA_CE_N usage
-- 2011-11-19 427 3.0.1 now numeric_std clean
-- 2010-12-29 351 3.0 use rlink/tb now
-- 2010-11-13 338 1.0.2 now dcm aware: add O_CLKSYS, use rritb_core_dcm
-- 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
-- 2010-05-28 295 1.0 Initial version (derived from tb_s3board_fusp)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.rlinktblib.all;
use work.serport.all;
use work.nexys2lib.all;
use work.simlib.all;
use work.simbus.all;
entity tb_nexys2_fusp is
end tb_nexys2_fusp;
architecture sim of tb_nexys2_fusp is
signal CLKOSC : slbit := '0';
signal CLKSYS : slbit := '0';
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal RX_HOLD : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_LED : slv8 := (others=>'0');
signal O_ANO_N : slv4 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal O_MEM_CE_N : slbit := '1';
signal O_MEM_BE_N : slv2 := (others=>'1');
signal O_MEM_WE_N : slbit := '1';
signal O_MEM_OE_N : slbit := '1';
signal O_MEM_ADV_N : slbit := '1';
signal O_MEM_CLK : slbit := '0';
signal O_MEM_CRE : slbit := '0';
signal I_MEM_WAIT : slbit := '0';
signal O_MEM_ADDR : slv23 := (others=>'Z');
signal IO_MEM_DATA : slv16 := (others=>'0');
signal O_FLA_CE_N : slbit := '0';
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal R_PORTSEL : slbit := '0';
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clockosc_period : time := 20 ns;
constant clockosc_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 9 ns;
begin
TBCORE : tbcore_rlink_dcm
generic map (
CLKOSC_PERIOD => clockosc_period,
CLKOSC_OFFSET => clockosc_offset,
SETUP_TIME => setup_time,
C2OUT_TIME => c2out_time)
port map (
CLKOSC => CLKOSC,
CLKSYS => CLKSYS,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => RX_HOLD,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
RX_HOLD <= TXBUSY or RTS_N; -- back preasure for data flow to tb
N2CORE : entity work.tb_nexys2_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
UUT : nexys2_fusp_aif
port map (
I_CLK50 => CLKOSC,
O_CLKSYS => CLKSYS,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N,
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA,
O_FLA_CE_N => O_FLA_CE_N,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
UART : serport_uart_rxtx
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKSYS,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => UART_TXD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
proc_port_mux: process (R_PORTSEL, UART_TXD, CTS_N,
O_TXD, O_FUSP_TXD, O_FUSP_RTS_N)
begin
if R_PORTSEL = '0' then -- use main board rs232, no flow cntl
I_RXD <= UART_TXD; -- write port 0 inputs
UART_RXD <= O_TXD; -- get port 0 outputs
RTS_N <= '0';
I_FUSP_RXD <= '1'; -- port 1 inputs to idle state
I_FUSP_CTS_N <= '0';
else -- otherwise use pmod1 rs232
I_FUSP_RXD <= UART_TXD; -- write port 1 inputs
I_FUSP_CTS_N <= CTS_N;
UART_RXD <= O_FUSP_TXD; -- get port 1 outputs
RTS_N <= O_FUSP_RTS_N;
I_RXD <= '1'; -- port 0 inputs to idle state
end if;
end process proc_port_mux;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKSYS);
wait for c2out_time;
if RXERR = '1' then
writetimestamp(oline, SB_CLKCYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL <= to_x01(SB_DATA(0));
end if;
end if;
end process proc_simbus;
end sim;
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00468
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.7 (7)
-- 9.7 (10)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00468_1(ARCH00468_1)
-- ENT00468(ARCH00468)
-- ENT00468_Test_Bench(ARCH00468_Test_Bench)
--
-- REVISION HISTORY:
--
-- 6-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
entity ENT00468_1 is
generic ( G : Integer ) ;
port ( P : in Integer ;
Q : out Integer ) ;
end ENT00468_1 ;
use WORK.STANDARD_TYPES.all ;
architecture ARCH00468_1 of ENT00468_1 is
begin
process ( P )
variable First_Time : boolean := True ;
begin
if First_Time then
First_Time := False ;
else
Q <= transport (P + G) after 0 ns ;
end if ;
end process ;
end ARCH00468_1 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00468 is
generic ( G1_Low, G1_High : t_enum1 ;
G2_Low, G2_High : Integer ) ;
end ENT00468 ;
architecture ARCH00468 of ENT00468 is
component Comp1
generic ( G : Integer ) ;
port ( P : in Integer ;
Q : out Integer ) ;
end component ;
for all : Comp1 use entity WORK.ENT00468_1 ( ARCH00468_1 );
type Arr_enum1 is array (t_enum1 range G1_Low to G1_High)
of Integer ;
signal S_enum1 : Arr_enum1 := Arr_enum1'(others => -1) ;
subtype t_uint is Integer range G2_Low to G2_High ;
type Arr_uint is array (t_uint) of Integer ;
signal S_uint : Arr_uint := Arr_uint'(others => -1) ;
begin
s_enum1(Arr_enum1'Left) <= transport 0 after 0 ns ;
For_Gen1 : -- Null range
for i in Arr_enum1'Left downto t_enum1'Pred (Arr_enum1'Right) generate
L1 : Comp1
generic map ( t_enum1'Pos (i) )
port map ( s_enum1(i), s_enum1(t_enum1'Succ(i)) ) ;
end generate For_Gen1 ;
Check_It1 :
process
begin
wait for 30 ns ;
test_report ( "ARCH00468.Check_It1" ,
"Globally static null discrete ranges are permited on "&
"generate statements" ,
s_enum1 = Arr_enum1 ' (0, -1, -1, -1) ) ;
wait ;
end process Check_It1 ;
------------
s_uint(Arr_uint'Left) <= transport 0 after 0 ns ;
For_Gen2 : -- Null Range
for i in Arr_uint'Left downto t_uint'Pred (Arr_uint'Right) generate
L2 : Comp1
generic map ( t_uint'Pos (i) )
port map ( s_uint(i), s_uint(t_uint'Succ(i)) ) ;
end generate For_Gen2 ;
Check_It2 :
process
begin
wait for 30 ns ;
test_report ( "ARCH00468.Check_It2" ,
"Globally static null discrete ranges are permited on "&
"generate statements" ,
s_uint = Arr_uint ' (10 => 0, 11 to 20 => -1) ) ;
wait ;
end process Check_It2 ;
end ARCH00468 ;
entity ENT00468_Test_Bench is
end ENT00468_Test_Bench ;
use WORK.STANDARD_TYPES.all ;
architecture ARCH00468_Test_Bench of ENT00468_Test_Bench is
begin
L1:
block
component UUT generic ( G1_Low, G1_High : t_enum1 ;
G2_Low, G2_High : Integer ) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00468 ( ARCH00468 ) ;
begin
CIS1 : UUT generic map ( t_enum1'Low, t_enum1'High,
G2_High => 20,
G2_Low => 10 ) ;
end block L1 ;
end ARCH00468_Test_Bench ;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rgbfifo_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.rgbfifo_pkg.ALL;
ENTITY rgbfifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF rgbfifo_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:rgbfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rgbfifo_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.rgbfifo_pkg.ALL;
ENTITY rgbfifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF rgbfifo_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:rgbfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rgbfifo_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.rgbfifo_pkg.ALL;
ENTITY rgbfifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF rgbfifo_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:rgbfifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
---counts a number of clock cycles for the refresh rate to not be noticable by the human eye
--- but still high enough for the Seven Segment diodes to be able to turn on and off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DigitFSM is
Port ( Clock : in STD_LOGIC;
Data_En : out STD_LOGIC_VECTOR (7 downto 0);
Digit_sel : out STD_LOGIC_VECTOR (2 downto 0));
end DigitFSM;
architecture Behavioral of DigitFSM is
signal counter: STD_LOGIC_VECTOR (20 downto 0):=(others =>'0'); --1.250.000 counter max
signal counter_unsigned: unsigned(20 downto 0):=(others =>'0');
Type State_type is (SSD0,SSD1,SSD2,SSD3,SSD4,SSD5,SSD6,SSD7);
Signal state: State_type:=SSD0;
begin
process
begin
WAIT UNTIL Clock'EVENT AND Clock='1';
Case state is
when SSD0=>
Data_En<="11111110";
Digit_sel<="000";
if counter < 100000 then-- 125000
counter_unsigned<=unsigned(counter)+1;
else
counter_unsigned<= (others => '0');
state <= SSD1;
end if;
when SSD1=>
Data_En<="11111101";
Digit_sel<="001";
if counter < 100000 then --125000
counter_unsigned<=unsigned(counter)+1;
else
counter_unsigned<= (others => '0');
state <= SSD2;
end if;
when SSD2=>
Data_En<="11111011";
Digit_sel<="010";
if counter < 100000 then --125000
counter_unsigned<=unsigned(counter)+1;
else
counter_unsigned<= (others => '0');
state <= SSD3;
end if;
when SSD3=>
Data_En<="11110111";
Digit_sel<="011";
if counter < 100000 then --125000
counter_unsigned<=unsigned(counter)+1;
else
counter_unsigned<= (others => '0');
state <= SSD4;
end if;
when SSD4=>
Data_En<="11101111";
Digit_sel<="100";
if counter < 100000 then-- 125000
counter_unsigned<=unsigned(counter)+1;
else
counter_unsigned<= (others => '0');
state <= SSD5;
end if;
when SSD5=>
Data_En<="11011111";
Digit_sel<="101";
if counter < 100000 then --125000
counter_unsigned<=unsigned(counter)+1;
else
counter_unsigned<= (others => '0');
state <= SSD6;
end if;
when SSD6=>
Data_En<="10111111";
Digit_sel<="110";
if counter < 100000 then --125000
counter_unsigned<=unsigned(counter)+1;
else
counter_unsigned<= (others => '0');
state <= SSD7;
end if;
when SSD7=>
Data_En<="01111111";
Digit_sel<="111";
if counter < 100000 then --125000
counter_unsigned<=unsigned(counter)+1;
else
counter_unsigned<= (others => '0');
state <= SSD0;
end if;
end case;
end process;
counter<=STD_LOGIC_VECTOR(counter_unsigned);
end Behavioral; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1010.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
PACKAGE c06s03b00x00p10n01i01010pkg IS
--
-- This packages contains declarations of User attributes
--
-- ----------------------------------------------------------------------
--
TYPE RESISTANCE IS RANGE 0 TO 1E9
UNITS
pf;
nf = 1000 pf;
mf = 1000 nf;
END UNITS;
TYPE t_logic IS (
U, D,
Z0, Z1, ZDX, DZX, ZX,
W0, W1, WZ0, WZ1, WDX, DWX, WZX, ZWX, WX,
R0, R1, RW0, RW1, RZ0, RZ1, RDX, DRX, RZX, ZRX, RWX, WRX, RX,
F0, F1, FR0, FR1, FW0, FW1, FZ0, FZ1, FDX, DFX, FZX, ZFX, FWX, WFX, FRX, RFX, FX
);
--
-- Scalar types Declarations
--
SUBTYPE st_scl1 IS BOOLEAN;
SUBTYPE st_scl2 IS BIT;
SUBTYPE st_scl3 IS CHARACTER;
SUBTYPE st_scl4 IS INTEGER;
SUBTYPE st_scl5 IS REAL;
SUBTYPE st_scl6 IS TIME;
SUBTYPE st_scl7 IS RESISTANCE;
SUBTYPE st_scl8 IS t_logic;
--
-- character string types
--
SUBTYPE st_str1 IS STRING;
SUBTYPE st_str2 IS STRING (1 TO 4);
--
-- Scalar types with a range constraint
--
SUBTYPE cst_scl1 IS BOOLEAN RANGE TRUE TO TRUE;
SUBTYPE cst_scl2 IS BIT RANGE '0' TO '0';
SUBTYPE cst_scl3 IS CHARACTER RANGE 'a' TO 'z';
SUBTYPE cst_scl4 IS INTEGER RANGE 10 DOWNTO 0;
SUBTYPE cst_scl5 IS REAL RANGE 0.0 TO 10.0;
SUBTYPE cst_scl6 IS TIME RANGE 0 fs TO 10 ns;
SUBTYPE cst_scl7 IS RESISTANCE RANGE 0 pf TO 10000 pf;
SUBTYPE cst_scl8 IS t_logic RANGE F0 TO FX;
-- -----------------------------------------------------------------------------------------
-- Attribute Declarations
-- -----------------------------------------------------------------------------------------
--
ATTRIBUTE atr_scl1 : st_scl1;
ATTRIBUTE atr_scl2 : st_scl2;
ATTRIBUTE atr_scl3 : st_scl3;
ATTRIBUTE atr_scl4 : st_scl4;
ATTRIBUTE atr_scl5 : st_scl5;
ATTRIBUTE atr_scl6 : st_scl6;
ATTRIBUTE atr_scl7 : st_scl7;
ATTRIBUTE atr_scl8 : st_scl8;
ATTRIBUTE atr_str1 : st_str1;
ATTRIBUTE atr_str2 : st_str2;
ATTRIBUTE cat_scl1 : cst_scl1;
ATTRIBUTE cat_scl2 : cst_scl2;
ATTRIBUTE cat_scl3 : cst_scl3;
ATTRIBUTE cat_scl4 : cst_scl4;
ATTRIBUTE cat_scl5 : cst_scl5;
ATTRIBUTE cat_scl6 : cst_scl6;
ATTRIBUTE cat_scl7 : cst_scl7;
ATTRIBUTE cat_scl8 : cst_scl8;
END;
USE WORK.c06s03b00x00p10n01i01010pkg.all;
ENTITY c06s03b00x00p10n01i01010ent IS
END c06s03b00x00p10n01i01010ent;
USE WORK.c06s03b00x00p10n01i01010pkg.all;
ENTITY c06s03b00x00p10n01i01010ent_a IS
GENERIC ( gene_1 : cst_scl7;
gene_2 : st_str2 );
PORT ( port_1 : cst_scl7;
port_2 : st_str2 );
--
ATTRIBUTE atr_scl1 OF port_1: SIGNAL IS TRUE;
ATTRIBUTE atr_scl2 OF port_1: SIGNAL IS '0';
ATTRIBUTE atr_scl3 OF port_1: SIGNAL IS 'z';
ATTRIBUTE atr_scl4 OF port_1: SIGNAL IS 0;
ATTRIBUTE atr_scl5 OF port_1: SIGNAL IS 10.0;
ATTRIBUTE atr_scl6 OF port_1: SIGNAL IS 10 ns;
ATTRIBUTE atr_scl7 OF port_1: SIGNAL IS 10000 pf;
ATTRIBUTE atr_scl8 OF port_1: SIGNAL IS FX;
ATTRIBUTE atr_str1 OF port_1: SIGNAL IS "signal";
ATTRIBUTE atr_str2 OF port_1: SIGNAL IS "XXXX";
--
ATTRIBUTE cat_scl1 OF port_1: SIGNAL IS TRUE;
--
ATTRIBUTE atr_scl1 OF port_2: SIGNAL IS TRUE;
ATTRIBUTE atr_str1 OF port_2: SIGNAL IS "signal";
ATTRIBUTE atr_str2 OF port_2: SIGNAL IS "XXXX";
ATTRIBUTE cat_scl1 OF port_2: SIGNAL IS TRUE;
--
ATTRIBUTE atr_scl1 OF gene_1: CONSTANT IS TRUE;
ATTRIBUTE atr_str1 OF gene_1: CONSTANT IS "signal";
ATTRIBUTE atr_str2 OF gene_1: CONSTANT IS "XXXX";
ATTRIBUTE cat_scl1 OF gene_1: CONSTANT IS TRUE;
--
ATTRIBUTE atr_scl1 OF gene_2: CONSTANT IS TRUE;
ATTRIBUTE atr_str1 OF gene_2: CONSTANT IS "signal";
ATTRIBUTE atr_str2 OF gene_2: CONSTANT IS "XXXX";
ATTRIBUTE cat_scl1 OF gene_2: CONSTANT IS TRUE;
END c06s03b00x00p10n01i01010ent_a;
-----------------------------------------------------------------------
-- ARCHITECTURAL DECLARATION
-----------------------------------------------------------------------
ARCHITECTURE c06s03b00x00p10n01i01010arch_a OF c06s03b00x00p10n01i01010ent_a IS
SIGNAL sign_1 : cst_scl7;
SIGNAL sign_2 : st_str2;
--
ATTRIBUTE atr_scl1 OF sign_1: SIGNAL IS TRUE;
ATTRIBUTE atr_scl2 OF sign_1: SIGNAL IS '0';
ATTRIBUTE atr_scl3 OF sign_1: SIGNAL IS 'z';
ATTRIBUTE atr_scl4 OF sign_1: SIGNAL IS 0;
ATTRIBUTE atr_scl5 OF sign_1: SIGNAL IS 10.0;
ATTRIBUTE atr_scl6 OF sign_1: SIGNAL IS 10 ns;
ATTRIBUTE atr_scl7 OF sign_1: SIGNAL IS 10000 pf;
ATTRIBUTE atr_scl8 OF sign_1: SIGNAL IS FX;
ATTRIBUTE atr_str1 OF sign_1: SIGNAL IS "signal";
ATTRIBUTE atr_str2 OF sign_1: SIGNAL IS "XXXX";
--
ATTRIBUTE cat_scl1 OF sign_1: SIGNAL IS TRUE;
--
ATTRIBUTE atr_scl1 OF sign_2: SIGNAL IS TRUE;
ATTRIBUTE atr_str1 OF sign_2: SIGNAL IS "signal";
ATTRIBUTE atr_str2 OF sign_2: SIGNAL IS "XXXX";
ATTRIBUTE cat_scl1 OF sign_2: SIGNAL IS TRUE;
--
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( port_1'atr_scl1 = TRUE and
port_1'atr_scl2 = '0' and
port_1'atr_scl3 = 'z' and
port_1'atr_scl4 = 0 and
port_1'atr_scl5 = 10.0 and
port_1'atr_scl6 = 10 ns and
port_1'atr_scl7 = 10000 pf and
port_1'atr_scl8 = FX and
port_1'atr_str1 = "signal" and
port_1'atr_str2 = "XXXX" and
port_1'cat_scl1 = TRUE and
port_2'atr_scl1 = TRUE and
port_2'atr_str1 = "signal" and
port_2'atr_str2 = "XXXX" and
port_2'cat_scl1 = TRUE and
gene_1'atr_scl1 = TRUE and
gene_1'atr_str1 = "signal" and
gene_1'atr_str2 = "XXXX" and
gene_1'cat_scl1 = TRUE and
gene_2'atr_scl1 = TRUE and
gene_2'atr_str1 = "signal" and
gene_2'atr_str2 = "XXXX" and
gene_2'cat_scl1 = TRUE )
report "***PASSED TEST: c06s03b00x00p10n01i01010"
severity NOTE;
assert ( port_1'atr_scl1 = TRUE and
port_1'atr_scl2 = '0' and
port_1'atr_scl3 = 'z' and
port_1'atr_scl4 = 0 and
port_1'atr_scl5 = 10.0 and
port_1'atr_scl6 = 10 ns and
port_1'atr_scl7 = 10000 pf and
port_1'atr_scl8 = FX and
port_1'atr_str1 = "signal" and
port_1'atr_str2 = "XXXX" and
port_1'cat_scl1 = TRUE and
port_2'atr_scl1 = TRUE and
port_2'atr_str1 = "signal" and
port_2'atr_str2 = "XXXX" and
port_2'cat_scl1 = TRUE and
gene_1'atr_scl1 = TRUE and
gene_1'atr_str1 = "signal" and
gene_1'atr_str2 = "XXXX" and
gene_1'cat_scl1 = TRUE and
gene_2'atr_scl1 = TRUE and
gene_2'atr_str1 = "signal" and
gene_2'atr_str2 = "XXXX" and
gene_2'cat_scl1 = TRUE )
report "***FAILED TEST: c06s03b00x00p10n01i01010 - An expanded name denotes an entity, the prefix denotes a construct that is ports, signals and generics."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p10n01i01010arch_a;
ARCHITECTURE c06s03b00x00p10n01i01010arch OF c06s03b00x00p10n01i01010ent IS
COMPONENT c06s03b00x00p10n01i01010ent_a
GENERIC ( gene_1 : cst_scl7;
gene_2 : st_str2 );
PORT ( port_1 : cst_scl7;
port_2 : st_str2 );
END COMPONENT;
FOR SUB : c06s03b00x00p10n01i01010ent_a USE ENTITY work.c06s03b00x00p10n01i01010ent_a(c06s03b00x00p10n01i01010arch_a);
SIGNAL s1 : cst_scl7;
SIGNAL s2 : st_str2;
BEGIN
SUB : c06s03b00x00p10n01i01010ent_a GENERIC MAP ( 10 pf, "ABCD" )
PORT MAP ( s1, s2 );
END c06s03b00x00p10n01i01010arch;
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