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library ieee;
use ieee.std_logic_1164.all;
library work;
use work.motor_control_pkg.all;
use work.symmetric_pwm_deadtime_pkg.all;
entity symmetric_pwm_deadtime_tb is
end symmetric_pwm_deadtime_tb;
architecture behavior of symmetric_pwm_deadtime_tb is
constant WIDTH : positive := 8;
constant T_DEAD : natural := 10; -- Deadtime in clk cycles
signal clk : std_logic := '0';
signal clk_en : std_logic := '1';
signal reset : std_logic := '1';
signal value : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');
signal pwm : half_bridge_type;
signal center : std_logic; -- Center of the 'on'-periode
signal break : std_logic := '0';
begin
clk <= not clk after 10 NS; -- 50 Mhz clock
reset <= '1', '0' after 50 NS; -- erzeugt Resetsignal
tb : process
begin
wait until falling_edge(reset);
value <= x"7F";
wait for 100 US;
value <= x"01";
wait for 100 US;
value <= x"0a";
wait for 100 US;
value <= x"FE";
wait for 100 US;
value <= x"00";
wait for 100 US;
value <= x"FF";
wait for 100 US;
end process;
tb2 : process
begin
wait until falling_edge(reset);
wait for 40 US;
break <= '1';
wait for 30 US;
break <= '0';
wait for 150 US;
break <= '1';
wait for 30 US;
break <= '0';
end process;
uut : symmetric_pwm_deadtime
generic map (
WIDTH => WIDTH,
T_DEAD => T_DEAD)
port map (
pwm_p => pwm,
center_p => center,
clk_en_p => clk_en,
value_p => value,
break_p => break,
reset => reset,
clk => clk);
end;
|
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.motor_control_pkg.all;
use work.symmetric_pwm_deadtime_pkg.all;
entity symmetric_pwm_deadtime_tb is
end symmetric_pwm_deadtime_tb;
architecture behavior of symmetric_pwm_deadtime_tb is
constant WIDTH : positive := 8;
constant T_DEAD : natural := 10; -- Deadtime in clk cycles
signal clk : std_logic := '0';
signal clk_en : std_logic := '1';
signal reset : std_logic := '1';
signal value : std_logic_vector(WIDTH - 1 downto 0) := (others => '0');
signal pwm : half_bridge_type;
signal center : std_logic; -- Center of the 'on'-periode
signal break : std_logic := '0';
begin
clk <= not clk after 10 NS; -- 50 Mhz clock
reset <= '1', '0' after 50 NS; -- erzeugt Resetsignal
tb : process
begin
wait until falling_edge(reset);
value <= x"7F";
wait for 100 US;
value <= x"01";
wait for 100 US;
value <= x"0a";
wait for 100 US;
value <= x"FE";
wait for 100 US;
value <= x"00";
wait for 100 US;
value <= x"FF";
wait for 100 US;
end process;
tb2 : process
begin
wait until falling_edge(reset);
wait for 40 US;
break <= '1';
wait for 30 US;
break <= '0';
wait for 150 US;
break <= '1';
wait for 30 US;
break <= '0';
end process;
uut : symmetric_pwm_deadtime
generic map (
WIDTH => WIDTH,
T_DEAD => T_DEAD)
port map (
pwm_p => pwm,
center_p => center,
clk_en_p => clk_en,
value_p => value,
break_p => break,
reset => reset,
clk => clk);
end;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:v_cresample:4.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY v_cresample_v4_0;
USE v_cresample_v4_0.v_cresample;
ENTITY tutorial_v_cresample_0_0 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_video_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_video_tvalid : IN STD_LOGIC;
s_axis_video_tready : OUT STD_LOGIC;
s_axis_video_tuser : IN STD_LOGIC;
s_axis_video_tlast : IN STD_LOGIC;
m_axis_video_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_video_tvalid : OUT STD_LOGIC;
m_axis_video_tready : IN STD_LOGIC;
m_axis_video_tuser : OUT STD_LOGIC;
m_axis_video_tlast : OUT STD_LOGIC
);
END tutorial_v_cresample_0_0;
ARCHITECTURE tutorial_v_cresample_0_0_arch OF tutorial_v_cresample_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_v_cresample_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT v_cresample IS
GENERIC (
C_S_AXIS_VIDEO_DATA_WIDTH : INTEGER;
C_M_AXIS_VIDEO_DATA_WIDTH : INTEGER;
C_S_AXIS_VIDEO_TDATA_WIDTH : INTEGER;
C_M_AXIS_VIDEO_TDATA_WIDTH : INTEGER;
C_S_AXIS_VIDEO_FORMAT : INTEGER;
C_M_AXIS_VIDEO_FORMAT : INTEGER;
C_S_AXI_CLK_FREQ_HZ : INTEGER;
C_HAS_AXI4_LITE : INTEGER;
C_HAS_INTC_IF : INTEGER;
C_HAS_DEBUG : INTEGER;
C_FAMILY : STRING;
C_MAX_COLS : INTEGER;
C_ACTIVE_COLS : INTEGER;
C_ACTIVE_ROWS : INTEGER;
C_CHROMA_PARITY : INTEGER;
C_FIELD_PARITY : INTEGER;
C_INTERLACED : INTEGER;
C_NUM_H_TAPS : INTEGER;
C_NUM_V_TAPS : INTEGER;
C_CONVERT_TYPE : INTEGER;
C_COEF_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aclken : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
intc_if : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
irq : OUT STD_LOGIC;
s_axis_video_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_video_tvalid : IN STD_LOGIC;
s_axis_video_tready : OUT STD_LOGIC;
s_axis_video_tuser : IN STD_LOGIC;
s_axis_video_tlast : IN STD_LOGIC;
m_axis_video_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_video_tvalid : OUT STD_LOGIC;
m_axis_video_tready : IN STD_LOGIC;
m_axis_video_tuser : OUT STD_LOGIC;
m_axis_video_tlast : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END COMPONENT v_cresample;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn_intf RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TUSER";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_video_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 video_in TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TLAST";
BEGIN
U0 : v_cresample
GENERIC MAP (
C_S_AXIS_VIDEO_DATA_WIDTH => 8,
C_M_AXIS_VIDEO_DATA_WIDTH => 8,
C_S_AXIS_VIDEO_TDATA_WIDTH => 24,
C_M_AXIS_VIDEO_TDATA_WIDTH => 16,
C_S_AXIS_VIDEO_FORMAT => 1,
C_M_AXIS_VIDEO_FORMAT => 0,
C_S_AXI_CLK_FREQ_HZ => 100000000,
C_HAS_AXI4_LITE => 0,
C_HAS_INTC_IF => 0,
C_HAS_DEBUG => 0,
C_FAMILY => "zynq",
C_MAX_COLS => 1920,
C_ACTIVE_COLS => 1920,
C_ACTIVE_ROWS => 1080,
C_CHROMA_PARITY => 1,
C_FIELD_PARITY => 1,
C_INTERLACED => 0,
C_NUM_H_TAPS => 3,
C_NUM_V_TAPS => 0,
C_CONVERT_TYPE => 2,
C_COEF_WIDTH => 16
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => aresetn,
s_axi_aclk => '0',
s_axi_aclken => '1',
s_axi_aresetn => '1',
s_axis_video_tdata => s_axis_video_tdata,
s_axis_video_tvalid => s_axis_video_tvalid,
s_axis_video_tready => s_axis_video_tready,
s_axis_video_tuser => s_axis_video_tuser,
s_axis_video_tlast => s_axis_video_tlast,
m_axis_video_tdata => m_axis_video_tdata,
m_axis_video_tvalid => m_axis_video_tvalid,
m_axis_video_tready => m_axis_video_tready,
m_axis_video_tuser => m_axis_video_tuser,
m_axis_video_tlast => m_axis_video_tlast,
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 9)),
s_axi_arvalid => '0',
s_axi_rready => '0'
);
END tutorial_v_cresample_0_0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- The operation is:
-- 1) An internal counter is initilaised to zero after a reset is received.
-- 2) An enable allows an internal running counter to count clock pulses
-- 3) A tick signal output is generated when a the number of pulses accumulated
-- are equal to a specified parameter
entity TimeBase is
generic (N: in Natural := 12; VALUE: Natural := 1999);
port(
CLOCK : in std_logic; -- input clock of 20MHz
TICK : out std_logic; -- out 1 sec timebase signal
RESET : in std_logic; -- master reset signal (active high)
ENABLE : in std_logic;
COUNT_VALUE: out std_logic_vector (N-1 downto 0)
);
end TimeBase;
architecture TimeBase_rtl of TimeBase is
signal RunningCounter : std_logic_vector(N-1 downto 0); -- this is the N bit free running counter to allow a big count
begin
RunningCounterProcess : process (CLOCK)
begin
if ( CLOCK'event and CLOCK = '1') then
if (RESET = '1') then
RunningCounter <= (others => '0');
elsif ( ENABLE = '1') then
RunningCounter <= RunningCounter + 1;
end if;
else
RunningCounter <= RunningCounter;
end if;
end process;
TICK <= '1' when (RunningCounter = VALUE) else '0';
COUNT_VALUE <= RunningCounter;
end TimeBase_rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- The operation is:
-- 1) An internal counter is initilaised to zero after a reset is received.
-- 2) An enable allows an internal running counter to count clock pulses
-- 3) A tick signal output is generated when a the number of pulses accumulated
-- are equal to a specified parameter
entity TimeBase is
generic (N: in Natural := 12; VALUE: Natural := 1999);
port(
CLOCK : in std_logic; -- input clock of 20MHz
TICK : out std_logic; -- out 1 sec timebase signal
RESET : in std_logic; -- master reset signal (active high)
ENABLE : in std_logic;
COUNT_VALUE: out std_logic_vector (N-1 downto 0)
);
end TimeBase;
architecture TimeBase_rtl of TimeBase is
signal RunningCounter : std_logic_vector(N-1 downto 0); -- this is the N bit free running counter to allow a big count
begin
RunningCounterProcess : process (CLOCK)
begin
if ( CLOCK'event and CLOCK = '1') then
if (RESET = '1') then
RunningCounter <= (others => '0');
elsif ( ENABLE = '1') then
RunningCounter <= RunningCounter + 1;
end if;
else
RunningCounter <= RunningCounter;
end if;
end process;
TICK <= '1' when (RunningCounter = VALUE) else '0';
COUNT_VALUE <= RunningCounter;
end TimeBase_rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- The operation is:
-- 1) An internal counter is initilaised to zero after a reset is received.
-- 2) An enable allows an internal running counter to count clock pulses
-- 3) A tick signal output is generated when a the number of pulses accumulated
-- are equal to a specified parameter
entity TimeBase is
generic (N: in Natural := 12; VALUE: Natural := 1999);
port(
CLOCK : in std_logic; -- input clock of 20MHz
TICK : out std_logic; -- out 1 sec timebase signal
RESET : in std_logic; -- master reset signal (active high)
ENABLE : in std_logic;
COUNT_VALUE: out std_logic_vector (N-1 downto 0)
);
end TimeBase;
architecture TimeBase_rtl of TimeBase is
signal RunningCounter : std_logic_vector(N-1 downto 0); -- this is the N bit free running counter to allow a big count
begin
RunningCounterProcess : process (CLOCK)
begin
if ( CLOCK'event and CLOCK = '1') then
if (RESET = '1') then
RunningCounter <= (others => '0');
elsif ( ENABLE = '1') then
RunningCounter <= RunningCounter + 1;
end if;
else
RunningCounter <= RunningCounter;
end if;
end process;
TICK <= '1' when (RunningCounter = VALUE) else '0';
COUNT_VALUE <= RunningCounter;
end TimeBase_rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- The operation is:
-- 1) An internal counter is initilaised to zero after a reset is received.
-- 2) An enable allows an internal running counter to count clock pulses
-- 3) A tick signal output is generated when a the number of pulses accumulated
-- are equal to a specified parameter
entity TimeBase is
generic (N: in Natural := 12; VALUE: Natural := 1999);
port(
CLOCK : in std_logic; -- input clock of 20MHz
TICK : out std_logic; -- out 1 sec timebase signal
RESET : in std_logic; -- master reset signal (active high)
ENABLE : in std_logic;
COUNT_VALUE: out std_logic_vector (N-1 downto 0)
);
end TimeBase;
architecture TimeBase_rtl of TimeBase is
signal RunningCounter : std_logic_vector(N-1 downto 0); -- this is the N bit free running counter to allow a big count
begin
RunningCounterProcess : process (CLOCK)
begin
if ( CLOCK'event and CLOCK = '1') then
if (RESET = '1') then
RunningCounter <= (others => '0');
elsif ( ENABLE = '1') then
RunningCounter <= RunningCounter + 1;
end if;
else
RunningCounter <= RunningCounter;
end if;
end process;
TICK <= '1' when (RunningCounter = VALUE) else '0';
COUNT_VALUE <= RunningCounter;
end TimeBase_rtl;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_out_one_hot_pseudo_checkers is
port ( credit: in std_logic_vector(1 downto 0);
req_X_E, req_X_N, req_X_W, req_X_S, req_X_L :in std_logic; -- From LBDR modules
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_out's FSM
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : in std_logic; -- Grants given to LBDR requests (encoded as one-hot)
state_in: in std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N,
err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W,
err_West_credit_not_zero_req_X_E_grant_E,
err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E,
err_North_req_X_E,
err_East_req_X_W,
err_West_req_X_S,
err_South_req_X_L,
err_Local_req_X_N,
err_IDLE_req_X_W,
err_North_req_X_W,
err_East_req_X_S,
err_West_req_X_L,
err_South_req_X_N,
err_Local_req_X_E,
err_IDLE_req_X_S,
err_North_req_X_S,
err_East_req_X_L,
err_West_req_X_N,
err_South_req_X_E,
err_Local_req_X_W,
err_IDLE_req_X_L,
err_North_req_X_L,
err_East_req_X_N,
err_West_req_X_E,
err_South_req_X_W,
err_Local_req_X_S,
err_state_in_onehot,
err_no_request_grants,
err_request_IDLE_state,
err_request_IDLE_not_Grants,
err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant,
err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero : out std_logic
);
end Arbiter_out_one_hot_pseudo_checkers;
architecture behavior of Arbiter_out_one_hot_pseudo_checkers is
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
SIGNAL Requests: std_logic_vector (4 downto 0);
SIGNAL Grants: std_logic_vector (4 downto 0);
begin
Requests <= req_X_N & req_X_E & req_X_W & req_X_S & req_X_L;
Grants <= grant_Y_N & grant_Y_E & grant_Y_W & grant_Y_S & grant_Y_L;
-- Checkers
--checked
process (Requests, state_in)
begin
if (Requests = "00000" and state_in /= IDLE ) then
err_Requests_state_in_state_not_equal <= '1';
else
err_Requests_state_in_state_not_equal <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 1
--checked
-- N has highest priority, then E, W, S and L (and then again N).
process (state, req_X_N, state_in)
begin
if ( state = IDLE and req_X_N = '1' and state_in /= North ) then
err_IDLE_req_X_N <= '1';
else
err_IDLE_req_X_N <= '0';
end if;
end process;
--checked
process (state, req_X_N, state_in)
begin
if (state = North and req_X_N = '1' and state_in /= North) then
err_North_req_X_N <= '1';
else
err_North_req_X_N <= '0';
end if;
end process;
--checked
process (state, credit, req_X_N, grant_Y_N)
begin
if ( state = North and credit /= "00" and req_X_N = '1' and grant_Y_N /= '1' ) then
err_North_credit_not_zero_req_X_N_grant_N <= '1';
else
err_North_credit_not_zero_req_X_N_grant_N <= '0';
end if;
end process;
--checked
process (state, credit, req_X_N, grant_Y_N)
begin
if ( state = North and (credit = "00" or req_X_N = '0') and grant_Y_N /= '0' ) then
err_North_credit_zero_or_not_req_X_N_not_grant_N <= '1';
else
err_North_credit_zero_or_not_req_X_N_not_grant_N <= '0';
end if;
end process;
--checked
process (state, req_X_E, state_in)
begin
if (state = East and req_X_E = '1' and state_in /= East) then
err_East_req_X_E <= '1';
else
err_East_req_X_E <= '0';
end if;
end process;
--checked
process (state, credit, req_X_E, grant_Y_E)
begin
if ( state = East and credit /= "00" and req_X_E = '1' and grant_Y_E = '0' ) then
err_East_credit_not_zero_req_X_E_grant_E <= '1';
else
err_East_credit_not_zero_req_X_E_grant_E <= '0';
end if;
end process;
--checked
process (state, credit, req_X_E, grant_Y_E)
begin
if ( state = East and (credit = "00" or req_X_E = '0') and grant_Y_E /= '0' ) then
err_East_credit_zero_or_not_req_X_E_not_grant_E <= '1';
else
err_East_credit_zero_or_not_req_X_E_not_grant_E <= '0';
end if;
end process;
--checked
process (state, req_X_W, state_in)
begin
if (state = West and req_X_W = '1' and state_in /= West) then
err_West_req_X_W <= '1';
else
err_West_req_X_W <= '0';
end if;
end process;
--checked
process (state, credit, req_X_W, grant_Y_W)
begin
if ( state = West and credit /= "00" and req_X_W = '1' and grant_Y_W = '0') then
err_West_credit_not_zero_req_X_E_grant_E <= '1';
else
err_West_credit_not_zero_req_X_E_grant_E <= '0';
end if;
end process;
--checked
process (state, credit, req_X_W, grant_Y_W)
begin
if ( state = West and (credit = "00" or req_X_W = '0') and grant_Y_W /= '0' ) then
err_West_credit_zero_or_not_req_X_W_not_grant_W <= '1';
else
err_West_credit_zero_or_not_req_X_W_not_grant_W <= '0';
end if;
end process;
--checked
process (state, req_X_S, state_in)
begin
if (state = South and req_X_S = '1' and state_in /= South) then
err_South_req_X_S <= '1';
else
err_South_req_X_S <= '0';
end if;
end process;
--checked
process (state, credit, req_X_S, grant_Y_S)
begin
if ( state = South and credit /= "00" and req_X_S = '1' and grant_Y_S = '0' ) then
err_South_credit_not_zero_req_X_S_grant_S <= '1';
else
err_South_credit_not_zero_req_X_S_grant_S <= '0';
end if;
end process;
--checked
process (state, credit, req_X_S, grant_Y_S)
begin
if ( state = South and (credit = "00" or req_X_S = '0') and grant_Y_S /= '0' ) then
err_South_credit_zero_or_not_req_X_S_not_grant_S <= '1';
else
err_South_credit_zero_or_not_req_X_S_not_grant_S <= '0';
end if;
end process;
--checked
-- Local is a bit different (including others case)
process (state, req_X_L, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and state_in /= Local) then
err_Local_req_X_L <= '1';
else
err_Local_req_X_L <= '0';
end if;
end process;
--checked
process (state, credit, req_X_L, grant_Y_L)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
credit /= "00" and req_X_L = '1' and grant_Y_L = '0' ) then
err_Local_credit_not_zero_req_X_L_grant_L <= '1';
else
err_Local_credit_not_zero_req_X_L_grant_L <= '0';
end if;
end process;
--checked
process (state, credit, req_X_L, grant_Y_L)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
( credit = "00" or req_X_L = '0') and grant_Y_L /= '0' ) then
err_Local_credit_zero_or_not_req_X_L_not_grant_L <= '1';
else
err_Local_credit_zero_or_not_req_X_L_not_grant_L <= '0';
end if;
end process;
-- Checked
-- Double checked!
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-- Round 2
--checked
-- IDLE
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_IDLE_req_X_E <= '1';
else
err_IDLE_req_X_E <= '0';
end if;
end process;
-- North
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_North_req_X_E <= '1';
else
err_North_req_X_E <= '0';
end if;
end process;
-- East
process (state, req_X_E, req_X_W, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_East_req_X_W <= '1';
else
err_East_req_X_W <= '0';
end if;
end process;
-- West
process (state, req_X_W, req_X_S, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_West_req_X_S <= '1';
else
err_West_req_X_S <= '0';
end if;
end process;
-- South
-- Shall I consider local for this case or the others case ? I guess local, according to the previous checkers
-- for the router with CTS/RTS handshaking Flow Control
process (state, req_X_S, req_X_L, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_South_req_X_L <= '1';
else
err_South_req_X_L <= '0';
end if;
end process;
-- Local and invalid states (others case)
process (state, req_X_L, req_X_N, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_Local_req_X_N <= '1';
else
err_Local_req_X_N <= '0';
end if;
end process;
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-- Round 3
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_IDLE_req_X_W <= '1';
else
err_IDLE_req_X_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_North_req_X_W <= '1';
else
err_North_req_X_W <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, state_in)
begin
if (state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_East_req_X_S <= '1';
else
err_East_req_X_S <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, state_in)
begin
if (state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_West_req_X_L <= '1';
else
err_West_req_X_L <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, state_in)
begin
if (state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_South_req_X_N <= '1';
else
err_South_req_X_N <= '0';
end if;
end process;
-- Local and invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, state_in)
begin
if (state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_Local_req_X_E <= '1';
else
err_Local_req_X_E <= '0';
end if;
end process;
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-- Round 4
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_IDLE_req_X_S <= '1';
else
err_IDLE_req_X_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_North_req_X_S <= '1';
else
err_North_req_X_S <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
state_in /= Local) then
err_East_req_X_L <= '1';
else
err_East_req_X_L <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_West_req_X_N <= '1';
else
err_West_req_X_N <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_South_req_X_E <= '1';
else
err_South_req_X_E <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_Local_req_X_W <= '1';
else
err_Local_req_X_W <= '0';
end if;
end process;
-- Checked
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-- Round 5
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_IDLE_req_X_L <= '1';
else
err_IDLE_req_X_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_North_req_X_L <= '1';
else
err_North_req_X_L <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_East_req_X_N <= '1';
else
err_East_req_X_N <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_West_req_X_E <= '1';
else
err_West_req_X_E <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_South_req_X_W <= '1';
else
err_South_req_X_W <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_Local_req_X_S <= '1';
else
err_Local_req_X_S <= '0';
end if;
end process;
-- Checked
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process (state_in)
begin
if (state_in /= IDLE and state_in /= North and state_in /= East and state_in /= West and
state_in /= South and state_in /= Local) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
-- Checked
process (Requests, Grants)
begin
if ( Requests = "00000" and Grants /= "00000") then
err_no_request_grants <= '1';
else
err_no_request_grants <= '0';
end if;
end process;
-- Checked
process (Requests, state_in)
begin
if (Requests /= "00000" and state_in = IDLE) then
err_request_IDLE_state <= '1';
else
err_request_IDLE_state <= '0';
end if;
end process;
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process (state, Grants)
begin
if (state = IDLE and Grants /= "00000") then
err_request_IDLE_not_Grants <= '1';
else
err_request_IDLE_not_Grants <= '0';
end if;
end process;
process (state, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L)
begin
if (state = North and (grant_Y_E = '1' or grant_Y_W = '1' or grant_Y_S = '1' or grant_Y_L = '1') ) then
err_state_North_Invalid_Grant <= '1';
else
err_state_North_Invalid_Grant <= '0';
end if;
end process;
process (state, grant_Y_N, grant_Y_W, grant_Y_S, grant_Y_L)
begin
if (state = East and (grant_Y_N = '1' or grant_Y_W = '1' or grant_Y_S = '1' or grant_Y_L = '1') ) then
err_state_East_Invalid_Grant <= '1';
else
err_state_East_Invalid_Grant <= '0';
end if;
end process;
process (state, grant_Y_N, grant_Y_E, grant_Y_S, grant_Y_L)
begin
if (state = West and (grant_Y_N = '1' or grant_Y_E = '1' or grant_Y_S = '1' or grant_Y_L = '1') ) then
err_state_West_Invalid_Grant <= '1';
else
err_state_West_Invalid_Grant <= '0';
end if;
end process;
process (state, grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_L)
begin
if (state = South and (grant_Y_N = '1' or grant_Y_E = '1' or grant_Y_W = '1' or grant_Y_L = '1') ) then
err_state_South_Invalid_Grant <= '1';
else
err_state_South_Invalid_Grant <= '0';
end if;
end process;
-- Local or invalid state(s) (a bit different logic!)
process (state, grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S)
begin
if (state /= IDLE and state /= North and state /= East and state /= West and state /= South and
(grant_Y_N = '1' or grant_Y_E = '1' or grant_Y_W = '1' or grant_Y_S = '1') ) then
err_state_Local_Invalid_Grant <= '1';
else
err_state_Local_Invalid_Grant <= '0';
end if;
end process;
-- Because we do not have multi-casting, Grants must always be one-hot or all zeros, no other possible combination for them !
process (Grants)
begin
if (Grants /= "00000" and Grants /= "00001" and Grants /= "00010" and Grants /= "00100" and Grants /= "01000" and Grants /= "10000") then
err_Grants_onehot_or_all_zero <= '1';
else
err_Grants_onehot_or_all_zero <= '0';
end if;
end process;
end behavior; |
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_out_one_hot_pseudo_checkers is
port ( credit: in std_logic_vector(1 downto 0);
req_X_E, req_X_N, req_X_W, req_X_S, req_X_L :in std_logic; -- From LBDR modules
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_out's FSM
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : in std_logic; -- Grants given to LBDR requests (encoded as one-hot)
state_in: in std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N,
err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W,
err_West_credit_not_zero_req_X_E_grant_E,
err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E,
err_North_req_X_E,
err_East_req_X_W,
err_West_req_X_S,
err_South_req_X_L,
err_Local_req_X_N,
err_IDLE_req_X_W,
err_North_req_X_W,
err_East_req_X_S,
err_West_req_X_L,
err_South_req_X_N,
err_Local_req_X_E,
err_IDLE_req_X_S,
err_North_req_X_S,
err_East_req_X_L,
err_West_req_X_N,
err_South_req_X_E,
err_Local_req_X_W,
err_IDLE_req_X_L,
err_North_req_X_L,
err_East_req_X_N,
err_West_req_X_E,
err_South_req_X_W,
err_Local_req_X_S,
err_state_in_onehot,
err_no_request_grants,
err_request_IDLE_state,
err_request_IDLE_not_Grants,
err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant,
err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero : out std_logic
);
end Arbiter_out_one_hot_pseudo_checkers;
architecture behavior of Arbiter_out_one_hot_pseudo_checkers is
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
SIGNAL Requests: std_logic_vector (4 downto 0);
SIGNAL Grants: std_logic_vector (4 downto 0);
begin
Requests <= req_X_N & req_X_E & req_X_W & req_X_S & req_X_L;
Grants <= grant_Y_N & grant_Y_E & grant_Y_W & grant_Y_S & grant_Y_L;
-- Checkers
--checked
process (Requests, state_in)
begin
if (Requests = "00000" and state_in /= IDLE ) then
err_Requests_state_in_state_not_equal <= '1';
else
err_Requests_state_in_state_not_equal <= '0';
end if;
end process;
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-- Round 1
--checked
-- N has highest priority, then E, W, S and L (and then again N).
process (state, req_X_N, state_in)
begin
if ( state = IDLE and req_X_N = '1' and state_in /= North ) then
err_IDLE_req_X_N <= '1';
else
err_IDLE_req_X_N <= '0';
end if;
end process;
--checked
process (state, req_X_N, state_in)
begin
if (state = North and req_X_N = '1' and state_in /= North) then
err_North_req_X_N <= '1';
else
err_North_req_X_N <= '0';
end if;
end process;
--checked
process (state, credit, req_X_N, grant_Y_N)
begin
if ( state = North and credit /= "00" and req_X_N = '1' and grant_Y_N /= '1' ) then
err_North_credit_not_zero_req_X_N_grant_N <= '1';
else
err_North_credit_not_zero_req_X_N_grant_N <= '0';
end if;
end process;
--checked
process (state, credit, req_X_N, grant_Y_N)
begin
if ( state = North and (credit = "00" or req_X_N = '0') and grant_Y_N /= '0' ) then
err_North_credit_zero_or_not_req_X_N_not_grant_N <= '1';
else
err_North_credit_zero_or_not_req_X_N_not_grant_N <= '0';
end if;
end process;
--checked
process (state, req_X_E, state_in)
begin
if (state = East and req_X_E = '1' and state_in /= East) then
err_East_req_X_E <= '1';
else
err_East_req_X_E <= '0';
end if;
end process;
--checked
process (state, credit, req_X_E, grant_Y_E)
begin
if ( state = East and credit /= "00" and req_X_E = '1' and grant_Y_E = '0' ) then
err_East_credit_not_zero_req_X_E_grant_E <= '1';
else
err_East_credit_not_zero_req_X_E_grant_E <= '0';
end if;
end process;
--checked
process (state, credit, req_X_E, grant_Y_E)
begin
if ( state = East and (credit = "00" or req_X_E = '0') and grant_Y_E /= '0' ) then
err_East_credit_zero_or_not_req_X_E_not_grant_E <= '1';
else
err_East_credit_zero_or_not_req_X_E_not_grant_E <= '0';
end if;
end process;
--checked
process (state, req_X_W, state_in)
begin
if (state = West and req_X_W = '1' and state_in /= West) then
err_West_req_X_W <= '1';
else
err_West_req_X_W <= '0';
end if;
end process;
--checked
process (state, credit, req_X_W, grant_Y_W)
begin
if ( state = West and credit /= "00" and req_X_W = '1' and grant_Y_W = '0') then
err_West_credit_not_zero_req_X_E_grant_E <= '1';
else
err_West_credit_not_zero_req_X_E_grant_E <= '0';
end if;
end process;
--checked
process (state, credit, req_X_W, grant_Y_W)
begin
if ( state = West and (credit = "00" or req_X_W = '0') and grant_Y_W /= '0' ) then
err_West_credit_zero_or_not_req_X_W_not_grant_W <= '1';
else
err_West_credit_zero_or_not_req_X_W_not_grant_W <= '0';
end if;
end process;
--checked
process (state, req_X_S, state_in)
begin
if (state = South and req_X_S = '1' and state_in /= South) then
err_South_req_X_S <= '1';
else
err_South_req_X_S <= '0';
end if;
end process;
--checked
process (state, credit, req_X_S, grant_Y_S)
begin
if ( state = South and credit /= "00" and req_X_S = '1' and grant_Y_S = '0' ) then
err_South_credit_not_zero_req_X_S_grant_S <= '1';
else
err_South_credit_not_zero_req_X_S_grant_S <= '0';
end if;
end process;
--checked
process (state, credit, req_X_S, grant_Y_S)
begin
if ( state = South and (credit = "00" or req_X_S = '0') and grant_Y_S /= '0' ) then
err_South_credit_zero_or_not_req_X_S_not_grant_S <= '1';
else
err_South_credit_zero_or_not_req_X_S_not_grant_S <= '0';
end if;
end process;
--checked
-- Local is a bit different (including others case)
process (state, req_X_L, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and state_in /= Local) then
err_Local_req_X_L <= '1';
else
err_Local_req_X_L <= '0';
end if;
end process;
--checked
process (state, credit, req_X_L, grant_Y_L)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
credit /= "00" and req_X_L = '1' and grant_Y_L = '0' ) then
err_Local_credit_not_zero_req_X_L_grant_L <= '1';
else
err_Local_credit_not_zero_req_X_L_grant_L <= '0';
end if;
end process;
--checked
process (state, credit, req_X_L, grant_Y_L)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
( credit = "00" or req_X_L = '0') and grant_Y_L /= '0' ) then
err_Local_credit_zero_or_not_req_X_L_not_grant_L <= '1';
else
err_Local_credit_zero_or_not_req_X_L_not_grant_L <= '0';
end if;
end process;
-- Checked
-- Double checked!
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-- Round 2
--checked
-- IDLE
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_IDLE_req_X_E <= '1';
else
err_IDLE_req_X_E <= '0';
end if;
end process;
-- North
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_North_req_X_E <= '1';
else
err_North_req_X_E <= '0';
end if;
end process;
-- East
process (state, req_X_E, req_X_W, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_East_req_X_W <= '1';
else
err_East_req_X_W <= '0';
end if;
end process;
-- West
process (state, req_X_W, req_X_S, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_West_req_X_S <= '1';
else
err_West_req_X_S <= '0';
end if;
end process;
-- South
-- Shall I consider local for this case or the others case ? I guess local, according to the previous checkers
-- for the router with CTS/RTS handshaking Flow Control
process (state, req_X_S, req_X_L, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_South_req_X_L <= '1';
else
err_South_req_X_L <= '0';
end if;
end process;
-- Local and invalid states (others case)
process (state, req_X_L, req_X_N, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_Local_req_X_N <= '1';
else
err_Local_req_X_N <= '0';
end if;
end process;
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-- Round 3
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_IDLE_req_X_W <= '1';
else
err_IDLE_req_X_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_North_req_X_W <= '1';
else
err_North_req_X_W <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, state_in)
begin
if (state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_East_req_X_S <= '1';
else
err_East_req_X_S <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, state_in)
begin
if (state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_West_req_X_L <= '1';
else
err_West_req_X_L <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, state_in)
begin
if (state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_South_req_X_N <= '1';
else
err_South_req_X_N <= '0';
end if;
end process;
-- Local and invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, state_in)
begin
if (state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_Local_req_X_E <= '1';
else
err_Local_req_X_E <= '0';
end if;
end process;
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-- Round 4
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_IDLE_req_X_S <= '1';
else
err_IDLE_req_X_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_North_req_X_S <= '1';
else
err_North_req_X_S <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
state_in /= Local) then
err_East_req_X_L <= '1';
else
err_East_req_X_L <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_West_req_X_N <= '1';
else
err_West_req_X_N <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_South_req_X_E <= '1';
else
err_South_req_X_E <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_Local_req_X_W <= '1';
else
err_Local_req_X_W <= '0';
end if;
end process;
-- Checked
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-- Round 5
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_IDLE_req_X_L <= '1';
else
err_IDLE_req_X_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_North_req_X_L <= '1';
else
err_North_req_X_L <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_East_req_X_N <= '1';
else
err_East_req_X_N <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_West_req_X_E <= '1';
else
err_West_req_X_E <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_South_req_X_W <= '1';
else
err_South_req_X_W <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_Local_req_X_S <= '1';
else
err_Local_req_X_S <= '0';
end if;
end process;
-- Checked
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process (state_in)
begin
if (state_in /= IDLE and state_in /= North and state_in /= East and state_in /= West and
state_in /= South and state_in /= Local) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
-- Checked
process (Requests, Grants)
begin
if ( Requests = "00000" and Grants /= "00000") then
err_no_request_grants <= '1';
else
err_no_request_grants <= '0';
end if;
end process;
-- Checked
process (Requests, state_in)
begin
if (Requests /= "00000" and state_in = IDLE) then
err_request_IDLE_state <= '1';
else
err_request_IDLE_state <= '0';
end if;
end process;
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process (state, Grants)
begin
if (state = IDLE and Grants /= "00000") then
err_request_IDLE_not_Grants <= '1';
else
err_request_IDLE_not_Grants <= '0';
end if;
end process;
process (state, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L)
begin
if (state = North and (grant_Y_E = '1' or grant_Y_W = '1' or grant_Y_S = '1' or grant_Y_L = '1') ) then
err_state_North_Invalid_Grant <= '1';
else
err_state_North_Invalid_Grant <= '0';
end if;
end process;
process (state, grant_Y_N, grant_Y_W, grant_Y_S, grant_Y_L)
begin
if (state = East and (grant_Y_N = '1' or grant_Y_W = '1' or grant_Y_S = '1' or grant_Y_L = '1') ) then
err_state_East_Invalid_Grant <= '1';
else
err_state_East_Invalid_Grant <= '0';
end if;
end process;
process (state, grant_Y_N, grant_Y_E, grant_Y_S, grant_Y_L)
begin
if (state = West and (grant_Y_N = '1' or grant_Y_E = '1' or grant_Y_S = '1' or grant_Y_L = '1') ) then
err_state_West_Invalid_Grant <= '1';
else
err_state_West_Invalid_Grant <= '0';
end if;
end process;
process (state, grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_L)
begin
if (state = South and (grant_Y_N = '1' or grant_Y_E = '1' or grant_Y_W = '1' or grant_Y_L = '1') ) then
err_state_South_Invalid_Grant <= '1';
else
err_state_South_Invalid_Grant <= '0';
end if;
end process;
-- Local or invalid state(s) (a bit different logic!)
process (state, grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S)
begin
if (state /= IDLE and state /= North and state /= East and state /= West and state /= South and
(grant_Y_N = '1' or grant_Y_E = '1' or grant_Y_W = '1' or grant_Y_S = '1') ) then
err_state_Local_Invalid_Grant <= '1';
else
err_state_Local_Invalid_Grant <= '0';
end if;
end process;
-- Because we do not have multi-casting, Grants must always be one-hot or all zeros, no other possible combination for them !
process (Grants)
begin
if (Grants /= "00000" and Grants /= "00001" and Grants /= "00010" and Grants /= "00100" and Grants /= "01000" and Grants /= "10000") then
err_Grants_onehot_or_all_zero <= '1';
else
err_Grants_onehot_or_all_zero <= '0';
end if;
end process;
end behavior; |
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Arbiter_out_one_hot_pseudo_checkers is
port ( credit: in std_logic_vector(1 downto 0);
req_X_E, req_X_N, req_X_W, req_X_S, req_X_L :in std_logic; -- From LBDR modules
state: in std_logic_vector (5 downto 0); -- 6 states for Arbiter_out's FSM
grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L : in std_logic; -- Grants given to LBDR requests (encoded as one-hot)
state_in: in std_logic_vector (5 downto 0); -- 6 states for Arbiter's FSM
-- Checker outputs
err_Requests_state_in_state_not_equal,
err_IDLE_req_X_N,
err_North_req_X_N,
err_North_credit_not_zero_req_X_N_grant_N,
err_North_credit_zero_or_not_req_X_N_not_grant_N,
err_East_req_X_E,
err_East_credit_not_zero_req_X_E_grant_E,
err_East_credit_zero_or_not_req_X_E_not_grant_E,
err_West_req_X_W,
err_West_credit_not_zero_req_X_E_grant_E,
err_West_credit_zero_or_not_req_X_W_not_grant_W,
err_South_req_X_S,
err_South_credit_not_zero_req_X_S_grant_S,
err_South_credit_zero_or_not_req_X_S_not_grant_S,
err_Local_req_X_L,
err_Local_credit_not_zero_req_X_L_grant_L,
err_Local_credit_zero_or_not_req_X_L_not_grant_L,
err_IDLE_req_X_E,
err_North_req_X_E,
err_East_req_X_W,
err_West_req_X_S,
err_South_req_X_L,
err_Local_req_X_N,
err_IDLE_req_X_W,
err_North_req_X_W,
err_East_req_X_S,
err_West_req_X_L,
err_South_req_X_N,
err_Local_req_X_E,
err_IDLE_req_X_S,
err_North_req_X_S,
err_East_req_X_L,
err_West_req_X_N,
err_South_req_X_E,
err_Local_req_X_W,
err_IDLE_req_X_L,
err_North_req_X_L,
err_East_req_X_N,
err_West_req_X_E,
err_South_req_X_W,
err_Local_req_X_S,
err_state_in_onehot,
err_no_request_grants,
err_request_IDLE_state,
err_request_IDLE_not_Grants,
err_state_North_Invalid_Grant,
err_state_East_Invalid_Grant,
err_state_West_Invalid_Grant,
err_state_South_Invalid_Grant,
err_state_Local_Invalid_Grant,
err_Grants_onehot_or_all_zero : out std_logic
);
end Arbiter_out_one_hot_pseudo_checkers;
architecture behavior of Arbiter_out_one_hot_pseudo_checkers is
CONSTANT IDLE: std_logic_vector (5 downto 0) := "000001";
CONSTANT Local: std_logic_vector (5 downto 0) := "000010";
CONSTANT North: std_logic_vector (5 downto 0) := "000100";
CONSTANT East: std_logic_vector (5 downto 0) := "001000";
CONSTANT West: std_logic_vector (5 downto 0) := "010000";
CONSTANT South: std_logic_vector (5 downto 0) := "100000";
SIGNAL Requests: std_logic_vector (4 downto 0);
SIGNAL Grants: std_logic_vector (4 downto 0);
begin
Requests <= req_X_N & req_X_E & req_X_W & req_X_S & req_X_L;
Grants <= grant_Y_N & grant_Y_E & grant_Y_W & grant_Y_S & grant_Y_L;
-- Checkers
--checked
process (Requests, state_in)
begin
if (Requests = "00000" and state_in /= IDLE ) then
err_Requests_state_in_state_not_equal <= '1';
else
err_Requests_state_in_state_not_equal <= '0';
end if;
end process;
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-- Round 1
--checked
-- N has highest priority, then E, W, S and L (and then again N).
process (state, req_X_N, state_in)
begin
if ( state = IDLE and req_X_N = '1' and state_in /= North ) then
err_IDLE_req_X_N <= '1';
else
err_IDLE_req_X_N <= '0';
end if;
end process;
--checked
process (state, req_X_N, state_in)
begin
if (state = North and req_X_N = '1' and state_in /= North) then
err_North_req_X_N <= '1';
else
err_North_req_X_N <= '0';
end if;
end process;
--checked
process (state, credit, req_X_N, grant_Y_N)
begin
if ( state = North and credit /= "00" and req_X_N = '1' and grant_Y_N /= '1' ) then
err_North_credit_not_zero_req_X_N_grant_N <= '1';
else
err_North_credit_not_zero_req_X_N_grant_N <= '0';
end if;
end process;
--checked
process (state, credit, req_X_N, grant_Y_N)
begin
if ( state = North and (credit = "00" or req_X_N = '0') and grant_Y_N /= '0' ) then
err_North_credit_zero_or_not_req_X_N_not_grant_N <= '1';
else
err_North_credit_zero_or_not_req_X_N_not_grant_N <= '0';
end if;
end process;
--checked
process (state, req_X_E, state_in)
begin
if (state = East and req_X_E = '1' and state_in /= East) then
err_East_req_X_E <= '1';
else
err_East_req_X_E <= '0';
end if;
end process;
--checked
process (state, credit, req_X_E, grant_Y_E)
begin
if ( state = East and credit /= "00" and req_X_E = '1' and grant_Y_E = '0' ) then
err_East_credit_not_zero_req_X_E_grant_E <= '1';
else
err_East_credit_not_zero_req_X_E_grant_E <= '0';
end if;
end process;
--checked
process (state, credit, req_X_E, grant_Y_E)
begin
if ( state = East and (credit = "00" or req_X_E = '0') and grant_Y_E /= '0' ) then
err_East_credit_zero_or_not_req_X_E_not_grant_E <= '1';
else
err_East_credit_zero_or_not_req_X_E_not_grant_E <= '0';
end if;
end process;
--checked
process (state, req_X_W, state_in)
begin
if (state = West and req_X_W = '1' and state_in /= West) then
err_West_req_X_W <= '1';
else
err_West_req_X_W <= '0';
end if;
end process;
--checked
process (state, credit, req_X_W, grant_Y_W)
begin
if ( state = West and credit /= "00" and req_X_W = '1' and grant_Y_W = '0') then
err_West_credit_not_zero_req_X_E_grant_E <= '1';
else
err_West_credit_not_zero_req_X_E_grant_E <= '0';
end if;
end process;
--checked
process (state, credit, req_X_W, grant_Y_W)
begin
if ( state = West and (credit = "00" or req_X_W = '0') and grant_Y_W /= '0' ) then
err_West_credit_zero_or_not_req_X_W_not_grant_W <= '1';
else
err_West_credit_zero_or_not_req_X_W_not_grant_W <= '0';
end if;
end process;
--checked
process (state, req_X_S, state_in)
begin
if (state = South and req_X_S = '1' and state_in /= South) then
err_South_req_X_S <= '1';
else
err_South_req_X_S <= '0';
end if;
end process;
--checked
process (state, credit, req_X_S, grant_Y_S)
begin
if ( state = South and credit /= "00" and req_X_S = '1' and grant_Y_S = '0' ) then
err_South_credit_not_zero_req_X_S_grant_S <= '1';
else
err_South_credit_not_zero_req_X_S_grant_S <= '0';
end if;
end process;
--checked
process (state, credit, req_X_S, grant_Y_S)
begin
if ( state = South and (credit = "00" or req_X_S = '0') and grant_Y_S /= '0' ) then
err_South_credit_zero_or_not_req_X_S_not_grant_S <= '1';
else
err_South_credit_zero_or_not_req_X_S_not_grant_S <= '0';
end if;
end process;
--checked
-- Local is a bit different (including others case)
process (state, req_X_L, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
req_X_L = '1' and state_in /= Local) then
err_Local_req_X_L <= '1';
else
err_Local_req_X_L <= '0';
end if;
end process;
--checked
process (state, credit, req_X_L, grant_Y_L)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
credit /= "00" and req_X_L = '1' and grant_Y_L = '0' ) then
err_Local_credit_not_zero_req_X_L_grant_L <= '1';
else
err_Local_credit_not_zero_req_X_L_grant_L <= '0';
end if;
end process;
--checked
process (state, credit, req_X_L, grant_Y_L)
begin
if ( state /= IDLE and state /= North and state /=East and state /= West and state /= South and
( credit = "00" or req_X_L = '0') and grant_Y_L /= '0' ) then
err_Local_credit_zero_or_not_req_X_L_not_grant_L <= '1';
else
err_Local_credit_zero_or_not_req_X_L_not_grant_L <= '0';
end if;
end process;
-- Checked
-- Double checked!
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 2
--checked
-- IDLE
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_IDLE_req_X_E <= '1';
else
err_IDLE_req_X_E <= '0';
end if;
end process;
-- North
process (state, req_X_N, req_X_E, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_North_req_X_E <= '1';
else
err_North_req_X_E <= '0';
end if;
end process;
-- East
process (state, req_X_E, req_X_W, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_East_req_X_W <= '1';
else
err_East_req_X_W <= '0';
end if;
end process;
-- West
process (state, req_X_W, req_X_S, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_West_req_X_S <= '1';
else
err_West_req_X_S <= '0';
end if;
end process;
-- South
-- Shall I consider local for this case or the others case ? I guess local, according to the previous checkers
-- for the router with CTS/RTS handshaking Flow Control
process (state, req_X_S, req_X_L, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_South_req_X_L <= '1';
else
err_South_req_X_L <= '0';
end if;
end process;
-- Local and invalid states (others case)
process (state, req_X_L, req_X_N, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_Local_req_X_N <= '1';
else
err_Local_req_X_N <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 3
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_IDLE_req_X_W <= '1';
else
err_IDLE_req_X_W <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, state_in)
begin
if (state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and state_in /= West) then
err_North_req_X_W <= '1';
else
err_North_req_X_W <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, state_in)
begin
if (state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and state_in /= South) then
err_East_req_X_S <= '1';
else
err_East_req_X_S <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, state_in)
begin
if (state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and state_in /= Local) then
err_West_req_X_L <= '1';
else
err_West_req_X_L <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, state_in)
begin
if (state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and state_in /= North) then
err_South_req_X_N <= '1';
else
err_South_req_X_N <= '0';
end if;
end process;
-- Local and invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, state_in)
begin
if (state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and state_in /= East) then
err_Local_req_X_E <= '1';
else
err_Local_req_X_E <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 4
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_IDLE_req_X_S <= '1';
else
err_IDLE_req_X_S <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_North_req_X_S <= '1';
else
err_North_req_X_S <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1' and
state_in /= Local) then
err_East_req_X_L <= '1';
else
err_East_req_X_L <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_West_req_X_N <= '1';
else
err_West_req_X_N <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_South_req_X_E <= '1';
else
err_South_req_X_E <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_Local_req_X_W <= '1';
else
err_Local_req_X_W <= '0';
end if;
end process;
-- Checked
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-- Round 5
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = IDLE and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_IDLE_req_X_L <= '1';
else
err_IDLE_req_X_L <= '0';
end if;
end process;
process (state, req_X_N, req_X_E, req_X_W, req_X_S, req_X_L, state_in)
begin
if ( state = North and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '1'
and state_in /= Local) then
err_North_req_X_L <= '1';
else
err_North_req_X_L <= '0';
end if;
end process;
process (state, req_X_E, req_X_W, req_X_S, req_X_L, req_X_N, state_in)
begin
if ( state = East and req_X_E = '0' and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '1' and
state_in /= North) then
err_East_req_X_N <= '1';
else
err_East_req_X_N <= '0';
end if;
end process;
process (state, req_X_W, req_X_S, req_X_L, req_X_N, req_X_E, state_in)
begin
if ( state = West and req_X_W = '0' and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '1' and
state_in /= East) then
err_West_req_X_E <= '1';
else
err_West_req_X_E <= '0';
end if;
end process;
process (state, req_X_S, req_X_L, req_X_N, req_X_E, req_X_W, state_in)
begin
if ( state = South and req_X_S = '0' and req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '1' and
state_in /= West) then
err_South_req_X_W <= '1';
else
err_South_req_X_W <= '0';
end if;
end process;
-- Local state or invalid state(s) (others case)
process (state, req_X_L, req_X_N, req_X_E, req_X_W, req_X_S, state_in)
begin
if ( state /= IDLE and state /= North and state /=East and state /=West and state /= South and
req_X_L = '0' and req_X_N = '0' and req_X_E = '0' and req_X_W = '0' and req_X_S = '1' and
state_in /= South) then
err_Local_req_X_S <= '1';
else
err_Local_req_X_S <= '0';
end if;
end process;
-- Checked
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
process (state_in)
begin
if (state_in /= IDLE and state_in /= North and state_in /= East and state_in /= West and
state_in /= South and state_in /= Local) then
err_state_in_onehot <= '1';
else
err_state_in_onehot <= '0';
end if;
end process;
-- Checked
process (Requests, Grants)
begin
if ( Requests = "00000" and Grants /= "00000") then
err_no_request_grants <= '1';
else
err_no_request_grants <= '0';
end if;
end process;
-- Checked
process (Requests, state_in)
begin
if (Requests /= "00000" and state_in = IDLE) then
err_request_IDLE_state <= '1';
else
err_request_IDLE_state <= '0';
end if;
end process;
-----------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------
process (state, Grants)
begin
if (state = IDLE and Grants /= "00000") then
err_request_IDLE_not_Grants <= '1';
else
err_request_IDLE_not_Grants <= '0';
end if;
end process;
process (state, grant_Y_E, grant_Y_W, grant_Y_S, grant_Y_L)
begin
if (state = North and (grant_Y_E = '1' or grant_Y_W = '1' or grant_Y_S = '1' or grant_Y_L = '1') ) then
err_state_North_Invalid_Grant <= '1';
else
err_state_North_Invalid_Grant <= '0';
end if;
end process;
process (state, grant_Y_N, grant_Y_W, grant_Y_S, grant_Y_L)
begin
if (state = East and (grant_Y_N = '1' or grant_Y_W = '1' or grant_Y_S = '1' or grant_Y_L = '1') ) then
err_state_East_Invalid_Grant <= '1';
else
err_state_East_Invalid_Grant <= '0';
end if;
end process;
process (state, grant_Y_N, grant_Y_E, grant_Y_S, grant_Y_L)
begin
if (state = West and (grant_Y_N = '1' or grant_Y_E = '1' or grant_Y_S = '1' or grant_Y_L = '1') ) then
err_state_West_Invalid_Grant <= '1';
else
err_state_West_Invalid_Grant <= '0';
end if;
end process;
process (state, grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_L)
begin
if (state = South and (grant_Y_N = '1' or grant_Y_E = '1' or grant_Y_W = '1' or grant_Y_L = '1') ) then
err_state_South_Invalid_Grant <= '1';
else
err_state_South_Invalid_Grant <= '0';
end if;
end process;
-- Local or invalid state(s) (a bit different logic!)
process (state, grant_Y_N, grant_Y_E, grant_Y_W, grant_Y_S)
begin
if (state /= IDLE and state /= North and state /= East and state /= West and state /= South and
(grant_Y_N = '1' or grant_Y_E = '1' or grant_Y_W = '1' or grant_Y_S = '1') ) then
err_state_Local_Invalid_Grant <= '1';
else
err_state_Local_Invalid_Grant <= '0';
end if;
end process;
-- Because we do not have multi-casting, Grants must always be one-hot or all zeros, no other possible combination for them !
process (Grants)
begin
if (Grants /= "00000" and Grants /= "00001" and Grants /= "00010" and Grants /= "00100" and Grants /= "01000" and Grants /= "10000") then
err_Grants_onehot_or_all_zero <= '1';
else
err_Grants_onehot_or_all_zero <= '0';
end if;
end process;
end behavior; |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_2;
USE floating_point_v7_1_2.floating_point_v7_1_2;
ENTITY doHistStretch_ap_fdiv_14_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END doHistStretch_ap_fdiv_14_no_dsp_32;
ARCHITECTURE doHistStretch_ap_fdiv_14_no_dsp_32_arch OF doHistStretch_ap_fdiv_14_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF doHistStretch_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_2 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_2;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_2
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 14,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END doHistStretch_ap_fdiv_14_no_dsp_32_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_2;
USE floating_point_v7_1_2.floating_point_v7_1_2;
ENTITY doHistStretch_ap_fdiv_14_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END doHistStretch_ap_fdiv_14_no_dsp_32;
ARCHITECTURE doHistStretch_ap_fdiv_14_no_dsp_32_arch OF doHistStretch_ap_fdiv_14_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF doHistStretch_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_2 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_2;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_2
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 14,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END doHistStretch_ap_fdiv_14_no_dsp_32_arch;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_pas-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavioral of product_adder_subtracter is
begin
behavior : process (a, b) is
constant Tpd_in_out : time := 3 ns;
variable op2 : std_ulogic_vector(b'range);
variable carry_in : std_ulogic;
variable carry_out : std_ulogic;
begin
carry_out := To_X01(mode);
if To_X01(mode) = '1' then
op2 := not b;
else
op2 := b;
end if;
for index in 0 to 31 loop
carry_in := carry_out; -- of previous bit
s(index) <= a(index) xor op2(index) xor carry_in after Tpd_in_out;
carry_out := (a(index) and op2(index))
or (carry_in and (a(index) xor op2(index)));
end loop;
s(32) <= a(31) xor op2(31) xor carry_out after Tpd_in_out;
end process behavior;
end architecture behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_pas-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavioral of product_adder_subtracter is
begin
behavior : process (a, b) is
constant Tpd_in_out : time := 3 ns;
variable op2 : std_ulogic_vector(b'range);
variable carry_in : std_ulogic;
variable carry_out : std_ulogic;
begin
carry_out := To_X01(mode);
if To_X01(mode) = '1' then
op2 := not b;
else
op2 := b;
end if;
for index in 0 to 31 loop
carry_in := carry_out; -- of previous bit
s(index) <= a(index) xor op2(index) xor carry_in after Tpd_in_out;
carry_out := (a(index) and op2(index))
or (carry_in and (a(index) xor op2(index)));
end loop;
s(32) <= a(31) xor op2(31) xor carry_out after Tpd_in_out;
end process behavior;
end architecture behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_pas-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavioral of product_adder_subtracter is
begin
behavior : process (a, b) is
constant Tpd_in_out : time := 3 ns;
variable op2 : std_ulogic_vector(b'range);
variable carry_in : std_ulogic;
variable carry_out : std_ulogic;
begin
carry_out := To_X01(mode);
if To_X01(mode) = '1' then
op2 := not b;
else
op2 := b;
end if;
for index in 0 to 31 loop
carry_in := carry_out; -- of previous bit
s(index) <= a(index) xor op2(index) xor carry_in after Tpd_in_out;
carry_out := (a(index) and op2(index))
or (carry_in and (a(index) xor op2(index)));
end loop;
s(32) <= a(31) xor op2(31) xor carry_out after Tpd_in_out;
end process behavior;
end architecture behavioral;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: PS/2 Ascii Generator
-- Project Name: Keyboard Controller
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Generate ASCII from PS/2 input
-- Maintain Keyboard(reset,set num,caps lock)
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity PS2_ASCII_GEN is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
PS2_RX : in STD_LOGIC_VECTOR (7 downto 0);
PS2_RD : in STD_LOGIC;
PS2_BS : in STD_LOGIC;
PS2_ER : in STD_LOGIC;
PS2_TX : out STD_LOGIC_VECTOR (7 downto 0);
PS2_WR : out STD_LOGIC;
ASCII : out STD_LOGIC_VECTOR (7 downto 0);
ASCII_RD : out STD_LOGIC;
ASCII_SP : out STD_LOGIC); -- Special Key Flag
end PS2_ASCII_GEN;
architecture Behavioral of PS2_ASCII_GEN is
type statetype is (idle, shift, read_b, read_e, read_eb, caps_toggle, busy_wait,reset);
signal state : statetype := idle;
signal wstate : statetype := idle;
signal ascii_lower : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal ascii_upper : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
shared variable shift_key : boolean := false;
shared variable caps : boolean := false;
begin
with PS2_RX select
ascii_lower <=
-- Alphabet
x"61" when x"1C",-- a
x"62" when x"32",-- b
x"63" when x"21",-- c
x"64" when x"23",-- d
x"65" when x"24",-- e
x"66" when x"2B",-- f
x"67" when x"34",-- g
x"68" when x"33",-- h
x"69" when x"43",-- i
x"6A" when x"3B",-- j
x"6B" when x"42",-- k
x"6C" when x"4B",-- l
x"6D" when x"3A",-- m
x"6E" when x"31",-- n
x"6F" when x"44",-- o
x"70" when x"4D",-- p
x"71" when x"15",-- q
x"72" when x"2D",-- r
x"73" when x"1B",-- s
x"74" when x"2C",-- t
x"75" when x"3C",-- u
x"76" when x"2A",-- v
x"77" when x"1D",-- w
x"78" when x"22",-- x
x"79" when x"35",-- y
x"7A" when x"1A",-- z
--Top Row
x"60" when x"0E",-- `
x"31" when x"16",-- 1
x"32" when x"1E",-- 2
x"33" when x"26",-- 3
x"34" when x"25",-- 4
x"35" when x"2E",-- 5
x"36" when x"36",-- 6
x"37" when x"3D",-- 7
x"38" when x"3E",-- 8
x"39" when x"46",-- 9
x"30" when x"45",-- 0
x"2D" when x"4E",-- -
x"3D" when x"55",-- =
--Enter Corner
x"5B" when x"54",-- [
x"5D" when x"5B",-- ]
x"5C" when x"5D",-- \
x"3B" when x"4C",-- ;
x"27" when x"52",-- '
x"2C" when x"41",-- ,
x"2E" when x"49",-- .
x"2F" when x"4A",-- /
--Function Keys -- Based on the IBM PC Codes
x"1B" when x"76",-- Esc (Escape)
x"3B" when x"05",-- F1
x"3C" when x"06",-- F2
x"3D" when x"04",-- F3
x"3E" when x"0C",-- F4
x"3F" when x"03",-- F5
x"40" when x"0B",-- F6
x"41" when x"83",-- F7
x"42" when x"0A",-- F8
x"43" when x"01",-- F9
x"44" when x"09",-- F10
x"85" when x"78",-- F11
x"86" when x"07",-- F12
x"09" when x"0D",-- Tab (Horizontal Tab)
x"0D" when x"5A",-- Enter (Carriage Return)
--need no value *(special characters)
x"00" when x"58",-- Caps Lock
x"00" when x"14",-- Ctrl
x"00" when x"11",-- Alt
x"00" when x"66",-- Back Space
--Direction Keys
x"48" when x"75",-- Up
x"50" when x"72",-- Down
x"4B" when x"6B",-- Left
x"4D" when x"74",-- Right
--Unknown input
x"00" when OTHERS; -- Null
with PS2_RX select
ascii_upper <=
-- Alphabet
x"41" when x"1C",-- A
x"42" when x"32",-- B
x"43" when x"21",-- C
x"44" when x"23",-- D
x"45" when x"24",-- E
x"46" when x"2B",-- F
x"47" when x"34",-- G
x"48" when x"33",-- H
x"49" when x"43",-- I
x"4A" when x"3B",-- J
x"4B" when x"42",-- K
x"4C" when x"4B",-- L
x"4D" when x"3A",-- M
x"4E" when x"31",-- N
x"4F" when x"44",-- O
x"50" when x"4D",-- P
x"51" when x"15",-- Q
x"52" when x"2D",-- R
x"53" when x"1B",-- S
x"54" when x"2C",-- T
x"55" when x"3C",-- U
x"56" when x"2A",-- V
x"57" when x"1D",-- W
x"58" when x"22",-- X
x"59" when x"35",-- Y
x"5A" when x"1A",-- Z
-- Special Upper case Characters (top left to bottom right)
-- Top Row
x"7E" when x"0E",-- ~
x"21" when x"16",-- !
x"40" when x"1E",-- @
x"23" when x"26",-- #
x"24" when x"25",-- $
x"25" when x"2E",-- %
x"5E" when x"36",-- ^
x"26" when x"3D",-- &
x"2A" when x"3E",-- *
x"28" when x"46",-- (
x"29" when x"45",-- )
x"5F" when x"4E",-- _
x"2B" when x"55",-- +
-- Enter Corner
x"7B" when x"54",-- {
x"7D" when x"5B",-- }
x"7C" when x"5D",-- |
x"3A" when x"4C",-- :
x"22" when x"52",-- "
x"3C" when x"41",-- <
x"3E" when x"49",-- >
x"3F" when x"4A",-- ?
-- Unknown Key
x"00" when OTHERS; -- Null
process (CLK,RST,PS2_RX,PS2_RD,PS2_ER)
begin
if (RST = '1' and PS2_ER = '1') then
state <= reset;
elsif (PS2_RD'event and PS2_RD = '1') then--(CLK'event and CLK = '1') then
case state is
when idle =>
--if (PS2_RD'event and PS2_RD = '1') then
ASCII_SP <= '0';
ASCII_RD <= '0';
if PS2_RX = x"F0" then
state <= read_b;
elsif PS2_RX = x"E0" then
state <= read_e;
elsif(PS2_RX = x"12" or PS2_RX = x"54") then
state <= shift;
end if;
--end if;
when read_b =>
--if (PS2_RD'event and PS2_RD = '1') then
if caps = true then
ASCII <= ascii_upper;
else
ASCII <= ascii_lower;
end if;
ASCII_RD <= '1';
--end if;
when read_e =>
--if (PS2_RD'event and PS2_RD = '1') then
if PS2_RX = x"F0" then
state <= read_eb;
ASCII_SP <= '1'; -- Enable Special Mode
else
state <= idle;
end if;
--end if;
when read_eb =>
--if (PS2_RD'event and PS2_RD = '1') then
ASCII <= ascii_lower;
ASCII_RD <= '1';
--end if;
when shift =>
--ASCII <= ascii_upper;
--ASCII_RD <= '1';
state <= idle;
when caps_toggle =>
PS2_TX <= x"ED";
PS2_WR <= '1';
when reset =>
PS2_TX <= x"FF"; --send keyboard reset cmd
PS2_WR <= '1';
state <= idle;
when busy_wait =>
if PS2_BS = '0' then
state <= wstate;
end if;
when others =>
state <= idle;
end case;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity nt_ss is
port(
clk : in STD_LOGIC;
SI : in bit;
PO : out bit_VECTOR(7 downto 0)
);
end nt_ss;
--}} End of automatically maintained section
architecture nt_ss of nt_ss is
signal tmp:bit_vector(7 downto 0);
begin
process (clk)
begin
if (clk'event and clk='1') then
tmp <= tmp(6 downto 0)& SI;
end if;
PO <= tmp;
end process;
end nt_ss;
--clk=20Mhz; SI= random |
---------------------------------------------------------------------------
-- Copyright © 2010 Lawrence Wilkinson [email protected]
--
-- This file is part of LJW2030, a VHDL implementation of the IBM
-- System/360 Model 30.
--
-- LJW2030 is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- LJW2030 is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with LJW2030 . If not, see <http://www.gnu.org/licenses/>.
--
---------------------------------------------------------------------------
--
-- File: ibm2030-switches.vhd
-- Creation Date: 21:49:37 20/01/2010
-- Description:
-- 360/30 Front Panel switch handling
-- Some switches are provided by the pushbuttons and sliders on the S3BOARD
-- Rotary switches are connected externally with a mixture of scanning and
-- discrete inputs. In all cases the "Process" position is not connected so
-- omitting the switches entirely allows the system to run normally.
-- Page references like "5-01A" refer to the IBM Maintenance Diagram Manual (MDM)
-- for the 360/30 R25-5103-1
-- References like "02AE6" refer to coordinate "E6" on page "5-02A"
-- Logic references like "AB3D5" refer to card "D5" in board "B3" in gate "A"
-- Gate A is the main logic gate, B is the second (optional) logic gate,
-- C is the core storage and X is the CCROS unit
--
-- Revision History:
-- Revision 1.0 2010-07-09
-- Initial Release
-- Revision 1.01 2010-07-20
-- [LJW] Add Switch connection information, no functional change
--
--
-- Func Port Pin Conn A2 A B C D E F G H J AC E' ROS Rate Check
-- Ground 1 - - - - - - - - - - - - - -
-- +5V 2 - - - - - - - - - - - - - -
-- +3.3V Vcco 3 - - - - - - - - - - C C C C
-- Hex0 pa_io1 E6 4 * * * * * * * * * # - - - -
-- Hex1 pa_io2 D5 5 * * * * * * * * * # - - - -
-- Hex2 pa_io3 C5 6 * * * * * * * * * # - - - -
-- Hex3 pa_io4 D6 7 * * * * * * * * * # - - - -
-- ScanA pa_io5 C6 8 S - - - - - - - - - - - - -
-- ScanB pa_io6 E7 9 - S - - - - - - - - - - - -
-- ScanC pa_io7 C7 10 - - S - - - - - - - - - - -
-- ScanD pa_io8 D7 11 - - - S - - - - - - - - - -
-- ScanE pa_io9 C8 12 - - - - S - - - - - - - - -
-- ScanF pa_io10 D8 13 - - - - - S - - - - - - - -
-- ScanG pa_io11 C9 14 - - - - - - S - - - - - - -
-- ScanH pa_io12 D10 15 - - - - - - - S - - - - - -
-- ScanJ pa_io13 A3 16 - - - - - - - - S - - - - -
-- ScanAC pa_io14 B4 17 - - - - - - - - - S - - - -
-- E_Inner pa_io15 A4 18 - - - - - - - - - - * - - -
-- E_Outer pa_io16 B5 19 - - - - - - - - - - * - - -
-- ROS InhCFStop pa_io17 A5 20 - - - - - - - - - - - * - -
-- ROS Scan pa_io18 B6 21 - - - - - - - - - - - * - -
-- Rate_InstrStep ma2_db0 B7 22 - - - - - - - - - - - - * -
-- Rate_SingleCyc ma2_db1 A7 23 - - - - - - - - - - - - * -
-- Check_Diag ma2_db2 B8 24 - - - - - - - - - - - - - *
-- Check_Disable ma2_db3 A8 25 - - - - - - - - - - - - - *
-- Check_Stop ma2_db4 A9 26 - - - - - - - - - - - - - *
-- Check_Restart ma2_db5 B10 27 - - - - - - - - - - - - - *
--
-- * = Hex0,1,2,3 inputs have diodes from each of the 9 hex-encoded switches A-J (A to switch, K to FPGA, total 36 diodes)
-- # = The Address Compare switch (AC) is 10-position, unencoded, with diodes to perform the 0-9 encoding (total 15 diodes)
-- S = Scan output to switch common (one output at a time goes high to scan)
-- C = Common connection for non-scanned switches
-- Switch E' is the selector switch which is part of switch E and selects the inner, middle or outer rings
-- The "Proc" positions of the ROS, Rate and Check switches are not connected - if no switches are present then these 3 and the AC switch default to "Proc"
-- The "Middle" position of the E selector switch is not connected - the default is therefore the MS/LS ring
-- Pulldowns are provided by the FPGA input
--
-- Most of the remaining switches are connected to the on-board pushbuttons and slide switches:
-- Reset
-- Start
-- Stop
-- Load
-- Lamp Test
-- ROAR Reset
-- Display
-- Store
-- Check Reset
-- Set IC
-- Interrupt
-- Fast/Slow clock control
-- Two switches are not used:
-- Power Off
-- Timer Interrupt
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.Buses_package.all;
use work.Gates_package.EvenParity;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity switches is
Port ( -- Raw switch inputs: (These can be modified to suit the board being used)
SwA_scan : out STD_LOGIC;
SwB_scan : out STD_LOGIC;
SwC_scan : out STD_LOGIC;
SwD_scan : out STD_LOGIC;
SwE_scan : out STD_LOGIC;
SwF_scan : out STD_LOGIC;
SwG_scan : out STD_LOGIC;
SwH_scan : out STD_LOGIC;
SwJ_scan : out STD_LOGIC;
SwAC_scan : out STD_LOGIC; -- Address Compare
Hex_in : in STD_LOGIC_VECTOR(3 downto 0);
SW_E_Inner, SW_E_Outer : in STD_LOGIC;
RawSw_Proc_Inh_CF_Stop, RawSw_Proc_Scan : in STD_LOGIC; -- ROS Control
RawSw_Rate_Single_Cycle, RawSw_Rate_Instruction_Step : in STD_LOGIC; -- Rate
RawSw_Chk_Chk_Restart, RawSw_Chk_Diagnostic, RawSw_Chk_Stop, RawSw_Chk_Disable : in STD_LOGIC; -- Check Control
pb : in std_logic_vector(3 downto 0); -- On-board pushbuttons
sw : in std_logic_vector(7 downto 0); -- On-board slide switches
-- Scanned switch inputs - MAX7318 connections
SCL : out STD_LOGIC;
SDA : inout STD_LOGIC;
-- Other inputs
clk : in STD_LOGIC; -- 50MHz
status_lamps : in STD_LOGIC_VECTOR(4 downto 0);
-- Conditioned switch outputs:
SwA,SwB,SwC,SwD,SwF,SwG,SwH,SwJ : out STD_LOGIC_VECTOR(3 downto 0);
SwAP,SwBP,SwCP,SwDP,SwFP,SwGP,SwHP,SwJP : out STD_LOGIC;
SwE : out E_SW_BUS_Type;
Sw_PowerOff, Sw_Interrupt, Sw_Load : out STD_LOGIC; -- Right-hand pushbuttons
Sw_SystemReset, Sw_RoarReset, Sw_Start, Sw_SetIC, Sw_CheckReset,
Sw_Stop, Sw_IntTmr, Sw_Store, Sw_LampTest, Sw_Display : out STD_LOGIC; -- Left-hand pushbuttons
Sw_Proc_Inh_CF_Stop, Sw_Proc_Proc, Sw_Proc_Scan : out STD_LOGIC; -- ROS Control
Sw_Rate_Single_Cycle, Sw_Rate_Instruction_Step, Sw_Rate_Process : out STD_LOGIC; -- Rate
Sw_Chk_Chk_Restart, Sw_Chk_Diagnostic, Sw_Chk_Stop, Sw_Chk_Process, Sw_Chk_Disable : out STD_LOGIC; -- Check Control
Sw_ROAR_RESTT,Sw_ROAR_RESTT_WITHOUT_RST,Sw_EARLY_ROAR_STOP,Sw_ROAR_STOP, Sw_ROAR_RESTT_STOR_BYPASS,
Sw_ROAR_SYNC,Sw_ADDR_COMP_PROC,Sw_SAR_DLYD_STOP,Sw_SAR_STOP,Sw_SAR_RESTART : out STD_LOGIC; -- Address Compare
-- 1kHz clock signal
Clock1ms : out STD_LOGIC;
-- 50Hz Timer signal
Timer : out STD_LOGIC
);
end switches;
architecture Behavioral of switches is
subtype debounce is std_logic_vector(0 to 3);
signal scan : std_logic_vector(3 downto 0) := "0000";
signal counter : std_logic_vector(14 downto 0) := (others=>'0');
signal counter1k : std_logic_vector(15 downto 0) := (others=>'0');
signal timerCounter : std_logic_vector(5 downto 0) := (others=>'0');
signal SwE_raw,SwE_combined : std_logic_vector(3 downto 0) := "0000";
signal UseInner,UseMid,UseOuter : Boolean;
signal SwAC,SwAC_combined : std_logic_vector(3 downto 0) := "0000"; -- Address Compare switch
signal Parity_in : std_logic;
signal RawSw_PowerOff, RawSw_Interrupt, RawSw_Load, RawSw_SystemReset, RawSw_RoarReset, RawSw_Start,
RawSw_SetIC, RawSw_CheckReset, RawSw_Stop, RawSw_IntTmr, RawSw_Store, RawSw_LampTest,
RawSw_Display : STD_LOGIC; -- Right-hand pushbuttons
signal debouncePowerOff, debounceInterrupt, debounceLoad,
debounceSystemReset, debounceRoarReset, debounceStart, debounceSetIC, debounceCheckReset,
debounceStop, debounceIntTmr, debounceStore, debounceLampTest, debounceDisplay : debounce;
signal timerOut : std_logic := '0';
signal sClock1ms : std_logic := '0';
signal max7318_switches : std_logic_vector(0 to 63);
constant divider : std_logic_vector(14 downto 0) := "100111000100000"; -- 20,000 gives 2.5kHz
constant divider2000 : std_logic_vector(14 downto 0) := "110000110101000"; -- 25,000 gives 2kHz
constant sample : std_logic_vector(14 downto 0) := "100111000011110"; -- 19,999
constant divider100 : std_logic_vector(4 downto 0) := "11001"; --- 25 converts 2.5kHz to 100Hz for timer
begin
max7318 : entity panel_Switches port map (
clk => clk,
SCL => SCL,
SDA => SDA,
LEDs => status_lamps,
Switches => max7318_switches -- If the MAX7318 is not present, this vector should be all zero
);
Parity_in <= EvenParity(Hex_in);
scan_counter: process(clk)
begin
if (rising_edge(clk)) then
if counter=sample then
if scan="0000" then SwA <= Hex_in or max7318_switches(12 to 15); SwAP <= Parity_in; end if;
if scan="0001" then SwB <= Hex_in or max7318_switches(16 to 19); SwBP <= Parity_in; end if;
if scan="0010" then SwC <= Hex_in or max7318_switches(20 to 23); SwCP <= Parity_in; end if;
if scan="0011" then SwD <= Hex_in or max7318_switches(24 to 27); SwDP <= Parity_in; end if;
if scan="0100" then SwE_raw <= Hex_in or max7318_switches(36 to 39); end if;
if scan="0101" then SwF <= Hex_in or max7318_switches(28 to 31); SwFP <= Parity_in; end if;
if scan="0110" then SwG <= Hex_in or max7318_switches(40 to 43); SwGP <= Parity_in; end if;
if scan="0111" then SwH <= Hex_in or max7318_switches(44 to 47); SwHP <= Parity_in; end if;
if scan="1000" then SwJ <= Hex_in or max7318_switches(48 to 51); SwJP <= Parity_in; end if;
if scan="1001" then SwAC <= Hex_in or max7318_switches(4 to 7); end if;
end if;
if counter=divider then
counter<=(others=>'0');
if scan="1001" then
scan <= "0000";
else
scan <= scan + 1;
end if;
debouncePowerOff <= debouncePowerOff(1 to 3) & rawSw_PowerOff;
debounceInterrupt <= debounceInterrupt(1 to 3) & (rawSw_Interrupt or max7318_switches(53));
debounceLoad <= debounceLoad(1 to 3) & (rawSw_Load or max7318_switches(52));
debounceSystemReset <= debounceSystemReset(1 to 3) & (rawSw_SystemReset or max7318_switches(63));
debounceRoarReset <= debounceRoarReset(1 to 3) & (rawSw_RoarReset or max7318_switches(61));
debounceStart <= debounceStart(1 to 3) & (rawSw_Start or max7318_switches(56));
debounceSetIC <= debounceSetIC(1 to 3) & (rawSw_SetIC or max7318_switches(60));
debounceCheckReset <= debounceCheckReset(1 to 3) & (rawSw_CheckReset or max7318_switches(58));
debounceStop <= debounceStop(1 to 3) & (rawSw_Stop or max7318_switches(55));
debounceIntTmr <= debounceIntTmr(1 to 3) & (rawSw_IntTmr or max7318_switches(62));
debounceStore <= debounceStore(1 to 3) & (rawSw_Store or max7318_switches(59));
debounceLampTest <= debounceLampTest(1 to 3) & (rawSw_LampTest or max7318_switches(57));
debounceDisplay <= debounceDisplay(1 to 3) & (rawSw_Display or max7318_switches(54));
if (debouncePowerOff = "0000") then Sw_PowerOff <= '0'; else if (debouncePowerOff = "1111") then Sw_PowerOff <= '1'; end if; end if;
if (debounceInterrupt = "0000") then Sw_Interrupt <= '0'; else if (debounceInterrupt = "1111") then Sw_Interrupt <= '1'; end if; end if;
if (debounceLoad = "0000") then Sw_Load <= '0'; else if (debounceLoad = "1111") then Sw_Load <= '1'; end if; end if;
if (debounceSystemReset = "0000") then Sw_SystemReset <= '0'; else if (debounceSystemReset = "1111") then Sw_SystemReset <= '1'; end if; end if;
if (debounceRoarReset = "0000") then Sw_RoarReset <= '0'; else if (debounceRoarReset = "1111") then Sw_RoarReset <= '1'; end if; end if;
if (debounceStart = "0000") then Sw_Start <= '0'; else if (debounceStart = "1111") then Sw_Start <= '1'; end if; end if;
if (debounceSetIC = "0000") then Sw_SetIC <= '0'; else if (debounceSetIC = "1111") then Sw_SetIC <= '1'; end if; end if;
if (debounceCheckReset = "0000") then Sw_CheckReset <= '0'; else if (debounceCheckReset = "1111") then Sw_CheckReset <= '1'; end if; end if;
if (debounceStop = "0000") then Sw_Stop <= '0'; else if (debounceStop = "1111") then Sw_Stop <= '1'; end if; end if;
if (debounceIntTmr = "0000") then Sw_IntTmr <= '0'; else if (debounceIntTmr = "1111") then Sw_IntTmr <= '1'; end if; end if;
if (debounceStore = "0000") then Sw_Store <= '0'; else if (debounceStore = "1111") then Sw_Store <= '1'; end if; end if;
if (debounceLampTest = "0000") then Sw_LampTest <= '0'; else if (debounceLampTest = "1111") then Sw_LampTest <= '1'; end if; end if;
if (debounceDisplay = "0000") then Sw_Display <= '0'; else if (debounceDisplay = "1111") then Sw_Display <= '1'; end if; end if;
if (timerCounter = divider100) then
timerOut <= not timerOut;
Timer <= timerOut;
timerCounter <= (others=>'0');
else
timerCounter <= timerCounter + 1;
end if;
else
counter <= counter + 1;
end if;
end if;
end process;
Clock1kHz : process(clk)
begin
if (rising_edge(clk)) then
if counter1k = divider2000 then
counter1k <= (others => '0');
sClock1ms <= not sClock1ms;
else
counter1k <= counter1k + 1;
end if;
end if;
end process;
Clock1ms <= sClock1ms;
SwA_scan <= '1' when scan="0000" else '0';
SwB_scan <= '1' when scan="0001" else '0';
SwC_scan <= '1' when scan="0010" else '0';
SwD_scan <= '1' when scan="0011" else '0';
SwE_scan <= '1' when scan="0100" else '0';
SwF_scan <= '1' when scan="0101" else '0';
SwG_scan <= '1' when scan="0110" else '0';
SwH_scan <= '1' when scan="0111" else '0';
SwJ_scan <= '1' when scan="1000" else '0';
SwAC_scan <= '1' when scan="1001" else '0';
-- Inner ring
UseInner <= (SW_E_INNER='1' or max7318_switches(34)='1');
UseMid <= SW_E_INNER='0' and max7318_switches(34)='0' and SW_E_OUTER='0' and max7318_switches(35)='0';
UseOuter <= (SW_E_OUTER='1' or max7318_switches(35)='1');
SwE_combined <= SwE_raw or max7318_switches(36 to 39);
SwE.I_SEL <= '1' when SwE_combined="0000" and UseInner else '0';
SwE.J_SEL <= '1' when SwE_combined="0001" and UseInner else '0';
SwE.U_SEL <= '1' when SwE_combined="0010" and UseInner else '0';
SwE.V_SEL <= '1' when SwE_combined="0011" and UseInner else '0';
SwE.L_SEL <= '1' when SwE_combined="0100" and UseInner else '0';
SwE.T_SEL <= '1' when SwE_combined="0101" and UseInner else '0';
SwE.D_SEL <= '1' when SwE_combined="0110" and UseInner else '0';
SwE.R_SEL <= '1' when SwE_combined="0111" and UseInner else '0';
SwE.S_SEL <= '1' when SwE_combined="1000" and UseInner else '0';
SwE.G_SEL <= '1' when SwE_combined="1001" and UseInner else '0';
SwE.H_SEL <= '1' when SwE_combined="1010" and UseInner else '0';
SwE.FI_SEL <= '1' when SwE_combined="1011" and UseInner else '0';
SwE.FT_SEL <= '1' when SwE_combined="1100" and UseInner else '0';
-- Mid ring
SwE.MS_SEL <= '1' when SwE_combined="0000" and UseMid else '0';
SwE.LS_SEL <= '1' when SwE_combined="0001" and UseMid else '0';
-- Outer ring
SwE.E_SEL_SW_GS <= '1' when SwE_combined="0000" and UseOuter else '0';
SwE.E_SEL_SW_GT <= '1' when SwE_combined="0001" and UseOuter else '0';
SwE.E_SEL_SW_GUV_GCD <= '1' when SwE_combined="0010" and UseOuter else '0';
SwE.E_SEL_SW_HS <= '1' when SwE_combined="0011" and UseOuter else '0';
SwE.E_SEL_SW_HT <= '1' when SwE_combined="0100" and UseOuter else '0';
SwE.E_SEL_SW_HUV_HCD <= '1' when SwE_combined="0101" and UseOuter else '0';
SwE.Q_SEL <= '1' when SwE_combined="0110" and UseOuter else '0';
SwE.C_SEL <= '1' when SwE_combined="0111" and UseOuter else '0';
SwE.F_SEL <= '1' when SwE_combined="1000" and UseOuter else '0';
SwE.TT_SEL <= '1' when SwE_combined="1001" and UseOuter else '0';
SwE.TI_SEL <= '1' when SwE_combined="1010" and UseOuter else '0';
SwE.JI_SEL <= '1' when SwE_combined="1011" and UseOuter else '0';
-- SwE.IJ_SEL <= '1' when (SwE_raw="0000" or SwE_raw="0001") and SW_E_INNER='1' and USE_MAN_DECODER_PWR='1' else '0'; -- AC1G6,AC1D2
-- SwE.UV_SEL <= '1' when (SwE_raw="0010" or SwE_raw="0011") and SW_E_INNER='1' and USE_MAN_DECODER_PWR='1' else '0'; -- AC1G6,AC1D2
-- Address Compare
SwAC_combined <= SwAC or max7318_switches(4 to 7);
Sw_ADDR_COMP_PROC <= '1' when SwAC_combined="0000" else '0';
Sw_SAR_DLYD_STOP <= '1' when SwAC_combined="0001" else '0';
Sw_SAR_STOP <= '1' when SwAC_combined="0010" else '0';
Sw_SAR_RESTART <= '1' when SwAC_combined="0011" else '0';
Sw_ROAR_RESTT_STOR_BYPASS <= '1' when SwAC_combined="0100" else '0';
Sw_ROAR_RESTT <= '1' when SwAC_combined="0101" else '0';
Sw_ROAR_RESTT_WITHOUT_RST <= '1' when SwAC_combined="0110" else '0';
Sw_EARLY_ROAR_STOP <= '1' when SwAC_combined="0111" else '0';
Sw_ROAR_STOP <= '1' when SwAC_combined="1000" else '0';
Sw_ROAR_SYNC <= '1' when SwAC_combined="1001" else '0';
-- ROS Control
Sw_Proc_Inh_CF_Stop <= '1' when RawSw_Proc_Inh_CF_Stop='1' or max7318_switches(0)='1' else '0';
Sw_Proc_Proc <= '1' when RawSw_Proc_Inh_CF_Stop='0' and RawSw_Proc_Scan='0' and max7318_switches(0 to 1)="00" else '0';
Sw_Proc_Scan <= '1' when RawSw_Proc_Scan='1' or max7318_switches(1)='1' else '0';
-- Rate
Sw_Rate_Single_Cycle <= '1' when RawSw_Rate_Single_Cycle='1' or max7318_switches(3)='1' else '0';
Sw_Rate_Process <= '1' when RawSw_Rate_Single_Cycle='0' and RawSw_Rate_Instruction_Step='0' and max7318_switches(2 to 3)="00" else '0';
Sw_Rate_Instruction_Step <= '1' when RawSw_Rate_Instruction_Step='1' or max7318_switches(2)='1' else '0';
-- Check Control
Sw_Chk_Chk_Restart <= '1' when RawSw_Chk_Chk_Restart='1' or max7318_switches(11)='1' else '0';
Sw_Chk_Diagnostic <= '1' when RawSw_Chk_Diagnostic='1' or max7318_switches(8)='1' else '0';
Sw_Chk_Stop <= '1' when RawSw_Chk_Stop='1' or max7318_switches(10)='1' else '0';
Sw_Chk_Process <= '1' when RawSw_Chk_Chk_Restart='0' and RawSw_Chk_Diagnostic='0' and RawSw_Chk_Stop='0' and RawSw_Chk_Disable='0' and max7318_switches(8 to 11)="0000"else '0';
Sw_Chk_Disable <= '1' when RawSw_Chk_Disable='1' or max7318_switches(9)='1' else '0';
-- Unimplemented switches
RawSw_PowerOff <= '0';
-- Pushbuttons
RawSw_SystemReset <= pb(0);
RawSw_Start <= pb(1);
RawSw_Load <= pb(2);
RawSw_Stop <= pb(3);
-- Slide switches
RawSw_IntTmr <= sw(0);
RawSw_Display <= sw(1);
RawSw_Store <= sw(2);
RawSw_Interrupt <= sw(3);
RawSw_RoarReset <= sw(4);
RawSw_SetIC <= sw(5);
RawSw_CheckReset <= sw(6);
RawSw_LampTest <= sw(7);
end behavioral;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Tue May 13 22:49:19 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode funcsim /home/keith/Documents/VHDL-lib/top/lab_6/ip/dds/dds_funcsim.vhdl
-- Design : dds
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
`protect begin_protected
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`protect end_protected
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \ddsdds_compiler_v6_0__parameterized0\ is
port (
aclk : in STD_LOGIC;
aclken : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tready : out STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 );
s_axis_phase_tlast : in STD_LOGIC;
s_axis_phase_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_config_tvalid : in STD_LOGIC;
s_axis_config_tready : out STD_LOGIC;
s_axis_config_tdata : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_config_tlast : in STD_LOGIC;
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tready : in STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_data_tlast : out STD_LOGIC;
m_axis_data_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_phase_tvalid : out STD_LOGIC;
m_axis_phase_tready : in STD_LOGIC;
m_axis_phase_tdata : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_phase_tlast : out STD_LOGIC;
m_axis_phase_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
event_pinc_invalid : out STD_LOGIC;
event_poff_invalid : out STD_LOGIC;
event_phase_in_invalid : out STD_LOGIC;
event_s_phase_tlast_missing : out STD_LOGIC;
event_s_phase_tlast_unexpected : out STD_LOGIC;
event_s_phase_chanid_incorrect : out STD_LOGIC;
event_s_config_tlast_missing : out STD_LOGIC;
event_s_config_tlast_unexpected : out STD_LOGIC;
debug_axi_pinc_in : out STD_LOGIC_VECTOR ( 21 downto 0 );
debug_axi_poff_in : out STD_LOGIC_VECTOR ( 21 downto 0 );
debug_axi_resync_in : out STD_LOGIC;
debug_axi_chan_in : out STD_LOGIC_VECTOR ( 0 to 0 );
debug_core_nd : out STD_LOGIC;
debug_phase : out STD_LOGIC_VECTOR ( 21 downto 0 );
debug_phase_nd : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \ddsdds_compiler_v6_0__parameterized0\ : entity is "dds_compiler_v6_0";
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of \ddsdds_compiler_v6_0__parameterized0\ : entity is "zynq";
attribute C_MODE_OF_OPERATION : integer;
attribute C_MODE_OF_OPERATION of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_MODULUS : integer;
attribute C_MODULUS of \ddsdds_compiler_v6_0__parameterized0\ : entity is 9;
attribute C_ACCUMULATOR_WIDTH : integer;
attribute C_ACCUMULATOR_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 22;
attribute C_CHANNELS : integer;
attribute C_CHANNELS of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_HAS_PHASE_OUT : integer;
attribute C_HAS_PHASE_OUT of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_HAS_PHASEGEN : integer;
attribute C_HAS_PHASEGEN of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_HAS_SINCOS : integer;
attribute C_HAS_SINCOS of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_LATENCY : integer;
attribute C_LATENCY of \ddsdds_compiler_v6_0__parameterized0\ : entity is 7;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_NEGATIVE_COSINE : integer;
attribute C_NEGATIVE_COSINE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_NEGATIVE_SINE : integer;
attribute C_NEGATIVE_SINE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_NOISE_SHAPING : integer;
attribute C_NOISE_SHAPING of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_OUTPUTS_REQUIRED : integer;
attribute C_OUTPUTS_REQUIRED of \ddsdds_compiler_v6_0__parameterized0\ : entity is 2;
attribute C_OUTPUT_FORM : integer;
attribute C_OUTPUT_FORM of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_OUTPUT_WIDTH : integer;
attribute C_OUTPUT_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 16;
attribute C_PHASE_ANGLE_WIDTH : integer;
attribute C_PHASE_ANGLE_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 16;
attribute C_PHASE_INCREMENT : integer;
attribute C_PHASE_INCREMENT of \ddsdds_compiler_v6_0__parameterized0\ : entity is 3;
attribute C_PHASE_INCREMENT_VALUE : string;
attribute C_PHASE_INCREMENT_VALUE of \ddsdds_compiler_v6_0__parameterized0\ : entity is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_RESYNC : integer;
attribute C_RESYNC of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_PHASE_OFFSET : integer;
attribute C_PHASE_OFFSET of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_PHASE_OFFSET_VALUE : string;
attribute C_PHASE_OFFSET_VALUE of \ddsdds_compiler_v6_0__parameterized0\ : entity is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_OPTIMISE_GOAL : integer;
attribute C_OPTIMISE_GOAL of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_USE_DSP48 : integer;
attribute C_USE_DSP48 of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_POR_MODE : integer;
attribute C_POR_MODE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_AMPLITUDE : integer;
attribute C_AMPLITUDE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_HAS_TLAST : integer;
attribute C_HAS_TLAST of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_HAS_TREADY : integer;
attribute C_HAS_TREADY of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_HAS_S_PHASE : integer;
attribute C_HAS_S_PHASE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_S_PHASE_TDATA_WIDTH : integer;
attribute C_S_PHASE_TDATA_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 24;
attribute C_S_PHASE_HAS_TUSER : integer;
attribute C_S_PHASE_HAS_TUSER of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_S_PHASE_TUSER_WIDTH : integer;
attribute C_S_PHASE_TUSER_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_HAS_S_CONFIG : integer;
attribute C_HAS_S_CONFIG of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_S_CONFIG_SYNC_MODE : integer;
attribute C_S_CONFIG_SYNC_MODE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_S_CONFIG_TDATA_WIDTH : integer;
attribute C_S_CONFIG_TDATA_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_HAS_M_DATA : integer;
attribute C_HAS_M_DATA of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_M_DATA_TDATA_WIDTH : integer;
attribute C_M_DATA_TDATA_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 32;
attribute C_M_DATA_HAS_TUSER : integer;
attribute C_M_DATA_HAS_TUSER of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_M_DATA_TUSER_WIDTH : integer;
attribute C_M_DATA_TUSER_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_HAS_M_PHASE : integer;
attribute C_HAS_M_PHASE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_M_PHASE_TDATA_WIDTH : integer;
attribute C_M_PHASE_TDATA_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_M_PHASE_HAS_TUSER : integer;
attribute C_M_PHASE_HAS_TUSER of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_M_PHASE_TUSER_WIDTH : integer;
attribute C_M_PHASE_TUSER_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of \ddsdds_compiler_v6_0__parameterized0\ : entity is 0;
attribute C_CHAN_WIDTH : integer;
attribute C_CHAN_WIDTH of \ddsdds_compiler_v6_0__parameterized0\ : entity is 1;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of \ddsdds_compiler_v6_0__parameterized0\ : entity is "yes";
end \ddsdds_compiler_v6_0__parameterized0\;
architecture STRUCTURE of \ddsdds_compiler_v6_0__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal NLW_i_synth_debug_axi_resync_in_UNCONNECTED : STD_LOGIC;
attribute C_ACCUMULATOR_WIDTH of i_synth : label is 22;
attribute C_AMPLITUDE of i_synth : label is 0;
attribute C_CHANNELS of i_synth : label is 1;
attribute C_CHAN_WIDTH of i_synth : label is 1;
attribute C_DEBUG_INTERFACE of i_synth : label is 0;
attribute C_HAS_ACLKEN of i_synth : label is 0;
attribute C_HAS_ARESETN of i_synth : label is 0;
attribute C_HAS_M_DATA of i_synth : label is 1;
attribute C_HAS_M_PHASE of i_synth : label is 0;
attribute C_HAS_PHASEGEN of i_synth : label is 1;
attribute C_HAS_PHASE_OUT of i_synth : label is 0;
attribute C_HAS_SINCOS of i_synth : label is 1;
attribute C_HAS_S_CONFIG of i_synth : label is 0;
attribute C_HAS_S_PHASE of i_synth : label is 1;
attribute C_HAS_TLAST of i_synth : label is 0;
attribute C_HAS_TREADY of i_synth : label is 0;
attribute C_LATENCY of i_synth : label is 7;
attribute C_MEM_TYPE of i_synth : label is 1;
attribute C_MODE_OF_OPERATION of i_synth : label is 0;
attribute C_MODULUS of i_synth : label is 9;
attribute C_M_DATA_HAS_TUSER of i_synth : label is 0;
attribute C_M_DATA_TDATA_WIDTH of i_synth : label is 32;
attribute C_M_DATA_TUSER_WIDTH of i_synth : label is 1;
attribute C_M_PHASE_HAS_TUSER of i_synth : label is 0;
attribute C_M_PHASE_TDATA_WIDTH of i_synth : label is 1;
attribute C_M_PHASE_TUSER_WIDTH of i_synth : label is 1;
attribute C_NEGATIVE_COSINE of i_synth : label is 0;
attribute C_NEGATIVE_SINE of i_synth : label is 0;
attribute C_NOISE_SHAPING of i_synth : label is 0;
attribute C_OPTIMISE_GOAL of i_synth : label is 0;
attribute C_OUTPUTS_REQUIRED of i_synth : label is 2;
attribute C_OUTPUT_FORM of i_synth : label is 0;
attribute C_OUTPUT_WIDTH of i_synth : label is 16;
attribute C_PHASE_ANGLE_WIDTH of i_synth : label is 16;
attribute C_PHASE_INCREMENT of i_synth : label is 3;
attribute C_PHASE_INCREMENT_VALUE of i_synth : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_PHASE_OFFSET of i_synth : label is 0;
attribute C_PHASE_OFFSET_VALUE of i_synth : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_POR_MODE of i_synth : label is 0;
attribute C_RESYNC of i_synth : label is 0;
attribute C_S_CONFIG_SYNC_MODE of i_synth : label is 0;
attribute C_S_CONFIG_TDATA_WIDTH of i_synth : label is 1;
attribute C_S_PHASE_HAS_TUSER of i_synth : label is 0;
attribute C_S_PHASE_TDATA_WIDTH of i_synth : label is 24;
attribute C_S_PHASE_TUSER_WIDTH of i_synth : label is 1;
attribute C_USE_DSP48 of i_synth : label is 0;
attribute C_XDEVICEFAMILY of i_synth : label is "zynq";
attribute downgradeipidentifiedwarnings of i_synth : label is "yes";
attribute secure_extras : string;
attribute secure_extras of i_synth : label is "A";
begin
debug_axi_resync_in <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
i_synth: entity work.\ddsdds_compiler_v6_0_viv__parameterized0\
port map (
aclk => aclk,
aclken => aclken,
aresetn => aresetn,
debug_axi_chan_in(0) => debug_axi_chan_in(0),
debug_axi_pinc_in(21 downto 0) => debug_axi_pinc_in(21 downto 0),
debug_axi_poff_in(21 downto 0) => debug_axi_poff_in(21 downto 0),
debug_axi_resync_in => NLW_i_synth_debug_axi_resync_in_UNCONNECTED,
debug_core_nd => debug_core_nd,
debug_phase(21 downto 0) => debug_phase(21 downto 0),
debug_phase_nd => debug_phase_nd,
event_phase_in_invalid => event_phase_in_invalid,
event_pinc_invalid => event_pinc_invalid,
event_poff_invalid => event_poff_invalid,
event_s_config_tlast_missing => event_s_config_tlast_missing,
event_s_config_tlast_unexpected => event_s_config_tlast_unexpected,
event_s_phase_chanid_incorrect => event_s_phase_chanid_incorrect,
event_s_phase_tlast_missing => event_s_phase_tlast_missing,
event_s_phase_tlast_unexpected => event_s_phase_tlast_unexpected,
m_axis_data_tdata(31 downto 0) => m_axis_data_tdata(31 downto 0),
m_axis_data_tlast => m_axis_data_tlast,
m_axis_data_tready => m_axis_data_tready,
m_axis_data_tuser(0) => m_axis_data_tuser(0),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_phase_tdata(0) => m_axis_phase_tdata(0),
m_axis_phase_tlast => m_axis_phase_tlast,
m_axis_phase_tready => m_axis_phase_tready,
m_axis_phase_tuser(0) => m_axis_phase_tuser(0),
m_axis_phase_tvalid => m_axis_phase_tvalid,
s_axis_config_tdata(0) => s_axis_config_tdata(0),
s_axis_config_tlast => s_axis_config_tlast,
s_axis_config_tready => s_axis_config_tready,
s_axis_config_tvalid => s_axis_config_tvalid,
s_axis_phase_tdata(23 downto 0) => s_axis_phase_tdata(23 downto 0),
s_axis_phase_tlast => s_axis_phase_tlast,
s_axis_phase_tready => s_axis_phase_tready,
s_axis_phase_tuser(0) => s_axis_phase_tuser(0),
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity dds is
port (
aclk : in STD_LOGIC;
s_axis_phase_tvalid : in STD_LOGIC;
s_axis_phase_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 );
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of dds : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of dds : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of dds : entity is "dds_compiler_v6_0,Vivado 2014.1";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of dds : entity is "dds,dds_compiler_v6_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of dds : entity is "dds,dds_compiler_v6_0,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dds_compiler,x_ipVersion=6.0,x_ipCoreRevision=4,x_ipLanguage=VHDL,C_XDEVICEFAMILY=zynq,C_MODE_OF_OPERATION=0,C_MODULUS=9,C_ACCUMULATOR_WIDTH=22,C_CHANNELS=1,C_HAS_PHASE_OUT=0,C_HAS_PHASEGEN=1,C_HAS_SINCOS=1,C_LATENCY=7,C_MEM_TYPE=1,C_NEGATIVE_COSINE=0,C_NEGATIVE_SINE=0,C_NOISE_SHAPING=0,C_OUTPUTS_REQUIRED=2,C_OUTPUT_FORM=0,C_OUTPUT_WIDTH=16,C_PHASE_ANGLE_WIDTH=16,C_PHASE_INCREMENT=3,C_PHASE_INCREMENT_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_RESYNC=0,C_PHASE_OFFSET=0,C_PHASE_OFFSET_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_OPTIMISE_GOAL=0,C_USE_DSP48=0,C_POR_MODE=0,C_AMPLITUDE=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_HAS_TLAST=0,C_HAS_TREADY=0,C_HAS_S_PHASE=1,C_S_PHASE_TDATA_WIDTH=24,C_S_PHASE_HAS_TUSER=0,C_S_PHASE_TUSER_WIDTH=1,C_HAS_S_CONFIG=0,C_S_CONFIG_SYNC_MODE=0,C_S_CONFIG_TDATA_WIDTH=1,C_HAS_M_DATA=1,C_M_DATA_TDATA_WIDTH=32,C_M_DATA_HAS_TUSER=0,C_M_DATA_TUSER_WIDTH=1,C_HAS_M_PHASE=0,C_M_PHASE_TDATA_WIDTH=1,C_M_PHASE_HAS_TUSER=0,C_M_PHASE_TUSER_WIDTH=1,C_DEBUG_INTERFACE=0,C_CHAN_WIDTH=1}";
end dds;
architecture STRUCTURE of dds is
signal NLW_U0_debug_axi_resync_in_UNCONNECTED : STD_LOGIC;
signal NLW_U0_debug_core_nd_UNCONNECTED : STD_LOGIC;
signal NLW_U0_debug_phase_nd_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_phase_in_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_pinc_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_poff_invalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_config_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_phase_chanid_incorrect_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_phase_tlast_missing_UNCONNECTED : STD_LOGIC;
signal NLW_U0_event_s_phase_tlast_unexpected_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_data_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_phase_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_phase_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_config_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_phase_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_debug_axi_chan_in_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_debug_axi_pinc_in_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_U0_debug_axi_poff_in_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_U0_debug_phase_UNCONNECTED : STD_LOGIC_VECTOR ( 21 downto 0 );
signal NLW_U0_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_phase_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_phase_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ACCUMULATOR_WIDTH : integer;
attribute C_ACCUMULATOR_WIDTH of U0 : label is 22;
attribute C_AMPLITUDE : integer;
attribute C_AMPLITUDE of U0 : label is 0;
attribute C_CHANNELS : integer;
attribute C_CHANNELS of U0 : label is 1;
attribute C_CHAN_WIDTH : integer;
attribute C_CHAN_WIDTH of U0 : label is 1;
attribute C_DEBUG_INTERFACE : integer;
attribute C_DEBUG_INTERFACE of U0 : label is 0;
attribute C_HAS_ACLKEN : integer;
attribute C_HAS_ACLKEN of U0 : label is 0;
attribute C_HAS_ARESETN : integer;
attribute C_HAS_ARESETN of U0 : label is 0;
attribute C_HAS_M_DATA : integer;
attribute C_HAS_M_DATA of U0 : label is 1;
attribute C_HAS_M_PHASE : integer;
attribute C_HAS_M_PHASE of U0 : label is 0;
attribute C_HAS_PHASEGEN : integer;
attribute C_HAS_PHASEGEN of U0 : label is 1;
attribute C_HAS_PHASE_OUT : integer;
attribute C_HAS_PHASE_OUT of U0 : label is 0;
attribute C_HAS_SINCOS : integer;
attribute C_HAS_SINCOS of U0 : label is 1;
attribute C_HAS_S_CONFIG : integer;
attribute C_HAS_S_CONFIG of U0 : label is 0;
attribute C_HAS_S_PHASE : integer;
attribute C_HAS_S_PHASE of U0 : label is 1;
attribute C_HAS_TLAST : integer;
attribute C_HAS_TLAST of U0 : label is 0;
attribute C_HAS_TREADY : integer;
attribute C_HAS_TREADY of U0 : label is 0;
attribute C_LATENCY : integer;
attribute C_LATENCY of U0 : label is 7;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 1;
attribute C_MODE_OF_OPERATION : integer;
attribute C_MODE_OF_OPERATION of U0 : label is 0;
attribute C_MODULUS : integer;
attribute C_MODULUS of U0 : label is 9;
attribute C_M_DATA_HAS_TUSER : integer;
attribute C_M_DATA_HAS_TUSER of U0 : label is 0;
attribute C_M_DATA_TDATA_WIDTH : integer;
attribute C_M_DATA_TDATA_WIDTH of U0 : label is 32;
attribute C_M_DATA_TUSER_WIDTH : integer;
attribute C_M_DATA_TUSER_WIDTH of U0 : label is 1;
attribute C_M_PHASE_HAS_TUSER : integer;
attribute C_M_PHASE_HAS_TUSER of U0 : label is 0;
attribute C_M_PHASE_TDATA_WIDTH : integer;
attribute C_M_PHASE_TDATA_WIDTH of U0 : label is 1;
attribute C_M_PHASE_TUSER_WIDTH : integer;
attribute C_M_PHASE_TUSER_WIDTH of U0 : label is 1;
attribute C_NEGATIVE_COSINE : integer;
attribute C_NEGATIVE_COSINE of U0 : label is 0;
attribute C_NEGATIVE_SINE : integer;
attribute C_NEGATIVE_SINE of U0 : label is 0;
attribute C_NOISE_SHAPING : integer;
attribute C_NOISE_SHAPING of U0 : label is 0;
attribute C_OPTIMISE_GOAL : integer;
attribute C_OPTIMISE_GOAL of U0 : label is 0;
attribute C_OUTPUTS_REQUIRED : integer;
attribute C_OUTPUTS_REQUIRED of U0 : label is 2;
attribute C_OUTPUT_FORM : integer;
attribute C_OUTPUT_FORM of U0 : label is 0;
attribute C_OUTPUT_WIDTH : integer;
attribute C_OUTPUT_WIDTH of U0 : label is 16;
attribute C_PHASE_ANGLE_WIDTH : integer;
attribute C_PHASE_ANGLE_WIDTH of U0 : label is 16;
attribute C_PHASE_INCREMENT : integer;
attribute C_PHASE_INCREMENT of U0 : label is 3;
attribute C_PHASE_INCREMENT_VALUE : string;
attribute C_PHASE_INCREMENT_VALUE of U0 : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_PHASE_OFFSET : integer;
attribute C_PHASE_OFFSET of U0 : label is 0;
attribute C_PHASE_OFFSET_VALUE : string;
attribute C_PHASE_OFFSET_VALUE of U0 : label is "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0";
attribute C_POR_MODE : integer;
attribute C_POR_MODE of U0 : label is 0;
attribute C_RESYNC : integer;
attribute C_RESYNC of U0 : label is 0;
attribute C_S_CONFIG_SYNC_MODE : integer;
attribute C_S_CONFIG_SYNC_MODE of U0 : label is 0;
attribute C_S_CONFIG_TDATA_WIDTH : integer;
attribute C_S_CONFIG_TDATA_WIDTH of U0 : label is 1;
attribute C_S_PHASE_HAS_TUSER : integer;
attribute C_S_PHASE_HAS_TUSER of U0 : label is 0;
attribute C_S_PHASE_TDATA_WIDTH : integer;
attribute C_S_PHASE_TDATA_WIDTH of U0 : label is 24;
attribute C_S_PHASE_TUSER_WIDTH : integer;
attribute C_S_PHASE_TUSER_WIDTH of U0 : label is 1;
attribute C_USE_DSP48 : integer;
attribute C_USE_DSP48 of U0 : label is 0;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.\ddsdds_compiler_v6_0__parameterized0\
port map (
aclk => aclk,
aclken => '1',
aresetn => '1',
debug_axi_chan_in(0) => NLW_U0_debug_axi_chan_in_UNCONNECTED(0),
debug_axi_pinc_in(21 downto 0) => NLW_U0_debug_axi_pinc_in_UNCONNECTED(21 downto 0),
debug_axi_poff_in(21 downto 0) => NLW_U0_debug_axi_poff_in_UNCONNECTED(21 downto 0),
debug_axi_resync_in => NLW_U0_debug_axi_resync_in_UNCONNECTED,
debug_core_nd => NLW_U0_debug_core_nd_UNCONNECTED,
debug_phase(21 downto 0) => NLW_U0_debug_phase_UNCONNECTED(21 downto 0),
debug_phase_nd => NLW_U0_debug_phase_nd_UNCONNECTED,
event_phase_in_invalid => NLW_U0_event_phase_in_invalid_UNCONNECTED,
event_pinc_invalid => NLW_U0_event_pinc_invalid_UNCONNECTED,
event_poff_invalid => NLW_U0_event_poff_invalid_UNCONNECTED,
event_s_config_tlast_missing => NLW_U0_event_s_config_tlast_missing_UNCONNECTED,
event_s_config_tlast_unexpected => NLW_U0_event_s_config_tlast_unexpected_UNCONNECTED,
event_s_phase_chanid_incorrect => NLW_U0_event_s_phase_chanid_incorrect_UNCONNECTED,
event_s_phase_tlast_missing => NLW_U0_event_s_phase_tlast_missing_UNCONNECTED,
event_s_phase_tlast_unexpected => NLW_U0_event_s_phase_tlast_unexpected_UNCONNECTED,
m_axis_data_tdata(31 downto 0) => m_axis_data_tdata(31 downto 0),
m_axis_data_tlast => NLW_U0_m_axis_data_tlast_UNCONNECTED,
m_axis_data_tready => '0',
m_axis_data_tuser(0) => NLW_U0_m_axis_data_tuser_UNCONNECTED(0),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_phase_tdata(0) => NLW_U0_m_axis_phase_tdata_UNCONNECTED(0),
m_axis_phase_tlast => NLW_U0_m_axis_phase_tlast_UNCONNECTED,
m_axis_phase_tready => '0',
m_axis_phase_tuser(0) => NLW_U0_m_axis_phase_tuser_UNCONNECTED(0),
m_axis_phase_tvalid => NLW_U0_m_axis_phase_tvalid_UNCONNECTED,
s_axis_config_tdata(0) => '0',
s_axis_config_tlast => '0',
s_axis_config_tready => NLW_U0_s_axis_config_tready_UNCONNECTED,
s_axis_config_tvalid => '0',
s_axis_phase_tdata(23 downto 0) => s_axis_phase_tdata(23 downto 0),
s_axis_phase_tlast => '0',
s_axis_phase_tready => NLW_U0_s_axis_phase_tready_UNCONNECTED,
s_axis_phase_tuser(0) => '0',
s_axis_phase_tvalid => s_axis_phase_tvalid
);
end STRUCTURE;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file tx_fifo.vhd when simulating
-- the core, tx_fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY tx_fifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END tx_fifo;
ARCHITECTURE tx_fifo_a OF tx_fifo IS
-- synthesis translate_off
COMPONENT wrapped_tx_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_tx_fifo USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 10,
c_default_value => "BlankString",
c_din_width => 32,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 32,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "1kx36",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 1023,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 1022,
c_prog_full_type => 1,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 10,
c_rd_depth => 1024,
c_rd_freq => 1,
c_rd_pntr_width => 10,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 10,
c_wr_depth => 1024,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 10,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_tx_fifo
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
prog_full => prog_full
);
-- synthesis translate_on
END tx_fifo_a;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file tx_fifo.vhd when simulating
-- the core, tx_fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY tx_fifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END tx_fifo;
ARCHITECTURE tx_fifo_a OF tx_fifo IS
-- synthesis translate_off
COMPONENT wrapped_tx_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_tx_fifo USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 10,
c_default_value => "BlankString",
c_din_width => 32,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 32,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "1kx36",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 1023,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 1022,
c_prog_full_type => 1,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 10,
c_rd_depth => 1024,
c_rd_freq => 1,
c_rd_pntr_width => 10,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 10,
c_wr_depth => 1024,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 10,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_tx_fifo
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
prog_full => prog_full
);
-- synthesis translate_on
END tx_fifo_a;
|
library ieee;
use ieee.std_logic_1164.all;
-- use ieee.math_real.all;
-- use ieee.numeric_std.all;
-- use ieee.std_logic_unsigned.all
library uart_bfm;
use uart_bfm.uart_bfm.all;
-- library uart_rx;
-- use uart_rx.uart_rx;
entity uart_tb is
end uart_tb;
architecture tb of uart_tb is
component uart is
port(
Clk : in std_ulogic;
Rst : in std_ulogic;
BaudRateGen : in std_ulogic_vector(19 downto 0);
NumStopBits : in std_ulogic_vector(1 downto 0);
UseParity : in std_ulogic;
ParityType : in std_ulogic;
-- rx
BitRx : in std_ulogic;
ByteTx : out std_ulogic_vector(7 downto 0);
ByteTxValid : out std_ulogic;
ParErr : out std_ulogic;
StopErr : out std_ulogic;
-- tx
ByteRx : in std_ulogic_vector(7 downto 0);
ByteRxValid : in std_ulogic;
BitTx : out std_ulogic;
TxBusy : out std_ulogic
);
end component;
signal byte : std_ulogic_vector(7 downto 0) := X"A5";
signal uart_tx : std_logic;
signal clk : std_ulogic := '1';
signal rst : std_ulogic := '1';
signal dout : std_ulogic_vector(7 downto 0);
signal doutValid : std_ulogic;
signal uartByteRx : std_ulogic_vector(7 downto 0);
signal uartByteRxValid : std_ulogic;
signal uartBitTx : std_ulogic;
signal uartTxBusy : std_ulogic;
signal test_done : std_ulogic := '0';
begin
uart_0 : uart
port map (
Clk => clk,
Rst => rst,
BaudRateGen => X"00036",
NumStopBits => "01",
UseParity => '1',
ParityType => '1',
BitRx => uart_tx,
-- ByteTx => dout,
-- ByteTxValid => doutValid,
ByteTx => uartByteRx,
ByteTxValid => uartByteRxValid,
ParErr => open,
StopErr => open,
-- tx
ByteRx => uartByteRx,
ByteRxValid => uartByteRxValid,
BitTx => uartBitTx,
TxBusy => uartTxBusy
);
P_CLK : process
begin
clk <= '0';
loop
wait for 5 ns;
clk <= not clk;
exit when test_done = '1';
end loop;
assert test_done = '0'
report "test run completed"
severity note;
-- loop
-- clk <= not clk after 5 ns;
-- exit when test_done = '1';
-- end loop;
wait;
end process P_CLK;
rst <= '0' after 15 ns;
-- clk16 <= not clk16 after 271 ns;
P_STIMULUS : process
begin
wait for 100 ns;
uart_tx_byte("odd", 1, x"A5", uart_tx);
uart_tx_byte("odd", 1, x"FF", uart_tx);
uart_tx_byte("odd", 1, x"00", uart_tx);
uart_tx_byte("odd", 1, x"15", uart_tx);
wait for 150 us;
test_done <= '1';
wait;
end process P_STIMULUS;
end tb;
|
-- $Id: s6_cmt_sfs_gsim.vhd 556 2014-05-29 19:01:39Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: s6_cmt_sfs - sim
-- Description: Spartan-6 CMT for simple frequency synthesis
-- simple vhdl model, without Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan-6
-- Tool versions: xst 14.5, 14.6; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.0 Initial version (derived from s7_cmt_sfs_gsim)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity s6_cmt_sfs is -- Spartan-6 CMT for simple freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1; -- output divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or MMCM
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- pll/mmcm locked
);
end s6_cmt_sfs;
architecture sim of s6_cmt_sfs is
signal CLK_DIVPULSE : slbit := '0';
signal CLKOUT_PERIOD : time := 0 ns;
signal R_CLKOUT : slbit := '0';
signal R_LOCKED : slbit := '0';
begin
proc_init : process
-- currently frequency limits taken from Spartan-6 speed grade -2
constant f_vcomin_pll : integer := 400;
constant f_vcomax_pll : integer := 1000;
constant f_pdmin_pll : integer := 19;
constant f_pdmax_pll : integer := 375;
variable t_vco : time := 0 ns;
variable t_vcomin : time := 0 ns;
variable t_vcomax : time := 0 ns;
variable t_pd : time := 0 ns;
variable t_pdmin : time := 0 ns;
variable t_pdmax : time := 0 ns;
begin
-- validate generics
if not (GEN_TYPE = "PLL" or GEN_TYPE = "DCM") then
assert false
report "assert(GEN_TYPE='PLL' or GEN_TYPE='DCM')"
severity failure;
end if;
if VCO_DIVIDE/=1 or VCO_MULTIPLY/=1 or OUT_DIVIDE/=1 then
if GEN_TYPE = "PLL" then
-- check DIV/MULT parameter range
if VCO_DIVIDE<1 or VCO_DIVIDE>52 or
VCO_MULTIPLY<1 or VCO_MULTIPLY>64 or
OUT_DIVIDE<1 or OUT_DIVIDE>128
then
assert false
report
"assert(VCO_DIVIDE in 1:52 VCO_MULTIPLY in 1:64 OUT_DIVIDE in 1:128)"
severity failure;
end if;
-- setup VCO and PD range check boundaries
t_vcomin := (1000 ns / f_vcomax_pll) - 1 ps;
t_vcomax := (1000 ns / f_vcomin_pll) + 1 ps;
t_pdmin := (1000 ns / f_pdmax_pll) - 1 ps;
t_pdmax := (1000 ns / f_pdmin_pll) + 1 ps;
-- now check whether VCO and PD frequency is in range
t_pd := (1 ps * (1000.0*CLKIN_PERIOD)) * VCO_DIVIDE;
t_vco := t_pd / VCO_MULTIPLY;
if t_vco<t_vcomin or t_vco>t_vcomax then
assert false
report "assert(VCO frequency out of range)"
severity failure;
end if;
if t_pd<t_pdmin or t_pd>t_pdmax then
assert FALSE
report "assert(PD frequency out of range)"
severity failure;
end if;
end if; -- GEN_TYPE = "PLL"
if GEN_TYPE = "DCM" then
-- check DIV/MULT parameter range
if VCO_DIVIDE<1 or VCO_DIVIDE>32 or
VCO_MULTIPLY<2 or VCO_MULTIPLY>32 or
OUT_DIVIDE/=1
then
assert false
report
"assert(VCO_DIVIDE in 1:32 VCO_MULTIPLY in 2:32 OUT_DIVIDE=1)"
severity failure;
end if;
end if; -- GEN_TYPE = "MMCM"
end if; -- one factor /= 1
wait;
end process proc_init;
proc_clkin : process (CLKIN)
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : time := 0 ns;
variable t_period : time := 0 ns;
variable nclkin : integer := 1;
begin
if CLKIN'event then
if CLKIN = '1' then -- if CLKIN rising edge
if t_lastclkin > 0 ns then
t_lastperiod := t_period;
t_period := now - t_lastclkin;
CLKOUT_PERIOD <= (t_period * VCO_DIVIDE * OUT_DIVIDE) / VCO_MULTIPLY;
if t_lastperiod > 0 ns and abs(t_period-t_lastperiod) > 1 ps then
report "s6_cmt_sp_sfs: CLKIN unstable" severity warning;
end if;
end if;
t_lastclkin := now;
if t_period > 0 ns then
nclkin := nclkin - 1;
if nclkin <= 0 then
nclkin := VCO_DIVIDE * OUT_DIVIDE;
CLK_DIVPULSE <= '1';
R_LOCKED <= '1';
end if;
end if;
else -- if CLKIN falling edge
CLK_DIVPULSE <= '0';
end if;
end if;
end process proc_clkin;
proc_clkout : process
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : time := 0 ns;
variable t_period : time := 0 ns;
variable nclkin : integer := 1;
begin
loop
wait until CLK_DIVPULSE = '1';
for i in 1 to VCO_MULTIPLY loop
R_CLKOUT <= '1';
wait for CLKOUT_PERIOD/2;
R_CLKOUT <= '0';
if i /= VCO_MULTIPLY then
wait for CLKOUT_PERIOD/2;
end if;
end loop; -- i
end loop;
end process proc_clkout;
CLKFX <= R_CLKOUT;
LOCKED <= R_LOCKED;
end sim;
|
-- megafunction wizard: %ROM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: rom.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.0.0 Build 156 04/24/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY rom IS
PORT
(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END rom;
ARCHITECTURE SYN OF rom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock0 : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(15 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "sine.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 256,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
widthad_a => 8,
width_a => 16,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "sine.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
-- Retrieval info: PRIVATE: WidthData NUMERIC "16"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "sine.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity ROM is
generic ( load_file_name : string );
port ( sel : in std_logic;
address : in std_logic_vector;
data : inout std_logic_vector );
end entity ROM;
--------------------------------------------------
architecture behavioral of ROM is
begin
behavior : process is
subtype word is std_logic_vector(0 to data'length - 1);
type storage_array is
array (natural range 0 to 2**address'length - 1) of word;
variable storage : storage_array;
variable index : natural;
-- . . . -- other declarations
type load_file_type is file of word;
file load_file : load_file_type open read_mode is load_file_name;
begin
-- load ROM contents from load_file
index := 0;
while not endfile(load_file) loop
read(load_file, storage(index));
index := index + 1;
end loop;
-- respond to ROM accesses
loop
-- . . .
end loop;
end process behavior;
end architecture behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity ROM is
generic ( load_file_name : string );
port ( sel : in std_logic;
address : in std_logic_vector;
data : inout std_logic_vector );
end entity ROM;
--------------------------------------------------
architecture behavioral of ROM is
begin
behavior : process is
subtype word is std_logic_vector(0 to data'length - 1);
type storage_array is
array (natural range 0 to 2**address'length - 1) of word;
variable storage : storage_array;
variable index : natural;
-- . . . -- other declarations
type load_file_type is file of word;
file load_file : load_file_type open read_mode is load_file_name;
begin
-- load ROM contents from load_file
index := 0;
while not endfile(load_file) loop
read(load_file, storage(index));
index := index + 1;
end loop;
-- respond to ROM accesses
loop
-- . . .
end loop;
end process behavior;
end architecture behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity ROM is
generic ( load_file_name : string );
port ( sel : in std_logic;
address : in std_logic_vector;
data : inout std_logic_vector );
end entity ROM;
--------------------------------------------------
architecture behavioral of ROM is
begin
behavior : process is
subtype word is std_logic_vector(0 to data'length - 1);
type storage_array is
array (natural range 0 to 2**address'length - 1) of word;
variable storage : storage_array;
variable index : natural;
-- . . . -- other declarations
type load_file_type is file of word;
file load_file : load_file_type open read_mode is load_file_name;
begin
-- load ROM contents from load_file
index := 0;
while not endfile(load_file) loop
read(load_file, storage(index));
index := index + 1;
end loop;
-- respond to ROM accesses
loop
-- . . .
end loop;
end process behavior;
end architecture behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
entity registers_tb is end;
architecture registers_tb_arc of registers_tb is
signal clk: std_logic := '0';
signal reset_n: std_logic;
signal sel_a: std_logic_vector(4 downto 0);
signal reg_a_out: std_logic_vector(31 downto 0);
signal sel_b: std_logic_vector(4 downto 0);
signal reg_b_out: std_logic_vector(31 downto 0);
signal sel_c: std_logic_vector(4 downto 0);
signal write_c: std_logic;
signal reg_c_in: std_logic_vector(31 downto 0);
signal sel_d: std_logic_vector(4 downto 0);
signal write_d: std_logic;
signal reg_d_in: std_logic_vector(31 downto 0);
begin
clk <= not clk after 13 ns;
reset_n <= '0', '1' after 100 ns;
process
procedure write_c_reg(data: std_logic_vector(31 downto 0); sel: std_logic_vector(4 downto 0))is
begin
reg_c_in <= data;
sel_c <= sel;
write_c <= '1';
wait until rising_edge(clk); wait for 1 ns;
write_c <= '0';
wait for 1 ns;
end procedure write_c_reg;
begin
sel_a <= (others => '0');
sel_b <= (others => '0');
sel_c <= (others => '0');
reg_c_in <= (others => '0');
write_c <= '0';
wait for 140 ns;
write_c_reg(x"ABCDEF01", "00110");
write_c_reg(x"12345678", "10110");
write_c_reg(x"F1E2D3C4", "00001");
wait for 200 ns;
sel_a <= "00001";
sel_b <= "10110";
wait for 37 ns;
-- read and write on the same cycle
sel_b <= "00110";
write_c_reg(x"555DEF01", "00110");
wait;
end process;
uut: entity work.registers(registers_arc)
generic map
(
NREGS_LOG2 => 5
)
port map
(
clk => clk,
reset_n => reset_n,
sel_a => sel_a,
reg_a_out => reg_a_out,
sel_b => sel_b,
reg_b_out => reg_b_out,
sel_c => sel_c,
write_c => write_c,
reg_c_in => reg_c_in,
sel_d => sel_d,
write_d => write_d,
reg_d_in => reg_d_in
);
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
entity registers_tb is end;
architecture registers_tb_arc of registers_tb is
signal clk: std_logic := '0';
signal reset_n: std_logic;
signal sel_a: std_logic_vector(4 downto 0);
signal reg_a_out: std_logic_vector(31 downto 0);
signal sel_b: std_logic_vector(4 downto 0);
signal reg_b_out: std_logic_vector(31 downto 0);
signal sel_c: std_logic_vector(4 downto 0);
signal write_c: std_logic;
signal reg_c_in: std_logic_vector(31 downto 0);
signal sel_d: std_logic_vector(4 downto 0);
signal write_d: std_logic;
signal reg_d_in: std_logic_vector(31 downto 0);
begin
clk <= not clk after 13 ns;
reset_n <= '0', '1' after 100 ns;
process
procedure write_c_reg(data: std_logic_vector(31 downto 0); sel: std_logic_vector(4 downto 0))is
begin
reg_c_in <= data;
sel_c <= sel;
write_c <= '1';
wait until rising_edge(clk); wait for 1 ns;
write_c <= '0';
wait for 1 ns;
end procedure write_c_reg;
begin
sel_a <= (others => '0');
sel_b <= (others => '0');
sel_c <= (others => '0');
reg_c_in <= (others => '0');
write_c <= '0';
wait for 140 ns;
write_c_reg(x"ABCDEF01", "00110");
write_c_reg(x"12345678", "10110");
write_c_reg(x"F1E2D3C4", "00001");
wait for 200 ns;
sel_a <= "00001";
sel_b <= "10110";
wait for 37 ns;
-- read and write on the same cycle
sel_b <= "00110";
write_c_reg(x"555DEF01", "00110");
wait;
end process;
uut: entity work.registers(registers_arc)
generic map
(
NREGS_LOG2 => 5
)
port map
(
clk => clk,
reset_n => reset_n,
sel_a => sel_a,
reg_a_out => reg_a_out,
sel_b => sel_b,
reg_b_out => reg_b_out,
sel_c => sel_c,
write_c => write_c,
reg_c_in => reg_c_in,
sel_d => sel_d,
write_d => write_d,
reg_d_in => reg_d_in
);
end;
|
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`protect end_protected
|
-------------------------------------------------------------------------------
-- srl_fifo.vhd
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003,2012,2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
--
-- History:
-- goran 2001-06-12 First Version
-- stefana 2012-03-16 Added support for 32 processors and external BSCAN
-- stefana 2013-11-01 Added support for depth 32
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity SRL_FIFO is
generic (
C_DATA_BITS : natural := 8;
C_DEPTH : natural := 16
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic
);
end entity SRL_FIFO;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
architecture IMP of SRL_FIFO is
constant C_ADDR_BITS : integer := 4 + boolean'pos(C_DEPTH = 32);
signal Addr : std_logic_vector(0 to C_ADDR_BITS - 1);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic := '0';
signal data_Exists_I : std_logic := '0';
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to C_ADDR_BITS - 1);
signal sum_A : std_logic_vector(0 to C_ADDR_BITS - 1);
signal addr_cy : std_logic_vector(0 to C_ADDR_BITS - 1);
begin -- architecture IMP
assert (C_DEPTH = 16) or (C_DEPTH = 32) report "SRL FIFO: C_DEPTH must be 16 or 32" severity FAILURE;
buffer_Full <= '1' when (Addr = (0 to C_ADDR_BITS - 1 => '1')) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (Addr = (0 to C_ADDR_BITS - 1 => '0')) else '0';
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : process (Clk) is
begin -- process Data_Exists_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then
data_Exists_I <= '0';
else
data_Exists_I <= next_Data_Exists;
end if;
end if;
end process Data_Exists_DFF;
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to C_ADDR_BITS - 1 generate
begin
hsum_A(I) <= (FIFO_Read xor addr(I)) and (FIFO_Write or not buffer_Empty);
-- Don't need the last muxcy, addr_cy(C_ADDR_BITS) is not used anywhere
Used_MuxCY: if I < C_ADDR_BITS - 1 generate
begin
MUXCY_L_I : MUXCY_L
port map (
DI => addr(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
end generate Used_MuxCY;
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DATA_BITS - 1 generate
begin
D16 : if C_DEPTH = 16 generate
begin
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => Addr(0), -- [in std_logic]
A1 => Addr(1), -- [in std_logic]
A2 => Addr(2), -- [in std_logic]
A3 => Addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate D16;
D32 : if C_DEPTH = 32 generate
begin
SRLC32E_I : SRLC32E
-- pragma translate_off
generic map (
INIT => x"00000000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
CLK => Clk, -- [in std_logic]
A(4) => Addr(4), -- [in std_logic]
A(3) => Addr(3), -- [in std_logic]
A(2) => Addr(2), -- [in std_logic]
A(1) => Addr(1), -- [in std_logic]
A(0) => Addr(0), -- [in std_logic]
Q31 => open, -- [out std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate D32;
end generate FIFO_RAM;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- srl_fifo.vhd
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003,2012,2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
--
-- History:
-- goran 2001-06-12 First Version
-- stefana 2012-03-16 Added support for 32 processors and external BSCAN
-- stefana 2013-11-01 Added support for depth 32
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity SRL_FIFO is
generic (
C_DATA_BITS : natural := 8;
C_DEPTH : natural := 16
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic
);
end entity SRL_FIFO;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
architecture IMP of SRL_FIFO is
constant C_ADDR_BITS : integer := 4 + boolean'pos(C_DEPTH = 32);
signal Addr : std_logic_vector(0 to C_ADDR_BITS - 1);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic := '0';
signal data_Exists_I : std_logic := '0';
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to C_ADDR_BITS - 1);
signal sum_A : std_logic_vector(0 to C_ADDR_BITS - 1);
signal addr_cy : std_logic_vector(0 to C_ADDR_BITS - 1);
begin -- architecture IMP
assert (C_DEPTH = 16) or (C_DEPTH = 32) report "SRL FIFO: C_DEPTH must be 16 or 32" severity FAILURE;
buffer_Full <= '1' when (Addr = (0 to C_ADDR_BITS - 1 => '1')) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (Addr = (0 to C_ADDR_BITS - 1 => '0')) else '0';
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : process (Clk) is
begin -- process Data_Exists_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then
data_Exists_I <= '0';
else
data_Exists_I <= next_Data_Exists;
end if;
end if;
end process Data_Exists_DFF;
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to C_ADDR_BITS - 1 generate
begin
hsum_A(I) <= (FIFO_Read xor addr(I)) and (FIFO_Write or not buffer_Empty);
-- Don't need the last muxcy, addr_cy(C_ADDR_BITS) is not used anywhere
Used_MuxCY: if I < C_ADDR_BITS - 1 generate
begin
MUXCY_L_I : MUXCY_L
port map (
DI => addr(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
end generate Used_MuxCY;
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DATA_BITS - 1 generate
begin
D16 : if C_DEPTH = 16 generate
begin
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => Addr(0), -- [in std_logic]
A1 => Addr(1), -- [in std_logic]
A2 => Addr(2), -- [in std_logic]
A3 => Addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate D16;
D32 : if C_DEPTH = 32 generate
begin
SRLC32E_I : SRLC32E
-- pragma translate_off
generic map (
INIT => x"00000000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
CLK => Clk, -- [in std_logic]
A(4) => Addr(4), -- [in std_logic]
A(3) => Addr(3), -- [in std_logic]
A(2) => Addr(2), -- [in std_logic]
A(1) => Addr(1), -- [in std_logic]
A(0) => Addr(0), -- [in std_logic]
Q31 => open, -- [out std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate D32;
end generate FIFO_RAM;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- srl_fifo.vhd
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003,2012,2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
--
-- History:
-- goran 2001-06-12 First Version
-- stefana 2012-03-16 Added support for 32 processors and external BSCAN
-- stefana 2013-11-01 Added support for depth 32
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity SRL_FIFO is
generic (
C_DATA_BITS : natural := 8;
C_DEPTH : natural := 16
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic
);
end entity SRL_FIFO;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
architecture IMP of SRL_FIFO is
constant C_ADDR_BITS : integer := 4 + boolean'pos(C_DEPTH = 32);
signal Addr : std_logic_vector(0 to C_ADDR_BITS - 1);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic := '0';
signal data_Exists_I : std_logic := '0';
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to C_ADDR_BITS - 1);
signal sum_A : std_logic_vector(0 to C_ADDR_BITS - 1);
signal addr_cy : std_logic_vector(0 to C_ADDR_BITS - 1);
begin -- architecture IMP
assert (C_DEPTH = 16) or (C_DEPTH = 32) report "SRL FIFO: C_DEPTH must be 16 or 32" severity FAILURE;
buffer_Full <= '1' when (Addr = (0 to C_ADDR_BITS - 1 => '1')) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (Addr = (0 to C_ADDR_BITS - 1 => '0')) else '0';
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : process (Clk) is
begin -- process Data_Exists_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then
data_Exists_I <= '0';
else
data_Exists_I <= next_Data_Exists;
end if;
end if;
end process Data_Exists_DFF;
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to C_ADDR_BITS - 1 generate
begin
hsum_A(I) <= (FIFO_Read xor addr(I)) and (FIFO_Write or not buffer_Empty);
-- Don't need the last muxcy, addr_cy(C_ADDR_BITS) is not used anywhere
Used_MuxCY: if I < C_ADDR_BITS - 1 generate
begin
MUXCY_L_I : MUXCY_L
port map (
DI => addr(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
end generate Used_MuxCY;
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DATA_BITS - 1 generate
begin
D16 : if C_DEPTH = 16 generate
begin
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => Addr(0), -- [in std_logic]
A1 => Addr(1), -- [in std_logic]
A2 => Addr(2), -- [in std_logic]
A3 => Addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate D16;
D32 : if C_DEPTH = 32 generate
begin
SRLC32E_I : SRLC32E
-- pragma translate_off
generic map (
INIT => x"00000000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
CLK => Clk, -- [in std_logic]
A(4) => Addr(4), -- [in std_logic]
A(3) => Addr(3), -- [in std_logic]
A(2) => Addr(2), -- [in std_logic]
A(1) => Addr(1), -- [in std_logic]
A(0) => Addr(0), -- [in std_logic]
Q31 => open, -- [out std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate D32;
end generate FIFO_RAM;
end architecture IMP;
|
-------------------------------------------------------------------------------
-- srl_fifo.vhd
-------------------------------------------------------------------------------
--
-- (c) Copyright 2003,2012,2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
--
-- History:
-- goran 2001-06-12 First Version
-- stefana 2012-03-16 Added support for 32 processors and external BSCAN
-- stefana 2013-11-01 Added support for depth 32
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity SRL_FIFO is
generic (
C_DATA_BITS : natural := 8;
C_DEPTH : natural := 16
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic
);
end entity SRL_FIFO;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
architecture IMP of SRL_FIFO is
constant C_ADDR_BITS : integer := 4 + boolean'pos(C_DEPTH = 32);
signal Addr : std_logic_vector(0 to C_ADDR_BITS - 1);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic := '0';
signal data_Exists_I : std_logic := '0';
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to C_ADDR_BITS - 1);
signal sum_A : std_logic_vector(0 to C_ADDR_BITS - 1);
signal addr_cy : std_logic_vector(0 to C_ADDR_BITS - 1);
begin -- architecture IMP
assert (C_DEPTH = 16) or (C_DEPTH = 32) report "SRL FIFO: C_DEPTH must be 16 or 32" severity FAILURE;
buffer_Full <= '1' when (Addr = (0 to C_ADDR_BITS - 1 => '1')) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (Addr = (0 to C_ADDR_BITS - 1 => '0')) else '0';
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : process (Clk) is
begin -- process Data_Exists_DFF
if Clk'event and Clk = '1' then -- rising clock edge
if Reset = '1' then
data_Exists_I <= '0';
else
data_Exists_I <= next_Data_Exists;
end if;
end if;
end process Data_Exists_DFF;
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to C_ADDR_BITS - 1 generate
begin
hsum_A(I) <= (FIFO_Read xor addr(I)) and (FIFO_Write or not buffer_Empty);
-- Don't need the last muxcy, addr_cy(C_ADDR_BITS) is not used anywhere
Used_MuxCY: if I < C_ADDR_BITS - 1 generate
begin
MUXCY_L_I : MUXCY_L
port map (
DI => addr(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
end generate Used_MuxCY;
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DATA_BITS - 1 generate
begin
D16 : if C_DEPTH = 16 generate
begin
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => Addr(0), -- [in std_logic]
A1 => Addr(1), -- [in std_logic]
A2 => Addr(2), -- [in std_logic]
A3 => Addr(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate D16;
D32 : if C_DEPTH = 32 generate
begin
SRLC32E_I : SRLC32E
-- pragma translate_off
generic map (
INIT => x"00000000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
CLK => Clk, -- [in std_logic]
A(4) => Addr(4), -- [in std_logic]
A(3) => Addr(3), -- [in std_logic]
A(2) => Addr(2), -- [in std_logic]
A(1) => Addr(1), -- [in std_logic]
A(0) => Addr(0), -- [in std_logic]
Q31 => open, -- [out std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate D32;
end generate FIFO_RAM;
end architecture IMP;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package spwcomp is
component grspwc2 is
generic(
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1;
tech : integer;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--time iface
tickin : in std_ulogic;
tickinraw : in std_ulogic;
timein : in std_logic_vector(7 downto 0);
tickindone : out std_ulogic;
tickout : out std_ulogic;
tickoutraw : out std_ulogic;
timeout : out std_logic_vector(7 downto 0);
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(9 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(9 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0';
--parallel rx data out
rxdav : out std_ulogic;
rxdataout : out std_logic_vector(8 downto 0);
loopback : out std_ulogic
);
end component;
component grspwc is
generic(
sysfreq : integer := 40000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
tech : integer;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(9 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0';
rmapact : out std_ulogic
);
end component;
component grspwc_axcelerator is
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspwc_unisim is
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(1 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--clk bufs
rxclki : in std_logic_vector(1 downto 0);
--rx ahb fifo
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(4 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(31 downto 0);
rxwaddress : out std_logic_vector(4 downto 0);
rxrdata : in std_logic_vector(31 downto 0);
--tx ahb fifo
txrenable : out std_ulogic;
txraddress : out std_logic_vector(4 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(31 downto 0);
txwaddress : out std_logic_vector(4 downto 0);
txrdata : in std_logic_vector(31 downto 0);
--nchar fifo
ncrenable : out std_ulogic;
ncraddress : out std_logic_vector(5 downto 0);
ncwrite : out std_ulogic;
ncwdata : out std_logic_vector(8 downto 0);
ncwaddress : out std_logic_vector(5 downto 0);
ncrdata : in std_logic_vector(8 downto 0);
--rmap buf
rmrenable : out std_ulogic;
rmraddress : out std_logic_vector(7 downto 0);
rmwrite : out std_ulogic;
rmwdata : out std_logic_vector(7 downto 0);
rmwaddress : out std_logic_vector(7 downto 0);
rmrdata : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspw_gen is
generic(
tech : integer := 0;
sysfreq : integer := 10000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
ports : integer range 1 to 2 := 1;
memtech : integer := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
rxclk : in std_logic_vector(1 downto 0);
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(9 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end component;
component grspw_codec_core is
generic(
ports : integer range 1 to 2 := 1;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
fifosize : integer range 16 to 2048 := 64;
tech : integer;
scantest : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--link fsm
linkdisabled : in std_ulogic;
linkstart : in std_ulogic;
autostart : in std_ulogic;
portsel : in std_ulogic;
noportforce : in std_ulogic;
rdivisor : in std_logic_vector(7 downto 0);
idivisor : in std_logic_vector(7 downto 0);
state : out std_logic_vector(2 downto 0);
actport : out std_ulogic;
dconnecterr : out std_ulogic;
crederr : out std_ulogic;
escerr : out std_ulogic;
parerr : out std_ulogic;
--rx fifo signals
rxrenable : out std_ulogic;
rxraddress : out std_logic_vector(10 downto 0);
rxwrite : out std_ulogic;
rxwdata : out std_logic_vector(9 downto 0);
rxwaddress : out std_logic_vector(10 downto 0);
rxrdata : in std_logic_vector(9 downto 0);
rxaccess : out std_ulogic;
--rx iface
rxicharav : out std_ulogic;
rxicharcnt : out std_logic_vector(11 downto 0);
rxichar : out std_logic_vector(8 downto 0);
rxiread : in std_ulogic;
rxififorst : in std_ulogic;
--tx fifo signals
txrenable : out std_ulogic;
txraddress : out std_logic_vector(10 downto 0);
txwrite : out std_ulogic;
txwdata : out std_logic_vector(8 downto 0);
txwaddress : out std_logic_vector(10 downto 0);
txrdata : in std_logic_vector(8 downto 0);
txaccess : out std_ulogic;
--tx iface
txicharcnt : out std_logic_vector(11 downto 0);
txifull : out std_ulogic;
txiempty : out std_ulogic;
txiwrite : in std_ulogic;
txichar : in std_logic_vector(8 downto 0);
txififorst : in std_ulogic;
txififorstact: out std_ulogic;
--time iface
tickin : in std_ulogic;
timein : in std_logic_vector(7 downto 0);
tickin_done : out std_ulogic;
tickout : out std_ulogic;
timeout : out std_logic_vector(7 downto 0)
);
end component;
component grspw2_gen is
generic(
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
scantest : integer range 0 to 1 := 0;
ports : integer range 1 to 2 := 1;
dmachan : integer range 1 to 4 := 1;
tech : integer;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
techfifo : integer range 0 to 1 := 1;
memtech : integer := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--time iface
tickin : in std_ulogic;
tickinraw : in std_ulogic;
timein : in std_logic_vector(7 downto 0);
tickindone : out std_ulogic;
tickout : out std_ulogic;
tickoutraw : out std_ulogic;
timeout : out std_logic_vector(7 downto 0);
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0';
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
--parallel rx data out
rxdav : out std_ulogic;
rxdataout : out std_logic_vector(8 downto 0)
);
end component;
component grspw_codec_gen is
generic(
ports : integer range 1 to 2 := 1;
input_type : integer range 0 to 4 := 0;
output_type : integer range 0 to 2 := 0;
rxtx_sameclk : integer range 0 to 1 := 0;
fifosize : integer range 16 to 2048 := 64;
tech : integer;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxclk0 : in std_ulogic;
rxclk1 : in std_ulogic;
txclk : in std_ulogic;
txclkn : in std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
--spw in
d : in std_logic_vector(3 downto 0);
dv : in std_logic_vector(3 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(3 downto 0);
so : out std_logic_vector(3 downto 0);
--link fsm
linkdisabled : in std_ulogic;
linkstart : in std_ulogic;
autostart : in std_ulogic;
portsel : in std_ulogic;
noportforce : in std_ulogic;
rdivisor : in std_logic_vector(7 downto 0);
idivisor : in std_logic_vector(7 downto 0);
state : out std_logic_vector(2 downto 0);
actport : out std_ulogic;
dconnecterr : out std_ulogic;
crederr : out std_ulogic;
escerr : out std_ulogic;
parerr : out std_ulogic;
--rx iface
rxicharav : out std_ulogic;
rxicharcnt : out std_logic_vector(11 downto 0);
rxichar : out std_logic_vector(8 downto 0);
rxiread : in std_ulogic;
rxififorst : in std_ulogic;
--tx iface
txicharcnt : out std_logic_vector(11 downto 0);
txifull : out std_ulogic;
txiempty : out std_ulogic;
txiwrite : in std_ulogic;
txichar : in std_logic_vector(8 downto 0);
txififorst : in std_ulogic;
txififorstact: out std_ulogic;
--time iface
tickin : in std_ulogic;
timein : in std_logic_vector(7 downto 0);
tickin_done : out std_ulogic;
tickout : out std_ulogic;
timeout : out std_logic_vector(7 downto 0);
--misc
merror : out std_ulogic
);
end component;
end package;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_sg_if.vhd
-- Description: This entity is the MM2S Scatter Gather Interface for Descriptor
-- Fetches and Updates.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library proc_common_v4_0;
use proc_common_v4_0.srl_fifo_f;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_sg_if is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1 ;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0 ;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 ;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- Master AXI Control Stream Data Width
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0 ;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- SG MM2S Descriptor Fetch AXI Stream In --
m_axis_mm2s_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_ftch_tvalid : in std_logic ; --
m_axis_mm2s_ftch_tready : out std_logic ; --
m_axis_mm2s_ftch_tlast : in std_logic ; --
m_axis_mm2s_ftch_tdata_new : in std_logic_vector --
(96 downto 0); --
m_axis_mm2s_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_mm2s_ftch_tvalid_new : in std_logic ; --
m_axis_ftch1_desc_available : in std_logic;
--
--
-- SG MM2S Descriptor Update AXI Stream Out --
s_axis_mm2s_updtptr_tdata : out std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0); --
s_axis_mm2s_updtptr_tvalid : out std_logic ; --
s_axis_mm2s_updtptr_tready : in std_logic ; --
s_axis_mm2s_updtptr_tlast : out std_logic ; --
--
s_axis_mm2s_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_mm2s_updtsts_tvalid : out std_logic ; --
s_axis_mm2s_updtsts_tready : in std_logic ; --
s_axis_mm2s_updtsts_tlast : out std_logic ; --
--
--
-- MM2S Descriptor Fetch Request (from mm2s_sm) --
desc_available : out std_logic ; --
desc_fetch_req : in std_logic ; --
desc_fetch_done : out std_logic ; --
updt_pending : out std_logic ;
packet_in_progress : out std_logic ; --
--
-- MM2S Descriptor Update Request (from mm2s_sm) --
desc_update_done : out std_logic ; --
--
mm2s_sts_received_clr : out std_logic ; --
mm2s_sts_received : in std_logic ; --
mm2s_ftch_stale_desc : in std_logic ; --
mm2s_done : in std_logic ; --
mm2s_interr : in std_logic ; --
mm2s_slverr : in std_logic ; --
mm2s_decerr : in std_logic ; --
mm2s_tag : in std_logic_vector(3 downto 0) ; --
mm2s_halt : in std_logic ; --
--
-- Control Stream Output --
cntrlstrm_fifo_wren : out std_logic ; --
cntrlstrm_fifo_din : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : in std_logic ; --
--
--
-- MM2S Descriptor Field Output --
mm2s_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
mm2s_new_curdesc_wren : out std_logic ; --
--
mm2s_desc_baddress : out std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_desc_blength : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_v : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_blength_s : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
mm2s_desc_eof : out std_logic ; --
mm2s_desc_sof : out std_logic ; --
mm2s_desc_cmplt : out std_logic ; --
mm2s_desc_info : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app0 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app1 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app2 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app3 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
mm2s_desc_app4 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) --
);
end axi_dma_mm2s_sg_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_sg_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Status reserved bits
constant RESERVED_STS : std_logic_vector(4 downto 0) := (others => '0');
-- Used to determine when Control word is coming, in order to check SOF bit.
-- This then indicates that the app fields need to be directed towards the
-- control stream fifo.
-- Word Five Count
-- Incrementing these counts by 2 as i am now sending two extra fields from BD
--constant SEVEN_COUNT : std_logic_vector(3 downto 0) := "1011"; --"0111";
constant SEVEN_COUNT : std_logic_vector(3 downto 0) := "0001";
-- Word Six Count
--constant EIGHT_COUNT : std_logic_vector(3 downto 0) := "0101"; --"1000";
constant EIGHT_COUNT : std_logic_vector(3 downto 0) := "0010";
-- Word Seven Count
--constant NINE_COUNT : std_logic_vector(3 downto 0) := "1010"; --"1001";
constant NINE_COUNT : std_logic_vector(3 downto 0) := "0011";
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_shftenbl : std_logic := '0';
signal ftch_tready : std_logic := '0';
signal desc_fetch_done_i : std_logic := '0';
signal desc_reg12 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg11 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg10 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg9 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg8 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg7 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg6 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg5 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_dummy : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_dummy1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_curdesc_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_curdesc_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_baddr_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_baddr_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_blength_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_blength_v_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal mm2s_desc_blength_s_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
-- Fetch control signals for driving out control app stream
signal analyze_control : std_logic := '0';
signal redirect_app : std_logic := '0';
signal redirect_app_d1 : std_logic := '0';
signal redirect_app_re : std_logic := '0';
signal redirect_app_hold : std_logic := '0';
signal mask_fifo_write : std_logic := '0';
-- Current descriptor control and fetch throttle control
signal mm2s_new_curdesc_wren_i : std_logic := '0';
signal mm2s_pending_update : std_logic := '0';
signal mm2s_pending_ptr_updt : std_logic := '0';
-- Descriptor Update Signals
signal mm2s_complete : std_logic := '0';
signal mm2s_xferd_bytes : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_xferd_bytes_int : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
-- Update Descriptor Pointer Holding Registers
signal updt_desc_reg0 : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH downto 0) := (others => '0');
signal updt_desc_reg1 : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH downto 0) := (others => '0');
-- Update Descriptor Status Holding Register
signal updt_desc_reg2 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
-- Pointer shift control
signal updt_shftenbl : std_logic := '0';
-- Update pointer stream
signal updtptr_tvalid : std_logic := '0';
signal updtptr_tlast : std_logic := '0';
signal updtptr_tdata : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
-- Update status stream
signal updtsts_tvalid : std_logic := '0';
signal updtsts_tlast : std_logic := '0';
signal updtsts_tdata : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
-- Status control
signal sts_received : std_logic := '0';
signal sts_received_d1 : std_logic := '0';
signal sts_received_re : std_logic := '0';
-- Queued Update signals
signal updt_data_clr : std_logic := '0';
signal updt_sts_clr : std_logic := '0';
signal updt_data : std_logic := '0';
signal updt_sts : std_logic := '0';
signal packet_start : std_logic := '0';
signal packet_end : std_logic := '0';
signal mm2s_halt_d1_cdc_tig : std_logic := '0';
signal mm2s_halt_cdc_d2 : std_logic := '0';
signal mm2s_halt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF mm2s_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF mm2s_halt_cdc_d2 : SIGNAL IS "true";
signal temp : std_logic := '0';
signal m_axis_mm2s_ftch_tlast_new : std_logic := '1';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Drive buffer length out
mm2s_desc_blength <= mm2s_desc_blength_i;
mm2s_desc_blength_v <= mm2s_desc_blength_v_i;
mm2s_desc_blength_s <= mm2s_desc_blength_s_i;
-- Drive fetch request done on tlast
desc_fetch_done_i <= m_axis_mm2s_ftch_tlast_new
and m_axis_mm2s_ftch_tvalid_new;
-- pass out of module
desc_fetch_done <= desc_fetch_done_i;
-- Shift in data from SG engine if tvalid and fetch request
ftch_shftenbl <= m_axis_mm2s_ftch_tvalid_new
and ftch_tready
and desc_fetch_req
and not mm2s_pending_update;
-- Passed curdes write out to register module
mm2s_new_curdesc_wren <= desc_fetch_done_i; --mm2s_new_curdesc_wren_i;
-- tvalid asserted means descriptor availble
desc_available <= m_axis_ftch1_desc_available; --m_axis_mm2s_ftch_tvalid_new;
--***************************************************************************--
--** Register DataMover Halt to secondary if needed
--***************************************************************************--
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt will remain asserted until halt_cmplt detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => mm2s_halt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- mm2s_halt_d1_cdc_tig <= '0';
-- -- mm2s_halt_d2 <= '0';
-- -- else
-- mm2s_halt_d1_cdc_tig <= mm2s_halt;
-- mm2s_halt_cdc_d2 <= mm2s_halt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
mm2s_halt_d2 <= mm2s_halt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
mm2s_halt_d2 <= mm2s_halt;
end generate GEN_FOR_SYNC;
--***************************************************************************--
--** Descriptor Fetch Logic **--
--***************************************************************************--
packet_start <= '1' when mm2s_new_curdesc_wren_i ='1'
and desc_reg6(DESC_SOF_BIT) = '1'
else '0';
packet_end <= '1' when mm2s_new_curdesc_wren_i ='1'
and desc_reg6(DESC_EOF_BIT) = '1'
else '0';
REG_PACKET_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or packet_end = '1')then
packet_in_progress <= '0';
elsif(packet_start = '1')then
packet_in_progress <= '1';
end if;
end if;
end process REG_PACKET_PROGRESS;
-- Status/Control stream enabled therefore APP fields are included
GEN_FTCHIF_WITH_APP : if (C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
-- Control Stream Ethernet TAG
constant ETHERNET_CNTRL_TAG : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH - 1 downto 0)
:= X"A000_0000";
begin
desc_reg7(30 downto 0) <= (others => '0');
desc_reg7 (DESC_STS_CMPLTD_BIT) <= m_axis_mm2s_ftch_tdata_new (64); -- downto 64);
desc_reg6 <= m_axis_mm2s_ftch_tdata_new (63 downto 32);
desc_reg2 <= m_axis_mm2s_ftch_tdata_new (31 downto 0);
desc_reg0 <= m_axis_mm2s_ftch_tdata_new (96 downto 65);
mm2s_desc_curdesc_lsb <= desc_reg0;
mm2s_desc_curdesc_msb <= (others => '0'); --desc_reg1;
mm2s_desc_baddr_lsb <= desc_reg2;
mm2s_desc_baddr_msb <= (others => '0'); --desc_reg3;
-- desc 5 are reserved and thus don't care
-- CR 583779, need to pass on tuser and cache information
mm2s_desc_info <= (others => '0'); --desc_reg4; -- this coincides with desc_fetch_done
mm2s_desc_blength_i <= desc_reg6(DESC_BLENGTH_MSB_BIT downto DESC_BLENGTH_LSB_BIT);
mm2s_desc_blength_v_i <= (others => '0');
mm2s_desc_blength_s_i <= (others => '0');
mm2s_desc_eof <= desc_reg6(DESC_EOF_BIT);
mm2s_desc_sof <= desc_reg6(DESC_SOF_BIT);
mm2s_desc_cmplt <= desc_reg7(DESC_STS_CMPLTD_BIT);
mm2s_desc_app0 <= desc_reg8;
mm2s_desc_app1 <= desc_reg9;
mm2s_desc_app2 <= desc_reg10;
mm2s_desc_app3 <= desc_reg11;
mm2s_desc_app4 <= desc_reg12;
-- Drive ready if descriptor fetch request is being made
-- If not redirecting app fields then drive ready based on sm request
-- If redirecting app fields then drive ready based on room in cntrl strm fifo
ftch_tready <= desc_fetch_req -- desc fetch request
and not mm2s_pending_update; -- no pntr updates pending
m_axis_mm2s_ftch_tready <= ftch_tready;
redirect_app <= '0';
cntrlstrm_fifo_din <= (others => '0');
cntrlstrm_fifo_wren <= '0';
end generate GEN_FTCHIF_WITH_APP;
-- Status/Control stream diabled therefore APP fields are NOT included
GEN_FTCHIF_WITHOUT_APP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
GEN_NO_MCDMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
desc_reg7(30 downto 0) <= (others => '0');
desc_reg7(DESC_STS_CMPLTD_BIT) <= m_axis_mm2s_ftch_tdata_new (64); --95 downto 64);
desc_reg6 <= m_axis_mm2s_ftch_tdata_new (63 downto 32);
desc_reg2 <= m_axis_mm2s_ftch_tdata_new (31 downto 0);
desc_reg0 <= m_axis_mm2s_ftch_tdata_new (96 downto 65); --127 downto 96);
mm2s_desc_curdesc_lsb <= desc_reg0;
mm2s_desc_curdesc_msb <= (others => '0'); --desc_reg1;
mm2s_desc_baddr_lsb <= desc_reg2;
mm2s_desc_baddr_msb <= (others => '0'); --desc_reg3;
-- desc 4 and desc 5 are reserved and thus don't care
-- CR 583779, need to send the user and xchache info
mm2s_desc_info <= (others => '0'); --desc_reg4;
mm2s_desc_blength_i <= desc_reg6(DESC_BLENGTH_MSB_BIT downto DESC_BLENGTH_LSB_BIT);
mm2s_desc_blength_v_i <= (others => '0');
mm2s_desc_blength_s_i <= (others => '0');
mm2s_desc_eof <= desc_reg6(DESC_EOF_BIT);
mm2s_desc_sof <= desc_reg6(DESC_SOF_BIT);
mm2s_desc_cmplt <= desc_reg7(DESC_STS_CMPLTD_BIT);
mm2s_desc_app0 <= (others => '0');
mm2s_desc_app1 <= (others => '0');
mm2s_desc_app2 <= (others => '0');
mm2s_desc_app3 <= (others => '0');
mm2s_desc_app4 <= (others => '0');
end generate GEN_NO_MCDMA;
GEN_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
desc_reg7(30 downto 0) <= (others => '0');
desc_reg7 (DESC_STS_CMPLTD_BIT) <= m_axis_mm2s_ftch_tdata_new (64); --95 downto 64);
desc_reg6 <= m_axis_mm2s_ftch_tdata_new (63 downto 32);
desc_reg2 <= m_axis_mm2s_ftch_tdata_new (31 downto 0);
desc_reg0 <= m_axis_mm2s_ftch_tdata_new (96 downto 65); --127 downto 96);
desc_reg4 <= m_axis_mm2s_ftch_tdata_mcdma_new (31 downto 0); --63 downto 32);
desc_reg5 <= m_axis_mm2s_ftch_tdata_mcdma_new (63 downto 32);
mm2s_desc_curdesc_lsb <= desc_reg0;
mm2s_desc_curdesc_msb <= (others => '0'); --desc_reg1;
mm2s_desc_baddr_lsb <= desc_reg2;
mm2s_desc_baddr_msb <= (others => '0'); --desc_reg3;
-- As per new MCDMA descriptor
mm2s_desc_info <= desc_reg4; -- (31 downto 24) & desc_reg7 (23 downto 0);
mm2s_desc_blength_s_i <= "0000000" & desc_reg5(15 downto 0);
mm2s_desc_blength_v_i <= "0000000000" & desc_reg5(31 downto 19);
mm2s_desc_blength_i <= "0000000" & desc_reg6(15 downto 0);
mm2s_desc_eof <= desc_reg6(DESC_EOF_BIT);
mm2s_desc_sof <= desc_reg6(DESC_SOF_BIT);
mm2s_desc_cmplt <= '0' ; --desc_reg7(DESC_STS_CMPLTD_BIT); -- we are not considering the completed bit
mm2s_desc_app0 <= (others => '0');
mm2s_desc_app1 <= (others => '0');
mm2s_desc_app2 <= (others => '0');
mm2s_desc_app3 <= (others => '0');
mm2s_desc_app4 <= (others => '0');
end generate GEN_MCDMA;
-- Drive ready if descriptor fetch request is being made
ftch_tready <= desc_fetch_req -- desc fetch request
and not mm2s_pending_update; -- no pntr updates pending
m_axis_mm2s_ftch_tready <= ftch_tready;
cntrlstrm_fifo_wren <= '0';
cntrlstrm_fifo_din <= (others => '0');
end generate GEN_FTCHIF_WITHOUT_APP;
-------------------------------------------------------------------------------
-- BUFFER ADDRESS
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_BUFADDR : if C_M_AXI_MM2S_ADDR_WIDTH = 64 generate
mm2s_desc_baddress <= mm2s_desc_baddr_msb & mm2s_desc_baddr_lsb;
end generate GEN_NEW_64BIT_BUFADDR;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_BUFADDR : if C_M_AXI_MM2S_ADDR_WIDTH = 32 generate
mm2s_desc_baddress <= mm2s_desc_baddr_lsb;
end generate GEN_NEW_32BIT_BUFADDR;
-------------------------------------------------------------------------------
-- NEW CURRENT DESCRIPTOR
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
mm2s_new_curdesc <= mm2s_desc_curdesc_msb & mm2s_desc_curdesc_lsb;
end generate GEN_NEW_64BIT_CURDESC;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
mm2s_new_curdesc <= mm2s_desc_curdesc_lsb;
end generate GEN_NEW_32BIT_CURDESC;
mm2s_new_curdesc_wren_i <= desc_fetch_done_i;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
--*****************************************************************************
--** Pointer Update Logic
--*****************************************************************************
-----------------------------------------------------------------------
-- Capture LSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
-----------------------------------------------------------------------
UPDT_DESC_WRD0: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 <= (others => '0');
elsif(mm2s_new_curdesc_wren_i = '1')then
updt_desc_reg0 <= DESC_LAST
& mm2s_desc_curdesc_lsb;
end if;
end if;
end process UPDT_DESC_WRD0;
-----------------------------------------------------------------------
-- Capture MSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
-----------------------------------------------------------------------
UPDT_DESC_WRD1: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg1 <= (others => '0');
elsif(mm2s_new_curdesc_wren_i = '1')then
updt_desc_reg1 <= DESC_LAST
& mm2s_desc_curdesc_msb;
-- Shift data out on shift enable
elsif(updt_shftenbl = '1')then
updt_desc_reg1 <= (others => '0');
end if;
end if;
end process UPDT_DESC_WRD1;
-- Shift in data from SG engine if tvalid, tready, and not on last word
updt_shftenbl <= updt_data and updtptr_tvalid and s_axis_mm2s_updtptr_tready;
-- Update data done when updating data and tlast received and target
-- (i.e. SG Engine) is ready
updt_data_clr <= '1' when updtptr_tvalid = '1' and updtptr_tlast = '1'
and s_axis_mm2s_updtptr_tready = '1'
else '0';
-- When desc data ready for update set and hold flag until
-- data can be updated to queue. Note it may
-- be held off due to update of status
UPDT_DATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
updt_data <= '0';
-- clear flag when data update complete
-- elsif(updt_data_clr = '1')then
-- updt_data <= '0';
-- -- set flag when desc fetched as indicated
-- -- by curdesc wren
elsif(mm2s_new_curdesc_wren_i = '1')then
updt_data <= '1';
end if;
end if;
end process UPDT_DATA_PROCESS;
updtptr_tvalid <= updt_data;
updtptr_tlast <= updt_desc_reg0(C_S_AXIS_UPDPTR_TDATA_WIDTH);
updtptr_tdata <= updt_desc_reg0(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0);
--*****************************************************************************
--** Status Update Logic
--*****************************************************************************
mm2s_complete <= '1'; -- Fixed at '1'
---------------------------------------------------------------------------
-- Descriptor queuing turned on in sg engine therefore need to instantiate
-- fifo to hold fetch buffer lengths. Also need to throttle fetches
-- if pointer has not been updated yet or length fifo is full
---------------------------------------------------------------------------
GEN_UPDT_FOR_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
signal xb_fifo_reset : std_logic; -- xfer'ed bytes fifo reset
signal xb_fifo_full : std_logic; -- xfer'ed bytes fifo full
begin
-----------------------------------------------------------------------
-- Need to flag a pending pointer update to prevent subsequent fetch of
-- descriptor from stepping on the stored pointer, and buffer length
-----------------------------------------------------------------------
REG_PENDING_UPDT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
mm2s_pending_ptr_updt <= '0';
elsif (desc_fetch_done_i = '1') then --(mm2s_new_curdesc_wren_i = '1')then
mm2s_pending_ptr_updt <= '1';
end if;
end if;
end process REG_PENDING_UPDT;
-- Pointer pending update or xferred bytes fifo full
mm2s_pending_update <= mm2s_pending_ptr_updt or xb_fifo_full;
updt_pending <= mm2s_pending_update;
-----------------------------------------------------------------------
-- On MM2S transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
GEN_MICRO_DMA : if C_MICRO_DMA = 1 generate
mm2s_xferd_bytes <= (others => '0');
xb_fifo_full <= '0';
end generate GEN_MICRO_DMA;
GEN_NO_MICRO_DMA : if C_MICRO_DMA = 0 generate
XFERRED_BYTE_FIFO : entity proc_common_v4_0.srl_fifo_f
generic map(
C_DWIDTH => BUFFER_LENGTH_WIDTH ,
C_DEPTH => 16 ,
C_FAMILY => C_FAMILY
)
port map(
Clk => m_axi_sg_aclk ,
Reset => xb_fifo_reset ,
FIFO_Write => desc_fetch_done_i, --mm2s_new_curdesc_wren_i ,
Data_In => mm2s_desc_blength_i ,
FIFO_Read => sts_received_re ,
Data_Out => mm2s_xferd_bytes ,
FIFO_Empty => open ,
FIFO_Full => xb_fifo_full ,
Addr => open
);
end generate GEN_NO_MICRO_DMA;
xb_fifo_reset <= not m_axi_sg_aresetn;
-- clear status received flag in cmdsts_if to
-- allow more status to be received from datamover
mm2s_sts_received_clr <= updt_sts_clr;
-- Generate a rising edge off status received in order to
-- flag status update
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= mm2s_sts_received;
end if;
end if;
end process REG_STATUS;
-- CR566306 - status invalid during halt
--sts_received_re <= mm2s_sts_received and not sts_received_d1;
sts_received_re <= mm2s_sts_received and not sts_received_d1 and not mm2s_halt_d2;
end generate GEN_UPDT_FOR_QUEUE;
---------------------------------------------------------------------------
-- If no queue in sg engine then do not need to instantiate a
-- fifo to hold buffer lengths. Also do not need to hold off
-- fetch based on if status has been updated or not because
-- descriptors are only processed one at a time
---------------------------------------------------------------------------
GEN_UPDT_FOR_NO_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
mm2s_sts_received_clr <= '1'; -- Not needed for the No Queue configuration
mm2s_pending_update <= '0'; -- Not needed for the No Queue configuration
-----------------------------------------------------------------------
-- On MM2S transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
REG_XFERRED_BYTES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_xferd_bytes <= (others => '0');
elsif(mm2s_new_curdesc_wren_i = '1')then
mm2s_xferd_bytes <= mm2s_desc_blength_i;
end if;
end if;
end process REG_XFERRED_BYTES;
-- Status received based on a DONE or an ERROR from DataMover
sts_received <= mm2s_done or mm2s_interr or mm2s_decerr or mm2s_slverr;
-- Generate a rising edge off status received in order to
-- flag status update
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= sts_received;
end if;
end if;
end process REG_STATUS;
-- CR566306 - status invalid during halt
--sts_received_re <= mm2s_sts_received and not sts_received_d1;
sts_received_re <= sts_received and not sts_received_d1 and not mm2s_halt_d2;
end generate GEN_UPDT_FOR_NO_QUEUE;
-----------------------------------------------------------------------
-- Receive Status SG Update Logic
-----------------------------------------------------------------------
-- clear flag when updating status and see a tlast and target
-- (i.e. sg engine) is ready
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tlast = '1'
and updtsts_tvalid = '1'
and s_axis_mm2s_updtsts_tready = '1'
else '0';
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_sts_clr = '1')then
updt_sts <= '0';
-- clear flag when status update done
-- or datamover halted
-- elsif(updt_sts_clr = '1')then
-- updt_sts <= '0';
-- -- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg2 <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_reg2 <= DESC_LAST
& mm2s_tag(DATAMOVER_STS_TAGLSB_BIT) -- Desc_IOC
& mm2s_complete
& mm2s_decerr
& mm2s_slverr
& mm2s_interr
& RESERVED_STS
& mm2s_xferd_bytes;
end if;
end if;
end process UPDT_DESC_WRD2;
updtsts_tdata <= updt_desc_reg2(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
-- MSB asserts last on last word of update stream
updtsts_tlast <= updt_desc_reg2(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive tvalid
updtsts_tvalid <= updt_sts;
-- Drive update done to mm2s sm for the no queue case to indicate
-- readyd to fetch next descriptor
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
-- Update Pointer Stream
s_axis_mm2s_updtptr_tvalid <= updtptr_tvalid;
s_axis_mm2s_updtptr_tlast <= updtptr_tlast and updtptr_tvalid;
s_axis_mm2s_updtptr_tdata <= updtptr_tdata ;
-- Update Status Stream
s_axis_mm2s_updtsts_tvalid <= updtsts_tvalid;
s_axis_mm2s_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
s_axis_mm2s_updtsts_tdata <= updtsts_tdata ;
-----------------------------------------------------------------------
end implementation;
|
constant SPIFSMLength : integer := 1295;
constant SPIFSMCfg : std_logic_vector(SPIFSMLength-1 downto 0) := "00001001000000000000010100001000101000000000000000000110001000000000001000011111000000000000000000001111100000000000000000000000000000000101000000000000001000000000000000001100001100000000001000000100000000010100000000000000100001001000000000110000110000000000100010010100000010010000100000000000110000101000000101000101000000000000000111110000000000000000000000000000001111100000000000000000000000000000011111000000000000000000000000000000111110000000000000000000000000000001111100000000000000000000000000000000111110000000000000000000000000000000011111000000000000000000000000000000001111100000000000000000000000000000000111110000000000000000000000000000000011111000000000000000000000000000000001111100000000000000000000000000000000111110000000000000000000000000000000011111000000000000000000000000000000001111100000000000000000000000000000000111110000000000000000000000000000000000001111100000000000000000000000000000000000011111000000000000000000000000000000000000111110000000000000000000000000000000000001111100000000000000000000000000000000000011111000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000111110000000000000000000000000000000000000000000011111000000000000000000000000000000000000000000001111100000000000000000000000000000000000000000000";
|
-- libraries -------------------------------------------------------------------------------------------{{{
library ieee;
use ieee.std_logic_1164.all;
use ieee.float_pkg.all;
use ieee.numeric_std.ALL;
use ieee.math_real.all;
use ieee.math_complex.all;
library work;
use work.all;
use work.FGPU_definitions.all;
use work.FGPU_simulation_pkg.all;
use ieee.std_logic_textio.all;
use std.textio.all;
---------------------------------------------------------------------------------------------------------}}}
entity global_mem is
-- generics & ports {{{
generic(
MEM_PHY_ADDR_W : natural := 17;
ADDR_OFFSET : unsigned := X"1000_0000";
MAX_NDRANGE_SIZE : natural := 64*1024
);
port(
new_kernel : in std_logic;
finished_kernel : in std_logic;
size_0 : in natural;
size_1 : in natural;
target_offset_addr : in natural := 2**(N+L+M-1+2);
problemSize : in natural;
-- AXI Slave Interfaces
-- common signals
mx_arlen_awlen : in std_logic_vector(7 downto 0):= (others=>'0');
-- interface 0 {{{
-- ar channel
m0_araddr : in std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0');
m0_arvalid : in std_logic := '0';
m0_arready : buffer std_logic := '0';
m0_arid : in std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- r channel
m0_rdata : out std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0');
m0_rlast : out std_logic := '0';
m0_rvalid : buffer std_logic := '0';
m0_rready : in std_logic;
m0_rid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- aw channel
m0_awaddr : in std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0');
m0_awvalid : in std_logic := '0';
m0_awready : buffer std_logic := '0';
m0_awid : in std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- w channel
m0_wdata : in std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0');
m0_wstrb : in std_logic_vector(GMEM_DATA_W/8-1 downto 0):= (others=>'0');
m0_wlast : in std_logic := '0';
m0_wvalid : in std_logic := '0';
m0_wready : buffer std_logic := '0';
-- b channel
m0_bvalid : out std_logic := '0';
m0_bready : in std_logic := '0';
m0_bid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- }}}
-- interface 1 {{{
-- ar channel
m1_araddr : in std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0');
m1_arvalid : in std_logic := '0';
m1_arready : buffer std_logic := '0';
m1_arid : in std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- r channel
m1_rdata : out std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0');
m1_rlast : out std_logic := '0';
m1_rvalid : buffer std_logic := '0';
m1_rready : in std_logic;
m1_rid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- aw channel
m1_awaddr : in std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0');
m1_awvalid : in std_logic := '0';
m1_awready : buffer std_logic := '0';
m1_awid : in std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- w channel
m1_wdata : in std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0');
m1_wstrb : in std_logic_vector(GMEM_DATA_W/8-1 downto 0):= (others=>'0');
m1_wlast : in std_logic := '0';
m1_wvalid : in std_logic := '0';
m1_wready : buffer std_logic := '0';
-- b channel
m1_bvalid : out std_logic := '0';
m1_bready : in std_logic := '0';
m1_bid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- }}}
-- interface 2 {{{
-- ar channel
m2_araddr : in std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0');
m2_arvalid : in std_logic := '0';
m2_arready : buffer std_logic := '0';
m2_arid : in std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- r channel
m2_rdata : out std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0');
m2_rlast : out std_logic := '0';
m2_rvalid : buffer std_logic := '0';
m2_rready : in std_logic;
m2_rid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- aw channel
m2_awaddr : in std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0');
m2_awvalid : in std_logic := '0';
m2_awready : buffer std_logic := '0';
m2_awid : in std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- w channel
m2_wdata : in std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0');
m2_wstrb : in std_logic_vector(GMEM_DATA_W/8-1 downto 0):= (others=>'0');
m2_wlast : in std_logic := '0';
m2_wvalid : in std_logic := '0';
m2_wready : buffer std_logic := '0';
-- b channel
m2_bvalid : out std_logic := '0';
m2_bready : in std_logic := '0';
m2_bid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- }}}
-- interface 3 {{{
-- ar channel
m3_araddr : in std_logic_vector(GMEM_ADDR_W-1 downto 0):= (others=>'0');
m3_arvalid : in std_logic := '0';
m3_arready : buffer std_logic := '0';
m3_arid : in std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- r channel
m3_rdata : out std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0');
m3_rlast : out std_logic := '0';
m3_rvalid : buffer std_logic := '0';
m3_rready : in std_logic;
m3_rid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- aw channel
m3_awaddr : in std_logic_vector(GMEM_ADDR_W-1 downto 0) := (others=>'0');
m3_awvalid : in std_logic := '0';
m3_awready : buffer std_logic := '0';
m3_awid : in std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- w channel
m3_wdata : in std_logic_vector(GMEM_DATA_W-1 downto 0):= (others=>'0');
m3_wstrb : in std_logic_vector(GMEM_DATA_W/8-1 downto 0):= (others=>'0');
m3_wlast : in std_logic := '0';
m3_wvalid : in std_logic := '0';
m3_wready : buffer std_logic := '0';
-- b channel
m3_bvalid : out std_logic := '0';
m3_bready : in std_logic := '0';
m3_bid : out std_logic_vector(ID_WIDTH-1 downto 0) := (others=>'0');
-- }}}
clk, nrst : in std_logic
);
-- }}}
end global_mem;
architecture Behavioral of global_mem is
-- constants & functions {{{
constant C_MEM_SIZE : integer := 2**MEM_PHY_ADDR_W;
CONSTANT MAX_DELAY : real := 20.0;
CONSTANT MIN_DELAY : integer := 10; -- delay = min + rand*max
CONSTANT IMPLEMENT_DELAY : boolean := false;
CONSTANT MAX_STEAM_PAUSE : real := 15.0;
CONSTANT IMPLEMENT_NO_STREAM_READ : boolean := false;
CONSTANT FILL_MODULO : natural := 49;
CONSTANT BVALID_DELAY_W : natural := 2;
type gmem_type is array (C_MEM_SIZE-1 downto 0) of std_logic_vector(GMEM_DATA_W-1 downto 0);
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is -- {{{
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end; -- }}}
function init_me_with_modulu(len: in integer; fill_modulo: in natural) return gmem_type is -- {{{
variable i : integer := 0;
variable res : gmem_type := (others=>(others=>'0'));
begin
for i in 0 to len-1 loop --len-1 loop
for j in 0 to GMEM_DATA_W/32-1 loop
res(i)((j+1)*32-1 downto j*32) := std_logic_vector(to_unsigned((i*2+j) mod fill_modulo, 32));
end loop;
-- res(i)(31 downto 0) := std_logic_vector(to_unsigned(i, 32) );
-- res(i)(63 downto 32) := std_logic_vector(to_signed(-i, 32));
end loop;
return(res);
end; -- }}}
impure function init_mem_fft (size_0: in integer ) return gmem_type is -- {{{
variable res : gmem_type := (others=>(others=>'0'));
variable seed1, seed2 : positive := 1;
variable rand : real;
variable tmp_unsigned : unsigned(DATA_W-1 downto 0) := (others=>'0');
variable nStages, tmp_integer : integer;
variable tmp_std_logic : std_logic := '0';
variable li : line;
begin
nStages := 1;
tmp_integer := 1;
while tmp_integer < size_0 loop
tmp_integer := tmp_integer * 2;
nStages := nStages + 1;
end loop;
assert DATA_W*2 = GMEM_DATA_W;
-- write data with bit reverse
for i in 0 to 2*size_0-1 loop
tmp_unsigned := to_unsigned(i, 32);
for m in 0 to nStages/2 loop
tmp_std_logic := tmp_unsigned(nStages-1-m);
tmp_unsigned(nStages-1-m) := tmp_unsigned(m);
tmp_unsigned(m) := tmp_std_logic;
end loop;
res(to_integer(tmp_unsigned))(DATA_W-1 downto 0) := to_slv(to_float(i mod 4)); -- real part
res(to_integer(tmp_unsigned))(2*DATA_W-1 downto DATA_W) := (others=>'0'); -- imaginary part
end loop;
-- for i in 0 to 7 loop
-- write(li, to_real(to_float(res(i)(DATA_W-1 downto 0))));
-- swrite(li, " +j ");
-- write(li, to_real(to_float(res(i)(2*DATA_W-1 downto DATA_W))));
-- write(li, LF);
-- end loop;
-- writeline(OUTPUT, li);
-- write twiddles
for i in 0 to 2*size_0-1 loop
-- res(C_MEM_SIZE/2 + i)(DATA_W-1 downto 0) := to_slv(to_float(cos(to_real(MATH_PI*i/to_real(size_0)))));
res(C_MEM_SIZE/4 + i)(DATA_W-1 downto 0) := to_slv(to_float(cos(real(MATH_PI*real(i)/real(size_0)))));
res(C_MEM_SIZE/4 + i)(2*DATA_W-1 downto DATA_W) := to_slv(-to_float(sin(real(MATH_PI*real(i)/real(size_0)))));
end loop;
-- for i in 0 to 7 loop
-- write(li, to_real(to_float(res(C_MEM_SIZE/4+i)(DATA_W-1 downto 0))));
-- swrite(li, " +j ");
-- write(li, to_real(to_float(res(C_MEM_SIZE/4+i)(2*DATA_W-1 downto DATA_W))));
-- write(li, LF);
-- end loop;
-- writeline(OUTPUT, li);
return(res);
end; -- }}}
function init_mem_floydwarshall (len: in integer) return gmem_type is -- {{{
variable i : integer := 0;
variable res : gmem_type := (others=>(others=>'0'));
variable seed1, seed2 : positive := 1;
variable rand : real;
begin
for i in 0 to len-1 loop --len-1 loop
for j in 0 to GMEM_DATA_W/DATA_W-1 loop
uniform(seed1, seed2, rand);
res(i)((j+1)*DATA_W-1 downto j*DATA_W) := to_slv(to_float(rand*10.0));
if i = j then
res(i)((j+1)*DATA_W-1 downto j*DATA_W) := (others=>'0');
end if;
end loop;
end loop;
return(res);
end; -- }}}
function init_mem_rand_float (len: in integer; data_width: in integer) return gmem_type is -- {{{
variable i : integer := 0;
variable res : gmem_type := (others=>(others=>'0'));
variable seed1, seed2 : positive := 1;
variable rand : real;
begin
for i in 0 to len-1 loop --len-1 loop
for j in 0 to GMEM_DATA_W/data_width-1 loop
uniform(seed1, seed2, rand);
res(i)((j+1)*data_width-1 downto j*data_width) := to_slv(to_float(rand));
end loop;
end loop;
return(res);
end; -- }}}
function init_mem_rand (len: in integer; data_width: in integer) return gmem_type is -- {{{
variable i : integer := 0;
variable res : gmem_type := (others=>(others=>'0'));
variable tmp_integer : integer;
variable tmp_unsigned : unsigned(DATA_W-1 downto 0) := (others=>'0');
variable seed1, seed2 : positive := 1;
variable rand : real;
begin
for i in 0 to len-1 loop --len-1 loop
for j in 0 to GMEM_DATA_W/data_width-1 loop
uniform(seed1, seed2, rand);
rand := rand * 1024.0 * 1024.0 * 1024.0 * 2.0;
tmp_integer := integer(rand);
tmp_unsigned := to_unsigned(tmp_integer, DATA_W);
res(i)((j+1)*data_width-1 downto j*data_width) := std_logic_vector(tmp_unsigned(data_width-1 downto 0));
end loop;
end loop;
return(res);
end; -- }}}
function init_mem_float (len: in integer) return gmem_type is -- {{{
variable i : integer := 0;
variable res : gmem_type := (others=>(others=>'0'));
variable tmp_unsigned : unsigned(DATA_W-1 downto 0) := (others=>'0');
begin
for i in 0 to len-1 loop --len-1 loop
for j in 0 to GMEM_DATA_W/DATA_W-1 loop
tmp_unsigned := to_unsigned(GMEM_DATA_W/DATA_W*i+j, DATA_W);
res(i)((j+1)*DATA_W-1 downto j*DATA_W) := std_logic_vector(to_float(tmp_unsigned));
end loop;
end loop;
return(res);
end; --}}}
function init_mem (len: in integer; data_width: in integer) return gmem_type is -- {{{
variable i : integer := 0;
variable res : gmem_type := (others=>(others=>'0'));
variable tmp_unsigned : unsigned(DATA_W-1 downto 0) := (others=>'0');
begin
for i in 0 to len-1 loop --len-1 loop
for j in 0 to GMEM_DATA_W/data_width-1 loop
tmp_unsigned := to_unsigned(GMEM_DATA_W/data_width*i+j, DATA_W);
res(i)((j+1)*data_width-1 downto j*data_width) := std_logic_vector(tmp_unsigned(data_width-1 downto 0));
end loop;
end loop;
return(res);
end; --}}}
--}}}
-- read & write addresses {{{
signal gmem: gmem_type := init_mem(C_MEM_SIZE/2, DATA_W);
signal tmp_gmem : SLV32_ARRAY(0 to 2**16-1) := (others=>(others=>'0'));
type mem_phy_addr_array is array(natural range <>) of unsigned(MEM_PHY_ADDR_W-1 downto 0);
signal wr_addr : gmem_addr_array(N_AXI-1 downto 0) := (others=>(others=>'0'));
type gmem_addr_2d_array is array(natural range <>, natural range <>) of unsigned(GMEM_ADDR_W-1 downto 0);
signal wr_addr_offset : mem_phy_addr_array(N_AXI-1 downto 0) := (others=>(others=>'0'));
signal written_count : integer := 0;
signal written_addrs : std_logic_vector(MAX_NDRANGE_SIZE-1 downto 0) := (others=>'0');
signal new_kernel_d0, new_kernel_d1 : std_logic := '0';
-- }}}
-- other signals {{{
signal delay : nat_2d_array(N_AXI-1 downto 0, N_WR_FIFOS_AXI-1 downto 0) := (others=>(others=>0));
-- }}}
-- alias signals {{{
signal wvalid, wready : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal wdata, rdata : gmem_word_array(N_AXI-1 downto 0) := (others=>(others=>'0'));
signal wstrb : gmem_be_array(N_AXI-1 downto 0) := (others=>(others=>'0'));
signal awready, awvalid : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal arready, arvalid : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal rready, rvalid, rlast : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal bvalid, bready : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal araddr, awaddr : gmem_addr_array(N_AXI-1 downto 0) := (others=>(others=>'0'));
signal arid, rid, awid, bid : id_array(N_AXI-1 downto 0) := (others=>(others=>'0'));
signal wlast : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
-- }}}
-- read multiplexing {{{
type st_reader_type is (idle, delay_before_read, send_data);
type st_reader_array is array (natural range <>, natural range<>) of st_reader_type;
-- }}}
-- write signals {{{
constant c_awaddr_fifo_capacity_w : natural := 3;
constant c_awaddr_fifo_capacity : natural := 2**c_awaddr_fifo_capacity_w;
-- awaddr fifo
type awaddr_fifo_array is array(natural range <>) of gmem_addr_array(c_awaddr_fifo_capacity-1 downto 0);
signal awaddr_fifo : awaddr_fifo_array(N_AXI-1 downto 0) := (others=>(others=>(others=>'0')));
type awaddr_fifo_addr_vec is array(natural range <>) of unsigned(c_awaddr_fifo_capacity_w-1 downto 0);
signal awaddr_fifo_wrAddr : awaddr_fifo_addr_vec(N_AXI-1 downto 0) := (others=>(others=>'0'));
signal awaddr_fifo_rdAddr : awaddr_fifo_addr_vec(N_AXI-1 downto 0) := (others=>(others=>'0'));
signal awaddr_fifo_nempty : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal awaddr_fifo_full : std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
signal awaddr_fifo_pop, awaddr_fifo_push: std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
-- awid fifo
type awid_fifo_array is array(natural range <>) of id_array(max(1, 2**BVALID_DELAY_W/2**BURST_W)*c_awaddr_fifo_capacity-1 downto 0);
signal awid_fifo : awid_fifo_array(N_AXI-1 downto 0) := (others=>(others=>(others=>'0')));
type awid_fifo_addr_array is array( natural range <>) of unsigned(c_awaddr_fifo_capacity_w+max(BVALID_DELAY_W-BURST_W, 0)-1 downto 0);
signal awid_fifo_rdAddr : awid_fifo_addr_array(N_AXI-1 downto 0) := (others=>(others=>'0'));
signal awid_fifo_wrAddr : awid_fifo_addr_array(N_AXI-1 downto 0) := (others=>(others=>'0'));
type st_write_type is (get_address, write);
type st_write_array is array (natural range <>) of st_write_type;
signal st_write : st_write_array(N_AXI-1 downto 0) := (others=>get_address);
-- write pipe for delaying bvalid
type wdata_vec_type is array (natural range <>) of gmem_word_array(N_AXI-1 downto 0);
signal wdata_vec : wdata_vec_type(2**BVALID_DELAY_W-1 downto 0) := (others=>(others=>(others=>'0')));
type wstrb_vec_type is array(natural range <>) of gmem_be_array(N_AXI-1 downto 0);
signal wstrb_vec : wstrb_vec_type(2**BVALID_DELAY_W-1 downto 0) := (others=>(others=>(others=>'0')));
type wlast_vec_type is array(natural range <>) of std_logic_vector(N_AXI-1 downto 0);
signal wlast_vec, wvalid_vec : wlast_vec_type(2**BVALID_DELAY_W-1 downto 0) := (others=>(others=>'0'));
type wr_addr_offset_vec_type is array(natural range <>) of mem_phy_addr_array(N_AXI-1 downto 0);
signal wr_addr_offset_vec : wr_addr_offset_vec_type(2**BVALID_DELAY_W-1 downto 0) := (others=>(others=>(others=>'0')));
--}}}
begin
-- alias signals ---------------------------------------------------------------------------------------{{{
wvalid(0) <= m0_wvalid;
wdata(0) <= m0_wdata;
wstrb(0) <= m0_wstrb;
wlast(0) <= m0_wlast;
m0_wready <= wready(0);
m0_awready <= awready(0);
awvalid(0) <= m0_awvalid;
awaddr(0) <= unsigned(m0_awaddr);
araddr(0) <= unsigned(m0_araddr);
m0_arready <= arready(0);
arvalid(0) <= m0_arvalid;
arid(0) <= m0_arid;
rready(0) <= m0_rready;
m0_rvalid <= rvalid(0);
m0_rid <= rid(0);
awid(0) <= m0_awid;
m0_bid <= bid(0);
m0_rdata <= rdata(0);
m0_rlast <= rlast(0);
m0_bvalid <= bvalid(0);
bready(0) <= m0_bready;
MORE_THAN_1_W_AXI : if N_AXI > 1 generate
begin
wvalid(1) <= m1_wvalid;
wdata(1) <= m1_wdata;
wstrb(1) <= m1_wstrb;
wlast(1) <= m1_wlast;
m1_wready <= wready(1);
m1_awready <= awready(1);
awaddr(1) <= unsigned(m1_awaddr);
araddr(1) <= unsigned(m1_araddr);
awvalid(1) <= m1_awvalid;
m1_arready <= arready(1);
arvalid(1) <= m1_arvalid;
arid(1) <= m1_arid;
rready(1) <= m1_rready;
m1_rvalid <= rvalid(1);
m1_rid <= rid(1);
awid(1) <= m1_awid;
m1_bid <= bid(1);
m1_rdata <= rdata(1);
m1_rlast <= rlast(1);
m1_bvalid <= bvalid(1);
bready(1) <= m1_bready;
end generate;
MORE_THAN_2_W_AXI: if N_AXI > 2 generate
begin
wvalid(2) <= m2_wvalid;
wdata(2) <= m2_wdata;
wstrb(2) <= m2_wstrb;
wlast(2) <= m2_wlast;
m2_wready <= wready(2);
m2_awready <= awready(2);
awvalid(2) <= m2_awvalid;
awaddr(2) <= unsigned(m2_awaddr);
araddr(2) <= unsigned(m2_araddr);
m2_arready <= arready(2);
arvalid(2) <= m2_arvalid;
arid(2) <= m2_arid;
awid(2) <= m2_awid;
m2_bid <= bid(2);
rready(2) <= m2_rready;
m2_rvalid <= rvalid(2);
m2_rid <= rid(2);
m2_rdata <= rdata(2);
m2_rlast <= rlast(2);
m2_bvalid <= bvalid(2);
bready(2) <= m2_bready;
end generate;
MORE_THAN_3_W_AXI : if N_AXI > 3 generate
begin
wvalid(3) <= m3_wvalid;
wdata(3) <= m3_wdata;
wstrb(3) <= m3_wstrb;
wlast(3) <= m3_wlast;
m3_wready <= wready(3);
m3_awready <= awready(3);
awvalid(3) <= m3_awvalid;
awaddr(3) <= unsigned(m3_awaddr);
araddr(3) <= unsigned(m3_araddr);
m3_arready <= arready(3);
arvalid(3) <= m3_arvalid;
arid(3) <= m3_arid;
awid(3) <= m3_awid;
m3_bid <= bid(3);
rready(3) <= m3_rready;
m3_rvalid <= rvalid(3);
m3_rid <= rid(3);
m3_rdata <= rdata(3);
m3_rlast <= rlast(3);
m3_bvalid <= bvalid(3);
bready(3) <= m3_bready;
end generate;
---------------------------------------------------------------------------------------------------------}}}
-- mem module -------------------------------------------------------------------------------------------{{{
process(clk)
begin
if rising_edge(clk) then
for j in 0 to N_AXI-1 loop
if wvalid_vec(0)(j) = '1' and wready(j) = '1' then
for i in 0 to GMEM_DATA_W/8-1 loop
if wstrb_vec(0)(j)(i) = '1' then
gmem(to_integer(wr_addr_offset_vec(0)(j)))((i+1)*8-1 downto i*8) <= wdata_vec(0)(j)((i+1)*8-1 downto i*8);
end if;
end loop;
end if;
end loop;
if new_kernel = '1' then
if kernel_name = mat_mul or kernel_name = xcorr then
gmem <= init_me_with_modulu(C_MEM_SIZE/2, FILL_MODULO);
elsif kernel_name = fadd or kernel_name = add_float or kernel_name = mul_float or kernel_name = median or kernel_name = max_half_atomic then
gmem <= init_mem_rand(C_MEM_SIZE/2, 32);
elsif kernel_name = floydwarshall then
gmem <= init_mem_floydwarshall(C_MEM_SIZE/2);
elsif kernel_name = fft_hard then
gmem <= init_mem_fft(size_0);
elsif kernel_name = fir_char4 then
gmem <= init_mem(C_MEM_SIZE/2, 8);
elsif kernel_name = parallelSelection then
gmem <= init_mem_float(C_MEM_SIZE/2);
-- elsif kernel_name = ludecompose then
-- gmem <= init_mem_rand(C_MEM_SIZE/2, 32);
-- -- gmem(0)(DATA_W-1 downto 0) <= to_slv(to_float(121));
-- -- gmem(0)(2*DATA_W-1 downto DATA_W) <= to_slv(to_float(68));
-- -- gmem(1)(DATA_W-1 downto 0) <= to_slv(to_float(30));
-- -- gmem(1)(2*DATA_W-1 downto DATA_W) <= to_slv(to_float(73));
-- -- gmem(2)(DATA_W-1 downto 0) <= to_slv(to_float(109));
-- -- gmem(2)(2*DATA_W-1 downto DATA_W) <= to_slv(to_float(94));
-- -- gmem(3)(DATA_W-1 downto 0) <= to_slv(to_float(62));
-- -- gmem(3)(2*DATA_W-1 downto DATA_W) <= to_slv(to_float(31));
-- -- gmem(4)(DATA_W-1 downto 0) <= to_slv(to_float(113));
-- -- gmem(4)(2*DATA_W-1 downto DATA_W) <= to_slv(to_float(5));
-- -- gmem(5)(DATA_W-1 downto 0) <= to_slv(to_float(27));
-- -- gmem(5)(2*DATA_W-1 downto DATA_W) <= to_slv(to_float(106));
-- -- gmem(6)(DATA_W-1 downto 0) <= to_slv(to_float(33));
-- -- gmem(6)(2*DATA_W-1 downto DATA_W) <= to_slv(to_float(6));
-- -- gmem(7)(DATA_W-1 downto 0) <= to_slv(to_float(86));
-- -- gmem(7)(2*DATA_W-1 downto DATA_W) <= to_slv(to_float(92));
else
gmem <= init_mem(C_MEM_SIZE/2, 32);
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------------}}}
-- read control -------------------------------------------------------------------------------------------{{{
read_fsms: process(clk)
variable seed1, seed2 : positive := 1;
variable rand : real;
variable rdAddr, wrAddr : gmem_addr_2d_array(N_AXI-1 downto 0, N_WR_FIFOS_AXI-1 downto 0) := (others=>(others=>(others=>'0')));
variable st_reader : st_reader_array(N_AXI-1 downto 0, N_WR_FIFOS_AXI-1 downto 0) := (others=>(others=>idle));
variable rlen : nat_2d_array(N_AXI-1 downto 0, N_WR_FIFOS_AXI-1 downto 0) := (others=>(others=>0));
begin
if rising_edge(clk) then
if nrst = '0' then
else
for i in 0 to N_AXI-1 loop
arready(i) <= '0';
rvalid(i) <= '0';
rlast(i) <= '0';
-- id readers
for j in 0 to N_WR_FIFOS_AXI-1 loop
case st_reader(i, j) is
when idle =>
if arvalid(i) = '1' and arready(i) = '0' and to_integer(unsigned(arid(i))) = j then
arready(i) <= '1';
rdAddr(i, j) := unsigned(araddr(i)) - ADDR_OFFSET;
rlen(i, j) := to_integer(unsigned(mx_arlen_awlen));
if IMPLEMENT_DELAY then
st_reader(i, j) := delay_before_read;
uniform(seed1, seed2, rand);
delay(i, j) <= MIN_DELAY + integer(rand*MAX_DELAY);
else
st_reader(i, j) := send_data;
end if;
end if;
when delay_before_read =>
if delay(i,j) /= 0 then
delay(i, j) <= delay(i, j) - 1;
else
st_reader(i, j) := send_data;
end if;
when send_data =>
if to_integer(unsigned(rid(i))) = j and rvalid(i) = '1' and rready(i) = '1' then
rdAddr(i, j) := rdAddr(i, j) + 8;
if rlen(i, j) = 0 then
st_reader(i, j) := idle;
else
rlen(i, j) := rlen(i, j) - 1;
if IMPLEMENT_NO_STREAM_READ then
uniform(seed1, seed2, rand);
if rand < 0.5 then
uniform(seed1, seed2, rand);
delay(i, j) <= integer(rand*MAX_STEAM_PAUSE);
st_reader(i, j) := delay_before_read;
end if;
end if;
end if;
end if;
end case;
end loop;
for j in 0 to N_WR_FIFOS_AXI-1 loop
if st_reader(i, j) = send_data then
rvalid(i) <= '1';
rdata(i) <= gmem(to_integer(rdAddr(i, j)(MEM_PHY_ADDR_W+2+GMEM_N_BANK_W-1 downto 2+GMEM_N_BANK_W)));
rid(i) <= std_logic_vector(to_unsigned(j, ID_WIDTH));
if rlen(i, j) = 0 then
rlast(i) <= '1';
end if;
exit;
end if;
end loop;
end loop;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------------}}}
-- write control -------------------------------------------------------------------------------------------{{{
wr_addr_offset_alias: for i in 0 to N_AXI-1 generate
begin
wr_addr_offset(i) <= wr_addr(i)(MEM_PHY_ADDR_W+2+GMEM_N_BANK_W-1 downto 2+GMEM_N_BANK_W);
end generate;
awready <= not awaddr_fifo_full;
awaddr_fifo_push <= awvalid and awready;
process(clk)
variable pop_awaddr: std_logic_vector(N_AXI-1 downto 0) := (others=>'0');
variable seed1, seed2 : positive := 1;
variable rand : real;
variable bid_wait_cycles : natural := 0;
begin
if rising_edge(clk) then
if nrst = '0' then
awaddr_fifo_wrAddr <= (others=>(others=>'0'));
awaddr_fifo_rdAddr <= (others=>(others=>'0'));
st_write <= (others=> get_address);
awaddr_fifo_nempty <= (others=>'0');
awaddr_fifo_full <= (others=>'0');
awaddr_fifo_pop <= (others=>'0');
awid_fifo_rdAddr <= (others=>(others=>'0'));
awid_fifo_wrAddr <= (others=>(others=>'0'));
else
wready <= (others=>'1');
wdata_vec(wdata_vec'high) <= wdata;
wdata_vec(wdata_vec'high-1 downto 0) <= wdata_vec(wdata_vec'high downto 1);
wlast_vec(wlast_vec'high-1 downto 0) <= wlast_vec(wlast_vec'high downto 1);
for i in 0 to N_AXI-1 loop
wlast_vec(wlast_vec'high)(i) <= '0';
if wlast(i) = '1' then
while true loop
uniform(seed1, seed2, rand);
bid_wait_cycles := integer(rand*real(2**BVALID_DELAY_W));
if bid_wait_cycles > 2**BVALID_DELAY_W-2 then
bid_wait_cycles := 2**BVALID_DELAY_W-2;
end if;
-- if bid_wait_cycles = 0 then
-- bid_wait_cycles := 1;
-- end if;
-- report "bid_wait_cycles = " & integer'image(bid_wait_cycles);
if wlast_vec(bid_wait_cycles+1)(i) = '0' then
wlast_vec(bid_wait_cycles)(i) <= '1';
exit;
else
-- report "setting wlast failed";
end if;
end loop;
end if;
end loop;
wvalid_vec(wvalid_vec'high) <= wvalid;
wvalid_vec(wvalid_vec'high-1 downto 0) <= wvalid_vec(wvalid_vec'high downto 1);
wstrb_vec(wstrb_vec'high) <= wstrb;
wstrb_vec(wstrb_vec'high-1 downto 0) <= wstrb_vec(wstrb_vec'high downto 1);
wr_addr_offset_vec(wr_addr_offset_vec'high) <= wr_addr_offset;
wr_addr_offset_vec(wr_addr_offset_vec'high-1 downto 0) <= wr_addr_offset_vec(wr_addr_offset_vec'high downto 1);
for i in 0 to N_AXI-1 loop
if wlast_vec(0)(i) = '1' then
bvalid(i) <= '1';
bid(i) <= awid_fifo(i)(to_integer(awid_fifo_rdAddr(i)));
awid_fifo_rdAddr(i) <= awid_fifo_rdAddr(i) + 1;
elsif bready(i) = '1' then
bvalid(i) <= '0';
end if;
pop_awaddr(i) := '0';
awaddr_fifo_pop(i) <= '0';
case st_write(i) is
when get_address =>
if awaddr_fifo_nempty(i) = '1' then
awaddr_fifo_pop(i) <= '1';
pop_awaddr(i) := '1';
wr_addr(i) <= awaddr_fifo(i)(to_integer(awaddr_fifo_rdAddr(i))) - ADDR_OFFSET;
awaddr_fifo_rdAddr(i) <= awaddr_fifo_rdAddr(i) + 1;
st_write(i) <= write;
end if;
when write =>
if wvalid(i) = '1' and wready(i) = '1' then
wr_addr(i) <= wr_addr(i) + 8;
if wlast(i) = '1' then
if awaddr_fifo_nempty(i) = '1' then
awaddr_fifo_pop(i) <= '1';
pop_awaddr(i) := '1';
wr_addr(i) <= awaddr_fifo(i)(to_integer(awaddr_fifo_rdAddr(i))) - ADDR_OFFSET;
awaddr_fifo_rdAddr(i) <= awaddr_fifo_rdAddr(i) + 1;
st_write(i) <= write;
else
st_write(i) <= get_address;
end if;
end if;
end if;
end case;
if awaddr_fifo_push(i) = '1' then
-- if to_integer(unsigned(awaddr(i)(17 downto 0))) = 3712 then
-- report "heeere";
-- end if;
awaddr_fifo(i)(to_integer(awaddr_fifo_wrAddr(i))) <= unsigned(awaddr(i));
awaddr_fifo_wrAddr(i) <= awaddr_fifo_wrAddr(i) + 1;
awid_fifo(i)(to_integer(awid_fifo_wrAddr(i))) <= awid(i);
awid_fifo_wrAddr(i) <= awid_fifo_wrAddr(i) + 1;
end if;
if awaddr_fifo_push(i) = '1' and pop_awaddr(i) = '0' and awaddr_fifo_wrAddr(i)+1 = awaddr_fifo_rdAddr(i) then
awaddr_fifo_full(i) <= '1';
elsif awaddr_fifo_push(i) = '0' and pop_awaddr(i) = '1' then
awaddr_fifo_full(i) <= '0';
end if;
if awaddr_fifo_push(i) = '1' and pop_awaddr(i) = '0' then
awaddr_fifo_nempty(i) <= '1';
elsif awaddr_fifo_push(i) = '0' and pop_awaddr(i) = '1' and awaddr_fifo_rdAddr(i)+1 = awaddr_fifo_wrAddr(i) then
awaddr_fifo_nempty(i) <= '0';
end if;
end loop;
end if;
end if;
end process;
--------------------------------------------------------------------------------------------------------}}}
-- test process -------------------------------------------------------------------------------------------{{{
test_process: process(clk)
-- test procedures {{{
-- variables {{{
variable wr_addr_int : integer := 0;
variable li : line;
variable offset : integer := 16#0008_0000#;
variable stride : natural := 65;
variable written_count_tmp : integer := 0;
type SLV16_ARRAY is array (natural range <>) of std_logic_vector(15 downto 0);
type SLV8_ARRAY is array(natural range <>) of std_logic_vector(7 downto 0);
variable must_data_word : SLV32_ARRAY(1 downto 0) := (others=>(others=>'0'));
variable must_data_half : SLV16_ARRAY(3 downto 0) := (others=>(others=>'0'));
variable must_data_byte : SLV8_ARRAY(7 downto 0) := (others=>(others=>'0'));
variable must_data : std_logic_vector(GMEM_DATA_W-1 downto 0) := (others=>'0');
variable word_addr, second_word_addr : natural := 0;
variable byte_addr : natural := 0;
variable half_addr : natural := 0;
variable tmp_signed : signed(DATA_W-1 downto 0) := (others=>'0');
variable tmp_unsigned_64 : unsigned(GMEM_DATA_W-1 downto 0) := (others=>'0');
variable tmp_unsigned : unsigned(DATA_W-1 downto 0) := (others=>'0');
variable tmp_integer : integer;
variable tmp_float : float32 := to_float(0);
variable tmp_std_logic : std_logic := '0';
variable rowIndx, colIndx, res, k : natural := 0;
variable p00, p01, p02, p10, p11, p12, p20, p21, p22 : unsigned(DATA_W-1 downto 0) := (others=>'0');
variable nStages, stageIndx, pairDistance, blockWidth, leftIndx, rightIndx: integer := 0;
variable leftElement, rightElement, greater, lesser : unsigned(DATA_W-1 downto 0) := (others=>'0');
variable leftElement_float, rightElement_float, greater_float, lesser_float : float32 := to_float(0);
variable twiddle, a, b, res_a, res_b : complex;
variable passIndx, sameDirectionBlock : integer := 0;
variable nGroups, groupOffset : integer := 0;
variable x1, y1, z1, m1, x2, y2, z2, m2 : float32 := to_float(0);
variable xdiff, ydiff, zdiff, distSquared : float32 := to_float(0);
variable accx, accy, accz, invDist, invDistCube, s : float32 := to_float(0);
variable oldVelx, oldVely, oldVelz, newVelx, newVely, newVelz : float32 := to_float(0);
variable softeningFactor : float32 := to_float(500); -- don't change (fixed in sch_ram.xml)
variable deltaTime : float32 := to_float(0.005); -- don't change (fixed in sch_ram.xml)
-- }}}
procedure ludecompose_round is
begin
end procedure;
procedure fft_round is -- {{{
begin
for i in 0 to size_0-1 loop
pairDistance := 2**stageIndx;
blockWidth := 2 * pairDistance;
nGroups := size_0/pairDistance;
groupOffset := to_integer(to_unsigned(i, 32) and to_unsigned(pairDistance-1, 32));
leftIndx := groupOffset + (i/pairDistance)*blockWidth;
rightIndx := leftIndx + pairDistance;
a.re := to_real(to_float(tmp_gmem(2*leftIndx)));
a.im := to_real(to_float(tmp_gmem(2*leftIndx+1)));
b.re := to_real(to_float(tmp_gmem(2*rightIndx)));
b.im := to_real(to_float(tmp_gmem(2*rightIndx+1)));
-- swrite(li, "a = ");
-- write(li, a.re);
-- swrite(li, " +j ");
-- write(li, a.im);
-- swrite(li, ", b = ");
-- write(li, b.re);
-- swrite(li, " +j ");
-- write(li, b.im);
-- write(li, LF);
twiddle.re := to_real(to_float(gmem(C_MEM_SIZE/4+nGroups*groupOffset)(DATA_W-1 downto 0)));
twiddle.im := to_real(to_float(gmem(C_MEM_SIZE/4+nGroups*groupOffset)(2*DATA_W-1 downto DATA_W)));
res_a := a+twiddle*b;
res_b := a-twiddle*b;
-- swrite(li, "res_a = ");
-- write(li, res_a.re);
-- swrite(li, " +j ");
-- write(li, res_a.im);
-- swrite(li, ", res_b = ");
-- write(li, res_b.re);
-- swrite(li, " +j ");
-- write(li, res_b.im);
-- write(li, LF);
tmp_gmem(2*leftIndx) <= to_slv(to_float(res_a.re));
tmp_gmem(2*leftIndx+1) <= to_slv(to_float(res_a.im));
tmp_gmem(2*rightIndx) <= to_slv(to_float(res_b.re));
tmp_gmem(2*rightIndx+1) <= to_slv(to_float(res_b.im));
end loop;
-- report "fft round is executed";
-- for i in 0 to 7 loop
-- write(li, to_real(to_float(tmp_gmem(2*i))));
-- swrite(li, " +j ");
-- write(li, to_real(to_float(tmp_gmem(2*i+1))));
-- write(li, LF);
-- end loop;
-- writeline(OUTPUT, li);
end procedure; -- }}}
procedure bitonic_float_round is -- {{{
begin
sameDirectionBlock := 2**(stageIndx);
-- report "bitonic round excutes with stageIndx = " & integer'image(stageIndx) & " and passIndx = " & integer'image(passIndx);
for i in 0 to size_0-1 loop
pairDistance := 2**(stageIndx-passIndx);
blockWidth := 2 * pairDistance;
leftIndx := (i mod pairDistance) + (i/pairDistance)*blockWidth;
rightIndx := leftIndx + pairDistance;
leftElement_float := to_float(tmp_gmem(leftIndx));
rightElement_float := to_float(tmp_gmem(rightIndx));
if gt(leftElement_float, rightElement_float) then
greater_float := leftElement_float;
lesser_float := rightElement_float;
else
greater_float := rightElement_float;
lesser_float := leftElement_float;
end if;
if (i/sameDirectionBlock) mod 2 /= 1 then
leftElement_float := greater_float;
rightElement_float := lesser_float;
else
leftElement_float := lesser_float;
rightElement_float := greater_float;
end if;
tmp_gmem(leftIndx) <= to_slv(leftElement_float);
tmp_gmem(rightIndx) <= to_slv(rightElement_float);
end loop;
-- report "bitonic round is executed";
end procedure; -- }}}
procedure bitonic_round is -- {{{
begin
sameDirectionBlock := 2**(stageIndx);
-- report "bitonic round excutes with stageIndx = " & integer'image(stageIndx) & " and passIndx = " & integer'image(passIndx);
for i in 0 to size_0-1 loop
pairDistance := 2**(stageIndx-passIndx);
blockWidth := 2 * pairDistance;
leftIndx := (i mod pairDistance) + (i/pairDistance)*blockWidth;
rightIndx := leftIndx + pairDistance;
leftElement := unsigned(tmp_gmem(leftIndx));
rightElement := unsigned(tmp_gmem(rightIndx));
if leftElement > rightElement then
greater := leftElement;
lesser := rightElement;
else
greater := rightElement;
lesser := leftElement;
end if;
if (i/sameDirectionBlock) mod 2 /= 1 then
leftElement := greater;
rightElement := lesser;
else
leftElement := lesser;
rightElement := greater;
end if;
tmp_gmem(leftIndx) <= std_logic_vector(leftElement);
tmp_gmem(rightIndx) <= std_logic_vector(rightElement);
end loop;
-- report "bitonic round is executed";
end procedure; -- }}}
function canonicalize_float(f: std_logic_vector(31 downto 0)) return std_logic_vector is -- {{{
variable res : std_logic_vector(31 downto 0) := (others=>'0');
begin
res := f;
if f(30 downto 23) = X"FF" then --NaN or infinity
if f(22 downto 0) /= (0 to 22 => '0') then --NaN
res(22 downto 0) := (0=>'1', others=>'0');
res(31) := '0';
end if;
end if;
return res;
end function; -- }}}
function pixel_value(i, j, stride: natural) return integer is -- {{{
variable res : integer := 0;
variable tmp, addr : natural := 0;
variable word_addr : unsigned(DATA_W-1 downto 0) := (others=>'0');
begin
addr := i*stride+j;
tmp := addr mod 4;
word_addr := to_unsigned(addr/ 4, DATA_W);
if tmp = 0 then
res := to_integer(word_addr(7 downto 0));
elsif tmp = 1 then
res := to_integer(word_addr(15 downto 8));
elsif tmp = 2 then
res := to_integer(word_addr(23 downto 16));
else
res := to_integer(word_addr(31 downto 24));
end if;
return res;
end function; -- }}}
procedure sort3(x, y, z: inout integer) is -- {{{
variable tmp_integer : integer := 0;
begin
-- sort in ascending order
if x > y then
tmp_integer := x;
x := y;
y := tmp_integer;
end if;
if x > z then
tmp_integer := x;
x := z;
z := tmp_integer;
end if;
if y > z then
tmp_integer := y;
y := z;
z := tmp_integer;
end if;
end procedure; --}}}
procedure compute_max_half_atomic is -- {{{
variable res : integer;
begin
res := to_integer(signed(gmem(0)(DATA_W/2-1 downto 0)));
for i in 0 to problemSize/4-1 loop -- 4 half words in one gmem address
res := max(res, to_integer(signed(gmem(i)(DATA_W/2-1 downto 0))));
res := max(res, to_integer(signed(gmem(i)(DATA_W-1 downto DATA_W/2))));
res := max(res, to_integer(signed(gmem(i)(DATA_W+DATA_W/2-1 downto DATA_W))));
res := max(res, to_integer(signed(gmem(i)(2*DATA_W-1 downto DATA_W+DATA_W/2))));
end loop;
tmp_gmem(0) <= std_logic_vector(to_signed(res, DATA_W));
end procedure; -- }}}
procedure compute_median is -- {{{
variable pixel_align : integer := 0;
variable p00x, p01x, p02x, p10x, p11x, p12x, p20x, p21x, p22x : integer := 0;
variable res : unsigned(DATA_W-1 downto 0) := (others=>'0');
begin
-- print image
-- for i in 0 to size_1-1 loop
-- for j in 0 to size_0/2-1 loop
-- tmp_integer := (i*size_0 +2*j)/GMEM_N_BANK;
-- write(li, to_hstring(gmem(tmp_integer)(DATA_W-1 downto 0)));
-- swrite(li, " ");
-- write(li, to_hstring(gmem(tmp_integer)(2*DATA_W-1 downto DATA_W)));
-- swrite(li, " ");
-- end loop;
-- write(li, LF);
-- writeline(output, li);
-- end loop;
for i in 1 to size_1-2 loop
for j in 1 to size_0-2 loop
pixel_align := (j+1) mod 2;
if pixel_align = 0 then
tmp_integer := ((i-1)*size_0 +j)/GMEM_N_BANK;
p00 := unsigned(gmem(tmp_integer)(DATA_W-1 downto 0));
p01 := unsigned(gmem(tmp_integer)(2*DATA_W-1 downto DATA_W));
p02 := unsigned(gmem(tmp_integer+1)(DATA_W-1 downto 0));
tmp_integer := ((i+0)*size_0 +j)/GMEM_N_BANK;
p10 := unsigned(gmem(tmp_integer)(DATA_W-1 downto 0));
p11 := unsigned(gmem(tmp_integer)(2*DATA_W-1 downto DATA_W));
p12 := unsigned(gmem(tmp_integer+1)(DATA_W-1 downto 0));
tmp_integer := ((i+1)*size_0 +j)/GMEM_N_BANK;
p20 := unsigned(gmem(tmp_integer)(DATA_W-1 downto 0));
p21 := unsigned(gmem(tmp_integer)(2*DATA_W-1 downto DATA_W));
p22 := unsigned(gmem(tmp_integer+1)(DATA_W-1 downto 0));
else
tmp_integer := ((i-1)*size_0 +j)/GMEM_N_BANK;
p00 := unsigned(gmem(tmp_integer-1)(2*DATA_W-1 downto DATA_W));
p01 := unsigned(gmem(tmp_integer)(DATA_W-1 downto 0));
p02 := unsigned(gmem(tmp_integer)(2*DATA_W-1 downto DATA_W));
tmp_integer := ((i+0)*size_0 +j)/GMEM_N_BANK;
p10 := unsigned(gmem(tmp_integer-1)(2*DATA_W-1 downto DATA_W));
p11 := unsigned(gmem(tmp_integer)(DATA_W-1 downto 0));
p12 := unsigned(gmem(tmp_integer)(2*DATA_W-1 downto DATA_W));
tmp_integer := ((i+1)*size_0 +j)/GMEM_N_BANK;
p20 := unsigned(gmem(tmp_integer-1)(2*DATA_W-1 downto DATA_W));
p21 := unsigned(gmem(tmp_integer)(DATA_W-1 downto 0));
p22 := unsigned(gmem(tmp_integer)(2*DATA_W-1 downto DATA_W));
end if;
-- show stencil
-- write(li, to_hstring(p00)); swrite(li, " "); write(li, to_hstring(p01)); swrite(li, " "); write(li, to_hstring(p02)&LF);
-- write(li, to_hstring(p10)); swrite(li, " "); write(li, to_hstring(p11)); swrite(li, " "); write(li, to_hstring(p12)&LF);
-- write(li, to_hstring(p20)); swrite(li, " "); write(li, to_hstring(p21)); swrite(li, " "); write(li, to_hstring(p22)&LF&LF);
-- writeline(output, li);
for k in 0 to 2 loop -- rgb
-- get color values
p00x := to_integer(p00((k+1)*8-1 downto k*8));
p01x := to_integer(p01((k+1)*8-1 downto k*8));
p02x := to_integer(p02((k+1)*8-1 downto k*8));
p10x := to_integer(p10((k+1)*8-1 downto k*8));
p11x := to_integer(p11((k+1)*8-1 downto k*8));
p12x := to_integer(p12((k+1)*8-1 downto k*8));
p20x := to_integer(p20((k+1)*8-1 downto k*8));
p21x := to_integer(p21((k+1)*8-1 downto k*8));
p22x := to_integer(p22((k+1)*8-1 downto k*8));
-- sort rows
sort3(p00x, p01x, p02x);
sort3(p10x, p11x, p12x);
sort3(p20x, p21x, p22x);
-- sort columns
sort3(p00x, p10x, p20x);
sort3(p01x, p11x, p21x);
sort3(p02x, p12x, p22x);
-- sort diagonal
sort3(p00x, p11x, p22x);
-- set resulting byte value
res((k+1)*8-1 downto 8*k) := to_unsigned(p11x, 8);
end loop;
tmp_gmem(i*size_1+j) <= std_logic_vector(res);
end loop;
end loop;
end procedure; --}}}
procedure check_kernel is -- {{{
begin
for i in 0 to N_AXI-1 loop
if wvalid(i) = '1' and wready(i) = '1' then
wr_addr_int := to_integer(unsigned(wr_addr_offset(i)));
-- assert wr_addr_int /= 16#1b9b8# and wr_addr_int /= 16#1b9b9# and wr_addr_int /= 16#1b9ba# and wr_addr_int /= 16#1b9bb# and wr_addr_int /= 16#1b9bc# and wr_addr_int /= 16#1b9bd# and wr_addr_int /= 16#1b9be# and wr_addr_int /= 16#1b9bf#;
-- write(output, "0x" & to_hstring(to_signed(word_addr, 32)) & LF);
if kernel_name = bitonic or kernel_name = fft_hard or kernel_name = floydwarshall then
word_addr := wr_addr_int*2; -- index of first parameter value
else
word_addr := wr_addr_int*2-(offset+target_offset_addr)/4; -- index of first parameter value
end if;
second_word_addr := word_addr + 64*1024; -- index of the second parameter
-- assert word_addr < 64*1024 severity failure;
assert word_addr >= 0 report integer'image(word_addr) severity failure ;
byte_addr := word_addr * 4;
half_addr := word_addr * 2;
case kernel_name is
when copy =>
for k in 0 to 1 loop
must_data((k+1)*DATA_W-1 downto k*DATA_W) := std_logic_vector(to_unsigned(word_addr+k, DATA_W));
end loop;
when parallelSelection =>
for k in 0 to 1 loop
-- must_data((k+1)*DATA_W-1 downto k*DATA_W) := std_logic_vector(to_unsigned(word_addr+k, DATA_W));
must_data((k+1)*DATA_W-1 downto k*DATA_W) := std_logic_vector(to_float(word_addr+k));
end loop;
when max_half_atomic =>
must_data(DATA_W-1 downto 0) := tmp_gmem(0);
when sobel =>
when bitonic | fft_hard | median =>
must_data(DATA_W-1 downto 0) := tmp_gmem(word_addr);
-- report integer'image(word_addr);
-- report integer'image(to_integer(unsigned(tmp_gmem(word_addr))));
-- report integer'image(to_integer(unsigned(tmp_gmem(word_addr+1))));
must_data(2*DATA_W-1 downto DATA_W) := tmp_gmem(word_addr+1);
when fir_char4 =>
for k in 0 to GMEM_DATA_W/8-1 loop
res := 0;
tmp_integer := (byte_addr+k) mod 256;
for p in 0 to 12-1 loop
res := res + (tmp_integer+p)*p;
end loop;
tmp_unsigned := to_unsigned(res, DATA_W);
must_data((k+1)*GMEM_DATA_W/8-1 downto k*GMEM_DATA_W/8) := std_logic_vector(tmp_unsigned(7 downto 0));
end loop;
when fadd => -- {{{
must_data(DATA_W-1 downto 0) := to_slv( to_float(gmem(word_addr/GMEM_N_BANK)(DATA_W-1 downto 0)) +
to_float(gmem(second_word_addr/GMEM_N_BANK)(DATA_W-1 downto 0)) );
must_data(2*DATA_W-1 downto DATA_W) := to_slv(to_float(gmem(word_addr/GMEM_N_BANK)(2*DATA_W-1 downto DATA_W)) +
to_float(gmem(second_word_addr/GMEM_N_BANK)(2*DATA_W-1 downto DATA_W)) );
-- }}}
when floydwarshall => -- {{{
-- }}}
when add_float => -- {{{
must_data(DATA_W-1 downto 0) := to_slv(to_float(gmem(word_addr/GMEM_N_BANK)(DATA_W-1 downto 0)) + to_float(1));
must_data(2*DATA_W-1 downto DATA_W) := to_slv(to_float(gmem(word_addr/GMEM_N_BANK)(2*DATA_W-1 downto DATA_W)) + to_float(1));
-- }}}
when mul_float => -- {{{
must_data(DATA_W-1 downto 0) := to_slv( to_float(gmem(word_addr/GMEM_N_BANK)(DATA_W-1 downto 0)) *
to_float(gmem(second_word_addr/GMEM_N_BANK)(DATA_W-1 downto 0)) );
must_data(2*DATA_W-1 downto DATA_W) := to_slv(to_float(gmem(word_addr/GMEM_N_BANK)(2*DATA_W-1 downto DATA_W)) *
to_float(gmem(second_word_addr/GMEM_N_BANK)(2*DATA_W-1 downto DATA_W)) );
-- }}}
when mat_mul => -- {{{
colIndx := word_addr mod size_0;
rowIndx := word_addr / size_0;
res := 0;
for k in 0 to size_0-1 loop
res := res + ((rowIndx*size_0+k) mod FILL_MODULO) * ((colIndx+k*size_0)mod FILL_MODULO);
end loop;
-- res := size_0*size_0*rowIndx*colIndx + (size_0*size_0*rowIndx+colIndx)*(size_0-1)*size_0/2 + size_0*(size_0-1)*size_0*(2*size_0-1)/6;
must_data(DATA_W-1 downto 0) := std_logic_vector(to_unsigned(res, DATA_W));
colIndx := (word_addr+1) mod size_0;
rowIndx := (word_addr+1) / size_0;
res := 0;
for k in 0 to size_0-1 loop
res := res + ((rowIndx*size_0+k) mod FILL_MODULO) * ((colIndx+k*size_0)mod FILL_MODULO);
end loop;
must_data(2*DATA_W-1 downto DATA_W) := std_logic_vector(to_unsigned(res, DATA_W));
-- }}}
when fir => -- {{{
res := 0;
for p in 0 to 5-1 loop
res := res + (word_addr+p)*p;
end loop;
must_data(DATA_W-1 downto 0) := std_logic_vector(to_unsigned(res, DATA_W));
res := 0;
for p in 0 to 5-1 loop
res := res + (word_addr+p+1);
end loop;
must_data(2*DATA_W-1 downto DATA_W) := std_logic_vector(to_unsigned(res, DATA_W));
-- }}}
when xcorr => -- {{{
res := 0;
for k in 0 to size_0-1 loop
res := res + (k mod FILL_MODULO) * ((word_addr+k) mod FILL_MODULO);
end loop;
must_data(DATA_W-1 downto 0) := std_logic_vector(to_unsigned(res, DATA_W));
res := 0;
for k in 0 to size_0-1 loop
res := res + (k mod FILL_MODULO) * ((word_addr+1+k) mod FILL_MODULO);
end loop;
must_data(2*DATA_W-1 downto DATA_W) := std_logic_vector(to_unsigned(res, DATA_W));
-- }}}
when sum_atomic => -- {{{
must_data(DATA_W-1 downto 0) := std_logic_vector(to_unsigned((size_0-1)*size_0/2, DATA_W));
when others =>
report "undifined program index!" severity failure;
end case; --- }}}
if wvalid(i) = '1' and wready(i) = '1' then
case COMP_TYPE is
when 0 => -- byte {{{
for k in 0 to 7 loop
if wstrb(i)(k) = '1' and must_data((k+1)*8-1 downto k*8) /= wdata(i)((k+1)*8-1 downto k*8) then
report "wdata byte " & integer'image(k) & " on AXI " & integer'image(i) &
" data is " & integer'image(to_integer(unsigned(wdata(i)((k+1)*8-1 downto k*8)))) &
" must be " & integer'image(to_integer(unsigned(must_data((k+1)*8-1 downto k*8)))) &
" on byte Nr. " & integer'image(byte_addr)
severity failure;
end if;
if wstrb(i)(k) = '1' then
if written_addrs(byte_addr+k) = '0' then
written_count_tmp := written_count_tmp + 1;
else
-- report "double write";
end if;
written_addrs(byte_addr+k) <= '1';
end if;
end loop;
--}}}
when 1 => -- half word {{{
for k in 0 to 3 loop
assert wstrb(i)((k+1)*2-1 downto k*2) = "00" or must_data((k+1)*16-1 downto k*16) = wdata(i)((k+1)*16-1 downto k*16)
report "wdata half word " & integer'image(k) & " on AXI " & integer'image(i) severity failure;
if wstrb(i)(k*2) = '1' then
if written_addrs(half_addr+k) = '0' then
written_count_tmp := written_count_tmp + 1;
else
-- report "double write";
end if;
written_addrs(half_addr+k) <= '1';
end if;
end loop;
-- }}}
when 2 => -- word {{{
for k in 0 to 1 loop
if kernel_name = add_float or kernel_name = mul_float or kernel_name = fadd then
if wstrb(i)((k+1)*DATA_W/8-1 downto k*DATA_W) = X"F" then
if canonicalize_float(must_data((k+1)*DATA_W-1 downto k*DATA_W)) /=
canonicalize_float(wdata(i)((k+1)*DATA_W-1 downto k*DATA_W)) then
write(output, "wdata word " & integer'image(k) & " on AXI " & integer'image(i) & " is " &
"0x" & to_hstring(unsigned(wdata(i)((k+1)*DATA_W-1 downto k*DATA_W))) &
" (should be " & "0x" & to_hstring(unsigned(must_data((k+1)*DATA_W-1 downto k*DATA_W))) & ") for word_addr = " &
integer'image(word_addr+k) & LF);
if kernel_name = fadd then
write(li, to_real(to_float(gmem(word_addr/GMEM_N_BANK)((k+1)*DATA_W-1 downto k*DATA_W))));
write(li, LF);
write(li, to_real(to_float(must_data((k+1)*DATA_W-1 downto k*DATA_W))));
writeline(output, li);
else
write(output, to_hstring(gmem(word_addr/GMEM_N_BANK)((k+1)*DATA_W-1 downto k*DATA_W))&LF);
write(output, to_hstring(gmem(second_word_addr/GMEM_N_BANK)((k+1)*DATA_W-1 downto k*DATA_W))&LF);
end if;
assert false ;
-- assert false severity failure;
end if;
end if;
elsif kernel_name = fft_hard then
if wstrb(i)((k+1)*DATA_W/8-1 downto k*DATA_W) = X"F" then
if must_data((k+1)*DATA_W-1 downto k*DATA_W) /= wdata(i)((k+1)*DATA_W-1 downto k*DATA_W) then
write(output, "wdata word " & integer'image(k) & " on AXI " & integer'image(i) & " is " &
"0x" & to_hstring(unsigned(wdata(i)((k+1)*DATA_W-1 downto k*DATA_W))) &
" (should be " & "0x" & to_hstring(unsigned(must_data((k+1)*DATA_W-1 downto k*DATA_W))) & ") for word_addr = " &
integer'image(word_addr+k) & LF);
write(li, to_real(to_float(wdata(i)((k+1)*DATA_W-1 downto k*DATA_W))));
write(li, LF);
write(li, to_real(to_float(must_data((k+1)*DATA_W-1 downto k*DATA_W))));
writeline(output, li);
-- for i in 0 to 7 loop
-- swrite(li, "x= ");
-- write(li, to_real(to_float(tmp_gmem(4*i))));
-- swrite(li, ",y= ");
-- write(li, to_real(to_float(tmp_gmem(4*i+1))));
-- swrite(li, ",z= ");
-- write(li, to_real(to_float(tmp_gmem(4*i+2))));
-- swrite(li, ",m= ");
-- write(li, to_real(to_float(tmp_gmem(4*i+3))));
-- write(li, LF);
-- end loop;
-- writeline(OUTPUT, li);
-- for i in 0 to 7 loop
-- write(li, to_real(to_float(tmp_gmem(2*i))));
-- swrite(li, " +j ");
-- write(li, to_real(to_float(tmp_gmem(2*i+1))));
-- write(li, LF);
-- end loop;
-- writeline(OUTPUT, li);
if must_data((k+1)*DATA_W-1 downto k*DATA_W+18) /= wdata(i)((k+1)*DATA_W-1 downto k*DATA_W+18) then
-- ignore some lsbs
assert false severity failure;
end if;
end if;
end if;
elsif kernel_name /= sum_atomic then
if wstrb(i)((k+1)*DATA_W/8-1 downto k*DATA_W) = X"F" and
must_data((k+1)*DATA_W-1 downto k*DATA_W) /= wdata(i)((k+1)*DATA_W-1 downto k*DATA_W) then
write(output, "wdata word " & integer'image(k) & " on AXI " & integer'image(i) & " is " &
integer'image(to_integer(unsigned(wdata(i)((k+1)*DATA_W-1 downto k*DATA_W)))) &
" (should be " & integer'image(to_integer(unsigned(must_data((k+1)*DATA_W-1 downto k*DATA_W)))) & ") for word_addr = " &
integer'image(word_addr+k) & LF);
assert false severity failure;
end if;
end if;
if wstrb(i)(k*DATA_W/8) = '1' then
if written_addrs(word_addr+k) = '0' then
written_count_tmp := written_count_tmp + 1;
else
-- report "double write";
end if;
written_addrs(word_addr+k) <= '1';
end if;
end loop;
-- }}}
when others =>
report "undefined computation type!" severity failure;
end case;
end if;
end if;
end loop;
end procedure;
procedure check_written_count(num: integer) is
begin
if written_count = num then
if STAT = 0 then
report "Kernel finished successfully! Size was :"&integer'image(num);
end if;
else
report "XXXXXXXXXXXXXXXXXXXX NOT ALL RESULTS ARE WRITTEN XXXXXXXXXXXXXXXXXX ! Size was :"&integer'image(num)& " written are: "&integer'image(written_count);
for i in 0 to num-1 loop
assert written_addrs(i) = '1' report "The address "&integer'image(i)&" is not written" severity failure;
end loop;
assert false severity failure;
end if;
end procedure;
-- }}}
begin
if rising_edge(clk) then
written_count_tmp := 0;
check_kernel;
new_kernel_d0 <= new_kernel;
new_kernel_d1 <= new_kernel_d0;
if new_kernel = '1' then
written_count <= 0;
written_addrs <= (others=>'0');
if kernel_name = bitonic then
for i in 0 to 2**16-1 loop
tmp_gmem(i) <= std_logic_vector(to_unsigned(i, 32));
end loop;
nStages := 1;
tmp_integer := 1;
while tmp_integer < size_0 loop
tmp_integer := tmp_integer * 2;
nStages := nStages + 1;
end loop;
stageIndx := 0;
passIndx := 0;
elsif kernel_name = fft_hard then
nStages := 1;
tmp_integer := 1;
while tmp_integer < size_0 loop
tmp_integer := tmp_integer * 2;
nStages := nStages + 1;
end loop;
stageIndx := 0;
-- with bit reverse
for i in 0 to size_0*2-1 loop
tmp_unsigned := to_unsigned(i, 32);
for j in 0 to nStages/2 loop
tmp_std_logic := tmp_unsigned(nStages-1-j);
tmp_unsigned(nStages-1-j) := tmp_unsigned(j);
tmp_unsigned(j) := tmp_std_logic;
end loop;
tmp_gmem(2*to_integer(tmp_unsigned)) <= to_slv(to_float(i mod 4)); -- real part
tmp_gmem(2*to_integer(tmp_unsigned)+1) <= (others=>'0'); -- imaginary part
end loop;
end if;
else
written_count <= written_count + written_count_tmp;
if new_kernel_d0 = '1' then
if kernel_name = bitonic then
bitonic_round;
if passIndx = stageIndx then
passIndx := 0;
stageIndx := stageIndx + 1;
else
passIndx := passIndx + 1;
end if;
elsif kernel_name = fft_hard then
-- report "tmp_gmem = ";
-- for i in 0 to 7 loop
-- write(li, to_real(to_float(tmp_gmem(2*i))));
-- swrite(li, " +j ");
-- write(li, to_real(to_float(tmp_gmem(2*i+1))));
-- write(li, LF);
-- end loop;
-- writeline(OUTPUT, li);
fft_round;
stageIndx := stageIndx + 1;
elsif kernel_name = median then
compute_median;
elsif kernel_name = max_half_atomic then
compute_max_half_atomic;
end if;
end if;
end if;
if finished_kernel = '1' then
if kernel_name = bitonic then
-- if passIndx /= 1 then
if kernel_name = bitonic then
bitonic_round;
else
bitonic_float_round;
end if;
-- end if;
if passIndx = stageIndx then
passIndx := 0;
stageIndx := stageIndx + 1;
else
passIndx := passIndx + 1;
end if;
elsif kernel_name = fft_hard then
fft_round;
stageIndx := stageIndx + 1;
elsif kernel_name = sum_atomic or kernel_name = max_half_atomic then
assert must_data(DATA_W-1 downto 0) = gmem(65536)(DATA_W-1 downto 0)
report "result is " & integer'image(to_integer(unsigned(gmem(65536)(DATA_W-1 downto 0))))& " (must be " &
integer'image(to_integer(unsigned(must_data(DATA_W-1 downto 0)))) & ")"
severity failure;
-- report "wdata word " & integer'image(k) & " on AXI " & integer'image(i) & " is " &
-- integer'image(to_integer(unsigned(wdata(i)((k+1)*DATA_W-1 downto k*DATA_W)))) &
-- " (should be " & integer'image(to_integer(unsigned(must_data((k+1)*DATA_W-1 downto k*DATA_W)))) & ") for word_addr = " &
-- integer'image(word_addr+k) severity failure;
-- report integer'image(to_integer(unsigned(must_data(DATA_W-1 downto 0))));
check_written_count(1);
else
if COMP_TYPE = 0 then -- byte mode
check_written_count(size_0*size_1*4);
elsif kernel_name = median then
check_written_count(size_0*size_1-2*(size_0-1)-2*(size_1-1)); -- no write for edge pixels
else
check_written_count(size_0*size_1);
end if;
end if;
end if;
-- write(li, std_logic_vector(wr_addr_offset(0)));
-- writeline(OUTPUT, li);
-- report "written addr: " & integer'image(2*(wr_addr_int-16#400#));
end if;
end process;
---------------------------------------------------------------------------------------------------------}}}
-- performance measurements ------------------------------------------------------------------------------{{{
perf_count: if STAT = 1 generate
process(clk)
-- variable n_empty_bytes, n_written_bytes : natural := 0;
-- variable empty_bytes_percentage: real := 0.0;
variable min_n_bursts, n_wr_increase, n_rd_increase : real := 0.0;
variable min_n_read_bursts, min_n_write_bursts : real := 0.0;
variable n_wr_bursts, n_rd_bursts : natural := 0;
variable size, data_size_word : natural := 0;
begin
if rising_edge(clk) then
if finished_kernel = '1' then
if kernel_name = sum_atomic or kernel_name = max_half_atomic then
data_size_word := problemSize;
-- empty_bytes_percentage := real(n_empty_bytes)/real(n_written_bytes);
-- report "# of written empty bytes = " & integer'image(n_empty_bytes);
-- report "# of written bytes = " & integer'image(n_written_bytes);
min_n_read_bursts := ceil(real(data_size_word)/real(GMEM_N_BANK)/real(to_integer(unsigned(mx_arlen_awlen)+1))); -- smallest number of bursts need ti finish the task
min_n_write_bursts := ceil(real(1)/real(GMEM_N_BANK)/real(to_integer(unsigned(mx_arlen_awlen)+1)));
n_wr_increase := real(n_wr_bursts)/min_n_write_bursts*100.0 - 100.0;
n_rd_increase := real(n_rd_bursts)/min_n_read_bursts*100.0 - 100.0;
report "Problem size= "&integer'image(data_size_word) & ", # WR Bursts= " & integer'image(n_wr_bursts) & " (+" & integer'image(integer(n_wr_increase)) &"%)" &
", # RD Bursts= " & integer'image(n_rd_bursts) & " (+" & integer'image(integer(n_rd_increase)) &"%)";
-- n_empty_bytes := 0;
-- n_written_bytes := 0;
n_wr_bursts := 0;
n_rd_bursts := 0;
elsif kernel_name /= bitonic and kernel_name /= fft_hard then
size := size_0*size_1;
if COMP_TYPE = 0 then -- byte
data_size_word := size_0*size_1 / 4;
elsif COMP_TYPE = 1 then -- half word
data_size_word := size_0*size_1 / 2;
else -- word
data_size_word := size_0*size_1;
end if;
-- empty_bytes_percentage := real(n_empty_bytes)/real(n_written_bytes);
-- report "# of written empty bytes = " & integer'image(n_empty_bytes);
-- report "# of written bytes = " & integer'image(n_written_bytes);
min_n_bursts := ceil(real(data_size_word)/real(GMEM_N_BANK)/real(to_integer(unsigned(mx_arlen_awlen)+1))); -- smallest number of bursts need ti finish the task
n_wr_increase := real(n_wr_bursts)/min_n_bursts*100.0 - 100.0;
n_rd_increase := real(n_rd_bursts)/min_n_bursts*100.0 - 100.0;
-- report "Size= "&integer'image(data_size_word) &", Empty written bytes = " & integer'image(integer(empty_bytes_percentage)) & " %"&", # Bursts= " &
-- integer'image(n_wr_bursts) & " (+" & integer'image(integer(n_wr_increase)) &" %)";
report "Size= "&integer'image(size) & ", # WR Bursts= " & integer'image(n_wr_bursts) & " (+" & integer'image(integer(n_wr_increase)) &"%)" &
", # RD Bursts= " & integer'image(n_rd_bursts) & " (+" & integer'image(integer(n_rd_increase)) &"%)";
-- n_empty_bytes := 0;
-- n_written_bytes := 0;
n_wr_bursts := 0;
n_rd_bursts := 0;
end if;
else
for i in 0 to N_AXI-1 loop
if awvalid(i) = '1' and awready(i) = '1' then
n_wr_bursts := n_wr_bursts + 1;
end if;
if arvalid(i) = '1' and arready(i) = '1' then
n_rd_bursts := n_rd_bursts + 1;
end if;
-- if wvalid(i) = '1' then
-- for j in 0 to GMEM_DATA_W/8-1 loop
-- if wstrb(i)(j) = '1' then
-- -- n_written_bytes := n_written_bytes + 1;
-- else
-- -- n_empty_bytes := n_empty_bytes + 1;
-- end if;
-- end loop;
-- end if;
end loop;
end if;
end if;
end process;
end generate;
---------------------------------------------------------------------------------------------------------}}}
---------------------------------------------------------------------------------------------------------- }}}
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.netcomp.all;
library gaisler;
use gaisler.pci.all;
use work.pcilib2.all;
entity grpci2_phy_wrapper is
generic(
tech : integer := DEFMEMTECH;
oepol : integer := 0;
bypass : integer range 0 to 1 := 1;
netlist : integer := 0;
scantest: integer := 0;
iotest : integer := 0
);
port(
pciclk : in std_logic;
pcii : in pci_in_type;
phyi : in grpci2_phy_in_type;
pcio : out pci_out_type;
phyo : out grpci2_phy_out_type;
iotmact : in std_ulogic;
iotmoe : in std_ulogic;
iotdout : in std_logic_vector(44 downto 0);
iotdin : out std_logic_vector(45 downto 0)
);
end;
architecture wrapper of grpci2_phy_wrapper is
attribute dont_touch : boolean;
attribute dont_touch of net : label is true;
begin
rtl : if netlist = 0 generate
phy0 : grpci2_phy
generic map( tech => tech, oepol => oepol,
bypass => bypass, netlist => netlist,
scantest => scantest, iotest => iotest)
port map(
pciclk => pciclk,
pcii => pcii,
phyi => phyi,
pcio => pcio,
phyo => phyo,
iotmact => iotmact,
iotmoe => iotmoe,
iotdout => iotdout,
iotdin => iotdin
);
end generate;
net : if netlist /= 0 generate
phy0 : grpci2_phy_net
generic map( tech => tech, oepol => oepol,
bypass => bypass, netlist => netlist)
port map(
pciclk => pciclk,
--pcii : in pci_in_type,
pcii_rst => pcii.rst,
pcii_gnt => pcii.gnt,
pcii_idsel => pcii.idsel,
pcii_ad => pcii.ad,
pcii_cbe => pcii.cbe,
pcii_frame => pcii.frame,
pcii_irdy => pcii.irdy,
pcii_trdy => pcii.trdy,
pcii_devsel => pcii.devsel,
pcii_stop => pcii.stop,
pcii_lock => pcii.lock,
pcii_perr => pcii.perr,
pcii_serr => pcii.serr,
pcii_par => pcii.par,
pcii_host => pcii.host,
pcii_pci66 => pcii.pci66,
pcii_pme_status => pcii.pme_status,
pcii_int => pcii.int,
--phyi : in grpci2_phy_in_type,
phyi_pcirstout => phyi.pcirstout,
phyi_pciasyncrst => phyi.pciasyncrst,
phyi_pcisoftrst => phyi.pcisoftrst,
phyi_pciinten => phyi.pciinten,
phyi_m_request => phyi.m_request,
phyi_m_mabort => phyi.m_mabort,
phyi_pr_m_fstate => phyi.pr_m_fstate,
phyi_pr_m_cfifo_0_data => phyi.pr_m_cfifo(0).data,
phyi_pr_m_cfifo_0_last => phyi.pr_m_cfifo(0).last,
phyi_pr_m_cfifo_0_stlast => phyi.pr_m_cfifo(0).stlast,
phyi_pr_m_cfifo_0_hold => phyi.pr_m_cfifo(0).hold,
phyi_pr_m_cfifo_0_valid => phyi.pr_m_cfifo(0).valid,
phyi_pr_m_cfifo_0_err => phyi.pr_m_cfifo(0).err,
phyi_pr_m_cfifo_1_data => phyi.pr_m_cfifo(1).data,
phyi_pr_m_cfifo_1_last => phyi.pr_m_cfifo(1).last,
phyi_pr_m_cfifo_1_stlast => phyi.pr_m_cfifo(1).stlast,
phyi_pr_m_cfifo_1_hold => phyi.pr_m_cfifo(1).hold,
phyi_pr_m_cfifo_1_valid => phyi.pr_m_cfifo(1).valid,
phyi_pr_m_cfifo_1_err => phyi.pr_m_cfifo(1).err,
phyi_pr_m_cfifo_2_data => phyi.pr_m_cfifo(2).data,
phyi_pr_m_cfifo_2_last => phyi.pr_m_cfifo(2).last,
phyi_pr_m_cfifo_2_stlast => phyi.pr_m_cfifo(2).stlast,
phyi_pr_m_cfifo_2_hold => phyi.pr_m_cfifo(2).hold,
phyi_pr_m_cfifo_2_valid => phyi.pr_m_cfifo(2).valid,
phyi_pr_m_cfifo_2_err => phyi.pr_m_cfifo(2).err,
phyi_pv_m_cfifo_0_data => phyi.pv_m_cfifo(0).data,
phyi_pv_m_cfifo_0_last => phyi.pv_m_cfifo(0).last,
phyi_pv_m_cfifo_0_stlast => phyi.pv_m_cfifo(0).stlast,
phyi_pv_m_cfifo_0_hold => phyi.pv_m_cfifo(0).hold,
phyi_pv_m_cfifo_0_valid => phyi.pv_m_cfifo(0).valid,
phyi_pv_m_cfifo_0_err => phyi.pv_m_cfifo(0).err,
phyi_pv_m_cfifo_1_data => phyi.pv_m_cfifo(1).data,
phyi_pv_m_cfifo_1_last => phyi.pv_m_cfifo(1).last,
phyi_pv_m_cfifo_1_stlast => phyi.pv_m_cfifo(1).stlast,
phyi_pv_m_cfifo_1_hold => phyi.pv_m_cfifo(1).hold,
phyi_pv_m_cfifo_1_valid => phyi.pv_m_cfifo(1).valid,
phyi_pv_m_cfifo_1_err => phyi.pv_m_cfifo(1).err,
phyi_pv_m_cfifo_2_data => phyi.pv_m_cfifo(2).data,
phyi_pv_m_cfifo_2_last => phyi.pv_m_cfifo(2).last,
phyi_pv_m_cfifo_2_stlast => phyi.pv_m_cfifo(2).stlast,
phyi_pv_m_cfifo_2_hold => phyi.pv_m_cfifo(2).hold,
phyi_pv_m_cfifo_2_valid => phyi.pv_m_cfifo(2).valid,
phyi_pv_m_cfifo_2_err => phyi.pv_m_cfifo(2).err,
phyi_pr_m_addr => phyi.pr_m_addr,
phyi_pr_m_cbe_data => phyi.pr_m_cbe_data,
phyi_pr_m_cbe_cmd => phyi.pr_m_cbe_cmd,
phyi_pr_m_first => phyi.pr_m_first,
phyi_pv_m_term => phyi.pv_m_term,
phyi_pr_m_ltimer => phyi.pr_m_ltimer,
phyi_pr_m_burst => phyi.pr_m_burst,
phyi_pr_m_abort => phyi.pr_m_abort,
phyi_pr_m_perren => phyi.pr_m_perren,
phyi_pr_m_done_fifo => phyi.pr_m_done_fifo,
phyi_t_abort => phyi.t_abort,
phyi_t_ready => phyi.t_ready,
phyi_t_retry => phyi.t_retry,
phyi_pr_t_state => phyi.pr_t_state,
phyi_pv_t_state => phyi.pv_t_state,
phyi_pr_t_fstate => phyi.pr_t_fstate,
phyi_pr_t_cfifo_0_data => phyi.pr_t_cfifo(0).data,
phyi_pr_t_cfifo_0_last => phyi.pr_t_cfifo(0).last,
phyi_pr_t_cfifo_0_stlast => phyi.pr_t_cfifo(0).stlast,
phyi_pr_t_cfifo_0_hold => phyi.pr_t_cfifo(0).hold,
phyi_pr_t_cfifo_0_valid => phyi.pr_t_cfifo(0).valid,
phyi_pr_t_cfifo_0_err => phyi.pr_t_cfifo(0).err,
phyi_pr_t_cfifo_1_data => phyi.pr_t_cfifo(1).data,
phyi_pr_t_cfifo_1_last => phyi.pr_t_cfifo(1).last,
phyi_pr_t_cfifo_1_stlast => phyi.pr_t_cfifo(1).stlast,
phyi_pr_t_cfifo_1_hold => phyi.pr_t_cfifo(1).hold,
phyi_pr_t_cfifo_1_valid => phyi.pr_t_cfifo(1).valid,
phyi_pr_t_cfifo_1_err => phyi.pr_t_cfifo(1).err,
phyi_pr_t_cfifo_2_data => phyi.pr_t_cfifo(2).data,
phyi_pr_t_cfifo_2_last => phyi.pr_t_cfifo(2).last,
phyi_pr_t_cfifo_2_stlast => phyi.pr_t_cfifo(2).stlast,
phyi_pr_t_cfifo_2_hold => phyi.pr_t_cfifo(2).hold,
phyi_pr_t_cfifo_2_valid => phyi.pr_t_cfifo(2).valid,
phyi_pr_t_cfifo_2_err => phyi.pr_t_cfifo(2).err,
phyi_pv_t_diswithout => phyi.pv_t_diswithout,
phyi_pr_t_stoped => phyi.pr_t_stoped,
phyi_pr_t_lcount => phyi.pr_t_lcount,
phyi_pr_t_first_word => phyi.pr_t_first_word,
phyi_pr_t_cur_acc_0_read => phyi.pr_t_cur_acc_0_read,
phyi_pv_t_hold_write => phyi.pv_t_hold_write,
phyi_pv_t_hold_reset => phyi.pv_t_hold_reset,
phyi_pr_conf_comm_perren => phyi.pr_conf_comm_perren,
phyi_pr_conf_comm_serren => phyi.pr_conf_comm_serren,
--pcio : out pci_out_type,
pcio_aden => pcio.aden,
pcio_vaden => pcio.vaden,
pcio_cbeen => pcio.cbeen,
pcio_frameen => pcio.frameen,
pcio_irdyen => pcio.irdyen,
pcio_trdyen => pcio.trdyen,
pcio_devselen => pcio.devselen,
pcio_stopen => pcio.stopen,
pcio_ctrlen => pcio.ctrlen,
pcio_perren => pcio.perren,
pcio_paren => pcio.paren,
pcio_reqen => pcio.reqen,
pcio_locken => pcio.locken,
pcio_serren => pcio.serren,
pcio_inten => pcio.inten,
pcio_vinten => pcio.vinten,
pcio_req => pcio.req,
pcio_ad => pcio.ad,
pcio_cbe => pcio.cbe,
pcio_frame => pcio.frame,
pcio_irdy => pcio.irdy,
pcio_trdy => pcio.trdy,
pcio_devsel => pcio.devsel,
pcio_stop => pcio.stop,
pcio_perr => pcio.perr,
pcio_serr => pcio.serr,
pcio_par => pcio.par,
pcio_lock => pcio.lock,
pcio_power_state => pcio.power_state,
pcio_pme_enable => pcio.pme_enable,
pcio_pme_clear => pcio.pme_clear,
pcio_int => pcio.int,
pcio_rst => pcio.rst,
--phyo : out grpci2_phy_out_type
phyo_pciv_rst => phyo.pciv.rst,
phyo_pciv_gnt => phyo.pciv.gnt,
phyo_pciv_idsel => phyo.pciv.idsel,
phyo_pciv_ad => phyo.pciv.ad,
phyo_pciv_cbe => phyo.pciv.cbe,
phyo_pciv_frame => phyo.pciv.frame,
phyo_pciv_irdy => phyo.pciv.irdy,
phyo_pciv_trdy => phyo.pciv.trdy,
phyo_pciv_devsel => phyo.pciv.devsel,
phyo_pciv_stop => phyo.pciv.stop,
phyo_pciv_lock => phyo.pciv.lock,
phyo_pciv_perr => phyo.pciv.perr,
phyo_pciv_serr => phyo.pciv.serr,
phyo_pciv_par => phyo.pciv.par,
phyo_pciv_host => phyo.pciv.host,
phyo_pciv_pci66 => phyo.pciv.pci66,
phyo_pciv_pme_status => phyo.pciv.pme_status,
phyo_pciv_int => phyo.pciv.int,
phyo_pr_m_state => phyo.pr_m_state,
phyo_pr_m_last => phyo.pr_m_last,
phyo_pr_m_hold => phyo.pr_m_hold,
phyo_pr_m_term => phyo.pr_m_term,
phyo_pr_t_hold => phyo.pr_t_hold,
phyo_pr_t_stop => phyo.pr_t_stop,
phyo_pr_t_abort => phyo.pr_t_abort,
phyo_pr_t_diswithout => phyo.pr_t_diswithout,
phyo_pr_t_addr_perr => phyo.pr_t_addr_perr,
phyo_pcirsto => phyo.pcirsto,
phyo_pr_po_ad => phyo.pr_po.ad,
phyo_pr_po_aden => phyo.pr_po.aden,
phyo_pr_po_cbe => phyo.pr_po.cbe,
phyo_pr_po_cbeen => phyo.pr_po.cbeen,
phyo_pr_po_frame => phyo.pr_po.frame,
phyo_pr_po_frameen => phyo.pr_po.frameen,
phyo_pr_po_irdy => phyo.pr_po.irdy,
phyo_pr_po_irdyen => phyo.pr_po.irdyen,
phyo_pr_po_trdy => phyo.pr_po.trdy,
phyo_pr_po_trdyen => phyo.pr_po.trdyen,
phyo_pr_po_stop => phyo.pr_po.stop,
phyo_pr_po_stopen => phyo.pr_po.stopen,
phyo_pr_po_devsel => phyo.pr_po.devsel,
phyo_pr_po_devselen => phyo.pr_po.devselen,
phyo_pr_po_par => phyo.pr_po.par,
phyo_pr_po_paren => phyo.pr_po.paren,
phyo_pr_po_perr => phyo.pr_po.perr,
phyo_pr_po_perren => phyo.pr_po.perren,
phyo_pr_po_lock => phyo.pr_po.lock,
phyo_pr_po_locken => phyo.pr_po.locken,
phyo_pr_po_req => phyo.pr_po.req,
phyo_pr_po_reqen => phyo.pr_po.reqen,
phyo_pr_po_serren => phyo.pr_po.serren,
phyo_pr_po_inten => phyo.pr_po.inten,
phyo_pr_po_vinten => phyo.pr_po.vinten,
phyo_pio_rst => phyo.pio.rst,
phyo_pio_gnt => phyo.pio.gnt,
phyo_pio_idsel => phyo.pio.idsel,
phyo_pio_ad => phyo.pio.ad,
phyo_pio_cbe => phyo.pio.cbe,
phyo_pio_frame => phyo.pio.frame,
phyo_pio_irdy => phyo.pio.irdy,
phyo_pio_trdy => phyo.pio.trdy,
phyo_pio_devsel => phyo.pio.devsel,
phyo_pio_stop => phyo.pio.stop,
phyo_pio_lock => phyo.pio.lock,
phyo_pio_perr => phyo.pio.perr,
phyo_pio_serr => phyo.pio.serr,
phyo_pio_par => phyo.pio.par,
phyo_pio_host => phyo.pio.host,
phyo_pio_pci66 => phyo.pio.pci66,
phyo_pio_pme_status => phyo.pio.pme_status,
phyo_pio_int => phyo.pio.int,
phyo_poo_ad => phyo.poo.ad,
phyo_poo_aden => phyo.poo.aden,
phyo_poo_cbe => phyo.poo.cbe,
phyo_poo_cbeen => phyo.poo.cbeen,
phyo_poo_frame => phyo.poo.frame,
phyo_poo_frameen => phyo.poo.frameen,
phyo_poo_irdy => phyo.poo.irdy,
phyo_poo_irdyen => phyo.poo.irdyen,
phyo_poo_trdy => phyo.poo.trdy,
phyo_poo_trdyen => phyo.poo.trdyen,
phyo_poo_stop => phyo.poo.stop,
phyo_poo_stopen => phyo.poo.stopen,
phyo_poo_devsel => phyo.poo.devsel,
phyo_poo_devselen => phyo.poo.devselen,
phyo_poo_par => phyo.poo.par,
phyo_poo_paren => phyo.poo.paren,
phyo_poo_perr => phyo.poo.perr,
phyo_poo_perren => phyo.poo.perren,
phyo_poo_lock => phyo.poo.lock,
phyo_poo_locken => phyo.poo.locken,
phyo_poo_req => phyo.poo.req,
phyo_poo_reqen => phyo.poo.reqen,
phyo_poo_serren => phyo.poo.serren,
phyo_poo_inten => phyo.poo.inten,
phyo_poo_vinten => phyo.poo.vinten
);
end generate;
end;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3;
constant CFG_MEMTECH : integer := spartan3;
constant CFG_PADTECH : integer := spartan3;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 8;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 1;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#00F0#;
constant CFG_GRGPIO_WIDTH : integer := (18);
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 1;
constant CFG_SVGA_ENABLE : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
--this is the COBS encoder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
library work;
use work.myDeclare.all;
entity cobs_encoder is
Port (
bus_clk : in std_logic;
reset : in std_logic;
--cobs inputs
pre_cobs_data_in : in async_stream_type;
data_in_length : in std_logic_vector(4 downto 0);
cobs_conv_begin : in std_logic;
--cobs outputs
cobs_data_out : out cobs_stream_types;
data_out_length : out std_logic_vector(4 downto 0);
cobs_conv_rdy : out std_logic
);
end cobs_encoder;
architecture Behavioral of cobs_encoder is
type cobs_sm_type is (IDLE, CONV);
signal cobs_sm : cobs_sm_type;
signal vec_cnt : unsigned(4 downto 0);
signal idxreg : unsigned(4 downto 0);
signal cobs_data : cobs_stream_types;
signal pre_cobs_data : cobs_stream_types; --this is put into cobs_data format with the padding for consistency.
begin
cobs_data_out <= cobs_data;
--cobs process
cobs_proc: process(bus_clk, reset, cobs_conv_begin, idxreg, vec_cnt)
begin
if (reset = '1') then
cobs_sm <= IDLE;
vec_cnt <= (others=>'0');
idxreg <= to_unsigned(24,5); --always initialized to 254, last position of the COBS data.
cobs_conv_rdy <= '0';
for i in 0 to 25 loop
cobs_data(i) <= (others=>'0');
pre_cobs_data(i) <= (others=>'0');
end loop;
elsif (rising_edge(bus_clk)) then
case cobs_sm is
when IDLE => --idle state
if cobs_conv_begin = '1' then
cobs_sm <= CONV;
vec_cnt <= unsigned(data_in_length); --initilize the vector count to data_in_length
idxreg <= unsigned(data_in_length)+1; --initlize reg1 to data_in_length
for i in 0 to 23 loop
pre_cobs_data(i+1) <= pre_cobs_data_in(i);
end loop;
pre_cobs_data(25) <= (others=>'0'); --always fill the 255 position with 0.
pre_cobs_data(0) <= (others=>'1');
data_out_length <= (others=>'0');
end if;
cobs_conv_rdy <= '0'; --lower the conv flag
when CONV =>
if vec_cnt >= 1 then
vec_cnt <= vec_cnt - 1;
if pre_cobs_data(to_integer(vec_cnt)) = "00000000" then
cobs_data(to_integer(vec_cnt)) <= "000" & std_logic_vector(idxreg - vec_cnt);
idxreg <= vec_cnt;
else
cobs_data(to_integer(vec_cnt)) <= pre_cobs_data(to_integer(vec_cnt));
end if;
else
cobs_sm <= IDLE;
cobs_data(0) <= "000" & std_logic_vector(idxreg);
cobs_conv_rdy <= '1';
data_out_length <= std_logic_vector(unsigned(data_in_length) + 2);
end if;
end case;
end if;
end process;
end Behavioral;
|
-- tracking_camera_system_jtag_uart_0_avalon_jtag_slave_translator.vhd
-- Generated using ACDS version 12.1sp1 243 at 2015.02.13.13:59:38
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tracking_camera_system_jtag_uart_0_avalon_jtag_slave_translator is
generic (
AV_ADDRESS_W : integer := 1;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 1;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(0 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_waitrequest : in std_logic := '0'; -- .waitrequest
av_chipselect : out std_logic; -- .chipselect
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_byteenable : out std_logic_vector(0 downto 0);
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_writebyteenable : out std_logic_vector(0 downto 0);
uav_clken : in std_logic := '0'
);
end entity tracking_camera_system_jtag_uart_0_avalon_jtag_slave_translator;
architecture rtl of tracking_camera_system_jtag_uart_0_avalon_jtag_slave_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(0 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_chipselect : out std_logic; -- chipselect
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component altera_merlin_slave_translator;
begin
jtag_uart_0_avalon_jtag_slave_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_waitrequest => av_waitrequest, -- .waitrequest
av_chipselect => av_chipselect, -- .chipselect
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
end architecture rtl; -- of tracking_camera_system_jtag_uart_0_avalon_jtag_slave_translator
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2914.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p03n01i02914ent IS
END c02s01b01x02p03n01i02914ent;
ARCHITECTURE c02s01b01x02p03n01i02914arch OF c02s01b01x02p03n01i02914ent IS
procedure proc1 (signal S1: out bit) is
variable V1 : bit;
begin
-- Failure_here : attribute DELAYED may not be read within a procedure
V1 := S1'DELAYED;
end proc1;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x02p03n01i02914 - The attribute DELAYED of formal signal parameters can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p03n01i02914arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2914.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p03n01i02914ent IS
END c02s01b01x02p03n01i02914ent;
ARCHITECTURE c02s01b01x02p03n01i02914arch OF c02s01b01x02p03n01i02914ent IS
procedure proc1 (signal S1: out bit) is
variable V1 : bit;
begin
-- Failure_here : attribute DELAYED may not be read within a procedure
V1 := S1'DELAYED;
end proc1;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x02p03n01i02914 - The attribute DELAYED of formal signal parameters can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p03n01i02914arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2914.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b01x02p03n01i02914ent IS
END c02s01b01x02p03n01i02914ent;
ARCHITECTURE c02s01b01x02p03n01i02914arch OF c02s01b01x02p03n01i02914ent IS
procedure proc1 (signal S1: out bit) is
variable V1 : bit;
begin
-- Failure_here : attribute DELAYED may not be read within a procedure
V1 := S1'DELAYED;
end proc1;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s01b01x02p03n01i02914 - The attribute DELAYED of formal signal parameters can not be read."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b01x02p03n01i02914arch;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:46:37 02/13/2017
-- Design Name:
-- Module Name: C:/Xilinx/__testbecher/testbencher/a_tb.vhd
-- Project Name: testbencher
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ABus2AXI4Lite
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY a_tb IS
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Master Bus Interface M00_AXI
C_MASTER_AXI_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"00000000";
C_MASTER_AXI_ADDR_WIDTH : integer := 32;
C_MASTER_AXI_DATA_WIDTH : integer := 32;
C_SLAVE_AXI_ADDR_WIDTH : integer := 32;
C_SLAVE_AXI_DATA_WIDTH : integer := 32;
C_FILESYS_AXI_ADDR_WIDTH : integer := 32;
C_FILESYS_AXI_DATA_WIDTH : integer := 32
);
END a_tb;
ARCHITECTURE behavior OF a_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ABus2AXI4Lite
PORT(
-- abus ports
abus_address : in std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
abus_data_in : in std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_data_out : out std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_data_direction : out std_logic := '0'; -- .direction
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
abus_wait : out std_logic := '1'; -- .waitrequest
abus_wait_direction : out std_logic := '0'; -- .direction
abus_irq : out std_logic := '0'; -- .interrupt
abus_irq_direction : out std_logic := '0'; -- .direction
abus_reset : in std_logic := '0'; -- .saturn_reset
-- Ports of Axi Master Bus Interface
master_axi_aclk : in std_logic;
master_axi_aresetn : in std_logic;
master_axi_awaddr : out std_logic_vector(C_MASTER_AXI_ADDR_WIDTH-1 downto 0);
master_axi_awprot : out std_logic_vector(2 downto 0);
master_axi_awvalid : out std_logic;
master_axi_awready : in std_logic;
master_axi_wdata : out std_logic_vector(C_MASTER_AXI_DATA_WIDTH-1 downto 0);
master_axi_wstrb : out std_logic_vector(C_MASTER_AXI_DATA_WIDTH/8-1 downto 0);
master_axi_wvalid : out std_logic;
master_axi_wready : in std_logic;
master_axi_bresp : in std_logic_vector(1 downto 0);
master_axi_bvalid : in std_logic;
master_axi_bready : out std_logic;
master_axi_araddr : out std_logic_vector(C_MASTER_AXI_ADDR_WIDTH-1 downto 0);
master_axi_arprot : out std_logic_vector(2 downto 0);
master_axi_arvalid : out std_logic;
master_axi_arready : in std_logic;
master_axi_rdata : in std_logic_vector(C_MASTER_AXI_DATA_WIDTH-1 downto 0);
master_axi_rresp : in std_logic_vector(1 downto 0);
master_axi_rvalid : in std_logic;
master_axi_rready : out std_logic;
-- Ports of Slave Bus Interface
slave_axi_aclk : in std_logic;
slave_axi_aresetn : in std_logic;
slave_axi_awaddr : in std_logic_vector(C_SLAVE_AXI_ADDR_WIDTH-1 downto 0);
slave_axi_awprot : in std_logic_vector(2 downto 0);
slave_axi_awvalid : in std_logic;
slave_axi_awready : out std_logic;
slave_axi_wdata : in std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
slave_axi_wstrb : in std_logic_vector(C_SLAVE_AXI_DATA_WIDTH/8-1 downto 0);
slave_axi_wvalid : in std_logic;
slave_axi_wready : out std_logic;
slave_axi_bresp : out std_logic_vector(1 downto 0);
slave_axi_bvalid : out std_logic;
slave_axi_bready : in std_logic;
slave_axi_araddr : in std_logic_vector(C_SLAVE_AXI_ADDR_WIDTH-1 downto 0);
slave_axi_arprot : in std_logic_vector(2 downto 0);
slave_axi_arvalid : in std_logic;
slave_axi_arready : out std_logic;
slave_axi_rdata : out std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
slave_axi_rresp : out std_logic_vector(1 downto 0);
slave_axi_rvalid : out std_logic;
slave_axi_rready : in std_logic
);
END COMPONENT;
COMPONENT test_mem
PORT(
s_aclk : IN std_logic;
s_aresetn : IN std_logic;
s_axi_awaddr : in std_logic_vector(31 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(31 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic
);
END COMPONENT;
--Inputs
signal abus_address : std_logic_vector(25 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal abus_chipselect : std_logic_vector(2 downto 0) := (others => '0');
signal abus_read : std_logic := '0';
signal abus_write : std_logic_vector(1 downto 0) := (others => '0');
signal abus_reset : std_logic := '0';
signal master_axi_init_axi_txn : std_logic := '0';
signal master_axi_aclk : std_logic := '0';
signal master_axi_aresetn : std_logic := '0';
signal master_axi_awready : std_logic := '0';
signal master_axi_wready : std_logic := '0';
signal master_axi_bresp : std_logic_vector(1 downto 0) := (others => '0');
signal master_axi_bvalid : std_logic := '0';
signal master_axi_arready : std_logic := '0';
signal master_axi_rdata : std_logic_vector(31 downto 0) := (others => '0');
signal master_axi_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal master_axi_rvalid : std_logic := '0';
signal slave_axi_awaddr : std_logic_vector(31 downto 0) := (others => '0');
signal slave_axi_awprot : std_logic_vector(2 downto 0) := (others => '0');
signal slave_axi_awvalid : std_logic := '0';
signal slave_axi_wdata : std_logic_vector(31 downto 0) := (others => '0');
signal slave_axi_wstrb : std_logic_vector(3 downto 0) := (others => '0');
signal slave_axi_wvalid : std_logic := '0';
signal slave_axi_bready : std_logic := '0';
signal slave_axi_araddr : std_logic_vector(31 downto 0) := (others => '0');
signal slave_axi_arprot : std_logic_vector(2 downto 0) := (others => '0');
signal slave_axi_arvalid : std_logic := '0';
signal slave_axi_rready : std_logic := '0';
--Outputs
signal abus_data_out : std_logic_vector(15 downto 0);
signal abus_data_direction : std_logic := '0';
signal abus_wait : std_logic := '0';
signal abus_wait_direction : std_logic := '0';
signal abus_irq : std_logic := '0';
signal abus_irq_direction : std_logic := '0';
signal master_axi_error : std_logic := '0';
signal master_axi_txn_done : std_logic := '0';
signal master_axi_awaddr : std_logic_vector(31 downto 0) := (others => '0');
signal master_axi_awprot : std_logic_vector(2 downto 0) := (others => '0');
signal master_axi_awvalid : std_logic := '0';
signal master_axi_wdata : std_logic_vector(31 downto 0) := (others => '0');
signal master_axi_wstrb : std_logic_vector(3 downto 0) := (others => '0');
signal master_axi_wvalid : std_logic := '0';
signal master_axi_bready : std_logic := '0';
signal master_axi_araddr : std_logic_vector(31 downto 0) := (others => '0');
signal master_axi_arprot : std_logic_vector(2 downto 0) := (others => '0');
signal master_axi_arvalid : std_logic := '0';
signal master_axi_rready : std_logic := '0';
signal slave_axi_aclk : std_logic := '0';
signal slave_axi_aresetn : std_logic := '0';
signal slave_axi_awready : std_logic := '0';
signal slave_axi_wready : std_logic := '0';
signal slave_axi_bresp : std_logic_vector(1 downto 0) := (others => '0');
signal slave_axi_bvalid : std_logic := '0';
signal slave_axi_arready : std_logic := '0';
signal slave_axi_rdata : std_logic_vector(31 downto 0) := (others => '0');
signal slave_axi_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal slave_axi_rvalid : std_logic := '0';
-- Clock period definitions
constant master_axi_aclk_period : time := 10 ns;
procedure abus_write_proc (addr : in std_logic_vector(25 downto 0);
data : in std_logic_vector(15 downto 0);
chipselect : in std_logic_vector(2 downto 0);
signal ABus_Ad : out std_logic_vector(25 downto 0);
signal ABus_Da : out std_logic_vector(15 downto 0);
signal ABus_CS : out std_logic_vector(2 downto 0);
signal ABus_Wr : out std_logic_vector(1 downto 0)
) is
begin
--set quantizer 25mhz
ABus_Ad <= addr;
ABus_Da <= data;
wait for 100ns;
ABus_CS <= chipselect;
wait for 100ns;
ABus_Wr <= "00";
wait for 1000ns;
ABus_Wr <= "11";
wait for 100ns;
ABus_CS <= "111";
ABus_Da <= (others => 'Z');
wait for 100ns;
end abus_write_proc;
procedure abus_read_proc (addr : in std_logic_vector(25 downto 0);
chipselect : in std_logic_vector(2 downto 0);
signal ABus_Ad : out std_logic_vector(25 downto 0);
signal ABus_CS : out std_logic_vector(2 downto 0);
signal ABus_Re : out std_logic
) is
begin
--set quantizer 25mhz
ABus_Ad <= addr;
wait for 100ns;
ABus_CS <= chipselect;
wait for 100ns;
ABus_Re <= '0';
wait for 1000ns;
ABus_Re <= '1';
wait for 100ns;
ABus_CS <= "111";
wait for 100ns;
end abus_read_proc;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ABus2AXI4Lite PORT MAP (
abus_address => abus_address,
abus_data_in => abus_data_in,
abus_data_out => abus_data_out,
abus_data_direction => abus_data_direction,
abus_chipselect => abus_chipselect,
abus_read => abus_read,
abus_write => abus_write,
abus_wait => abus_wait,
abus_wait_direction => abus_wait_direction,
abus_irq => abus_irq,
abus_irq_direction => abus_irq_direction,
abus_reset => abus_reset,
master_axi_aclk => master_axi_aclk,
master_axi_aresetn => master_axi_aresetn,
master_axi_awaddr => master_axi_awaddr,
master_axi_awprot => master_axi_awprot,
master_axi_awvalid => master_axi_awvalid,
master_axi_awready => master_axi_awready,
master_axi_wdata => master_axi_wdata,
master_axi_wstrb => master_axi_wstrb,
master_axi_wvalid => master_axi_wvalid,
master_axi_wready => master_axi_wready,
master_axi_bresp => master_axi_bresp,
master_axi_bvalid => master_axi_bvalid,
master_axi_bready => master_axi_bready,
master_axi_araddr => master_axi_araddr,
master_axi_arprot => master_axi_arprot,
master_axi_arvalid => master_axi_arvalid,
master_axi_arready => master_axi_arready,
master_axi_rdata => master_axi_rdata,
master_axi_rresp => master_axi_rresp,
master_axi_rvalid => master_axi_rvalid,
master_axi_rready => master_axi_rready,
slave_axi_aclk => slave_axi_aclk,
slave_axi_aresetn => slave_axi_aresetn,
slave_axi_awaddr => slave_axi_awaddr,
slave_axi_awprot => slave_axi_awprot,
slave_axi_awvalid => slave_axi_awvalid,
slave_axi_awready => slave_axi_awready,
slave_axi_wdata => slave_axi_wdata,
slave_axi_wstrb => slave_axi_wstrb,
slave_axi_wvalid => slave_axi_wvalid,
slave_axi_wready => slave_axi_wready,
slave_axi_bresp => slave_axi_bresp,
slave_axi_bvalid => slave_axi_bvalid,
slave_axi_bready => slave_axi_bready,
slave_axi_araddr => slave_axi_araddr,
slave_axi_arprot => slave_axi_arprot,
slave_axi_arvalid => slave_axi_arvalid,
slave_axi_arready => slave_axi_arready,
slave_axi_rdata => slave_axi_rdata,
slave_axi_rresp => slave_axi_rresp,
slave_axi_rvalid => slave_axi_rvalid,
slave_axi_rready => slave_axi_rready
);
das_mem: test_mem PORT MAP (
s_aclk => master_axi_aclk,
s_aresetn => master_axi_aresetn,
s_axi_awaddr => master_axi_awaddr,
s_axi_awvalid => master_axi_awvalid,
s_axi_awready => master_axi_awready,
s_axi_wdata => master_axi_wdata,
s_axi_wstrb => master_axi_wstrb,
s_axi_wvalid => master_axi_wvalid,
s_axi_wready => master_axi_wready,
s_axi_bresp => master_axi_bresp,
s_axi_bvalid => master_axi_bvalid,
s_axi_bready => master_axi_bready,
s_axi_araddr => master_axi_araddr,
s_axi_arvalid => master_axi_arvalid,
s_axi_arready => master_axi_arready,
s_axi_rdata => master_axi_rdata,
s_axi_rresp => master_axi_rresp,
s_axi_rvalid => master_axi_rvalid,
s_axi_rready => master_axi_rready
);
-- Clock process definitions
master_axi_aclk_process :process
begin
master_axi_aclk <= '0';
wait for master_axi_aclk_period/2;
master_axi_aclk <= '1';
wait for master_axi_aclk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
abus_write <= "11";
abus_read <= '1';
abus_chipselect <= "111";
master_axi_aresetn <= '0';
-- hold reset state for 100 ns.
wait for 100 ns;
wait for master_axi_aclk_period*10;
master_axi_aresetn <= '1';
-- insert stimulus here
--abus read transaction
wait for 1000 ns;
abus_write_proc("00"&X"000000",X"FADE","101",abus_address,abus_data_in,abus_chipselect,abus_write);
abus_write_proc("00"&X"000002",X"1193","101",abus_address,abus_data_in,abus_chipselect,abus_write);
abus_write_proc("00"&X"000004",X"0003","101",abus_address,abus_data_in,abus_chipselect,abus_write);
abus_write_proc("00"&X"000006",X"FACE","101",abus_address,abus_data_in,abus_chipselect,abus_write);
abus_read_proc("00"&X"000000","101",abus_address,abus_chipselect,abus_read);
abus_read_proc("00"&X"000002","101",abus_address,abus_chipselect,abus_read);
abus_read_proc("00"&X"000004","101",abus_address,abus_chipselect,abus_read);
abus_read_proc("00"&X"000006","101",abus_address,abus_chipselect,abus_read);
--wasca system regs write and read
wait for 1000 ns;
abus_write_proc("11"&X"FFFFF4",X"ACBD","110",abus_address,abus_data_in,abus_chipselect,abus_write); --mode
abus_read_proc("11"&X"FFFFF0","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFFFF2","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFFFF4","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFFFF8","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFFFFA","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFFFFC","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFFFFE","110",abus_address,abus_chipselect,abus_read);
--wasca filesystem regs write and read
wait for 1000 ns;
abus_write_proc("11"&X"FFEFF0",X"FADE","110",abus_address,abus_data_in,abus_chipselect,abus_write); --lock
abus_write_proc("11"&X"FFEFF2",X"0001","110",abus_address,abus_data_in,abus_chipselect,abus_write); --cmd
abus_read_proc("11"&X"FFFFF4","110",abus_address,abus_chipselect,abus_read);--status
abus_write_proc("11"&X"FFE000",X"DADA","110",abus_address,abus_data_in,abus_chipselect,abus_write); --data buf
abus_write_proc("11"&X"FFE002",X"DADA","110",abus_address,abus_data_in,abus_chipselect,abus_write); --data buf
abus_write_proc("11"&X"FFE7FC",X"DADA","110",abus_address,abus_data_in,abus_chipselect,abus_write); --data buf
abus_write_proc("11"&X"FFE7FE",X"DADA","110",abus_address,abus_data_in,abus_chipselect,abus_write); --data buf
abus_write_proc("11"&X"FFE800",X"CDCD","110",abus_address,abus_data_in,abus_chipselect,abus_write); --data buf
abus_write_proc("11"&X"FFE802",X"CDCD","110",abus_address,abus_data_in,abus_chipselect,abus_write); --data buf
abus_write_proc("11"&X"FFEFEC",X"CDCD","110",abus_address,abus_data_in,abus_chipselect,abus_write); --data buf
abus_write_proc("11"&X"FFEFEE",X"CDCD","110",abus_address,abus_data_in,abus_chipselect,abus_write); --data buf
abus_read_proc("11"&X"FFF000","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFF002","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFF7FC","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFF7FE","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFF800","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFF802","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFFFEC","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFFFEE","110",abus_address,abus_chipselect,abus_read);
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:46:37 02/13/2017
-- Design Name:
-- Module Name: C:/Xilinx/__testbecher/testbencher/a_tb.vhd
-- Project Name: testbencher
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ABus2AXI4Lite
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY a_tb IS
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Master Bus Interface M00_AXI
C_MASTER_AXI_TARGET_SLAVE_BASE_ADDR : std_logic_vector := x"00000000";
C_MASTER_AXI_ADDR_WIDTH : integer := 32;
C_MASTER_AXI_DATA_WIDTH : integer := 32;
C_SLAVE_AXI_ADDR_WIDTH : integer := 32;
C_SLAVE_AXI_DATA_WIDTH : integer := 32;
C_FILESYS_AXI_ADDR_WIDTH : integer := 32;
C_FILESYS_AXI_DATA_WIDTH : integer := 32
);
END a_tb;
ARCHITECTURE behavior OF a_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ABus2AXI4Lite
PORT(
-- abus ports
abus_address : in std_logic_vector(25 downto 0) := (others => '0'); -- abus.address
abus_data_in : in std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_data_out : out std_logic_vector(15 downto 0) := (others => '0'); -- abus.addressdata
abus_data_direction : out std_logic := '0'; -- .direction
abus_chipselect : in std_logic_vector(2 downto 0) := (others => '0'); -- .chipselect
abus_read : in std_logic := '0'; -- .read
abus_write : in std_logic_vector(1 downto 0) := (others => '0'); -- .write
abus_wait : out std_logic := '1'; -- .waitrequest
abus_wait_direction : out std_logic := '0'; -- .direction
abus_irq : out std_logic := '0'; -- .interrupt
abus_irq_direction : out std_logic := '0'; -- .direction
abus_reset : in std_logic := '0'; -- .saturn_reset
-- Ports of Axi Master Bus Interface
master_axi_aclk : in std_logic;
master_axi_aresetn : in std_logic;
master_axi_awaddr : out std_logic_vector(C_MASTER_AXI_ADDR_WIDTH-1 downto 0);
master_axi_awprot : out std_logic_vector(2 downto 0);
master_axi_awvalid : out std_logic;
master_axi_awready : in std_logic;
master_axi_wdata : out std_logic_vector(C_MASTER_AXI_DATA_WIDTH-1 downto 0);
master_axi_wstrb : out std_logic_vector(C_MASTER_AXI_DATA_WIDTH/8-1 downto 0);
master_axi_wvalid : out std_logic;
master_axi_wready : in std_logic;
master_axi_bresp : in std_logic_vector(1 downto 0);
master_axi_bvalid : in std_logic;
master_axi_bready : out std_logic;
master_axi_araddr : out std_logic_vector(C_MASTER_AXI_ADDR_WIDTH-1 downto 0);
master_axi_arprot : out std_logic_vector(2 downto 0);
master_axi_arvalid : out std_logic;
master_axi_arready : in std_logic;
master_axi_rdata : in std_logic_vector(C_MASTER_AXI_DATA_WIDTH-1 downto 0);
master_axi_rresp : in std_logic_vector(1 downto 0);
master_axi_rvalid : in std_logic;
master_axi_rready : out std_logic;
-- Ports of Slave Bus Interface
slave_axi_aclk : in std_logic;
slave_axi_aresetn : in std_logic;
slave_axi_awaddr : in std_logic_vector(C_SLAVE_AXI_ADDR_WIDTH-1 downto 0);
slave_axi_awprot : in std_logic_vector(2 downto 0);
slave_axi_awvalid : in std_logic;
slave_axi_awready : out std_logic;
slave_axi_wdata : in std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
slave_axi_wstrb : in std_logic_vector(C_SLAVE_AXI_DATA_WIDTH/8-1 downto 0);
slave_axi_wvalid : in std_logic;
slave_axi_wready : out std_logic;
slave_axi_bresp : out std_logic_vector(1 downto 0);
slave_axi_bvalid : out std_logic;
slave_axi_bready : in std_logic;
slave_axi_araddr : in std_logic_vector(C_SLAVE_AXI_ADDR_WIDTH-1 downto 0);
slave_axi_arprot : in std_logic_vector(2 downto 0);
slave_axi_arvalid : in std_logic;
slave_axi_arready : out std_logic;
slave_axi_rdata : out std_logic_vector(C_SLAVE_AXI_DATA_WIDTH-1 downto 0);
slave_axi_rresp : out std_logic_vector(1 downto 0);
slave_axi_rvalid : out std_logic;
slave_axi_rready : in std_logic
);
END COMPONENT;
COMPONENT test_mem
PORT(
s_aclk : IN std_logic;
s_aresetn : IN std_logic;
s_axi_awaddr : in std_logic_vector(31 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(31 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic
);
END COMPONENT;
--Inputs
signal abus_address : std_logic_vector(25 downto 0) := (others => '0');
signal abus_data_in : std_logic_vector(15 downto 0) := (others => '0');
signal abus_chipselect : std_logic_vector(2 downto 0) := (others => '0');
signal abus_read : std_logic := '0';
signal abus_write : std_logic_vector(1 downto 0) := (others => '0');
signal abus_reset : std_logic := '0';
signal master_axi_init_axi_txn : std_logic := '0';
signal master_axi_aclk : std_logic := '0';
signal master_axi_aresetn : std_logic := '0';
signal master_axi_awready : std_logic := '0';
signal master_axi_wready : std_logic := '0';
signal master_axi_bresp : std_logic_vector(1 downto 0) := (others => '0');
signal master_axi_bvalid : std_logic := '0';
signal master_axi_arready : std_logic := '0';
signal master_axi_rdata : std_logic_vector(31 downto 0) := (others => '0');
signal master_axi_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal master_axi_rvalid : std_logic := '0';
signal slave_axi_awaddr : std_logic_vector(31 downto 0) := (others => '0');
signal slave_axi_awprot : std_logic_vector(2 downto 0) := (others => '0');
signal slave_axi_awvalid : std_logic := '0';
signal slave_axi_wdata : std_logic_vector(31 downto 0) := (others => '0');
signal slave_axi_wstrb : std_logic_vector(3 downto 0) := (others => '0');
signal slave_axi_wvalid : std_logic := '0';
signal slave_axi_bready : std_logic := '0';
signal slave_axi_araddr : std_logic_vector(31 downto 0) := (others => '0');
signal slave_axi_arprot : std_logic_vector(2 downto 0) := (others => '0');
signal slave_axi_arvalid : std_logic := '0';
signal slave_axi_rready : std_logic := '0';
--Outputs
signal abus_data_out : std_logic_vector(15 downto 0);
signal abus_data_direction : std_logic := '0';
signal abus_wait : std_logic := '0';
signal abus_wait_direction : std_logic := '0';
signal abus_irq : std_logic := '0';
signal abus_irq_direction : std_logic := '0';
signal master_axi_error : std_logic := '0';
signal master_axi_txn_done : std_logic := '0';
signal master_axi_awaddr : std_logic_vector(31 downto 0) := (others => '0');
signal master_axi_awprot : std_logic_vector(2 downto 0) := (others => '0');
signal master_axi_awvalid : std_logic := '0';
signal master_axi_wdata : std_logic_vector(31 downto 0) := (others => '0');
signal master_axi_wstrb : std_logic_vector(3 downto 0) := (others => '0');
signal master_axi_wvalid : std_logic := '0';
signal master_axi_bready : std_logic := '0';
signal master_axi_araddr : std_logic_vector(31 downto 0) := (others => '0');
signal master_axi_arprot : std_logic_vector(2 downto 0) := (others => '0');
signal master_axi_arvalid : std_logic := '0';
signal master_axi_rready : std_logic := '0';
signal slave_axi_aclk : std_logic := '0';
signal slave_axi_aresetn : std_logic := '0';
signal slave_axi_awready : std_logic := '0';
signal slave_axi_wready : std_logic := '0';
signal slave_axi_bresp : std_logic_vector(1 downto 0) := (others => '0');
signal slave_axi_bvalid : std_logic := '0';
signal slave_axi_arready : std_logic := '0';
signal slave_axi_rdata : std_logic_vector(31 downto 0) := (others => '0');
signal slave_axi_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal slave_axi_rvalid : std_logic := '0';
-- Clock period definitions
constant master_axi_aclk_period : time := 10 ns;
procedure abus_write_proc (addr : in std_logic_vector(25 downto 0);
data : in std_logic_vector(15 downto 0);
chipselect : in std_logic_vector(2 downto 0);
signal ABus_Ad : out std_logic_vector(25 downto 0);
signal ABus_Da : out std_logic_vector(15 downto 0);
signal ABus_CS : out std_logic_vector(2 downto 0);
signal ABus_Wr : out std_logic_vector(1 downto 0)
) is
begin
--set quantizer 25mhz
ABus_Ad <= addr;
ABus_Da <= data;
wait for 100ns;
ABus_CS <= chipselect;
wait for 100ns;
ABus_Wr <= "00";
wait for 1000ns;
ABus_Wr <= "11";
wait for 100ns;
ABus_CS <= "111";
ABus_Da <= (others => 'Z');
wait for 100ns;
end abus_write_proc;
procedure abus_read_proc (addr : in std_logic_vector(25 downto 0);
chipselect : in std_logic_vector(2 downto 0);
signal ABus_Ad : out std_logic_vector(25 downto 0);
signal ABus_CS : out std_logic_vector(2 downto 0);
signal ABus_Re : out std_logic
) is
begin
--set quantizer 25mhz
ABus_Ad <= addr;
wait for 100ns;
ABus_CS <= chipselect;
wait for 100ns;
ABus_Re <= '0';
wait for 1000ns;
ABus_Re <= '1';
wait for 100ns;
ABus_CS <= "111";
wait for 100ns;
end abus_read_proc;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ABus2AXI4Lite PORT MAP (
abus_address => abus_address,
abus_data_in => abus_data_in,
abus_data_out => abus_data_out,
abus_data_direction => abus_data_direction,
abus_chipselect => abus_chipselect,
abus_read => abus_read,
abus_write => abus_write,
abus_wait => abus_wait,
abus_wait_direction => abus_wait_direction,
abus_irq => abus_irq,
abus_irq_direction => abus_irq_direction,
abus_reset => abus_reset,
master_axi_aclk => master_axi_aclk,
master_axi_aresetn => master_axi_aresetn,
master_axi_awaddr => master_axi_awaddr,
master_axi_awprot => master_axi_awprot,
master_axi_awvalid => master_axi_awvalid,
master_axi_awready => master_axi_awready,
master_axi_wdata => master_axi_wdata,
master_axi_wstrb => master_axi_wstrb,
master_axi_wvalid => master_axi_wvalid,
master_axi_wready => master_axi_wready,
master_axi_bresp => master_axi_bresp,
master_axi_bvalid => master_axi_bvalid,
master_axi_bready => master_axi_bready,
master_axi_araddr => master_axi_araddr,
master_axi_arprot => master_axi_arprot,
master_axi_arvalid => master_axi_arvalid,
master_axi_arready => master_axi_arready,
master_axi_rdata => master_axi_rdata,
master_axi_rresp => master_axi_rresp,
master_axi_rvalid => master_axi_rvalid,
master_axi_rready => master_axi_rready,
slave_axi_aclk => slave_axi_aclk,
slave_axi_aresetn => slave_axi_aresetn,
slave_axi_awaddr => slave_axi_awaddr,
slave_axi_awprot => slave_axi_awprot,
slave_axi_awvalid => slave_axi_awvalid,
slave_axi_awready => slave_axi_awready,
slave_axi_wdata => slave_axi_wdata,
slave_axi_wstrb => slave_axi_wstrb,
slave_axi_wvalid => slave_axi_wvalid,
slave_axi_wready => slave_axi_wready,
slave_axi_bresp => slave_axi_bresp,
slave_axi_bvalid => slave_axi_bvalid,
slave_axi_bready => slave_axi_bready,
slave_axi_araddr => slave_axi_araddr,
slave_axi_arprot => slave_axi_arprot,
slave_axi_arvalid => slave_axi_arvalid,
slave_axi_arready => slave_axi_arready,
slave_axi_rdata => slave_axi_rdata,
slave_axi_rresp => slave_axi_rresp,
slave_axi_rvalid => slave_axi_rvalid,
slave_axi_rready => slave_axi_rready
);
das_mem: test_mem PORT MAP (
s_aclk => master_axi_aclk,
s_aresetn => master_axi_aresetn,
s_axi_awaddr => master_axi_awaddr,
s_axi_awvalid => master_axi_awvalid,
s_axi_awready => master_axi_awready,
s_axi_wdata => master_axi_wdata,
s_axi_wstrb => master_axi_wstrb,
s_axi_wvalid => master_axi_wvalid,
s_axi_wready => master_axi_wready,
s_axi_bresp => master_axi_bresp,
s_axi_bvalid => master_axi_bvalid,
s_axi_bready => master_axi_bready,
s_axi_araddr => master_axi_araddr,
s_axi_arvalid => master_axi_arvalid,
s_axi_arready => master_axi_arready,
s_axi_rdata => master_axi_rdata,
s_axi_rresp => master_axi_rresp,
s_axi_rvalid => master_axi_rvalid,
s_axi_rready => master_axi_rready
);
-- Clock process definitions
master_axi_aclk_process :process
begin
master_axi_aclk <= '0';
wait for master_axi_aclk_period/2;
master_axi_aclk <= '1';
wait for master_axi_aclk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
abus_write <= "11";
abus_read <= '1';
abus_chipselect <= "111";
master_axi_aresetn <= '0';
-- hold reset state for 100 ns.
wait for 100 ns;
wait for master_axi_aclk_period*10;
master_axi_aresetn <= '1';
-- insert stimulus here
--abus read transaction
wait for 1000 ns;
abus_write_proc("00"&X"000000",X"FADE","101",abus_address,abus_data_in,abus_chipselect,abus_write);
abus_write_proc("00"&X"000002",X"1193","101",abus_address,abus_data_in,abus_chipselect,abus_write);
abus_write_proc("00"&X"000004",X"0003","101",abus_address,abus_data_in,abus_chipselect,abus_write);
abus_write_proc("00"&X"000006",X"FACE","101",abus_address,abus_data_in,abus_chipselect,abus_write);
abus_read_proc("00"&X"000000","101",abus_address,abus_chipselect,abus_read);
abus_read_proc("00"&X"000002","101",abus_address,abus_chipselect,abus_read);
abus_read_proc("00"&X"000004","101",abus_address,abus_chipselect,abus_read);
abus_read_proc("00"&X"000006","101",abus_address,abus_chipselect,abus_read);
--wasca system regs write and read
wait for 1000 ns;
abus_write_proc("11"&X"FFFFF4",X"ACBD","110",abus_address,abus_data_in,abus_chipselect,abus_write); --mode
abus_read_proc("11"&X"FFFFF0","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFFFF2","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFFFF4","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFFFF8","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFFFFA","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFFFFC","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFFFFE","110",abus_address,abus_chipselect,abus_read);
--wasca filesystem regs write and read
wait for 1000 ns;
abus_write_proc("11"&X"FFEFF0",X"FADE","110",abus_address,abus_data_in,abus_chipselect,abus_write); --lock
abus_write_proc("11"&X"FFEFF2",X"0001","110",abus_address,abus_data_in,abus_chipselect,abus_write); --cmd
abus_read_proc("11"&X"FFFFF4","110",abus_address,abus_chipselect,abus_read);--status
abus_write_proc("11"&X"FFE000",X"DADA","110",abus_address,abus_data_in,abus_chipselect,abus_write); --data buf
abus_write_proc("11"&X"FFE002",X"DADA","110",abus_address,abus_data_in,abus_chipselect,abus_write); --data buf
abus_write_proc("11"&X"FFE7FC",X"DADA","110",abus_address,abus_data_in,abus_chipselect,abus_write); --data buf
abus_write_proc("11"&X"FFE7FE",X"DADA","110",abus_address,abus_data_in,abus_chipselect,abus_write); --data buf
abus_write_proc("11"&X"FFE800",X"CDCD","110",abus_address,abus_data_in,abus_chipselect,abus_write); --data buf
abus_write_proc("11"&X"FFE802",X"CDCD","110",abus_address,abus_data_in,abus_chipselect,abus_write); --data buf
abus_write_proc("11"&X"FFEFEC",X"CDCD","110",abus_address,abus_data_in,abus_chipselect,abus_write); --data buf
abus_write_proc("11"&X"FFEFEE",X"CDCD","110",abus_address,abus_data_in,abus_chipselect,abus_write); --data buf
abus_read_proc("11"&X"FFF000","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFF002","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFF7FC","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFF7FE","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFF800","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFF802","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFFFEC","110",abus_address,abus_chipselect,abus_read);
abus_read_proc("11"&X"FFFFEE","110",abus_address,abus_chipselect,abus_read);
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Designer: Paolo Fulgoni <[email protected]>
--
-- Create Date: 09/14/2007
-- Last Update: 04/14/2008
-- Project Name: camellia-vhdl
-- Description: Dual-port SBOX4
--
-- Copyright (C) 2007 Paolo Fulgoni
-- This file is part of camellia-vhdl.
-- camellia-vhdl is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
-- camellia-vhdl is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- The Camellia cipher algorithm is 128 bit cipher developed by NTT and
-- Mitsubishi Electric researchers.
-- http://info.isl.ntt.co.jp/crypt/eng/camellia/
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity SBOX4 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
);
end SBOX4;
architecture RTL of SBOX4 is
component SBOX1 is
port (
clk : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(0 to 7);
addrb : IN STD_LOGIC_VECTOR(0 to 7);
douta : OUT STD_LOGIC_VECTOR(0 to 7);
doutb : OUT STD_LOGIC_VECTOR(0 to 7)
);
end component;
-- SBOX1 signals
signal s1_addra : STD_LOGIC_VECTOR(0 to 7);
signal s1_addrb : STD_LOGIC_VECTOR(0 to 7);
signal s1_clk : STD_LOGIC;
signal s1_douta : STD_LOGIC_VECTOR(0 to 7);
signal s1_doutb : STD_LOGIC_VECTOR(0 to 7);
begin
S1 : SBOX1
port map(s1_clk, s1_addra, s1_addrb, s1_douta, s1_doutb);
s1_clk <= clk;
s1_addra <= addra(1 to 7) & addra(0);
s1_addrb <= addrb(1 to 7) & addrb(0);
douta <= s1_douta;
doutb <= s1_doutb;
end RTL;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_bram_ctrl_v4_0_11;
USE axi_bram_ctrl_v4_0_11.axi_bram_ctrl;
ENTITY zynq_design_1_axi_bram_ctrl_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END zynq_design_1_axi_bram_ctrl_0_0;
ARCHITECTURE zynq_design_1_axi_bram_ctrl_0_0_arch OF zynq_design_1_axi_bram_ctrl_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zynq_design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_bram_ctrl IS
GENERIC (
C_BRAM_INST_MODE : STRING;
C_MEMORY_DEPTH : INTEGER;
C_BRAM_ADDR_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_ID_WIDTH : INTEGER;
C_S_AXI_PROTOCOL : STRING;
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER;
C_SINGLE_PORT_BRAM : INTEGER;
C_FAMILY : STRING;
C_SELECT_XPM : INTEGER;
C_S_AXI_CTRL_ADDR_WIDTH : INTEGER;
C_S_AXI_CTRL_DATA_WIDTH : INTEGER;
C_ECC : INTEGER;
C_ECC_TYPE : INTEGER;
C_FAULT_INJECT : INTEGER;
C_ECC_ONOFF_RESET_VALUE : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
ecc_interrupt : OUT STD_LOGIC;
ecc_ue : OUT STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC;
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC;
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_ctrl_awvalid : IN STD_LOGIC;
s_axi_ctrl_awready : OUT STD_LOGIC;
s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_wvalid : IN STD_LOGIC;
s_axi_ctrl_wready : OUT STD_LOGIC;
s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_bvalid : OUT STD_LOGIC;
s_axi_ctrl_bready : IN STD_LOGIC;
s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_arvalid : IN STD_LOGIC;
s_axi_ctrl_arready : OUT STD_LOGIC;
s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_ctrl_rvalid : OUT STD_LOGIC;
s_axi_ctrl_rready : IN STD_LOGIC;
bram_rst_a : OUT STD_LOGIC;
bram_clk_a : OUT STD_LOGIC;
bram_en_a : OUT STD_LOGIC;
bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_a : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rst_b : OUT STD_LOGIC;
bram_clk_b : OUT STD_LOGIC;
bram_en_b : OUT STD_LOGIC;
bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
bram_addr_b : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_bram_ctrl;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF zynq_design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "axi_bram_ctrl,Vivado 2017.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF zynq_design_1_axi_bram_ctrl_0_0_arch : ARCHITECTURE IS "zynq_design_1_axi_bram_ctrl_0_0,axi_bram_ctrl,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF zynq_design_1_axi_bram_ctrl_0_0_arch: ARCHITECTURE IS "zynq_design_1_axi_bram_ctrl_0_0,axi_bram_ctrl,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_bram_ctrl,x_ipVersion=4.0,x_ipCoreRevision=11,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_BRAM_INST_MODE=EXTERNAL,C_MEMORY_DEPTH=16384,C_BRAM_ADDR_WIDTH=14,C_S_AXI_ADDR_WIDTH=16,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=12,C_S_AXI_PROTOCOL=AXI4,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_SINGLE_PORT_BRAM=0,C_FAMILY=zynq,C_SELECT_XPM=0,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=3" &
"2,C_ECC=0,C_ECC_TYPE=0,C_FAULT_INJECT=0,C_ECC_ONOFF_RESET_VALUE=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF bram_rst_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
ATTRIBUTE X_INTERFACE_INFO OF bram_clk_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF bram_en_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF bram_we_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF bram_addr_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_b: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : axi_bram_ctrl
GENERIC MAP (
C_BRAM_INST_MODE => "EXTERNAL",
C_MEMORY_DEPTH => 16384,
C_BRAM_ADDR_WIDTH => 14,
C_S_AXI_ADDR_WIDTH => 16,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_ID_WIDTH => 12,
C_S_AXI_PROTOCOL => "AXI4",
C_S_AXI_SUPPORTS_NARROW_BURST => 0,
C_SINGLE_PORT_BRAM => 0,
C_FAMILY => "zynq",
C_SELECT_XPM => 0,
C_S_AXI_CTRL_ADDR_WIDTH => 32,
C_S_AXI_CTRL_DATA_WIDTH => 32,
C_ECC => 0,
C_ECC_TYPE => 0,
C_FAULT_INJECT => 0,
C_ECC_ONOFF_RESET_VALUE => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awid => s_axi_awid,
s_axi_awaddr => s_axi_awaddr,
s_axi_awlen => s_axi_awlen,
s_axi_awsize => s_axi_awsize,
s_axi_awburst => s_axi_awburst,
s_axi_awlock => s_axi_awlock,
s_axi_awcache => s_axi_awcache,
s_axi_awprot => s_axi_awprot,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
s_axi_araddr => s_axi_araddr,
s_axi_arlen => s_axi_arlen,
s_axi_arsize => s_axi_arsize,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
s_axi_arcache => s_axi_arcache,
s_axi_arprot => s_axi_arprot,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_wvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_rready => '0',
bram_rst_a => bram_rst_a,
bram_clk_a => bram_clk_a,
bram_en_a => bram_en_a,
bram_we_a => bram_we_a,
bram_addr_a => bram_addr_a,
bram_wrdata_a => bram_wrdata_a,
bram_rddata_a => bram_rddata_a,
bram_rst_b => bram_rst_b,
bram_clk_b => bram_clk_b,
bram_en_b => bram_en_b,
bram_we_b => bram_we_b,
bram_addr_b => bram_addr_b,
bram_wrdata_b => bram_wrdata_b,
bram_rddata_b => bram_rddata_b
);
END zynq_design_1_axi_bram_ctrl_0_0_arch;
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Technology specific dual-port RAM.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library techmap;
use techmap.gencomp.all;
use techmap.types_mem.all;
entity syncram_2p_tech is
generic (
tech : integer := 0;
abits : integer := 6;
dbits : integer := 8;
sepclk : integer := 0;
wrfst : integer := 0;
testen : integer := 0;
words : integer := 0;
custombits : integer := 1
);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0)
);
end;
architecture rtl of syncram_2p_tech is
component syncram_2p_inferred is
generic (
abits : integer := 8;
dbits : integer := 32;
sepclk: integer := 0
);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end component;
begin
inf : if tech = inferred generate
x0 : syncram_2p_inferred generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, write, dataout);
end generate;
xilinx6 : if tech = virtex6 or tech = kintex7 or tech = artix7 generate
x0 : syncram_2p_inferred generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, write, dataout);
end generate;
end;
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Technology specific dual-port RAM.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library techmap;
use techmap.gencomp.all;
use techmap.types_mem.all;
entity syncram_2p_tech is
generic (
tech : integer := 0;
abits : integer := 6;
dbits : integer := 8;
sepclk : integer := 0;
wrfst : integer := 0;
testen : integer := 0;
words : integer := 0;
custombits : integer := 1
);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0)
);
end;
architecture rtl of syncram_2p_tech is
component syncram_2p_inferred is
generic (
abits : integer := 8;
dbits : integer := 32;
sepclk: integer := 0
);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end component;
begin
inf : if tech = inferred generate
x0 : syncram_2p_inferred generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, write, dataout);
end generate;
xilinx6 : if tech = virtex6 or tech = kintex7 or tech = artix7 generate
x0 : syncram_2p_inferred generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, write, dataout);
end generate;
end;
|
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
|
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
|
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
|
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
|
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
|
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := CONFIG_MCTRL_LEON2;
constant CFG_MCTRL_RAM8BIT : integer := CONFIG_MCTRL_8BIT;
constant CFG_MCTRL_RAM16BIT : integer := CONFIG_MCTRL_16BIT;
constant CFG_MCTRL_5CS : integer := CONFIG_MCTRL_5CS;
constant CFG_MCTRL_SDEN : integer := CONFIG_MCTRL_SDRAM;
constant CFG_MCTRL_SEPBUS : integer := CONFIG_MCTRL_SDRAM_SEPBUS;
constant CFG_MCTRL_INVCLK : integer := CONFIG_MCTRL_SDRAM_INVCLK;
constant CFG_MCTRL_SD64 : integer := CONFIG_MCTRL_SDRAM_BUS64;
constant CFG_MCTRL_PAGE : integer := CONFIG_MCTRL_PAGE + CONFIG_MCTRL_PROGPAGE;
|
----------------------------------------------------------------------------------
--MIPS Register File Test Bench
--By: Kevin Mottler
--Camel Clarkson 32 Bit MIPS Design Group
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Decoder is
Port (
i_w_Addr : in std_logic_vector(4 downto 0);
o_w_Addr : out std_logic_vector(31 downto 0)
);
end Decoder;
architecture Behavioral of Decoder is
begin
process(i_w_Addr)
begin
case i_w_Addr is
when "00000" =>
o_w_Addr <= "00000000000000000000000000000001";
when "00001" =>
o_w_Addr <= "00000000000000000000000000000010";
when "00010" =>
o_w_Addr <= "00000000000000000000000000000100";
when "00011" =>
o_w_Addr <= "00000000000000000000000000001000";
when "00100" =>
o_w_Addr <= "00000000000000000000000000010000";
when "00101" =>
o_w_Addr <= "00000000000000000000000000100000";
when "00110" =>
o_w_Addr <= "00000000000000000000000001000000";
when "00111" =>
o_w_Addr <= "00000000000000000000000010000000";
when "01000" =>
o_w_Addr <= "00000000000000000000000100000000";
when "01001" =>
o_w_Addr <= "00000000000000000000001000000000";
when "01010" =>
o_w_Addr <= "00000000000000000000010000000000";
when "01011" =>
o_w_Addr <= "00000000000000000000100000000000";
when "01100" =>
o_w_Addr <= "00000000000000000001000000000000";
when "01101" =>
o_w_Addr <= "00000000000000000010000000000000";
when "01110" =>
o_w_Addr <= "00000000000000000100000000000000";
when "01111" =>
o_w_Addr <= "00000000000000001000000000000000";
when "10000" =>
o_w_Addr <= "00000000000000010000000000000000";
when "10001" =>
o_w_Addr <= "00000000000000100000000000000000";
when "10010" =>
o_w_Addr <= "00000000000001000000000000000000";
when "10011" =>
o_w_Addr <= "00000000000010000000000000000000";
when "10100" =>
o_w_Addr <= "00000000000100000000000000000000";
when "10101" =>
o_w_Addr <= "00000000001000000000000000000000";
when "10110" =>
o_w_Addr <= "00000000010000000000000000000000";
when "10111" =>
o_w_Addr <= "00000000100000000000000000000000";
when "11000" =>
o_w_Addr <= "00000001000000000000000000000000";
when "11001" =>
o_w_Addr <= "00000010000000000000000000000000";
when "11010" =>
o_w_Addr <= "00000100000000000000000000000000";
when "11011" =>
o_w_Addr <= "00001000000000000000000000000000";
when "11100" =>
o_w_Addr <= "00010000000000000000000000000000";
when "11101" =>
o_w_Addr <= "00100000000000000000000000000000";
when "11110" =>
o_w_Addr <= "01000000000000000000000000000000";
when "11111" =>
o_w_Addr <= "10000000000000000000000000000000";
when others =>
o_w_Addr <= "00000000000000000000000000000000";
end case;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rec06_pkg.all;
entity rec06 is
port (inp : std_logic;
o : out myrec);
end rec06;
architecture behav of rec06 is
begin
o.b <= not inp;
o.a.c <= 2 when inp = '1' else 3;
o.a.d <= "0000" when inp = '0' else "1000";
end behav;
|
-- This file is part of the ethernet_mac_test project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity clock_generator is
port(
reset_i : in std_ulogic;
clock_125_i : in std_ulogic;
clock_125_o : out std_ulogic;
clock_125_inv_o : out std_ulogic;
clock_125_unbuffered_o : out std_ulogic;
clock_50_o : out std_ulogic;
locked_o : out std_ulogic
);
end entity;
architecture spartan of clock_generator is
signal int_clock_125 : std_ulogic;
signal int_clock_125_buffered : std_ulogic;
signal int_clock_125_inv : std_ulogic;
signal int_clock_50 : std_ulogic;
signal clock_feedback : std_ulogic;
begin
clock_125_unbuffered_o <= int_clock_125;
clock_125_o <= int_clock_125_buffered;
BUFIO2FB_inst : BUFIO2FB
generic map(
DIVIDE_BYPASS => TRUE -- Bypass divider (TRUE/FALSE)
)
port map(
O => clock_feedback, -- 1-bit output: Output feedback clock (connect to feedback input of DCM/PLL)
I => int_clock_125_buffered -- 1-bit input: Feedback clock input (connect to input port)
);
clock_125_BUFG_inst : BUFG
port map(
O => int_clock_125_buffered, -- 1-bit output: Clock buffer output
I => int_clock_125 -- 1-bit input: Clock buffer input
);
clock_125_inv_BUFG_inst : BUFG
port map(
O => clock_125_inv_o, -- 1-bit output: Clock buffer output
I => int_clock_125_inv -- 1-bit input: Clock buffer input
);
clock_50_BUFG_inst : BUFG
port map(
O => clock_50_o,
I => int_clock_50
);
-- TODO Remove BUFIO2FB
DCM_SP_inst : DCM_SP
generic map(
CLKDV_DIVIDE => 5.0, -- CLKDV divide value
-- (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).
CLKFX_DIVIDE => 5, -- Divide value on CLKFX outputs - D - (1-32)
CLKFX_MULTIPLY => 2, -- Multiply value on CLKFX outputs - M - (2-32)
CLKIN_DIVIDE_BY_2 => FALSE, -- CLKIN divide by two (TRUE/FALSE)
CLKIN_PERIOD => 8.0, -- Input clock period specified in nS
CLKOUT_PHASE_SHIFT => "NONE", -- Output phase shift (NONE, FIXED, VARIABLE)
CLK_FEEDBACK => "1X", -- Feedback source (NONE, 1X, 2X)
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
DFS_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
DLL_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
DSS_MODE => "NONE", -- Unsupported - Do not change value
DUTY_CYCLE_CORRECTION => TRUE, -- Unsupported - Do not change value
FACTORY_JF => X"c080", -- Unsupported - Do not change value
PHASE_SHIFT => 0, -- Amount of fixed phase shift (-255 to 255)
STARTUP_WAIT => FALSE -- Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)
)
port map(
CLK0 => int_clock_125, -- 1-bit output: 0 degree clock output
CLK180 => int_clock_125_inv, -- 1-bit output: 180 degree clock output
CLK270 => open, -- 1-bit output: 270 degree clock output
CLK2X => open, -- 1-bit output: 2X clock frequency clock output
CLK2X180 => open, -- 1-bit output: 2X clock frequency, 180 degree clock output
CLK90 => open, -- 1-bit output: 90 degree clock output
CLKDV => open, -- 1-bit output: Divided clock output
CLKFX => int_clock_50, -- 1-bit output: Digital Frequency Synthesizer output (DFS)
CLKFX180 => open, -- 1-bit output: 180 degree CLKFX output
LOCKED => locked_o, -- 1-bit output: DCM_SP Lock Output
PSDONE => open, -- 1-bit output: Phase shift done output
STATUS => open, -- 8-bit output: DCM_SP status output
CLKFB => clock_feedback, -- 1-bit input: Clock feedback input
CLKIN => clock_125_i, -- 1-bit input: Clock input
DSSEN => '0', -- 1-bit input: Unsupported, specify to GND.
PSCLK => '0', -- 1-bit input: Phase shift clock input
PSEN => '0', -- 1-bit input: Phase shift enable
PSINCDEC => '0', -- 1-bit input: Phase shift increment/decrement input
RST => '0' -- 1-bit input: Active high reset input
);
end architecture; |
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
--
-- .. hwt-autodoc::
--
ENTITY IfStatementPartiallyEnclosed IS
PORT(
a : OUT STD_LOGIC;
b : OUT STD_LOGIC;
c : IN STD_LOGIC;
clk : IN STD_LOGIC;
d : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF IfStatementPartiallyEnclosed IS
SIGNAL a_reg : STD_LOGIC;
SIGNAL a_reg_next : STD_LOGIC;
SIGNAL b_reg : STD_LOGIC;
SIGNAL b_reg_next : STD_LOGIC;
BEGIN
a <= a_reg;
assig_process_a_reg_next: PROCESS(b_reg, c, d)
BEGIN
IF c = '1' THEN
a_reg_next <= '1';
b_reg_next <= '1';
ELSIF d = '1' THEN
a_reg_next <= '0';
b_reg_next <= b_reg;
ELSE
a_reg_next <= '1';
b_reg_next <= '1';
END IF;
END PROCESS;
b <= b_reg;
assig_process_b_reg: PROCESS(clk)
BEGIN
IF RISING_EDGE(clk) THEN
b_reg <= b_reg_next;
a_reg <= a_reg_next;
END IF;
END PROCESS;
END ARCHITECTURE;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex2;
constant CFG_MEMTECH : integer := virtex2;
constant CFG_PADTECH : integer := virtex2;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex2;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (4);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (2);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (4);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 1 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000004#;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 1;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SDRAM controller
constant CFG_SDCTRL : integer := 0;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- PCI interface
constant CFG_PCI : integer := 0;
constant CFG_PCIVID : integer := 16#0#;
constant CFG_PCIDID : integer := 16#0#;
constant CFG_PCIDEPTH : integer := 8;
constant CFG_PCI_MTF : integer := 1;
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
constant CFG_SDEN : integer := CFG_MCTRL_SDEN + CFG_SDCTRL;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK + CFG_SDCTRL_INVCLK;
constant CFG_SEPBUS : integer := CFG_MCTRL_SEPBUS + CFG_SDCTRL;
constant CFG_SD64 : integer := CFG_MCTRL_SD64 + CFG_SDCTRL_SD64;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FSqr is
port (
clk : in std_logic;
flt_in : in std_logic_vector(31 downto 0);
flt_out : out std_logic_vector(31 downto 0));
end FSqr;
architecture twoproc_pipeline of FSqr is
component FSqrTable is
port (
clk : in std_logic;
k : in std_logic_vector(9 downto 0);
v : out std_logic_vector(35 downto 0) := (others => '0'));
end component;
signal k : std_logic_vector(9 downto 0) := (others => '0');
signal v : std_logic_vector(35 downto 0);
signal rest : unsigned(13 downto 0) := (others => '0');
signal sgn_in, sgn_in_p : std_logic := '0';
signal exp_in, exp_in_p : unsigned(7 downto 0) := (others => '0');
signal a0, a0_p : unsigned(22 downto 0) := (others => '0');
signal t1, t1_p : unsigned(22 downto 0) := (others => '0');
begin
conbinatorial1 : process(flt_in)
begin
k <= flt_in(23 downto 14);
end process;
table_map : FSqrTable port map (clk => clk, k => k, v => v);
sequential2 : process(clk)
begin
if rising_edge(clk) then
sgn_in <= flt_in(31);
exp_in <= unsigned(flt_in(30 downto 23));
rest <= unsigned(flt_in(13 downto 0));
end if;
end process;
conbinatorial2 : process(v, rest)
variable a1 : unsigned(12 downto 0);
variable tmp : unsigned(26 downto 0);
begin
a0 <= unsigned(v(35 downto 13));
a1 := unsigned(v(12 downto 0));
tmp := a1 * rest;
t1 <= "000000000" & tmp(26 downto 13);
end process;
sequential3 : process(clk)
begin
if rising_edge(clk) then
sgn_in_p <= sgn_in;
exp_in_p <= exp_in;
a0_p <= a0;
t1_p <= t1;
end if;
end process;
conbinatorial3 : process(sgn_in_p, exp_in_p, a0_p, t1_p)
variable exp_out : unsigned(7 downto 0);
variable frc_out : unsigned(22 downto 0);
begin
if exp_in_p = x"00" then
exp_out := x"00";
frc_out := (others => '0');
elsif sgn_in_p = '1' then
exp_out := x"FF";
frc_out := x"00000" & "00" & '1';
else
exp_out := x"3F" + ("0" & exp_in_p(7 downto 1)) + unsigned'(0 => exp_in_p(0));
frc_out := a0_p + t1_p;
end if;
flt_out <= std_logic_vector(sgn_in_p & exp_out & frc_out);
end process;
end twoproc_pipeline;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_mm2s_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_sg Library Modules
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_reset;
use axi_sg_v4_1_2.axi_sg_cmd_status;
use axi_sg_v4_1_2.axi_sg_scc;
use axi_sg_v4_1_2.axi_sg_addr_cntl;
use axi_sg_v4_1_2.axi_sg_rddata_cntl;
use axi_sg_v4_1_2.axi_sg_rd_status_cntl;
use axi_sg_v4_1_2.axi_sg_skid_buf;
-------------------------------------------------------------------------------
entity axi_sg_mm2s_basic_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 16 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_ENABLE_MULTI_CHANNEL : Integer range 0 to 1 := 1;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock and Reset inputs -----------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
sg_ctl : in std_logic_vector (7 downto 0);
-- MM2S Halt request input control ---------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- Error discrete output -------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ----------
-- These are used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(1+C_ENABLE_MULTI_CHANNEL)*C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
-------------------------------------------------------------
-- Address Posting contols ----------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
-------------------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -----------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
-------------------------------------------------------------------
);
end entity axi_sg_mm2s_basic_wrap;
architecture implementation of axi_sg_mm2s_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
-- coverage off
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
-- coverage on
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := 2;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 256 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 256 := C_MM2S_SDATA_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (C_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := 1;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 64 := 1;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := 0;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 2;
Constant MM2S_BURST_SIZE : integer range 16 to 256 := 16;
Constant RD_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant DRE_ALIGN_ZEROS : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
-- obsoleted Constant DISABLE_WAIT_FOR_DATA : integer := 0;
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0);
signal sig_mm2s_cache_data : std_logic_vector(7 downto 0);
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_data2skid_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0) := (others => '0');
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug Support ------------------------------------------
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF2222" ; -- 32 bit Constant indicating MM2S Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_MULTI_CHANNEL = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_MULTI_CHANNEL = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= sg_ctl (3 downto 0); -- SG Cache from register
mm2s_aruser <= sg_ctl (7 downto 4); -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Cache signal tie-off
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_sg_v4_1_2.axi_sg_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_sg_v4_1_2.axi_sg_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_mm2s_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_sg_v4_1_2.axi_sg_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_sg_v4_1_2.axi_sg_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_sg_v4_1_2.axi_sg_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => DISABLE_WAIT_FOR_DATA ,
--C_ADDR_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_ADDR_FIFO_DEPTH => RD_ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => mm2s_allow_addr_req ,
addr_req_posted => mm2s_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_sg_v4_1_2.axi_sg_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_MM2S_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => open ,
mm2s_dre_use_autodest => open ,
mm2s_dre_src_align => open ,
mm2s_dre_dest_align => open ,
mm2s_dre_flush => open ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => mm2s_strm_wvalid ,
mm2s_strm_wready => mm2s_strm_wready ,
mm2s_strm_wdata => mm2s_strm_wdata ,
mm2s_strm_wstrb => mm2s_strm_wstrb ,
mm2s_strm_wlast => mm2s_strm_wlast ,
-- MM2S Store and Forward Supplimental Control -----------
mm2s_data2sf_cmd_cmplt => open ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => DRE_ALIGN_ZEROS ,
mstr2data_dre_dest_align => DRE_ALIGN_ZEROS ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
-- I_MM2S_SKID_BUF : entity axi_sg_v4_1_2.axi_sg_skid_buf
-- generic map (
--
-- C_WDATA_WIDTH => MM2S_SDATA_WIDTH
--
-- )
-- port map (
--
-- -- System Ports
-- aclk => mm2s_aclk ,
-- arst => sig_stream_rst ,
--
-- -- Shutdown control (assert for 1 clk pulse)
-- skid_stop => sig_data2skid_halt ,
--
-- -- Slave Side (Stream Data Input)
-- s_valid => sig_data2skid_wvalid ,
-- s_ready => sig_data2skid_wready ,
-- s_data => sig_data2skid_wdata ,
-- s_strb => sig_data2skid_wstrb ,
-- s_last => sig_data2skid_wlast ,
--
-- -- Master Side (Stream Data Output
-- m_valid => mm2s_strm_wvalid ,
-- m_ready => mm2s_strm_wready ,
-- m_data => mm2s_strm_wdata ,
-- m_strb => mm2s_strm_wstrb ,
-- m_last => mm2s_strm_wlast
--
-- );
--
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_mm2s_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_sg Library Modules
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_reset;
use axi_sg_v4_1_2.axi_sg_cmd_status;
use axi_sg_v4_1_2.axi_sg_scc;
use axi_sg_v4_1_2.axi_sg_addr_cntl;
use axi_sg_v4_1_2.axi_sg_rddata_cntl;
use axi_sg_v4_1_2.axi_sg_rd_status_cntl;
use axi_sg_v4_1_2.axi_sg_skid_buf;
-------------------------------------------------------------------------------
entity axi_sg_mm2s_basic_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 16 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_ENABLE_MULTI_CHANNEL : Integer range 0 to 1 := 1;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock and Reset inputs -----------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
sg_ctl : in std_logic_vector (7 downto 0);
-- MM2S Halt request input control ---------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- Error discrete output -------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ----------
-- These are used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(1+C_ENABLE_MULTI_CHANNEL)*C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
-------------------------------------------------------------
-- Address Posting contols ----------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
-------------------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -----------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
-------------------------------------------------------------------
);
end entity axi_sg_mm2s_basic_wrap;
architecture implementation of axi_sg_mm2s_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
-- coverage off
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
-- coverage on
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := 2;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 256 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 256 := C_MM2S_SDATA_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (C_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := 1;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 64 := 1;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := 0;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 2;
Constant MM2S_BURST_SIZE : integer range 16 to 256 := 16;
Constant RD_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant DRE_ALIGN_ZEROS : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
-- obsoleted Constant DISABLE_WAIT_FOR_DATA : integer := 0;
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0);
signal sig_mm2s_cache_data : std_logic_vector(7 downto 0);
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_data2skid_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0) := (others => '0');
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug Support ------------------------------------------
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF2222" ; -- 32 bit Constant indicating MM2S Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_MULTI_CHANNEL = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_MULTI_CHANNEL = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= sg_ctl (3 downto 0); -- SG Cache from register
mm2s_aruser <= sg_ctl (7 downto 4); -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Cache signal tie-off
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_sg_v4_1_2.axi_sg_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_sg_v4_1_2.axi_sg_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_mm2s_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_sg_v4_1_2.axi_sg_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_sg_v4_1_2.axi_sg_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_sg_v4_1_2.axi_sg_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => DISABLE_WAIT_FOR_DATA ,
--C_ADDR_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_ADDR_FIFO_DEPTH => RD_ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => mm2s_allow_addr_req ,
addr_req_posted => mm2s_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_sg_v4_1_2.axi_sg_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_MM2S_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => open ,
mm2s_dre_use_autodest => open ,
mm2s_dre_src_align => open ,
mm2s_dre_dest_align => open ,
mm2s_dre_flush => open ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => mm2s_strm_wvalid ,
mm2s_strm_wready => mm2s_strm_wready ,
mm2s_strm_wdata => mm2s_strm_wdata ,
mm2s_strm_wstrb => mm2s_strm_wstrb ,
mm2s_strm_wlast => mm2s_strm_wlast ,
-- MM2S Store and Forward Supplimental Control -----------
mm2s_data2sf_cmd_cmplt => open ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => DRE_ALIGN_ZEROS ,
mstr2data_dre_dest_align => DRE_ALIGN_ZEROS ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
-- I_MM2S_SKID_BUF : entity axi_sg_v4_1_2.axi_sg_skid_buf
-- generic map (
--
-- C_WDATA_WIDTH => MM2S_SDATA_WIDTH
--
-- )
-- port map (
--
-- -- System Ports
-- aclk => mm2s_aclk ,
-- arst => sig_stream_rst ,
--
-- -- Shutdown control (assert for 1 clk pulse)
-- skid_stop => sig_data2skid_halt ,
--
-- -- Slave Side (Stream Data Input)
-- s_valid => sig_data2skid_wvalid ,
-- s_ready => sig_data2skid_wready ,
-- s_data => sig_data2skid_wdata ,
-- s_strb => sig_data2skid_wstrb ,
-- s_last => sig_data2skid_wlast ,
--
-- -- Master Side (Stream Data Output
-- m_valid => mm2s_strm_wvalid ,
-- m_ready => mm2s_strm_wready ,
-- m_data => mm2s_strm_wdata ,
-- m_strb => mm2s_strm_wstrb ,
-- m_last => mm2s_strm_wlast
--
-- );
--
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_mm2s_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_sg Library Modules
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_reset;
use axi_sg_v4_1_2.axi_sg_cmd_status;
use axi_sg_v4_1_2.axi_sg_scc;
use axi_sg_v4_1_2.axi_sg_addr_cntl;
use axi_sg_v4_1_2.axi_sg_rddata_cntl;
use axi_sg_v4_1_2.axi_sg_rd_status_cntl;
use axi_sg_v4_1_2.axi_sg_skid_buf;
-------------------------------------------------------------------------------
entity axi_sg_mm2s_basic_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 16 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_ENABLE_MULTI_CHANNEL : Integer range 0 to 1 := 1;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock and Reset inputs -----------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
sg_ctl : in std_logic_vector (7 downto 0);
-- MM2S Halt request input control ---------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- Error discrete output -------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ----------
-- These are used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(1+C_ENABLE_MULTI_CHANNEL)*C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
-------------------------------------------------------------
-- Address Posting contols ----------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
-------------------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -----------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
-------------------------------------------------------------------
);
end entity axi_sg_mm2s_basic_wrap;
architecture implementation of axi_sg_mm2s_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
-- coverage off
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
-- coverage on
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := 2;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 256 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 256 := C_MM2S_SDATA_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (C_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := 1;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 64 := 1;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := 0;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 2;
Constant MM2S_BURST_SIZE : integer range 16 to 256 := 16;
Constant RD_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant DRE_ALIGN_ZEROS : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
-- obsoleted Constant DISABLE_WAIT_FOR_DATA : integer := 0;
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0);
signal sig_mm2s_cache_data : std_logic_vector(7 downto 0);
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_data2skid_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0) := (others => '0');
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug Support ------------------------------------------
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF2222" ; -- 32 bit Constant indicating MM2S Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_MULTI_CHANNEL = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_MULTI_CHANNEL = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= sg_ctl (3 downto 0); -- SG Cache from register
mm2s_aruser <= sg_ctl (7 downto 4); -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Cache signal tie-off
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_sg_v4_1_2.axi_sg_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_sg_v4_1_2.axi_sg_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_mm2s_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_sg_v4_1_2.axi_sg_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_sg_v4_1_2.axi_sg_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_sg_v4_1_2.axi_sg_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => DISABLE_WAIT_FOR_DATA ,
--C_ADDR_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_ADDR_FIFO_DEPTH => RD_ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => mm2s_allow_addr_req ,
addr_req_posted => mm2s_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_sg_v4_1_2.axi_sg_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_MM2S_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => open ,
mm2s_dre_use_autodest => open ,
mm2s_dre_src_align => open ,
mm2s_dre_dest_align => open ,
mm2s_dre_flush => open ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => mm2s_strm_wvalid ,
mm2s_strm_wready => mm2s_strm_wready ,
mm2s_strm_wdata => mm2s_strm_wdata ,
mm2s_strm_wstrb => mm2s_strm_wstrb ,
mm2s_strm_wlast => mm2s_strm_wlast ,
-- MM2S Store and Forward Supplimental Control -----------
mm2s_data2sf_cmd_cmplt => open ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => DRE_ALIGN_ZEROS ,
mstr2data_dre_dest_align => DRE_ALIGN_ZEROS ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
-- I_MM2S_SKID_BUF : entity axi_sg_v4_1_2.axi_sg_skid_buf
-- generic map (
--
-- C_WDATA_WIDTH => MM2S_SDATA_WIDTH
--
-- )
-- port map (
--
-- -- System Ports
-- aclk => mm2s_aclk ,
-- arst => sig_stream_rst ,
--
-- -- Shutdown control (assert for 1 clk pulse)
-- skid_stop => sig_data2skid_halt ,
--
-- -- Slave Side (Stream Data Input)
-- s_valid => sig_data2skid_wvalid ,
-- s_ready => sig_data2skid_wready ,
-- s_data => sig_data2skid_wdata ,
-- s_strb => sig_data2skid_wstrb ,
-- s_last => sig_data2skid_wlast ,
--
-- -- Master Side (Stream Data Output
-- m_valid => mm2s_strm_wvalid ,
-- m_ready => mm2s_strm_wready ,
-- m_data => mm2s_strm_wdata ,
-- m_strb => mm2s_strm_wstrb ,
-- m_last => mm2s_strm_wlast
--
-- );
--
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_mm2s_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_sg Library Modules
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_reset;
use axi_sg_v4_1_2.axi_sg_cmd_status;
use axi_sg_v4_1_2.axi_sg_scc;
use axi_sg_v4_1_2.axi_sg_addr_cntl;
use axi_sg_v4_1_2.axi_sg_rddata_cntl;
use axi_sg_v4_1_2.axi_sg_rd_status_cntl;
use axi_sg_v4_1_2.axi_sg_skid_buf;
-------------------------------------------------------------------------------
entity axi_sg_mm2s_basic_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 16 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_ENABLE_MULTI_CHANNEL : Integer range 0 to 1 := 1;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock and Reset inputs -----------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
sg_ctl : in std_logic_vector (7 downto 0);
-- MM2S Halt request input control ---------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- Error discrete output -------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ----------
-- These are used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(1+C_ENABLE_MULTI_CHANNEL)*C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
-------------------------------------------------------------
-- Address Posting contols ----------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
-------------------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -----------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
-------------------------------------------------------------------
);
end entity axi_sg_mm2s_basic_wrap;
architecture implementation of axi_sg_mm2s_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
-- coverage off
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
-- coverage on
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := 2;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 256 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 256 := C_MM2S_SDATA_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (C_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := 1;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 64 := 1;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := 0;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 2;
Constant MM2S_BURST_SIZE : integer range 16 to 256 := 16;
Constant RD_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant DRE_ALIGN_ZEROS : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
-- obsoleted Constant DISABLE_WAIT_FOR_DATA : integer := 0;
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0);
signal sig_mm2s_cache_data : std_logic_vector(7 downto 0);
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_data2skid_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0) := (others => '0');
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug Support ------------------------------------------
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF2222" ; -- 32 bit Constant indicating MM2S Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_MULTI_CHANNEL = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_MULTI_CHANNEL = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= sg_ctl (3 downto 0); -- SG Cache from register
mm2s_aruser <= sg_ctl (7 downto 4); -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Cache signal tie-off
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_sg_v4_1_2.axi_sg_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_sg_v4_1_2.axi_sg_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_mm2s_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_sg_v4_1_2.axi_sg_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_sg_v4_1_2.axi_sg_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_sg_v4_1_2.axi_sg_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => DISABLE_WAIT_FOR_DATA ,
--C_ADDR_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_ADDR_FIFO_DEPTH => RD_ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => mm2s_allow_addr_req ,
addr_req_posted => mm2s_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_sg_v4_1_2.axi_sg_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_MM2S_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => open ,
mm2s_dre_use_autodest => open ,
mm2s_dre_src_align => open ,
mm2s_dre_dest_align => open ,
mm2s_dre_flush => open ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => mm2s_strm_wvalid ,
mm2s_strm_wready => mm2s_strm_wready ,
mm2s_strm_wdata => mm2s_strm_wdata ,
mm2s_strm_wstrb => mm2s_strm_wstrb ,
mm2s_strm_wlast => mm2s_strm_wlast ,
-- MM2S Store and Forward Supplimental Control -----------
mm2s_data2sf_cmd_cmplt => open ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => DRE_ALIGN_ZEROS ,
mstr2data_dre_dest_align => DRE_ALIGN_ZEROS ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
-- I_MM2S_SKID_BUF : entity axi_sg_v4_1_2.axi_sg_skid_buf
-- generic map (
--
-- C_WDATA_WIDTH => MM2S_SDATA_WIDTH
--
-- )
-- port map (
--
-- -- System Ports
-- aclk => mm2s_aclk ,
-- arst => sig_stream_rst ,
--
-- -- Shutdown control (assert for 1 clk pulse)
-- skid_stop => sig_data2skid_halt ,
--
-- -- Slave Side (Stream Data Input)
-- s_valid => sig_data2skid_wvalid ,
-- s_ready => sig_data2skid_wready ,
-- s_data => sig_data2skid_wdata ,
-- s_strb => sig_data2skid_wstrb ,
-- s_last => sig_data2skid_wlast ,
--
-- -- Master Side (Stream Data Output
-- m_valid => mm2s_strm_wvalid ,
-- m_ready => mm2s_strm_wready ,
-- m_data => mm2s_strm_wdata ,
-- m_strb => mm2s_strm_wstrb ,
-- m_last => mm2s_strm_wlast
--
-- );
--
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_mm2s_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_sg Library Modules
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_reset;
use axi_sg_v4_1_2.axi_sg_cmd_status;
use axi_sg_v4_1_2.axi_sg_scc;
use axi_sg_v4_1_2.axi_sg_addr_cntl;
use axi_sg_v4_1_2.axi_sg_rddata_cntl;
use axi_sg_v4_1_2.axi_sg_rd_status_cntl;
use axi_sg_v4_1_2.axi_sg_skid_buf;
-------------------------------------------------------------------------------
entity axi_sg_mm2s_basic_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 16 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_ENABLE_MULTI_CHANNEL : Integer range 0 to 1 := 1;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock and Reset inputs -----------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
sg_ctl : in std_logic_vector (7 downto 0);
-- MM2S Halt request input control ---------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- Error discrete output -------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ----------
-- These are used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(1+C_ENABLE_MULTI_CHANNEL)*C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
-------------------------------------------------------------
-- Address Posting contols ----------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
-------------------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -----------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
-------------------------------------------------------------------
);
end entity axi_sg_mm2s_basic_wrap;
architecture implementation of axi_sg_mm2s_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
-- coverage off
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
-- coverage on
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := 2;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 256 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 256 := C_MM2S_SDATA_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (C_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := 1;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 64 := 1;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := 0;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 2;
Constant MM2S_BURST_SIZE : integer range 16 to 256 := 16;
Constant RD_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant DRE_ALIGN_ZEROS : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
-- obsoleted Constant DISABLE_WAIT_FOR_DATA : integer := 0;
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0);
signal sig_mm2s_cache_data : std_logic_vector(7 downto 0);
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_data2skid_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0) := (others => '0');
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug Support ------------------------------------------
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF2222" ; -- 32 bit Constant indicating MM2S Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_MULTI_CHANNEL = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_MULTI_CHANNEL = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= sg_ctl (3 downto 0); -- SG Cache from register
mm2s_aruser <= sg_ctl (7 downto 4); -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Cache signal tie-off
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_sg_v4_1_2.axi_sg_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_sg_v4_1_2.axi_sg_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_mm2s_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_sg_v4_1_2.axi_sg_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_sg_v4_1_2.axi_sg_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_sg_v4_1_2.axi_sg_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => DISABLE_WAIT_FOR_DATA ,
--C_ADDR_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_ADDR_FIFO_DEPTH => RD_ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => mm2s_allow_addr_req ,
addr_req_posted => mm2s_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_sg_v4_1_2.axi_sg_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_MM2S_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => open ,
mm2s_dre_use_autodest => open ,
mm2s_dre_src_align => open ,
mm2s_dre_dest_align => open ,
mm2s_dre_flush => open ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => mm2s_strm_wvalid ,
mm2s_strm_wready => mm2s_strm_wready ,
mm2s_strm_wdata => mm2s_strm_wdata ,
mm2s_strm_wstrb => mm2s_strm_wstrb ,
mm2s_strm_wlast => mm2s_strm_wlast ,
-- MM2S Store and Forward Supplimental Control -----------
mm2s_data2sf_cmd_cmplt => open ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => DRE_ALIGN_ZEROS ,
mstr2data_dre_dest_align => DRE_ALIGN_ZEROS ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
-- I_MM2S_SKID_BUF : entity axi_sg_v4_1_2.axi_sg_skid_buf
-- generic map (
--
-- C_WDATA_WIDTH => MM2S_SDATA_WIDTH
--
-- )
-- port map (
--
-- -- System Ports
-- aclk => mm2s_aclk ,
-- arst => sig_stream_rst ,
--
-- -- Shutdown control (assert for 1 clk pulse)
-- skid_stop => sig_data2skid_halt ,
--
-- -- Slave Side (Stream Data Input)
-- s_valid => sig_data2skid_wvalid ,
-- s_ready => sig_data2skid_wready ,
-- s_data => sig_data2skid_wdata ,
-- s_strb => sig_data2skid_wstrb ,
-- s_last => sig_data2skid_wlast ,
--
-- -- Master Side (Stream Data Output
-- m_valid => mm2s_strm_wvalid ,
-- m_ready => mm2s_strm_wready ,
-- m_data => mm2s_strm_wdata ,
-- m_strb => mm2s_strm_wstrb ,
-- m_last => mm2s_strm_wlast
--
-- );
--
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
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-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
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-- CRITICAL APPLICATIONS
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_mm2s_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_sg Library Modules
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_reset;
use axi_sg_v4_1_2.axi_sg_cmd_status;
use axi_sg_v4_1_2.axi_sg_scc;
use axi_sg_v4_1_2.axi_sg_addr_cntl;
use axi_sg_v4_1_2.axi_sg_rddata_cntl;
use axi_sg_v4_1_2.axi_sg_rd_status_cntl;
use axi_sg_v4_1_2.axi_sg_skid_buf;
-------------------------------------------------------------------------------
entity axi_sg_mm2s_basic_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 16 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_ENABLE_MULTI_CHANNEL : Integer range 0 to 1 := 1;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock and Reset inputs -----------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
sg_ctl : in std_logic_vector (7 downto 0);
-- MM2S Halt request input control ---------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- Error discrete output -------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ----------
-- These are used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(1+C_ENABLE_MULTI_CHANNEL)*C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
-------------------------------------------------------------
-- Address Posting contols ----------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
-------------------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -----------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
-------------------------------------------------------------------
);
end entity axi_sg_mm2s_basic_wrap;
architecture implementation of axi_sg_mm2s_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
-- coverage off
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
-- coverage on
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := 2;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 256 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 256 := C_MM2S_SDATA_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (C_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := 1;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 64 := 1;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := 0;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 2;
Constant MM2S_BURST_SIZE : integer range 16 to 256 := 16;
Constant RD_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant DRE_ALIGN_ZEROS : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
-- obsoleted Constant DISABLE_WAIT_FOR_DATA : integer := 0;
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0);
signal sig_mm2s_cache_data : std_logic_vector(7 downto 0);
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_data2skid_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0) := (others => '0');
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug Support ------------------------------------------
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF2222" ; -- 32 bit Constant indicating MM2S Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_MULTI_CHANNEL = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_MULTI_CHANNEL = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= sg_ctl (3 downto 0); -- SG Cache from register
mm2s_aruser <= sg_ctl (7 downto 4); -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Cache signal tie-off
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_sg_v4_1_2.axi_sg_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_sg_v4_1_2.axi_sg_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_mm2s_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_sg_v4_1_2.axi_sg_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_sg_v4_1_2.axi_sg_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_sg_v4_1_2.axi_sg_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => DISABLE_WAIT_FOR_DATA ,
--C_ADDR_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_ADDR_FIFO_DEPTH => RD_ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => mm2s_allow_addr_req ,
addr_req_posted => mm2s_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_sg_v4_1_2.axi_sg_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_MM2S_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => open ,
mm2s_dre_use_autodest => open ,
mm2s_dre_src_align => open ,
mm2s_dre_dest_align => open ,
mm2s_dre_flush => open ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => mm2s_strm_wvalid ,
mm2s_strm_wready => mm2s_strm_wready ,
mm2s_strm_wdata => mm2s_strm_wdata ,
mm2s_strm_wstrb => mm2s_strm_wstrb ,
mm2s_strm_wlast => mm2s_strm_wlast ,
-- MM2S Store and Forward Supplimental Control -----------
mm2s_data2sf_cmd_cmplt => open ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => DRE_ALIGN_ZEROS ,
mstr2data_dre_dest_align => DRE_ALIGN_ZEROS ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
-- I_MM2S_SKID_BUF : entity axi_sg_v4_1_2.axi_sg_skid_buf
-- generic map (
--
-- C_WDATA_WIDTH => MM2S_SDATA_WIDTH
--
-- )
-- port map (
--
-- -- System Ports
-- aclk => mm2s_aclk ,
-- arst => sig_stream_rst ,
--
-- -- Shutdown control (assert for 1 clk pulse)
-- skid_stop => sig_data2skid_halt ,
--
-- -- Slave Side (Stream Data Input)
-- s_valid => sig_data2skid_wvalid ,
-- s_ready => sig_data2skid_wready ,
-- s_data => sig_data2skid_wdata ,
-- s_strb => sig_data2skid_wstrb ,
-- s_last => sig_data2skid_wlast ,
--
-- -- Master Side (Stream Data Output
-- m_valid => mm2s_strm_wvalid ,
-- m_ready => mm2s_strm_wready ,
-- m_data => mm2s_strm_wdata ,
-- m_strb => mm2s_strm_wstrb ,
-- m_last => mm2s_strm_wlast
--
-- );
--
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_mm2s_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_sg Library Modules
library axi_sg_v4_1_2;
use axi_sg_v4_1_2.axi_sg_reset;
use axi_sg_v4_1_2.axi_sg_cmd_status;
use axi_sg_v4_1_2.axi_sg_scc;
use axi_sg_v4_1_2.axi_sg_addr_cntl;
use axi_sg_v4_1_2.axi_sg_rddata_cntl;
use axi_sg_v4_1_2.axi_sg_rd_status_cntl;
use axi_sg_v4_1_2.axi_sg_skid_buf;
-------------------------------------------------------------------------------
entity axi_sg_mm2s_basic_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 16 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_ENABLE_MULTI_CHANNEL : Integer range 0 to 1 := 1;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock and Reset inputs -----------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
sg_ctl : in std_logic_vector (7 downto 0);
-- MM2S Halt request input control ---------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- Error discrete output -------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ----------
-- These are used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(1+C_ENABLE_MULTI_CHANNEL)*C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
-------------------------------------------------------------
-- Address Posting contols ----------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
-------------------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -----------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
-------------------------------------------------------------------
);
end entity axi_sg_mm2s_basic_wrap;
architecture implementation of axi_sg_mm2s_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
-- coverage off
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
-- coverage on
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := 2;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 256 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 256 := C_MM2S_SDATA_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (C_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := 1;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 64 := 1;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := 0;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 2;
Constant MM2S_BURST_SIZE : integer range 16 to 256 := 16;
Constant RD_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant DRE_ALIGN_ZEROS : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
-- obsoleted Constant DISABLE_WAIT_FOR_DATA : integer := 0;
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0);
signal sig_mm2s_cache_data : std_logic_vector(7 downto 0);
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_data2skid_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0) := (others => '0');
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug Support ------------------------------------------
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF2222" ; -- 32 bit Constant indicating MM2S Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_MULTI_CHANNEL = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_MULTI_CHANNEL = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= sg_ctl (3 downto 0); -- SG Cache from register
mm2s_aruser <= sg_ctl (7 downto 4); -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Cache signal tie-off
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_sg_v4_1_2.axi_sg_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_sg_v4_1_2.axi_sg_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_mm2s_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_sg_v4_1_2.axi_sg_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_sg_v4_1_2.axi_sg_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_sg_v4_1_2.axi_sg_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => DISABLE_WAIT_FOR_DATA ,
--C_ADDR_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_ADDR_FIFO_DEPTH => RD_ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => mm2s_allow_addr_req ,
addr_req_posted => mm2s_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_sg_v4_1_2.axi_sg_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_MM2S_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => open ,
mm2s_dre_use_autodest => open ,
mm2s_dre_src_align => open ,
mm2s_dre_dest_align => open ,
mm2s_dre_flush => open ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => mm2s_strm_wvalid ,
mm2s_strm_wready => mm2s_strm_wready ,
mm2s_strm_wdata => mm2s_strm_wdata ,
mm2s_strm_wstrb => mm2s_strm_wstrb ,
mm2s_strm_wlast => mm2s_strm_wlast ,
-- MM2S Store and Forward Supplimental Control -----------
mm2s_data2sf_cmd_cmplt => open ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => DRE_ALIGN_ZEROS ,
mstr2data_dre_dest_align => DRE_ALIGN_ZEROS ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
-- I_MM2S_SKID_BUF : entity axi_sg_v4_1_2.axi_sg_skid_buf
-- generic map (
--
-- C_WDATA_WIDTH => MM2S_SDATA_WIDTH
--
-- )
-- port map (
--
-- -- System Ports
-- aclk => mm2s_aclk ,
-- arst => sig_stream_rst ,
--
-- -- Shutdown control (assert for 1 clk pulse)
-- skid_stop => sig_data2skid_halt ,
--
-- -- Slave Side (Stream Data Input)
-- s_valid => sig_data2skid_wvalid ,
-- s_ready => sig_data2skid_wready ,
-- s_data => sig_data2skid_wdata ,
-- s_strb => sig_data2skid_wstrb ,
-- s_last => sig_data2skid_wlast ,
--
-- -- Master Side (Stream Data Output
-- m_valid => mm2s_strm_wvalid ,
-- m_ready => mm2s_strm_wready ,
-- m_data => mm2s_strm_wdata ,
-- m_strb => mm2s_strm_wstrb ,
-- m_last => mm2s_strm_wlast
--
-- );
--
end implementation;
|
----------------------------------------------------------------------------
--
-- Atmel AVR CPU Entity Declaration
--
-- This is the entity declaration for the complete AVR CPU. The design
-- should implement this entity to make testing possible.
--
-- Revision History:
-- 11 May 98 Glen George Initial revision.
-- 9 May 00 Glen George Updated comments.
-- 7 May 02 Glen George Updated comments.
-- 21 Jan 08 Glen George Updated comments.
--
----------------------------------------------------------------------------
--
-- AVR_CPU
--
-- This is the complete entity declaration for the AVR CPU. It is used to
-- test the complete design.
--
-- Inputs:
-- ProgDB - program memory data bus (16 bits)
-- Reset - active low reset signal
-- INT0 - active low interrupt
-- INT1 - active low interrupt
-- clock - the system clock
--
-- Outputs:
-- ProgAB - program memory address bus (16 bits)
-- DataAB - data memory address bus (16 bits)
-- DataWr - data write signal
-- DataRd - data read signal
-- Debug - debug return value (0 for no error)
--
-- Inputs/Outputs:
-- DataDB - data memory data bus (8 bits)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library opcodes;
use opcodes.opcodes.all;
entity AVR_CPU is
port (
clock : in std_logic; -- system clock
Reset : in std_logic; -- reset signal (active low)
INT0 : in std_logic; -- interrupt signal (active low)
INT1 : in std_logic; -- interrupt signal (active low)
ProgAB : out std_logic_vector(15 downto 0); -- program memory address bus
ProgDB : in std_logic_vector(15 downto 0); -- program memory data bus
DataWr : out std_logic; -- data memory write enable (active low)
DataRd : out std_logic; -- data memory read enable (active low)
DataAB : out std_logic_vector(15 downto 0); -- data memory address bus
DataDB : inout std_logic_vector( 7 downto 0); -- data memory data bus
IRDebug : out std_logic_vector(15 downto 0); -- current instruction
Debug : out std_logic_vector( 7 downto 0) -- R16 debug output
);
end AVR_CPU;
architecture Structural of AVR_CPU is
-- Signals between Control Unit and ALU
signal ALUBlockSel : std_logic_vector(1 downto 0);
signal ALUBlockInstructionSel : std_logic_vector(3 downto 0);
signal ALUOp2Sel : std_logic;
signal ImmediateOut : std_logic_vector(7 downto 0);
signal ALUStatusMask : std_logic_vector(7 downto 0);
signal ALUStatusBitChangeEn : std_logic;
signal ALUBitClrSet : std_logic;
signal ALUBitTOp : std_logic;
signal statusZmod : std_logic;
signal ALUResult : std_logic_vector(7 downto 0);
signal ALUStatReg : std_logic_vector(7 downto 0);
-- Signals between ALU and Registers
signal RegA : std_logic_vector(7 downto 0); -- first operand
signal RegB : std_logic_vector(7 downto 0); -- second operand
-- Signals between Control Unit and Registers
signal EnableIn : std_logic; -- enable writing to register
signal SelIn : std_logic_vector( 6 downto 0); -- select input register for writing
signal SelA : std_logic_vector( 6 downto 0); -- register to output at regA
signal SelB : std_logic_vector( 6 downto 0); -- register to output at regB
signal MemRegAddr : std_logic_vector(15 downto 0); -- register-based indirect memory access
signal DataIOSel : std_logic_vector( 1 downto 0); -- selects whether data is input or output (incl. src)
signal AddrOffset : std_logic_vector(15 downto 0); -- offset of address
signal SpecAddr : std_logic_vector( 1 downto 0); -- selects X, Y, Z, or SP
signal SpecWr : std_logic; -- whether to write to the special addresses
signal RetAddrSel : std_logic_vector( 1 downto 0); -- writes stack (SP) entry to return addr buffer
signal RegDataInSel : std_logic_vector( 1 downto 0); -- selects which input goes to register in
signal MemAddr : std_logic_vector(15 downto 0); -- memory address (16 bits)
-- Signals between Control Unit and DMA / Memory
signal DMARead : std_logic;
signal DMAWrite : std_logic;
-- Signals between Control Unit and PMA Unit
signal IR : opcode_word; -- Instruction Register
signal PCUpdateSel : std_logic_vector(1 downto 0); -- source of next program counter
signal NextPC : std_logic_vector(15 downto 0); -- next program counter
signal PCOffset : std_logic_vector(11 downto 0); -- increment for program counter
signal NewIns : std_logic; -- indicates new instruction should be loaded
-- Signals between Registers and PMA Unit
signal NewPCZ : std_logic_vector(15 downto 0); -- jump to address stored in Z register
signal RetAddrRd : std_logic_vector(15 downto 0); -- jump to address stored in latest stack entry
begin
IRDebug <= IR; -- route IR to the debug output
-- Connect the ALU to the testing interface (reads input values and gives
-- status and result)
ALU : entity work.ALU
port map (
clock => clock,
ALUBlockSel => ALUBlockSel,
ALUBlockInstructionSel => ALUBlockInstructionSel,
ALUOp2Sel => ALUOp2Sel,
ImmediateOut => ImmediateOut,
ALUStatusMask => ALUStatusMask,
ALUStatusBitChangeEn => ALUStatusBitChangeEn,
ALUBitClrSet => ALUBitClrSet,
ALUBitTOp => ALUBitTOp,
statusZmod => statusZmod,
RegAOut => RegA,
RegBOut => RegB,
RegIn => ALUResult,
RegStatus => ALUStatReg
);
-- Connect the Control Unit to the testing interface (reads instruction
-- and tells ALU what to do)
ControlUnit : entity work.AVRControl
port map (
clock => clock,
IR => IR,
ProgDB => ProgDB,
MemRegAddr => MemRegAddr,
ALUStatusMask => ALUStatusMask,
ALUStatusBitChangeEn => ALUStatusBitChangeEn,
ALUBitClrSet => ALUBitClrSet,
ALUBitTOp => ALUBitTOp,
ALUOp2Sel => ALUOp2Sel,
ImmediateOut => ImmediateOut,
ALUBlockSel => ALUBlockSel,
ALUBlockInstructionSel => ALUBlockInstructionSel,
statusZmod => statusZmod,
EnableIn => EnableIn,
SelIn => SelIn,
SelA => SelA,
SelB => SelB,
ALUResult => ALUResult,
ALUStatReg => ALUStatReg,
DataIOSel => DataIOSel,
AddrOffset => AddrOffset,
SpecAddr => SpecAddr,
SpecWr => SpecWr,
RetAddrSel => RetAddrSel,
OutRd => DMARead,
OutWr => DMAWrite,
RegDataInSel => RegDataInSel,
MemAddr => MemAddr,
PCUpdateSel => PCUpdateSel,
NextPC => NextPC,
PCOffset => PCOffset,
NewIns => NewIns
);
Registers : entity work.AVRRegisters
port map (
clock => clock,
Reset => Reset,
EnableIn => EnableIn,
SelIn => SelIn,
SelA => SelA,
SelB => SelB,
ALUIn => ALUResult,
RegDataImm => ImmediateOut,
RegDataInSel => RegDataInSel,
RegAOut => RegA,
RegBOut => RegB,
SpecOut => open,
PCZ => NewPCZ,
SpecAddr => SpecAddr,
SpecWr => SpecWr,
MemRegData => DataDB,
AddrOffset => AddrOffset,
MemRegAddr => MemRegAddr,
DataIOSel => DataIOSel,
RetAddrSel => RetAddrSel,
RetAddrRd => RetAddrRd,
RetAddrWr => NextPC,
DebugReg => Debug
);
DMA : entity work.DMAUnit
port map (
clock => clock,
MemAddr => MemAddr,
MemAB => DataAB,
InRd => DMARead,
InWr => DMAWrite,
OutRd => DataRd,
OutWr => DataWr
);
PMA : entity work.PMAUnit
port map (
ProgAB => ProgAB,
ProgDB => ProgDB,
PCUpdateSel => PCUpdateSel,
NextPC => NextPC,
PCOffset => PCOffset,
NewIns => NewIns,
IR => IR,
NewPCZ => NewPCZ,
NewPCS => RetAddrRd,
Reset => Reset,
Clk => Clock
);
end Structural; |
library verilog;
use verilog.vl_types.all;
entity CMMaster4Stage is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
F2_ENVMPOWEREDDOWN: in vl_logic;
COM_MASTERENABLE: in vl_logic;
COM_CLEARSTATUS : in vl_logic;
COM_ERRORSTATUS : out vl_logic;
HADDR : in vl_logic_vector(31 downto 0);
HMASTLOCK : in vl_logic;
HSIZE : in vl_logic_vector(2 downto 0);
HTRANS1 : in vl_logic;
HWRITE : in vl_logic;
HRESP : out vl_logic;
HRDATA : out vl_logic_vector(31 downto 0);
HREADY_M : out vl_logic;
sAddrReady : in vl_logic_vector(7 downto 0);
sDataReady : in vl_logic_vector(7 downto 0);
sHResp : in vl_logic_vector(7 downto 0);
gatedHADDR : out vl_logic_vector(31 downto 0);
gatedHMASTLOCK : out vl_logic;
gatedHSIZE : out vl_logic_vector(2 downto 0);
gatedHTRANS1 : out vl_logic;
gatedHWRITE : out vl_logic;
sAddrSel : out vl_logic_vector(7 downto 0);
sDataSel : out vl_logic_vector(7 downto 0);
prevDataSlaveReady: out vl_logic;
HRDATA_S0 : in vl_logic_vector(31 downto 0);
HREADYOUT_S0 : in vl_logic;
HRDATA_S1 : in vl_logic_vector(31 downto 0);
HREADYOUT_S1 : in vl_logic;
HRDATA_S2 : in vl_logic_vector(31 downto 0);
HREADYOUT_S2 : in vl_logic;
HRDATA_S3 : in vl_logic_vector(31 downto 0);
HREADYOUT_S3 : in vl_logic;
HRDATA_S4 : in vl_logic_vector(31 downto 0);
HREADYOUT_S4 : in vl_logic;
HRDATA_S5 : in vl_logic_vector(31 downto 0);
HREADYOUT_S5 : in vl_logic;
HRDATA_S6 : in vl_logic_vector(31 downto 0);
HREADYOUT_S6 : in vl_logic;
HRDATA_S7 : in vl_logic_vector(31 downto 0);
HREADYOUT_S7 : in vl_logic
);
end CMMaster4Stage;
|
library verilog;
use verilog.vl_types.all;
entity CMMaster4Stage is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
F2_ENVMPOWEREDDOWN: in vl_logic;
COM_MASTERENABLE: in vl_logic;
COM_CLEARSTATUS : in vl_logic;
COM_ERRORSTATUS : out vl_logic;
HADDR : in vl_logic_vector(31 downto 0);
HMASTLOCK : in vl_logic;
HSIZE : in vl_logic_vector(2 downto 0);
HTRANS1 : in vl_logic;
HWRITE : in vl_logic;
HRESP : out vl_logic;
HRDATA : out vl_logic_vector(31 downto 0);
HREADY_M : out vl_logic;
sAddrReady : in vl_logic_vector(7 downto 0);
sDataReady : in vl_logic_vector(7 downto 0);
sHResp : in vl_logic_vector(7 downto 0);
gatedHADDR : out vl_logic_vector(31 downto 0);
gatedHMASTLOCK : out vl_logic;
gatedHSIZE : out vl_logic_vector(2 downto 0);
gatedHTRANS1 : out vl_logic;
gatedHWRITE : out vl_logic;
sAddrSel : out vl_logic_vector(7 downto 0);
sDataSel : out vl_logic_vector(7 downto 0);
prevDataSlaveReady: out vl_logic;
HRDATA_S0 : in vl_logic_vector(31 downto 0);
HREADYOUT_S0 : in vl_logic;
HRDATA_S1 : in vl_logic_vector(31 downto 0);
HREADYOUT_S1 : in vl_logic;
HRDATA_S2 : in vl_logic_vector(31 downto 0);
HREADYOUT_S2 : in vl_logic;
HRDATA_S3 : in vl_logic_vector(31 downto 0);
HREADYOUT_S3 : in vl_logic;
HRDATA_S4 : in vl_logic_vector(31 downto 0);
HREADYOUT_S4 : in vl_logic;
HRDATA_S5 : in vl_logic_vector(31 downto 0);
HREADYOUT_S5 : in vl_logic;
HRDATA_S6 : in vl_logic_vector(31 downto 0);
HREADYOUT_S6 : in vl_logic;
HRDATA_S7 : in vl_logic_vector(31 downto 0);
HREADYOUT_S7 : in vl_logic
);
end CMMaster4Stage;
|
library verilog;
use verilog.vl_types.all;
entity CMMaster4Stage is
port(
HCLK : in vl_logic;
HRESETn : in vl_logic;
F2_ESRAMSIZE : in vl_logic_vector(1 downto 0);
F2_ENVMPOWEREDDOWN: in vl_logic;
COM_MASTERENABLE: in vl_logic;
COM_CLEARSTATUS : in vl_logic;
COM_ERRORSTATUS : out vl_logic;
HADDR : in vl_logic_vector(31 downto 0);
HMASTLOCK : in vl_logic;
HSIZE : in vl_logic_vector(2 downto 0);
HTRANS1 : in vl_logic;
HWRITE : in vl_logic;
HRESP : out vl_logic;
HRDATA : out vl_logic_vector(31 downto 0);
HREADY_M : out vl_logic;
sAddrReady : in vl_logic_vector(7 downto 0);
sDataReady : in vl_logic_vector(7 downto 0);
sHResp : in vl_logic_vector(7 downto 0);
gatedHADDR : out vl_logic_vector(31 downto 0);
gatedHMASTLOCK : out vl_logic;
gatedHSIZE : out vl_logic_vector(2 downto 0);
gatedHTRANS1 : out vl_logic;
gatedHWRITE : out vl_logic;
sAddrSel : out vl_logic_vector(7 downto 0);
sDataSel : out vl_logic_vector(7 downto 0);
prevDataSlaveReady: out vl_logic;
HRDATA_S0 : in vl_logic_vector(31 downto 0);
HREADYOUT_S0 : in vl_logic;
HRDATA_S1 : in vl_logic_vector(31 downto 0);
HREADYOUT_S1 : in vl_logic;
HRDATA_S2 : in vl_logic_vector(31 downto 0);
HREADYOUT_S2 : in vl_logic;
HRDATA_S3 : in vl_logic_vector(31 downto 0);
HREADYOUT_S3 : in vl_logic;
HRDATA_S4 : in vl_logic_vector(31 downto 0);
HREADYOUT_S4 : in vl_logic;
HRDATA_S5 : in vl_logic_vector(31 downto 0);
HREADYOUT_S5 : in vl_logic;
HRDATA_S6 : in vl_logic_vector(31 downto 0);
HREADYOUT_S6 : in vl_logic;
HRDATA_S7 : in vl_logic_vector(31 downto 0);
HREADYOUT_S7 : in vl_logic
);
end CMMaster4Stage;
|
library ieee;
use ieee.std_logic_1164.all;
entity edgedetector is
port ( rst : in std_logic;
x : in std_logic;
clk : in std_logic;
x_falling_edge : out std_logic;
x_rising_edge : out std_logic);
end edgedetector;
architecture rtl of edgedetector is
signal q1,q2 : std_logic;
begin
edge : process(clk,rst)
begin
if(rst = '0') then
q1 <= '1';
q2 <= '1';
elsif(rising_edge(clk)) then
q2 <= q1;
q1 <= x;
end if;
end process;
x_falling_edge <= q2 and not(q1);
x_rising_edge <= q1 and not(q2);
end rtl;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library util;
use util.types_pkg.all;
use util.logic_pkg.all;
library tech;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of cache_core_banked_1rw is
constant assoc : natural := 2**log2_assoc;
constant banks : natural := 2**log2_banks;
type comb_type is record
tag_en : std_ulogic;
tag_we : std_ulogic;
tag_banken : std_ulogic_vector(assoc-1 downto 0);
tag_addr : std_ulogic_vector(index_bits-1 downto 0);
tag_rdata : std_ulogic_vector2(assoc-1 downto 0, tag_bits downto 0);
tag_wdata : std_ulogic_vector2(assoc-1 downto 0, tag_bits downto 0);
data_en : std_ulogic;
data_we : std_ulogic;
data_banken : std_ulogic_vector(assoc*banks-1 downto 0);
data_addr : std_ulogic_vector(index_bits+offset_bits-1 downto 0);
data_rdata : std_ulogic_vector2(assoc*banks-1 downto 0, word_bits-1 downto 0);
data_wdata : std_ulogic_vector2(assoc*banks-1 downto 0, word_bits-1 downto 0);
end record;
signal c : comb_type;
begin
c.tag_en <= en and tagen;
c.tag_we <= we;
c.tag_banken <= way;
c.tag_addr <= index;
c.data_en <= en and dataen;
c.data_we <= we;
c.data_addr <= index & offset;
way_loop : for n in assoc-1 downto 0 generate
tag_wdata_tagbit_loop : for m in tag_bits-1 downto 0 generate
c.tag_wdata(n, m) <= wtag(m);
end generate;
bank_loop : for m in banks-1 downto 0 generate
c.data_banken(n*banks+m) <= way(n) and banken(m);
data_bit_loop : for p in word_bits-1 downto 0 generate
c.data_wdata(n*banks+m, p) <= wdata(m, p);
rdata(n, m, p) <= c.data_rdata(n*banks+m, p);
end generate;
end generate;
end generate;
rtag <= c.tag_rdata;
seq : process (clk) is
begin
if rising_edge(clk) then
case rstn is
when '0' =>
r <= r_init;
when '1' =>
r <= r_next;
when others =>
r <= r_x;
end case;
end if;
end process;
tag_sram : entity tech.syncram_banked_1rw(rtl)
generic map (
addr_bits => index_bits,
word_bits => tag_bits,
log2_banks => log2_assoc
)
port map (
clk => clk,
en => c.tag_en,
we => c.tag_we,
banken => c.tag_banken,
addr => c.tag_addr,
wdata => c.tag_wdata,
rdata => c.tag_rdata
);
data_sram : entity tech.syncram_banked_1rw(rtl)
generic map (
addr_bits => index_bits,
word_bits => word_bits,
log2_banks => log2_assoc + log2_banks
)
port map (
clk => clk,
en => c.data_en,
we => c.data_we,
banken => c.data_banken,
addr => c.data_addr,
wdata => c.data_wdata,
rdata => c.data_rdata
);
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity heatersLogic is
generic(
heatNumber : natural := 20
);
port(
rsDataIn : in std_logic_vector(7 downto 0);
rsRdy : in std_logic;
rst : in std_logic;
clk50Mhz : in std_logic;
readyOut : out std_logic
);
end heatersLogic;
architecture Behavioral of heatersLogic is
component Heater
port(
rst : IN std_logic;
clk50Mhz : IN std_logic;
pulseWidth : IN std_logic_vector(7 downto 0);
heaterEnable : OUT std_logic
);
end component;
attribute keep_hierarchy : string;
attribute keep_hierarchy of Heater: component is "TRUE";
type registers is array (1 to heatNumber) of std_logic_vector(7 downto 0);
signal reg : registers := (others => X"00");
type state_type is (start, number, value);
signal state, next_state : state_type;
signal save : std_logic := '0';
signal hNumber : integer range 0 to heatNumber := 0;
type enableSignal is array (1 to heatNumber) of std_logic;
signal heaterEnableSignal : enableSignal := (others => '0');
attribute keep : string;
attribute keep of heaterEnableSignal: signal is "true";
attribute S: string;
attribute S of heaterEnableSignal: signal is "yes";
begin
readyOut <= '1';
Heaters_instances:
for I in 1 to heatNumber generate
InstHeater: Heater port map(
rst => rst,
clk50Mhz => clk50Mhz,
pulseWidth => reg(I),
heaterEnable => heaterEnableSignal(I)
);
end generate;
SYNC_PROC: process (clk50Mhz)
begin
if (clk50Mhz'event and clk50Mhz = '1') then
if (rst = '1') then
state <= start;
reg <= (others => X"00");
else
state <= next_state;
for I in 1 to heatNumber loop
if I = hNumber and save = '1' then
reg(I) <= rsDataIn;
else
reg(I) <= reg(I);
end if;
end loop;
end if;
end if;
end process;
OUTPUT_DECODE: process (state, rsDataIn, rsRdy, hNumber)
begin
if (state = number and rsRdy = '1') then
hNumber <= to_integer(unsigned(rsDataIn));
save <= '0';
elsif (state = value and rsRdy = '1') then
hNumber <= hNumber;
save <= '1';
else
hNumber <= hNumber;
save <= '0';
end if;
end process;
NEXT_STATE_DECODE: process (state, rsDataIn, rsRdy)
begin
next_state <= state;
case (state) is
when start =>
if rsRdy = '1' and rsDataIn = X"55" then
next_state <= number;
end if;
when number =>
if rsRdy = '1' then
next_state <= value;
end if;
when value =>
if rsRdy = '1' then
next_state <= start;
end if;
when others =>
next_state <= start;
end case;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:38:49 06/13/2011
-- Design Name:
-- Module Name: UDP_Complete_nomac - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - separated RX and TX clocks
-- Revision 0.03 - Added mac_tx_tfirst
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity UDP_Complete_nomac is
generic (
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
Port (
-- UDP TX signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready: out std_logic; -- indicates udp_tx is ready to take data
-- UDP RX signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- IP RX signals
ip_rx_hdr : out ipv4_rx_header_type;
-- system signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in udp_control_type;
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tfirst : in std_logic;
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
end UDP_Complete_nomac;
architecture structural of UDP_Complete_nomac is
------------------------------------------------------------------------------
-- Component Declaration for TX_ARBITRATOR
------------------------------------------------------------------------------
component tx_arbitrator_over_ip
port(
clk : in std_logic;
reset : in std_logic;
req_1 : in std_logic;
grant_1 : out std_logic;
data_1 : in ipv4_tx_type; -- data byte to tx
req_2 : in std_logic;
grant_2 : out std_logic;
data_2 : in ipv4_tx_type; -- data byte to tx
data : out ipv4_tx_type -- data byte to tx
);
end component;
------------------------------------------------------------------------------
-- Component Declaration for ICMP
------------------------------------------------------------------------------
COMPONENT icmp
PORT(
ip_rx_start : in std_logic; -- indicates receipt of ip frame.
ip_rx : in ipv4_rx_type;
ip_tx_start : out std_logic;
ip_tx_data_out_rdy : in std_logic;
ip_tx_result : in std_logic_vector(1 downto 0);
icmp_tx : out ipv4_tx_type;
icmp_rx_count : out std_logic_vector(15 downto 0);
icmp_tx_count : out std_logic_vector(15 downto 0);
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic;
req_ip_layer : out std_logic;
granted_ip_layer : in std_logic
);
END COMPONENT;
------------------------------------------------------------------------------
-- Component Declaration for UDP TX
------------------------------------------------------------------------------
COMPONENT UDP_TX
PORT(
-- UDP Layer signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0);-- tx status (changes during transmission)
udp_tx_data_out_ready: out std_logic; -- indicates udp_tx is ready to take data
-- system signals
clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
reset : in STD_LOGIC;
-- IP layer TX signals
ip_tx_start : out std_logic;
ip_tx : out ipv4_tx_type; -- IP tx cxns
ip_tx_result : in std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : in std_logic; -- indicates IP TX is ready to take data
--arbit
req_ip_layer : out std_logic;
granted_ip_layer : in std_logic
);
END COMPONENT;
------------------------------------------------------------------------------
-- Component Declaration for UDP RX
------------------------------------------------------------------------------
COMPONENT UDP_RX
PORT(
-- UDP Layer signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- system signals
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- IP layer RX signals
ip_rx_start : in std_logic; -- indicates receipt of ip header
ip_rx : in ipv4_rx_type
);
END COMPONENT;
------------------------------------------------------------------------------
-- Component Declaration for the IP layer
------------------------------------------------------------------------------
component IP_complete_nomac
generic (
use_arpv2 : boolean := true;
no_default_gateway: boolean := true;
CLOCK_FREQ : integer := 125000000; -- freq of data_in_clk -- needed to timout cntr
ARP_TIMEOUT : integer := 60; -- ARP response timeout (s)
ARP_MAX_PKT_TMO : integer := 5; -- # wrong nwk pkts received before set error
MAX_ARP_ENTRIES : integer := 255 -- max entries in the ARP store
);
Port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in ip_control_type;
-- status signals
arp_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- count of arp pkts received
ip_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tfirst : in std_logic;
mac_rx_tlast : in std_logic -- indicates last byte of the trame
);
end component;
-- IP TX connectivity
signal ip_tx_int : ipv4_tx_type;
signal ip_tx_start_int : std_logic;
signal ip_tx_result_int : std_logic_vector (1 downto 0);
signal ip_tx_data_out_ready_int : std_logic;
-- IP RX connectivity
signal ip_rx_int : ipv4_rx_type;
signal ip_rx_start_int : std_logic := '0';
signal ip_1_tx_start_int, ip_2_tx_start_int : std_logic;
signal data_arbit_int, data_icmp_tx_int, data_udp_tx_int : ipv4_tx_type;
signal req_1_int, grant_1_int, req_2_int, grant_2_int : std_logic;
signal icmp_rx_count_int, icmp_tx_count_int : std_logic_vector(15 downto 0);
begin
-- ip_tx_int.data.data_out_valid <= data_arbit_int.data.data_out_valid;
-- ip_tx_int.data.data_out_last <= data_arbit_int.data.data_out_last;
-- ip_tx_int.data.data_out <= data_arbit_int.data.data_out;
ip_tx_int <= data_arbit_int;
ip_tx_start_int <= ip_1_tx_start_int when grant_1_int = '1' else ip_2_tx_start_int;
tx_arbitrator_over_ip_block : tx_arbitrator_over_ip
PORT MAP(
clk => tx_clk,
reset => reset,
req_1 => req_1_int,
grant_1 => grant_1_int,
data_1 => data_udp_tx_int, -- data byte to tx from UDP
req_2 => req_2_int,
grant_2 => grant_2_int,
data_2 => data_icmp_tx_int, -- data byte to tx from ICMP
data => data_arbit_int
);
icmp_block : icmp
PORT MAP(
ip_rx_start => ip_rx_start_int,
ip_rx => ip_rx_int,
-- IP layer TX signals
ip_tx_start => ip_2_tx_start_int,
ip_tx_data_out_rdy => ip_tx_data_out_ready_int,
ip_tx_result => ip_tx_result_int,
-- ICMP layer TX signals
icmp_tx => data_icmp_tx_int,
icmp_rx_count => icmp_rx_count_int,
icmp_tx_count => icmp_tx_count_int,
rx_clk => rx_clk,
tx_clk => tx_clk,
reset => reset,
req_ip_layer => req_2_int,
granted_ip_layer => grant_2_int
);
-- output followers
ip_rx_hdr <= ip_rx_int.hdr;
-- Instantiate the UDP TX block
udp_tx_block: UDP_TX
PORT MAP (
-- UDP Layer signals
udp_tx_start => udp_tx_start,
udp_txi => udp_txi,
udp_tx_result => udp_tx_result,
udp_tx_data_out_ready=> udp_tx_data_out_ready,
-- system signals
clk => tx_clk,
reset => reset,
-- IP layer TX signals
ip_tx_start => ip_1_tx_start_int,
ip_tx => data_udp_tx_int,--ip_tx_int,
ip_tx_result => ip_tx_result_int,
ip_tx_data_out_ready => ip_tx_data_out_ready_int,
req_ip_layer => req_1_int,
granted_ip_layer => grant_1_int
);
-- Instantiate the UDP RX block
udp_rx_block: UDP_RX PORT MAP (
-- UDP Layer signals
udp_rxo => udp_rxo,
udp_rx_start => udp_rx_start,
-- system signals
clk => rx_clk,
reset => reset,
-- IP layer RX signals
ip_rx_start => ip_rx_start_int,
ip_rx => ip_rx_int
);
------------------------------------------------------------------------------
-- Instantiate the IP layer
------------------------------------------------------------------------------
IP_block : IP_complete_nomac
generic map (
use_arpv2 => false,
no_default_gateway => false,--
CLOCK_FREQ => CLOCK_FREQ,
ARP_TIMEOUT => ARP_TIMEOUT,
ARP_MAX_PKT_TMO => ARP_MAX_PKT_TMO,
MAX_ARP_ENTRIES => MAX_ARP_ENTRIES
)
PORT MAP (
-- IP interface
ip_tx_start => ip_tx_start_int,
ip_tx => ip_tx_int,
ip_tx_result => ip_tx_result_int,
ip_tx_data_out_ready => ip_tx_data_out_ready_int,
ip_rx_start => ip_rx_start_int,
ip_rx => ip_rx_int,
-- System interface
rx_clk => rx_clk,
tx_clk => tx_clk,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
control => control.ip_controls,
-- status signals
arp_pkt_count => arp_pkt_count,
ip_pkt_count => ip_pkt_count,
-- MAC Transmitter
mac_tx_tdata => mac_tx_tdata,
mac_tx_tvalid => mac_tx_tvalid,
mac_tx_tready => mac_tx_tready,
mac_tx_tfirst => mac_tx_tfirst,
mac_tx_tlast => mac_tx_tlast,
-- MAC Receiver
mac_rx_tdata => mac_rx_tdata,
mac_rx_tvalid => mac_rx_tvalid,
mac_rx_tready => mac_rx_tready,
mac_rx_tfirst => mac_rx_tfirst,
mac_rx_tlast => mac_rx_tlast
);
end structural;
|
--
-- This file is part of top_wireworld
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY top_wireworld_testbench IS
END top_wireworld_testbench;
ARCHITECTURE behavior OF top_wireworld_testbench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT top_wireworld
PORT(
clk : IN std_logic;
w1a : INOUT std_logic_vector(15 downto 0);
w1b : INOUT std_logic_vector(15 downto 0);
w2c : INOUT std_logic_vector(15 downto 0);
rx : IN std_logic;
tx : INOUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rx : std_logic := '0';
--BiDirs
signal w1a : std_logic_vector(15 downto 0);
signal w1b : std_logic_vector(15 downto 0);
signal w2c : std_logic_vector(15 downto 0);
signal tx : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: top_wireworld PORT MAP (
clk => clk,
w1a => w1a,
w1b => w1b,
w2c => w2c,
rx => rx,
tx => tx
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for clk_period;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := altera;
constant CFG_MEMTECH : integer := altera;
constant CFG_PADTECH : integer := altera;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := inferred;
constant CFG_CLKMUL : integer := 2;
constant CFG_CLKDIV : integer := 2;
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 2;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 2;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 0;
constant CFG_ATBSZ : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 0;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 1;
constant CFG_SRCTRL_PROMWS : integer := (3);
constant CFG_SRCTRL_RAMWS : integer := (2);
constant CFG_SRCTRL_IOWS : integer := (0);
constant CFG_SRCTRL_RMW : integer := 1;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := (19);
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 0;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SDRAM controller
constant CFG_SDCTRL : integer := 0;
constant CFG_SDCTRL_INVCLK : integer := 0;
constant CFG_SDCTRL_SD64 : integer := 0;
constant CFG_SDCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 0;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 8;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANLOOP : integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- PCI interface
constant CFG_PCI : integer := 0;
constant CFG_PCIVID : integer := 16#0#;
constant CFG_PCIDID : integer := 16#0#;
constant CFG_PCIDEPTH : integer := 8;
constant CFG_PCI_MTF : integer := 1;
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 1;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 0;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:10:11 04/22/2016
-- Design Name:
-- Module Name: U:/ECE368_Project_Lab1_Team5/jump_unit_tb.vhd
-- Project Name: Project1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: jump_unit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY jump_unit_tb IS
END jump_unit_tb;
ARCHITECTURE behavior OF jump_unit_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT jump_unit
PORT(
CLK : IN std_logic;
OP : IN std_logic_vector(3 downto 0);
CCR : IN std_logic_vector(3 downto 0);
MASK : IN std_logic_vector(3 downto 0);
IMMD : IN std_logic_vector(15 downto 0);
BRSIG : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal OP : std_logic_vector(3 downto 0) := (others => '0');
signal CCR : std_logic_vector(3 downto 0) := (others => '0');
signal MASK : std_logic_vector(3 downto 0) := (others => '0');
signal IMMD : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal BRSIG : std_logic;
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: jump_unit PORT MAP (
CLK => CLK,
OP => OP,
CCR => CCR,
MASK => MASK,
IMMD => IMMD,
BRSIG => BRSIG
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for CLK_period*10;
-- insert stimulus here
OP <= x"0";
MASK <= x"0";
CCR <= x"0";
wait for CLK_period;
for i in 0 to 15 loop
OP <= std_logic_vector(to_unsigned(i,OP'length));
wait for CLK_period;
for j in 0 to 3 loop
MASK <= std_logic_vector(to_unsigned(j,MASK'length));
wait for CLK_period;
for k in 0 to 3 loop
CCR <= std_logic_vector(to_unsigned(k,CCR'length));
wait for CLK_period;
if(MASK = CCR AND OP = x"F") then -- BRSIG = 1
assert(BRSIG = '1') report "BRSIG assigned incorrectly, MASK = CCR AND OP = x'F'" severity ERROR;
elsif(MASK = CCR AND NOT(OP=x"F")) then
assert(BRSIG = '0') report "BRSIG assigned incorrectly, MASK = CCR AND OP != x'F'." severity ERROR;
elsif ( NOT(MASK = CCR) AND OP=x"F") then
assert(BRSIG = '0') report "BRSIG assigned incorrectly, MASK != CCR AND OP = x'F'." severity ERROR;
else
assert(BRSIG = '0') report "BRSIG assigned incorrectly, MASK != CCR AND OP != x'F'." severity ERROR;
end if;
end loop;
end loop;
end loop;
OP <= x"0";
MASK <= x"0";
CCR <= x"0";
wait;
end process;
END;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc129.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x01p04n02i00129ent IS
END c04s03b02x01p04n02i00129ent;
ARCHITECTURE c04s03b02x01p04n02i00129arch OF c04s03b02x01p04n02i00129ent IS
component A2
port (constant PT2: INTEGER); -- Failure_here
-- ERROR: the only object class allowed in a local port is signal.
end component ;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b02x01p04n02i00129 - The only object class allowed is signal."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x01p04n02i00129arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc129.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x01p04n02i00129ent IS
END c04s03b02x01p04n02i00129ent;
ARCHITECTURE c04s03b02x01p04n02i00129arch OF c04s03b02x01p04n02i00129ent IS
component A2
port (constant PT2: INTEGER); -- Failure_here
-- ERROR: the only object class allowed in a local port is signal.
end component ;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b02x01p04n02i00129 - The only object class allowed is signal."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x01p04n02i00129arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc129.vhd,v 1.2 2001-10-26 16:30:08 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x01p04n02i00129ent IS
END c04s03b02x01p04n02i00129ent;
ARCHITECTURE c04s03b02x01p04n02i00129arch OF c04s03b02x01p04n02i00129ent IS
component A2
port (constant PT2: INTEGER); -- Failure_here
-- ERROR: the only object class allowed in a local port is signal.
end component ;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b02x01p04n02i00129 - The only object class allowed is signal."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x01p04n02i00129arch;
|
-------------------------------------------------------------------------------
--
-- Title : or64bit
-- Design : ALU
-- Author : riczhang
-- Company : Stony Brook University
--
-------------------------------------------------------------------------------
--
-- File : c:\My_Designs\ESE345_PROJECT\ALU\src\or64bit.vhd
-- Generated : Mon Dec 5 17:40:01 2016
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
--{{ Section below this comment is automatically maintained
-- and may be overwritten
--{entity {or64bit} architecture {behavioral}}
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity or64bit is
port(
rs1: in std_logic_vector(63 downto 0);
rs2: in std_logic_vector(63 downto 0);
rd: out std_logic_vector (63 downto 0)
);
end or64bit;
--}} End of automatically maintained section
architecture behavioral of or64bit is
begin
rd <= rs1 or rs2;
end behavioral;
|
-------------------------------------------------------------------------------
-- Module: tb_tld
-- Purpose: Testbench for Top Level Domain of ECDSA
--
-- Author: Leander Schulz
-- Date: 01.11.2017
-- Last change: 01.11.2017
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY tb_tld IS
END ENTITY tb_tld;
ARCHITECTURE tb_arch OF tb_tld IS
-- import tld of ecdsa
COMPONENT tld_ecdsa IS
PORT (
-- Clock and reset
clk_i: IN std_logic;
rst_i: IN std_logic;
-- Uart read/write
uart_rx_i : IN std_logic;
uart_wx_i : OUT std_logic;
rst_led : OUT std_logic
);
END COMPONENT tld_ecdsa;
--internal signals
SIGNAL s_clk : std_logic;
SIGNAL s_rst : std_logic := '0';
SIGNAL S_rx : std_logic;
SIGNAL S_tx : std_logic;
SIGNAL s_led : std_logic;
SIGNAL s_r : std_logic_vector (167 DOWNTO 0);
SIGNAL s_s : std_logic_vector (167 DOWNTO 0);
SIGNAL s_m : std_logic_vector (167 DOWNTO 0);
SIGNAL s_mode : std_logic;
BEGIN
-- create ecdsa instance
tld_inst : tld_ecdsa
PORT MAP (
clk_i => s_clk,
rst_i => s_rst,
uart_rx_i => s_rx,
uart_wx_i => s_tx,
rst_led => s_led
);
-- generate clock signal
p_clk : PROCESS BEGIN
s_clk <= '0';
WAIT FOR 10 ns;
s_clk <= '1';
WAIT FOR 10 ns;
END PROCESS p_clk;
-- begin testbench tests
testing : PROCESS IS
PROCEDURE p_send (
SIGNAL s_mode : IN std_logic;
SIGNAL s_r : IN std_logic_vector(167 DOWNTO 0);
SIGNAL s_s : IN std_logic_vector(167 DOWNTO 0);
SIGNAL s_m : IN std_logic_vector(167 DOWNTO 0);
SIGNAL s_rx : OUT std_logic
) IS
BEGIN
-- send mode
ASSERT FALSE REPORT "Send Mode" SEVERITY NOTE;
s_rx <= '0'; -- Start Bit
WAIT FOR 2000 ns;
FOR i IN 0 TO 7 LOOP
s_rx <= s_mode;
WAIT FOR 2000 ns;
END LOOP;
s_rx <= '1'; -- stop bit and idle
WAIT FOR 5000 ns;
IF s_mode = '1' THEN
-- send r
ASSERT FALSE REPORT "Send Point R" SEVERITY NOTE;
FOR i IN 20 DOWNTO 0 LOOP
s_rx <= '0'; -- Start Bit
WAIT FOR 2000 ns;
FOR j IN 0 TO 7 LOOP
s_rx <= s_r(i*8+j); -- send bits 0-7
WAIT FOR 2000 ns;
END LOOP;
s_rx <= '1'; -- stop bit and idle
WAIT FOR 5000 ns;
END LOOP;
-- send s
ASSERT FALSE REPORT "Send Point S" SEVERITY NOTE;
FOR i IN 20 DOWNTO 0 LOOP
s_rx <= '0'; -- Start Bit
WAIT FOR 2000 ns;
FOR j IN 0 TO 7 LOOP
s_rx <= s_s(i*8+j); -- send bits 0-7
WAIT FOR 2000 ns;
END LOOP;
s_rx <= '1'; -- stop bit and idle
WAIT FOR 5000 ns;
END LOOP;
END IF;
-- send m
ASSERT FALSE REPORT "Send Message" SEVERITY NOTE;
FOR i IN 20 DOWNTO 0 LOOP
s_rx <= '0'; -- Start Bit
WAIT FOR 2000 ns;
FOR j IN 0 TO 7 LOOP
ASSERT (i*8+j)<168 SEVERITY WARNING;
s_rx <= s_m(i*8+j); -- send bits 0-7
WAIT FOR 2000 ns;
END LOOP;
s_rx <= '1'; -- stop bit and idle
WAIT FOR 5000 ns;
END LOOP;
END p_send;
BEGIN
-- Initialise Hardware
s_rx <= '1';
WAIT FOR 100 ns;
s_rst <= '1';
WAIT FOR 20 ns;
s_rst <= '0';
WAIT FOR 80 ns;
-- Test Case 1 --------------------------------------
s_r <= x"020B448AD8BE882CD980816C7EEA289FD3B2D517DB";
s_s <= x"0586558EFE0D6068075EA682084A259E370B4A375B";
--s_m <= x"00CD06203260EEE9549351BD29733E7D1E2ED49D88";
s_m <= x"0669148956365B7FABBC2383ED3ED1678D4E564463";
-- Sign
s_mode <= '0';
p_send(s_mode,s_r,s_s,s_m,s_rx);
-- TODO: check tx for valid result
WAIT FOR 3500 us;
-- Verify
s_mode <= '1';
p_send(s_mode,s_r,s_s,s_m,s_rx);
-- should evaluate to false
WAIT FOR 3500 us;
-- Test Case 1 - Verify
s_mode <= '1';
p_send(s_mode,s_r,s_s,s_m,s_rx);
WAIT FOR 3500 us;
-- Test Case 2 --------------------------------------
s_r <= x"020B448AD8BE882CD980816C7EEA289FD3B2D517DB";
s_s <= x"005107642C9D1D591ED4F944040B28EB692B7680A0";
s_m <= x"0669148956365B7FABBC2383ED3ED1678D4E564463";
-- Sign
s_mode <= '0';
p_send(s_mode,s_r,s_s,s_m,s_rx);
-- result:
-- 020B448AD8BE882CD980816C7EEA289FD3B2D517DB
-- 0586558EFE0D6068075EA682084A259E370B4A375B
-- 0669148956365B7FABBC2383ED3ED1678D4E564463
WAIT FOR 3500 us;
-- Verify
s_mode <= '1';
p_send(s_mode,s_r,s_s,s_m,s_rx);
-- should evaluate to true
WAIT;
END PROCESS testing;
END ARCHITECTURE tb_arch;
|
--
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
entity voice_generator is
port (EN: in std_logic
;CLK_EVEN: in std_logic
;CLK_ODD: in std_logic
;FREQ: in time_signal
;GATE: in std_logic
;PARAMS: in synthesis_params
;AUDIO_OUT: out voice_signal
;OUT_TO_FIFO: out state_vector_t
;IN_FROM_FIFO: in state_vector_t
);
end entity;
architecture voice_generator_impl of voice_generator is
signal s1_freq: time_signal := (others=>'0');
signal s1_cutoff: time_signal;
signal s1_cutoff_stage: adsr_stage;
signal s1_cutoff_prev_gate: std_logic;
signal s1_gain: time_signal;
signal s1_gain_stage: adsr_stage;
signal s1_gain_prev_gate: std_logic;
signal s1_phase: time_signal;
signal s4_wf: waveform_t;
signal s4_cutoff: ctl_signal;
signal s4_theta: ctl_signal;
signal s4_gain: ctl_signal;
signal s8_theta: ctl_signal;
signal s8_gain: ctl_signal;
signal s9_z: voice_signal;
signal s9_gain: ctl_signal;
signal s12_z_ampl: voice_signal;
begin
process(CLK_EVEN)
begin
if EN='1' and rising_edge(CLK_EVEN) then
s1_freq <= FREQ;
end if;
end process;
phase_gen:
entity
work.phase_gen (phase_gen_impl)
port map
('1'
,CLK_EVEN
,IN_FROM_FIFO.sv_phase
,s1_phase
);
env_gen_cutoff:
entity
work.env_gen (env_gen_impl)
port map
('1'
,CLK_EVEN
,GATE
,PARAMS.sp_cutoff_base
,PARAMS.sp_cutoff_env
,PARAMS.sp_cutoff_attack
,PARAMS.sp_cutoff_decay
,PARAMS.sp_cutoff_sustain
,PARAMS.sp_cutoff_rel
,IN_FROM_FIFO.sv_cutoff
,s1_cutoff
,IN_FROM_FIFO.sv_cutoff_stage
,s1_cutoff_stage
,IN_FROM_FIFO.sv_cutoff_prev_gate
,s1_cutoff_prev_gate
);
env_gen_gain:
entity
work.env_gen (env_gen_impl)
port map
('1'
,CLK_EVEN
,GATE
,x"00"
,x"FF"
,PARAMS.sp_gain_attack
,PARAMS.sp_gain_decay
,PARAMS.sp_gain_sustain
,PARAMS.sp_gain_rel
,IN_FROM_FIFO.sv_gain
,s1_gain
,IN_FROM_FIFO.sv_gain_stage
,s1_gain_stage
,IN_FROM_FIFO.sv_gain_prev_gate
,s1_gain_prev_gate
);
voice_controller:
entity
work.voice_controller (voice_controller_impl)
port map
('1'
,CLK_ODD
,CLK_EVEN
,PARAMS.sp_mode
,s1_freq
,s1_cutoff
,s4_cutoff
,s1_gain
,s4_gain
,s1_phase
,s4_theta
,s4_wf
);
phase_distort:
entity
work.phase_distort (phase_distort_impl)
port map
('1'
,CLK_EVEN
,CLK_ODD
,s4_wf
,s4_cutoff
,s4_theta
,s8_theta
,s4_gain
,s8_gain
);
waveshaper:
entity
work.waveshaper(waveshaper_sin)
port map
('1'
,CLK_ODD
,s8_theta
,s9_z
,s8_gain
,s9_gain
);
amplifier:
entity
work.amplifier (amplifier_impl)
port map
('1'
,CLK_EVEN
,CLK_ODD
,s9_gain
,s9_z
,s12_z_ampl
);
AUDIO_OUT <= s12_z_ampl;
OUT_TO_FIFO <=
(s1_phase
,s1_gain
,s1_gain_stage
,s1_gain_prev_gate
,s1_cutoff
,s1_cutoff_stage
,s1_cutoff_prev_gate
);
end architecture;
|
--
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
entity voice_generator is
port (EN: in std_logic
;CLK_EVEN: in std_logic
;CLK_ODD: in std_logic
;FREQ: in time_signal
;GATE: in std_logic
;PARAMS: in synthesis_params
;AUDIO_OUT: out voice_signal
;OUT_TO_FIFO: out state_vector_t
;IN_FROM_FIFO: in state_vector_t
);
end entity;
architecture voice_generator_impl of voice_generator is
signal s1_freq: time_signal := (others=>'0');
signal s1_cutoff: time_signal;
signal s1_cutoff_stage: adsr_stage;
signal s1_cutoff_prev_gate: std_logic;
signal s1_gain: time_signal;
signal s1_gain_stage: adsr_stage;
signal s1_gain_prev_gate: std_logic;
signal s1_phase: time_signal;
signal s4_wf: waveform_t;
signal s4_cutoff: ctl_signal;
signal s4_theta: ctl_signal;
signal s4_gain: ctl_signal;
signal s8_theta: ctl_signal;
signal s8_gain: ctl_signal;
signal s9_z: voice_signal;
signal s9_gain: ctl_signal;
signal s12_z_ampl: voice_signal;
begin
process(CLK_EVEN)
begin
if EN='1' and rising_edge(CLK_EVEN) then
s1_freq <= FREQ;
end if;
end process;
phase_gen:
entity
work.phase_gen (phase_gen_impl)
port map
('1'
,CLK_EVEN
,IN_FROM_FIFO.sv_phase
,s1_phase
);
env_gen_cutoff:
entity
work.env_gen (env_gen_impl)
port map
('1'
,CLK_EVEN
,GATE
,PARAMS.sp_cutoff_base
,PARAMS.sp_cutoff_env
,PARAMS.sp_cutoff_attack
,PARAMS.sp_cutoff_decay
,PARAMS.sp_cutoff_sustain
,PARAMS.sp_cutoff_rel
,IN_FROM_FIFO.sv_cutoff
,s1_cutoff
,IN_FROM_FIFO.sv_cutoff_stage
,s1_cutoff_stage
,IN_FROM_FIFO.sv_cutoff_prev_gate
,s1_cutoff_prev_gate
);
env_gen_gain:
entity
work.env_gen (env_gen_impl)
port map
('1'
,CLK_EVEN
,GATE
,x"00"
,x"FF"
,PARAMS.sp_gain_attack
,PARAMS.sp_gain_decay
,PARAMS.sp_gain_sustain
,PARAMS.sp_gain_rel
,IN_FROM_FIFO.sv_gain
,s1_gain
,IN_FROM_FIFO.sv_gain_stage
,s1_gain_stage
,IN_FROM_FIFO.sv_gain_prev_gate
,s1_gain_prev_gate
);
voice_controller:
entity
work.voice_controller (voice_controller_impl)
port map
('1'
,CLK_ODD
,CLK_EVEN
,PARAMS.sp_mode
,s1_freq
,s1_cutoff
,s4_cutoff
,s1_gain
,s4_gain
,s1_phase
,s4_theta
,s4_wf
);
phase_distort:
entity
work.phase_distort (phase_distort_impl)
port map
('1'
,CLK_EVEN
,CLK_ODD
,s4_wf
,s4_cutoff
,s4_theta
,s8_theta
,s4_gain
,s8_gain
);
waveshaper:
entity
work.waveshaper(waveshaper_sin)
port map
('1'
,CLK_ODD
,s8_theta
,s9_z
,s8_gain
,s9_gain
);
amplifier:
entity
work.amplifier (amplifier_impl)
port map
('1'
,CLK_EVEN
,CLK_ODD
,s9_gain
,s9_z
,s12_z_ampl
);
AUDIO_OUT <= s12_z_ampl;
OUT_TO_FIFO <=
(s1_phase
,s1_gain
,s1_gain_stage
,s1_gain_prev_gate
,s1_cutoff
,s1_cutoff_stage
,s1_cutoff_prev_gate
);
end architecture;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: VGA Buffer Ram
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Ram for the VGA Display
-- Holds the buffer for the VGA
---------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity VGA_BUFFER_RAM is
generic( ADDR_WIDTH: integer:=13;
DATA_WIDTH:integer:=8
);
port( CLK : in std_logic;
RST : in std_logic;
WE : in std_logic;
ADDR_A : in std_logic_vector(ADDR_WIDTH-1 downto 0);
ADDR_B : in std_logic_vector(ADDR_WIDTH-1 downto 0);
DIN_A : in std_logic_vector(7 downto 0);
DOUT_B : out std_logic_vector(6 downto 0)
);
end VGA_BUFFER_RAM;
architecture Behavioral of VGA_BUFFER_RAM is
type ram_type is array (0 to 2**ADDR_WIDTH-1) of std_logic_vector (DATA_WIDTH-1 downto 0);
signal addr_b_reg: std_logic_vector(ADDR_WIDTH-1 downto 0);
signal ram: ram_type;-- := (
-- --1: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --2: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --3: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --4: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --5: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --6: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --7: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --8: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --9: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --10: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --11: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --12: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --13: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --14: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --15: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --16: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --17: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --18: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --19: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --20: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --21: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --22: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --23: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --24: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --25: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --26: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --27: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --28: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --29: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --30: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --31: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --32: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --33: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --34: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --35: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --36: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --37: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --38: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --39: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
--
-- --40: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",
-- X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20",X"20"--4096
-- );
begin
process(CLK, WE)
variable tmp_b : integer;
begin
if (CLK'event and CLK = '1') then
if (WE = '1') then
ram(to_integer(unsigned(ADDR_A))) <= DIN_A;
end if;
addr_b_reg <= ADDR_B;
end if;
end process;
DOUT_B <= ram(to_integer(unsigned(addr_b_reg)))(6 downto 0);
end Behavioral;
|
-------------------------------------------------------------------------------
--! @file asyncFifo-rtl-a.vhd
--
--! @brief The asynchronous Fifo architecture.
--
--! @details This is a generic dual clocked FIFO using the dpRam component as
--! memory.
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
architecture rtl of asyncFifo is
--! Address width
constant cAddrWidth : natural := logDualis(gWordSize);
--! Type for DPRAM port commons
type tDpramPortCommon is record
clk : std_logic;
enable : std_logic;
address : std_logic_vector(cAddrWidth-1 downto 0);
end record;
--! Type for DPRAM port assignment
type tDpramPort is record
wrPort : tDpramPortCommon;
rdPort : tDpramPortCommon;
write : std_logic;
writedata : std_logic_vector(gDataWidth-1 downto 0);
readdata : std_logic_vector(gDataWidth-1 downto 0);
end record;
--! Type for control port
type tControlPort is record
clk : std_logic;
rst : std_logic;
request : std_logic;
otherPointer : std_logic_vector(cAddrWidth downto 0);
empty : std_logic;
full : std_logic;
pointer : std_logic_vector(cAddrWidth downto 0);
address : std_logic_vector(cAddrWidth-1 downto 0);
usedWord : std_logic_vector(cAddrWidth-1 downto 0);
end record;
--! Type for pointer synchronizers
type tPointerSyncPort is record
clk : std_logic;
rst : std_logic;
din : std_logic_vector(cAddrWidth downto 0);
dout : std_logic_vector(cAddrWidth downto 0);
end record;
--! DPRAM instance
signal inst_dpram : tDpramPort;
--! Write controller instance
signal inst_writeCtrl : tControlPort;
--! Read controller instance
signal inst_readCtrl : tControlPort;
--! Write pointer synchronizer instance
signal inst_writeSync : tPointerSyncPort;
--! Read pointer synchronizer instance
signal inst_readSync : tPointerSyncPort;
begin
assert (gMemRes = "ON")
report "This FIFO implementation only supports memory resources!"
severity warning;
---------------------------------------------------------------------------
-- Assign Outputs
---------------------------------------------------------------------------
-- Write port
oWrEmpty <= inst_writeCtrl.empty;
oWrFull <= inst_writeCtrl.full;
oWrUsedw <= inst_writeCtrl.usedWord;
-- Read port
oRdEmpty <= inst_readCtrl.empty;
oRdFull <= inst_readCtrl.full;
oRdUsedw <= inst_readCtrl.usedWord;
oRdData <= inst_dpram.readdata;
---------------------------------------------------------------------------
-- Map DPRAM instance
---------------------------------------------------------------------------
-- Write port
inst_dpram.wrPort.clk <= iWrClk;
inst_dpram.wrPort.enable <= inst_writeCtrl.request;
inst_dpram.write <= inst_writeCtrl.request;
inst_dpram.wrPort.address <= inst_writeCtrl.address;
inst_dpram.writedata <= iWrData;
-- Read port
inst_dpram.rdPort.clk <= iRdClk;
inst_dpram.rdPort.enable <= iRdReq;
inst_dpram.rdPort.address <= inst_readCtrl.address;
---------------------------------------------------------------------------
-- Map Write and Read controller instance
---------------------------------------------------------------------------
inst_readCtrl.clk <= iRdClk;
inst_readCtrl.rst <= iAclr;
inst_readCtrl.request <= iRdReq;
inst_readCtrl.otherPointer <= inst_writeSync.dout;
inst_writeCtrl.clk <= iWrClk;
inst_writeCtrl.rst <= iAclr;
inst_writeCtrl.request <= iWrReq and not inst_writeCtrl.full;
inst_writeCtrl.otherPointer <= inst_readSync.dout;
---------------------------------------------------------------------------
-- Map pointer synchronizers
---------------------------------------------------------------------------
inst_readSync.rst <= iAclr;
inst_readSync.clk <= iWrClk; -- synchronize read pointer to write clock
inst_readSync.din <= inst_readCtrl.pointer;
inst_writeSync.rst <= iAclr;
inst_writeSync.clk <= iRdClk; -- synchronize write pointer to read clock
inst_writeSync.din <= inst_writeCtrl.pointer;
---------------------------------------------------------------------------
-- Instances
---------------------------------------------------------------------------
--! This is the FIFO read controller.
FIFO_READ_CONTROL : entity work.fifoRead
generic map (
gAddrWidth => cAddrWidth
)
port map (
iClk => inst_readCtrl.clk,
iRst => inst_readCtrl.rst,
iRead => inst_readCtrl.request,
iWrPointer => inst_readCtrl.otherPointer,
oEmpty => inst_readCtrl.empty,
oFull => inst_readCtrl.full,
oPointer => inst_readCtrl.pointer,
oAddress => inst_readCtrl.address,
oUsedWord => inst_readCtrl.usedWord
);
--! This is the FIFO write controller.
FIFO_WRITE_CONTROL : entity work.fifoWrite
generic map (
gAddrWidth => cAddrWidth
)
port map (
iClk => inst_writeCtrl.clk,
iRst => inst_writeCtrl.rst,
iWrite => inst_writeCtrl.request,
iRdPointer => inst_writeCtrl.otherPointer,
oEmpty => inst_writeCtrl.empty,
oFull => inst_writeCtrl.full,
oPointer => inst_writeCtrl.pointer,
oAddress => inst_writeCtrl.address,
oUsedWord => inst_writeCtrl.usedWord
);
--! This is the FIFO buffer.
FIFO_BUFFER : entity work.dpRamSplxNbe
generic map (
gWordWidth => gDataWidth,
gNumberOfWords => gWordSize,
gInitFile => "UNUSED"
)
port map (
iClk_A => inst_dpram.wrPort.clk,
iEnable_A => inst_dpram.wrPort.enable,
iWriteEnable_A => inst_dpram.write,
iAddress_A => inst_dpram.wrPort.address,
iWritedata_A => inst_dpram.writedata,
iClk_B => inst_dpram.rdPort.clk,
iEnable_B => inst_dpram.rdPort.enable,
iAddress_B => inst_dpram.rdPort.address,
oReaddata_B => inst_dpram.readdata
);
--! This generate block instantiates multiple synchrinizers to transfer
--! the write and read pointers to the opposite clock domains.
GEN_POINTERSYNC : for i in cAddrWidth downto 0 generate
WRITESYNC : entity libcommon.synchronizer
generic map (
gStages => gSyncStages,
gInit => cInactivated
)
port map (
iArst => inst_writeSync.rst,
iClk => inst_writeSync.clk,
iAsync => inst_writeSync.din(i),
oSync => inst_writeSync.dout(i)
);
READSYNC : entity libcommon.synchronizer
generic map (
gStages => gSyncStages,
gInit => cInactivated
)
port map (
iArst => inst_readSync.rst,
iClk => inst_readSync.clk,
iAsync => inst_readSync.din(i),
oSync => inst_readSync.dout(i)
);
end generate GEN_POINTERSYNC;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- pragma translate_off
--library synplify;
--use synplify.attributes.all;
-- pragma translate_on
entity ADDC is
generic (
width : integer
);
port(
opa: in std_logic_vector(width-1 downto 0);
opb: in std_logic_vector(width-1 downto 0);
ci: in std_logic;
sum: out std_logic_vector(width-1 downto 0);
co: out std_logic
);
end ADDC;
architecture behavior of ADDC is
begin
process(opa,opb,ci)
variable res:std_logic_vector( width downto 0 ):=(others=>'0');
begin
res:=('0'&opa)+('0'&opb)+ci;
sum<=res(width-1 downto 0);
co<=res(width);
end process;
end behavior;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pci
-- File: pci.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Package with component and type declarations for PCI cores
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
package pci is
type pci_in_type is record
rst : std_ulogic;
gnt : std_ulogic;
idsel : std_ulogic;
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_ulogic;
irdy : std_ulogic;
trdy : std_ulogic;
devsel : std_ulogic;
stop : std_ulogic;
lock : std_ulogic;
perr : std_ulogic;
serr : std_ulogic;
par : std_ulogic;
host : std_ulogic;
pci66 : std_ulogic;
pme_status : std_ulogic;
int : std_logic_vector(3 downto 0); -- D downto A
end record;
constant pci_in_none : pci_in_type := (
rst => '0',
gnt => '0',
idsel => '0',
ad => (others => '0'),
cbe => (others => '0'),
frame => '0',
irdy => '0',
trdy => '0',
devsel => '0',
stop => '0',
lock => '0',
perr => '0',
serr => '0',
par => '0',
host => '0',
pci66 => '0',
pme_status => '0',
int => (others => '0'));
type pci_out_type is record
aden : std_ulogic;
vaden : std_logic_vector(31 downto 0);
cbeen : std_logic_vector(3 downto 0);
frameen : std_ulogic;
irdyen : std_ulogic;
trdyen : std_ulogic;
devselen : std_ulogic;
stopen : std_ulogic;
ctrlen : std_ulogic;
perren : std_ulogic;
paren : std_ulogic;
reqen : std_ulogic;
locken : std_ulogic;
serren : std_ulogic;
inten : std_logic;
vinten : std_logic_vector(3 downto 0);
req : std_ulogic;
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_ulogic;
irdy : std_ulogic;
trdy : std_ulogic;
devsel : std_ulogic;
stop : std_ulogic;
perr : std_ulogic;
serr : std_ulogic;
par : std_ulogic;
lock : std_ulogic;
power_state : std_logic_vector(1 downto 0);
pme_enable : std_ulogic;
pme_clear : std_ulogic;
int : std_logic;
rst : std_ulogic;
end record;
constant pci_out_none : pci_out_type := (
aden => '1', vaden => (others => '1'), cbeen => (others => '1'),
frameen => '1', irdyen => '1', trdyen => '1', devselen => '1',
stopen => '1', ctrlen => '1', perren => '1', paren => '1', reqen => '1',
locken => '1', serren => '1', inten => '1', vinten => (others => '1'), req => '1', ad => (others => '0'),
cbe => (others => '1'), frame => '1', irdy => '1', trdy => '1', devsel => '1',
stop => '1', perr => '1', serr => '1', par => '1', lock => '1',
power_state => (others => '1'), pme_enable => '1',pme_clear => '1',
int => '1', rst => '1');
component pci_target
generic (
hindex : integer := 0;
abits : integer := 21;
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
nsync : integer range 1 to 2 := 1; -- 1 or 2 sync regs between clocks
oepol : integer := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
pciclk : in std_ulogic;
pcii : in pci_in_type;
pcio : out pci_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type
);
end component;
component pci_mt
generic (
hmstndx : integer := 0;
abits : integer := 21;
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
master : integer := 1; -- Enable PCI Master
hslvndx : integer := 0;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
nsync : integer range 1 to 2 := 1; -- 1 or 2 sync regs between clocks
oepol : integer := 0
);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
component dmactrl
generic (
hindex : integer := 0;
slvindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
blength : integer := 4);
port (
rst : in std_logic;
clk : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi0 : in ahb_slv_in_type;
ahbso0 : out ahb_slv_out_type;
ahbsi1 : out ahb_slv_in_type;
ahbso1 : in ahb_slv_out_type);
end component;
component pci_mtf
generic (
memtech : integer := DEFMEMTECH;
hmstndx : integer := 0;
dmamst : integer := NAHBMST;
readpref : integer := 0;
abits : integer := 21;
dmaabits : integer := 26;
fifodepth : integer := 3; -- FIFO depth
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
master : integer := 1; -- Enable PCI Master
hslvndx : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
irq : integer := 0;
irqmask : integer := 0;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
oepol : integer := 0;
endian : integer := 0;
class_code: integer := 16#0B4000#;
rev : integer := 0;
scanen : integer := 0;
syncrst : integer := 0;
hostrst : integer := 0);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
component pcitrace
generic (
depth : integer range 6 to 12 := 8;
iregs : integer := 1;
memtech : integer := DEFMEMTECH;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#f00#
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
pciclk : in std_ulogic;
pcii : in pci_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end component;
component pcipads
generic (
padtech : integer := 0;
noreset : integer := 0;
oepol : integer := 0;
host : integer := 1;
int : integer := 0;
no66 : integer := 0;
onchipreqgnt : integer := 0;
drivereset : integer := 0;
constidsel : integer := 0;
level : integer := pci33;
voltage : integer := x33v;
nolock : integer := 0
);
port (
pci_rst : inout std_logic;
pci_gnt : in std_ulogic;
pci_idsel : in std_ulogic;
pci_lock : inout std_ulogic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic; -- tristate pad but never read
pci_serr : inout std_logic; -- open drain output
pci_host : in std_ulogic;
pci_66 : in std_ulogic;
pcii : out pci_in_type;
pcio : in pci_out_type;
pci_int : inout std_logic_vector(3 downto 0)
);
end component;
component pcidma
generic (
memtech : integer := DEFMEMTECH;
dmstndx : integer := 0;
dapbndx : integer := 0;
dapbaddr : integer := 0;
dapbmask : integer := 16#fff#;
dapbirq : integer := 0;
blength : integer := 16;
mstndx : integer := 0;
abits : integer := 21;
dmaabits : integer := 26;
fifodepth : integer := 3; -- FIFO depth
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
slvndx : integer := 0;
apbndx : integer := 0;
apbaddr : integer := 0;
apbmask : integer := 16#fff#;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
oepol : integer := 0;
endian : integer := 0; -- 0 little, 1 big
class_code: integer := 16#0B4000#;
rev : integer := 0;
irq : integer := 0;
irqmask : integer := 0;
scanen : integer := 0;
hostrst : integer := 0;
syncrst : integer := 0);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
dapbo : out apb_slv_out_type;
dahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
type pci_ahb_dma_in_type is record
address : std_logic_vector(31 downto 0);
wdata : std_logic_vector(31 downto 0);
start : std_ulogic;
burst : std_ulogic;
write : std_ulogic;
busy : std_ulogic;
irq : std_ulogic;
size : std_logic_vector(1 downto 0);
end record;
type pci_ahb_dma_out_type is record
start : std_ulogic;
active : std_ulogic;
ready : std_ulogic;
retry : std_ulogic;
mexc : std_ulogic;
haddr : std_logic_vector(9 downto 0);
rdata : std_logic_vector(31 downto 0);
end record;
component pciahbmst
generic (
hindex : integer := 0;
hirq : integer := 0;
venid : integer := VENDOR_GAISLER;
devid : integer := 0;
version : integer := 0;
chprot : integer := 3;
incaddr : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
dmai : in pci_ahb_dma_in_type;
dmao : out pci_ahb_dma_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end component;
component pcif
generic (
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
class : integer := 0;
revision_id : integer := 0;
aaddr_width : integer := 28;
maddr_width : integer := 28;
pcibars : integer := 1;
ahbmasters : integer := 8;
fifo_depth : integer := 3;
ft : integer := 0;
memtech : integer := 0;
hmstndx : integer := 0;
hslvndx : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#);
port(
rst : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type);
--debug : out std_logic_vector(233 downto 0));
end component;
component pcif_async
generic (
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
class : integer := 0;
revision_id : integer := 0;
bar1 : integer := 20;
bar2 : integer := 24;
bar3 : integer := 0;
bar4 : integer := 0;
ahbmasters : integer := 28;
fifo_depth : integer := 1;
ft : integer := 0;
nsync : integer := 2;
irqctrl : integer := 0;
host : integer := 0;
memtech : integer := 0;
hmstndx : integer := 0;
hslvndx : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
pirq : integer := 0;
netlist : integer := 0;
debugen : integer := 0;
hostrst : integer := 0
);
port(
rst : in std_logic;
clk : in std_logic;
pcirst : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type--;
--debug : out std_logic_vector(255 downto 0)
);
end component;
component grpci2
generic (
memtech : integer := DEFMEMTECH;
tbmemtech : integer := DEFMEMTECH;
oepol : integer := 0;
hmindex : integer := 0;
hdmindex : integer := 0;
hsindex : integer := 0;
haddr : integer := 0;
hmask : integer := 0;
ioaddr : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
irq : integer := 0;
irqmode : integer range 0 to 3 := 0;
master : integer range 0 to 1 := 1;
target : integer range 0 to 1 := 1;
dma : integer range 0 to 1 := 1;
tracebuffer : integer range 0 to 16384 := 0;
confspace : integer range 0 to 1 := 1;
vendorid : integer := 16#0000#;
deviceid : integer := 16#0000#;
classcode : integer := 16#000000#;
revisionid : integer := 16#00#;
cap_pointer : integer := 16#40#;
ext_cap_pointer : integer := 16#00#;
iobase : integer := 16#FFF#;
extcfg : integer := 16#0000000#;
bar0 : integer range 0 to 31 := 28;
bar1 : integer range 0 to 31 := 0;
bar2 : integer range 0 to 31 := 0;
bar3 : integer range 0 to 31 := 0;
bar4 : integer range 0 to 31 := 0;
bar5 : integer range 0 to 31 := 0;
bar0_map : integer := 16#000000#;
bar1_map : integer := 16#000000#;
bar2_map : integer := 16#000000#;
bar3_map : integer := 16#000000#;
bar4_map : integer := 16#000000#;
bar5_map : integer := 16#000000#;
bartype : integer range 0 to 65535 := 16#0000#;
barminsize : integer range 5 to 31 := 12;
fifo_depth : integer range 3 to 7 := 3;
fifo_count : integer range 2 to 4 := 2;
conv_endian : integer range 0 to 1 := 0; -- 1: little (PCI) <~> big (AHB), 0: big (PCI) <=> big (AHB)
deviceirq : integer range 0 to 1 := 1;
deviceirqmask : integer range 0 to 15 := 16#0#;
hostirq : integer range 0 to 1 := 1;
hostirqmask : integer range 0 to 15 := 16#0#;
nsync : integer range 0 to 2 := 2;
hostrst : integer range 0 to 2 := 0;-- 0: PCI reset is never driven, 1: PCI reset is driven from AHB reset if host, 2: PCI reset is always driven from AHB reset
bypass : integer range 0 to 1 := 1;
ft : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
debug : integer range 0 to 1 := 0;
tbapben : integer range 0 to 1 := 0;
tbpindex : integer := 0;
tbpaddr : integer := 0;
tbpmask : integer := 16#F00#;
netlist : integer range 0 to 1 := 0;
multifunc : integer range 0 to 1 := 0; -- Enables Multi-function support
multiint : integer range 0 to 1 := 0;
masters : integer := 16#FFFF#;
mf1_deviceid : integer := 16#0000#;
mf1_classcode : integer := 16#000000#;
mf1_revisionid : integer := 16#00#;
mf1_bar0 : integer range 0 to 31 := 0;
mf1_bar1 : integer range 0 to 31 := 0;
mf1_bar2 : integer range 0 to 31 := 0;
mf1_bar3 : integer range 0 to 31 := 0;
mf1_bar4 : integer range 0 to 31 := 0;
mf1_bar5 : integer range 0 to 31 := 0;
mf1_bartype : integer range 0 to 65535 := 16#0000#;
mf1_bar0_map : integer := 16#000000#;
mf1_bar1_map : integer := 16#000000#;
mf1_bar2_map : integer := 16#000000#;
mf1_bar3_map : integer := 16#000000#;
mf1_bar4_map : integer := 16#000000#;
mf1_bar5_map : integer := 16#000000#;
mf1_cap_pointer : integer := 16#40#;
mf1_ext_cap_pointer : integer := 16#00#;
mf1_extcfg : integer := 16#0000000#;
mf1_masters : integer := 16#0000#;
iotest : integer := 0);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
dirq : in std_logic_vector(3 downto 0);
pcii : in pci_in_type;
pcio : out pci_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbdmi : in ahb_mst_in_type;
ahbdmo : out ahb_mst_out_type;
ptarst : out std_logic;
tbapbi : in apb_slv_in_type := apb_slv_in_none;
tbapbo : out apb_slv_out_type;
debugo : out std_logic_vector(debug*255 downto 0)
);
end component;
constant PCI_VENDOR_ESA : integer := 16#16E3#;
constant PCI_VENDOR_GAISLER : integer := 16#1AC8#;
constant PCI_VENDOR_AEROFLEX : integer := 16#1AD0#;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1384.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01384ent IS
END c08s05b00x00p03n01i01384ent;
ARCHITECTURE c08s05b00x00p03n01i01384arch OF c08s05b00x00p03n01i01384ent IS
BEGIN
TESTING: PROCESS
type small_int is range 0 to 7;
variable v1 : small_int := 0;
BEGIN
small_int := v1; -- illegal type name target
assert FALSE
report "***FAILED TEST: c08s05b00x00p03n01i01384 - Target of a variable assignment can not be the name of a type name."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01384arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1384.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01384ent IS
END c08s05b00x00p03n01i01384ent;
ARCHITECTURE c08s05b00x00p03n01i01384arch OF c08s05b00x00p03n01i01384ent IS
BEGIN
TESTING: PROCESS
type small_int is range 0 to 7;
variable v1 : small_int := 0;
BEGIN
small_int := v1; -- illegal type name target
assert FALSE
report "***FAILED TEST: c08s05b00x00p03n01i01384 - Target of a variable assignment can not be the name of a type name."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01384arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1384.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01384ent IS
END c08s05b00x00p03n01i01384ent;
ARCHITECTURE c08s05b00x00p03n01i01384arch OF c08s05b00x00p03n01i01384ent IS
BEGIN
TESTING: PROCESS
type small_int is range 0 to 7;
variable v1 : small_int := 0;
BEGIN
small_int := v1; -- illegal type name target
assert FALSE
report "***FAILED TEST: c08s05b00x00p03n01i01384 - Target of a variable assignment can not be the name of a type name."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01384arch;
|
-- -----------------------------------------------------------------------
--
-- Turbo Chameleon 64
--
-- Multi purpose FPGA expansion for the Commodore 64 computer
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2018 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
-- I/O controller entity for the shiftregister controlling PS/2,
-- LEDs and reset signals on Turbo Chameleon 64 second edition.
--
-- -----------------------------------------------------------------------
-- clk - System clock
--
-- ser_out_clk - Serial clock, connect on toplevel to port with same name
-- ser_out_dat - Serial data, connect on toplevel to port with same name
-- ser_out_rclk - Serial strobe, connect on toplevel to port with same name
--
-- reset_c64 - Active high, pulls reset on the cartridge port
-- reset_iec - Active high, pulls reset on teh IEC connector
-- ps2_mouse_clk - Open drain output for PS/2 mouse clock (active low)
-- ps2_mouse_dat - Open drain output for PS/2 mouse data (active low)
-- ps2_keybard_clk - Open drain output for PS/2 keyboard clock (active low)
-- ps2_keybard_dat - Open drain output for PS/2 keyboard data (active low)
-- led_green - Active high, enable the green LED
-- led_red - Active high, enable the red LED
-- -----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- -----------------------------------------------------------------------
entity chameleon2_io_shiftreg is
port (
clk : in std_logic;
ser_out_clk : out std_logic;
ser_out_dat : out std_logic;
ser_out_rclk : out std_logic;
reset_c64 : in std_logic;
reset_iec : in std_logic;
ps2_mouse_clk : in std_logic;
ps2_mouse_dat : in std_logic;
ps2_keyboard_clk : in std_logic;
ps2_keyboard_dat : in std_logic;
led_green : in std_logic;
led_red : in std_logic
);
end entity;
architecture rtl of chameleon2_io_shiftreg is
signal state_reg : unsigned(6 downto 0) := (others => '0');
signal clk_reg : std_logic := '0';
signal dat_reg : std_logic := '0';
signal rclk_reg : std_logic := '1';
begin
ser_out_clk <= clk_reg;
ser_out_dat <= dat_reg;
ser_out_rclk <= rclk_reg;
process(clk)
begin
if rising_edge(clk) then
state_reg <= state_reg + 1;
clk_reg <= state_reg(2) and (not state_reg(6));
rclk_reg <= state_reg(2) and state_reg(6);
case state_reg(6 downto 3) is
when "0000" => dat_reg <= reset_c64;
when "0001" => dat_reg <= reset_iec;
when "0010" => dat_reg <= not ps2_mouse_clk;
when "0011" => dat_reg <= not ps2_mouse_dat;
when "0100" => dat_reg <= not ps2_keyboard_clk;
when "0101" => dat_reg <= not ps2_keyboard_dat;
when "0110" => dat_reg <= not led_green;
when "0111" => dat_reg <= not led_red;
when "1000" => null;
when others => state_reg <= (others => '0');
end case;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity PC is
port (
counter: in std_logic_vector(15 downto 0 );
new_counter: out std_logic_vector(15 downto 0 );
CLK: in std_logic;
RESET: in std_logic
);
end entity PC;
architecture PC_Arch of PC is
begin
--------------------------------------
--set0: syncram generic map (n =>16) port map (CLK,'0',new_count,"0000000000000000",copied_data); --clk,enable,(address to WRITE in),data to write, outputdata from selected address
process(CLK,RESET)
begin
if RESET='1' then new_counter<="0000000000000000" ; --RESET PC
end if;
if RESET='0' and CLK='1' then
new_counter <= std_logic_vector(unsigned(counter)+1);
end if;
------------------------------------------------
end process;
end architecture PC_Arch; |
entity nvc_bug is
end nvc_bug;
architecture behav of nvc_bug is
type std_logic_vector is array (integer range <>) of integer;
function to_bitvector(x : std_logic_vector) return bit_vector;
signal mode : std_logic_vector(1 downto 0);
begin
process
subtype modetype is bit_vector(mode'range);
begin
case modetype'(to_bitvector(mode)) is
when "00" =>
when "01" =>
when "10" =>
when "11" =>
when others =>
end case;
assert false report "end of test" severity note;
wait;
end process;
end behav;
|
entity nvc_bug is
end nvc_bug;
architecture behav of nvc_bug is
type std_logic_vector is array (integer range <>) of integer;
function to_bitvector(x : std_logic_vector) return bit_vector;
signal mode : std_logic_vector(1 downto 0);
begin
process
subtype modetype is bit_vector(mode'range);
begin
case modetype'(to_bitvector(mode)) is
when "00" =>
when "01" =>
when "10" =>
when "11" =>
when others =>
end case;
assert false report "end of test" severity note;
wait;
end process;
end behav;
|
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