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-------------------------------------------------------------------------------
-- axi_datamover_s2mm_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover S2MM Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_reset;
use axi_datamover_v5_1_11.axi_datamover_cmd_status;
use axi_datamover_v5_1_11.axi_datamover_scc;
use axi_datamover_v5_1_11.axi_datamover_addr_cntl;
use axi_datamover_v5_1_11.axi_datamover_wrdata_cntl;
use axi_datamover_v5_1_11.axi_datamover_wr_status_cntl;
Use axi_datamover_v5_1_11.axi_datamover_skid2mm_buf;
Use axi_datamover_v5_1_11.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_basic_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_MICRO_DMA : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- S2MM Halt request input control ---------------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------------
-- S2MM Error discrete output --------------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------------
-- Optional Command/Status Interface Clock and Reset Inputs -------
-- Only used when C_S2MM_STSCMD_IS_ASYNC = 1 --
--
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) ------------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
---------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(7 downto 0); --
s2mm_sts_wstrb : out std_logic_vector(0 downto 0); --
s2mm_sts_wlast : out std_logic; --
--------------------------------------------------------------------
-- Address posting controls ----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
--------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ---------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -----------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O -----------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
-----------------------------------------------------------------
);
end entity axi_datamover_s2mm_basic_wrap;
architecture implementation of axi_datamover_s2mm_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_wdemux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Write Strobe demux select control.
--
-------------------------------------------------------------------
function func_calc_wdemux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
end case;
Return (num_addr_bits_needed);
end function func_calc_wdemux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant S2MM_AWID_VALUE : integer range 0 to 255 := C_S2MM_AWID;
Constant S2MM_AWID_WIDTH : integer range 1 to 8 := C_S2MM_ID_WIDTH;
Constant S2MM_ADDR_WIDTH : integer range 32 to 64 := C_S2MM_ADDR_WIDTH;
Constant S2MM_MDATA_WIDTH : integer range 32 to 256 := C_S2MM_MDATA_WIDTH;
Constant S2MM_SDATA_WIDTH : integer range 8 to 256 := C_S2MM_SDATA_WIDTH;
Constant S2MM_CMD_WIDTH : integer := (C_TAG_WIDTH+C_S2MM_ADDR_WIDTH+32);
Constant S2MM_STS_WIDTH : integer := 8; -- always 8 for S2MM Basic Version
Constant INCLUDE_S2MM_STSFIFO : integer range 0 to 1 := 1;
Constant S2MM_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_S2MM_STSCMD_FIFO_DEPTH;
Constant S2MM_STSCMD_IS_ASYNC : integer range 0 to 1 := C_S2MM_STSCMD_IS_ASYNC;
Constant S2MM_BURST_SIZE : integer range 16 to 256 := 16;
Constant WR_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2;-- 2 added for going
-- full thresholding
-- in WSC
Constant SEL_ADDR_WIDTH : integer := func_calc_wdemux_sel_bits(S2MM_MDATA_WIDTH);
Constant INCLUDE_S2MM_DRE : integer range 0 to 1 := 1;
Constant OMIT_S2MM_DRE : integer range 0 to 1 := 0;
Constant OMIT_INDET_BTT : integer := 0;
Constant SF_BYTES_RCVD_WIDTH : integer := 1;
Constant ZEROS_8_BIT : std_logic_vector(7 downto 0) := (others => '0');
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_s2mm_cmd_wdata : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm_cache_data : std_logic_vector(7 downto 0) := (others => '0');
signal sig_cmd2mstr_command : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_last : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2addr_data_rdy : std_logic := '0';
signal sig_data2all_tlast_error : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2wsc_calc_error : std_logic := '0';
signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2wsc_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sig_data2wsc_cmd_empty : std_logic := '0';
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(7 downto 0) := (others => '0');
signal sig_stat2wsc_status_ready : std_logic := '0';
signal sig_wsc2stat_status_valid : std_logic := '0';
signal sig_wsc2mstr_halt_pipe : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_skid2data_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_skid2axi_wvalid : std_logic := '0';
signal sig_axi2skid_wready : std_logic := '0';
signal sig_skid2axi_wdata : std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_skid2axi_wstrb : std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_skid2axi_wlast : std_logic := '0';
signal sig_data2wsc_sof : std_logic := '0';
signal sig_data2wsc_eof : std_logic := '0';
signal sig_data2wsc_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_data2wsc_eop : std_logic := '0';
signal sig_data2wsc_bytes_rcvd : std_logic_vector(SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_wsc2rst_stop_cmplt : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_realign2wdc_eop_error : std_logic := '0';
signal skid2wdc_wvalid : std_logic := '0';
signal wdc2skid_wready : std_logic := '0';
signal skid2wdc_wdata : std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal skid2wdc_wstrb : std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal skid2wdc_wlast : std_logic := '0';
signal s2mm_awcache_int : std_logic_vector (3 downto 0);
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
begin --(architecture implementation)
-- Debug Port Assignments
s2mm_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the s2mm_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (s2mm_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"CAFE2222" ; -- 32 bit Constant indicating S2MM Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2wsc_status_ready;
sig_dbg_data_1(7) <= sig_wsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2wsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_wsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_wsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_wsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_wsc2stat_status(6) ; -- Slave Error
--sig_dbg_data_1(19) <= sig_wsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(19) <= '0' ; -- OKAY not used by TB
sig_dbg_data_1(20) <= sig_stat2wsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_wsc2stat_status_valid ; -- Status Valid Handshake
sig_dbg_data_1(29 downto 22) <= sig_mstr2data_len ; -- WDC Cmd FIFO LEN input
sig_dbg_data_1(30) <= sig_mstr2data_cmd_valid ; -- WDC Cmd FIFO Valid Inpute
sig_dbg_data_1(31) <= sig_data2mstr_cmd_ready ; -- WDC Cmd FIFO Ready Output
-- Write Data Channel I/O
s2mm_wvalid <= sig_skid2axi_wvalid;
sig_axi2skid_wready <= s2mm_wready ;
s2mm_wdata <= sig_skid2axi_wdata ;
s2mm_wstrb <= sig_skid2axi_wstrb ;
s2mm_wlast <= sig_skid2axi_wlast ;
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; -- pre Interface-X guidelines for Masters
s2mm_awuser <= "0000"; -- pre Interface-X guidelines for Masters
sig_s2mm_cache_data <= (others => '0'); --s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; --sg_ctl (3 downto 0); -- SG Cache from register
s2mm_awuser <= "0000"; --sg_ctl (7 downto 4); -- SG Cache from register
sig_s2mm_cache_data <= s2mm_cmd_wdata(79+(C_S2MM_ADDR_WIDTH-32) downto 72+(C_S2MM_ADDR_WIDTH-32));
-- sig_s2mm_cache_data <= s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Internal error output discrete
s2mm_err <= sig_calc2dm_calc_err or sig_data2all_tlast_error;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_s2mm_cmd_wdata <= s2mm_cmd_wdata(S2MM_CMD_WIDTH-1 downto 0);
-- No Realigner in S2MM Basic
sig_realign2wdc_eop_error <= '0';
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1_11.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC
)
port map (
primary_aclk => s2mm_aclk ,
primary_aresetn => s2mm_aresetn ,
secondary_awclk => s2mm_cmdsts_awclk ,
secondary_aresetn => s2mm_cmdsts_aresetn ,
halt_req => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => sig_wsc2rst_stop_cmplt ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1_11.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_S2MM_STSFIFO ,
C_STSCMD_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_STS_WIDTH => S2MM_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
secondary_awclk => s2mm_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => s2mm_cmd_wvalid ,
cmd_wready => s2mm_cmd_wready ,
cmd_wdata => sig_s2mm_cmd_wdata ,
cache_data => sig_s2mm_cache_data ,
sts_wvalid => s2mm_sts_wvalid ,
sts_wready => s2mm_sts_wready ,
sts_wdata => s2mm_sts_wdata ,
sts_wstrb => s2mm_sts_wstrb ,
sts_wlast => s2mm_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_wsc2stat_status ,
stat2mstr_status_ready => sig_stat2wsc_status_ready ,
mst2stst_status_valid => sig_wsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Write Status Controller Block
--
------------------------------------------------------------
I_WR_STATUS_CNTLR : entity axi_datamover_v5_1_11.axi_datamover_wr_status_cntl
generic map (
C_ENABLE_INDET_BTT => OMIT_INDET_BTT ,
C_SF_BYTES_RCVD_WIDTH => SF_BYTES_RCVD_WIDTH ,
C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH ,
C_STS_WIDTH => S2MM_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2wsc_stop_request => sig_rst2all_stop_request ,
wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt ,
addr2wsc_addr_posted => sig_addr2data_addr_posted ,
s2mm_bresp => s2mm_bresp ,
s2mm_bvalid => s2mm_bvalid ,
s2mm_bready => s2mm_bready ,
calc2wsc_calc_error => sig_calc2dm_calc_err ,
addr2wsc_calc_error => sig_addr2wsc_calc_error ,
addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_error => sig_data2wsc_calc_err ,
data2wsc_last_error => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
data2wsc_valid => sig_data2wsc_valid ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2stat_status => sig_wsc2stat_status ,
stat2wsc_status_ready => sig_stat2wsc_status_ready ,
wsc2stat_status_valid => sig_wsc2stat_status_valid ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_datamover_v5_1_11.axi_datamover_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_S2MM_BURST_SIZE ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1_11.axi_datamover_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => ENABLE_WAIT_FOR_DATA ,
C_ADDR_FIFO_DEPTH => WR_ADDR_CNTL_FIFO_DEPTH ,
--C_ADDR_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_ADDR_ID => S2MM_AWID_VALUE ,
C_ADDR_ID_WIDTH => S2MM_AWID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => s2mm_awid ,
addr2axi_aaddr => s2mm_awaddr ,
addr2axi_alen => s2mm_awlen ,
addr2axi_asize => s2mm_awsize ,
addr2axi_aburst => s2mm_awburst ,
addr2axi_aprot => s2mm_awprot ,
addr2axi_avalid => s2mm_awvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => s2mm_awready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => s2mm_allow_addr_req ,
addr_req_posted => s2mm_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2wsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2wsc_cmd_fifo_empty
);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_STRM_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registerd Slave Stream inputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_S2MM_STRM_SKID_BUF : entity axi_datamover_v5_1_11.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => S2MM_SDATA_WIDTH
)
port map (
-- System Ports
aclk => s2mm_aclk ,
arst => sig_mmap_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_wvalid ,
s_ready => s2mm_strm_wready ,
s_data => s2mm_strm_wdata ,
s_strb => s2mm_strm_wstrb ,
s_last => s2mm_strm_wlast ,
-- Master Side (Stream Data Output
m_valid => skid2wdc_wvalid ,
m_ready => wdc2skid_wready ,
m_data => skid2wdc_wdata ,
m_strb => skid2wdc_wstrb ,
m_last => skid2wdc_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '0' generate
begin
skid2wdc_wvalid <= s2mm_strm_wvalid;
s2mm_strm_wready <= wdc2skid_wready;
skid2wdc_wdata <= s2mm_strm_wdata;
skid2wdc_wstrb <= s2mm_strm_wstrb;
skid2wdc_wlast <= s2mm_strm_wlast;
end generate DISABLE_AXIS_SKID;
------------------------------------------------------------
-- Instance: I_WR_DATA_CNTL
--
-- Description:
-- Write Data Controller Block
--
------------------------------------------------------------
I_WR_DATA_CNTL : entity axi_datamover_v5_1_11.axi_datamover_wrdata_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => ENABLE_WAIT_FOR_DATA ,
C_REALIGNER_INCLUDED => OMIT_S2MM_DRE ,
C_ENABLE_INDET_BTT => OMIT_INDET_BTT ,
C_SF_BYTES_RCVD_WIDTH => SF_BYTES_RCVD_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
data2skid_saddr_lsb => sig_data2skid_addr_lsb ,
data2skid_wdata => sig_data2skid_wdata ,
data2skid_wstrb => sig_data2skid_wstrb ,
data2skid_wlast => sig_data2skid_wlast ,
data2skid_wvalid => sig_data2skid_wvalid ,
skid2data_wready => sig_skid2data_wready ,
s2mm_strm_wvalid => skid2wdc_wvalid ,
s2mm_strm_wready => wdc2skid_wready ,
s2mm_strm_wdata => skid2wdc_wdata ,
s2mm_strm_wstrb => skid2wdc_wstrb ,
s2mm_strm_wlast => skid2wdc_wlast ,
s2mm_strm_eop => skid2wdc_wlast ,
s2mm_stbs_asserted => ZEROS_8_BIT ,
realign2wdc_eop_error => sig_realign2wdc_eop_error ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2all_tlast_error => sig_data2all_tlast_error ,
data2all_dcntlr_halted => sig_data2all_dcntlr_halted ,
data2skid_halt => sig_data2skid_halt ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_err => sig_data2wsc_calc_err ,
data2wsc_last_err => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_valid => sig_data2wsc_valid ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_S2MM_MMAP_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registered outputs and supports bi-dir throttling.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
------------------------------------------------------------
I_S2MM_MMAP_SKID_BUF : entity axi_datamover_v5_1_11.axi_datamover_skid2mm_buf
generic map (
C_MDATA_WIDTH => S2MM_MDATA_WIDTH ,
C_SDATA_WIDTH => S2MM_SDATA_WIDTH ,
C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH
)
port map (
-- System Ports
ACLK => s2mm_aclk ,
ARST => sig_stream_rst ,
-- Slave Side (Wr Data Controller Input Side )
S_ADDR_LSB => sig_data2skid_addr_lsb,
S_VALID => sig_data2skid_wvalid ,
S_READY => sig_skid2data_wready ,
S_Data => sig_data2skid_wdata ,
S_STRB => sig_data2skid_wstrb ,
S_Last => sig_data2skid_wlast ,
-- Master Side (MMap Write Data Output Side)
M_VALID => sig_skid2axi_wvalid ,
M_READY => sig_axi2skid_wready ,
M_Data => sig_skid2axi_wdata ,
M_STRB => sig_skid2axi_wstrb ,
M_Last => sig_skid2axi_wlast
);
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover S2MM Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_reset;
use axi_datamover_v5_1_11.axi_datamover_cmd_status;
use axi_datamover_v5_1_11.axi_datamover_scc;
use axi_datamover_v5_1_11.axi_datamover_addr_cntl;
use axi_datamover_v5_1_11.axi_datamover_wrdata_cntl;
use axi_datamover_v5_1_11.axi_datamover_wr_status_cntl;
Use axi_datamover_v5_1_11.axi_datamover_skid2mm_buf;
Use axi_datamover_v5_1_11.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_basic_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_MICRO_DMA : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- S2MM Halt request input control ---------------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------------
-- S2MM Error discrete output --------------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------------
-- Optional Command/Status Interface Clock and Reset Inputs -------
-- Only used when C_S2MM_STSCMD_IS_ASYNC = 1 --
--
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) ------------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
---------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(7 downto 0); --
s2mm_sts_wstrb : out std_logic_vector(0 downto 0); --
s2mm_sts_wlast : out std_logic; --
--------------------------------------------------------------------
-- Address posting controls ----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
--------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ---------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -----------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O -----------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
-----------------------------------------------------------------
);
end entity axi_datamover_s2mm_basic_wrap;
architecture implementation of axi_datamover_s2mm_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_wdemux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Write Strobe demux select control.
--
-------------------------------------------------------------------
function func_calc_wdemux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
end case;
Return (num_addr_bits_needed);
end function func_calc_wdemux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant S2MM_AWID_VALUE : integer range 0 to 255 := C_S2MM_AWID;
Constant S2MM_AWID_WIDTH : integer range 1 to 8 := C_S2MM_ID_WIDTH;
Constant S2MM_ADDR_WIDTH : integer range 32 to 64 := C_S2MM_ADDR_WIDTH;
Constant S2MM_MDATA_WIDTH : integer range 32 to 256 := C_S2MM_MDATA_WIDTH;
Constant S2MM_SDATA_WIDTH : integer range 8 to 256 := C_S2MM_SDATA_WIDTH;
Constant S2MM_CMD_WIDTH : integer := (C_TAG_WIDTH+C_S2MM_ADDR_WIDTH+32);
Constant S2MM_STS_WIDTH : integer := 8; -- always 8 for S2MM Basic Version
Constant INCLUDE_S2MM_STSFIFO : integer range 0 to 1 := 1;
Constant S2MM_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_S2MM_STSCMD_FIFO_DEPTH;
Constant S2MM_STSCMD_IS_ASYNC : integer range 0 to 1 := C_S2MM_STSCMD_IS_ASYNC;
Constant S2MM_BURST_SIZE : integer range 16 to 256 := 16;
Constant WR_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2;-- 2 added for going
-- full thresholding
-- in WSC
Constant SEL_ADDR_WIDTH : integer := func_calc_wdemux_sel_bits(S2MM_MDATA_WIDTH);
Constant INCLUDE_S2MM_DRE : integer range 0 to 1 := 1;
Constant OMIT_S2MM_DRE : integer range 0 to 1 := 0;
Constant OMIT_INDET_BTT : integer := 0;
Constant SF_BYTES_RCVD_WIDTH : integer := 1;
Constant ZEROS_8_BIT : std_logic_vector(7 downto 0) := (others => '0');
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_s2mm_cmd_wdata : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm_cache_data : std_logic_vector(7 downto 0) := (others => '0');
signal sig_cmd2mstr_command : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_last : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2addr_data_rdy : std_logic := '0';
signal sig_data2all_tlast_error : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2wsc_calc_error : std_logic := '0';
signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2wsc_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sig_data2wsc_cmd_empty : std_logic := '0';
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(7 downto 0) := (others => '0');
signal sig_stat2wsc_status_ready : std_logic := '0';
signal sig_wsc2stat_status_valid : std_logic := '0';
signal sig_wsc2mstr_halt_pipe : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_skid2data_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_skid2axi_wvalid : std_logic := '0';
signal sig_axi2skid_wready : std_logic := '0';
signal sig_skid2axi_wdata : std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_skid2axi_wstrb : std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_skid2axi_wlast : std_logic := '0';
signal sig_data2wsc_sof : std_logic := '0';
signal sig_data2wsc_eof : std_logic := '0';
signal sig_data2wsc_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_data2wsc_eop : std_logic := '0';
signal sig_data2wsc_bytes_rcvd : std_logic_vector(SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_wsc2rst_stop_cmplt : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_realign2wdc_eop_error : std_logic := '0';
signal skid2wdc_wvalid : std_logic := '0';
signal wdc2skid_wready : std_logic := '0';
signal skid2wdc_wdata : std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal skid2wdc_wstrb : std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal skid2wdc_wlast : std_logic := '0';
signal s2mm_awcache_int : std_logic_vector (3 downto 0);
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
begin --(architecture implementation)
-- Debug Port Assignments
s2mm_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the s2mm_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (s2mm_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"CAFE2222" ; -- 32 bit Constant indicating S2MM Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2wsc_status_ready;
sig_dbg_data_1(7) <= sig_wsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2wsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_wsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_wsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_wsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_wsc2stat_status(6) ; -- Slave Error
--sig_dbg_data_1(19) <= sig_wsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(19) <= '0' ; -- OKAY not used by TB
sig_dbg_data_1(20) <= sig_stat2wsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_wsc2stat_status_valid ; -- Status Valid Handshake
sig_dbg_data_1(29 downto 22) <= sig_mstr2data_len ; -- WDC Cmd FIFO LEN input
sig_dbg_data_1(30) <= sig_mstr2data_cmd_valid ; -- WDC Cmd FIFO Valid Inpute
sig_dbg_data_1(31) <= sig_data2mstr_cmd_ready ; -- WDC Cmd FIFO Ready Output
-- Write Data Channel I/O
s2mm_wvalid <= sig_skid2axi_wvalid;
sig_axi2skid_wready <= s2mm_wready ;
s2mm_wdata <= sig_skid2axi_wdata ;
s2mm_wstrb <= sig_skid2axi_wstrb ;
s2mm_wlast <= sig_skid2axi_wlast ;
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; -- pre Interface-X guidelines for Masters
s2mm_awuser <= "0000"; -- pre Interface-X guidelines for Masters
sig_s2mm_cache_data <= (others => '0'); --s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; --sg_ctl (3 downto 0); -- SG Cache from register
s2mm_awuser <= "0000"; --sg_ctl (7 downto 4); -- SG Cache from register
sig_s2mm_cache_data <= s2mm_cmd_wdata(79+(C_S2MM_ADDR_WIDTH-32) downto 72+(C_S2MM_ADDR_WIDTH-32));
-- sig_s2mm_cache_data <= s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Internal error output discrete
s2mm_err <= sig_calc2dm_calc_err or sig_data2all_tlast_error;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_s2mm_cmd_wdata <= s2mm_cmd_wdata(S2MM_CMD_WIDTH-1 downto 0);
-- No Realigner in S2MM Basic
sig_realign2wdc_eop_error <= '0';
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1_11.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC
)
port map (
primary_aclk => s2mm_aclk ,
primary_aresetn => s2mm_aresetn ,
secondary_awclk => s2mm_cmdsts_awclk ,
secondary_aresetn => s2mm_cmdsts_aresetn ,
halt_req => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => sig_wsc2rst_stop_cmplt ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1_11.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_S2MM_STSFIFO ,
C_STSCMD_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_STS_WIDTH => S2MM_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
secondary_awclk => s2mm_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => s2mm_cmd_wvalid ,
cmd_wready => s2mm_cmd_wready ,
cmd_wdata => sig_s2mm_cmd_wdata ,
cache_data => sig_s2mm_cache_data ,
sts_wvalid => s2mm_sts_wvalid ,
sts_wready => s2mm_sts_wready ,
sts_wdata => s2mm_sts_wdata ,
sts_wstrb => s2mm_sts_wstrb ,
sts_wlast => s2mm_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_wsc2stat_status ,
stat2mstr_status_ready => sig_stat2wsc_status_ready ,
mst2stst_status_valid => sig_wsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Write Status Controller Block
--
------------------------------------------------------------
I_WR_STATUS_CNTLR : entity axi_datamover_v5_1_11.axi_datamover_wr_status_cntl
generic map (
C_ENABLE_INDET_BTT => OMIT_INDET_BTT ,
C_SF_BYTES_RCVD_WIDTH => SF_BYTES_RCVD_WIDTH ,
C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH ,
C_STS_WIDTH => S2MM_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2wsc_stop_request => sig_rst2all_stop_request ,
wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt ,
addr2wsc_addr_posted => sig_addr2data_addr_posted ,
s2mm_bresp => s2mm_bresp ,
s2mm_bvalid => s2mm_bvalid ,
s2mm_bready => s2mm_bready ,
calc2wsc_calc_error => sig_calc2dm_calc_err ,
addr2wsc_calc_error => sig_addr2wsc_calc_error ,
addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_error => sig_data2wsc_calc_err ,
data2wsc_last_error => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
data2wsc_valid => sig_data2wsc_valid ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2stat_status => sig_wsc2stat_status ,
stat2wsc_status_ready => sig_stat2wsc_status_ready ,
wsc2stat_status_valid => sig_wsc2stat_status_valid ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_datamover_v5_1_11.axi_datamover_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_S2MM_BURST_SIZE ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1_11.axi_datamover_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => ENABLE_WAIT_FOR_DATA ,
C_ADDR_FIFO_DEPTH => WR_ADDR_CNTL_FIFO_DEPTH ,
--C_ADDR_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_ADDR_ID => S2MM_AWID_VALUE ,
C_ADDR_ID_WIDTH => S2MM_AWID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => s2mm_awid ,
addr2axi_aaddr => s2mm_awaddr ,
addr2axi_alen => s2mm_awlen ,
addr2axi_asize => s2mm_awsize ,
addr2axi_aburst => s2mm_awburst ,
addr2axi_aprot => s2mm_awprot ,
addr2axi_avalid => s2mm_awvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => s2mm_awready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => s2mm_allow_addr_req ,
addr_req_posted => s2mm_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2wsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2wsc_cmd_fifo_empty
);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_STRM_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registerd Slave Stream inputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_S2MM_STRM_SKID_BUF : entity axi_datamover_v5_1_11.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => S2MM_SDATA_WIDTH
)
port map (
-- System Ports
aclk => s2mm_aclk ,
arst => sig_mmap_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_wvalid ,
s_ready => s2mm_strm_wready ,
s_data => s2mm_strm_wdata ,
s_strb => s2mm_strm_wstrb ,
s_last => s2mm_strm_wlast ,
-- Master Side (Stream Data Output
m_valid => skid2wdc_wvalid ,
m_ready => wdc2skid_wready ,
m_data => skid2wdc_wdata ,
m_strb => skid2wdc_wstrb ,
m_last => skid2wdc_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '0' generate
begin
skid2wdc_wvalid <= s2mm_strm_wvalid;
s2mm_strm_wready <= wdc2skid_wready;
skid2wdc_wdata <= s2mm_strm_wdata;
skid2wdc_wstrb <= s2mm_strm_wstrb;
skid2wdc_wlast <= s2mm_strm_wlast;
end generate DISABLE_AXIS_SKID;
------------------------------------------------------------
-- Instance: I_WR_DATA_CNTL
--
-- Description:
-- Write Data Controller Block
--
------------------------------------------------------------
I_WR_DATA_CNTL : entity axi_datamover_v5_1_11.axi_datamover_wrdata_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => ENABLE_WAIT_FOR_DATA ,
C_REALIGNER_INCLUDED => OMIT_S2MM_DRE ,
C_ENABLE_INDET_BTT => OMIT_INDET_BTT ,
C_SF_BYTES_RCVD_WIDTH => SF_BYTES_RCVD_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
data2skid_saddr_lsb => sig_data2skid_addr_lsb ,
data2skid_wdata => sig_data2skid_wdata ,
data2skid_wstrb => sig_data2skid_wstrb ,
data2skid_wlast => sig_data2skid_wlast ,
data2skid_wvalid => sig_data2skid_wvalid ,
skid2data_wready => sig_skid2data_wready ,
s2mm_strm_wvalid => skid2wdc_wvalid ,
s2mm_strm_wready => wdc2skid_wready ,
s2mm_strm_wdata => skid2wdc_wdata ,
s2mm_strm_wstrb => skid2wdc_wstrb ,
s2mm_strm_wlast => skid2wdc_wlast ,
s2mm_strm_eop => skid2wdc_wlast ,
s2mm_stbs_asserted => ZEROS_8_BIT ,
realign2wdc_eop_error => sig_realign2wdc_eop_error ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2all_tlast_error => sig_data2all_tlast_error ,
data2all_dcntlr_halted => sig_data2all_dcntlr_halted ,
data2skid_halt => sig_data2skid_halt ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_err => sig_data2wsc_calc_err ,
data2wsc_last_err => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_valid => sig_data2wsc_valid ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_S2MM_MMAP_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registered outputs and supports bi-dir throttling.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
------------------------------------------------------------
I_S2MM_MMAP_SKID_BUF : entity axi_datamover_v5_1_11.axi_datamover_skid2mm_buf
generic map (
C_MDATA_WIDTH => S2MM_MDATA_WIDTH ,
C_SDATA_WIDTH => S2MM_SDATA_WIDTH ,
C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH
)
port map (
-- System Ports
ACLK => s2mm_aclk ,
ARST => sig_stream_rst ,
-- Slave Side (Wr Data Controller Input Side )
S_ADDR_LSB => sig_data2skid_addr_lsb,
S_VALID => sig_data2skid_wvalid ,
S_READY => sig_skid2data_wready ,
S_Data => sig_data2skid_wdata ,
S_STRB => sig_data2skid_wstrb ,
S_Last => sig_data2skid_wlast ,
-- Master Side (MMap Write Data Output Side)
M_VALID => sig_skid2axi_wvalid ,
M_READY => sig_axi2skid_wready ,
M_Data => sig_skid2axi_wdata ,
M_STRB => sig_skid2axi_wstrb ,
M_Last => sig_skid2axi_wlast
);
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover S2MM Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_reset;
use axi_datamover_v5_1_11.axi_datamover_cmd_status;
use axi_datamover_v5_1_11.axi_datamover_scc;
use axi_datamover_v5_1_11.axi_datamover_addr_cntl;
use axi_datamover_v5_1_11.axi_datamover_wrdata_cntl;
use axi_datamover_v5_1_11.axi_datamover_wr_status_cntl;
Use axi_datamover_v5_1_11.axi_datamover_skid2mm_buf;
Use axi_datamover_v5_1_11.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_basic_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_MICRO_DMA : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- S2MM Halt request input control ---------------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------------
-- S2MM Error discrete output --------------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------------
-- Optional Command/Status Interface Clock and Reset Inputs -------
-- Only used when C_S2MM_STSCMD_IS_ASYNC = 1 --
--
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) ------------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
---------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(7 downto 0); --
s2mm_sts_wstrb : out std_logic_vector(0 downto 0); --
s2mm_sts_wlast : out std_logic; --
--------------------------------------------------------------------
-- Address posting controls ----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
--------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ---------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -----------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O -----------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
-----------------------------------------------------------------
);
end entity axi_datamover_s2mm_basic_wrap;
architecture implementation of axi_datamover_s2mm_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_wdemux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Write Strobe demux select control.
--
-------------------------------------------------------------------
function func_calc_wdemux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
end case;
Return (num_addr_bits_needed);
end function func_calc_wdemux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant S2MM_AWID_VALUE : integer range 0 to 255 := C_S2MM_AWID;
Constant S2MM_AWID_WIDTH : integer range 1 to 8 := C_S2MM_ID_WIDTH;
Constant S2MM_ADDR_WIDTH : integer range 32 to 64 := C_S2MM_ADDR_WIDTH;
Constant S2MM_MDATA_WIDTH : integer range 32 to 256 := C_S2MM_MDATA_WIDTH;
Constant S2MM_SDATA_WIDTH : integer range 8 to 256 := C_S2MM_SDATA_WIDTH;
Constant S2MM_CMD_WIDTH : integer := (C_TAG_WIDTH+C_S2MM_ADDR_WIDTH+32);
Constant S2MM_STS_WIDTH : integer := 8; -- always 8 for S2MM Basic Version
Constant INCLUDE_S2MM_STSFIFO : integer range 0 to 1 := 1;
Constant S2MM_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_S2MM_STSCMD_FIFO_DEPTH;
Constant S2MM_STSCMD_IS_ASYNC : integer range 0 to 1 := C_S2MM_STSCMD_IS_ASYNC;
Constant S2MM_BURST_SIZE : integer range 16 to 256 := 16;
Constant WR_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2;-- 2 added for going
-- full thresholding
-- in WSC
Constant SEL_ADDR_WIDTH : integer := func_calc_wdemux_sel_bits(S2MM_MDATA_WIDTH);
Constant INCLUDE_S2MM_DRE : integer range 0 to 1 := 1;
Constant OMIT_S2MM_DRE : integer range 0 to 1 := 0;
Constant OMIT_INDET_BTT : integer := 0;
Constant SF_BYTES_RCVD_WIDTH : integer := 1;
Constant ZEROS_8_BIT : std_logic_vector(7 downto 0) := (others => '0');
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_s2mm_cmd_wdata : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm_cache_data : std_logic_vector(7 downto 0) := (others => '0');
signal sig_cmd2mstr_command : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_last : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2addr_data_rdy : std_logic := '0';
signal sig_data2all_tlast_error : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2wsc_calc_error : std_logic := '0';
signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2wsc_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sig_data2wsc_cmd_empty : std_logic := '0';
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(7 downto 0) := (others => '0');
signal sig_stat2wsc_status_ready : std_logic := '0';
signal sig_wsc2stat_status_valid : std_logic := '0';
signal sig_wsc2mstr_halt_pipe : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_skid2data_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_skid2axi_wvalid : std_logic := '0';
signal sig_axi2skid_wready : std_logic := '0';
signal sig_skid2axi_wdata : std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_skid2axi_wstrb : std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_skid2axi_wlast : std_logic := '0';
signal sig_data2wsc_sof : std_logic := '0';
signal sig_data2wsc_eof : std_logic := '0';
signal sig_data2wsc_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_data2wsc_eop : std_logic := '0';
signal sig_data2wsc_bytes_rcvd : std_logic_vector(SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_wsc2rst_stop_cmplt : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_realign2wdc_eop_error : std_logic := '0';
signal skid2wdc_wvalid : std_logic := '0';
signal wdc2skid_wready : std_logic := '0';
signal skid2wdc_wdata : std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal skid2wdc_wstrb : std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal skid2wdc_wlast : std_logic := '0';
signal s2mm_awcache_int : std_logic_vector (3 downto 0);
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
begin --(architecture implementation)
-- Debug Port Assignments
s2mm_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the s2mm_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (s2mm_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"CAFE2222" ; -- 32 bit Constant indicating S2MM Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2wsc_status_ready;
sig_dbg_data_1(7) <= sig_wsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2wsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_wsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_wsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_wsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_wsc2stat_status(6) ; -- Slave Error
--sig_dbg_data_1(19) <= sig_wsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(19) <= '0' ; -- OKAY not used by TB
sig_dbg_data_1(20) <= sig_stat2wsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_wsc2stat_status_valid ; -- Status Valid Handshake
sig_dbg_data_1(29 downto 22) <= sig_mstr2data_len ; -- WDC Cmd FIFO LEN input
sig_dbg_data_1(30) <= sig_mstr2data_cmd_valid ; -- WDC Cmd FIFO Valid Inpute
sig_dbg_data_1(31) <= sig_data2mstr_cmd_ready ; -- WDC Cmd FIFO Ready Output
-- Write Data Channel I/O
s2mm_wvalid <= sig_skid2axi_wvalid;
sig_axi2skid_wready <= s2mm_wready ;
s2mm_wdata <= sig_skid2axi_wdata ;
s2mm_wstrb <= sig_skid2axi_wstrb ;
s2mm_wlast <= sig_skid2axi_wlast ;
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; -- pre Interface-X guidelines for Masters
s2mm_awuser <= "0000"; -- pre Interface-X guidelines for Masters
sig_s2mm_cache_data <= (others => '0'); --s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; --sg_ctl (3 downto 0); -- SG Cache from register
s2mm_awuser <= "0000"; --sg_ctl (7 downto 4); -- SG Cache from register
sig_s2mm_cache_data <= s2mm_cmd_wdata(79+(C_S2MM_ADDR_WIDTH-32) downto 72+(C_S2MM_ADDR_WIDTH-32));
-- sig_s2mm_cache_data <= s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Internal error output discrete
s2mm_err <= sig_calc2dm_calc_err or sig_data2all_tlast_error;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_s2mm_cmd_wdata <= s2mm_cmd_wdata(S2MM_CMD_WIDTH-1 downto 0);
-- No Realigner in S2MM Basic
sig_realign2wdc_eop_error <= '0';
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1_11.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC
)
port map (
primary_aclk => s2mm_aclk ,
primary_aresetn => s2mm_aresetn ,
secondary_awclk => s2mm_cmdsts_awclk ,
secondary_aresetn => s2mm_cmdsts_aresetn ,
halt_req => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => sig_wsc2rst_stop_cmplt ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1_11.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_S2MM_STSFIFO ,
C_STSCMD_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_STS_WIDTH => S2MM_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
secondary_awclk => s2mm_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => s2mm_cmd_wvalid ,
cmd_wready => s2mm_cmd_wready ,
cmd_wdata => sig_s2mm_cmd_wdata ,
cache_data => sig_s2mm_cache_data ,
sts_wvalid => s2mm_sts_wvalid ,
sts_wready => s2mm_sts_wready ,
sts_wdata => s2mm_sts_wdata ,
sts_wstrb => s2mm_sts_wstrb ,
sts_wlast => s2mm_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_wsc2stat_status ,
stat2mstr_status_ready => sig_stat2wsc_status_ready ,
mst2stst_status_valid => sig_wsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Write Status Controller Block
--
------------------------------------------------------------
I_WR_STATUS_CNTLR : entity axi_datamover_v5_1_11.axi_datamover_wr_status_cntl
generic map (
C_ENABLE_INDET_BTT => OMIT_INDET_BTT ,
C_SF_BYTES_RCVD_WIDTH => SF_BYTES_RCVD_WIDTH ,
C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH ,
C_STS_WIDTH => S2MM_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2wsc_stop_request => sig_rst2all_stop_request ,
wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt ,
addr2wsc_addr_posted => sig_addr2data_addr_posted ,
s2mm_bresp => s2mm_bresp ,
s2mm_bvalid => s2mm_bvalid ,
s2mm_bready => s2mm_bready ,
calc2wsc_calc_error => sig_calc2dm_calc_err ,
addr2wsc_calc_error => sig_addr2wsc_calc_error ,
addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_error => sig_data2wsc_calc_err ,
data2wsc_last_error => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
data2wsc_valid => sig_data2wsc_valid ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2stat_status => sig_wsc2stat_status ,
stat2wsc_status_ready => sig_stat2wsc_status_ready ,
wsc2stat_status_valid => sig_wsc2stat_status_valid ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_datamover_v5_1_11.axi_datamover_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_S2MM_BURST_SIZE ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1_11.axi_datamover_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => ENABLE_WAIT_FOR_DATA ,
C_ADDR_FIFO_DEPTH => WR_ADDR_CNTL_FIFO_DEPTH ,
--C_ADDR_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_ADDR_ID => S2MM_AWID_VALUE ,
C_ADDR_ID_WIDTH => S2MM_AWID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => s2mm_awid ,
addr2axi_aaddr => s2mm_awaddr ,
addr2axi_alen => s2mm_awlen ,
addr2axi_asize => s2mm_awsize ,
addr2axi_aburst => s2mm_awburst ,
addr2axi_aprot => s2mm_awprot ,
addr2axi_avalid => s2mm_awvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => s2mm_awready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => s2mm_allow_addr_req ,
addr_req_posted => s2mm_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2wsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2wsc_cmd_fifo_empty
);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_STRM_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registerd Slave Stream inputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_S2MM_STRM_SKID_BUF : entity axi_datamover_v5_1_11.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => S2MM_SDATA_WIDTH
)
port map (
-- System Ports
aclk => s2mm_aclk ,
arst => sig_mmap_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_wvalid ,
s_ready => s2mm_strm_wready ,
s_data => s2mm_strm_wdata ,
s_strb => s2mm_strm_wstrb ,
s_last => s2mm_strm_wlast ,
-- Master Side (Stream Data Output
m_valid => skid2wdc_wvalid ,
m_ready => wdc2skid_wready ,
m_data => skid2wdc_wdata ,
m_strb => skid2wdc_wstrb ,
m_last => skid2wdc_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '0' generate
begin
skid2wdc_wvalid <= s2mm_strm_wvalid;
s2mm_strm_wready <= wdc2skid_wready;
skid2wdc_wdata <= s2mm_strm_wdata;
skid2wdc_wstrb <= s2mm_strm_wstrb;
skid2wdc_wlast <= s2mm_strm_wlast;
end generate DISABLE_AXIS_SKID;
------------------------------------------------------------
-- Instance: I_WR_DATA_CNTL
--
-- Description:
-- Write Data Controller Block
--
------------------------------------------------------------
I_WR_DATA_CNTL : entity axi_datamover_v5_1_11.axi_datamover_wrdata_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => ENABLE_WAIT_FOR_DATA ,
C_REALIGNER_INCLUDED => OMIT_S2MM_DRE ,
C_ENABLE_INDET_BTT => OMIT_INDET_BTT ,
C_SF_BYTES_RCVD_WIDTH => SF_BYTES_RCVD_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
data2skid_saddr_lsb => sig_data2skid_addr_lsb ,
data2skid_wdata => sig_data2skid_wdata ,
data2skid_wstrb => sig_data2skid_wstrb ,
data2skid_wlast => sig_data2skid_wlast ,
data2skid_wvalid => sig_data2skid_wvalid ,
skid2data_wready => sig_skid2data_wready ,
s2mm_strm_wvalid => skid2wdc_wvalid ,
s2mm_strm_wready => wdc2skid_wready ,
s2mm_strm_wdata => skid2wdc_wdata ,
s2mm_strm_wstrb => skid2wdc_wstrb ,
s2mm_strm_wlast => skid2wdc_wlast ,
s2mm_strm_eop => skid2wdc_wlast ,
s2mm_stbs_asserted => ZEROS_8_BIT ,
realign2wdc_eop_error => sig_realign2wdc_eop_error ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2all_tlast_error => sig_data2all_tlast_error ,
data2all_dcntlr_halted => sig_data2all_dcntlr_halted ,
data2skid_halt => sig_data2skid_halt ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_err => sig_data2wsc_calc_err ,
data2wsc_last_err => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_valid => sig_data2wsc_valid ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_S2MM_MMAP_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registered outputs and supports bi-dir throttling.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
------------------------------------------------------------
I_S2MM_MMAP_SKID_BUF : entity axi_datamover_v5_1_11.axi_datamover_skid2mm_buf
generic map (
C_MDATA_WIDTH => S2MM_MDATA_WIDTH ,
C_SDATA_WIDTH => S2MM_SDATA_WIDTH ,
C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH
)
port map (
-- System Ports
ACLK => s2mm_aclk ,
ARST => sig_stream_rst ,
-- Slave Side (Wr Data Controller Input Side )
S_ADDR_LSB => sig_data2skid_addr_lsb,
S_VALID => sig_data2skid_wvalid ,
S_READY => sig_skid2data_wready ,
S_Data => sig_data2skid_wdata ,
S_STRB => sig_data2skid_wstrb ,
S_Last => sig_data2skid_wlast ,
-- Master Side (MMap Write Data Output Side)
M_VALID => sig_skid2axi_wvalid ,
M_READY => sig_axi2skid_wready ,
M_Data => sig_skid2axi_wdata ,
M_STRB => sig_skid2axi_wstrb ,
M_Last => sig_skid2axi_wlast
);
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover S2MM Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_reset;
use axi_datamover_v5_1_11.axi_datamover_cmd_status;
use axi_datamover_v5_1_11.axi_datamover_scc;
use axi_datamover_v5_1_11.axi_datamover_addr_cntl;
use axi_datamover_v5_1_11.axi_datamover_wrdata_cntl;
use axi_datamover_v5_1_11.axi_datamover_wr_status_cntl;
Use axi_datamover_v5_1_11.axi_datamover_skid2mm_buf;
Use axi_datamover_v5_1_11.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_basic_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_MICRO_DMA : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- S2MM Halt request input control ---------------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------------
-- S2MM Error discrete output --------------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------------
-- Optional Command/Status Interface Clock and Reset Inputs -------
-- Only used when C_S2MM_STSCMD_IS_ASYNC = 1 --
--
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) ------------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
---------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(7 downto 0); --
s2mm_sts_wstrb : out std_logic_vector(0 downto 0); --
s2mm_sts_wlast : out std_logic; --
--------------------------------------------------------------------
-- Address posting controls ----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
--------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ---------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -----------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O -----------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
-----------------------------------------------------------------
);
end entity axi_datamover_s2mm_basic_wrap;
architecture implementation of axi_datamover_s2mm_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_wdemux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Write Strobe demux select control.
--
-------------------------------------------------------------------
function func_calc_wdemux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
end case;
Return (num_addr_bits_needed);
end function func_calc_wdemux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant S2MM_AWID_VALUE : integer range 0 to 255 := C_S2MM_AWID;
Constant S2MM_AWID_WIDTH : integer range 1 to 8 := C_S2MM_ID_WIDTH;
Constant S2MM_ADDR_WIDTH : integer range 32 to 64 := C_S2MM_ADDR_WIDTH;
Constant S2MM_MDATA_WIDTH : integer range 32 to 256 := C_S2MM_MDATA_WIDTH;
Constant S2MM_SDATA_WIDTH : integer range 8 to 256 := C_S2MM_SDATA_WIDTH;
Constant S2MM_CMD_WIDTH : integer := (C_TAG_WIDTH+C_S2MM_ADDR_WIDTH+32);
Constant S2MM_STS_WIDTH : integer := 8; -- always 8 for S2MM Basic Version
Constant INCLUDE_S2MM_STSFIFO : integer range 0 to 1 := 1;
Constant S2MM_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_S2MM_STSCMD_FIFO_DEPTH;
Constant S2MM_STSCMD_IS_ASYNC : integer range 0 to 1 := C_S2MM_STSCMD_IS_ASYNC;
Constant S2MM_BURST_SIZE : integer range 16 to 256 := 16;
Constant WR_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2;-- 2 added for going
-- full thresholding
-- in WSC
Constant SEL_ADDR_WIDTH : integer := func_calc_wdemux_sel_bits(S2MM_MDATA_WIDTH);
Constant INCLUDE_S2MM_DRE : integer range 0 to 1 := 1;
Constant OMIT_S2MM_DRE : integer range 0 to 1 := 0;
Constant OMIT_INDET_BTT : integer := 0;
Constant SF_BYTES_RCVD_WIDTH : integer := 1;
Constant ZEROS_8_BIT : std_logic_vector(7 downto 0) := (others => '0');
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_s2mm_cmd_wdata : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm_cache_data : std_logic_vector(7 downto 0) := (others => '0');
signal sig_cmd2mstr_command : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_last : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2addr_data_rdy : std_logic := '0';
signal sig_data2all_tlast_error : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2wsc_calc_error : std_logic := '0';
signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2wsc_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sig_data2wsc_cmd_empty : std_logic := '0';
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(7 downto 0) := (others => '0');
signal sig_stat2wsc_status_ready : std_logic := '0';
signal sig_wsc2stat_status_valid : std_logic := '0';
signal sig_wsc2mstr_halt_pipe : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_skid2data_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_skid2axi_wvalid : std_logic := '0';
signal sig_axi2skid_wready : std_logic := '0';
signal sig_skid2axi_wdata : std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_skid2axi_wstrb : std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_skid2axi_wlast : std_logic := '0';
signal sig_data2wsc_sof : std_logic := '0';
signal sig_data2wsc_eof : std_logic := '0';
signal sig_data2wsc_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_data2wsc_eop : std_logic := '0';
signal sig_data2wsc_bytes_rcvd : std_logic_vector(SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_wsc2rst_stop_cmplt : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_realign2wdc_eop_error : std_logic := '0';
signal skid2wdc_wvalid : std_logic := '0';
signal wdc2skid_wready : std_logic := '0';
signal skid2wdc_wdata : std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal skid2wdc_wstrb : std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal skid2wdc_wlast : std_logic := '0';
signal s2mm_awcache_int : std_logic_vector (3 downto 0);
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
begin --(architecture implementation)
-- Debug Port Assignments
s2mm_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the s2mm_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (s2mm_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"CAFE2222" ; -- 32 bit Constant indicating S2MM Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2wsc_status_ready;
sig_dbg_data_1(7) <= sig_wsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2wsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_wsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_wsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_wsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_wsc2stat_status(6) ; -- Slave Error
--sig_dbg_data_1(19) <= sig_wsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(19) <= '0' ; -- OKAY not used by TB
sig_dbg_data_1(20) <= sig_stat2wsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_wsc2stat_status_valid ; -- Status Valid Handshake
sig_dbg_data_1(29 downto 22) <= sig_mstr2data_len ; -- WDC Cmd FIFO LEN input
sig_dbg_data_1(30) <= sig_mstr2data_cmd_valid ; -- WDC Cmd FIFO Valid Inpute
sig_dbg_data_1(31) <= sig_data2mstr_cmd_ready ; -- WDC Cmd FIFO Ready Output
-- Write Data Channel I/O
s2mm_wvalid <= sig_skid2axi_wvalid;
sig_axi2skid_wready <= s2mm_wready ;
s2mm_wdata <= sig_skid2axi_wdata ;
s2mm_wstrb <= sig_skid2axi_wstrb ;
s2mm_wlast <= sig_skid2axi_wlast ;
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; -- pre Interface-X guidelines for Masters
s2mm_awuser <= "0000"; -- pre Interface-X guidelines for Masters
sig_s2mm_cache_data <= (others => '0'); --s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; --sg_ctl (3 downto 0); -- SG Cache from register
s2mm_awuser <= "0000"; --sg_ctl (7 downto 4); -- SG Cache from register
sig_s2mm_cache_data <= s2mm_cmd_wdata(79+(C_S2MM_ADDR_WIDTH-32) downto 72+(C_S2MM_ADDR_WIDTH-32));
-- sig_s2mm_cache_data <= s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Internal error output discrete
s2mm_err <= sig_calc2dm_calc_err or sig_data2all_tlast_error;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_s2mm_cmd_wdata <= s2mm_cmd_wdata(S2MM_CMD_WIDTH-1 downto 0);
-- No Realigner in S2MM Basic
sig_realign2wdc_eop_error <= '0';
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1_11.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC
)
port map (
primary_aclk => s2mm_aclk ,
primary_aresetn => s2mm_aresetn ,
secondary_awclk => s2mm_cmdsts_awclk ,
secondary_aresetn => s2mm_cmdsts_aresetn ,
halt_req => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => sig_wsc2rst_stop_cmplt ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1_11.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_S2MM_STSFIFO ,
C_STSCMD_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_STS_WIDTH => S2MM_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
secondary_awclk => s2mm_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => s2mm_cmd_wvalid ,
cmd_wready => s2mm_cmd_wready ,
cmd_wdata => sig_s2mm_cmd_wdata ,
cache_data => sig_s2mm_cache_data ,
sts_wvalid => s2mm_sts_wvalid ,
sts_wready => s2mm_sts_wready ,
sts_wdata => s2mm_sts_wdata ,
sts_wstrb => s2mm_sts_wstrb ,
sts_wlast => s2mm_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_wsc2stat_status ,
stat2mstr_status_ready => sig_stat2wsc_status_ready ,
mst2stst_status_valid => sig_wsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Write Status Controller Block
--
------------------------------------------------------------
I_WR_STATUS_CNTLR : entity axi_datamover_v5_1_11.axi_datamover_wr_status_cntl
generic map (
C_ENABLE_INDET_BTT => OMIT_INDET_BTT ,
C_SF_BYTES_RCVD_WIDTH => SF_BYTES_RCVD_WIDTH ,
C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH ,
C_STS_WIDTH => S2MM_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2wsc_stop_request => sig_rst2all_stop_request ,
wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt ,
addr2wsc_addr_posted => sig_addr2data_addr_posted ,
s2mm_bresp => s2mm_bresp ,
s2mm_bvalid => s2mm_bvalid ,
s2mm_bready => s2mm_bready ,
calc2wsc_calc_error => sig_calc2dm_calc_err ,
addr2wsc_calc_error => sig_addr2wsc_calc_error ,
addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_error => sig_data2wsc_calc_err ,
data2wsc_last_error => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
data2wsc_valid => sig_data2wsc_valid ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2stat_status => sig_wsc2stat_status ,
stat2wsc_status_ready => sig_stat2wsc_status_ready ,
wsc2stat_status_valid => sig_wsc2stat_status_valid ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_datamover_v5_1_11.axi_datamover_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_S2MM_BURST_SIZE ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1_11.axi_datamover_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => ENABLE_WAIT_FOR_DATA ,
C_ADDR_FIFO_DEPTH => WR_ADDR_CNTL_FIFO_DEPTH ,
--C_ADDR_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_ADDR_ID => S2MM_AWID_VALUE ,
C_ADDR_ID_WIDTH => S2MM_AWID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => s2mm_awid ,
addr2axi_aaddr => s2mm_awaddr ,
addr2axi_alen => s2mm_awlen ,
addr2axi_asize => s2mm_awsize ,
addr2axi_aburst => s2mm_awburst ,
addr2axi_aprot => s2mm_awprot ,
addr2axi_avalid => s2mm_awvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => s2mm_awready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => s2mm_allow_addr_req ,
addr_req_posted => s2mm_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2wsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2wsc_cmd_fifo_empty
);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_STRM_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registerd Slave Stream inputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_S2MM_STRM_SKID_BUF : entity axi_datamover_v5_1_11.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => S2MM_SDATA_WIDTH
)
port map (
-- System Ports
aclk => s2mm_aclk ,
arst => sig_mmap_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_wvalid ,
s_ready => s2mm_strm_wready ,
s_data => s2mm_strm_wdata ,
s_strb => s2mm_strm_wstrb ,
s_last => s2mm_strm_wlast ,
-- Master Side (Stream Data Output
m_valid => skid2wdc_wvalid ,
m_ready => wdc2skid_wready ,
m_data => skid2wdc_wdata ,
m_strb => skid2wdc_wstrb ,
m_last => skid2wdc_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '0' generate
begin
skid2wdc_wvalid <= s2mm_strm_wvalid;
s2mm_strm_wready <= wdc2skid_wready;
skid2wdc_wdata <= s2mm_strm_wdata;
skid2wdc_wstrb <= s2mm_strm_wstrb;
skid2wdc_wlast <= s2mm_strm_wlast;
end generate DISABLE_AXIS_SKID;
------------------------------------------------------------
-- Instance: I_WR_DATA_CNTL
--
-- Description:
-- Write Data Controller Block
--
------------------------------------------------------------
I_WR_DATA_CNTL : entity axi_datamover_v5_1_11.axi_datamover_wrdata_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => ENABLE_WAIT_FOR_DATA ,
C_REALIGNER_INCLUDED => OMIT_S2MM_DRE ,
C_ENABLE_INDET_BTT => OMIT_INDET_BTT ,
C_SF_BYTES_RCVD_WIDTH => SF_BYTES_RCVD_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
data2skid_saddr_lsb => sig_data2skid_addr_lsb ,
data2skid_wdata => sig_data2skid_wdata ,
data2skid_wstrb => sig_data2skid_wstrb ,
data2skid_wlast => sig_data2skid_wlast ,
data2skid_wvalid => sig_data2skid_wvalid ,
skid2data_wready => sig_skid2data_wready ,
s2mm_strm_wvalid => skid2wdc_wvalid ,
s2mm_strm_wready => wdc2skid_wready ,
s2mm_strm_wdata => skid2wdc_wdata ,
s2mm_strm_wstrb => skid2wdc_wstrb ,
s2mm_strm_wlast => skid2wdc_wlast ,
s2mm_strm_eop => skid2wdc_wlast ,
s2mm_stbs_asserted => ZEROS_8_BIT ,
realign2wdc_eop_error => sig_realign2wdc_eop_error ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2all_tlast_error => sig_data2all_tlast_error ,
data2all_dcntlr_halted => sig_data2all_dcntlr_halted ,
data2skid_halt => sig_data2skid_halt ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_err => sig_data2wsc_calc_err ,
data2wsc_last_err => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_valid => sig_data2wsc_valid ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_S2MM_MMAP_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registered outputs and supports bi-dir throttling.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
------------------------------------------------------------
I_S2MM_MMAP_SKID_BUF : entity axi_datamover_v5_1_11.axi_datamover_skid2mm_buf
generic map (
C_MDATA_WIDTH => S2MM_MDATA_WIDTH ,
C_SDATA_WIDTH => S2MM_SDATA_WIDTH ,
C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH
)
port map (
-- System Ports
ACLK => s2mm_aclk ,
ARST => sig_stream_rst ,
-- Slave Side (Wr Data Controller Input Side )
S_ADDR_LSB => sig_data2skid_addr_lsb,
S_VALID => sig_data2skid_wvalid ,
S_READY => sig_skid2data_wready ,
S_Data => sig_data2skid_wdata ,
S_STRB => sig_data2skid_wstrb ,
S_Last => sig_data2skid_wlast ,
-- Master Side (MMap Write Data Output Side)
M_VALID => sig_skid2axi_wvalid ,
M_READY => sig_axi2skid_wready ,
M_Data => sig_skid2axi_wdata ,
M_STRB => sig_skid2axi_wstrb ,
M_Last => sig_skid2axi_wlast
);
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_basic_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover S2MM Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_datamover Library Modules
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_reset;
use axi_datamover_v5_1_11.axi_datamover_cmd_status;
use axi_datamover_v5_1_11.axi_datamover_scc;
use axi_datamover_v5_1_11.axi_datamover_addr_cntl;
use axi_datamover_v5_1_11.axi_datamover_wrdata_cntl;
use axi_datamover_v5_1_11.axi_datamover_wr_status_cntl;
Use axi_datamover_v5_1_11.axi_datamover_skid2mm_buf;
Use axi_datamover_v5_1_11.axi_datamover_skid_buf;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_basic_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 1;
C_ENABLE_SKID_BUF : string := "11111";
C_MICRO_DMA : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
-- S2MM Halt request input control ---------------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------------
-- S2MM Error discrete output --------------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------------
-- Optional Command/Status Interface Clock and Reset Inputs -------
-- Only used when C_S2MM_STSCMD_IS_ASYNC = 1 --
--
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) ------------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
---------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(7 downto 0); --
s2mm_sts_wstrb : out std_logic_vector(0 downto 0); --
s2mm_sts_wlast : out std_logic; --
--------------------------------------------------------------------
-- Address posting controls ----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
--------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ---------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -----------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O -----------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
-----------------------------------------------------------------
);
end entity axi_datamover_s2mm_basic_wrap;
architecture implementation of axi_datamover_s2mm_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_wdemux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Write Strobe demux select control.
--
-------------------------------------------------------------------
function func_calc_wdemux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
end case;
Return (num_addr_bits_needed);
end function func_calc_wdemux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant S2MM_AWID_VALUE : integer range 0 to 255 := C_S2MM_AWID;
Constant S2MM_AWID_WIDTH : integer range 1 to 8 := C_S2MM_ID_WIDTH;
Constant S2MM_ADDR_WIDTH : integer range 32 to 64 := C_S2MM_ADDR_WIDTH;
Constant S2MM_MDATA_WIDTH : integer range 32 to 256 := C_S2MM_MDATA_WIDTH;
Constant S2MM_SDATA_WIDTH : integer range 8 to 256 := C_S2MM_SDATA_WIDTH;
Constant S2MM_CMD_WIDTH : integer := (C_TAG_WIDTH+C_S2MM_ADDR_WIDTH+32);
Constant S2MM_STS_WIDTH : integer := 8; -- always 8 for S2MM Basic Version
Constant INCLUDE_S2MM_STSFIFO : integer range 0 to 1 := 1;
Constant S2MM_STSCMD_FIFO_DEPTH : integer range 1 to 16 := C_S2MM_STSCMD_FIFO_DEPTH;
Constant S2MM_STSCMD_IS_ASYNC : integer range 0 to 1 := C_S2MM_STSCMD_IS_ASYNC;
Constant S2MM_BURST_SIZE : integer range 16 to 256 := 16;
Constant WR_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2;-- 2 added for going
-- full thresholding
-- in WSC
Constant SEL_ADDR_WIDTH : integer := func_calc_wdemux_sel_bits(S2MM_MDATA_WIDTH);
Constant INCLUDE_S2MM_DRE : integer range 0 to 1 := 1;
Constant OMIT_S2MM_DRE : integer range 0 to 1 := 0;
Constant OMIT_INDET_BTT : integer := 0;
Constant SF_BYTES_RCVD_WIDTH : integer := 1;
Constant ZEROS_8_BIT : std_logic_vector(7 downto 0) := (others => '0');
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_s2mm_cmd_wdata : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm_cache_data : std_logic_vector(7 downto 0) := (others => '0');
signal sig_cmd2mstr_command : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_last : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2addr_data_rdy : std_logic := '0';
signal sig_data2all_tlast_error : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2wsc_calc_error : std_logic := '0';
signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2wsc_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sig_data2wsc_cmd_empty : std_logic := '0';
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(7 downto 0) := (others => '0');
signal sig_stat2wsc_status_ready : std_logic := '0';
signal sig_wsc2stat_status_valid : std_logic := '0';
signal sig_wsc2mstr_halt_pipe : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_skid2data_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_skid2axi_wvalid : std_logic := '0';
signal sig_axi2skid_wready : std_logic := '0';
signal sig_skid2axi_wdata : std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_skid2axi_wstrb : std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_skid2axi_wlast : std_logic := '0';
signal sig_data2wsc_sof : std_logic := '0';
signal sig_data2wsc_eof : std_logic := '0';
signal sig_data2wsc_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_data2wsc_eop : std_logic := '0';
signal sig_data2wsc_bytes_rcvd : std_logic_vector(SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_wsc2rst_stop_cmplt : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_realign2wdc_eop_error : std_logic := '0';
signal skid2wdc_wvalid : std_logic := '0';
signal wdc2skid_wready : std_logic := '0';
signal skid2wdc_wdata : std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal skid2wdc_wstrb : std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal skid2wdc_wlast : std_logic := '0';
signal s2mm_awcache_int : std_logic_vector (3 downto 0);
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
begin --(architecture implementation)
-- Debug Port Assignments
s2mm_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the s2mm_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (s2mm_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"CAFE2222" ; -- 32 bit Constant indicating S2MM Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2wsc_status_ready;
sig_dbg_data_1(7) <= sig_wsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2wsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_wsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_wsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_wsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_wsc2stat_status(6) ; -- Slave Error
--sig_dbg_data_1(19) <= sig_wsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(19) <= '0' ; -- OKAY not used by TB
sig_dbg_data_1(20) <= sig_stat2wsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_wsc2stat_status_valid ; -- Status Valid Handshake
sig_dbg_data_1(29 downto 22) <= sig_mstr2data_len ; -- WDC Cmd FIFO LEN input
sig_dbg_data_1(30) <= sig_mstr2data_cmd_valid ; -- WDC Cmd FIFO Valid Inpute
sig_dbg_data_1(31) <= sig_data2mstr_cmd_ready ; -- WDC Cmd FIFO Ready Output
-- Write Data Channel I/O
s2mm_wvalid <= sig_skid2axi_wvalid;
sig_axi2skid_wready <= s2mm_wready ;
s2mm_wdata <= sig_skid2axi_wdata ;
s2mm_wstrb <= sig_skid2axi_wstrb ;
s2mm_wlast <= sig_skid2axi_wlast ;
GEN_CACHE : if (C_ENABLE_CACHE_USER = 0) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; -- pre Interface-X guidelines for Masters
s2mm_awuser <= "0000"; -- pre Interface-X guidelines for Masters
sig_s2mm_cache_data <= (others => '0'); --s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_CACHE_USER = 1) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; --sg_ctl (3 downto 0); -- SG Cache from register
s2mm_awuser <= "0000"; --sg_ctl (7 downto 4); -- SG Cache from register
sig_s2mm_cache_data <= s2mm_cmd_wdata(79+(C_S2MM_ADDR_WIDTH-32) downto 72+(C_S2MM_ADDR_WIDTH-32));
-- sig_s2mm_cache_data <= s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Internal error output discrete
s2mm_err <= sig_calc2dm_calc_err or sig_data2all_tlast_error;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_s2mm_cmd_wdata <= s2mm_cmd_wdata(S2MM_CMD_WIDTH-1 downto 0);
-- No Realigner in S2MM Basic
sig_realign2wdc_eop_error <= '0';
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_datamover_v5_1_11.axi_datamover_reset
generic map (
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC
)
port map (
primary_aclk => s2mm_aclk ,
primary_aresetn => s2mm_aresetn ,
secondary_awclk => s2mm_cmdsts_awclk ,
secondary_aresetn => s2mm_cmdsts_aresetn ,
halt_req => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => sig_wsc2rst_stop_cmplt ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_datamover_v5_1_11.axi_datamover_cmd_status
generic map (
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_S2MM_STSFIFO ,
C_STSCMD_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_STS_WIDTH => S2MM_STS_WIDTH ,
C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
secondary_awclk => s2mm_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => s2mm_cmd_wvalid ,
cmd_wready => s2mm_cmd_wready ,
cmd_wdata => sig_s2mm_cmd_wdata ,
cache_data => sig_s2mm_cache_data ,
sts_wvalid => s2mm_sts_wvalid ,
sts_wready => s2mm_sts_wready ,
sts_wdata => s2mm_sts_wdata ,
sts_wstrb => s2mm_sts_wstrb ,
sts_wlast => s2mm_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_wsc2stat_status ,
stat2mstr_status_ready => sig_stat2wsc_status_ready ,
mst2stst_status_valid => sig_wsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Write Status Controller Block
--
------------------------------------------------------------
I_WR_STATUS_CNTLR : entity axi_datamover_v5_1_11.axi_datamover_wr_status_cntl
generic map (
C_ENABLE_INDET_BTT => OMIT_INDET_BTT ,
C_SF_BYTES_RCVD_WIDTH => SF_BYTES_RCVD_WIDTH ,
C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH ,
C_STS_WIDTH => S2MM_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2wsc_stop_request => sig_rst2all_stop_request ,
wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt ,
addr2wsc_addr_posted => sig_addr2data_addr_posted ,
s2mm_bresp => s2mm_bresp ,
s2mm_bvalid => s2mm_bvalid ,
s2mm_bready => s2mm_bready ,
calc2wsc_calc_error => sig_calc2dm_calc_err ,
addr2wsc_calc_error => sig_addr2wsc_calc_error ,
addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_error => sig_data2wsc_calc_err ,
data2wsc_last_error => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
data2wsc_valid => sig_data2wsc_valid ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2stat_status => sig_wsc2stat_status ,
stat2wsc_status_ready => sig_stat2wsc_status_ready ,
wsc2stat_status_valid => sig_wsc2stat_status_valid ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_datamover_v5_1_11.axi_datamover_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_S2MM_BURST_SIZE ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_datamover_v5_1_11.axi_datamover_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => ENABLE_WAIT_FOR_DATA ,
C_ADDR_FIFO_DEPTH => WR_ADDR_CNTL_FIFO_DEPTH ,
--C_ADDR_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_ADDR_ID => S2MM_AWID_VALUE ,
C_ADDR_ID_WIDTH => S2MM_AWID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => s2mm_awid ,
addr2axi_aaddr => s2mm_awaddr ,
addr2axi_alen => s2mm_awlen ,
addr2axi_asize => s2mm_awsize ,
addr2axi_aburst => s2mm_awburst ,
addr2axi_aprot => s2mm_awprot ,
addr2axi_avalid => s2mm_awvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => s2mm_awready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => s2mm_allow_addr_req ,
addr_req_posted => s2mm_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2wsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2wsc_cmd_fifo_empty
);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_STRM_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registerd Slave Stream inputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
I_S2MM_STRM_SKID_BUF : entity axi_datamover_v5_1_11.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => S2MM_SDATA_WIDTH
)
port map (
-- System Ports
aclk => s2mm_aclk ,
arst => sig_mmap_rst ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => sig_data2skid_halt ,
-- Slave Side (Stream Data Input)
s_valid => s2mm_strm_wvalid ,
s_ready => s2mm_strm_wready ,
s_data => s2mm_strm_wdata ,
s_strb => s2mm_strm_wstrb ,
s_last => s2mm_strm_wlast ,
-- Master Side (Stream Data Output
m_valid => skid2wdc_wvalid ,
m_ready => wdc2skid_wready ,
m_data => skid2wdc_wdata ,
m_strb => skid2wdc_wstrb ,
m_last => skid2wdc_wlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(4) = '0' generate
begin
skid2wdc_wvalid <= s2mm_strm_wvalid;
s2mm_strm_wready <= wdc2skid_wready;
skid2wdc_wdata <= s2mm_strm_wdata;
skid2wdc_wstrb <= s2mm_strm_wstrb;
skid2wdc_wlast <= s2mm_strm_wlast;
end generate DISABLE_AXIS_SKID;
------------------------------------------------------------
-- Instance: I_WR_DATA_CNTL
--
-- Description:
-- Write Data Controller Block
--
------------------------------------------------------------
I_WR_DATA_CNTL : entity axi_datamover_v5_1_11.axi_datamover_wrdata_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => ENABLE_WAIT_FOR_DATA ,
C_REALIGNER_INCLUDED => OMIT_S2MM_DRE ,
C_ENABLE_INDET_BTT => OMIT_INDET_BTT ,
C_SF_BYTES_RCVD_WIDTH => SF_BYTES_RCVD_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
data2skid_saddr_lsb => sig_data2skid_addr_lsb ,
data2skid_wdata => sig_data2skid_wdata ,
data2skid_wstrb => sig_data2skid_wstrb ,
data2skid_wlast => sig_data2skid_wlast ,
data2skid_wvalid => sig_data2skid_wvalid ,
skid2data_wready => sig_skid2data_wready ,
s2mm_strm_wvalid => skid2wdc_wvalid ,
s2mm_strm_wready => wdc2skid_wready ,
s2mm_strm_wdata => skid2wdc_wdata ,
s2mm_strm_wstrb => skid2wdc_wstrb ,
s2mm_strm_wlast => skid2wdc_wlast ,
s2mm_strm_eop => skid2wdc_wlast ,
s2mm_stbs_asserted => ZEROS_8_BIT ,
realign2wdc_eop_error => sig_realign2wdc_eop_error ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2all_tlast_error => sig_data2all_tlast_error ,
data2all_dcntlr_halted => sig_data2all_dcntlr_halted ,
data2skid_halt => sig_data2skid_halt ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_err => sig_data2wsc_calc_err ,
data2wsc_last_err => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_valid => sig_data2wsc_valid ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_S2MM_MMAP_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registered outputs and supports bi-dir throttling.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
------------------------------------------------------------
I_S2MM_MMAP_SKID_BUF : entity axi_datamover_v5_1_11.axi_datamover_skid2mm_buf
generic map (
C_MDATA_WIDTH => S2MM_MDATA_WIDTH ,
C_SDATA_WIDTH => S2MM_SDATA_WIDTH ,
C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH
)
port map (
-- System Ports
ACLK => s2mm_aclk ,
ARST => sig_stream_rst ,
-- Slave Side (Wr Data Controller Input Side )
S_ADDR_LSB => sig_data2skid_addr_lsb,
S_VALID => sig_data2skid_wvalid ,
S_READY => sig_skid2data_wready ,
S_Data => sig_data2skid_wdata ,
S_STRB => sig_data2skid_wstrb ,
S_Last => sig_data2skid_wlast ,
-- Master Side (MMap Write Data Output Side)
M_VALID => sig_skid2axi_wvalid ,
M_READY => sig_axi2skid_wready ,
M_Data => sig_skid2axi_wdata ,
M_STRB => sig_skid2axi_wstrb ,
M_Last => sig_skid2axi_wlast
);
end implementation;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_b_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:29 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_b_e-e.vhd,v 1.1 2004/04/06 10:50:17 wig Exp $
-- $Date: 2004/04/06 10:50:17 $
-- $Log: inst_b_e-e.vhd,v $
-- Revision 1.1 2004/04/06 10:50:17 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_b_e
--
entity inst_b_e is
-- Generics:
-- No Generated Generics for Entity inst_b_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_b_e
end inst_b_e;
--
-- End of Generated Entity inst_b_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------
--
-- File: DPHY_LaneSFEN.vhd
-- Author: Elod Gyorgy
-- Original Project: MIPI D-PHY Receiver IP
-- Date: 15 December 2017
--
-------------------------------------------------------------------------------
--MIT License
--
--Copyright (c) 2016 Digilent
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module implements a MIPI D-PHY 1.0 CIL-SFEN lane: slave (receiver),
-- forward high-speed, events forward escape mode (future work), no reverse
-- direction. It is architecture-independent by itself, but the instantiated
-- HS-Deserializer has its own requirements. The D-PHY physical interface is
-- assumed to be de-multiplexed into low-power LP(1:0) and high-speed HS inputs
-- by external circuitry (outside the FPGA). On the logic side data is forwarded
-- via the PPI interface as described in the D-PHY spec Annex A.
-- This data lane module requires high-speed serial and divided parallel clocks
-- as provided by the accompanying SCNN clock lane module.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.math_real.all;
use work.DebugLib.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DPHY_LaneSFEN is
Generic (
kRefClkFreqHz : natural := 200_000_000;
kAddDelay_ps : integer := 0;
kNoLP : boolean := false
);
Port (
dLP0_in : in std_logic_vector(7 downto 0);
dLP1_in : in std_logic_vector(7 downto 0);
dLP0_out : out std_logic_vector(7 downto 0);
dLP1_out : out std_logic_vector(7 downto 0);
cLP_in : in STD_LOGIC_VECTOR (1 downto 0);
cLP_out : out STD_LOGIC_VECTOR (1 downto 0);
aLP : in STD_LOGIC_VECTOR (1 downto 0);
aHS : in STD_LOGIC;
RefClk : in STD_LOGIC;
SerClkHS : in STD_LOGIC;
DivClk : in STD_LOGIC;
aRxClkActiveHS : in STD_LOGIC;
--PPI
RxByteClkHS : out std_logic;
rbRxDataHS : out std_logic_vector(7 downto 0);
rbRxValidHS : out std_logic;
rbRxActiveHS : out std_logic;
rbRxSyncHS : out std_logic;
rbErrSotHS : out std_logic;
rbErrSotSyncHS : out std_logic;
aEnable : in std_logic; --Enable Lane Module. DivClk&SerClkHS must be stable
aForceRxmode : in std_logic; --Force Lane Module Into Receive mode / Wait for Stop state
aStopstate : out std_logic; --Lane is in Stop state.
aErrEsc : out std_logic; --Escape Entry Error.
aErrControl : out std_logic; --Control Error.
debug : out DebugSFEN_Type
-- dbg_cIntRst : out std_logic;
-- dbg_cLP : out std_logic_vector(1 downto 0);
-- dbg_state : out std_logic_vector(2 downto 0);
-- dbg_cHSClkRst : out std_logic;
-- dbg_cForceRxmode : out std_logic;
-- dbg_cInitTout : out std_logic;
-- dbg_cHSSettleTout : out std_logic;
-- dbg_cHSSettled : out std_logic;
-- dbg_cHSReset : out std_logic;
-- dbg_dSyncHard : out std_logic;
-- dbg_dSyncSoft : out std_logic;
-- dbg_dSyncErr : out std_logic
);
end DPHY_LaneSFEN;
architecture Behavioral of DPHY_LaneSFEN is
function MAX(LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end;
type state_type is (stInitCountDown, stWaitForStop, stStop, stHS_Rqst, stHS_Settle, stHS_Rcv);
signal state, nstate : state_type := stInitCountDown;
alias CtlClk : std_logic is RefClk;
alias kCtlClkFreqHz : natural is kRefClkFreqHz;
signal aLP_int, cLP, cLPGlitch: std_logic_vector(1 downto 0);
constant kTInit : natural := natural(ceil(100.0 * real(kCtlClkFreqHz) / 1_000_000.0)); --100us
constant kTHSSettle : natural := natural(ceil(85.0 * real(kCtlClkFreqHz) / 1_000_000_000.0)); --85ns
constant kTMinRx : natural := natural(ceil(20.0 * real(kCtlClkFreqHz) / 1_000_000_000.0)); --20ns
constant kOffset : natural := 3 + 1 ; -- adjust timeout values above to account for late start due to CtlClk sync
signal cDelayCnt : natural range 0 to MAX(kTInit,kTHSSettle) := 0;
signal cHS_Trail, cHSReset, dDelayCntEn, cDelayCntEn : std_logic;
signal dSyncHard, dSyncSoft, dSyncErr, dIntRst, dHSReset, dStopstate, dValid : std_logic;
signal cEnable, cIntRst, cHSClkRst, cForceRxmode, cInitDone, cHSSettled, cValid : std_logic;
signal cInitTout, cHSSettleTout: std_logic; --CtlClk timeout flags
signal dSyncHard_reg, dSyncSoft_reg, dSyncErr_reg, dInitDone : std_logic; -- for pulse generation
signal dDataOut : std_logic_vector(7 downto 0);
signal aNotEnable, aNotRxClkActiveHS : std_logic;
begin
debug.cIntRst <= cIntRst;
debug.cHSClkRst <= cHSClkRst;
debug.cLP <= cLP;
debug.state <= std_logic_vector(to_unsigned(state_type'pos(state), 3));
debug.cForceRxmode <= cForceRxmode;
debug.cInitTout <= cInitTout;
debug.cHSSettleTout <= cHSSettleTout;
debug.cHSSettled <= cHSSettled;
debug.cHSReset <= cHSReset;
debug.dSyncHard <= dSyncHard;
debug.dSyncSoft <= dSyncSoft;
debug.dSyncErr <= dSyncErr;
SyncAsyncEnable: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => '0',
aIn => aEnable,
OutClk => CtlClk,
oOut => cEnable);
cIntRst <= not cEnable;
aNotRxClkActiveHS <= not aRxClkActiveHS;
RxClkActiveHSResetBridge: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => aNotRxClkActiveHS,
OutClk => CtlClk,
oRst => cHSClkRst);
SyncAsyncForceRxMode: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => cIntRst,
aIn => aForceRxmode,
OutClk => CtlClk,
oOut => cForceRxmode);
UseOwnLP: if not kNoLP generate
-- Sync LP with CtlClk
-- T_LPX_min = 50ns = 4*UI_max
-- Synchronizing the LP bits separately is OK, because entering HS is done by
-- LP-11, LP-01, LP-00 sequences, so only one bit changes from one LPX period
-- to another.
-- At the end of HS, LP-00 goes to LP-11, but this is the only valid transition. So
-- spurious LP-01 or LP-10 between them can be ignored, until it stabilizes in LP-11.
GenSyncLP: for i in 0 to 1 generate
SyncAsyncx: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => '0',
aIn => aLP_int(i),
OutClk => CtlClk,
oOut => cLPGlitch(i));
GlitchFilterLPC: entity work.GlitchFilter
generic map (
kNoOfPeriodsToFilter => kTMinRx)
port map (
SampleClk => CtlClk,
sIn => cLPGlitch(i),
sOut => cLP(i),
sRst => '0');
end generate GenSyncLP;
end generate UseOwnLP;
cLP_out <= cLP;
ShareLPFromOtherLane: if kNoLP generate
cLP <= cLP_in;
end generate ShareLPFromOtherLane;
-- Time delay counter running on CtlClk, because it has a known, fixed frequency
-- We use it to keep track of timing parameters in time units rather than UIs.
DelayCounter: process(CtlClk)
begin
if Rising_Edge(CtlClk) then
if (cDelayCntEn = '0') then
cDelayCnt <= 0;
else
cDelayCnt <= cDelayCnt + 1;
end if;
end if;
end process DelayCounter;
cInitTout <= '1' when cDelayCnt = kTInit else '0';
cHSSettleTout <= '1' when cDelayCnt = kTHSSettle-1 else '0';
--Outputs
cDelayCntEn <= '1' when state = stInitCountDown or nstate = stHS_Settle else
'0';
ModeFSM_SyncProc: process (CtlClk)
begin
if Rising_Edge(CtlClk) then
if (cIntRst = '1') then
state <= stInitCountDown;
else
state <= nstate;
end if;
end if;
end process;
process(CtlClk, cHSClkRst)
begin
if (cHSClkRst = '1') then
cHSReset <= '1';
elsif Rising_Edge(CtlClk) then
if nstate = stHS_Settle then
cHSReset <= '0';
elsif state = stStop and cValid = '0' then
cHSReset <= '1';
end if;
end if;
end process;
process(CtlClk, cHSClkRst)
begin
if (cHSClkRst = '1') then
cHSSettled <= '0';
elsif Rising_Edge(CtlClk) then
if state = stHS_Settle and cHSSettleTout = '1' then
cHSSettled <= '1';
elsif state = stStop and cValid = '0' then
cHSSettled <= '0';
end if;
end if;
end process;
ModeFSM_NextStateProc: process (state, cLP, cInitTout, cForceRxmode, cHSSettleTout)
begin
nstate <= state;
case (state) is
when stInitCountDown =>
if cInitTout = '1' or cForceRxmode = '1' then
nstate <= stWaitForStop;
end if;
when stWaitForStop =>
if cLP = "11" then
nstate <= stStop;
end if;
when stStop =>
if cLP = "01" then -- HS-Rqst
nstate <= stHS_Rqst;
end if;
when stHS_Rqst =>
if cLP = "11" then
nstate <= stStop;
elsif cLP = "00" then
nstate <= stHS_Settle;
end if;
when stHS_Settle =>
if cLP = "11" then
nstate <= stStop;
elsif (cHSSettleTout = '1') then
nstate <= stHS_Rcv;
end if;
when stHS_Rcv =>
if cLP = "11" then
nstate <= stStop;
end if;
when others =>
null;
end case;
end process;
-----------------------------------------------------------------
-- PPI
-----------------------------------------------------------------
aStopstate <= '1' when state = stStop else '0';
RxByteClkHS <= DivClk;
--PPI requires least-significant bit to be the first one received
MakeLSF: for i in rbRxDataHS'range generate
rbRxDataHS(i) <= dDataOut(rbRxDataHS'length-1-i);
end generate MakeLSF;
rbRxValidHS <= dValid;
rbRxActiveHS <= dSyncHard or dSyncSoft;
rbRxSyncHS <= (dSyncHard and not dSyncHard_reg) or (dSyncSoft and not dSyncSoft_reg);
rbErrSotSyncHS <= (dSyncSoft and not dSyncSoft_reg);
rbErrSotHS <= dSyncErr and not dSyncErr_reg;
GenSyncPulse: process(DivClk)
begin
if Rising_Edge(DivClk) then
dSyncHard_reg <= dSyncHard;
dSyncSoft_reg <= dSyncSoft;
dSyncErr_reg <= dSyncErr;
end if;
end process;
HSDeserializerX: entity work.HS_Deserializer
Generic map (
kIs8b9b => false,
kAddDelay_ps => kAddDelay_ps,
kNoLP => kNoLP
)
Port map (
dLP0_in => dLP0_in,
dLP1_in => dLP1_in,
dLP0_out => dLP0_out,
dLP1_out => dLP1_out,
SerClk => SerClkHS,
DivClk => DivClk,
aHSIn => aHS,
aLPIn => aLP,
aLPOut => aLP_int,
dDataOut8 => dDataOut,
dValid => dValid,
dSyncHard => dSyncHard,
dSyncSoft => dSyncSoft,
dSyncErr => dSyncErr,
CtlClk => CtlClk,
cIDLY_LD => '0', --IDELAYE2 Load
cIDLY_CE => '0', --IDELAYE2 CE
cIDLY_INC => '0', --IDELAYE2 Tap Increment
cIDLY_CNT => open, --IDELAYE2 Current Tap Count
aRst => cHSReset,
aSettled => cHSSettled
);
SyncAsyncValid: entity work.SyncAsync
generic map (
kResetTo => '0',
kStages => 2) --use double FF synchronizer
port map (
aReset => cHSClkRst,
aIn => dValid,
OutClk => CtlClk,
oOut => cValid);
end Behavioral;
|
entity wait2 is
end entity;
architecture test of wait2 is
begin
proc1: process is
begin
wait for 1 ns;
assert now = 1 ns report "a";
wait for 2 ns;
assert now = 3 ns report "b";
wait for 0 fs;
assert now = 3 ns report "h";
wait for 0 fs;
assert now = 3 ns report "i";
report "done proc1";
wait;
end process;
proc2: process is
begin
wait for 1500 ps;
assert now = 1500 ps report "c";
wait for 1 ns;
assert now = 2500 ps report "d";
wait for 0 fs;
assert now = 2500 ps report "d";
wait for 0 fs;
assert now = 2500 ps report "e";
wait for 500 ps;
assert now = 3 ns report "f";
wait for 0 fs;
assert now = 3000 ps report "g";
report "done proc2";
wait;
end process;
end architecture;
|
entity wait2 is
end entity;
architecture test of wait2 is
begin
proc1: process is
begin
wait for 1 ns;
assert now = 1 ns report "a";
wait for 2 ns;
assert now = 3 ns report "b";
wait for 0 fs;
assert now = 3 ns report "h";
wait for 0 fs;
assert now = 3 ns report "i";
report "done proc1";
wait;
end process;
proc2: process is
begin
wait for 1500 ps;
assert now = 1500 ps report "c";
wait for 1 ns;
assert now = 2500 ps report "d";
wait for 0 fs;
assert now = 2500 ps report "d";
wait for 0 fs;
assert now = 2500 ps report "e";
wait for 500 ps;
assert now = 3 ns report "f";
wait for 0 fs;
assert now = 3000 ps report "g";
report "done proc2";
wait;
end process;
end architecture;
|
entity wait2 is
end entity;
architecture test of wait2 is
begin
proc1: process is
begin
wait for 1 ns;
assert now = 1 ns report "a";
wait for 2 ns;
assert now = 3 ns report "b";
wait for 0 fs;
assert now = 3 ns report "h";
wait for 0 fs;
assert now = 3 ns report "i";
report "done proc1";
wait;
end process;
proc2: process is
begin
wait for 1500 ps;
assert now = 1500 ps report "c";
wait for 1 ns;
assert now = 2500 ps report "d";
wait for 0 fs;
assert now = 2500 ps report "d";
wait for 0 fs;
assert now = 2500 ps report "e";
wait for 500 ps;
assert now = 3 ns report "f";
wait for 0 fs;
assert now = 3000 ps report "g";
report "done proc2";
wait;
end process;
end architecture;
|
entity wait2 is
end entity;
architecture test of wait2 is
begin
proc1: process is
begin
wait for 1 ns;
assert now = 1 ns report "a";
wait for 2 ns;
assert now = 3 ns report "b";
wait for 0 fs;
assert now = 3 ns report "h";
wait for 0 fs;
assert now = 3 ns report "i";
report "done proc1";
wait;
end process;
proc2: process is
begin
wait for 1500 ps;
assert now = 1500 ps report "c";
wait for 1 ns;
assert now = 2500 ps report "d";
wait for 0 fs;
assert now = 2500 ps report "d";
wait for 0 fs;
assert now = 2500 ps report "e";
wait for 500 ps;
assert now = 3 ns report "f";
wait for 0 fs;
assert now = 3000 ps report "g";
report "done proc2";
wait;
end process;
end architecture;
|
entity wait2 is
end entity;
architecture test of wait2 is
begin
proc1: process is
begin
wait for 1 ns;
assert now = 1 ns report "a";
wait for 2 ns;
assert now = 3 ns report "b";
wait for 0 fs;
assert now = 3 ns report "h";
wait for 0 fs;
assert now = 3 ns report "i";
report "done proc1";
wait;
end process;
proc2: process is
begin
wait for 1500 ps;
assert now = 1500 ps report "c";
wait for 1 ns;
assert now = 2500 ps report "d";
wait for 0 fs;
assert now = 2500 ps report "d";
wait for 0 fs;
assert now = 2500 ps report "e";
wait for 500 ps;
assert now = 3 ns report "f";
wait for 0 fs;
assert now = 3000 ps report "g";
report "done proc2";
wait;
end process;
end architecture;
|
entity bitand is
port (
x, y : in bit;
z : out bit );
end entity;
architecture test of bitand is
begin
z <= x and y;
end architecture;
entity issue9 is
end entity;
architecture test of issue9 is
signal x1, y1, z1 : bit;
begin
bitand_i: entity work.bitand
port map (
x=>x1,
y=>'0', --y=>y1 works !
z=>z1 );
process is
begin
y1 <='1';
x1 <= '0';
wait for 1 ns;
assert z1 = '0';
x1<='1';
wait for 1 ns;
assert z1 = '0';
wait;
end process;
end architecture;
|
entity bitand is
port (
x, y : in bit;
z : out bit );
end entity;
architecture test of bitand is
begin
z <= x and y;
end architecture;
entity issue9 is
end entity;
architecture test of issue9 is
signal x1, y1, z1 : bit;
begin
bitand_i: entity work.bitand
port map (
x=>x1,
y=>'0', --y=>y1 works !
z=>z1 );
process is
begin
y1 <='1';
x1 <= '0';
wait for 1 ns;
assert z1 = '0';
x1<='1';
wait for 1 ns;
assert z1 = '0';
wait;
end process;
end architecture;
|
entity bitand is
port (
x, y : in bit;
z : out bit );
end entity;
architecture test of bitand is
begin
z <= x and y;
end architecture;
entity issue9 is
end entity;
architecture test of issue9 is
signal x1, y1, z1 : bit;
begin
bitand_i: entity work.bitand
port map (
x=>x1,
y=>'0', --y=>y1 works !
z=>z1 );
process is
begin
y1 <='1';
x1 <= '0';
wait for 1 ns;
assert z1 = '0';
x1<='1';
wait for 1 ns;
assert z1 = '0';
wait;
end process;
end architecture;
|
entity bitand is
port (
x, y : in bit;
z : out bit );
end entity;
architecture test of bitand is
begin
z <= x and y;
end architecture;
entity issue9 is
end entity;
architecture test of issue9 is
signal x1, y1, z1 : bit;
begin
bitand_i: entity work.bitand
port map (
x=>x1,
y=>'0', --y=>y1 works !
z=>z1 );
process is
begin
y1 <='1';
x1 <= '0';
wait for 1 ns;
assert z1 = '0';
x1<='1';
wait for 1 ns;
assert z1 = '0';
wait;
end process;
end architecture;
|
entity bitand is
port (
x, y : in bit;
z : out bit );
end entity;
architecture test of bitand is
begin
z <= x and y;
end architecture;
entity issue9 is
end entity;
architecture test of issue9 is
signal x1, y1, z1 : bit;
begin
bitand_i: entity work.bitand
port map (
x=>x1,
y=>'0', --y=>y1 works !
z=>z1 );
process is
begin
y1 <='1';
x1 <= '0';
wait for 1 ns;
assert z1 = '0';
x1<='1';
wait for 1 ns;
assert z1 = '0';
wait;
end process;
end architecture;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_ch_07_03.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_07_03 is
end entity ch_07_03;
library bv_utilities;
use bv_utilities.bv_arithmetic.all;
architecture test of ch_07_03 is
constant T_delay_adder : delay_length := 10 ns;
-- code from book:
function bv_add ( bv1, bv2 : in bit_vector ) return bit_vector is
begin
-- . . .
-- not in book
return bv1 + bv2;
-- end not in book
end function bv_add;
signal source1, source2, sum : bit_vector(0 to 31);
-- end of code from book
begin
-- code from book:
adder : sum <= bv_add(source1, source2) after T_delay_adder;
-- end of code from book
stimulus : process is
begin
wait for 50 ns;
source1 <= X"00000002"; source2 <= X"00000003"; wait for 50 ns;
source2 <= X"FFFFFFF0"; wait for 50 ns;
source1 <= X"00000010"; wait for 50 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_ch_07_03.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_07_03 is
end entity ch_07_03;
library bv_utilities;
use bv_utilities.bv_arithmetic.all;
architecture test of ch_07_03 is
constant T_delay_adder : delay_length := 10 ns;
-- code from book:
function bv_add ( bv1, bv2 : in bit_vector ) return bit_vector is
begin
-- . . .
-- not in book
return bv1 + bv2;
-- end not in book
end function bv_add;
signal source1, source2, sum : bit_vector(0 to 31);
-- end of code from book
begin
-- code from book:
adder : sum <= bv_add(source1, source2) after T_delay_adder;
-- end of code from book
stimulus : process is
begin
wait for 50 ns;
source1 <= X"00000002"; source2 <= X"00000003"; wait for 50 ns;
source2 <= X"FFFFFFF0"; wait for 50 ns;
source1 <= X"00000010"; wait for 50 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_ch_07_03.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_07_03 is
end entity ch_07_03;
library bv_utilities;
use bv_utilities.bv_arithmetic.all;
architecture test of ch_07_03 is
constant T_delay_adder : delay_length := 10 ns;
-- code from book:
function bv_add ( bv1, bv2 : in bit_vector ) return bit_vector is
begin
-- . . .
-- not in book
return bv1 + bv2;
-- end not in book
end function bv_add;
signal source1, source2, sum : bit_vector(0 to 31);
-- end of code from book
begin
-- code from book:
adder : sum <= bv_add(source1, source2) after T_delay_adder;
-- end of code from book
stimulus : process is
begin
wait for 50 ns;
source1 <= X"00000002"; source2 <= X"00000003"; wait for 50 ns;
source2 <= X"FFFFFFF0"; wait for 50 ns;
source1 <= X"00000010"; wait for 50 ns;
wait;
end process stimulus;
end architecture test;
|
--------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2013 Johannes Walter <[email protected]>
--
-- Description:
-- Activate reset asynchronously and deactivate it synchronously.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity reset_generator is
generic (
-- Number of delay stages
num_delay_g : positive := 4;
-- Reset active state
active_g : std_ulogic := '0');
port (
-- Clock
clk_i : in std_ulogic;
-- Asynchronous reset input
rst_asy_i : in std_ulogic;
-- Reset output
rst_o : out std_ulogic);
end entity reset_generator;
architecture rtl of reset_generator is
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal rst : std_ulogic_vector(num_delay_g - 1 downto 0) := (others => active_g);
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
rst_o <= rst(rst'high);
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
regs : process (clk_i, rst_asy_i) is
begin -- process regs
if rst_asy_i = active_g then
rst <= (others => active_g);
elsif rising_edge(clk_i) then
rst <= rst(rst'high - 1 downto rst'low) & (not active_g);
end if;
end process regs;
end architecture rtl;
|
-- file: pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___192.000______0.000______50.0______196.182____381.200
-- CLK_OUT2____14.769______0.000______50.0______303.744____381.200
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_____________100____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity pll is
port
(-- Clock in ports
CLK_IN : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end pll;
architecture xilinx of pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "pll,clk_wiz_v3_6,{component_name=pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 5,
CLKFBOUT_MULT => 48,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 5,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 65,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 10.000,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2_unused,
CLKOUT3 => clkout3_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
-- Status and control signals
LOCKED => LOCKED,
RST => RESET,
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLK_OUT2,
I => clkout1);
end xilinx;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library util;
use util.numeric_pkg.all;
use work.cpu_btb_cache_config_pkg.all;
package cpu_btb_cache_replace_lru_pkg is
constant cpu_btb_cache_replace_lru_state_bits : natural := (2**cpu_btb_cache_log2_assoc-1)*cpu_btb_cache_log2_assoc;
subtype cpu_btb_cache_replace_lru_state_type is std_ulogic_vector(cpu_btb_cache_replace_lru_state_bits-1 downto 0);
type cpu_btb_cache_replace_lru_ctrl_in_type is record
re : std_ulogic;
we : std_ulogic;
end record;
type cpu_btb_cache_replace_lru_dp_in_type is record
rindex : std_ulogic_vector(cpu_btb_cache_index_bits-1 downto 0);
windex : std_ulogic_vector(cpu_btb_cache_index_bits-1 downto 0);
wway : std_ulogic_vector(2**cpu_btb_cache_log2_assoc-1 downto 0);
wstate : cpu_btb_cache_replace_lru_state_type;
end record;
type cpu_btb_cache_replace_lru_dp_out_type is record
rway : std_ulogic_vector(2**cpu_btb_cache_log2_assoc-1 downto 0);
rstate : cpu_btb_cache_replace_lru_state_type;
end record;
end package;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahb2avl_async_be
-- File: ahb2avl_async_be.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Avalon clock domain part of ahb2avl_async
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
entity ahb2avl_async_be is
generic (
avldbits : integer := 32;
avlabits : integer := 20;
ahbbits : integer := ahbdw;
burstlen : integer := 8;
nosync : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
avlsi : out ddravl_slv_in_type;
avlso : in ddravl_slv_out_type;
request: in ddr_request_type;
start_tog: in std_ulogic;
response: out ddr_response_type;
wbraddr : out std_logic_vector(log2((32*burstlen)/avldbits) downto 0);
wbrdata : in std_logic_vector(avldbits-1 downto 0);
rbwaddr : out std_logic_vector(log2((32*burstlen)/avldbits)-1 downto 0);
rbwdata : out std_logic_vector(avldbits-1 downto 0);
rbwrite : out std_logic
);
end;
architecture rtl of ahb2avl_async_be is
constant avlbl: integer := (burstlen*32) / avldbits;
constant onev: std_logic_vector(15 downto 0) := (others => '1');
type be_state is (idle,acc1,acc2,rdwait);
type be_regs is record
req1,req2 : ddr_request_type;
start1,start2: std_ulogic;
resp: ddr_response_type;
s: be_state;
ramaddr: std_logic_vector(log2(avlbl)-1 downto 0);
beginburst: std_ulogic;
wr: std_ulogic;
rd: std_ulogic;
reading: std_ulogic;
rdata_valid_prev: std_ulogic;
wmaskmode: std_ulogic;
rstarted: std_ulogic;
end record;
signal r,nr: be_regs;
begin
comb: process(r,rst,request,start_tog,avlso,wbrdata)
variable v: be_regs;
variable vstart: std_logic;
variable vreq: ddr_request_type;
variable startmask,endmask,mask,mask16,mask8: std_logic_vector(avldbits/8-1 downto 0);
variable ad32: std_logic_vector(3 downto 2);
variable nwmaskmode: std_ulogic;
variable rbw: std_ulogic;
variable slvi: ddravl_slv_in_type;
variable rddone: std_ulogic;
variable inc_ramaddr: std_ulogic;
variable aendaddr: std_logic_vector(9 downto 0);
begin
v := r;
slvi := ddravl_slv_in_none;
slvi.burstbegin := r.beginburst;
slvi.addr(avlabits-1 downto log2(avlbl)) :=
vreq.startaddr(avlabits-1-log2(avlbl)+log2(burstlen*4) downto log2(burstlen*4));
slvi.addr(log2(avlbl)-1 downto 0) := r.ramaddr;
slvi.wdata(avldbits-1 downto 0) := wbrdata;
slvi.write_req := r.wr;
slvi.size := std_logic_vector(to_unsigned(avlbl, slvi.size'length));
-- fix for accesses wider than 32-b word
aendaddr := request.endaddr; --(log2(4*burstlen)-1 downto 2);
if request.hsize(1 downto 0)="11" and request.hio='0' then
aendaddr(2):='1';
end if;
if ahbbits > 64 and request.hsize(2)='1' then
aendaddr(3 downto 2) := "11";
if ahbbits > 128 and request.hsize(0)='1' then
aendaddr(4) := '1';
end if;
end if;
v.req1 := request;
v.req1.endaddr := aendaddr;
v.req2 := r.req1;
v.start1 := start_tog;
v.start2 := r.start1;
vstart:=r.start2; vreq:=r.req2;
if nosync /= 0 then vstart:=start_tog; vreq:=r.req1; end if;
startmask := (others => '1'); endmask := (others => '1');
mask16 := (others => '1'); mask8 := (others => '1');
case avldbits is
when 32 =>
if vreq.startaddr(1)='0' then mask16:="1100"; else mask16:="0011"; end if;
if vreq.startaddr(0)='0' then mask8:="1010"; else mask8:="0101"; end if;
when 64 =>
if vreq.startaddr(2)='0' then startmask:="11111111";
else startmask:="00001111";
end if;
if vreq.endaddr(2)='0' then endmask:="11110000";
else endmask:="11111111";
end if;
if vreq.startaddr(1)='0' then mask16:="11001100"; else mask16:="00110011"; end if;
if vreq.startaddr(0)='0' then mask8:="10101010"; else mask8:="01010101"; end if;
when 128 =>
ad32 := vreq.startaddr(3 downto 2);
case ad32 is
when "00" => startmask:="1111111111111111";
when "01" => startmask:="0000111111111111";
when "10" => startmask:="0000000011111111";
when others => startmask:="0000000000001111";
end case;
ad32 := vreq.endaddr(3 downto 2);
case ad32 is
when "00" => endmask:="1111000000000000";
when "01" => endmask:="1111111100000000";
when "10" => endmask:="1111111111110000";
when others => endmask:="1111111111111111";
end case;
if vreq.startaddr(1)='0' then mask16:="1100110011001100"; else mask16:="0011001100110011"; end if;
if vreq.startaddr(0)='0' then mask8:="1010101010101010"; else mask8:="0101010101010101"; end if;
when 256 =>
case vreq.startaddr(4 downto 2) is
when "000" => startmask:="11111111111111111111111111111111";
when "001" => startmask:="00001111111111111111111111111111";
when "010" => startmask:="00000000111111111111111111111111";
when "011" => startmask:="00000000000011111111111111111111";
when "100" => startmask:="00000000000000001111111111111111";
when "101" => startmask:="00000000000000000000111111111111";
when "110" => startmask:="00000000000000000000000011111111";
when others => startmask:="00000000000000000000000000001111";
end case;
case vreq.endaddr(4 downto 2) is
when "000" => endmask:="11110000000000000000000000000000";
when "001" => endmask:="11111111000000000000000000000000";
when "010" => endmask:="11111111111100000000000000000000";
when "011" => endmask:="11111111111111110000000000000000";
when "100" => endmask:="11111111111111111111000000000000";
when "101" => endmask:="11111111111111111111111100000000";
when "110" => endmask:="11111111111111111111111111110000";
when others => endmask:="11111111111111111111111111111111";
end case;
if vreq.startaddr(1)='0' then mask16:="11001100110011001100110011001100"; else mask16:="00110011001100110011001100110011"; end if;
if vreq.startaddr(0)='0' then mask8:="10101010101010101010101010101010"; else mask8:="01010101010101010101010101010101"; end if;
when others =>
--pragma translate_off
assert false report "Unsupported data bus width" severity failure;
--pragma translate_on
end case;
mask := (others => r.wmaskmode);
nwmaskmode := r.wmaskmode;
if r.wmaskmode='0' then
if r.ramaddr=vreq.startaddr(log2(burstlen*4)-1 downto log2(avldbits/8)) then
mask := startmask;
nwmaskmode:='1';
if r.reading='1' then v.rstarted := '1'; end if;
end if;
end if;
if r.ramaddr=vreq.endaddr(log2(burstlen*4)-1 downto log2(avldbits/8)) then
mask := mask and endmask;
nwmaskmode:='0';
end if;
if vreq.hsize(2 downto 1)="00" then
mask := mask and mask16;
if vreq.hsize(0)='0' then
mask := mask and mask8;
end if;
end if;
rddone := '0';
inc_ramaddr := '0';
rbw := '0';
if r.reading /= '0' then
if avlso.rdata_valid='1' then
rbw := '1';
inc_ramaddr := '1';
if v.rstarted='1' then
v.resp.rctr_gray(log2(avlbl)-1 downto 0) := nextgray(r.resp.rctr_gray(log2(avlbl)-1 downto 0));
end if;
if r.ramaddr=(r.ramaddr'range => '1') then
rddone:='1';
end if;
end if;
else
v.resp.rctr_gray := (others => '0');
end if;
v.beginburst := '0';
case r.s is
when idle =>
if vstart /= r.resp.done_tog then
v.s := acc1;
v.beginburst := '1';
end if;
v.reading := '0';
v.rstarted := '0';
v.wmaskmode := '0';
v.rd := '0';
v.wr := '0';
when acc1 =>
v.wr := vreq.hwrite;
v.rd := not vreq.hwrite;
v.reading := not vreq.hwrite;
if vreq.hwrite='1' then
slvi.write_req := '1';
end if;
if vreq.hwrite/='0' then
v.s := acc2;
end if;
if vreq.hwrite='0' and avlso.ready='1' then
v.s := rdwait;
end if;
if vreq.hwrite = '0' then
mask := (others => '1');
end if;
if avlso.ready='1' and vreq.hwrite/='0' then
inc_ramaddr := '1';
end if;
when acc2 =>
if avlso.ready='1' then
inc_ramaddr := '1';
if r.ramaddr=onev(r.ramaddr'length-1 downto 0) then
v.wr := '0';
v.resp.done_tog := not r.resp.done_tog;
v.s := idle;
end if;
end if;
when rdwait =>
v.rd := '0';
if rddone='1' then
v.resp.done_tog := not r.resp.done_tog;
v.s := idle;
end if;
end case;
if inc_ramaddr/='0' then
v.ramaddr := std_logic_vector(unsigned(r.ramaddr)+1);
v.wmaskmode := nwmaskmode;
end if;
if v.s=idle then
v.ramaddr := (others => '0');
end if;
slvi.read_req := v.rd;
slvi.be(avldbits/8-1 downto 0) := mask;
if rst='0' then
v.s := idle;
v.resp := ddr_response_none;
end if;
nr <= v;
response <= r.resp;
wbraddr <= r.resp.done_tog & v.ramaddr;
rbwaddr <= r.ramaddr;
rbwdata <= avlso.rdata(avldbits-1 downto 0);
rbwrite <= rbw;
avlsi <= slvi;
end process;
regs: process(clk)
begin
if rising_edge(clk) then
r <= nr;
end if;
end process;
end;
|
package case1 is
type t is (a, b, c);
function test1(x : t) return integer;
function test2(x : bit_vector(1 to 4)) return integer;
end package;
package body case1 is
function test1(x : t) return integer is
begin
case x is
when a => return 10;
when b => return 20;
when c => return 30;
end case;
end function;
function test2(x : bit_vector(1 to 4)) return integer is
variable result : integer := 0;
begin
case x is
when "0000" => result := 0;
when "0001" => result := 1;
when "0010" => result := 2;
when "0011" => result := 3;
when "0100" => result := 4;
when "0101" => result := 5;
when "0110" => result := 6;
when "0111" => result := 7;
when "1000" => result := 8;
when "1001" => result := 9;
when "1010" => result := 10;
when "1011" => result := 11;
when "1100" => result := 12;
when "1101" => result := 13;
when "1110" => result := 14;
when "1111" => result := 15;
end case;
return result;
end function;
end package body;
|
architecture a of b is
signal x : integer := 0;
begin
p: process is
begin
end process;
process
variable y : integer := 5;
begin
x <= y;
end process;
process (x) is
begin
x <= x + 1;
end process;
postponed process is
begin
end process;
postponed assert x = 1;
end architecture;
|
architecture a of b is
signal x : integer := 0;
begin
p: process is
begin
end process;
process
variable y : integer := 5;
begin
x <= y;
end process;
process (x) is
begin
x <= x + 1;
end process;
postponed process is
begin
end process;
postponed assert x = 1;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity RegFile_T is
end RegFile_T;
architecture Beh of RegFile_T is
component RegFile
generic (
-- èíèöèàëèçàöèÿ ðåãèñòðà ïëþñ ðàçðÿäíîé øèíû äàííûõ
INITREG: std_logic_vector := "0000";
-- ðàçðÿäíîñòü øèíû àäðåñà
a: integer := 2);
port (
-- ñèãíàë èíèöèàëèçàöèè ðåãèñòðîâ
INIT: in std_logic;
-- øèíà äàííûõ äëÿ çàïèñè
WDP: in std_logic_vector(INITREG'range);
-- øèíà àäðåñà äëÿ çàïèñè
WA: in std_logic_vector(a-1 downto 0);
-- øèíà àäðåñà äëÿ ÷òåíèÿ
RA: in std_logic_vector(a-1 downto 0);
-- ñèãíàë ðàçðåøåíèÿ çàïèñè
WE: in std_logic;
-- ïðî÷èòàííûå äàííûå
RDP: out std_logic_vector(INITREG'range));
end component;
signal init: std_logic := '0';
signal wdp: std_logic_vector(3 downto 0):= "0000";
signal wa: std_logic_vector(1 downto 0) := "00";
signal ra: std_logic_vector(1 downto 0) := "00";
signal we: std_logic := '0';
signal rdp: std_logic_vector(3 downto 0) := "0000";
constant WAIT_Period: time := 10 ns;
begin
ufile: RegFile port map (
init => init,
wdp => wdp,
wa => wa,
ra => ra,
we => we,
rdp => rdp
);
main: process
begin
wait for wait_period;
init <= '1';
wait for wait_period / 2;
init <= '0';
wdp <= "1100";
wa <= "00";
we <= '1';
wait for wait_period / 2;
we <= '0';
wdp <= "1010";
wa <= "01";
wait for wait_period / 2;
we <= '1';
wait for wait_period / 2;
we <= '0';
wait for wait_period / 2;
ra <= "00";
wait for wait_period;
ra <= "01";
wait;
end process;
end Beh;
configuration config of RegFile_T is
for Beh
for ufile : RegFile
use entity work.regfile(Beh);
end for;
end for;
end config; |
--
-- TEST NAME:
--
-- CT00610
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.3 (1)
-- 9.3 (2)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00610
-- PKG00610/BODY
-- ENT00610_Test_Bench(ARCH00610_Test_Bench)
--
-- REVISION HISTORY:
--
-- 24-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-Checking
--
--
use WORK.all ;
use STANDARD_TYPES.all ;
package PKG00610 is
signal Check1, Check2 : Integer := 0 ;
procedure PROC ( signal called : out integer;
constant P : in integer );
end PKG00610 ;
--
use WORK.all;
package body PKG00610 is
procedure PROC ( signal called : out integer;
constant P : in integer ) is
begin
called <= P + 1 after 0ns ;
end PROC ;
end PKG00610 ;
--
use WORK.all ;
use WORK.PKG00610.all ;
use WORK.STANDARD_TYPES.all ;
entity ENT00610_Test_Bench is
end ENT00610_Test_Bench ;
use WORK.all;
architecture ARCH00610_Test_Bench of ENT00610_Test_Bench is
begin
L1:
block
begin
ALab: PROC (Check1, Check1) ;
process ( Check1 )
variable First_Time : boolean := True ;
begin
if First_Time then
First_Time := false ;
else
test_report ( "ARCH00610" ,
"Concurrent procedure call with no in/inout signal "&
"parameters has an implicit wait statement with no "&
"sens list" ,
Check1 = 1 ) ;
end if ;
end process ;
PROC (Check2, Check2) ;
process ( Check2 )
variable First_Time : boolean := True ;
begin
if First_Time then
First_Time := false ;
else
test_report ( "ARCH00610" ,
"Concurrent procedure call with no label",
Check2 = 1 ) ;
end if ;
end process ;
end block L1 ;
end ARCH00610_Test_Bench ;
--
|
-------------------------------------------------------------------------------
-- axi_datamover_indet_btt.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_indet_btt.vhd
--
-- Description:
-- This file implements the DataMover S2MM Indeterminate BTT support module.
-- This Module keeps track of the incoming data stream and generates a transfer
-- descriptor for each AXI MMap Burst worth of data loaded in the Data FIFO.
-- This information is stored in a separate FIFO that the Predictive Transfer
-- Calculator fetches sequentially as it is generating commands for the AXI MMap
-- bus.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0;
Use lib_pkg_v1_0.lib_pkg.clog2;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_sfifo_autord;
use axi_datamover_v5_1.axi_datamover_skid_buf;
Use axi_datamover_v5_1.axi_datamover_stbs_set;
Use axi_datamover_v5_1.axi_datamover_stbs_set_nodre;
-------------------------------------------------------------------------------
entity axi_datamover_indet_btt is
generic (
C_SF_FIFO_DEPTH : integer range 128 to 8192 := 128;
-- Sets the depth of the Data FIFO
C_IBTT_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- Sets the width of the sf2pcc_xfer_bytes port
C_STRT_OFFSET_WIDTH : Integer range 1 to 7 := 2;
-- Sets the bit width of the starting address offset port
-- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH)
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates what is set as the allowed max burst length for AXI4
-- transfers
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the width of the AXI4 MMap data path
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Indicates the width of the stream data path
C_ENABLE_SKID_BUF : string := "11111";
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_DRE : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- Clock input --------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-----------------------------------------------------------
-- Write Data Controller I/O ----------------------------------------------------------
--
ibtt2wdc_stbs_asserted : Out std_logic_vector(7 downto 0); --
-- Indicates the number of asserted WSTRB bits for the --
-- associated output stream data beat --
--
ibtt2wdc_eop : Out std_logic; --
-- Write End of Packet flag output to Write Data Controller --
--
ibtt2wdc_tdata : Out std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- Write DATA output to Write Data Controller --
--
ibtt2wdc_tstrb : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
-- Write DATA output to Write Data Controller --
--
ibtt2wdc_tlast : Out std_logic; --
-- Write LAST output to Write Data Controller --
--
ibtt2wdc_tvalid : Out std_logic; --
-- Write VALID output to Write Data Controller --
--
wdc2ibtt_tready : In std_logic; --
-- Write READY input from Write Data Controller --
---------------------------------------------------------------------------------------
-- DRE Stream In ----------------------------------------------------------------------
--
dre2ibtt_tvalid : In std_logic; --
-- DRE Stream VALID Output --
--
ibtt2dre_tready : Out Std_logic; --
-- DRE Stream READY input --
--
dre2ibtt_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- DRE Stream DATA input --
--
dre2ibtt_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- DRE Stream STRB input --
--
dre2ibtt_tlast : In std_logic; --
-- DRE Xfer LAST input --
--
dre2ibtt_eop : In std_logic; --
-- DRE Stream end of Stream packet flag --
--------------------------------------------------------------------------------------
-- Starting Address Offset Input -------------------------------------------------
--
dre2ibtt_strt_addr_offset : In std_logic_vector(C_STRT_OFFSET_WIDTH-1 downto 0); --
-- Used by Packing logic to set the initial data slice position for the --
-- packing operation. Packing is only needed if the MMap and Stream Data --
-- widths do not match. This input is sampled on the first valid DRE Stream In --
-- input databeat of a packet. --
-- --
-----------------------------------------------------------------------------------
-- Store and Forward Command Calculator Interface ---------------------------------------
--
sf2pcc_xfer_valid : Out std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the XFER_DESCR_FIFO --
--
pcc2sf_xfer_ready : in std_logic; --
-- Indicates that a full burst of data has been loaded into the data FIFO --
--
--
sf2pcc_cmd_cmplt : Out std_logic; --
-- Indicates that this is the final xfer for an associated command loaded --
-- into the Realigner by the IBTTCC interface --
--
--
sf2pcc_packet_eop : Out std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor --
--
sf2pcc_xfer_bytes : Out std_logic_vector(C_IBTT_XFER_BYTES_WIDTH-1 downto 0) --
-- This byte count is used by the IBTTCC for setting up the spawned child --
-- commands. The IBTTCC must use this count to generate the appropriate --
-- LEN value to put out on the AXI4 Write Addr Channel and the WSTRB on the AXI4 --
-- Write Data Channel. --
-----------------------------------------------------------------------------------------
);
end entity axi_datamover_indet_btt;
architecture implementation of axi_datamover_indet_btt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_cntr_width
--
-- Function Description:
-- This function calculates the needed counter bit width from the
-- number of count sates needed (input).
--
-------------------------------------------------------------------
function funct_get_cntr_width (num_cnt_values : integer) return integer is
Variable temp_cnt_width : Integer := 0;
begin
if (num_cnt_values <= 2) then
temp_cnt_width := 1;
elsif (num_cnt_values <= 4) then
temp_cnt_width := 2;
elsif (num_cnt_values <= 8) then
temp_cnt_width := 3;
elsif (num_cnt_values <= 16) then
temp_cnt_width := 4;
elsif (num_cnt_values <= 32) then
temp_cnt_width := 5;
elsif (num_cnt_values <= 64) then
temp_cnt_width := 6;
elsif (num_cnt_values <= 128) then
temp_cnt_width := 7;
else
temp_cnt_width := 8;
end if;
Return (temp_cnt_width);
end function funct_get_cntr_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 4 and 32. THis is used for sizing the SRL based XD FIFO.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 4) then
temp_pwr2 := 4;
elsif (input_value <= 8) then
temp_pwr2 := 8;
elsif (input_value <= 16) then
temp_pwr2 := 16;
else
temp_pwr2 := 32;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_PER_BYTE : integer := 8;
Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH;
Constant STRM_WSTB_WIDTH : integer := C_STREAM_DWIDTH/BITS_PER_BYTE;
Constant MMAP_WSTB_WIDTH : integer := C_MMAP_DWIDTH/BITS_PER_BYTE;
Constant STRM_STRBS_ASSERTED_WIDTH : integer := clog2(STRM_WSTB_WIDTH)+1;
-- Constant DATA_FIFO_DFACTOR : integer := 4; -- set buffer to 4 times the Max allowed Burst Length
-- Constant DATA_FIFO_DEPTH : integer := C_MAX_BURST_LEN*DATA_FIFO_DFACTOR;
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH+MMAP_WSTB_WIDTH*C_ENABLE_S2MM_TKEEP+2;
-- Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH+STRB_CNTR_WIDTH+2;
Constant DATA_FIFO_CNT_WIDTH : integer := clog2(DATA_FIFO_DEPTH)+1;
Constant BURST_CNTR_WIDTH : integer := clog2(C_MAX_BURST_LEN);
Constant MAX_BURST_DBEATS : Unsigned(BURST_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BURST_CNTR_WIDTH);
Constant DBC_ONE : Unsigned(BURST_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, BURST_CNTR_WIDTH);
Constant BYTE_CNTR_WIDTH : integer := C_IBTT_XFER_BYTES_WIDTH;
Constant BYTES_PER_MMAP_DBEAT : integer := C_MMAP_DWIDTH/BITS_PER_BYTE;
Constant BYTES_PER_STRM_DBEAT : integer := C_STREAM_DWIDTH/BITS_PER_BYTE;
--Constant MAX_BYTE_CNT : integer := C_MAX_BURST_LEN*BYTES_PER_DBEAT;
--Constant NUM_STRB_BITS : integer := BYTES_PER_DBEAT;
Constant BCNTR_ONE : Unsigned(BYTE_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, BYTE_CNTR_WIDTH);
--Constant XD_FIFO_DEPTH : integer := 16;
Constant XD_FIFO_DEPTH : integer := funct_rnd2pwr_of_2(DATA_FIFO_DEPTH/C_MAX_BURST_LEN);
Constant XD_FIFO_CNT_WIDTH : integer := clog2(XD_FIFO_DEPTH)+1;
Constant XD_FIFO_WIDTH : integer := BYTE_CNTR_WIDTH+2;
Constant MMAP_STBS_ASSERTED_WIDTH : integer := 8;
Constant SKIDBUF2WDC_DWIDTH : integer := C_MMAP_DWIDTH + MMAP_STBS_ASSERTED_WIDTH;
Constant SKIDBUF2WDC_STRB_WIDTH : integer := SKIDBUF2WDC_DWIDTH/BITS_PER_BYTE;
--Constant NUM_ZEROS_WIDTH : integer := MMAP_STBS_ASSERTED_WIDTH;
Constant STRB_CNTR_WIDTH : integer := MMAP_STBS_ASSERTED_WIDTH;
-- Signals
signal sig_wdc2ibtt_tready : std_logic := '0';
signal sig_ibtt2wdc_tvalid : std_logic := '0';
signal sig_ibtt2wdc_tdata : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tstrb : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tlast : std_logic := '0';
signal sig_ibtt2wdc_eop : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_rd_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_wr_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_push_xd_fifo : std_logic := '0';
signal sig_pop_xd_fifo : std_logic := '0';
signal sig_xd_fifo_data_in : std_logic_vector(XD_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_xd_fifo_data_out : std_logic_vector(XD_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_xd_fifo_dvalid : std_logic := '0';
signal sig_xd_fifo_full : std_logic := '0';
signal sig_tmp : std_logic := '0';
signal sig_strm_in_ready : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_good_tlast_dbeat : std_logic := '0';
signal sig_dre2ibtt_tlast_reg : std_logic := '0';
signal sig_dre2ibtt_eop_reg : std_logic := '0';
signal sig_burst_dbeat_cntr : Unsigned(BURST_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_dbeat_cntr : std_logic := '0';
signal sig_clr_dbeat_cntr : std_logic := '0';
signal sig_clr_dbc_reg : std_logic := '0';
signal sig_dbc_max : std_logic := '0';
signal sig_pcc2ibtt_xfer_ready : std_logic := '0';
signal sig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_byte_cntr : std_logic := '0';
signal sig_incr_byte_cntr : std_logic := '0';
signal sig_clr_byte_cntr : std_logic := '0';
signal sig_fifo_tstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_num_ls_zeros : integer range 0 to STRM_WSTB_WIDTH := 0;
signal sig_ls_assert_found : std_logic := '0';
signal sig_num_ms_zeros : integer range 0 to STRM_WSTB_WIDTH := 0;
signal sig_ms_assert_found : std_logic := '0';
-- signal sig_num_zeros : unsigned(NUM_ZEROS_WIDTH-1 downto 0) := (others => '0');
-- signal sig_num_ones : unsigned(NUM_ZEROS_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs2sfcc_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs2wdc_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_stbs_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tready : std_logic := '0';
signal sig_skidbuf_in_tvalid : std_logic := '0';
signal sig_skidbuf_in_tdata : std_logic_vector(SKIDBUF2WDC_DWIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tstrb : std_logic_vector(SKIDBUF2WDC_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tlast : std_logic := '0';
signal sig_skidbuf_in_eop : std_logic := '0';
signal sig_skidbuf_out_tready : std_logic := '0';
signal sig_skidbuf_out_tvalid : std_logic := '0';
signal sig_skidbuf_out_tdata : std_logic_vector(SKIDBUF2WDC_DWIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_out_tstrb : std_logic_vector(SKIDBUF2WDC_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_out_tlast : std_logic := '0';
signal sig_skidbuf_out_eop : std_logic := '0';
signal sig_enable_dbcntr : std_logic := '0';
signal sig_good_fifo_write : std_logic := '0';
begin --(architecture implementation)
-- Write Data Controller I/O
sig_wdc2ibtt_tready <= wdc2ibtt_tready ;
ibtt2wdc_tvalid <= sig_ibtt2wdc_tvalid ;
ibtt2wdc_tdata <= sig_ibtt2wdc_tdata ;
ibtt2wdc_tstrb <= sig_ibtt2wdc_tstrb ;
ibtt2wdc_tlast <= sig_ibtt2wdc_tlast ;
ibtt2wdc_eop <= sig_ibtt2wdc_eop ;
ibtt2wdc_stbs_asserted <= sig_ibtt2wdc_stbs_asserted;
-- PCC I/O
sf2pcc_xfer_valid <= sig_xd_fifo_dvalid;
sig_pcc2ibtt_xfer_ready <= pcc2sf_xfer_ready;
sf2pcc_packet_eop <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH+1);
sf2pcc_cmd_cmplt <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH);
sf2pcc_xfer_bytes <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH-1 downto 0);
-- DRE Stream In
ibtt2dre_tready <= sig_strm_in_ready;
-- sig_strm_in_ready <= not(sig_xd_fifo_full) and
-- not(sig_data_fifo_full);
sig_good_strm_dbeat <= dre2ibtt_tvalid and
sig_strm_in_ready;
sig_good_tlast_dbeat <= sig_good_strm_dbeat and
dre2ibtt_tlast;
-- Burst Packet Counter Logic -------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_DBC_STUFF
--
-- Process Description:
-- Just a register for data beat counter signals.
--
-------------------------------------------------------------
REG_DBC_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dre2ibtt_tlast_reg <= '0';
sig_dre2ibtt_eop_reg <= '0';
sig_clr_dbc_reg <= '0';
else
sig_dre2ibtt_tlast_reg <= dre2ibtt_tlast;
sig_dre2ibtt_eop_reg <= dre2ibtt_eop;
sig_clr_dbc_reg <= sig_clr_dbeat_cntr;
end if;
end if;
end process REG_DBC_STUFF;
-- sig_clr_dbc_reg <= sig_clr_dbeat_cntr;
-- Increment the dataBeat counter on a data fifo wide
-- load condition. If packer logic is enabled, this will
-- only occur when a full fifo data width has been collected
-- from the Stream input.
sig_incr_dbeat_cntr <= sig_good_strm_dbeat and
sig_enable_dbcntr;
-- Check to see if a max burst len of databeats have been
-- loaded into the FIFO
sig_dbc_max <= '1'
when (sig_burst_dbeat_cntr = MAX_BURST_DBEATS)
Else '0';
-- Start the counter over at a max burst len boundary or at
-- the end of the packet.
sig_clr_dbeat_cntr <= '1'
when (sig_dbc_max = '1' and
sig_good_strm_dbeat = '1' and
sig_enable_dbcntr = '1') or
(sig_good_tlast_dbeat = '1' and
sig_enable_dbcntr = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DBC_CMTR
--
-- Process Description:
-- The Databeat Counter keeps track of how many databeats have
-- been loaded into the Data FIFO. When a max burst worth of
-- databeats have been loaded (or a TLAST encountered), the
-- XD FIFO can be loaded with a transfer data set to be sent
-- to the IBTTCC.
--
-------------------------------------------------------------
IMP_DBC_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_dbeat_cntr = '1') then
sig_burst_dbeat_cntr <= (others => '0');
elsif (sig_incr_dbeat_cntr = '1') then
sig_burst_dbeat_cntr <= sig_burst_dbeat_cntr + DBC_ONE;
else
null; -- hold current value
end if;
end if;
end process IMP_DBC_CMTR;
----- Byte Counter Logic -----------------------------------------------
sig_clr_byte_cntr <= sig_clr_dbc_reg and
not(sig_good_strm_dbeat);
sig_ld_byte_cntr <= sig_clr_dbc_reg and
sig_good_strm_dbeat;
sig_incr_byte_cntr <= sig_good_strm_dbeat;
sig_byte_cntr_incr_value <= RESIZE(UNSIGNED(sig_stbs2sfcc_asserted), BYTE_CNTR_WIDTH);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BYTE_CMTR
--
-- Process Description:
-- Keeps a running byte count per burst packet loaded into the
-- xfer FIFO. It is based on the strobes set on the incoming
-- Stream dbeat.
--
-------------------------------------------------------------
IMP_BYTE_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_byte_cntr = '1') then
sig_byte_cntr <= (others => '0');
elsif (sig_ld_byte_cntr = '1') then
sig_byte_cntr <= sig_byte_cntr_incr_value;
elsif (sig_incr_byte_cntr = '1') then
sig_byte_cntr <= sig_byte_cntr + sig_byte_cntr_incr_value;
else
null; -- hold current value
end if;
end if;
end process IMP_BYTE_CMTR;
------------------------------------------------------------
-- Instance: I_IBTTCC_STBS_SET
--
-- Description:
-- Instance of the asserted strobe counter for the IBTTCC
-- interface.
--
------------------------------------------------------------
SAME_WIDTH_NO_DRE : if (C_ENABLE_DRE = 0 and (C_STREAM_DWIDTH = C_MMAP_DWIDTH)) generate
begin
I_IBTTCC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set_nodre
generic map (
C_STROBE_WIDTH => STRM_WSTB_WIDTH
)
port map (
tstrb_in => dre2ibtt_tstrb,
num_stbs_asserted => sig_stbs2sfcc_asserted -- 8 bit wide slv
);
end generate SAME_WIDTH_NO_DRE;
DIFF_WIDTH_OR_DRE : if (C_ENABLE_DRE /= 0 or (C_STREAM_DWIDTH /= C_MMAP_DWIDTH)) generate
begin
I_IBTTCC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set
generic map (
C_STROBE_WIDTH => STRM_WSTB_WIDTH
)
port map (
tstrb_in => dre2ibtt_tstrb,
num_stbs_asserted => sig_stbs2sfcc_asserted -- 8 bit wide slv
);
end generate DIFF_WIDTH_OR_DRE;
----- Xfer Descriptor FIFO Logic -----------------------------------------------
sig_push_xd_fifo <= sig_clr_dbc_reg ;
sig_pop_xd_fifo <= sig_pcc2ibtt_xfer_ready and
sig_xd_fifo_dvalid ;
sig_xd_fifo_data_in <= sig_dre2ibtt_eop_reg & -- (TLAST for the input Stream)
sig_dre2ibtt_tlast_reg & -- (TLAST for the IBTTCC command)
std_logic_vector(sig_byte_cntr); -- Number of bytes in this xfer
------------------------------------------------------------
-- Instance: I_XD_FIFO
--
-- Description:
-- Implement the Transfer Desciptor (XD) FIFO. This FIFO holds
-- the individual child command xfer descriptors used by the
-- IBTTCC to generate the commands sent to the Address Cntlr and
-- the Data Cntlr.
--
------------------------------------------------------------
I_XD_FIFO : entity axi_datamover_v5_1.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => XD_FIFO_WIDTH ,
C_DEPTH => XD_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => XD_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => 0 ,
C_NEED_ALMOST_FULL => 1 ,
C_USE_BLKMEM => 0 ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => mmap_reset ,
SFIFO_Clk => primary_aclk ,
SFIFO_Wr_en => sig_push_xd_fifo ,
SFIFO_Din => sig_xd_fifo_data_in ,
SFIFO_Rd_en => sig_pop_xd_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_xd_fifo_dvalid ,
SFIFO_Dout => sig_xd_fifo_data_out ,
SFIFO_Full => sig_xd_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => sig_tmp ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
----------------------------------------------------------------
-- Packing Logic ------------------------------------------
----------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_PACKING
--
-- If Generate Description:
-- Omits any packing logic in the Store and Forward module.
-- The Stream and MMap data widths are the same.
--
------------------------------------------------------------
OMIT_PACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate
begin
-- The data beat counter is always enabled when the packer
-- is omitted.
sig_enable_dbcntr <= '1';
sig_good_fifo_write <= sig_good_strm_dbeat;
sig_strm_in_ready <= not(sig_xd_fifo_full) and
not(sig_data_fifo_full) and
not (sig_tmp);
GEN_S2MM_TKEEP_ENABLE5 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Concatonate the Stream inputs into the single FIFO data
-- word input value
sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
dre2ibtt_tlast & -- Tlast marker
dre2ibtt_tstrb & -- TSTRB Value
dre2ibtt_tdata; -- data value
end generate GEN_S2MM_TKEEP_ENABLE5;
GEN_S2MM_TKEEP_DISABLE5 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Concatonate the Stream inputs into the single FIFO data
-- word input value
sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
dre2ibtt_tlast & -- Tlast marker
--dre2ibtt_tstrb & -- TSTRB Value
dre2ibtt_tdata; -- data value
end generate GEN_S2MM_TKEEP_DISABLE5;
end generate OMIT_PACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_PACKING
--
-- If Generate Description:
-- Includes packing logic in the IBTT Store and Forward
-- module. The MMap Data bus is wider than the Stream width.
--
------------------------------------------------------------
INCLUDE_PACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate
Constant TLAST_WIDTH : integer := 1; -- bit
Constant EOP_WIDTH : integer := 1; -- bit
Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH;
Constant STRB_SLICE_WIDTH : integer := STRM_WSTB_WIDTH;
Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH +
EOP_WIDTH;
Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO);
Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, OFFSET_CNTR_WIDTH);
Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH);
-- Types -----------------------------------------------------------------------------
type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(DATA_SLICE_WIDTH-1 downto 0);
type lsig_strb_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(STRB_SLICE_WIDTH-1 downto 0);
type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0);
-- local signals
signal lsig_data_slice_reg : lsig_data_slice_type;
signal lsig_strb_slice_reg : lsig_strb_slice_type;
signal lsig_flag_slice_reg : lsig_flag_slice_type;
signal lsig_reg_segment : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) := (others => '0');
signal lsig_segment_ld : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_segment_clr : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_0ffset_to_to_use : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_offset : std_logic := '0';
signal lsig_incr_offset : std_logic := '0';
signal lsig_offset_cntr_eq_max : std_logic := '0';
signal lsig_combined_data : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal lsig_combined_strb : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal lsig_tlast_or : std_logic := '0';
signal lsig_eop_or : std_logic := '0';
signal lsig_partial_tlast_or : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_partial_eop_or : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_packer_full : std_logic := '0';
signal lsig_packer_empty : std_logic := '0';
signal lsig_set_packer_full : std_logic := '0';
signal lsig_good_push2fifo : std_logic := '0';
signal lsig_first_dbeat : std_logic := '0';
begin
-- Generate the stream ready
sig_strm_in_ready <= not(sig_xd_fifo_full) and
not(sig_tmp) and
(not(lsig_packer_full) or
lsig_good_push2fifo) ;
-- Enable the Data Beat counter when the packer is
-- going full
sig_enable_dbcntr <= lsig_set_packer_full;
-- Assign the flag indicating that a fifo write is going
-- to occur at the next rising clock edge.
sig_good_fifo_write <= lsig_good_push2fifo;
GEN_S2MM_TKEEP_ENABLE6 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Format the composite FIFO input data word
sig_data_fifo_data_in <= lsig_eop_or & -- MS Bit
lsig_tlast_or &
lsig_combined_strb &
lsig_combined_data ; -- LS Bits
end generate GEN_S2MM_TKEEP_ENABLE6;
GEN_S2MM_TKEEP_DISABLE6 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Format the composite FIFO input data word
sig_data_fifo_data_in <= lsig_eop_or & -- MS Bit
lsig_tlast_or &
--lsig_combined_strb &
lsig_combined_data ; -- LS Bits
end generate GEN_S2MM_TKEEP_DISABLE6;
-- Generate a flag indicating a write to the DataFIFO
-- is going to complete
lsig_good_push2fifo <= lsig_packer_full and
not(sig_data_fifo_full);
-- Generate the control that loads the starting address
-- offset for the next input packet
lsig_ld_offset <= lsig_first_dbeat and
sig_good_strm_dbeat;
-- Generate the control for incrementing the offset counter
lsig_incr_offset <= sig_good_strm_dbeat;
-- Generate a flag indicating the packer input register
-- array is full or has loaded the last data beat of
-- the input paket
lsig_set_packer_full <= sig_good_strm_dbeat and
(dre2ibtt_tlast or
lsig_offset_cntr_eq_max);
-- Check to see if the offset counter has reached its max
-- value
lsig_offset_cntr_eq_max <= '1'
--when (lsig_0ffset_cntr = OFFSET_CNT_MAX)
when (lsig_0ffset_to_to_use = OFFSET_CNT_MAX)
Else '0';
-- Mux between the input start offset and the offset counter
-- output to use for the packer slice load control.
lsig_0ffset_to_to_use <= UNSIGNED(dre2ibtt_strt_addr_offset)
when (lsig_first_dbeat = '1')
Else lsig_0ffset_cntr;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_LD_MARKER
--
-- Process Description:
-- Implements the flop indicating the first databeat of
-- an input data packet.
--
-------------------------------------------------------------
IMP_OFFSET_LD_MARKER : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_first_dbeat <= '1';
elsif (sig_good_strm_dbeat = '1' and
dre2ibtt_tlast = '0') then
lsig_first_dbeat <= '0';
Elsif (sig_good_strm_dbeat = '1' and
dre2ibtt_tlast = '1') Then
lsig_first_dbeat <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_LD_MARKER;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_CNTR
--
-- Process Description:
-- Implements the address offset counter that is used to
-- steer the data loads into the packer register slices.
-- Note that the counter has to be loaded with the starting
-- offset plus one to sync up with the data input.
-------------------------------------------------------------
IMP_OFFSET_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_0ffset_cntr <= (others => '0');
Elsif (lsig_ld_offset = '1') Then
lsig_0ffset_cntr <= UNSIGNED(dre2ibtt_strt_addr_offset) + OFFSET_CNT_ONE;
elsif (lsig_incr_offset = '1') then
lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PACK_REG_FULL
--
-- Process Description:
-- Implements the Packer Register full/empty flags
--
-------------------------------------------------------------
IMP_PACK_REG_FULL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
Elsif (lsig_set_packer_full = '1' and
lsig_packer_full = '0') Then
lsig_packer_full <= '1';
lsig_packer_empty <= '0';
elsif (lsig_set_packer_full = '0' and
lsig_good_push2fifo = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PACK_REG_FULL;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_REG_SLICES
--
-- For Generate Description:
--
-- Implements the Packng Register Slices
--
--
------------------------------------------------------------
DO_REG_SLICES : for slice_index in 0 to MMAP2STRM_WIDTH_RATO-1 generate
begin
-- generate the register load enable for each slice segment based
-- on the address offset count value
lsig_segment_ld(slice_index) <= '1'
when (sig_good_strm_dbeat = '1' and
TO_INTEGER(lsig_0ffset_to_to_use) = slice_index)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DATA_SLICE
--
-- Process Description:
-- Implement a data register slice abd Strobe register slice
-- for the packer (upsizer).
--
-------------------------------------------------------------
IMP_DATA_SLICE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
lsig_strb_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_data_slice_reg(slice_index) <= dre2ibtt_tdata;
lsig_strb_slice_reg(slice_index) <= dre2ibtt_tstrb;
-- optional clear of slice reg
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
lsig_strb_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_DATA_SLICE;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FLAG_SLICE
--
-- Process Description:
-- Implement a flag register slice for the packer.
--
-------------------------------------------------------------
IMP_FLAG_SLICE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_flag_slice_reg(slice_index) <= dre2ibtt_tlast & -- bit 1
dre2ibtt_eop; -- bit 0
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_FLAG_SLICE;
end generate DO_REG_SLICES;
-- Do the OR functions of the Flags -------------------------------------
lsig_tlast_or <= lsig_partial_tlast_or(MMAP2STRM_WIDTH_RATO-1) ;
lsig_eop_or <= lsig_partial_eop_or(MMAP2STRM_WIDTH_RATO-1);
lsig_partial_tlast_or(0) <= lsig_flag_slice_reg(0)(1);
lsig_partial_eop_or(0) <= lsig_flag_slice_reg(0)(0);
------------------------------------------------------------
-- For Generate
--
-- Label: DO_FLAG_OR
--
-- For Generate Description:
-- Implement the OR of the TLAST and EOP Error flags.
--
--
--
------------------------------------------------------------
DO_FLAG_OR : for slice_index in 1 to MMAP2STRM_WIDTH_RATO-1 generate
begin
lsig_partial_tlast_or(slice_index) <= lsig_partial_tlast_or(slice_index-1) or
--lsig_partial_tlast_or(slice_index);
lsig_flag_slice_reg(slice_index)(1);
lsig_partial_eop_or(slice_index) <= lsig_partial_eop_or(slice_index-1) or
--lsig_partial_eop_or(slice_index);
lsig_flag_slice_reg(slice_index)(0);
end generate DO_FLAG_OR;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_DATA_COMBINER
--
-- For Generate Description:
-- Combines the Data Slice register and Strobe slice register
-- outputs into a single data and single strobe vector used for
-- input data to the Data FIFO.
--
--
------------------------------------------------------------
DO_DATA_COMBINER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate
begin
lsig_combined_data((slice_index*DATA_SLICE_WIDTH)-1 downto
(slice_index-1)*DATA_SLICE_WIDTH) <=
lsig_data_slice_reg(slice_index-1);
lsig_combined_strb((slice_index*STRB_SLICE_WIDTH)-1 downto
(slice_index-1)*STRB_SLICE_WIDTH) <=
lsig_strb_slice_reg(slice_index-1);
end generate DO_DATA_COMBINER;
end generate INCLUDE_PACKING;
-- Data FIFO Logic ------------------------------------------
--sig_push_data_fifo <= sig_good_strm_dbeat;
sig_push_data_fifo <= sig_good_fifo_write;
sig_pop_data_fifo <= sig_skidbuf_in_tready and
sig_data_fifo_dvalid;
-- -- Concatonate the Stream inputs into the single FIFO data in value
-- sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
-- dre2ibtt_tlast &
-- dre2ibtt_tstrb &
-- dre2ibtt_tdata;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_datamover_v5_1.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => 0 ,
C_NEED_ALMOST_FULL => 0 ,
C_USE_BLKMEM => 1 ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => mmap_reset ,
SFIFO_Clk => primary_aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => sig_data_fifo_rd_cnt ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => sig_data_fifo_wr_cnt ,
SFIFO_Rd_ack => open
);
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
GEN_S2MM_TKEEP_ENABLE7 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Rip the write strobe value from the FIFO output data
sig_fifo_tstrb_out <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-3 downto
C_MMAP_DWIDTH);
end generate GEN_S2MM_TKEEP_ENABLE7;
GEN_S2MM_TKEEP_DISBALE7 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
sig_fifo_tstrb_out <= (others => '1');
end generate GEN_S2MM_TKEEP_DISBALE7;
------------------------------------------------------------
-- Instance: I_WDC_STBS_SET
--
-- Description:
-- Instance of the asserted strobe counter for the WDC
-- interface.
--
------------------------------------------------------------
SAME_WIDTH_NO_DRE_WDC : if (C_ENABLE_DRE = 0 and (C_STREAM_DWIDTH = C_MMAP_DWIDTH)) generate
begin
I_WDC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set_nodre
generic map (
C_STROBE_WIDTH => MMAP_WSTB_WIDTH
)
port map (
tstrb_in => sig_fifo_tstrb_out,
num_stbs_asserted => sig_stbs2wdc_asserted
);
end generate SAME_WIDTH_NO_DRE_WDC;
DIFF_WIDTH_OR_DRE_WDC : if (C_ENABLE_DRE /= 0 or (C_STREAM_DWIDTH /= C_MMAP_DWIDTH)) generate
begin
I_WDC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set
generic map (
C_STROBE_WIDTH => MMAP_WSTB_WIDTH
)
port map (
tstrb_in => sig_fifo_tstrb_out,
num_stbs_asserted => sig_stbs2wdc_asserted
);
end generate DIFF_WIDTH_OR_DRE_WDC;
-------------------------------------------------------------------------
------- Isolation Skid Buffer Logic (needed for Fmax timing) -----------
-------------------------------------------------------------------------
-- Skid Buffer output assignments -----------
sig_skidbuf_out_tready <= sig_wdc2ibtt_tready;
sig_ibtt2wdc_tvalid <= sig_skidbuf_out_tvalid;
sig_ibtt2wdc_tdata <= sig_skidbuf_out_tdata(C_MMAP_DWIDTH-1 downto 0) ;
sig_ibtt2wdc_tstrb <= sig_skidbuf_out_tstrb(MMAP_WSTB_WIDTH-1 downto 0) ;
sig_ibtt2wdc_tlast <= sig_skidbuf_out_tlast ;
-- Rip the EOP marker from the MS bit of the skid output strobes
sig_ibtt2wdc_eop <= sig_skidbuf_out_tstrb(MMAP_WSTB_WIDTH) ;
-- Rip the upper 8 bits of the skid output data for the strobes asserted value
sig_ibtt2wdc_stbs_asserted <= sig_skidbuf_out_tdata(SKIDBUF2WDC_DWIDTH-1 downto
C_MMAP_DWIDTH);
-- Skid Buffer input assignments -----------
sig_skidbuf_in_tvalid <= sig_data_fifo_dvalid;
sig_skidbuf_in_eop <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-1);
sig_skidbuf_in_tlast <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-2);
-- Steal the extra input strobe bit and use it for the EOP marker
---- sig_skidbuf_in_tstrb <= sig_skidbuf_in_eop &
---- sig_data_fifo_data_out(DATA_FIFO_WIDTH-3 downto
---- C_MMAP_DWIDTH);
----
sig_skidbuf_in_tstrb <= sig_skidbuf_in_eop &
sig_fifo_tstrb_out;
-- Insert the Strobes Asserted count in the extra (MS) data byte
-- for the skid buffer
sig_skidbuf_in_tdata <= sig_stbs2wdc_asserted &
sig_data_fifo_data_out(C_MMAP_DWIDTH-1 downto 0);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(2) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_INDET_BTT_SKID_BUF
--
-- Description:
-- Instance for the Store and Forward isolation Skid Buffer
-- which is required to achieve Fmax timing. Note that this
-- skid buffer is 1 byte wider than the stream data width to
-- allow for the asserted strobes count to be passed through
-- it. The EOP marker is inserted in the extra strobe slot.
--
------------------------------------------------------------
I_INDET_BTT_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => SKIDBUF2WDC_DWIDTH
)
port map (
-- System Ports
aclk => primary_aclk ,
arst => mmap_reset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Stream Data Input)
s_valid => sig_skidbuf_in_tvalid ,
s_ready => sig_skidbuf_in_tready ,
s_data => sig_skidbuf_in_tdata ,
s_strb => sig_skidbuf_in_tstrb ,
s_last => sig_skidbuf_in_tlast ,
-- Master Side (Stream Data Output
m_valid => sig_skidbuf_out_tvalid ,
m_ready => sig_skidbuf_out_tready ,
m_data => sig_skidbuf_out_tdata ,
m_strb => sig_skidbuf_out_tstrb ,
m_last => sig_skidbuf_out_tlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(2) = '0' generate
begin
sig_skidbuf_out_tvalid <= sig_skidbuf_in_tvalid;
sig_skidbuf_in_tready <= sig_skidbuf_out_tready ;
sig_skidbuf_out_tdata <= sig_skidbuf_in_tdata ;
sig_skidbuf_out_tstrb <= sig_skidbuf_in_tstrb ;
sig_skidbuf_out_tlast <= sig_skidbuf_in_tlast ;
end generate DISABLE_AXIS_SKID;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_indet_btt.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_indet_btt.vhd
--
-- Description:
-- This file implements the DataMover S2MM Indeterminate BTT support module.
-- This Module keeps track of the incoming data stream and generates a transfer
-- descriptor for each AXI MMap Burst worth of data loaded in the Data FIFO.
-- This information is stored in a separate FIFO that the Predictive Transfer
-- Calculator fetches sequentially as it is generating commands for the AXI MMap
-- bus.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0;
Use lib_pkg_v1_0.lib_pkg.clog2;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_sfifo_autord;
use axi_datamover_v5_1.axi_datamover_skid_buf;
Use axi_datamover_v5_1.axi_datamover_stbs_set;
Use axi_datamover_v5_1.axi_datamover_stbs_set_nodre;
-------------------------------------------------------------------------------
entity axi_datamover_indet_btt is
generic (
C_SF_FIFO_DEPTH : integer range 128 to 8192 := 128;
-- Sets the depth of the Data FIFO
C_IBTT_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- Sets the width of the sf2pcc_xfer_bytes port
C_STRT_OFFSET_WIDTH : Integer range 1 to 7 := 2;
-- Sets the bit width of the starting address offset port
-- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH)
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates what is set as the allowed max burst length for AXI4
-- transfers
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the width of the AXI4 MMap data path
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Indicates the width of the stream data path
C_ENABLE_SKID_BUF : string := "11111";
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_DRE : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- Clock input --------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-----------------------------------------------------------
-- Write Data Controller I/O ----------------------------------------------------------
--
ibtt2wdc_stbs_asserted : Out std_logic_vector(7 downto 0); --
-- Indicates the number of asserted WSTRB bits for the --
-- associated output stream data beat --
--
ibtt2wdc_eop : Out std_logic; --
-- Write End of Packet flag output to Write Data Controller --
--
ibtt2wdc_tdata : Out std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- Write DATA output to Write Data Controller --
--
ibtt2wdc_tstrb : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
-- Write DATA output to Write Data Controller --
--
ibtt2wdc_tlast : Out std_logic; --
-- Write LAST output to Write Data Controller --
--
ibtt2wdc_tvalid : Out std_logic; --
-- Write VALID output to Write Data Controller --
--
wdc2ibtt_tready : In std_logic; --
-- Write READY input from Write Data Controller --
---------------------------------------------------------------------------------------
-- DRE Stream In ----------------------------------------------------------------------
--
dre2ibtt_tvalid : In std_logic; --
-- DRE Stream VALID Output --
--
ibtt2dre_tready : Out Std_logic; --
-- DRE Stream READY input --
--
dre2ibtt_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- DRE Stream DATA input --
--
dre2ibtt_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- DRE Stream STRB input --
--
dre2ibtt_tlast : In std_logic; --
-- DRE Xfer LAST input --
--
dre2ibtt_eop : In std_logic; --
-- DRE Stream end of Stream packet flag --
--------------------------------------------------------------------------------------
-- Starting Address Offset Input -------------------------------------------------
--
dre2ibtt_strt_addr_offset : In std_logic_vector(C_STRT_OFFSET_WIDTH-1 downto 0); --
-- Used by Packing logic to set the initial data slice position for the --
-- packing operation. Packing is only needed if the MMap and Stream Data --
-- widths do not match. This input is sampled on the first valid DRE Stream In --
-- input databeat of a packet. --
-- --
-----------------------------------------------------------------------------------
-- Store and Forward Command Calculator Interface ---------------------------------------
--
sf2pcc_xfer_valid : Out std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the XFER_DESCR_FIFO --
--
pcc2sf_xfer_ready : in std_logic; --
-- Indicates that a full burst of data has been loaded into the data FIFO --
--
--
sf2pcc_cmd_cmplt : Out std_logic; --
-- Indicates that this is the final xfer for an associated command loaded --
-- into the Realigner by the IBTTCC interface --
--
--
sf2pcc_packet_eop : Out std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor --
--
sf2pcc_xfer_bytes : Out std_logic_vector(C_IBTT_XFER_BYTES_WIDTH-1 downto 0) --
-- This byte count is used by the IBTTCC for setting up the spawned child --
-- commands. The IBTTCC must use this count to generate the appropriate --
-- LEN value to put out on the AXI4 Write Addr Channel and the WSTRB on the AXI4 --
-- Write Data Channel. --
-----------------------------------------------------------------------------------------
);
end entity axi_datamover_indet_btt;
architecture implementation of axi_datamover_indet_btt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_cntr_width
--
-- Function Description:
-- This function calculates the needed counter bit width from the
-- number of count sates needed (input).
--
-------------------------------------------------------------------
function funct_get_cntr_width (num_cnt_values : integer) return integer is
Variable temp_cnt_width : Integer := 0;
begin
if (num_cnt_values <= 2) then
temp_cnt_width := 1;
elsif (num_cnt_values <= 4) then
temp_cnt_width := 2;
elsif (num_cnt_values <= 8) then
temp_cnt_width := 3;
elsif (num_cnt_values <= 16) then
temp_cnt_width := 4;
elsif (num_cnt_values <= 32) then
temp_cnt_width := 5;
elsif (num_cnt_values <= 64) then
temp_cnt_width := 6;
elsif (num_cnt_values <= 128) then
temp_cnt_width := 7;
else
temp_cnt_width := 8;
end if;
Return (temp_cnt_width);
end function funct_get_cntr_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 4 and 32. THis is used for sizing the SRL based XD FIFO.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 4) then
temp_pwr2 := 4;
elsif (input_value <= 8) then
temp_pwr2 := 8;
elsif (input_value <= 16) then
temp_pwr2 := 16;
else
temp_pwr2 := 32;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_PER_BYTE : integer := 8;
Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH;
Constant STRM_WSTB_WIDTH : integer := C_STREAM_DWIDTH/BITS_PER_BYTE;
Constant MMAP_WSTB_WIDTH : integer := C_MMAP_DWIDTH/BITS_PER_BYTE;
Constant STRM_STRBS_ASSERTED_WIDTH : integer := clog2(STRM_WSTB_WIDTH)+1;
-- Constant DATA_FIFO_DFACTOR : integer := 4; -- set buffer to 4 times the Max allowed Burst Length
-- Constant DATA_FIFO_DEPTH : integer := C_MAX_BURST_LEN*DATA_FIFO_DFACTOR;
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH+MMAP_WSTB_WIDTH*C_ENABLE_S2MM_TKEEP+2;
-- Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH+STRB_CNTR_WIDTH+2;
Constant DATA_FIFO_CNT_WIDTH : integer := clog2(DATA_FIFO_DEPTH)+1;
Constant BURST_CNTR_WIDTH : integer := clog2(C_MAX_BURST_LEN);
Constant MAX_BURST_DBEATS : Unsigned(BURST_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BURST_CNTR_WIDTH);
Constant DBC_ONE : Unsigned(BURST_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, BURST_CNTR_WIDTH);
Constant BYTE_CNTR_WIDTH : integer := C_IBTT_XFER_BYTES_WIDTH;
Constant BYTES_PER_MMAP_DBEAT : integer := C_MMAP_DWIDTH/BITS_PER_BYTE;
Constant BYTES_PER_STRM_DBEAT : integer := C_STREAM_DWIDTH/BITS_PER_BYTE;
--Constant MAX_BYTE_CNT : integer := C_MAX_BURST_LEN*BYTES_PER_DBEAT;
--Constant NUM_STRB_BITS : integer := BYTES_PER_DBEAT;
Constant BCNTR_ONE : Unsigned(BYTE_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, BYTE_CNTR_WIDTH);
--Constant XD_FIFO_DEPTH : integer := 16;
Constant XD_FIFO_DEPTH : integer := funct_rnd2pwr_of_2(DATA_FIFO_DEPTH/C_MAX_BURST_LEN);
Constant XD_FIFO_CNT_WIDTH : integer := clog2(XD_FIFO_DEPTH)+1;
Constant XD_FIFO_WIDTH : integer := BYTE_CNTR_WIDTH+2;
Constant MMAP_STBS_ASSERTED_WIDTH : integer := 8;
Constant SKIDBUF2WDC_DWIDTH : integer := C_MMAP_DWIDTH + MMAP_STBS_ASSERTED_WIDTH;
Constant SKIDBUF2WDC_STRB_WIDTH : integer := SKIDBUF2WDC_DWIDTH/BITS_PER_BYTE;
--Constant NUM_ZEROS_WIDTH : integer := MMAP_STBS_ASSERTED_WIDTH;
Constant STRB_CNTR_WIDTH : integer := MMAP_STBS_ASSERTED_WIDTH;
-- Signals
signal sig_wdc2ibtt_tready : std_logic := '0';
signal sig_ibtt2wdc_tvalid : std_logic := '0';
signal sig_ibtt2wdc_tdata : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tstrb : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tlast : std_logic := '0';
signal sig_ibtt2wdc_eop : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_rd_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_wr_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_push_xd_fifo : std_logic := '0';
signal sig_pop_xd_fifo : std_logic := '0';
signal sig_xd_fifo_data_in : std_logic_vector(XD_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_xd_fifo_data_out : std_logic_vector(XD_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_xd_fifo_dvalid : std_logic := '0';
signal sig_xd_fifo_full : std_logic := '0';
signal sig_tmp : std_logic := '0';
signal sig_strm_in_ready : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_good_tlast_dbeat : std_logic := '0';
signal sig_dre2ibtt_tlast_reg : std_logic := '0';
signal sig_dre2ibtt_eop_reg : std_logic := '0';
signal sig_burst_dbeat_cntr : Unsigned(BURST_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_dbeat_cntr : std_logic := '0';
signal sig_clr_dbeat_cntr : std_logic := '0';
signal sig_clr_dbc_reg : std_logic := '0';
signal sig_dbc_max : std_logic := '0';
signal sig_pcc2ibtt_xfer_ready : std_logic := '0';
signal sig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_byte_cntr : std_logic := '0';
signal sig_incr_byte_cntr : std_logic := '0';
signal sig_clr_byte_cntr : std_logic := '0';
signal sig_fifo_tstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_num_ls_zeros : integer range 0 to STRM_WSTB_WIDTH := 0;
signal sig_ls_assert_found : std_logic := '0';
signal sig_num_ms_zeros : integer range 0 to STRM_WSTB_WIDTH := 0;
signal sig_ms_assert_found : std_logic := '0';
-- signal sig_num_zeros : unsigned(NUM_ZEROS_WIDTH-1 downto 0) := (others => '0');
-- signal sig_num_ones : unsigned(NUM_ZEROS_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs2sfcc_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs2wdc_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_stbs_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tready : std_logic := '0';
signal sig_skidbuf_in_tvalid : std_logic := '0';
signal sig_skidbuf_in_tdata : std_logic_vector(SKIDBUF2WDC_DWIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tstrb : std_logic_vector(SKIDBUF2WDC_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tlast : std_logic := '0';
signal sig_skidbuf_in_eop : std_logic := '0';
signal sig_skidbuf_out_tready : std_logic := '0';
signal sig_skidbuf_out_tvalid : std_logic := '0';
signal sig_skidbuf_out_tdata : std_logic_vector(SKIDBUF2WDC_DWIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_out_tstrb : std_logic_vector(SKIDBUF2WDC_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_out_tlast : std_logic := '0';
signal sig_skidbuf_out_eop : std_logic := '0';
signal sig_enable_dbcntr : std_logic := '0';
signal sig_good_fifo_write : std_logic := '0';
begin --(architecture implementation)
-- Write Data Controller I/O
sig_wdc2ibtt_tready <= wdc2ibtt_tready ;
ibtt2wdc_tvalid <= sig_ibtt2wdc_tvalid ;
ibtt2wdc_tdata <= sig_ibtt2wdc_tdata ;
ibtt2wdc_tstrb <= sig_ibtt2wdc_tstrb ;
ibtt2wdc_tlast <= sig_ibtt2wdc_tlast ;
ibtt2wdc_eop <= sig_ibtt2wdc_eop ;
ibtt2wdc_stbs_asserted <= sig_ibtt2wdc_stbs_asserted;
-- PCC I/O
sf2pcc_xfer_valid <= sig_xd_fifo_dvalid;
sig_pcc2ibtt_xfer_ready <= pcc2sf_xfer_ready;
sf2pcc_packet_eop <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH+1);
sf2pcc_cmd_cmplt <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH);
sf2pcc_xfer_bytes <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH-1 downto 0);
-- DRE Stream In
ibtt2dre_tready <= sig_strm_in_ready;
-- sig_strm_in_ready <= not(sig_xd_fifo_full) and
-- not(sig_data_fifo_full);
sig_good_strm_dbeat <= dre2ibtt_tvalid and
sig_strm_in_ready;
sig_good_tlast_dbeat <= sig_good_strm_dbeat and
dre2ibtt_tlast;
-- Burst Packet Counter Logic -------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_DBC_STUFF
--
-- Process Description:
-- Just a register for data beat counter signals.
--
-------------------------------------------------------------
REG_DBC_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dre2ibtt_tlast_reg <= '0';
sig_dre2ibtt_eop_reg <= '0';
sig_clr_dbc_reg <= '0';
else
sig_dre2ibtt_tlast_reg <= dre2ibtt_tlast;
sig_dre2ibtt_eop_reg <= dre2ibtt_eop;
sig_clr_dbc_reg <= sig_clr_dbeat_cntr;
end if;
end if;
end process REG_DBC_STUFF;
-- sig_clr_dbc_reg <= sig_clr_dbeat_cntr;
-- Increment the dataBeat counter on a data fifo wide
-- load condition. If packer logic is enabled, this will
-- only occur when a full fifo data width has been collected
-- from the Stream input.
sig_incr_dbeat_cntr <= sig_good_strm_dbeat and
sig_enable_dbcntr;
-- Check to see if a max burst len of databeats have been
-- loaded into the FIFO
sig_dbc_max <= '1'
when (sig_burst_dbeat_cntr = MAX_BURST_DBEATS)
Else '0';
-- Start the counter over at a max burst len boundary or at
-- the end of the packet.
sig_clr_dbeat_cntr <= '1'
when (sig_dbc_max = '1' and
sig_good_strm_dbeat = '1' and
sig_enable_dbcntr = '1') or
(sig_good_tlast_dbeat = '1' and
sig_enable_dbcntr = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DBC_CMTR
--
-- Process Description:
-- The Databeat Counter keeps track of how many databeats have
-- been loaded into the Data FIFO. When a max burst worth of
-- databeats have been loaded (or a TLAST encountered), the
-- XD FIFO can be loaded with a transfer data set to be sent
-- to the IBTTCC.
--
-------------------------------------------------------------
IMP_DBC_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_dbeat_cntr = '1') then
sig_burst_dbeat_cntr <= (others => '0');
elsif (sig_incr_dbeat_cntr = '1') then
sig_burst_dbeat_cntr <= sig_burst_dbeat_cntr + DBC_ONE;
else
null; -- hold current value
end if;
end if;
end process IMP_DBC_CMTR;
----- Byte Counter Logic -----------------------------------------------
sig_clr_byte_cntr <= sig_clr_dbc_reg and
not(sig_good_strm_dbeat);
sig_ld_byte_cntr <= sig_clr_dbc_reg and
sig_good_strm_dbeat;
sig_incr_byte_cntr <= sig_good_strm_dbeat;
sig_byte_cntr_incr_value <= RESIZE(UNSIGNED(sig_stbs2sfcc_asserted), BYTE_CNTR_WIDTH);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BYTE_CMTR
--
-- Process Description:
-- Keeps a running byte count per burst packet loaded into the
-- xfer FIFO. It is based on the strobes set on the incoming
-- Stream dbeat.
--
-------------------------------------------------------------
IMP_BYTE_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_byte_cntr = '1') then
sig_byte_cntr <= (others => '0');
elsif (sig_ld_byte_cntr = '1') then
sig_byte_cntr <= sig_byte_cntr_incr_value;
elsif (sig_incr_byte_cntr = '1') then
sig_byte_cntr <= sig_byte_cntr + sig_byte_cntr_incr_value;
else
null; -- hold current value
end if;
end if;
end process IMP_BYTE_CMTR;
------------------------------------------------------------
-- Instance: I_IBTTCC_STBS_SET
--
-- Description:
-- Instance of the asserted strobe counter for the IBTTCC
-- interface.
--
------------------------------------------------------------
SAME_WIDTH_NO_DRE : if (C_ENABLE_DRE = 0 and (C_STREAM_DWIDTH = C_MMAP_DWIDTH)) generate
begin
I_IBTTCC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set_nodre
generic map (
C_STROBE_WIDTH => STRM_WSTB_WIDTH
)
port map (
tstrb_in => dre2ibtt_tstrb,
num_stbs_asserted => sig_stbs2sfcc_asserted -- 8 bit wide slv
);
end generate SAME_WIDTH_NO_DRE;
DIFF_WIDTH_OR_DRE : if (C_ENABLE_DRE /= 0 or (C_STREAM_DWIDTH /= C_MMAP_DWIDTH)) generate
begin
I_IBTTCC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set
generic map (
C_STROBE_WIDTH => STRM_WSTB_WIDTH
)
port map (
tstrb_in => dre2ibtt_tstrb,
num_stbs_asserted => sig_stbs2sfcc_asserted -- 8 bit wide slv
);
end generate DIFF_WIDTH_OR_DRE;
----- Xfer Descriptor FIFO Logic -----------------------------------------------
sig_push_xd_fifo <= sig_clr_dbc_reg ;
sig_pop_xd_fifo <= sig_pcc2ibtt_xfer_ready and
sig_xd_fifo_dvalid ;
sig_xd_fifo_data_in <= sig_dre2ibtt_eop_reg & -- (TLAST for the input Stream)
sig_dre2ibtt_tlast_reg & -- (TLAST for the IBTTCC command)
std_logic_vector(sig_byte_cntr); -- Number of bytes in this xfer
------------------------------------------------------------
-- Instance: I_XD_FIFO
--
-- Description:
-- Implement the Transfer Desciptor (XD) FIFO. This FIFO holds
-- the individual child command xfer descriptors used by the
-- IBTTCC to generate the commands sent to the Address Cntlr and
-- the Data Cntlr.
--
------------------------------------------------------------
I_XD_FIFO : entity axi_datamover_v5_1.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => XD_FIFO_WIDTH ,
C_DEPTH => XD_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => XD_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => 0 ,
C_NEED_ALMOST_FULL => 1 ,
C_USE_BLKMEM => 0 ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => mmap_reset ,
SFIFO_Clk => primary_aclk ,
SFIFO_Wr_en => sig_push_xd_fifo ,
SFIFO_Din => sig_xd_fifo_data_in ,
SFIFO_Rd_en => sig_pop_xd_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_xd_fifo_dvalid ,
SFIFO_Dout => sig_xd_fifo_data_out ,
SFIFO_Full => sig_xd_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => sig_tmp ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
----------------------------------------------------------------
-- Packing Logic ------------------------------------------
----------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_PACKING
--
-- If Generate Description:
-- Omits any packing logic in the Store and Forward module.
-- The Stream and MMap data widths are the same.
--
------------------------------------------------------------
OMIT_PACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate
begin
-- The data beat counter is always enabled when the packer
-- is omitted.
sig_enable_dbcntr <= '1';
sig_good_fifo_write <= sig_good_strm_dbeat;
sig_strm_in_ready <= not(sig_xd_fifo_full) and
not(sig_data_fifo_full) and
not (sig_tmp);
GEN_S2MM_TKEEP_ENABLE5 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Concatonate the Stream inputs into the single FIFO data
-- word input value
sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
dre2ibtt_tlast & -- Tlast marker
dre2ibtt_tstrb & -- TSTRB Value
dre2ibtt_tdata; -- data value
end generate GEN_S2MM_TKEEP_ENABLE5;
GEN_S2MM_TKEEP_DISABLE5 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Concatonate the Stream inputs into the single FIFO data
-- word input value
sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
dre2ibtt_tlast & -- Tlast marker
--dre2ibtt_tstrb & -- TSTRB Value
dre2ibtt_tdata; -- data value
end generate GEN_S2MM_TKEEP_DISABLE5;
end generate OMIT_PACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_PACKING
--
-- If Generate Description:
-- Includes packing logic in the IBTT Store and Forward
-- module. The MMap Data bus is wider than the Stream width.
--
------------------------------------------------------------
INCLUDE_PACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate
Constant TLAST_WIDTH : integer := 1; -- bit
Constant EOP_WIDTH : integer := 1; -- bit
Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH;
Constant STRB_SLICE_WIDTH : integer := STRM_WSTB_WIDTH;
Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH +
EOP_WIDTH;
Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO);
Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, OFFSET_CNTR_WIDTH);
Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH);
-- Types -----------------------------------------------------------------------------
type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(DATA_SLICE_WIDTH-1 downto 0);
type lsig_strb_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(STRB_SLICE_WIDTH-1 downto 0);
type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0);
-- local signals
signal lsig_data_slice_reg : lsig_data_slice_type;
signal lsig_strb_slice_reg : lsig_strb_slice_type;
signal lsig_flag_slice_reg : lsig_flag_slice_type;
signal lsig_reg_segment : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) := (others => '0');
signal lsig_segment_ld : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_segment_clr : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_0ffset_to_to_use : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_offset : std_logic := '0';
signal lsig_incr_offset : std_logic := '0';
signal lsig_offset_cntr_eq_max : std_logic := '0';
signal lsig_combined_data : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal lsig_combined_strb : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal lsig_tlast_or : std_logic := '0';
signal lsig_eop_or : std_logic := '0';
signal lsig_partial_tlast_or : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_partial_eop_or : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_packer_full : std_logic := '0';
signal lsig_packer_empty : std_logic := '0';
signal lsig_set_packer_full : std_logic := '0';
signal lsig_good_push2fifo : std_logic := '0';
signal lsig_first_dbeat : std_logic := '0';
begin
-- Generate the stream ready
sig_strm_in_ready <= not(sig_xd_fifo_full) and
not(sig_tmp) and
(not(lsig_packer_full) or
lsig_good_push2fifo) ;
-- Enable the Data Beat counter when the packer is
-- going full
sig_enable_dbcntr <= lsig_set_packer_full;
-- Assign the flag indicating that a fifo write is going
-- to occur at the next rising clock edge.
sig_good_fifo_write <= lsig_good_push2fifo;
GEN_S2MM_TKEEP_ENABLE6 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Format the composite FIFO input data word
sig_data_fifo_data_in <= lsig_eop_or & -- MS Bit
lsig_tlast_or &
lsig_combined_strb &
lsig_combined_data ; -- LS Bits
end generate GEN_S2MM_TKEEP_ENABLE6;
GEN_S2MM_TKEEP_DISABLE6 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Format the composite FIFO input data word
sig_data_fifo_data_in <= lsig_eop_or & -- MS Bit
lsig_tlast_or &
--lsig_combined_strb &
lsig_combined_data ; -- LS Bits
end generate GEN_S2MM_TKEEP_DISABLE6;
-- Generate a flag indicating a write to the DataFIFO
-- is going to complete
lsig_good_push2fifo <= lsig_packer_full and
not(sig_data_fifo_full);
-- Generate the control that loads the starting address
-- offset for the next input packet
lsig_ld_offset <= lsig_first_dbeat and
sig_good_strm_dbeat;
-- Generate the control for incrementing the offset counter
lsig_incr_offset <= sig_good_strm_dbeat;
-- Generate a flag indicating the packer input register
-- array is full or has loaded the last data beat of
-- the input paket
lsig_set_packer_full <= sig_good_strm_dbeat and
(dre2ibtt_tlast or
lsig_offset_cntr_eq_max);
-- Check to see if the offset counter has reached its max
-- value
lsig_offset_cntr_eq_max <= '1'
--when (lsig_0ffset_cntr = OFFSET_CNT_MAX)
when (lsig_0ffset_to_to_use = OFFSET_CNT_MAX)
Else '0';
-- Mux between the input start offset and the offset counter
-- output to use for the packer slice load control.
lsig_0ffset_to_to_use <= UNSIGNED(dre2ibtt_strt_addr_offset)
when (lsig_first_dbeat = '1')
Else lsig_0ffset_cntr;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_LD_MARKER
--
-- Process Description:
-- Implements the flop indicating the first databeat of
-- an input data packet.
--
-------------------------------------------------------------
IMP_OFFSET_LD_MARKER : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_first_dbeat <= '1';
elsif (sig_good_strm_dbeat = '1' and
dre2ibtt_tlast = '0') then
lsig_first_dbeat <= '0';
Elsif (sig_good_strm_dbeat = '1' and
dre2ibtt_tlast = '1') Then
lsig_first_dbeat <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_LD_MARKER;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_CNTR
--
-- Process Description:
-- Implements the address offset counter that is used to
-- steer the data loads into the packer register slices.
-- Note that the counter has to be loaded with the starting
-- offset plus one to sync up with the data input.
-------------------------------------------------------------
IMP_OFFSET_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_0ffset_cntr <= (others => '0');
Elsif (lsig_ld_offset = '1') Then
lsig_0ffset_cntr <= UNSIGNED(dre2ibtt_strt_addr_offset) + OFFSET_CNT_ONE;
elsif (lsig_incr_offset = '1') then
lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PACK_REG_FULL
--
-- Process Description:
-- Implements the Packer Register full/empty flags
--
-------------------------------------------------------------
IMP_PACK_REG_FULL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
Elsif (lsig_set_packer_full = '1' and
lsig_packer_full = '0') Then
lsig_packer_full <= '1';
lsig_packer_empty <= '0';
elsif (lsig_set_packer_full = '0' and
lsig_good_push2fifo = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PACK_REG_FULL;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_REG_SLICES
--
-- For Generate Description:
--
-- Implements the Packng Register Slices
--
--
------------------------------------------------------------
DO_REG_SLICES : for slice_index in 0 to MMAP2STRM_WIDTH_RATO-1 generate
begin
-- generate the register load enable for each slice segment based
-- on the address offset count value
lsig_segment_ld(slice_index) <= '1'
when (sig_good_strm_dbeat = '1' and
TO_INTEGER(lsig_0ffset_to_to_use) = slice_index)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DATA_SLICE
--
-- Process Description:
-- Implement a data register slice abd Strobe register slice
-- for the packer (upsizer).
--
-------------------------------------------------------------
IMP_DATA_SLICE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
lsig_strb_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_data_slice_reg(slice_index) <= dre2ibtt_tdata;
lsig_strb_slice_reg(slice_index) <= dre2ibtt_tstrb;
-- optional clear of slice reg
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
lsig_strb_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_DATA_SLICE;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FLAG_SLICE
--
-- Process Description:
-- Implement a flag register slice for the packer.
--
-------------------------------------------------------------
IMP_FLAG_SLICE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_flag_slice_reg(slice_index) <= dre2ibtt_tlast & -- bit 1
dre2ibtt_eop; -- bit 0
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_FLAG_SLICE;
end generate DO_REG_SLICES;
-- Do the OR functions of the Flags -------------------------------------
lsig_tlast_or <= lsig_partial_tlast_or(MMAP2STRM_WIDTH_RATO-1) ;
lsig_eop_or <= lsig_partial_eop_or(MMAP2STRM_WIDTH_RATO-1);
lsig_partial_tlast_or(0) <= lsig_flag_slice_reg(0)(1);
lsig_partial_eop_or(0) <= lsig_flag_slice_reg(0)(0);
------------------------------------------------------------
-- For Generate
--
-- Label: DO_FLAG_OR
--
-- For Generate Description:
-- Implement the OR of the TLAST and EOP Error flags.
--
--
--
------------------------------------------------------------
DO_FLAG_OR : for slice_index in 1 to MMAP2STRM_WIDTH_RATO-1 generate
begin
lsig_partial_tlast_or(slice_index) <= lsig_partial_tlast_or(slice_index-1) or
--lsig_partial_tlast_or(slice_index);
lsig_flag_slice_reg(slice_index)(1);
lsig_partial_eop_or(slice_index) <= lsig_partial_eop_or(slice_index-1) or
--lsig_partial_eop_or(slice_index);
lsig_flag_slice_reg(slice_index)(0);
end generate DO_FLAG_OR;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_DATA_COMBINER
--
-- For Generate Description:
-- Combines the Data Slice register and Strobe slice register
-- outputs into a single data and single strobe vector used for
-- input data to the Data FIFO.
--
--
------------------------------------------------------------
DO_DATA_COMBINER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate
begin
lsig_combined_data((slice_index*DATA_SLICE_WIDTH)-1 downto
(slice_index-1)*DATA_SLICE_WIDTH) <=
lsig_data_slice_reg(slice_index-1);
lsig_combined_strb((slice_index*STRB_SLICE_WIDTH)-1 downto
(slice_index-1)*STRB_SLICE_WIDTH) <=
lsig_strb_slice_reg(slice_index-1);
end generate DO_DATA_COMBINER;
end generate INCLUDE_PACKING;
-- Data FIFO Logic ------------------------------------------
--sig_push_data_fifo <= sig_good_strm_dbeat;
sig_push_data_fifo <= sig_good_fifo_write;
sig_pop_data_fifo <= sig_skidbuf_in_tready and
sig_data_fifo_dvalid;
-- -- Concatonate the Stream inputs into the single FIFO data in value
-- sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
-- dre2ibtt_tlast &
-- dre2ibtt_tstrb &
-- dre2ibtt_tdata;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_datamover_v5_1.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => 0 ,
C_NEED_ALMOST_FULL => 0 ,
C_USE_BLKMEM => 1 ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => mmap_reset ,
SFIFO_Clk => primary_aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => sig_data_fifo_rd_cnt ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => sig_data_fifo_wr_cnt ,
SFIFO_Rd_ack => open
);
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
GEN_S2MM_TKEEP_ENABLE7 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Rip the write strobe value from the FIFO output data
sig_fifo_tstrb_out <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-3 downto
C_MMAP_DWIDTH);
end generate GEN_S2MM_TKEEP_ENABLE7;
GEN_S2MM_TKEEP_DISBALE7 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
sig_fifo_tstrb_out <= (others => '1');
end generate GEN_S2MM_TKEEP_DISBALE7;
------------------------------------------------------------
-- Instance: I_WDC_STBS_SET
--
-- Description:
-- Instance of the asserted strobe counter for the WDC
-- interface.
--
------------------------------------------------------------
SAME_WIDTH_NO_DRE_WDC : if (C_ENABLE_DRE = 0 and (C_STREAM_DWIDTH = C_MMAP_DWIDTH)) generate
begin
I_WDC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set_nodre
generic map (
C_STROBE_WIDTH => MMAP_WSTB_WIDTH
)
port map (
tstrb_in => sig_fifo_tstrb_out,
num_stbs_asserted => sig_stbs2wdc_asserted
);
end generate SAME_WIDTH_NO_DRE_WDC;
DIFF_WIDTH_OR_DRE_WDC : if (C_ENABLE_DRE /= 0 or (C_STREAM_DWIDTH /= C_MMAP_DWIDTH)) generate
begin
I_WDC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set
generic map (
C_STROBE_WIDTH => MMAP_WSTB_WIDTH
)
port map (
tstrb_in => sig_fifo_tstrb_out,
num_stbs_asserted => sig_stbs2wdc_asserted
);
end generate DIFF_WIDTH_OR_DRE_WDC;
-------------------------------------------------------------------------
------- Isolation Skid Buffer Logic (needed for Fmax timing) -----------
-------------------------------------------------------------------------
-- Skid Buffer output assignments -----------
sig_skidbuf_out_tready <= sig_wdc2ibtt_tready;
sig_ibtt2wdc_tvalid <= sig_skidbuf_out_tvalid;
sig_ibtt2wdc_tdata <= sig_skidbuf_out_tdata(C_MMAP_DWIDTH-1 downto 0) ;
sig_ibtt2wdc_tstrb <= sig_skidbuf_out_tstrb(MMAP_WSTB_WIDTH-1 downto 0) ;
sig_ibtt2wdc_tlast <= sig_skidbuf_out_tlast ;
-- Rip the EOP marker from the MS bit of the skid output strobes
sig_ibtt2wdc_eop <= sig_skidbuf_out_tstrb(MMAP_WSTB_WIDTH) ;
-- Rip the upper 8 bits of the skid output data for the strobes asserted value
sig_ibtt2wdc_stbs_asserted <= sig_skidbuf_out_tdata(SKIDBUF2WDC_DWIDTH-1 downto
C_MMAP_DWIDTH);
-- Skid Buffer input assignments -----------
sig_skidbuf_in_tvalid <= sig_data_fifo_dvalid;
sig_skidbuf_in_eop <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-1);
sig_skidbuf_in_tlast <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-2);
-- Steal the extra input strobe bit and use it for the EOP marker
---- sig_skidbuf_in_tstrb <= sig_skidbuf_in_eop &
---- sig_data_fifo_data_out(DATA_FIFO_WIDTH-3 downto
---- C_MMAP_DWIDTH);
----
sig_skidbuf_in_tstrb <= sig_skidbuf_in_eop &
sig_fifo_tstrb_out;
-- Insert the Strobes Asserted count in the extra (MS) data byte
-- for the skid buffer
sig_skidbuf_in_tdata <= sig_stbs2wdc_asserted &
sig_data_fifo_data_out(C_MMAP_DWIDTH-1 downto 0);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(2) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_INDET_BTT_SKID_BUF
--
-- Description:
-- Instance for the Store and Forward isolation Skid Buffer
-- which is required to achieve Fmax timing. Note that this
-- skid buffer is 1 byte wider than the stream data width to
-- allow for the asserted strobes count to be passed through
-- it. The EOP marker is inserted in the extra strobe slot.
--
------------------------------------------------------------
I_INDET_BTT_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => SKIDBUF2WDC_DWIDTH
)
port map (
-- System Ports
aclk => primary_aclk ,
arst => mmap_reset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Stream Data Input)
s_valid => sig_skidbuf_in_tvalid ,
s_ready => sig_skidbuf_in_tready ,
s_data => sig_skidbuf_in_tdata ,
s_strb => sig_skidbuf_in_tstrb ,
s_last => sig_skidbuf_in_tlast ,
-- Master Side (Stream Data Output
m_valid => sig_skidbuf_out_tvalid ,
m_ready => sig_skidbuf_out_tready ,
m_data => sig_skidbuf_out_tdata ,
m_strb => sig_skidbuf_out_tstrb ,
m_last => sig_skidbuf_out_tlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(2) = '0' generate
begin
sig_skidbuf_out_tvalid <= sig_skidbuf_in_tvalid;
sig_skidbuf_in_tready <= sig_skidbuf_out_tready ;
sig_skidbuf_out_tdata <= sig_skidbuf_in_tdata ;
sig_skidbuf_out_tstrb <= sig_skidbuf_in_tstrb ;
sig_skidbuf_out_tlast <= sig_skidbuf_in_tlast ;
end generate DISABLE_AXIS_SKID;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_indet_btt.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_indet_btt.vhd
--
-- Description:
-- This file implements the DataMover S2MM Indeterminate BTT support module.
-- This Module keeps track of the incoming data stream and generates a transfer
-- descriptor for each AXI MMap Burst worth of data loaded in the Data FIFO.
-- This information is stored in a separate FIFO that the Predictive Transfer
-- Calculator fetches sequentially as it is generating commands for the AXI MMap
-- bus.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0;
Use lib_pkg_v1_0.lib_pkg.clog2;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_sfifo_autord;
use axi_datamover_v5_1.axi_datamover_skid_buf;
Use axi_datamover_v5_1.axi_datamover_stbs_set;
Use axi_datamover_v5_1.axi_datamover_stbs_set_nodre;
-------------------------------------------------------------------------------
entity axi_datamover_indet_btt is
generic (
C_SF_FIFO_DEPTH : integer range 128 to 8192 := 128;
-- Sets the depth of the Data FIFO
C_IBTT_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- Sets the width of the sf2pcc_xfer_bytes port
C_STRT_OFFSET_WIDTH : Integer range 1 to 7 := 2;
-- Sets the bit width of the starting address offset port
-- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH)
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates what is set as the allowed max burst length for AXI4
-- transfers
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the width of the AXI4 MMap data path
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Indicates the width of the stream data path
C_ENABLE_SKID_BUF : string := "11111";
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_DRE : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- Clock input --------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-----------------------------------------------------------
-- Write Data Controller I/O ----------------------------------------------------------
--
ibtt2wdc_stbs_asserted : Out std_logic_vector(7 downto 0); --
-- Indicates the number of asserted WSTRB bits for the --
-- associated output stream data beat --
--
ibtt2wdc_eop : Out std_logic; --
-- Write End of Packet flag output to Write Data Controller --
--
ibtt2wdc_tdata : Out std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- Write DATA output to Write Data Controller --
--
ibtt2wdc_tstrb : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
-- Write DATA output to Write Data Controller --
--
ibtt2wdc_tlast : Out std_logic; --
-- Write LAST output to Write Data Controller --
--
ibtt2wdc_tvalid : Out std_logic; --
-- Write VALID output to Write Data Controller --
--
wdc2ibtt_tready : In std_logic; --
-- Write READY input from Write Data Controller --
---------------------------------------------------------------------------------------
-- DRE Stream In ----------------------------------------------------------------------
--
dre2ibtt_tvalid : In std_logic; --
-- DRE Stream VALID Output --
--
ibtt2dre_tready : Out Std_logic; --
-- DRE Stream READY input --
--
dre2ibtt_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- DRE Stream DATA input --
--
dre2ibtt_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- DRE Stream STRB input --
--
dre2ibtt_tlast : In std_logic; --
-- DRE Xfer LAST input --
--
dre2ibtt_eop : In std_logic; --
-- DRE Stream end of Stream packet flag --
--------------------------------------------------------------------------------------
-- Starting Address Offset Input -------------------------------------------------
--
dre2ibtt_strt_addr_offset : In std_logic_vector(C_STRT_OFFSET_WIDTH-1 downto 0); --
-- Used by Packing logic to set the initial data slice position for the --
-- packing operation. Packing is only needed if the MMap and Stream Data --
-- widths do not match. This input is sampled on the first valid DRE Stream In --
-- input databeat of a packet. --
-- --
-----------------------------------------------------------------------------------
-- Store and Forward Command Calculator Interface ---------------------------------------
--
sf2pcc_xfer_valid : Out std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the XFER_DESCR_FIFO --
--
pcc2sf_xfer_ready : in std_logic; --
-- Indicates that a full burst of data has been loaded into the data FIFO --
--
--
sf2pcc_cmd_cmplt : Out std_logic; --
-- Indicates that this is the final xfer for an associated command loaded --
-- into the Realigner by the IBTTCC interface --
--
--
sf2pcc_packet_eop : Out std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor --
--
sf2pcc_xfer_bytes : Out std_logic_vector(C_IBTT_XFER_BYTES_WIDTH-1 downto 0) --
-- This byte count is used by the IBTTCC for setting up the spawned child --
-- commands. The IBTTCC must use this count to generate the appropriate --
-- LEN value to put out on the AXI4 Write Addr Channel and the WSTRB on the AXI4 --
-- Write Data Channel. --
-----------------------------------------------------------------------------------------
);
end entity axi_datamover_indet_btt;
architecture implementation of axi_datamover_indet_btt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_cntr_width
--
-- Function Description:
-- This function calculates the needed counter bit width from the
-- number of count sates needed (input).
--
-------------------------------------------------------------------
function funct_get_cntr_width (num_cnt_values : integer) return integer is
Variable temp_cnt_width : Integer := 0;
begin
if (num_cnt_values <= 2) then
temp_cnt_width := 1;
elsif (num_cnt_values <= 4) then
temp_cnt_width := 2;
elsif (num_cnt_values <= 8) then
temp_cnt_width := 3;
elsif (num_cnt_values <= 16) then
temp_cnt_width := 4;
elsif (num_cnt_values <= 32) then
temp_cnt_width := 5;
elsif (num_cnt_values <= 64) then
temp_cnt_width := 6;
elsif (num_cnt_values <= 128) then
temp_cnt_width := 7;
else
temp_cnt_width := 8;
end if;
Return (temp_cnt_width);
end function funct_get_cntr_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 4 and 32. THis is used for sizing the SRL based XD FIFO.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 4) then
temp_pwr2 := 4;
elsif (input_value <= 8) then
temp_pwr2 := 8;
elsif (input_value <= 16) then
temp_pwr2 := 16;
else
temp_pwr2 := 32;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_PER_BYTE : integer := 8;
Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH;
Constant STRM_WSTB_WIDTH : integer := C_STREAM_DWIDTH/BITS_PER_BYTE;
Constant MMAP_WSTB_WIDTH : integer := C_MMAP_DWIDTH/BITS_PER_BYTE;
Constant STRM_STRBS_ASSERTED_WIDTH : integer := clog2(STRM_WSTB_WIDTH)+1;
-- Constant DATA_FIFO_DFACTOR : integer := 4; -- set buffer to 4 times the Max allowed Burst Length
-- Constant DATA_FIFO_DEPTH : integer := C_MAX_BURST_LEN*DATA_FIFO_DFACTOR;
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH+MMAP_WSTB_WIDTH*C_ENABLE_S2MM_TKEEP+2;
-- Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH+STRB_CNTR_WIDTH+2;
Constant DATA_FIFO_CNT_WIDTH : integer := clog2(DATA_FIFO_DEPTH)+1;
Constant BURST_CNTR_WIDTH : integer := clog2(C_MAX_BURST_LEN);
Constant MAX_BURST_DBEATS : Unsigned(BURST_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BURST_CNTR_WIDTH);
Constant DBC_ONE : Unsigned(BURST_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, BURST_CNTR_WIDTH);
Constant BYTE_CNTR_WIDTH : integer := C_IBTT_XFER_BYTES_WIDTH;
Constant BYTES_PER_MMAP_DBEAT : integer := C_MMAP_DWIDTH/BITS_PER_BYTE;
Constant BYTES_PER_STRM_DBEAT : integer := C_STREAM_DWIDTH/BITS_PER_BYTE;
--Constant MAX_BYTE_CNT : integer := C_MAX_BURST_LEN*BYTES_PER_DBEAT;
--Constant NUM_STRB_BITS : integer := BYTES_PER_DBEAT;
Constant BCNTR_ONE : Unsigned(BYTE_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, BYTE_CNTR_WIDTH);
--Constant XD_FIFO_DEPTH : integer := 16;
Constant XD_FIFO_DEPTH : integer := funct_rnd2pwr_of_2(DATA_FIFO_DEPTH/C_MAX_BURST_LEN);
Constant XD_FIFO_CNT_WIDTH : integer := clog2(XD_FIFO_DEPTH)+1;
Constant XD_FIFO_WIDTH : integer := BYTE_CNTR_WIDTH+2;
Constant MMAP_STBS_ASSERTED_WIDTH : integer := 8;
Constant SKIDBUF2WDC_DWIDTH : integer := C_MMAP_DWIDTH + MMAP_STBS_ASSERTED_WIDTH;
Constant SKIDBUF2WDC_STRB_WIDTH : integer := SKIDBUF2WDC_DWIDTH/BITS_PER_BYTE;
--Constant NUM_ZEROS_WIDTH : integer := MMAP_STBS_ASSERTED_WIDTH;
Constant STRB_CNTR_WIDTH : integer := MMAP_STBS_ASSERTED_WIDTH;
-- Signals
signal sig_wdc2ibtt_tready : std_logic := '0';
signal sig_ibtt2wdc_tvalid : std_logic := '0';
signal sig_ibtt2wdc_tdata : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tstrb : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tlast : std_logic := '0';
signal sig_ibtt2wdc_eop : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_rd_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_wr_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_push_xd_fifo : std_logic := '0';
signal sig_pop_xd_fifo : std_logic := '0';
signal sig_xd_fifo_data_in : std_logic_vector(XD_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_xd_fifo_data_out : std_logic_vector(XD_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_xd_fifo_dvalid : std_logic := '0';
signal sig_xd_fifo_full : std_logic := '0';
signal sig_tmp : std_logic := '0';
signal sig_strm_in_ready : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_good_tlast_dbeat : std_logic := '0';
signal sig_dre2ibtt_tlast_reg : std_logic := '0';
signal sig_dre2ibtt_eop_reg : std_logic := '0';
signal sig_burst_dbeat_cntr : Unsigned(BURST_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_dbeat_cntr : std_logic := '0';
signal sig_clr_dbeat_cntr : std_logic := '0';
signal sig_clr_dbc_reg : std_logic := '0';
signal sig_dbc_max : std_logic := '0';
signal sig_pcc2ibtt_xfer_ready : std_logic := '0';
signal sig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_byte_cntr : std_logic := '0';
signal sig_incr_byte_cntr : std_logic := '0';
signal sig_clr_byte_cntr : std_logic := '0';
signal sig_fifo_tstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_num_ls_zeros : integer range 0 to STRM_WSTB_WIDTH := 0;
signal sig_ls_assert_found : std_logic := '0';
signal sig_num_ms_zeros : integer range 0 to STRM_WSTB_WIDTH := 0;
signal sig_ms_assert_found : std_logic := '0';
-- signal sig_num_zeros : unsigned(NUM_ZEROS_WIDTH-1 downto 0) := (others => '0');
-- signal sig_num_ones : unsigned(NUM_ZEROS_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs2sfcc_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs2wdc_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_stbs_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tready : std_logic := '0';
signal sig_skidbuf_in_tvalid : std_logic := '0';
signal sig_skidbuf_in_tdata : std_logic_vector(SKIDBUF2WDC_DWIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tstrb : std_logic_vector(SKIDBUF2WDC_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tlast : std_logic := '0';
signal sig_skidbuf_in_eop : std_logic := '0';
signal sig_skidbuf_out_tready : std_logic := '0';
signal sig_skidbuf_out_tvalid : std_logic := '0';
signal sig_skidbuf_out_tdata : std_logic_vector(SKIDBUF2WDC_DWIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_out_tstrb : std_logic_vector(SKIDBUF2WDC_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_out_tlast : std_logic := '0';
signal sig_skidbuf_out_eop : std_logic := '0';
signal sig_enable_dbcntr : std_logic := '0';
signal sig_good_fifo_write : std_logic := '0';
begin --(architecture implementation)
-- Write Data Controller I/O
sig_wdc2ibtt_tready <= wdc2ibtt_tready ;
ibtt2wdc_tvalid <= sig_ibtt2wdc_tvalid ;
ibtt2wdc_tdata <= sig_ibtt2wdc_tdata ;
ibtt2wdc_tstrb <= sig_ibtt2wdc_tstrb ;
ibtt2wdc_tlast <= sig_ibtt2wdc_tlast ;
ibtt2wdc_eop <= sig_ibtt2wdc_eop ;
ibtt2wdc_stbs_asserted <= sig_ibtt2wdc_stbs_asserted;
-- PCC I/O
sf2pcc_xfer_valid <= sig_xd_fifo_dvalid;
sig_pcc2ibtt_xfer_ready <= pcc2sf_xfer_ready;
sf2pcc_packet_eop <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH+1);
sf2pcc_cmd_cmplt <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH);
sf2pcc_xfer_bytes <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH-1 downto 0);
-- DRE Stream In
ibtt2dre_tready <= sig_strm_in_ready;
-- sig_strm_in_ready <= not(sig_xd_fifo_full) and
-- not(sig_data_fifo_full);
sig_good_strm_dbeat <= dre2ibtt_tvalid and
sig_strm_in_ready;
sig_good_tlast_dbeat <= sig_good_strm_dbeat and
dre2ibtt_tlast;
-- Burst Packet Counter Logic -------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_DBC_STUFF
--
-- Process Description:
-- Just a register for data beat counter signals.
--
-------------------------------------------------------------
REG_DBC_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dre2ibtt_tlast_reg <= '0';
sig_dre2ibtt_eop_reg <= '0';
sig_clr_dbc_reg <= '0';
else
sig_dre2ibtt_tlast_reg <= dre2ibtt_tlast;
sig_dre2ibtt_eop_reg <= dre2ibtt_eop;
sig_clr_dbc_reg <= sig_clr_dbeat_cntr;
end if;
end if;
end process REG_DBC_STUFF;
-- sig_clr_dbc_reg <= sig_clr_dbeat_cntr;
-- Increment the dataBeat counter on a data fifo wide
-- load condition. If packer logic is enabled, this will
-- only occur when a full fifo data width has been collected
-- from the Stream input.
sig_incr_dbeat_cntr <= sig_good_strm_dbeat and
sig_enable_dbcntr;
-- Check to see if a max burst len of databeats have been
-- loaded into the FIFO
sig_dbc_max <= '1'
when (sig_burst_dbeat_cntr = MAX_BURST_DBEATS)
Else '0';
-- Start the counter over at a max burst len boundary or at
-- the end of the packet.
sig_clr_dbeat_cntr <= '1'
when (sig_dbc_max = '1' and
sig_good_strm_dbeat = '1' and
sig_enable_dbcntr = '1') or
(sig_good_tlast_dbeat = '1' and
sig_enable_dbcntr = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DBC_CMTR
--
-- Process Description:
-- The Databeat Counter keeps track of how many databeats have
-- been loaded into the Data FIFO. When a max burst worth of
-- databeats have been loaded (or a TLAST encountered), the
-- XD FIFO can be loaded with a transfer data set to be sent
-- to the IBTTCC.
--
-------------------------------------------------------------
IMP_DBC_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_dbeat_cntr = '1') then
sig_burst_dbeat_cntr <= (others => '0');
elsif (sig_incr_dbeat_cntr = '1') then
sig_burst_dbeat_cntr <= sig_burst_dbeat_cntr + DBC_ONE;
else
null; -- hold current value
end if;
end if;
end process IMP_DBC_CMTR;
----- Byte Counter Logic -----------------------------------------------
sig_clr_byte_cntr <= sig_clr_dbc_reg and
not(sig_good_strm_dbeat);
sig_ld_byte_cntr <= sig_clr_dbc_reg and
sig_good_strm_dbeat;
sig_incr_byte_cntr <= sig_good_strm_dbeat;
sig_byte_cntr_incr_value <= RESIZE(UNSIGNED(sig_stbs2sfcc_asserted), BYTE_CNTR_WIDTH);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BYTE_CMTR
--
-- Process Description:
-- Keeps a running byte count per burst packet loaded into the
-- xfer FIFO. It is based on the strobes set on the incoming
-- Stream dbeat.
--
-------------------------------------------------------------
IMP_BYTE_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_byte_cntr = '1') then
sig_byte_cntr <= (others => '0');
elsif (sig_ld_byte_cntr = '1') then
sig_byte_cntr <= sig_byte_cntr_incr_value;
elsif (sig_incr_byte_cntr = '1') then
sig_byte_cntr <= sig_byte_cntr + sig_byte_cntr_incr_value;
else
null; -- hold current value
end if;
end if;
end process IMP_BYTE_CMTR;
------------------------------------------------------------
-- Instance: I_IBTTCC_STBS_SET
--
-- Description:
-- Instance of the asserted strobe counter for the IBTTCC
-- interface.
--
------------------------------------------------------------
SAME_WIDTH_NO_DRE : if (C_ENABLE_DRE = 0 and (C_STREAM_DWIDTH = C_MMAP_DWIDTH)) generate
begin
I_IBTTCC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set_nodre
generic map (
C_STROBE_WIDTH => STRM_WSTB_WIDTH
)
port map (
tstrb_in => dre2ibtt_tstrb,
num_stbs_asserted => sig_stbs2sfcc_asserted -- 8 bit wide slv
);
end generate SAME_WIDTH_NO_DRE;
DIFF_WIDTH_OR_DRE : if (C_ENABLE_DRE /= 0 or (C_STREAM_DWIDTH /= C_MMAP_DWIDTH)) generate
begin
I_IBTTCC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set
generic map (
C_STROBE_WIDTH => STRM_WSTB_WIDTH
)
port map (
tstrb_in => dre2ibtt_tstrb,
num_stbs_asserted => sig_stbs2sfcc_asserted -- 8 bit wide slv
);
end generate DIFF_WIDTH_OR_DRE;
----- Xfer Descriptor FIFO Logic -----------------------------------------------
sig_push_xd_fifo <= sig_clr_dbc_reg ;
sig_pop_xd_fifo <= sig_pcc2ibtt_xfer_ready and
sig_xd_fifo_dvalid ;
sig_xd_fifo_data_in <= sig_dre2ibtt_eop_reg & -- (TLAST for the input Stream)
sig_dre2ibtt_tlast_reg & -- (TLAST for the IBTTCC command)
std_logic_vector(sig_byte_cntr); -- Number of bytes in this xfer
------------------------------------------------------------
-- Instance: I_XD_FIFO
--
-- Description:
-- Implement the Transfer Desciptor (XD) FIFO. This FIFO holds
-- the individual child command xfer descriptors used by the
-- IBTTCC to generate the commands sent to the Address Cntlr and
-- the Data Cntlr.
--
------------------------------------------------------------
I_XD_FIFO : entity axi_datamover_v5_1.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => XD_FIFO_WIDTH ,
C_DEPTH => XD_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => XD_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => 0 ,
C_NEED_ALMOST_FULL => 1 ,
C_USE_BLKMEM => 0 ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => mmap_reset ,
SFIFO_Clk => primary_aclk ,
SFIFO_Wr_en => sig_push_xd_fifo ,
SFIFO_Din => sig_xd_fifo_data_in ,
SFIFO_Rd_en => sig_pop_xd_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_xd_fifo_dvalid ,
SFIFO_Dout => sig_xd_fifo_data_out ,
SFIFO_Full => sig_xd_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => sig_tmp ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
----------------------------------------------------------------
-- Packing Logic ------------------------------------------
----------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_PACKING
--
-- If Generate Description:
-- Omits any packing logic in the Store and Forward module.
-- The Stream and MMap data widths are the same.
--
------------------------------------------------------------
OMIT_PACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate
begin
-- The data beat counter is always enabled when the packer
-- is omitted.
sig_enable_dbcntr <= '1';
sig_good_fifo_write <= sig_good_strm_dbeat;
sig_strm_in_ready <= not(sig_xd_fifo_full) and
not(sig_data_fifo_full) and
not (sig_tmp);
GEN_S2MM_TKEEP_ENABLE5 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Concatonate the Stream inputs into the single FIFO data
-- word input value
sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
dre2ibtt_tlast & -- Tlast marker
dre2ibtt_tstrb & -- TSTRB Value
dre2ibtt_tdata; -- data value
end generate GEN_S2MM_TKEEP_ENABLE5;
GEN_S2MM_TKEEP_DISABLE5 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Concatonate the Stream inputs into the single FIFO data
-- word input value
sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
dre2ibtt_tlast & -- Tlast marker
--dre2ibtt_tstrb & -- TSTRB Value
dre2ibtt_tdata; -- data value
end generate GEN_S2MM_TKEEP_DISABLE5;
end generate OMIT_PACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_PACKING
--
-- If Generate Description:
-- Includes packing logic in the IBTT Store and Forward
-- module. The MMap Data bus is wider than the Stream width.
--
------------------------------------------------------------
INCLUDE_PACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate
Constant TLAST_WIDTH : integer := 1; -- bit
Constant EOP_WIDTH : integer := 1; -- bit
Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH;
Constant STRB_SLICE_WIDTH : integer := STRM_WSTB_WIDTH;
Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH +
EOP_WIDTH;
Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO);
Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, OFFSET_CNTR_WIDTH);
Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH);
-- Types -----------------------------------------------------------------------------
type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(DATA_SLICE_WIDTH-1 downto 0);
type lsig_strb_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(STRB_SLICE_WIDTH-1 downto 0);
type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0);
-- local signals
signal lsig_data_slice_reg : lsig_data_slice_type;
signal lsig_strb_slice_reg : lsig_strb_slice_type;
signal lsig_flag_slice_reg : lsig_flag_slice_type;
signal lsig_reg_segment : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) := (others => '0');
signal lsig_segment_ld : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_segment_clr : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_0ffset_to_to_use : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_offset : std_logic := '0';
signal lsig_incr_offset : std_logic := '0';
signal lsig_offset_cntr_eq_max : std_logic := '0';
signal lsig_combined_data : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal lsig_combined_strb : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal lsig_tlast_or : std_logic := '0';
signal lsig_eop_or : std_logic := '0';
signal lsig_partial_tlast_or : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_partial_eop_or : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_packer_full : std_logic := '0';
signal lsig_packer_empty : std_logic := '0';
signal lsig_set_packer_full : std_logic := '0';
signal lsig_good_push2fifo : std_logic := '0';
signal lsig_first_dbeat : std_logic := '0';
begin
-- Generate the stream ready
sig_strm_in_ready <= not(sig_xd_fifo_full) and
not(sig_tmp) and
(not(lsig_packer_full) or
lsig_good_push2fifo) ;
-- Enable the Data Beat counter when the packer is
-- going full
sig_enable_dbcntr <= lsig_set_packer_full;
-- Assign the flag indicating that a fifo write is going
-- to occur at the next rising clock edge.
sig_good_fifo_write <= lsig_good_push2fifo;
GEN_S2MM_TKEEP_ENABLE6 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Format the composite FIFO input data word
sig_data_fifo_data_in <= lsig_eop_or & -- MS Bit
lsig_tlast_or &
lsig_combined_strb &
lsig_combined_data ; -- LS Bits
end generate GEN_S2MM_TKEEP_ENABLE6;
GEN_S2MM_TKEEP_DISABLE6 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Format the composite FIFO input data word
sig_data_fifo_data_in <= lsig_eop_or & -- MS Bit
lsig_tlast_or &
--lsig_combined_strb &
lsig_combined_data ; -- LS Bits
end generate GEN_S2MM_TKEEP_DISABLE6;
-- Generate a flag indicating a write to the DataFIFO
-- is going to complete
lsig_good_push2fifo <= lsig_packer_full and
not(sig_data_fifo_full);
-- Generate the control that loads the starting address
-- offset for the next input packet
lsig_ld_offset <= lsig_first_dbeat and
sig_good_strm_dbeat;
-- Generate the control for incrementing the offset counter
lsig_incr_offset <= sig_good_strm_dbeat;
-- Generate a flag indicating the packer input register
-- array is full or has loaded the last data beat of
-- the input paket
lsig_set_packer_full <= sig_good_strm_dbeat and
(dre2ibtt_tlast or
lsig_offset_cntr_eq_max);
-- Check to see if the offset counter has reached its max
-- value
lsig_offset_cntr_eq_max <= '1'
--when (lsig_0ffset_cntr = OFFSET_CNT_MAX)
when (lsig_0ffset_to_to_use = OFFSET_CNT_MAX)
Else '0';
-- Mux between the input start offset and the offset counter
-- output to use for the packer slice load control.
lsig_0ffset_to_to_use <= UNSIGNED(dre2ibtt_strt_addr_offset)
when (lsig_first_dbeat = '1')
Else lsig_0ffset_cntr;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_LD_MARKER
--
-- Process Description:
-- Implements the flop indicating the first databeat of
-- an input data packet.
--
-------------------------------------------------------------
IMP_OFFSET_LD_MARKER : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_first_dbeat <= '1';
elsif (sig_good_strm_dbeat = '1' and
dre2ibtt_tlast = '0') then
lsig_first_dbeat <= '0';
Elsif (sig_good_strm_dbeat = '1' and
dre2ibtt_tlast = '1') Then
lsig_first_dbeat <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_LD_MARKER;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_CNTR
--
-- Process Description:
-- Implements the address offset counter that is used to
-- steer the data loads into the packer register slices.
-- Note that the counter has to be loaded with the starting
-- offset plus one to sync up with the data input.
-------------------------------------------------------------
IMP_OFFSET_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_0ffset_cntr <= (others => '0');
Elsif (lsig_ld_offset = '1') Then
lsig_0ffset_cntr <= UNSIGNED(dre2ibtt_strt_addr_offset) + OFFSET_CNT_ONE;
elsif (lsig_incr_offset = '1') then
lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PACK_REG_FULL
--
-- Process Description:
-- Implements the Packer Register full/empty flags
--
-------------------------------------------------------------
IMP_PACK_REG_FULL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
Elsif (lsig_set_packer_full = '1' and
lsig_packer_full = '0') Then
lsig_packer_full <= '1';
lsig_packer_empty <= '0';
elsif (lsig_set_packer_full = '0' and
lsig_good_push2fifo = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PACK_REG_FULL;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_REG_SLICES
--
-- For Generate Description:
--
-- Implements the Packng Register Slices
--
--
------------------------------------------------------------
DO_REG_SLICES : for slice_index in 0 to MMAP2STRM_WIDTH_RATO-1 generate
begin
-- generate the register load enable for each slice segment based
-- on the address offset count value
lsig_segment_ld(slice_index) <= '1'
when (sig_good_strm_dbeat = '1' and
TO_INTEGER(lsig_0ffset_to_to_use) = slice_index)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DATA_SLICE
--
-- Process Description:
-- Implement a data register slice abd Strobe register slice
-- for the packer (upsizer).
--
-------------------------------------------------------------
IMP_DATA_SLICE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
lsig_strb_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_data_slice_reg(slice_index) <= dre2ibtt_tdata;
lsig_strb_slice_reg(slice_index) <= dre2ibtt_tstrb;
-- optional clear of slice reg
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
lsig_strb_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_DATA_SLICE;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FLAG_SLICE
--
-- Process Description:
-- Implement a flag register slice for the packer.
--
-------------------------------------------------------------
IMP_FLAG_SLICE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_flag_slice_reg(slice_index) <= dre2ibtt_tlast & -- bit 1
dre2ibtt_eop; -- bit 0
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_FLAG_SLICE;
end generate DO_REG_SLICES;
-- Do the OR functions of the Flags -------------------------------------
lsig_tlast_or <= lsig_partial_tlast_or(MMAP2STRM_WIDTH_RATO-1) ;
lsig_eop_or <= lsig_partial_eop_or(MMAP2STRM_WIDTH_RATO-1);
lsig_partial_tlast_or(0) <= lsig_flag_slice_reg(0)(1);
lsig_partial_eop_or(0) <= lsig_flag_slice_reg(0)(0);
------------------------------------------------------------
-- For Generate
--
-- Label: DO_FLAG_OR
--
-- For Generate Description:
-- Implement the OR of the TLAST and EOP Error flags.
--
--
--
------------------------------------------------------------
DO_FLAG_OR : for slice_index in 1 to MMAP2STRM_WIDTH_RATO-1 generate
begin
lsig_partial_tlast_or(slice_index) <= lsig_partial_tlast_or(slice_index-1) or
--lsig_partial_tlast_or(slice_index);
lsig_flag_slice_reg(slice_index)(1);
lsig_partial_eop_or(slice_index) <= lsig_partial_eop_or(slice_index-1) or
--lsig_partial_eop_or(slice_index);
lsig_flag_slice_reg(slice_index)(0);
end generate DO_FLAG_OR;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_DATA_COMBINER
--
-- For Generate Description:
-- Combines the Data Slice register and Strobe slice register
-- outputs into a single data and single strobe vector used for
-- input data to the Data FIFO.
--
--
------------------------------------------------------------
DO_DATA_COMBINER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate
begin
lsig_combined_data((slice_index*DATA_SLICE_WIDTH)-1 downto
(slice_index-1)*DATA_SLICE_WIDTH) <=
lsig_data_slice_reg(slice_index-1);
lsig_combined_strb((slice_index*STRB_SLICE_WIDTH)-1 downto
(slice_index-1)*STRB_SLICE_WIDTH) <=
lsig_strb_slice_reg(slice_index-1);
end generate DO_DATA_COMBINER;
end generate INCLUDE_PACKING;
-- Data FIFO Logic ------------------------------------------
--sig_push_data_fifo <= sig_good_strm_dbeat;
sig_push_data_fifo <= sig_good_fifo_write;
sig_pop_data_fifo <= sig_skidbuf_in_tready and
sig_data_fifo_dvalid;
-- -- Concatonate the Stream inputs into the single FIFO data in value
-- sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
-- dre2ibtt_tlast &
-- dre2ibtt_tstrb &
-- dre2ibtt_tdata;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_datamover_v5_1.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => 0 ,
C_NEED_ALMOST_FULL => 0 ,
C_USE_BLKMEM => 1 ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => mmap_reset ,
SFIFO_Clk => primary_aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => sig_data_fifo_rd_cnt ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => sig_data_fifo_wr_cnt ,
SFIFO_Rd_ack => open
);
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
GEN_S2MM_TKEEP_ENABLE7 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Rip the write strobe value from the FIFO output data
sig_fifo_tstrb_out <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-3 downto
C_MMAP_DWIDTH);
end generate GEN_S2MM_TKEEP_ENABLE7;
GEN_S2MM_TKEEP_DISBALE7 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
sig_fifo_tstrb_out <= (others => '1');
end generate GEN_S2MM_TKEEP_DISBALE7;
------------------------------------------------------------
-- Instance: I_WDC_STBS_SET
--
-- Description:
-- Instance of the asserted strobe counter for the WDC
-- interface.
--
------------------------------------------------------------
SAME_WIDTH_NO_DRE_WDC : if (C_ENABLE_DRE = 0 and (C_STREAM_DWIDTH = C_MMAP_DWIDTH)) generate
begin
I_WDC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set_nodre
generic map (
C_STROBE_WIDTH => MMAP_WSTB_WIDTH
)
port map (
tstrb_in => sig_fifo_tstrb_out,
num_stbs_asserted => sig_stbs2wdc_asserted
);
end generate SAME_WIDTH_NO_DRE_WDC;
DIFF_WIDTH_OR_DRE_WDC : if (C_ENABLE_DRE /= 0 or (C_STREAM_DWIDTH /= C_MMAP_DWIDTH)) generate
begin
I_WDC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set
generic map (
C_STROBE_WIDTH => MMAP_WSTB_WIDTH
)
port map (
tstrb_in => sig_fifo_tstrb_out,
num_stbs_asserted => sig_stbs2wdc_asserted
);
end generate DIFF_WIDTH_OR_DRE_WDC;
-------------------------------------------------------------------------
------- Isolation Skid Buffer Logic (needed for Fmax timing) -----------
-------------------------------------------------------------------------
-- Skid Buffer output assignments -----------
sig_skidbuf_out_tready <= sig_wdc2ibtt_tready;
sig_ibtt2wdc_tvalid <= sig_skidbuf_out_tvalid;
sig_ibtt2wdc_tdata <= sig_skidbuf_out_tdata(C_MMAP_DWIDTH-1 downto 0) ;
sig_ibtt2wdc_tstrb <= sig_skidbuf_out_tstrb(MMAP_WSTB_WIDTH-1 downto 0) ;
sig_ibtt2wdc_tlast <= sig_skidbuf_out_tlast ;
-- Rip the EOP marker from the MS bit of the skid output strobes
sig_ibtt2wdc_eop <= sig_skidbuf_out_tstrb(MMAP_WSTB_WIDTH) ;
-- Rip the upper 8 bits of the skid output data for the strobes asserted value
sig_ibtt2wdc_stbs_asserted <= sig_skidbuf_out_tdata(SKIDBUF2WDC_DWIDTH-1 downto
C_MMAP_DWIDTH);
-- Skid Buffer input assignments -----------
sig_skidbuf_in_tvalid <= sig_data_fifo_dvalid;
sig_skidbuf_in_eop <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-1);
sig_skidbuf_in_tlast <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-2);
-- Steal the extra input strobe bit and use it for the EOP marker
---- sig_skidbuf_in_tstrb <= sig_skidbuf_in_eop &
---- sig_data_fifo_data_out(DATA_FIFO_WIDTH-3 downto
---- C_MMAP_DWIDTH);
----
sig_skidbuf_in_tstrb <= sig_skidbuf_in_eop &
sig_fifo_tstrb_out;
-- Insert the Strobes Asserted count in the extra (MS) data byte
-- for the skid buffer
sig_skidbuf_in_tdata <= sig_stbs2wdc_asserted &
sig_data_fifo_data_out(C_MMAP_DWIDTH-1 downto 0);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(2) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_INDET_BTT_SKID_BUF
--
-- Description:
-- Instance for the Store and Forward isolation Skid Buffer
-- which is required to achieve Fmax timing. Note that this
-- skid buffer is 1 byte wider than the stream data width to
-- allow for the asserted strobes count to be passed through
-- it. The EOP marker is inserted in the extra strobe slot.
--
------------------------------------------------------------
I_INDET_BTT_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => SKIDBUF2WDC_DWIDTH
)
port map (
-- System Ports
aclk => primary_aclk ,
arst => mmap_reset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Stream Data Input)
s_valid => sig_skidbuf_in_tvalid ,
s_ready => sig_skidbuf_in_tready ,
s_data => sig_skidbuf_in_tdata ,
s_strb => sig_skidbuf_in_tstrb ,
s_last => sig_skidbuf_in_tlast ,
-- Master Side (Stream Data Output
m_valid => sig_skidbuf_out_tvalid ,
m_ready => sig_skidbuf_out_tready ,
m_data => sig_skidbuf_out_tdata ,
m_strb => sig_skidbuf_out_tstrb ,
m_last => sig_skidbuf_out_tlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(2) = '0' generate
begin
sig_skidbuf_out_tvalid <= sig_skidbuf_in_tvalid;
sig_skidbuf_in_tready <= sig_skidbuf_out_tready ;
sig_skidbuf_out_tdata <= sig_skidbuf_in_tdata ;
sig_skidbuf_out_tstrb <= sig_skidbuf_in_tstrb ;
sig_skidbuf_out_tlast <= sig_skidbuf_in_tlast ;
end generate DISABLE_AXIS_SKID;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_indet_btt.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_indet_btt.vhd
--
-- Description:
-- This file implements the DataMover S2MM Indeterminate BTT support module.
-- This Module keeps track of the incoming data stream and generates a transfer
-- descriptor for each AXI MMap Burst worth of data loaded in the Data FIFO.
-- This information is stored in a separate FIFO that the Predictive Transfer
-- Calculator fetches sequentially as it is generating commands for the AXI MMap
-- bus.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0;
Use lib_pkg_v1_0.lib_pkg.clog2;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_sfifo_autord;
use axi_datamover_v5_1.axi_datamover_skid_buf;
Use axi_datamover_v5_1.axi_datamover_stbs_set;
Use axi_datamover_v5_1.axi_datamover_stbs_set_nodre;
-------------------------------------------------------------------------------
entity axi_datamover_indet_btt is
generic (
C_SF_FIFO_DEPTH : integer range 128 to 8192 := 128;
-- Sets the depth of the Data FIFO
C_IBTT_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- Sets the width of the sf2pcc_xfer_bytes port
C_STRT_OFFSET_WIDTH : Integer range 1 to 7 := 2;
-- Sets the bit width of the starting address offset port
-- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH)
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates what is set as the allowed max burst length for AXI4
-- transfers
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the width of the AXI4 MMap data path
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Indicates the width of the stream data path
C_ENABLE_SKID_BUF : string := "11111";
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_DRE : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- Clock input --------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-----------------------------------------------------------
-- Write Data Controller I/O ----------------------------------------------------------
--
ibtt2wdc_stbs_asserted : Out std_logic_vector(7 downto 0); --
-- Indicates the number of asserted WSTRB bits for the --
-- associated output stream data beat --
--
ibtt2wdc_eop : Out std_logic; --
-- Write End of Packet flag output to Write Data Controller --
--
ibtt2wdc_tdata : Out std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- Write DATA output to Write Data Controller --
--
ibtt2wdc_tstrb : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
-- Write DATA output to Write Data Controller --
--
ibtt2wdc_tlast : Out std_logic; --
-- Write LAST output to Write Data Controller --
--
ibtt2wdc_tvalid : Out std_logic; --
-- Write VALID output to Write Data Controller --
--
wdc2ibtt_tready : In std_logic; --
-- Write READY input from Write Data Controller --
---------------------------------------------------------------------------------------
-- DRE Stream In ----------------------------------------------------------------------
--
dre2ibtt_tvalid : In std_logic; --
-- DRE Stream VALID Output --
--
ibtt2dre_tready : Out Std_logic; --
-- DRE Stream READY input --
--
dre2ibtt_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- DRE Stream DATA input --
--
dre2ibtt_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- DRE Stream STRB input --
--
dre2ibtt_tlast : In std_logic; --
-- DRE Xfer LAST input --
--
dre2ibtt_eop : In std_logic; --
-- DRE Stream end of Stream packet flag --
--------------------------------------------------------------------------------------
-- Starting Address Offset Input -------------------------------------------------
--
dre2ibtt_strt_addr_offset : In std_logic_vector(C_STRT_OFFSET_WIDTH-1 downto 0); --
-- Used by Packing logic to set the initial data slice position for the --
-- packing operation. Packing is only needed if the MMap and Stream Data --
-- widths do not match. This input is sampled on the first valid DRE Stream In --
-- input databeat of a packet. --
-- --
-----------------------------------------------------------------------------------
-- Store and Forward Command Calculator Interface ---------------------------------------
--
sf2pcc_xfer_valid : Out std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the XFER_DESCR_FIFO --
--
pcc2sf_xfer_ready : in std_logic; --
-- Indicates that a full burst of data has been loaded into the data FIFO --
--
--
sf2pcc_cmd_cmplt : Out std_logic; --
-- Indicates that this is the final xfer for an associated command loaded --
-- into the Realigner by the IBTTCC interface --
--
--
sf2pcc_packet_eop : Out std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor --
--
sf2pcc_xfer_bytes : Out std_logic_vector(C_IBTT_XFER_BYTES_WIDTH-1 downto 0) --
-- This byte count is used by the IBTTCC for setting up the spawned child --
-- commands. The IBTTCC must use this count to generate the appropriate --
-- LEN value to put out on the AXI4 Write Addr Channel and the WSTRB on the AXI4 --
-- Write Data Channel. --
-----------------------------------------------------------------------------------------
);
end entity axi_datamover_indet_btt;
architecture implementation of axi_datamover_indet_btt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_cntr_width
--
-- Function Description:
-- This function calculates the needed counter bit width from the
-- number of count sates needed (input).
--
-------------------------------------------------------------------
function funct_get_cntr_width (num_cnt_values : integer) return integer is
Variable temp_cnt_width : Integer := 0;
begin
if (num_cnt_values <= 2) then
temp_cnt_width := 1;
elsif (num_cnt_values <= 4) then
temp_cnt_width := 2;
elsif (num_cnt_values <= 8) then
temp_cnt_width := 3;
elsif (num_cnt_values <= 16) then
temp_cnt_width := 4;
elsif (num_cnt_values <= 32) then
temp_cnt_width := 5;
elsif (num_cnt_values <= 64) then
temp_cnt_width := 6;
elsif (num_cnt_values <= 128) then
temp_cnt_width := 7;
else
temp_cnt_width := 8;
end if;
Return (temp_cnt_width);
end function funct_get_cntr_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 4 and 32. THis is used for sizing the SRL based XD FIFO.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 4) then
temp_pwr2 := 4;
elsif (input_value <= 8) then
temp_pwr2 := 8;
elsif (input_value <= 16) then
temp_pwr2 := 16;
else
temp_pwr2 := 32;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_PER_BYTE : integer := 8;
Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH;
Constant STRM_WSTB_WIDTH : integer := C_STREAM_DWIDTH/BITS_PER_BYTE;
Constant MMAP_WSTB_WIDTH : integer := C_MMAP_DWIDTH/BITS_PER_BYTE;
Constant STRM_STRBS_ASSERTED_WIDTH : integer := clog2(STRM_WSTB_WIDTH)+1;
-- Constant DATA_FIFO_DFACTOR : integer := 4; -- set buffer to 4 times the Max allowed Burst Length
-- Constant DATA_FIFO_DEPTH : integer := C_MAX_BURST_LEN*DATA_FIFO_DFACTOR;
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH+MMAP_WSTB_WIDTH*C_ENABLE_S2MM_TKEEP+2;
-- Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH+STRB_CNTR_WIDTH+2;
Constant DATA_FIFO_CNT_WIDTH : integer := clog2(DATA_FIFO_DEPTH)+1;
Constant BURST_CNTR_WIDTH : integer := clog2(C_MAX_BURST_LEN);
Constant MAX_BURST_DBEATS : Unsigned(BURST_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BURST_CNTR_WIDTH);
Constant DBC_ONE : Unsigned(BURST_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, BURST_CNTR_WIDTH);
Constant BYTE_CNTR_WIDTH : integer := C_IBTT_XFER_BYTES_WIDTH;
Constant BYTES_PER_MMAP_DBEAT : integer := C_MMAP_DWIDTH/BITS_PER_BYTE;
Constant BYTES_PER_STRM_DBEAT : integer := C_STREAM_DWIDTH/BITS_PER_BYTE;
--Constant MAX_BYTE_CNT : integer := C_MAX_BURST_LEN*BYTES_PER_DBEAT;
--Constant NUM_STRB_BITS : integer := BYTES_PER_DBEAT;
Constant BCNTR_ONE : Unsigned(BYTE_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, BYTE_CNTR_WIDTH);
--Constant XD_FIFO_DEPTH : integer := 16;
Constant XD_FIFO_DEPTH : integer := funct_rnd2pwr_of_2(DATA_FIFO_DEPTH/C_MAX_BURST_LEN);
Constant XD_FIFO_CNT_WIDTH : integer := clog2(XD_FIFO_DEPTH)+1;
Constant XD_FIFO_WIDTH : integer := BYTE_CNTR_WIDTH+2;
Constant MMAP_STBS_ASSERTED_WIDTH : integer := 8;
Constant SKIDBUF2WDC_DWIDTH : integer := C_MMAP_DWIDTH + MMAP_STBS_ASSERTED_WIDTH;
Constant SKIDBUF2WDC_STRB_WIDTH : integer := SKIDBUF2WDC_DWIDTH/BITS_PER_BYTE;
--Constant NUM_ZEROS_WIDTH : integer := MMAP_STBS_ASSERTED_WIDTH;
Constant STRB_CNTR_WIDTH : integer := MMAP_STBS_ASSERTED_WIDTH;
-- Signals
signal sig_wdc2ibtt_tready : std_logic := '0';
signal sig_ibtt2wdc_tvalid : std_logic := '0';
signal sig_ibtt2wdc_tdata : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tstrb : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tlast : std_logic := '0';
signal sig_ibtt2wdc_eop : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_rd_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_wr_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_push_xd_fifo : std_logic := '0';
signal sig_pop_xd_fifo : std_logic := '0';
signal sig_xd_fifo_data_in : std_logic_vector(XD_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_xd_fifo_data_out : std_logic_vector(XD_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_xd_fifo_dvalid : std_logic := '0';
signal sig_xd_fifo_full : std_logic := '0';
signal sig_tmp : std_logic := '0';
signal sig_strm_in_ready : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_good_tlast_dbeat : std_logic := '0';
signal sig_dre2ibtt_tlast_reg : std_logic := '0';
signal sig_dre2ibtt_eop_reg : std_logic := '0';
signal sig_burst_dbeat_cntr : Unsigned(BURST_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_dbeat_cntr : std_logic := '0';
signal sig_clr_dbeat_cntr : std_logic := '0';
signal sig_clr_dbc_reg : std_logic := '0';
signal sig_dbc_max : std_logic := '0';
signal sig_pcc2ibtt_xfer_ready : std_logic := '0';
signal sig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_byte_cntr : std_logic := '0';
signal sig_incr_byte_cntr : std_logic := '0';
signal sig_clr_byte_cntr : std_logic := '0';
signal sig_fifo_tstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_num_ls_zeros : integer range 0 to STRM_WSTB_WIDTH := 0;
signal sig_ls_assert_found : std_logic := '0';
signal sig_num_ms_zeros : integer range 0 to STRM_WSTB_WIDTH := 0;
signal sig_ms_assert_found : std_logic := '0';
-- signal sig_num_zeros : unsigned(NUM_ZEROS_WIDTH-1 downto 0) := (others => '0');
-- signal sig_num_ones : unsigned(NUM_ZEROS_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs2sfcc_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs2wdc_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_stbs_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tready : std_logic := '0';
signal sig_skidbuf_in_tvalid : std_logic := '0';
signal sig_skidbuf_in_tdata : std_logic_vector(SKIDBUF2WDC_DWIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tstrb : std_logic_vector(SKIDBUF2WDC_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tlast : std_logic := '0';
signal sig_skidbuf_in_eop : std_logic := '0';
signal sig_skidbuf_out_tready : std_logic := '0';
signal sig_skidbuf_out_tvalid : std_logic := '0';
signal sig_skidbuf_out_tdata : std_logic_vector(SKIDBUF2WDC_DWIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_out_tstrb : std_logic_vector(SKIDBUF2WDC_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_out_tlast : std_logic := '0';
signal sig_skidbuf_out_eop : std_logic := '0';
signal sig_enable_dbcntr : std_logic := '0';
signal sig_good_fifo_write : std_logic := '0';
begin --(architecture implementation)
-- Write Data Controller I/O
sig_wdc2ibtt_tready <= wdc2ibtt_tready ;
ibtt2wdc_tvalid <= sig_ibtt2wdc_tvalid ;
ibtt2wdc_tdata <= sig_ibtt2wdc_tdata ;
ibtt2wdc_tstrb <= sig_ibtt2wdc_tstrb ;
ibtt2wdc_tlast <= sig_ibtt2wdc_tlast ;
ibtt2wdc_eop <= sig_ibtt2wdc_eop ;
ibtt2wdc_stbs_asserted <= sig_ibtt2wdc_stbs_asserted;
-- PCC I/O
sf2pcc_xfer_valid <= sig_xd_fifo_dvalid;
sig_pcc2ibtt_xfer_ready <= pcc2sf_xfer_ready;
sf2pcc_packet_eop <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH+1);
sf2pcc_cmd_cmplt <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH);
sf2pcc_xfer_bytes <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH-1 downto 0);
-- DRE Stream In
ibtt2dre_tready <= sig_strm_in_ready;
-- sig_strm_in_ready <= not(sig_xd_fifo_full) and
-- not(sig_data_fifo_full);
sig_good_strm_dbeat <= dre2ibtt_tvalid and
sig_strm_in_ready;
sig_good_tlast_dbeat <= sig_good_strm_dbeat and
dre2ibtt_tlast;
-- Burst Packet Counter Logic -------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_DBC_STUFF
--
-- Process Description:
-- Just a register for data beat counter signals.
--
-------------------------------------------------------------
REG_DBC_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dre2ibtt_tlast_reg <= '0';
sig_dre2ibtt_eop_reg <= '0';
sig_clr_dbc_reg <= '0';
else
sig_dre2ibtt_tlast_reg <= dre2ibtt_tlast;
sig_dre2ibtt_eop_reg <= dre2ibtt_eop;
sig_clr_dbc_reg <= sig_clr_dbeat_cntr;
end if;
end if;
end process REG_DBC_STUFF;
-- sig_clr_dbc_reg <= sig_clr_dbeat_cntr;
-- Increment the dataBeat counter on a data fifo wide
-- load condition. If packer logic is enabled, this will
-- only occur when a full fifo data width has been collected
-- from the Stream input.
sig_incr_dbeat_cntr <= sig_good_strm_dbeat and
sig_enable_dbcntr;
-- Check to see if a max burst len of databeats have been
-- loaded into the FIFO
sig_dbc_max <= '1'
when (sig_burst_dbeat_cntr = MAX_BURST_DBEATS)
Else '0';
-- Start the counter over at a max burst len boundary or at
-- the end of the packet.
sig_clr_dbeat_cntr <= '1'
when (sig_dbc_max = '1' and
sig_good_strm_dbeat = '1' and
sig_enable_dbcntr = '1') or
(sig_good_tlast_dbeat = '1' and
sig_enable_dbcntr = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DBC_CMTR
--
-- Process Description:
-- The Databeat Counter keeps track of how many databeats have
-- been loaded into the Data FIFO. When a max burst worth of
-- databeats have been loaded (or a TLAST encountered), the
-- XD FIFO can be loaded with a transfer data set to be sent
-- to the IBTTCC.
--
-------------------------------------------------------------
IMP_DBC_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_dbeat_cntr = '1') then
sig_burst_dbeat_cntr <= (others => '0');
elsif (sig_incr_dbeat_cntr = '1') then
sig_burst_dbeat_cntr <= sig_burst_dbeat_cntr + DBC_ONE;
else
null; -- hold current value
end if;
end if;
end process IMP_DBC_CMTR;
----- Byte Counter Logic -----------------------------------------------
sig_clr_byte_cntr <= sig_clr_dbc_reg and
not(sig_good_strm_dbeat);
sig_ld_byte_cntr <= sig_clr_dbc_reg and
sig_good_strm_dbeat;
sig_incr_byte_cntr <= sig_good_strm_dbeat;
sig_byte_cntr_incr_value <= RESIZE(UNSIGNED(sig_stbs2sfcc_asserted), BYTE_CNTR_WIDTH);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BYTE_CMTR
--
-- Process Description:
-- Keeps a running byte count per burst packet loaded into the
-- xfer FIFO. It is based on the strobes set on the incoming
-- Stream dbeat.
--
-------------------------------------------------------------
IMP_BYTE_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_byte_cntr = '1') then
sig_byte_cntr <= (others => '0');
elsif (sig_ld_byte_cntr = '1') then
sig_byte_cntr <= sig_byte_cntr_incr_value;
elsif (sig_incr_byte_cntr = '1') then
sig_byte_cntr <= sig_byte_cntr + sig_byte_cntr_incr_value;
else
null; -- hold current value
end if;
end if;
end process IMP_BYTE_CMTR;
------------------------------------------------------------
-- Instance: I_IBTTCC_STBS_SET
--
-- Description:
-- Instance of the asserted strobe counter for the IBTTCC
-- interface.
--
------------------------------------------------------------
SAME_WIDTH_NO_DRE : if (C_ENABLE_DRE = 0 and (C_STREAM_DWIDTH = C_MMAP_DWIDTH)) generate
begin
I_IBTTCC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set_nodre
generic map (
C_STROBE_WIDTH => STRM_WSTB_WIDTH
)
port map (
tstrb_in => dre2ibtt_tstrb,
num_stbs_asserted => sig_stbs2sfcc_asserted -- 8 bit wide slv
);
end generate SAME_WIDTH_NO_DRE;
DIFF_WIDTH_OR_DRE : if (C_ENABLE_DRE /= 0 or (C_STREAM_DWIDTH /= C_MMAP_DWIDTH)) generate
begin
I_IBTTCC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set
generic map (
C_STROBE_WIDTH => STRM_WSTB_WIDTH
)
port map (
tstrb_in => dre2ibtt_tstrb,
num_stbs_asserted => sig_stbs2sfcc_asserted -- 8 bit wide slv
);
end generate DIFF_WIDTH_OR_DRE;
----- Xfer Descriptor FIFO Logic -----------------------------------------------
sig_push_xd_fifo <= sig_clr_dbc_reg ;
sig_pop_xd_fifo <= sig_pcc2ibtt_xfer_ready and
sig_xd_fifo_dvalid ;
sig_xd_fifo_data_in <= sig_dre2ibtt_eop_reg & -- (TLAST for the input Stream)
sig_dre2ibtt_tlast_reg & -- (TLAST for the IBTTCC command)
std_logic_vector(sig_byte_cntr); -- Number of bytes in this xfer
------------------------------------------------------------
-- Instance: I_XD_FIFO
--
-- Description:
-- Implement the Transfer Desciptor (XD) FIFO. This FIFO holds
-- the individual child command xfer descriptors used by the
-- IBTTCC to generate the commands sent to the Address Cntlr and
-- the Data Cntlr.
--
------------------------------------------------------------
I_XD_FIFO : entity axi_datamover_v5_1.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => XD_FIFO_WIDTH ,
C_DEPTH => XD_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => XD_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => 0 ,
C_NEED_ALMOST_FULL => 1 ,
C_USE_BLKMEM => 0 ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => mmap_reset ,
SFIFO_Clk => primary_aclk ,
SFIFO_Wr_en => sig_push_xd_fifo ,
SFIFO_Din => sig_xd_fifo_data_in ,
SFIFO_Rd_en => sig_pop_xd_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_xd_fifo_dvalid ,
SFIFO_Dout => sig_xd_fifo_data_out ,
SFIFO_Full => sig_xd_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => sig_tmp ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
----------------------------------------------------------------
-- Packing Logic ------------------------------------------
----------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_PACKING
--
-- If Generate Description:
-- Omits any packing logic in the Store and Forward module.
-- The Stream and MMap data widths are the same.
--
------------------------------------------------------------
OMIT_PACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate
begin
-- The data beat counter is always enabled when the packer
-- is omitted.
sig_enable_dbcntr <= '1';
sig_good_fifo_write <= sig_good_strm_dbeat;
sig_strm_in_ready <= not(sig_xd_fifo_full) and
not(sig_data_fifo_full) and
not (sig_tmp);
GEN_S2MM_TKEEP_ENABLE5 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Concatonate the Stream inputs into the single FIFO data
-- word input value
sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
dre2ibtt_tlast & -- Tlast marker
dre2ibtt_tstrb & -- TSTRB Value
dre2ibtt_tdata; -- data value
end generate GEN_S2MM_TKEEP_ENABLE5;
GEN_S2MM_TKEEP_DISABLE5 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Concatonate the Stream inputs into the single FIFO data
-- word input value
sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
dre2ibtt_tlast & -- Tlast marker
--dre2ibtt_tstrb & -- TSTRB Value
dre2ibtt_tdata; -- data value
end generate GEN_S2MM_TKEEP_DISABLE5;
end generate OMIT_PACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_PACKING
--
-- If Generate Description:
-- Includes packing logic in the IBTT Store and Forward
-- module. The MMap Data bus is wider than the Stream width.
--
------------------------------------------------------------
INCLUDE_PACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate
Constant TLAST_WIDTH : integer := 1; -- bit
Constant EOP_WIDTH : integer := 1; -- bit
Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH;
Constant STRB_SLICE_WIDTH : integer := STRM_WSTB_WIDTH;
Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH +
EOP_WIDTH;
Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO);
Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, OFFSET_CNTR_WIDTH);
Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH);
-- Types -----------------------------------------------------------------------------
type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(DATA_SLICE_WIDTH-1 downto 0);
type lsig_strb_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(STRB_SLICE_WIDTH-1 downto 0);
type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0);
-- local signals
signal lsig_data_slice_reg : lsig_data_slice_type;
signal lsig_strb_slice_reg : lsig_strb_slice_type;
signal lsig_flag_slice_reg : lsig_flag_slice_type;
signal lsig_reg_segment : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) := (others => '0');
signal lsig_segment_ld : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_segment_clr : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_0ffset_to_to_use : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_offset : std_logic := '0';
signal lsig_incr_offset : std_logic := '0';
signal lsig_offset_cntr_eq_max : std_logic := '0';
signal lsig_combined_data : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal lsig_combined_strb : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal lsig_tlast_or : std_logic := '0';
signal lsig_eop_or : std_logic := '0';
signal lsig_partial_tlast_or : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_partial_eop_or : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_packer_full : std_logic := '0';
signal lsig_packer_empty : std_logic := '0';
signal lsig_set_packer_full : std_logic := '0';
signal lsig_good_push2fifo : std_logic := '0';
signal lsig_first_dbeat : std_logic := '0';
begin
-- Generate the stream ready
sig_strm_in_ready <= not(sig_xd_fifo_full) and
not(sig_tmp) and
(not(lsig_packer_full) or
lsig_good_push2fifo) ;
-- Enable the Data Beat counter when the packer is
-- going full
sig_enable_dbcntr <= lsig_set_packer_full;
-- Assign the flag indicating that a fifo write is going
-- to occur at the next rising clock edge.
sig_good_fifo_write <= lsig_good_push2fifo;
GEN_S2MM_TKEEP_ENABLE6 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Format the composite FIFO input data word
sig_data_fifo_data_in <= lsig_eop_or & -- MS Bit
lsig_tlast_or &
lsig_combined_strb &
lsig_combined_data ; -- LS Bits
end generate GEN_S2MM_TKEEP_ENABLE6;
GEN_S2MM_TKEEP_DISABLE6 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Format the composite FIFO input data word
sig_data_fifo_data_in <= lsig_eop_or & -- MS Bit
lsig_tlast_or &
--lsig_combined_strb &
lsig_combined_data ; -- LS Bits
end generate GEN_S2MM_TKEEP_DISABLE6;
-- Generate a flag indicating a write to the DataFIFO
-- is going to complete
lsig_good_push2fifo <= lsig_packer_full and
not(sig_data_fifo_full);
-- Generate the control that loads the starting address
-- offset for the next input packet
lsig_ld_offset <= lsig_first_dbeat and
sig_good_strm_dbeat;
-- Generate the control for incrementing the offset counter
lsig_incr_offset <= sig_good_strm_dbeat;
-- Generate a flag indicating the packer input register
-- array is full or has loaded the last data beat of
-- the input paket
lsig_set_packer_full <= sig_good_strm_dbeat and
(dre2ibtt_tlast or
lsig_offset_cntr_eq_max);
-- Check to see if the offset counter has reached its max
-- value
lsig_offset_cntr_eq_max <= '1'
--when (lsig_0ffset_cntr = OFFSET_CNT_MAX)
when (lsig_0ffset_to_to_use = OFFSET_CNT_MAX)
Else '0';
-- Mux between the input start offset and the offset counter
-- output to use for the packer slice load control.
lsig_0ffset_to_to_use <= UNSIGNED(dre2ibtt_strt_addr_offset)
when (lsig_first_dbeat = '1')
Else lsig_0ffset_cntr;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_LD_MARKER
--
-- Process Description:
-- Implements the flop indicating the first databeat of
-- an input data packet.
--
-------------------------------------------------------------
IMP_OFFSET_LD_MARKER : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_first_dbeat <= '1';
elsif (sig_good_strm_dbeat = '1' and
dre2ibtt_tlast = '0') then
lsig_first_dbeat <= '0';
Elsif (sig_good_strm_dbeat = '1' and
dre2ibtt_tlast = '1') Then
lsig_first_dbeat <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_LD_MARKER;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_CNTR
--
-- Process Description:
-- Implements the address offset counter that is used to
-- steer the data loads into the packer register slices.
-- Note that the counter has to be loaded with the starting
-- offset plus one to sync up with the data input.
-------------------------------------------------------------
IMP_OFFSET_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_0ffset_cntr <= (others => '0');
Elsif (lsig_ld_offset = '1') Then
lsig_0ffset_cntr <= UNSIGNED(dre2ibtt_strt_addr_offset) + OFFSET_CNT_ONE;
elsif (lsig_incr_offset = '1') then
lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PACK_REG_FULL
--
-- Process Description:
-- Implements the Packer Register full/empty flags
--
-------------------------------------------------------------
IMP_PACK_REG_FULL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
Elsif (lsig_set_packer_full = '1' and
lsig_packer_full = '0') Then
lsig_packer_full <= '1';
lsig_packer_empty <= '0';
elsif (lsig_set_packer_full = '0' and
lsig_good_push2fifo = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PACK_REG_FULL;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_REG_SLICES
--
-- For Generate Description:
--
-- Implements the Packng Register Slices
--
--
------------------------------------------------------------
DO_REG_SLICES : for slice_index in 0 to MMAP2STRM_WIDTH_RATO-1 generate
begin
-- generate the register load enable for each slice segment based
-- on the address offset count value
lsig_segment_ld(slice_index) <= '1'
when (sig_good_strm_dbeat = '1' and
TO_INTEGER(lsig_0ffset_to_to_use) = slice_index)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DATA_SLICE
--
-- Process Description:
-- Implement a data register slice abd Strobe register slice
-- for the packer (upsizer).
--
-------------------------------------------------------------
IMP_DATA_SLICE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
lsig_strb_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_data_slice_reg(slice_index) <= dre2ibtt_tdata;
lsig_strb_slice_reg(slice_index) <= dre2ibtt_tstrb;
-- optional clear of slice reg
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
lsig_strb_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_DATA_SLICE;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FLAG_SLICE
--
-- Process Description:
-- Implement a flag register slice for the packer.
--
-------------------------------------------------------------
IMP_FLAG_SLICE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_flag_slice_reg(slice_index) <= dre2ibtt_tlast & -- bit 1
dre2ibtt_eop; -- bit 0
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_FLAG_SLICE;
end generate DO_REG_SLICES;
-- Do the OR functions of the Flags -------------------------------------
lsig_tlast_or <= lsig_partial_tlast_or(MMAP2STRM_WIDTH_RATO-1) ;
lsig_eop_or <= lsig_partial_eop_or(MMAP2STRM_WIDTH_RATO-1);
lsig_partial_tlast_or(0) <= lsig_flag_slice_reg(0)(1);
lsig_partial_eop_or(0) <= lsig_flag_slice_reg(0)(0);
------------------------------------------------------------
-- For Generate
--
-- Label: DO_FLAG_OR
--
-- For Generate Description:
-- Implement the OR of the TLAST and EOP Error flags.
--
--
--
------------------------------------------------------------
DO_FLAG_OR : for slice_index in 1 to MMAP2STRM_WIDTH_RATO-1 generate
begin
lsig_partial_tlast_or(slice_index) <= lsig_partial_tlast_or(slice_index-1) or
--lsig_partial_tlast_or(slice_index);
lsig_flag_slice_reg(slice_index)(1);
lsig_partial_eop_or(slice_index) <= lsig_partial_eop_or(slice_index-1) or
--lsig_partial_eop_or(slice_index);
lsig_flag_slice_reg(slice_index)(0);
end generate DO_FLAG_OR;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_DATA_COMBINER
--
-- For Generate Description:
-- Combines the Data Slice register and Strobe slice register
-- outputs into a single data and single strobe vector used for
-- input data to the Data FIFO.
--
--
------------------------------------------------------------
DO_DATA_COMBINER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate
begin
lsig_combined_data((slice_index*DATA_SLICE_WIDTH)-1 downto
(slice_index-1)*DATA_SLICE_WIDTH) <=
lsig_data_slice_reg(slice_index-1);
lsig_combined_strb((slice_index*STRB_SLICE_WIDTH)-1 downto
(slice_index-1)*STRB_SLICE_WIDTH) <=
lsig_strb_slice_reg(slice_index-1);
end generate DO_DATA_COMBINER;
end generate INCLUDE_PACKING;
-- Data FIFO Logic ------------------------------------------
--sig_push_data_fifo <= sig_good_strm_dbeat;
sig_push_data_fifo <= sig_good_fifo_write;
sig_pop_data_fifo <= sig_skidbuf_in_tready and
sig_data_fifo_dvalid;
-- -- Concatonate the Stream inputs into the single FIFO data in value
-- sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
-- dre2ibtt_tlast &
-- dre2ibtt_tstrb &
-- dre2ibtt_tdata;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_datamover_v5_1.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => 0 ,
C_NEED_ALMOST_FULL => 0 ,
C_USE_BLKMEM => 1 ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => mmap_reset ,
SFIFO_Clk => primary_aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => sig_data_fifo_rd_cnt ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => sig_data_fifo_wr_cnt ,
SFIFO_Rd_ack => open
);
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
GEN_S2MM_TKEEP_ENABLE7 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Rip the write strobe value from the FIFO output data
sig_fifo_tstrb_out <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-3 downto
C_MMAP_DWIDTH);
end generate GEN_S2MM_TKEEP_ENABLE7;
GEN_S2MM_TKEEP_DISBALE7 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
sig_fifo_tstrb_out <= (others => '1');
end generate GEN_S2MM_TKEEP_DISBALE7;
------------------------------------------------------------
-- Instance: I_WDC_STBS_SET
--
-- Description:
-- Instance of the asserted strobe counter for the WDC
-- interface.
--
------------------------------------------------------------
SAME_WIDTH_NO_DRE_WDC : if (C_ENABLE_DRE = 0 and (C_STREAM_DWIDTH = C_MMAP_DWIDTH)) generate
begin
I_WDC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set_nodre
generic map (
C_STROBE_WIDTH => MMAP_WSTB_WIDTH
)
port map (
tstrb_in => sig_fifo_tstrb_out,
num_stbs_asserted => sig_stbs2wdc_asserted
);
end generate SAME_WIDTH_NO_DRE_WDC;
DIFF_WIDTH_OR_DRE_WDC : if (C_ENABLE_DRE /= 0 or (C_STREAM_DWIDTH /= C_MMAP_DWIDTH)) generate
begin
I_WDC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set
generic map (
C_STROBE_WIDTH => MMAP_WSTB_WIDTH
)
port map (
tstrb_in => sig_fifo_tstrb_out,
num_stbs_asserted => sig_stbs2wdc_asserted
);
end generate DIFF_WIDTH_OR_DRE_WDC;
-------------------------------------------------------------------------
------- Isolation Skid Buffer Logic (needed for Fmax timing) -----------
-------------------------------------------------------------------------
-- Skid Buffer output assignments -----------
sig_skidbuf_out_tready <= sig_wdc2ibtt_tready;
sig_ibtt2wdc_tvalid <= sig_skidbuf_out_tvalid;
sig_ibtt2wdc_tdata <= sig_skidbuf_out_tdata(C_MMAP_DWIDTH-1 downto 0) ;
sig_ibtt2wdc_tstrb <= sig_skidbuf_out_tstrb(MMAP_WSTB_WIDTH-1 downto 0) ;
sig_ibtt2wdc_tlast <= sig_skidbuf_out_tlast ;
-- Rip the EOP marker from the MS bit of the skid output strobes
sig_ibtt2wdc_eop <= sig_skidbuf_out_tstrb(MMAP_WSTB_WIDTH) ;
-- Rip the upper 8 bits of the skid output data for the strobes asserted value
sig_ibtt2wdc_stbs_asserted <= sig_skidbuf_out_tdata(SKIDBUF2WDC_DWIDTH-1 downto
C_MMAP_DWIDTH);
-- Skid Buffer input assignments -----------
sig_skidbuf_in_tvalid <= sig_data_fifo_dvalid;
sig_skidbuf_in_eop <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-1);
sig_skidbuf_in_tlast <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-2);
-- Steal the extra input strobe bit and use it for the EOP marker
---- sig_skidbuf_in_tstrb <= sig_skidbuf_in_eop &
---- sig_data_fifo_data_out(DATA_FIFO_WIDTH-3 downto
---- C_MMAP_DWIDTH);
----
sig_skidbuf_in_tstrb <= sig_skidbuf_in_eop &
sig_fifo_tstrb_out;
-- Insert the Strobes Asserted count in the extra (MS) data byte
-- for the skid buffer
sig_skidbuf_in_tdata <= sig_stbs2wdc_asserted &
sig_data_fifo_data_out(C_MMAP_DWIDTH-1 downto 0);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(2) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_INDET_BTT_SKID_BUF
--
-- Description:
-- Instance for the Store and Forward isolation Skid Buffer
-- which is required to achieve Fmax timing. Note that this
-- skid buffer is 1 byte wider than the stream data width to
-- allow for the asserted strobes count to be passed through
-- it. The EOP marker is inserted in the extra strobe slot.
--
------------------------------------------------------------
I_INDET_BTT_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => SKIDBUF2WDC_DWIDTH
)
port map (
-- System Ports
aclk => primary_aclk ,
arst => mmap_reset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Stream Data Input)
s_valid => sig_skidbuf_in_tvalid ,
s_ready => sig_skidbuf_in_tready ,
s_data => sig_skidbuf_in_tdata ,
s_strb => sig_skidbuf_in_tstrb ,
s_last => sig_skidbuf_in_tlast ,
-- Master Side (Stream Data Output
m_valid => sig_skidbuf_out_tvalid ,
m_ready => sig_skidbuf_out_tready ,
m_data => sig_skidbuf_out_tdata ,
m_strb => sig_skidbuf_out_tstrb ,
m_last => sig_skidbuf_out_tlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(2) = '0' generate
begin
sig_skidbuf_out_tvalid <= sig_skidbuf_in_tvalid;
sig_skidbuf_in_tready <= sig_skidbuf_out_tready ;
sig_skidbuf_out_tdata <= sig_skidbuf_in_tdata ;
sig_skidbuf_out_tstrb <= sig_skidbuf_in_tstrb ;
sig_skidbuf_out_tlast <= sig_skidbuf_in_tlast ;
end generate DISABLE_AXIS_SKID;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_indet_btt.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_indet_btt.vhd
--
-- Description:
-- This file implements the DataMover S2MM Indeterminate BTT support module.
-- This Module keeps track of the incoming data stream and generates a transfer
-- descriptor for each AXI MMap Burst worth of data loaded in the Data FIFO.
-- This information is stored in a separate FIFO that the Predictive Transfer
-- Calculator fetches sequentially as it is generating commands for the AXI MMap
-- bus.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0;
Use lib_pkg_v1_0.lib_pkg.clog2;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_sfifo_autord;
use axi_datamover_v5_1.axi_datamover_skid_buf;
Use axi_datamover_v5_1.axi_datamover_stbs_set;
Use axi_datamover_v5_1.axi_datamover_stbs_set_nodre;
-------------------------------------------------------------------------------
entity axi_datamover_indet_btt is
generic (
C_SF_FIFO_DEPTH : integer range 128 to 8192 := 128;
-- Sets the depth of the Data FIFO
C_IBTT_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- Sets the width of the sf2pcc_xfer_bytes port
C_STRT_OFFSET_WIDTH : Integer range 1 to 7 := 2;
-- Sets the bit width of the starting address offset port
-- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH)
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates what is set as the allowed max burst length for AXI4
-- transfers
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the width of the AXI4 MMap data path
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Indicates the width of the stream data path
C_ENABLE_SKID_BUF : string := "11111";
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_DRE : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- Clock input --------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-----------------------------------------------------------
-- Write Data Controller I/O ----------------------------------------------------------
--
ibtt2wdc_stbs_asserted : Out std_logic_vector(7 downto 0); --
-- Indicates the number of asserted WSTRB bits for the --
-- associated output stream data beat --
--
ibtt2wdc_eop : Out std_logic; --
-- Write End of Packet flag output to Write Data Controller --
--
ibtt2wdc_tdata : Out std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- Write DATA output to Write Data Controller --
--
ibtt2wdc_tstrb : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
-- Write DATA output to Write Data Controller --
--
ibtt2wdc_tlast : Out std_logic; --
-- Write LAST output to Write Data Controller --
--
ibtt2wdc_tvalid : Out std_logic; --
-- Write VALID output to Write Data Controller --
--
wdc2ibtt_tready : In std_logic; --
-- Write READY input from Write Data Controller --
---------------------------------------------------------------------------------------
-- DRE Stream In ----------------------------------------------------------------------
--
dre2ibtt_tvalid : In std_logic; --
-- DRE Stream VALID Output --
--
ibtt2dre_tready : Out Std_logic; --
-- DRE Stream READY input --
--
dre2ibtt_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- DRE Stream DATA input --
--
dre2ibtt_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- DRE Stream STRB input --
--
dre2ibtt_tlast : In std_logic; --
-- DRE Xfer LAST input --
--
dre2ibtt_eop : In std_logic; --
-- DRE Stream end of Stream packet flag --
--------------------------------------------------------------------------------------
-- Starting Address Offset Input -------------------------------------------------
--
dre2ibtt_strt_addr_offset : In std_logic_vector(C_STRT_OFFSET_WIDTH-1 downto 0); --
-- Used by Packing logic to set the initial data slice position for the --
-- packing operation. Packing is only needed if the MMap and Stream Data --
-- widths do not match. This input is sampled on the first valid DRE Stream In --
-- input databeat of a packet. --
-- --
-----------------------------------------------------------------------------------
-- Store and Forward Command Calculator Interface ---------------------------------------
--
sf2pcc_xfer_valid : Out std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the XFER_DESCR_FIFO --
--
pcc2sf_xfer_ready : in std_logic; --
-- Indicates that a full burst of data has been loaded into the data FIFO --
--
--
sf2pcc_cmd_cmplt : Out std_logic; --
-- Indicates that this is the final xfer for an associated command loaded --
-- into the Realigner by the IBTTCC interface --
--
--
sf2pcc_packet_eop : Out std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor --
--
sf2pcc_xfer_bytes : Out std_logic_vector(C_IBTT_XFER_BYTES_WIDTH-1 downto 0) --
-- This byte count is used by the IBTTCC for setting up the spawned child --
-- commands. The IBTTCC must use this count to generate the appropriate --
-- LEN value to put out on the AXI4 Write Addr Channel and the WSTRB on the AXI4 --
-- Write Data Channel. --
-----------------------------------------------------------------------------------------
);
end entity axi_datamover_indet_btt;
architecture implementation of axi_datamover_indet_btt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_cntr_width
--
-- Function Description:
-- This function calculates the needed counter bit width from the
-- number of count sates needed (input).
--
-------------------------------------------------------------------
function funct_get_cntr_width (num_cnt_values : integer) return integer is
Variable temp_cnt_width : Integer := 0;
begin
if (num_cnt_values <= 2) then
temp_cnt_width := 1;
elsif (num_cnt_values <= 4) then
temp_cnt_width := 2;
elsif (num_cnt_values <= 8) then
temp_cnt_width := 3;
elsif (num_cnt_values <= 16) then
temp_cnt_width := 4;
elsif (num_cnt_values <= 32) then
temp_cnt_width := 5;
elsif (num_cnt_values <= 64) then
temp_cnt_width := 6;
elsif (num_cnt_values <= 128) then
temp_cnt_width := 7;
else
temp_cnt_width := 8;
end if;
Return (temp_cnt_width);
end function funct_get_cntr_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 4 and 32. THis is used for sizing the SRL based XD FIFO.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 4) then
temp_pwr2 := 4;
elsif (input_value <= 8) then
temp_pwr2 := 8;
elsif (input_value <= 16) then
temp_pwr2 := 16;
else
temp_pwr2 := 32;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_PER_BYTE : integer := 8;
Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH;
Constant STRM_WSTB_WIDTH : integer := C_STREAM_DWIDTH/BITS_PER_BYTE;
Constant MMAP_WSTB_WIDTH : integer := C_MMAP_DWIDTH/BITS_PER_BYTE;
Constant STRM_STRBS_ASSERTED_WIDTH : integer := clog2(STRM_WSTB_WIDTH)+1;
-- Constant DATA_FIFO_DFACTOR : integer := 4; -- set buffer to 4 times the Max allowed Burst Length
-- Constant DATA_FIFO_DEPTH : integer := C_MAX_BURST_LEN*DATA_FIFO_DFACTOR;
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH+MMAP_WSTB_WIDTH*C_ENABLE_S2MM_TKEEP+2;
-- Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH+STRB_CNTR_WIDTH+2;
Constant DATA_FIFO_CNT_WIDTH : integer := clog2(DATA_FIFO_DEPTH)+1;
Constant BURST_CNTR_WIDTH : integer := clog2(C_MAX_BURST_LEN);
Constant MAX_BURST_DBEATS : Unsigned(BURST_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BURST_CNTR_WIDTH);
Constant DBC_ONE : Unsigned(BURST_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, BURST_CNTR_WIDTH);
Constant BYTE_CNTR_WIDTH : integer := C_IBTT_XFER_BYTES_WIDTH;
Constant BYTES_PER_MMAP_DBEAT : integer := C_MMAP_DWIDTH/BITS_PER_BYTE;
Constant BYTES_PER_STRM_DBEAT : integer := C_STREAM_DWIDTH/BITS_PER_BYTE;
--Constant MAX_BYTE_CNT : integer := C_MAX_BURST_LEN*BYTES_PER_DBEAT;
--Constant NUM_STRB_BITS : integer := BYTES_PER_DBEAT;
Constant BCNTR_ONE : Unsigned(BYTE_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, BYTE_CNTR_WIDTH);
--Constant XD_FIFO_DEPTH : integer := 16;
Constant XD_FIFO_DEPTH : integer := funct_rnd2pwr_of_2(DATA_FIFO_DEPTH/C_MAX_BURST_LEN);
Constant XD_FIFO_CNT_WIDTH : integer := clog2(XD_FIFO_DEPTH)+1;
Constant XD_FIFO_WIDTH : integer := BYTE_CNTR_WIDTH+2;
Constant MMAP_STBS_ASSERTED_WIDTH : integer := 8;
Constant SKIDBUF2WDC_DWIDTH : integer := C_MMAP_DWIDTH + MMAP_STBS_ASSERTED_WIDTH;
Constant SKIDBUF2WDC_STRB_WIDTH : integer := SKIDBUF2WDC_DWIDTH/BITS_PER_BYTE;
--Constant NUM_ZEROS_WIDTH : integer := MMAP_STBS_ASSERTED_WIDTH;
Constant STRB_CNTR_WIDTH : integer := MMAP_STBS_ASSERTED_WIDTH;
-- Signals
signal sig_wdc2ibtt_tready : std_logic := '0';
signal sig_ibtt2wdc_tvalid : std_logic := '0';
signal sig_ibtt2wdc_tdata : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tstrb : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tlast : std_logic := '0';
signal sig_ibtt2wdc_eop : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_rd_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_wr_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_push_xd_fifo : std_logic := '0';
signal sig_pop_xd_fifo : std_logic := '0';
signal sig_xd_fifo_data_in : std_logic_vector(XD_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_xd_fifo_data_out : std_logic_vector(XD_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_xd_fifo_dvalid : std_logic := '0';
signal sig_xd_fifo_full : std_logic := '0';
signal sig_tmp : std_logic := '0';
signal sig_strm_in_ready : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_good_tlast_dbeat : std_logic := '0';
signal sig_dre2ibtt_tlast_reg : std_logic := '0';
signal sig_dre2ibtt_eop_reg : std_logic := '0';
signal sig_burst_dbeat_cntr : Unsigned(BURST_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_dbeat_cntr : std_logic := '0';
signal sig_clr_dbeat_cntr : std_logic := '0';
signal sig_clr_dbc_reg : std_logic := '0';
signal sig_dbc_max : std_logic := '0';
signal sig_pcc2ibtt_xfer_ready : std_logic := '0';
signal sig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_byte_cntr : std_logic := '0';
signal sig_incr_byte_cntr : std_logic := '0';
signal sig_clr_byte_cntr : std_logic := '0';
signal sig_fifo_tstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_num_ls_zeros : integer range 0 to STRM_WSTB_WIDTH := 0;
signal sig_ls_assert_found : std_logic := '0';
signal sig_num_ms_zeros : integer range 0 to STRM_WSTB_WIDTH := 0;
signal sig_ms_assert_found : std_logic := '0';
-- signal sig_num_zeros : unsigned(NUM_ZEROS_WIDTH-1 downto 0) := (others => '0');
-- signal sig_num_ones : unsigned(NUM_ZEROS_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs2sfcc_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs2wdc_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_stbs_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tready : std_logic := '0';
signal sig_skidbuf_in_tvalid : std_logic := '0';
signal sig_skidbuf_in_tdata : std_logic_vector(SKIDBUF2WDC_DWIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tstrb : std_logic_vector(SKIDBUF2WDC_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tlast : std_logic := '0';
signal sig_skidbuf_in_eop : std_logic := '0';
signal sig_skidbuf_out_tready : std_logic := '0';
signal sig_skidbuf_out_tvalid : std_logic := '0';
signal sig_skidbuf_out_tdata : std_logic_vector(SKIDBUF2WDC_DWIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_out_tstrb : std_logic_vector(SKIDBUF2WDC_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_out_tlast : std_logic := '0';
signal sig_skidbuf_out_eop : std_logic := '0';
signal sig_enable_dbcntr : std_logic := '0';
signal sig_good_fifo_write : std_logic := '0';
begin --(architecture implementation)
-- Write Data Controller I/O
sig_wdc2ibtt_tready <= wdc2ibtt_tready ;
ibtt2wdc_tvalid <= sig_ibtt2wdc_tvalid ;
ibtt2wdc_tdata <= sig_ibtt2wdc_tdata ;
ibtt2wdc_tstrb <= sig_ibtt2wdc_tstrb ;
ibtt2wdc_tlast <= sig_ibtt2wdc_tlast ;
ibtt2wdc_eop <= sig_ibtt2wdc_eop ;
ibtt2wdc_stbs_asserted <= sig_ibtt2wdc_stbs_asserted;
-- PCC I/O
sf2pcc_xfer_valid <= sig_xd_fifo_dvalid;
sig_pcc2ibtt_xfer_ready <= pcc2sf_xfer_ready;
sf2pcc_packet_eop <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH+1);
sf2pcc_cmd_cmplt <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH);
sf2pcc_xfer_bytes <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH-1 downto 0);
-- DRE Stream In
ibtt2dre_tready <= sig_strm_in_ready;
-- sig_strm_in_ready <= not(sig_xd_fifo_full) and
-- not(sig_data_fifo_full);
sig_good_strm_dbeat <= dre2ibtt_tvalid and
sig_strm_in_ready;
sig_good_tlast_dbeat <= sig_good_strm_dbeat and
dre2ibtt_tlast;
-- Burst Packet Counter Logic -------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_DBC_STUFF
--
-- Process Description:
-- Just a register for data beat counter signals.
--
-------------------------------------------------------------
REG_DBC_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dre2ibtt_tlast_reg <= '0';
sig_dre2ibtt_eop_reg <= '0';
sig_clr_dbc_reg <= '0';
else
sig_dre2ibtt_tlast_reg <= dre2ibtt_tlast;
sig_dre2ibtt_eop_reg <= dre2ibtt_eop;
sig_clr_dbc_reg <= sig_clr_dbeat_cntr;
end if;
end if;
end process REG_DBC_STUFF;
-- sig_clr_dbc_reg <= sig_clr_dbeat_cntr;
-- Increment the dataBeat counter on a data fifo wide
-- load condition. If packer logic is enabled, this will
-- only occur when a full fifo data width has been collected
-- from the Stream input.
sig_incr_dbeat_cntr <= sig_good_strm_dbeat and
sig_enable_dbcntr;
-- Check to see if a max burst len of databeats have been
-- loaded into the FIFO
sig_dbc_max <= '1'
when (sig_burst_dbeat_cntr = MAX_BURST_DBEATS)
Else '0';
-- Start the counter over at a max burst len boundary or at
-- the end of the packet.
sig_clr_dbeat_cntr <= '1'
when (sig_dbc_max = '1' and
sig_good_strm_dbeat = '1' and
sig_enable_dbcntr = '1') or
(sig_good_tlast_dbeat = '1' and
sig_enable_dbcntr = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DBC_CMTR
--
-- Process Description:
-- The Databeat Counter keeps track of how many databeats have
-- been loaded into the Data FIFO. When a max burst worth of
-- databeats have been loaded (or a TLAST encountered), the
-- XD FIFO can be loaded with a transfer data set to be sent
-- to the IBTTCC.
--
-------------------------------------------------------------
IMP_DBC_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_dbeat_cntr = '1') then
sig_burst_dbeat_cntr <= (others => '0');
elsif (sig_incr_dbeat_cntr = '1') then
sig_burst_dbeat_cntr <= sig_burst_dbeat_cntr + DBC_ONE;
else
null; -- hold current value
end if;
end if;
end process IMP_DBC_CMTR;
----- Byte Counter Logic -----------------------------------------------
sig_clr_byte_cntr <= sig_clr_dbc_reg and
not(sig_good_strm_dbeat);
sig_ld_byte_cntr <= sig_clr_dbc_reg and
sig_good_strm_dbeat;
sig_incr_byte_cntr <= sig_good_strm_dbeat;
sig_byte_cntr_incr_value <= RESIZE(UNSIGNED(sig_stbs2sfcc_asserted), BYTE_CNTR_WIDTH);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BYTE_CMTR
--
-- Process Description:
-- Keeps a running byte count per burst packet loaded into the
-- xfer FIFO. It is based on the strobes set on the incoming
-- Stream dbeat.
--
-------------------------------------------------------------
IMP_BYTE_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_byte_cntr = '1') then
sig_byte_cntr <= (others => '0');
elsif (sig_ld_byte_cntr = '1') then
sig_byte_cntr <= sig_byte_cntr_incr_value;
elsif (sig_incr_byte_cntr = '1') then
sig_byte_cntr <= sig_byte_cntr + sig_byte_cntr_incr_value;
else
null; -- hold current value
end if;
end if;
end process IMP_BYTE_CMTR;
------------------------------------------------------------
-- Instance: I_IBTTCC_STBS_SET
--
-- Description:
-- Instance of the asserted strobe counter for the IBTTCC
-- interface.
--
------------------------------------------------------------
SAME_WIDTH_NO_DRE : if (C_ENABLE_DRE = 0 and (C_STREAM_DWIDTH = C_MMAP_DWIDTH)) generate
begin
I_IBTTCC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set_nodre
generic map (
C_STROBE_WIDTH => STRM_WSTB_WIDTH
)
port map (
tstrb_in => dre2ibtt_tstrb,
num_stbs_asserted => sig_stbs2sfcc_asserted -- 8 bit wide slv
);
end generate SAME_WIDTH_NO_DRE;
DIFF_WIDTH_OR_DRE : if (C_ENABLE_DRE /= 0 or (C_STREAM_DWIDTH /= C_MMAP_DWIDTH)) generate
begin
I_IBTTCC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set
generic map (
C_STROBE_WIDTH => STRM_WSTB_WIDTH
)
port map (
tstrb_in => dre2ibtt_tstrb,
num_stbs_asserted => sig_stbs2sfcc_asserted -- 8 bit wide slv
);
end generate DIFF_WIDTH_OR_DRE;
----- Xfer Descriptor FIFO Logic -----------------------------------------------
sig_push_xd_fifo <= sig_clr_dbc_reg ;
sig_pop_xd_fifo <= sig_pcc2ibtt_xfer_ready and
sig_xd_fifo_dvalid ;
sig_xd_fifo_data_in <= sig_dre2ibtt_eop_reg & -- (TLAST for the input Stream)
sig_dre2ibtt_tlast_reg & -- (TLAST for the IBTTCC command)
std_logic_vector(sig_byte_cntr); -- Number of bytes in this xfer
------------------------------------------------------------
-- Instance: I_XD_FIFO
--
-- Description:
-- Implement the Transfer Desciptor (XD) FIFO. This FIFO holds
-- the individual child command xfer descriptors used by the
-- IBTTCC to generate the commands sent to the Address Cntlr and
-- the Data Cntlr.
--
------------------------------------------------------------
I_XD_FIFO : entity axi_datamover_v5_1.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => XD_FIFO_WIDTH ,
C_DEPTH => XD_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => XD_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => 0 ,
C_NEED_ALMOST_FULL => 1 ,
C_USE_BLKMEM => 0 ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => mmap_reset ,
SFIFO_Clk => primary_aclk ,
SFIFO_Wr_en => sig_push_xd_fifo ,
SFIFO_Din => sig_xd_fifo_data_in ,
SFIFO_Rd_en => sig_pop_xd_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_xd_fifo_dvalid ,
SFIFO_Dout => sig_xd_fifo_data_out ,
SFIFO_Full => sig_xd_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => sig_tmp ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
----------------------------------------------------------------
-- Packing Logic ------------------------------------------
----------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_PACKING
--
-- If Generate Description:
-- Omits any packing logic in the Store and Forward module.
-- The Stream and MMap data widths are the same.
--
------------------------------------------------------------
OMIT_PACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate
begin
-- The data beat counter is always enabled when the packer
-- is omitted.
sig_enable_dbcntr <= '1';
sig_good_fifo_write <= sig_good_strm_dbeat;
sig_strm_in_ready <= not(sig_xd_fifo_full) and
not(sig_data_fifo_full) and
not (sig_tmp);
GEN_S2MM_TKEEP_ENABLE5 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Concatonate the Stream inputs into the single FIFO data
-- word input value
sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
dre2ibtt_tlast & -- Tlast marker
dre2ibtt_tstrb & -- TSTRB Value
dre2ibtt_tdata; -- data value
end generate GEN_S2MM_TKEEP_ENABLE5;
GEN_S2MM_TKEEP_DISABLE5 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Concatonate the Stream inputs into the single FIFO data
-- word input value
sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
dre2ibtt_tlast & -- Tlast marker
--dre2ibtt_tstrb & -- TSTRB Value
dre2ibtt_tdata; -- data value
end generate GEN_S2MM_TKEEP_DISABLE5;
end generate OMIT_PACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_PACKING
--
-- If Generate Description:
-- Includes packing logic in the IBTT Store and Forward
-- module. The MMap Data bus is wider than the Stream width.
--
------------------------------------------------------------
INCLUDE_PACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate
Constant TLAST_WIDTH : integer := 1; -- bit
Constant EOP_WIDTH : integer := 1; -- bit
Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH;
Constant STRB_SLICE_WIDTH : integer := STRM_WSTB_WIDTH;
Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH +
EOP_WIDTH;
Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO);
Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, OFFSET_CNTR_WIDTH);
Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH);
-- Types -----------------------------------------------------------------------------
type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(DATA_SLICE_WIDTH-1 downto 0);
type lsig_strb_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(STRB_SLICE_WIDTH-1 downto 0);
type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0);
-- local signals
signal lsig_data_slice_reg : lsig_data_slice_type;
signal lsig_strb_slice_reg : lsig_strb_slice_type;
signal lsig_flag_slice_reg : lsig_flag_slice_type;
signal lsig_reg_segment : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) := (others => '0');
signal lsig_segment_ld : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_segment_clr : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_0ffset_to_to_use : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_offset : std_logic := '0';
signal lsig_incr_offset : std_logic := '0';
signal lsig_offset_cntr_eq_max : std_logic := '0';
signal lsig_combined_data : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal lsig_combined_strb : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal lsig_tlast_or : std_logic := '0';
signal lsig_eop_or : std_logic := '0';
signal lsig_partial_tlast_or : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_partial_eop_or : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_packer_full : std_logic := '0';
signal lsig_packer_empty : std_logic := '0';
signal lsig_set_packer_full : std_logic := '0';
signal lsig_good_push2fifo : std_logic := '0';
signal lsig_first_dbeat : std_logic := '0';
begin
-- Generate the stream ready
sig_strm_in_ready <= not(sig_xd_fifo_full) and
not(sig_tmp) and
(not(lsig_packer_full) or
lsig_good_push2fifo) ;
-- Enable the Data Beat counter when the packer is
-- going full
sig_enable_dbcntr <= lsig_set_packer_full;
-- Assign the flag indicating that a fifo write is going
-- to occur at the next rising clock edge.
sig_good_fifo_write <= lsig_good_push2fifo;
GEN_S2MM_TKEEP_ENABLE6 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Format the composite FIFO input data word
sig_data_fifo_data_in <= lsig_eop_or & -- MS Bit
lsig_tlast_or &
lsig_combined_strb &
lsig_combined_data ; -- LS Bits
end generate GEN_S2MM_TKEEP_ENABLE6;
GEN_S2MM_TKEEP_DISABLE6 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Format the composite FIFO input data word
sig_data_fifo_data_in <= lsig_eop_or & -- MS Bit
lsig_tlast_or &
--lsig_combined_strb &
lsig_combined_data ; -- LS Bits
end generate GEN_S2MM_TKEEP_DISABLE6;
-- Generate a flag indicating a write to the DataFIFO
-- is going to complete
lsig_good_push2fifo <= lsig_packer_full and
not(sig_data_fifo_full);
-- Generate the control that loads the starting address
-- offset for the next input packet
lsig_ld_offset <= lsig_first_dbeat and
sig_good_strm_dbeat;
-- Generate the control for incrementing the offset counter
lsig_incr_offset <= sig_good_strm_dbeat;
-- Generate a flag indicating the packer input register
-- array is full or has loaded the last data beat of
-- the input paket
lsig_set_packer_full <= sig_good_strm_dbeat and
(dre2ibtt_tlast or
lsig_offset_cntr_eq_max);
-- Check to see if the offset counter has reached its max
-- value
lsig_offset_cntr_eq_max <= '1'
--when (lsig_0ffset_cntr = OFFSET_CNT_MAX)
when (lsig_0ffset_to_to_use = OFFSET_CNT_MAX)
Else '0';
-- Mux between the input start offset and the offset counter
-- output to use for the packer slice load control.
lsig_0ffset_to_to_use <= UNSIGNED(dre2ibtt_strt_addr_offset)
when (lsig_first_dbeat = '1')
Else lsig_0ffset_cntr;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_LD_MARKER
--
-- Process Description:
-- Implements the flop indicating the first databeat of
-- an input data packet.
--
-------------------------------------------------------------
IMP_OFFSET_LD_MARKER : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_first_dbeat <= '1';
elsif (sig_good_strm_dbeat = '1' and
dre2ibtt_tlast = '0') then
lsig_first_dbeat <= '0';
Elsif (sig_good_strm_dbeat = '1' and
dre2ibtt_tlast = '1') Then
lsig_first_dbeat <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_LD_MARKER;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_CNTR
--
-- Process Description:
-- Implements the address offset counter that is used to
-- steer the data loads into the packer register slices.
-- Note that the counter has to be loaded with the starting
-- offset plus one to sync up with the data input.
-------------------------------------------------------------
IMP_OFFSET_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_0ffset_cntr <= (others => '0');
Elsif (lsig_ld_offset = '1') Then
lsig_0ffset_cntr <= UNSIGNED(dre2ibtt_strt_addr_offset) + OFFSET_CNT_ONE;
elsif (lsig_incr_offset = '1') then
lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PACK_REG_FULL
--
-- Process Description:
-- Implements the Packer Register full/empty flags
--
-------------------------------------------------------------
IMP_PACK_REG_FULL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
Elsif (lsig_set_packer_full = '1' and
lsig_packer_full = '0') Then
lsig_packer_full <= '1';
lsig_packer_empty <= '0';
elsif (lsig_set_packer_full = '0' and
lsig_good_push2fifo = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PACK_REG_FULL;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_REG_SLICES
--
-- For Generate Description:
--
-- Implements the Packng Register Slices
--
--
------------------------------------------------------------
DO_REG_SLICES : for slice_index in 0 to MMAP2STRM_WIDTH_RATO-1 generate
begin
-- generate the register load enable for each slice segment based
-- on the address offset count value
lsig_segment_ld(slice_index) <= '1'
when (sig_good_strm_dbeat = '1' and
TO_INTEGER(lsig_0ffset_to_to_use) = slice_index)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DATA_SLICE
--
-- Process Description:
-- Implement a data register slice abd Strobe register slice
-- for the packer (upsizer).
--
-------------------------------------------------------------
IMP_DATA_SLICE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
lsig_strb_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_data_slice_reg(slice_index) <= dre2ibtt_tdata;
lsig_strb_slice_reg(slice_index) <= dre2ibtt_tstrb;
-- optional clear of slice reg
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
lsig_strb_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_DATA_SLICE;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FLAG_SLICE
--
-- Process Description:
-- Implement a flag register slice for the packer.
--
-------------------------------------------------------------
IMP_FLAG_SLICE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_flag_slice_reg(slice_index) <= dre2ibtt_tlast & -- bit 1
dre2ibtt_eop; -- bit 0
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_FLAG_SLICE;
end generate DO_REG_SLICES;
-- Do the OR functions of the Flags -------------------------------------
lsig_tlast_or <= lsig_partial_tlast_or(MMAP2STRM_WIDTH_RATO-1) ;
lsig_eop_or <= lsig_partial_eop_or(MMAP2STRM_WIDTH_RATO-1);
lsig_partial_tlast_or(0) <= lsig_flag_slice_reg(0)(1);
lsig_partial_eop_or(0) <= lsig_flag_slice_reg(0)(0);
------------------------------------------------------------
-- For Generate
--
-- Label: DO_FLAG_OR
--
-- For Generate Description:
-- Implement the OR of the TLAST and EOP Error flags.
--
--
--
------------------------------------------------------------
DO_FLAG_OR : for slice_index in 1 to MMAP2STRM_WIDTH_RATO-1 generate
begin
lsig_partial_tlast_or(slice_index) <= lsig_partial_tlast_or(slice_index-1) or
--lsig_partial_tlast_or(slice_index);
lsig_flag_slice_reg(slice_index)(1);
lsig_partial_eop_or(slice_index) <= lsig_partial_eop_or(slice_index-1) or
--lsig_partial_eop_or(slice_index);
lsig_flag_slice_reg(slice_index)(0);
end generate DO_FLAG_OR;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_DATA_COMBINER
--
-- For Generate Description:
-- Combines the Data Slice register and Strobe slice register
-- outputs into a single data and single strobe vector used for
-- input data to the Data FIFO.
--
--
------------------------------------------------------------
DO_DATA_COMBINER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate
begin
lsig_combined_data((slice_index*DATA_SLICE_WIDTH)-1 downto
(slice_index-1)*DATA_SLICE_WIDTH) <=
lsig_data_slice_reg(slice_index-1);
lsig_combined_strb((slice_index*STRB_SLICE_WIDTH)-1 downto
(slice_index-1)*STRB_SLICE_WIDTH) <=
lsig_strb_slice_reg(slice_index-1);
end generate DO_DATA_COMBINER;
end generate INCLUDE_PACKING;
-- Data FIFO Logic ------------------------------------------
--sig_push_data_fifo <= sig_good_strm_dbeat;
sig_push_data_fifo <= sig_good_fifo_write;
sig_pop_data_fifo <= sig_skidbuf_in_tready and
sig_data_fifo_dvalid;
-- -- Concatonate the Stream inputs into the single FIFO data in value
-- sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
-- dre2ibtt_tlast &
-- dre2ibtt_tstrb &
-- dre2ibtt_tdata;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_datamover_v5_1.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => 0 ,
C_NEED_ALMOST_FULL => 0 ,
C_USE_BLKMEM => 1 ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => mmap_reset ,
SFIFO_Clk => primary_aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => sig_data_fifo_rd_cnt ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => sig_data_fifo_wr_cnt ,
SFIFO_Rd_ack => open
);
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
GEN_S2MM_TKEEP_ENABLE7 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Rip the write strobe value from the FIFO output data
sig_fifo_tstrb_out <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-3 downto
C_MMAP_DWIDTH);
end generate GEN_S2MM_TKEEP_ENABLE7;
GEN_S2MM_TKEEP_DISBALE7 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
sig_fifo_tstrb_out <= (others => '1');
end generate GEN_S2MM_TKEEP_DISBALE7;
------------------------------------------------------------
-- Instance: I_WDC_STBS_SET
--
-- Description:
-- Instance of the asserted strobe counter for the WDC
-- interface.
--
------------------------------------------------------------
SAME_WIDTH_NO_DRE_WDC : if (C_ENABLE_DRE = 0 and (C_STREAM_DWIDTH = C_MMAP_DWIDTH)) generate
begin
I_WDC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set_nodre
generic map (
C_STROBE_WIDTH => MMAP_WSTB_WIDTH
)
port map (
tstrb_in => sig_fifo_tstrb_out,
num_stbs_asserted => sig_stbs2wdc_asserted
);
end generate SAME_WIDTH_NO_DRE_WDC;
DIFF_WIDTH_OR_DRE_WDC : if (C_ENABLE_DRE /= 0 or (C_STREAM_DWIDTH /= C_MMAP_DWIDTH)) generate
begin
I_WDC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set
generic map (
C_STROBE_WIDTH => MMAP_WSTB_WIDTH
)
port map (
tstrb_in => sig_fifo_tstrb_out,
num_stbs_asserted => sig_stbs2wdc_asserted
);
end generate DIFF_WIDTH_OR_DRE_WDC;
-------------------------------------------------------------------------
------- Isolation Skid Buffer Logic (needed for Fmax timing) -----------
-------------------------------------------------------------------------
-- Skid Buffer output assignments -----------
sig_skidbuf_out_tready <= sig_wdc2ibtt_tready;
sig_ibtt2wdc_tvalid <= sig_skidbuf_out_tvalid;
sig_ibtt2wdc_tdata <= sig_skidbuf_out_tdata(C_MMAP_DWIDTH-1 downto 0) ;
sig_ibtt2wdc_tstrb <= sig_skidbuf_out_tstrb(MMAP_WSTB_WIDTH-1 downto 0) ;
sig_ibtt2wdc_tlast <= sig_skidbuf_out_tlast ;
-- Rip the EOP marker from the MS bit of the skid output strobes
sig_ibtt2wdc_eop <= sig_skidbuf_out_tstrb(MMAP_WSTB_WIDTH) ;
-- Rip the upper 8 bits of the skid output data for the strobes asserted value
sig_ibtt2wdc_stbs_asserted <= sig_skidbuf_out_tdata(SKIDBUF2WDC_DWIDTH-1 downto
C_MMAP_DWIDTH);
-- Skid Buffer input assignments -----------
sig_skidbuf_in_tvalid <= sig_data_fifo_dvalid;
sig_skidbuf_in_eop <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-1);
sig_skidbuf_in_tlast <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-2);
-- Steal the extra input strobe bit and use it for the EOP marker
---- sig_skidbuf_in_tstrb <= sig_skidbuf_in_eop &
---- sig_data_fifo_data_out(DATA_FIFO_WIDTH-3 downto
---- C_MMAP_DWIDTH);
----
sig_skidbuf_in_tstrb <= sig_skidbuf_in_eop &
sig_fifo_tstrb_out;
-- Insert the Strobes Asserted count in the extra (MS) data byte
-- for the skid buffer
sig_skidbuf_in_tdata <= sig_stbs2wdc_asserted &
sig_data_fifo_data_out(C_MMAP_DWIDTH-1 downto 0);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(2) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_INDET_BTT_SKID_BUF
--
-- Description:
-- Instance for the Store and Forward isolation Skid Buffer
-- which is required to achieve Fmax timing. Note that this
-- skid buffer is 1 byte wider than the stream data width to
-- allow for the asserted strobes count to be passed through
-- it. The EOP marker is inserted in the extra strobe slot.
--
------------------------------------------------------------
I_INDET_BTT_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => SKIDBUF2WDC_DWIDTH
)
port map (
-- System Ports
aclk => primary_aclk ,
arst => mmap_reset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Stream Data Input)
s_valid => sig_skidbuf_in_tvalid ,
s_ready => sig_skidbuf_in_tready ,
s_data => sig_skidbuf_in_tdata ,
s_strb => sig_skidbuf_in_tstrb ,
s_last => sig_skidbuf_in_tlast ,
-- Master Side (Stream Data Output
m_valid => sig_skidbuf_out_tvalid ,
m_ready => sig_skidbuf_out_tready ,
m_data => sig_skidbuf_out_tdata ,
m_strb => sig_skidbuf_out_tstrb ,
m_last => sig_skidbuf_out_tlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(2) = '0' generate
begin
sig_skidbuf_out_tvalid <= sig_skidbuf_in_tvalid;
sig_skidbuf_in_tready <= sig_skidbuf_out_tready ;
sig_skidbuf_out_tdata <= sig_skidbuf_in_tdata ;
sig_skidbuf_out_tstrb <= sig_skidbuf_in_tstrb ;
sig_skidbuf_out_tlast <= sig_skidbuf_in_tlast ;
end generate DISABLE_AXIS_SKID;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_indet_btt.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_indet_btt.vhd
--
-- Description:
-- This file implements the DataMover S2MM Indeterminate BTT support module.
-- This Module keeps track of the incoming data stream and generates a transfer
-- descriptor for each AXI MMap Burst worth of data loaded in the Data FIFO.
-- This information is stored in a separate FIFO that the Predictive Transfer
-- Calculator fetches sequentially as it is generating commands for the AXI MMap
-- bus.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0;
Use lib_pkg_v1_0.lib_pkg.clog2;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_sfifo_autord;
use axi_datamover_v5_1.axi_datamover_skid_buf;
Use axi_datamover_v5_1.axi_datamover_stbs_set;
Use axi_datamover_v5_1.axi_datamover_stbs_set_nodre;
-------------------------------------------------------------------------------
entity axi_datamover_indet_btt is
generic (
C_SF_FIFO_DEPTH : integer range 128 to 8192 := 128;
-- Sets the depth of the Data FIFO
C_IBTT_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- Sets the width of the sf2pcc_xfer_bytes port
C_STRT_OFFSET_WIDTH : Integer range 1 to 7 := 2;
-- Sets the bit width of the starting address offset port
-- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH)
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates what is set as the allowed max burst length for AXI4
-- transfers
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the width of the AXI4 MMap data path
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Indicates the width of the stream data path
C_ENABLE_SKID_BUF : string := "11111";
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_DRE : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- Clock input --------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-----------------------------------------------------------
-- Write Data Controller I/O ----------------------------------------------------------
--
ibtt2wdc_stbs_asserted : Out std_logic_vector(7 downto 0); --
-- Indicates the number of asserted WSTRB bits for the --
-- associated output stream data beat --
--
ibtt2wdc_eop : Out std_logic; --
-- Write End of Packet flag output to Write Data Controller --
--
ibtt2wdc_tdata : Out std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- Write DATA output to Write Data Controller --
--
ibtt2wdc_tstrb : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
-- Write DATA output to Write Data Controller --
--
ibtt2wdc_tlast : Out std_logic; --
-- Write LAST output to Write Data Controller --
--
ibtt2wdc_tvalid : Out std_logic; --
-- Write VALID output to Write Data Controller --
--
wdc2ibtt_tready : In std_logic; --
-- Write READY input from Write Data Controller --
---------------------------------------------------------------------------------------
-- DRE Stream In ----------------------------------------------------------------------
--
dre2ibtt_tvalid : In std_logic; --
-- DRE Stream VALID Output --
--
ibtt2dre_tready : Out Std_logic; --
-- DRE Stream READY input --
--
dre2ibtt_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- DRE Stream DATA input --
--
dre2ibtt_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- DRE Stream STRB input --
--
dre2ibtt_tlast : In std_logic; --
-- DRE Xfer LAST input --
--
dre2ibtt_eop : In std_logic; --
-- DRE Stream end of Stream packet flag --
--------------------------------------------------------------------------------------
-- Starting Address Offset Input -------------------------------------------------
--
dre2ibtt_strt_addr_offset : In std_logic_vector(C_STRT_OFFSET_WIDTH-1 downto 0); --
-- Used by Packing logic to set the initial data slice position for the --
-- packing operation. Packing is only needed if the MMap and Stream Data --
-- widths do not match. This input is sampled on the first valid DRE Stream In --
-- input databeat of a packet. --
-- --
-----------------------------------------------------------------------------------
-- Store and Forward Command Calculator Interface ---------------------------------------
--
sf2pcc_xfer_valid : Out std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the XFER_DESCR_FIFO --
--
pcc2sf_xfer_ready : in std_logic; --
-- Indicates that a full burst of data has been loaded into the data FIFO --
--
--
sf2pcc_cmd_cmplt : Out std_logic; --
-- Indicates that this is the final xfer for an associated command loaded --
-- into the Realigner by the IBTTCC interface --
--
--
sf2pcc_packet_eop : Out std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor --
--
sf2pcc_xfer_bytes : Out std_logic_vector(C_IBTT_XFER_BYTES_WIDTH-1 downto 0) --
-- This byte count is used by the IBTTCC for setting up the spawned child --
-- commands. The IBTTCC must use this count to generate the appropriate --
-- LEN value to put out on the AXI4 Write Addr Channel and the WSTRB on the AXI4 --
-- Write Data Channel. --
-----------------------------------------------------------------------------------------
);
end entity axi_datamover_indet_btt;
architecture implementation of axi_datamover_indet_btt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_cntr_width
--
-- Function Description:
-- This function calculates the needed counter bit width from the
-- number of count sates needed (input).
--
-------------------------------------------------------------------
function funct_get_cntr_width (num_cnt_values : integer) return integer is
Variable temp_cnt_width : Integer := 0;
begin
if (num_cnt_values <= 2) then
temp_cnt_width := 1;
elsif (num_cnt_values <= 4) then
temp_cnt_width := 2;
elsif (num_cnt_values <= 8) then
temp_cnt_width := 3;
elsif (num_cnt_values <= 16) then
temp_cnt_width := 4;
elsif (num_cnt_values <= 32) then
temp_cnt_width := 5;
elsif (num_cnt_values <= 64) then
temp_cnt_width := 6;
elsif (num_cnt_values <= 128) then
temp_cnt_width := 7;
else
temp_cnt_width := 8;
end if;
Return (temp_cnt_width);
end function funct_get_cntr_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 4 and 32. THis is used for sizing the SRL based XD FIFO.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 4) then
temp_pwr2 := 4;
elsif (input_value <= 8) then
temp_pwr2 := 8;
elsif (input_value <= 16) then
temp_pwr2 := 16;
else
temp_pwr2 := 32;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_PER_BYTE : integer := 8;
Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH;
Constant STRM_WSTB_WIDTH : integer := C_STREAM_DWIDTH/BITS_PER_BYTE;
Constant MMAP_WSTB_WIDTH : integer := C_MMAP_DWIDTH/BITS_PER_BYTE;
Constant STRM_STRBS_ASSERTED_WIDTH : integer := clog2(STRM_WSTB_WIDTH)+1;
-- Constant DATA_FIFO_DFACTOR : integer := 4; -- set buffer to 4 times the Max allowed Burst Length
-- Constant DATA_FIFO_DEPTH : integer := C_MAX_BURST_LEN*DATA_FIFO_DFACTOR;
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH+MMAP_WSTB_WIDTH*C_ENABLE_S2MM_TKEEP+2;
-- Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH+STRB_CNTR_WIDTH+2;
Constant DATA_FIFO_CNT_WIDTH : integer := clog2(DATA_FIFO_DEPTH)+1;
Constant BURST_CNTR_WIDTH : integer := clog2(C_MAX_BURST_LEN);
Constant MAX_BURST_DBEATS : Unsigned(BURST_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BURST_CNTR_WIDTH);
Constant DBC_ONE : Unsigned(BURST_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, BURST_CNTR_WIDTH);
Constant BYTE_CNTR_WIDTH : integer := C_IBTT_XFER_BYTES_WIDTH;
Constant BYTES_PER_MMAP_DBEAT : integer := C_MMAP_DWIDTH/BITS_PER_BYTE;
Constant BYTES_PER_STRM_DBEAT : integer := C_STREAM_DWIDTH/BITS_PER_BYTE;
--Constant MAX_BYTE_CNT : integer := C_MAX_BURST_LEN*BYTES_PER_DBEAT;
--Constant NUM_STRB_BITS : integer := BYTES_PER_DBEAT;
Constant BCNTR_ONE : Unsigned(BYTE_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, BYTE_CNTR_WIDTH);
--Constant XD_FIFO_DEPTH : integer := 16;
Constant XD_FIFO_DEPTH : integer := funct_rnd2pwr_of_2(DATA_FIFO_DEPTH/C_MAX_BURST_LEN);
Constant XD_FIFO_CNT_WIDTH : integer := clog2(XD_FIFO_DEPTH)+1;
Constant XD_FIFO_WIDTH : integer := BYTE_CNTR_WIDTH+2;
Constant MMAP_STBS_ASSERTED_WIDTH : integer := 8;
Constant SKIDBUF2WDC_DWIDTH : integer := C_MMAP_DWIDTH + MMAP_STBS_ASSERTED_WIDTH;
Constant SKIDBUF2WDC_STRB_WIDTH : integer := SKIDBUF2WDC_DWIDTH/BITS_PER_BYTE;
--Constant NUM_ZEROS_WIDTH : integer := MMAP_STBS_ASSERTED_WIDTH;
Constant STRB_CNTR_WIDTH : integer := MMAP_STBS_ASSERTED_WIDTH;
-- Signals
signal sig_wdc2ibtt_tready : std_logic := '0';
signal sig_ibtt2wdc_tvalid : std_logic := '0';
signal sig_ibtt2wdc_tdata : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tstrb : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tlast : std_logic := '0';
signal sig_ibtt2wdc_eop : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_rd_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_wr_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_push_xd_fifo : std_logic := '0';
signal sig_pop_xd_fifo : std_logic := '0';
signal sig_xd_fifo_data_in : std_logic_vector(XD_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_xd_fifo_data_out : std_logic_vector(XD_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_xd_fifo_dvalid : std_logic := '0';
signal sig_xd_fifo_full : std_logic := '0';
signal sig_tmp : std_logic := '0';
signal sig_strm_in_ready : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_good_tlast_dbeat : std_logic := '0';
signal sig_dre2ibtt_tlast_reg : std_logic := '0';
signal sig_dre2ibtt_eop_reg : std_logic := '0';
signal sig_burst_dbeat_cntr : Unsigned(BURST_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_dbeat_cntr : std_logic := '0';
signal sig_clr_dbeat_cntr : std_logic := '0';
signal sig_clr_dbc_reg : std_logic := '0';
signal sig_dbc_max : std_logic := '0';
signal sig_pcc2ibtt_xfer_ready : std_logic := '0';
signal sig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_byte_cntr : std_logic := '0';
signal sig_incr_byte_cntr : std_logic := '0';
signal sig_clr_byte_cntr : std_logic := '0';
signal sig_fifo_tstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_num_ls_zeros : integer range 0 to STRM_WSTB_WIDTH := 0;
signal sig_ls_assert_found : std_logic := '0';
signal sig_num_ms_zeros : integer range 0 to STRM_WSTB_WIDTH := 0;
signal sig_ms_assert_found : std_logic := '0';
-- signal sig_num_zeros : unsigned(NUM_ZEROS_WIDTH-1 downto 0) := (others => '0');
-- signal sig_num_ones : unsigned(NUM_ZEROS_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs2sfcc_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs2wdc_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_stbs_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tready : std_logic := '0';
signal sig_skidbuf_in_tvalid : std_logic := '0';
signal sig_skidbuf_in_tdata : std_logic_vector(SKIDBUF2WDC_DWIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tstrb : std_logic_vector(SKIDBUF2WDC_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tlast : std_logic := '0';
signal sig_skidbuf_in_eop : std_logic := '0';
signal sig_skidbuf_out_tready : std_logic := '0';
signal sig_skidbuf_out_tvalid : std_logic := '0';
signal sig_skidbuf_out_tdata : std_logic_vector(SKIDBUF2WDC_DWIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_out_tstrb : std_logic_vector(SKIDBUF2WDC_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_out_tlast : std_logic := '0';
signal sig_skidbuf_out_eop : std_logic := '0';
signal sig_enable_dbcntr : std_logic := '0';
signal sig_good_fifo_write : std_logic := '0';
begin --(architecture implementation)
-- Write Data Controller I/O
sig_wdc2ibtt_tready <= wdc2ibtt_tready ;
ibtt2wdc_tvalid <= sig_ibtt2wdc_tvalid ;
ibtt2wdc_tdata <= sig_ibtt2wdc_tdata ;
ibtt2wdc_tstrb <= sig_ibtt2wdc_tstrb ;
ibtt2wdc_tlast <= sig_ibtt2wdc_tlast ;
ibtt2wdc_eop <= sig_ibtt2wdc_eop ;
ibtt2wdc_stbs_asserted <= sig_ibtt2wdc_stbs_asserted;
-- PCC I/O
sf2pcc_xfer_valid <= sig_xd_fifo_dvalid;
sig_pcc2ibtt_xfer_ready <= pcc2sf_xfer_ready;
sf2pcc_packet_eop <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH+1);
sf2pcc_cmd_cmplt <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH);
sf2pcc_xfer_bytes <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH-1 downto 0);
-- DRE Stream In
ibtt2dre_tready <= sig_strm_in_ready;
-- sig_strm_in_ready <= not(sig_xd_fifo_full) and
-- not(sig_data_fifo_full);
sig_good_strm_dbeat <= dre2ibtt_tvalid and
sig_strm_in_ready;
sig_good_tlast_dbeat <= sig_good_strm_dbeat and
dre2ibtt_tlast;
-- Burst Packet Counter Logic -------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_DBC_STUFF
--
-- Process Description:
-- Just a register for data beat counter signals.
--
-------------------------------------------------------------
REG_DBC_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dre2ibtt_tlast_reg <= '0';
sig_dre2ibtt_eop_reg <= '0';
sig_clr_dbc_reg <= '0';
else
sig_dre2ibtt_tlast_reg <= dre2ibtt_tlast;
sig_dre2ibtt_eop_reg <= dre2ibtt_eop;
sig_clr_dbc_reg <= sig_clr_dbeat_cntr;
end if;
end if;
end process REG_DBC_STUFF;
-- sig_clr_dbc_reg <= sig_clr_dbeat_cntr;
-- Increment the dataBeat counter on a data fifo wide
-- load condition. If packer logic is enabled, this will
-- only occur when a full fifo data width has been collected
-- from the Stream input.
sig_incr_dbeat_cntr <= sig_good_strm_dbeat and
sig_enable_dbcntr;
-- Check to see if a max burst len of databeats have been
-- loaded into the FIFO
sig_dbc_max <= '1'
when (sig_burst_dbeat_cntr = MAX_BURST_DBEATS)
Else '0';
-- Start the counter over at a max burst len boundary or at
-- the end of the packet.
sig_clr_dbeat_cntr <= '1'
when (sig_dbc_max = '1' and
sig_good_strm_dbeat = '1' and
sig_enable_dbcntr = '1') or
(sig_good_tlast_dbeat = '1' and
sig_enable_dbcntr = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DBC_CMTR
--
-- Process Description:
-- The Databeat Counter keeps track of how many databeats have
-- been loaded into the Data FIFO. When a max burst worth of
-- databeats have been loaded (or a TLAST encountered), the
-- XD FIFO can be loaded with a transfer data set to be sent
-- to the IBTTCC.
--
-------------------------------------------------------------
IMP_DBC_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_dbeat_cntr = '1') then
sig_burst_dbeat_cntr <= (others => '0');
elsif (sig_incr_dbeat_cntr = '1') then
sig_burst_dbeat_cntr <= sig_burst_dbeat_cntr + DBC_ONE;
else
null; -- hold current value
end if;
end if;
end process IMP_DBC_CMTR;
----- Byte Counter Logic -----------------------------------------------
sig_clr_byte_cntr <= sig_clr_dbc_reg and
not(sig_good_strm_dbeat);
sig_ld_byte_cntr <= sig_clr_dbc_reg and
sig_good_strm_dbeat;
sig_incr_byte_cntr <= sig_good_strm_dbeat;
sig_byte_cntr_incr_value <= RESIZE(UNSIGNED(sig_stbs2sfcc_asserted), BYTE_CNTR_WIDTH);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BYTE_CMTR
--
-- Process Description:
-- Keeps a running byte count per burst packet loaded into the
-- xfer FIFO. It is based on the strobes set on the incoming
-- Stream dbeat.
--
-------------------------------------------------------------
IMP_BYTE_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_byte_cntr = '1') then
sig_byte_cntr <= (others => '0');
elsif (sig_ld_byte_cntr = '1') then
sig_byte_cntr <= sig_byte_cntr_incr_value;
elsif (sig_incr_byte_cntr = '1') then
sig_byte_cntr <= sig_byte_cntr + sig_byte_cntr_incr_value;
else
null; -- hold current value
end if;
end if;
end process IMP_BYTE_CMTR;
------------------------------------------------------------
-- Instance: I_IBTTCC_STBS_SET
--
-- Description:
-- Instance of the asserted strobe counter for the IBTTCC
-- interface.
--
------------------------------------------------------------
SAME_WIDTH_NO_DRE : if (C_ENABLE_DRE = 0 and (C_STREAM_DWIDTH = C_MMAP_DWIDTH)) generate
begin
I_IBTTCC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set_nodre
generic map (
C_STROBE_WIDTH => STRM_WSTB_WIDTH
)
port map (
tstrb_in => dre2ibtt_tstrb,
num_stbs_asserted => sig_stbs2sfcc_asserted -- 8 bit wide slv
);
end generate SAME_WIDTH_NO_DRE;
DIFF_WIDTH_OR_DRE : if (C_ENABLE_DRE /= 0 or (C_STREAM_DWIDTH /= C_MMAP_DWIDTH)) generate
begin
I_IBTTCC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set
generic map (
C_STROBE_WIDTH => STRM_WSTB_WIDTH
)
port map (
tstrb_in => dre2ibtt_tstrb,
num_stbs_asserted => sig_stbs2sfcc_asserted -- 8 bit wide slv
);
end generate DIFF_WIDTH_OR_DRE;
----- Xfer Descriptor FIFO Logic -----------------------------------------------
sig_push_xd_fifo <= sig_clr_dbc_reg ;
sig_pop_xd_fifo <= sig_pcc2ibtt_xfer_ready and
sig_xd_fifo_dvalid ;
sig_xd_fifo_data_in <= sig_dre2ibtt_eop_reg & -- (TLAST for the input Stream)
sig_dre2ibtt_tlast_reg & -- (TLAST for the IBTTCC command)
std_logic_vector(sig_byte_cntr); -- Number of bytes in this xfer
------------------------------------------------------------
-- Instance: I_XD_FIFO
--
-- Description:
-- Implement the Transfer Desciptor (XD) FIFO. This FIFO holds
-- the individual child command xfer descriptors used by the
-- IBTTCC to generate the commands sent to the Address Cntlr and
-- the Data Cntlr.
--
------------------------------------------------------------
I_XD_FIFO : entity axi_datamover_v5_1.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => XD_FIFO_WIDTH ,
C_DEPTH => XD_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => XD_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => 0 ,
C_NEED_ALMOST_FULL => 1 ,
C_USE_BLKMEM => 0 ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => mmap_reset ,
SFIFO_Clk => primary_aclk ,
SFIFO_Wr_en => sig_push_xd_fifo ,
SFIFO_Din => sig_xd_fifo_data_in ,
SFIFO_Rd_en => sig_pop_xd_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_xd_fifo_dvalid ,
SFIFO_Dout => sig_xd_fifo_data_out ,
SFIFO_Full => sig_xd_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => sig_tmp ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
----------------------------------------------------------------
-- Packing Logic ------------------------------------------
----------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_PACKING
--
-- If Generate Description:
-- Omits any packing logic in the Store and Forward module.
-- The Stream and MMap data widths are the same.
--
------------------------------------------------------------
OMIT_PACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate
begin
-- The data beat counter is always enabled when the packer
-- is omitted.
sig_enable_dbcntr <= '1';
sig_good_fifo_write <= sig_good_strm_dbeat;
sig_strm_in_ready <= not(sig_xd_fifo_full) and
not(sig_data_fifo_full) and
not (sig_tmp);
GEN_S2MM_TKEEP_ENABLE5 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Concatonate the Stream inputs into the single FIFO data
-- word input value
sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
dre2ibtt_tlast & -- Tlast marker
dre2ibtt_tstrb & -- TSTRB Value
dre2ibtt_tdata; -- data value
end generate GEN_S2MM_TKEEP_ENABLE5;
GEN_S2MM_TKEEP_DISABLE5 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Concatonate the Stream inputs into the single FIFO data
-- word input value
sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
dre2ibtt_tlast & -- Tlast marker
--dre2ibtt_tstrb & -- TSTRB Value
dre2ibtt_tdata; -- data value
end generate GEN_S2MM_TKEEP_DISABLE5;
end generate OMIT_PACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_PACKING
--
-- If Generate Description:
-- Includes packing logic in the IBTT Store and Forward
-- module. The MMap Data bus is wider than the Stream width.
--
------------------------------------------------------------
INCLUDE_PACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate
Constant TLAST_WIDTH : integer := 1; -- bit
Constant EOP_WIDTH : integer := 1; -- bit
Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH;
Constant STRB_SLICE_WIDTH : integer := STRM_WSTB_WIDTH;
Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH +
EOP_WIDTH;
Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO);
Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, OFFSET_CNTR_WIDTH);
Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH);
-- Types -----------------------------------------------------------------------------
type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(DATA_SLICE_WIDTH-1 downto 0);
type lsig_strb_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(STRB_SLICE_WIDTH-1 downto 0);
type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0);
-- local signals
signal lsig_data_slice_reg : lsig_data_slice_type;
signal lsig_strb_slice_reg : lsig_strb_slice_type;
signal lsig_flag_slice_reg : lsig_flag_slice_type;
signal lsig_reg_segment : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) := (others => '0');
signal lsig_segment_ld : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_segment_clr : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_0ffset_to_to_use : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_offset : std_logic := '0';
signal lsig_incr_offset : std_logic := '0';
signal lsig_offset_cntr_eq_max : std_logic := '0';
signal lsig_combined_data : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal lsig_combined_strb : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal lsig_tlast_or : std_logic := '0';
signal lsig_eop_or : std_logic := '0';
signal lsig_partial_tlast_or : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_partial_eop_or : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_packer_full : std_logic := '0';
signal lsig_packer_empty : std_logic := '0';
signal lsig_set_packer_full : std_logic := '0';
signal lsig_good_push2fifo : std_logic := '0';
signal lsig_first_dbeat : std_logic := '0';
begin
-- Generate the stream ready
sig_strm_in_ready <= not(sig_xd_fifo_full) and
not(sig_tmp) and
(not(lsig_packer_full) or
lsig_good_push2fifo) ;
-- Enable the Data Beat counter when the packer is
-- going full
sig_enable_dbcntr <= lsig_set_packer_full;
-- Assign the flag indicating that a fifo write is going
-- to occur at the next rising clock edge.
sig_good_fifo_write <= lsig_good_push2fifo;
GEN_S2MM_TKEEP_ENABLE6 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Format the composite FIFO input data word
sig_data_fifo_data_in <= lsig_eop_or & -- MS Bit
lsig_tlast_or &
lsig_combined_strb &
lsig_combined_data ; -- LS Bits
end generate GEN_S2MM_TKEEP_ENABLE6;
GEN_S2MM_TKEEP_DISABLE6 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Format the composite FIFO input data word
sig_data_fifo_data_in <= lsig_eop_or & -- MS Bit
lsig_tlast_or &
--lsig_combined_strb &
lsig_combined_data ; -- LS Bits
end generate GEN_S2MM_TKEEP_DISABLE6;
-- Generate a flag indicating a write to the DataFIFO
-- is going to complete
lsig_good_push2fifo <= lsig_packer_full and
not(sig_data_fifo_full);
-- Generate the control that loads the starting address
-- offset for the next input packet
lsig_ld_offset <= lsig_first_dbeat and
sig_good_strm_dbeat;
-- Generate the control for incrementing the offset counter
lsig_incr_offset <= sig_good_strm_dbeat;
-- Generate a flag indicating the packer input register
-- array is full or has loaded the last data beat of
-- the input paket
lsig_set_packer_full <= sig_good_strm_dbeat and
(dre2ibtt_tlast or
lsig_offset_cntr_eq_max);
-- Check to see if the offset counter has reached its max
-- value
lsig_offset_cntr_eq_max <= '1'
--when (lsig_0ffset_cntr = OFFSET_CNT_MAX)
when (lsig_0ffset_to_to_use = OFFSET_CNT_MAX)
Else '0';
-- Mux between the input start offset and the offset counter
-- output to use for the packer slice load control.
lsig_0ffset_to_to_use <= UNSIGNED(dre2ibtt_strt_addr_offset)
when (lsig_first_dbeat = '1')
Else lsig_0ffset_cntr;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_LD_MARKER
--
-- Process Description:
-- Implements the flop indicating the first databeat of
-- an input data packet.
--
-------------------------------------------------------------
IMP_OFFSET_LD_MARKER : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_first_dbeat <= '1';
elsif (sig_good_strm_dbeat = '1' and
dre2ibtt_tlast = '0') then
lsig_first_dbeat <= '0';
Elsif (sig_good_strm_dbeat = '1' and
dre2ibtt_tlast = '1') Then
lsig_first_dbeat <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_LD_MARKER;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_CNTR
--
-- Process Description:
-- Implements the address offset counter that is used to
-- steer the data loads into the packer register slices.
-- Note that the counter has to be loaded with the starting
-- offset plus one to sync up with the data input.
-------------------------------------------------------------
IMP_OFFSET_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_0ffset_cntr <= (others => '0');
Elsif (lsig_ld_offset = '1') Then
lsig_0ffset_cntr <= UNSIGNED(dre2ibtt_strt_addr_offset) + OFFSET_CNT_ONE;
elsif (lsig_incr_offset = '1') then
lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PACK_REG_FULL
--
-- Process Description:
-- Implements the Packer Register full/empty flags
--
-------------------------------------------------------------
IMP_PACK_REG_FULL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
Elsif (lsig_set_packer_full = '1' and
lsig_packer_full = '0') Then
lsig_packer_full <= '1';
lsig_packer_empty <= '0';
elsif (lsig_set_packer_full = '0' and
lsig_good_push2fifo = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PACK_REG_FULL;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_REG_SLICES
--
-- For Generate Description:
--
-- Implements the Packng Register Slices
--
--
------------------------------------------------------------
DO_REG_SLICES : for slice_index in 0 to MMAP2STRM_WIDTH_RATO-1 generate
begin
-- generate the register load enable for each slice segment based
-- on the address offset count value
lsig_segment_ld(slice_index) <= '1'
when (sig_good_strm_dbeat = '1' and
TO_INTEGER(lsig_0ffset_to_to_use) = slice_index)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DATA_SLICE
--
-- Process Description:
-- Implement a data register slice abd Strobe register slice
-- for the packer (upsizer).
--
-------------------------------------------------------------
IMP_DATA_SLICE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
lsig_strb_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_data_slice_reg(slice_index) <= dre2ibtt_tdata;
lsig_strb_slice_reg(slice_index) <= dre2ibtt_tstrb;
-- optional clear of slice reg
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
lsig_strb_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_DATA_SLICE;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FLAG_SLICE
--
-- Process Description:
-- Implement a flag register slice for the packer.
--
-------------------------------------------------------------
IMP_FLAG_SLICE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_flag_slice_reg(slice_index) <= dre2ibtt_tlast & -- bit 1
dre2ibtt_eop; -- bit 0
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_FLAG_SLICE;
end generate DO_REG_SLICES;
-- Do the OR functions of the Flags -------------------------------------
lsig_tlast_or <= lsig_partial_tlast_or(MMAP2STRM_WIDTH_RATO-1) ;
lsig_eop_or <= lsig_partial_eop_or(MMAP2STRM_WIDTH_RATO-1);
lsig_partial_tlast_or(0) <= lsig_flag_slice_reg(0)(1);
lsig_partial_eop_or(0) <= lsig_flag_slice_reg(0)(0);
------------------------------------------------------------
-- For Generate
--
-- Label: DO_FLAG_OR
--
-- For Generate Description:
-- Implement the OR of the TLAST and EOP Error flags.
--
--
--
------------------------------------------------------------
DO_FLAG_OR : for slice_index in 1 to MMAP2STRM_WIDTH_RATO-1 generate
begin
lsig_partial_tlast_or(slice_index) <= lsig_partial_tlast_or(slice_index-1) or
--lsig_partial_tlast_or(slice_index);
lsig_flag_slice_reg(slice_index)(1);
lsig_partial_eop_or(slice_index) <= lsig_partial_eop_or(slice_index-1) or
--lsig_partial_eop_or(slice_index);
lsig_flag_slice_reg(slice_index)(0);
end generate DO_FLAG_OR;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_DATA_COMBINER
--
-- For Generate Description:
-- Combines the Data Slice register and Strobe slice register
-- outputs into a single data and single strobe vector used for
-- input data to the Data FIFO.
--
--
------------------------------------------------------------
DO_DATA_COMBINER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate
begin
lsig_combined_data((slice_index*DATA_SLICE_WIDTH)-1 downto
(slice_index-1)*DATA_SLICE_WIDTH) <=
lsig_data_slice_reg(slice_index-1);
lsig_combined_strb((slice_index*STRB_SLICE_WIDTH)-1 downto
(slice_index-1)*STRB_SLICE_WIDTH) <=
lsig_strb_slice_reg(slice_index-1);
end generate DO_DATA_COMBINER;
end generate INCLUDE_PACKING;
-- Data FIFO Logic ------------------------------------------
--sig_push_data_fifo <= sig_good_strm_dbeat;
sig_push_data_fifo <= sig_good_fifo_write;
sig_pop_data_fifo <= sig_skidbuf_in_tready and
sig_data_fifo_dvalid;
-- -- Concatonate the Stream inputs into the single FIFO data in value
-- sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
-- dre2ibtt_tlast &
-- dre2ibtt_tstrb &
-- dre2ibtt_tdata;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_datamover_v5_1.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => 0 ,
C_NEED_ALMOST_FULL => 0 ,
C_USE_BLKMEM => 1 ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => mmap_reset ,
SFIFO_Clk => primary_aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => sig_data_fifo_rd_cnt ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => sig_data_fifo_wr_cnt ,
SFIFO_Rd_ack => open
);
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
GEN_S2MM_TKEEP_ENABLE7 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Rip the write strobe value from the FIFO output data
sig_fifo_tstrb_out <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-3 downto
C_MMAP_DWIDTH);
end generate GEN_S2MM_TKEEP_ENABLE7;
GEN_S2MM_TKEEP_DISBALE7 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
sig_fifo_tstrb_out <= (others => '1');
end generate GEN_S2MM_TKEEP_DISBALE7;
------------------------------------------------------------
-- Instance: I_WDC_STBS_SET
--
-- Description:
-- Instance of the asserted strobe counter for the WDC
-- interface.
--
------------------------------------------------------------
SAME_WIDTH_NO_DRE_WDC : if (C_ENABLE_DRE = 0 and (C_STREAM_DWIDTH = C_MMAP_DWIDTH)) generate
begin
I_WDC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set_nodre
generic map (
C_STROBE_WIDTH => MMAP_WSTB_WIDTH
)
port map (
tstrb_in => sig_fifo_tstrb_out,
num_stbs_asserted => sig_stbs2wdc_asserted
);
end generate SAME_WIDTH_NO_DRE_WDC;
DIFF_WIDTH_OR_DRE_WDC : if (C_ENABLE_DRE /= 0 or (C_STREAM_DWIDTH /= C_MMAP_DWIDTH)) generate
begin
I_WDC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set
generic map (
C_STROBE_WIDTH => MMAP_WSTB_WIDTH
)
port map (
tstrb_in => sig_fifo_tstrb_out,
num_stbs_asserted => sig_stbs2wdc_asserted
);
end generate DIFF_WIDTH_OR_DRE_WDC;
-------------------------------------------------------------------------
------- Isolation Skid Buffer Logic (needed for Fmax timing) -----------
-------------------------------------------------------------------------
-- Skid Buffer output assignments -----------
sig_skidbuf_out_tready <= sig_wdc2ibtt_tready;
sig_ibtt2wdc_tvalid <= sig_skidbuf_out_tvalid;
sig_ibtt2wdc_tdata <= sig_skidbuf_out_tdata(C_MMAP_DWIDTH-1 downto 0) ;
sig_ibtt2wdc_tstrb <= sig_skidbuf_out_tstrb(MMAP_WSTB_WIDTH-1 downto 0) ;
sig_ibtt2wdc_tlast <= sig_skidbuf_out_tlast ;
-- Rip the EOP marker from the MS bit of the skid output strobes
sig_ibtt2wdc_eop <= sig_skidbuf_out_tstrb(MMAP_WSTB_WIDTH) ;
-- Rip the upper 8 bits of the skid output data for the strobes asserted value
sig_ibtt2wdc_stbs_asserted <= sig_skidbuf_out_tdata(SKIDBUF2WDC_DWIDTH-1 downto
C_MMAP_DWIDTH);
-- Skid Buffer input assignments -----------
sig_skidbuf_in_tvalid <= sig_data_fifo_dvalid;
sig_skidbuf_in_eop <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-1);
sig_skidbuf_in_tlast <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-2);
-- Steal the extra input strobe bit and use it for the EOP marker
---- sig_skidbuf_in_tstrb <= sig_skidbuf_in_eop &
---- sig_data_fifo_data_out(DATA_FIFO_WIDTH-3 downto
---- C_MMAP_DWIDTH);
----
sig_skidbuf_in_tstrb <= sig_skidbuf_in_eop &
sig_fifo_tstrb_out;
-- Insert the Strobes Asserted count in the extra (MS) data byte
-- for the skid buffer
sig_skidbuf_in_tdata <= sig_stbs2wdc_asserted &
sig_data_fifo_data_out(C_MMAP_DWIDTH-1 downto 0);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(2) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_INDET_BTT_SKID_BUF
--
-- Description:
-- Instance for the Store and Forward isolation Skid Buffer
-- which is required to achieve Fmax timing. Note that this
-- skid buffer is 1 byte wider than the stream data width to
-- allow for the asserted strobes count to be passed through
-- it. The EOP marker is inserted in the extra strobe slot.
--
------------------------------------------------------------
I_INDET_BTT_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => SKIDBUF2WDC_DWIDTH
)
port map (
-- System Ports
aclk => primary_aclk ,
arst => mmap_reset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Stream Data Input)
s_valid => sig_skidbuf_in_tvalid ,
s_ready => sig_skidbuf_in_tready ,
s_data => sig_skidbuf_in_tdata ,
s_strb => sig_skidbuf_in_tstrb ,
s_last => sig_skidbuf_in_tlast ,
-- Master Side (Stream Data Output
m_valid => sig_skidbuf_out_tvalid ,
m_ready => sig_skidbuf_out_tready ,
m_data => sig_skidbuf_out_tdata ,
m_strb => sig_skidbuf_out_tstrb ,
m_last => sig_skidbuf_out_tlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(2) = '0' generate
begin
sig_skidbuf_out_tvalid <= sig_skidbuf_in_tvalid;
sig_skidbuf_in_tready <= sig_skidbuf_out_tready ;
sig_skidbuf_out_tdata <= sig_skidbuf_in_tdata ;
sig_skidbuf_out_tstrb <= sig_skidbuf_in_tstrb ;
sig_skidbuf_out_tlast <= sig_skidbuf_in_tlast ;
end generate DISABLE_AXIS_SKID;
end implementation;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:28:52 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top zqynq_lab_1_design_xlconcat_0_1 -prefix
-- zqynq_lab_1_design_xlconcat_0_1_ zqynq_lab_1_design_xlconcat_0_0_stub.vhdl
-- Design : zqynq_lab_1_design_xlconcat_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity zqynq_lab_1_design_xlconcat_0_1 is
Port (
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end zqynq_lab_1_design_xlconcat_0_1;
architecture stub of zqynq_lab_1_design_xlconcat_0_1 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "In0[0:0],In1[0:0],dout[1:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "xlconcat_v2_1_1_xlconcat,Vivado 2017.2";
begin
end;
|
-- NEED RESULT: ENT00197: Wait statement longest static prefix check passed
-- NEED RESULT: P1: Wait longest static prefix test completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00197
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00197(ARCH00197)
-- ENT00197_Test_Bench(ARCH00197_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
entity ENT00197 is
generic (G : integer) ;
port (
s_st_int1 : inout st_int1
) ;
--
constant CG : integer := G+1;
attribute attr : integer ;
attribute attr of CG : constant is CG+1;
--
end ENT00197 ;
--
--
architecture ARCH00197 of ENT00197 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_int1 : chk_sig_type := -1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time := 0 ns;
begin
case counter is
when 0
=>
s_st_int1 <= transport
c_st_int1_2 after 10 ns ;
wait until s_st_int1 =
c_st_int1_2 ;
Test_Report (
"ENT00197",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_int1 =
c_st_int1_2 )) ;
--
when others
=> wait ;
--
end case ;
--
savtime := Std.Standard.Now ;
counter := counter + 1;
chk_st_int1 <= transport counter after (1 us - savtime) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Wait longest static prefix test completed",
chk_st_int1 = 1 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
end ARCH00197 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00197_Test_Bench is
end ENT00197_Test_Bench ;
--
--
architecture ARCH00197_Test_Bench of ENT00197_Test_Bench is
begin
L1:
block
signal s_st_int1 : st_int1 := c_st_int1_1 ;
--
--
component UUT
generic (G : integer) ;
port (
s_st_int1 : inout st_int1 := c_st_int1_1
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00197 ( ARCH00197 ) ;
begin
CIS1 : UUT
generic map (lowb+2)
port map (
s_st_int1
)
;
end block L1 ;
end ARCH00197_Test_Bench ;
|
-- VHDL Test Bench Created from source file cpu_engine.vhd -- 12:41:11 06/20/2003
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use work.cpu_pack.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
COMPONENT cpu16
PORT(
clk_i : IN std_logic;
switch : IN std_logic_vector(9 downto 0);
ser_in : IN std_logic;
temp_spo : IN std_logic;
xm_rdat : IN std_logic_vector(7 downto 0);
ser_out : OUT std_logic;
temp_spi : OUT std_logic;
temp_ce : OUT std_logic;
temp_sclk : OUT std_logic;
seg1 : OUT std_logic_vector(7 downto 0);
seg2 : OUT std_logic_vector(7 downto 0);
led : OUT std_logic_vector(7 downto 0);
xm_adr : OUT std_logic_vector(15 downto 0);
xm_wdat : OUT std_logic_vector(7 downto 0);
xm_we : OUT std_logic;
xm_ce : OUT std_logic
);
END COMPONENT;
signal clk_i : std_logic;
signal switch : std_logic_vector(9 downto 0) := "0000000000";
signal ser_in : std_logic := '0';
signal temp_spo : std_logic := '0';
signal xm_rdat : std_logic_vector(7 downto 0) := X"33";
signal ser_out : std_logic;
signal temp_spi : std_logic := '0';
signal temp_ce : std_logic;
signal temp_sclk : std_logic;
signal seg1 : std_logic_vector(7 downto 0) := X"00";
signal seg2 : std_logic_vector(7 downto 0) := X"00";
signal led : std_logic_vector(7 downto 0);
signal xm_adr : std_logic_vector(15 downto 0);
signal xm_wdat : std_logic_vector(7 downto 0);
signal xm_we : std_logic;
signal xm_ce : std_logic;
signal clk_counter : INTEGER := 0;
BEGIN
uut: cpu16 PORT MAP(
clk_i => clk_i,
switch => switch,
ser_in => ser_in,
ser_out => ser_out,
temp_spo => temp_spo,
temp_spi => temp_spi,
temp_ce => temp_ce,
temp_sclk => temp_sclk,
seg1 => seg1,
seg2 => seg2,
led => led,
xm_adr => xm_adr,
xm_rdat => xm_rdat,
xm_wdat => xm_wdat,
xm_we => xm_we,
xm_ce => xm_ce
);
-- *** Test Bench - User Defined Section ***
PROCESS -- clock process for CLK,
BEGIN
CLOCK_LOOP : LOOP
CLK_I <= transport '0';
WAIT FOR 1 ns;
CLK_I <= transport '1';
WAIT FOR 1 ns;
WAIT FOR 11 ns;
CLK_I <= transport '0';
WAIT FOR 12 ns;
END LOOP CLOCK_LOOP;
END PROCESS;
PROCESS(CLK_I)
BEGIN
if (rising_edge(CLK_I)) then
CLK_COUNTER <= CLK_COUNTER + 1;
case CLK_COUNTER is
when 0 => switch(9 downto 8) <= "11";
when 1 => switch(9 downto 8) <= "00";
when 1000 => CLK_COUNTER <= 0;
ASSERT (FALSE) REPORT
"simulation done (no error)"
SEVERITY FAILURE;
when others =>
end case;
end if;
END PROCESS;
END;
|
-- VHDL Test Bench Created from source file cpu_engine.vhd -- 12:41:11 06/20/2003
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use work.cpu_pack.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
COMPONENT cpu16
PORT(
clk_i : IN std_logic;
switch : IN std_logic_vector(9 downto 0);
ser_in : IN std_logic;
temp_spo : IN std_logic;
xm_rdat : IN std_logic_vector(7 downto 0);
ser_out : OUT std_logic;
temp_spi : OUT std_logic;
temp_ce : OUT std_logic;
temp_sclk : OUT std_logic;
seg1 : OUT std_logic_vector(7 downto 0);
seg2 : OUT std_logic_vector(7 downto 0);
led : OUT std_logic_vector(7 downto 0);
xm_adr : OUT std_logic_vector(15 downto 0);
xm_wdat : OUT std_logic_vector(7 downto 0);
xm_we : OUT std_logic;
xm_ce : OUT std_logic
);
END COMPONENT;
signal clk_i : std_logic;
signal switch : std_logic_vector(9 downto 0) := "0000000000";
signal ser_in : std_logic := '0';
signal temp_spo : std_logic := '0';
signal xm_rdat : std_logic_vector(7 downto 0) := X"33";
signal ser_out : std_logic;
signal temp_spi : std_logic := '0';
signal temp_ce : std_logic;
signal temp_sclk : std_logic;
signal seg1 : std_logic_vector(7 downto 0) := X"00";
signal seg2 : std_logic_vector(7 downto 0) := X"00";
signal led : std_logic_vector(7 downto 0);
signal xm_adr : std_logic_vector(15 downto 0);
signal xm_wdat : std_logic_vector(7 downto 0);
signal xm_we : std_logic;
signal xm_ce : std_logic;
signal clk_counter : INTEGER := 0;
BEGIN
uut: cpu16 PORT MAP(
clk_i => clk_i,
switch => switch,
ser_in => ser_in,
ser_out => ser_out,
temp_spo => temp_spo,
temp_spi => temp_spi,
temp_ce => temp_ce,
temp_sclk => temp_sclk,
seg1 => seg1,
seg2 => seg2,
led => led,
xm_adr => xm_adr,
xm_rdat => xm_rdat,
xm_wdat => xm_wdat,
xm_we => xm_we,
xm_ce => xm_ce
);
-- *** Test Bench - User Defined Section ***
PROCESS -- clock process for CLK,
BEGIN
CLOCK_LOOP : LOOP
CLK_I <= transport '0';
WAIT FOR 1 ns;
CLK_I <= transport '1';
WAIT FOR 1 ns;
WAIT FOR 11 ns;
CLK_I <= transport '0';
WAIT FOR 12 ns;
END LOOP CLOCK_LOOP;
END PROCESS;
PROCESS(CLK_I)
BEGIN
if (rising_edge(CLK_I)) then
CLK_COUNTER <= CLK_COUNTER + 1;
case CLK_COUNTER is
when 0 => switch(9 downto 8) <= "11";
when 1 => switch(9 downto 8) <= "00";
when 1000 => CLK_COUNTER <= 0;
ASSERT (FALSE) REPORT
"simulation done (no error)"
SEVERITY FAILURE;
when others =>
end case;
end if;
END PROCESS;
END;
|
-- VHDL Test Bench Created from source file cpu_engine.vhd -- 12:41:11 06/20/2003
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use work.cpu_pack.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
COMPONENT cpu16
PORT(
clk_i : IN std_logic;
switch : IN std_logic_vector(9 downto 0);
ser_in : IN std_logic;
temp_spo : IN std_logic;
xm_rdat : IN std_logic_vector(7 downto 0);
ser_out : OUT std_logic;
temp_spi : OUT std_logic;
temp_ce : OUT std_logic;
temp_sclk : OUT std_logic;
seg1 : OUT std_logic_vector(7 downto 0);
seg2 : OUT std_logic_vector(7 downto 0);
led : OUT std_logic_vector(7 downto 0);
xm_adr : OUT std_logic_vector(15 downto 0);
xm_wdat : OUT std_logic_vector(7 downto 0);
xm_we : OUT std_logic;
xm_ce : OUT std_logic
);
END COMPONENT;
signal clk_i : std_logic;
signal switch : std_logic_vector(9 downto 0) := "0000000000";
signal ser_in : std_logic := '0';
signal temp_spo : std_logic := '0';
signal xm_rdat : std_logic_vector(7 downto 0) := X"33";
signal ser_out : std_logic;
signal temp_spi : std_logic := '0';
signal temp_ce : std_logic;
signal temp_sclk : std_logic;
signal seg1 : std_logic_vector(7 downto 0) := X"00";
signal seg2 : std_logic_vector(7 downto 0) := X"00";
signal led : std_logic_vector(7 downto 0);
signal xm_adr : std_logic_vector(15 downto 0);
signal xm_wdat : std_logic_vector(7 downto 0);
signal xm_we : std_logic;
signal xm_ce : std_logic;
signal clk_counter : INTEGER := 0;
BEGIN
uut: cpu16 PORT MAP(
clk_i => clk_i,
switch => switch,
ser_in => ser_in,
ser_out => ser_out,
temp_spo => temp_spo,
temp_spi => temp_spi,
temp_ce => temp_ce,
temp_sclk => temp_sclk,
seg1 => seg1,
seg2 => seg2,
led => led,
xm_adr => xm_adr,
xm_rdat => xm_rdat,
xm_wdat => xm_wdat,
xm_we => xm_we,
xm_ce => xm_ce
);
-- *** Test Bench - User Defined Section ***
PROCESS -- clock process for CLK,
BEGIN
CLOCK_LOOP : LOOP
CLK_I <= transport '0';
WAIT FOR 1 ns;
CLK_I <= transport '1';
WAIT FOR 1 ns;
WAIT FOR 11 ns;
CLK_I <= transport '0';
WAIT FOR 12 ns;
END LOOP CLOCK_LOOP;
END PROCESS;
PROCESS(CLK_I)
BEGIN
if (rising_edge(CLK_I)) then
CLK_COUNTER <= CLK_COUNTER + 1;
case CLK_COUNTER is
when 0 => switch(9 downto 8) <= "11";
when 1 => switch(9 downto 8) <= "00";
when 1000 => CLK_COUNTER <= 0;
ASSERT (FALSE) REPORT
"simulation done (no error)"
SEVERITY FAILURE;
when others =>
end case;
end if;
END PROCESS;
END;
|
-------------------------------------------------------------------------------
--
-- (c) Copyright 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : gtx_wrapper_v6.vhd
-- Description: GTX module for Virtex6 PCIe Block
--
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity gtx_wrapper_v6 is
generic (
NO_OF_LANES : integer := 1;
REF_CLK_FREQ : integer := 0;
PL_FAST_TRAIN : boolean := FALSE
);
port (
-- TX
TX : out std_logic_vector(NO_OF_LANES - 1 downto 0);
TXN : out std_logic_vector(NO_OF_LANES - 1 downto 0);
TxData : in std_logic_vector((NO_OF_LANES * 16) - 1 downto 0);
TxDataK : in std_logic_vector((NO_OF_LANES * 2) - 1 downto 0);
TxElecIdle : in std_logic_vector(NO_OF_LANES - 1 downto 0);
TxCompliance : in std_logic_vector(NO_OF_LANES - 1 downto 0);
-- RX
RX : in std_logic_vector(NO_OF_LANES - 1 downto 0);
RXN : in std_logic_vector(NO_OF_LANES - 1 downto 0);
RxData : out std_logic_vector((NO_OF_LANES * 16) - 1 downto 0);
RxDataK : out std_logic_vector((NO_OF_LANES * 2) - 1 downto 0);
RxPolarity : in std_logic_vector(NO_OF_LANES - 1 downto 0);
RxValid : out std_logic_vector(NO_OF_LANES - 1 downto 0);
RxElecIdle : out std_logic_vector(NO_OF_LANES - 1 downto 0);
RxStatus : out std_logic_vector((NO_OF_LANES * 3) - 1 downto 0);
-- other
GTRefClkout : out std_logic_vector(NO_OF_LANES - 1 downto 0);
plm_in_l0 : in std_logic;
plm_in_rl : in std_logic;
plm_in_dt : in std_logic;
plm_in_rs : in std_logic;
RxPLLLkDet : out std_logic_vector(NO_OF_LANES - 1 downto 0);
TxDetectRx : in std_logic;
PhyStatus : out std_logic_vector(NO_OF_LANES - 1 downto 0);
TXPdownAsynch : in std_logic;
PowerDown : in std_logic_vector((NO_OF_LANES * 2) - 1 downto 0);
Rate : in std_logic;
Reset_n : in std_logic;
GTReset_n : in std_logic;
PCLK : in std_logic;
REFCLK : in std_logic;
TxDeemph : in std_logic;
TxMargin : in std_logic;
TxSwing : in std_logic;
ChanIsAligned : out std_logic_vector(NO_OF_LANES - 1 downto 0);
local_pcs_reset : in std_logic;
RxResetDone : out std_logic;
SyncDone : out std_logic;
DRPCLK : in std_logic;
TxOutClk : out std_logic
);
end gtx_wrapper_v6;
architecture v6_pcie of gtx_wrapper_v6 is
component GTX_RX_VALID_FILTER_V6 is
generic (
CLK_COR_MIN_LAT : integer
);
port (
USER_RXCHARISK : out std_logic_vector(1 downto 0);
USER_RXDATA : out std_logic_vector(15 downto 0);
USER_RXVALID : out std_logic;
USER_RXELECIDLE : out std_logic;
USER_RX_STATUS : out std_logic_vector(2 downto 0);
USER_RX_PHY_STATUS : out std_logic;
GT_RXCHARISK : in std_logic_vector(1 downto 0);
GT_RXDATA : in std_logic_vector(15 downto 0);
GT_RXVALID : in std_logic;
GT_RXELECIDLE : in std_logic;
GT_RX_STATUS : in std_logic_vector(2 downto 0);
GT_RX_PHY_STATUS : in std_logic;
PLM_IN_L0 : in std_logic;
PLM_IN_RS : in std_logic;
USER_CLK : in std_logic;
RESET : in std_logic
);
end component;
component GTX_DRP_CHANALIGN_FIX_3752_V6 is
generic (
C_SIMULATION : integer
);
port (
dwe : out std_logic;
din : out std_logic_vector(15 downto 0);
den : out std_logic;
daddr : out std_logic_vector(7 downto 0);
drpstate : out std_logic_vector(3 downto 0);
write_ts1 : in std_logic;
write_fts : in std_logic;
dout : in std_logic_vector(15 downto 0);
drdy : in std_logic;
Reset_n : in std_logic;
drp_clk : in std_logic
);
end component;
component GTX_TX_SYNC_RATE_V6 is
generic (
C_SIMULATION : integer
);
port (
ENPMAPHASEALIGN : out std_logic;
PMASETPHASE : out std_logic;
SYNC_DONE : out std_logic;
OUT_DIV_RESET : out std_logic;
PCS_RESET : out std_logic;
USER_PHYSTATUS : out std_logic;
TXALIGNDISABLE : out std_logic;
DELAYALIGNRESET : out std_logic;
USER_CLK : in std_logic;
RESET : in std_logic;
RATE : in std_logic;
RATEDONE : in std_logic;
GT_PHYSTATUS : in std_logic;
RESETDONE : in std_logic
);
end component;
FUNCTION to_stdlogicvector (
val_in : IN integer;
length : IN integer) RETURN std_logic_vector IS
VARIABLE ret : std_logic_vector(length-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE num : integer := val_in;
VARIABLE x : integer;
BEGIN
FOR index IN 0 TO length-1 LOOP
x := num rem 2;
num := num/2;
IF (x = 1) THEN
ret(index) := '1';
ELSE
ret(index) := '0';
END IF;
END LOOP;
RETURN(ret);
END to_stdlogicvector;
FUNCTION and_bw (
val_in : std_logic_vector) RETURN std_logic IS
VARIABLE ret : std_logic := '1';
BEGIN
FOR index IN val_in'RANGE LOOP
ret := ret AND val_in(index);
END LOOP;
RETURN(ret);
END and_bw;
FUNCTION to_integer (
in_val : IN boolean) RETURN integer IS
BEGIN
IF (in_val) THEN
RETURN(1);
ELSE
RETURN(0);
END IF;
END to_integer;
FUNCTION to_stdlogic (
in_val : IN boolean) RETURN std_logic IS
BEGIN
IF (in_val) THEN
RETURN('1');
ELSE
RETURN('0');
END IF;
END to_stdlogic;
-- purpose: PLL_CP_CFG selector function
function pll_cp_cfg_sel (
ref_freq : integer)
return bit_vector is
begin -- pll_cp_cfg_sel
if (ref_freq = 2) then
return (X"05");
else
return (X"05");
end if;
end pll_cp_cfg_sel;
FUNCTION clk_div (
in_val : IN integer) RETURN integer IS
BEGIN
if (in_val = 0) THEN
return (4);
elsif (in_val = 1) then
return (5);
else
return (10);
end if;
END clk_div;
FUNCTION pll_div (
in_val : IN integer) RETURN integer IS
BEGIN
if (in_val = 0) THEN
return (5);
elsif (in_val = 1) then
return (4);
elsif (in_val = 2) then
return (2);
else
return (0);
end if;
END pll_div;
-- ground and tied_to_vcc_i signals
signal tied_to_ground_i : std_logic;
signal tied_to_ground_vec_i : std_logic_vector(31 downto 0);
signal tied_to_vcc_i : std_logic;
type type_v6pcie10 is array (NO_OF_LANES + 1 downto 0) of std_logic_vector(3 downto 0);
type type_v6pcie11 is array (NO_OF_LANES - 1 downto 0) of std_logic;
type type_v6pcie16 is array (NO_OF_LANES - 1 downto 0) of std_logic_vector(12 downto 0);
-- dummy signals to avoid port mismatch with DUAL_GTX
signal RxData_dummy : std_logic_vector(15 downto 0);
signal RxDataK_dummy : std_logic_vector(1 downto 0);
signal TxData_dummy : std_logic_vector(15 downto 0);
signal TxDataK_dummy : std_logic_vector(1 downto 0);
-- inputs
signal GTX_TxData : std_logic_vector((NO_OF_LANES * 16) - 1 downto 0);
signal GTX_TxDataK : std_logic_vector((NO_OF_LANES * 2) - 1 downto 0);
signal GTX_TxElecIdle : std_logic_vector((NO_OF_LANES) - 1 downto 0);
signal GTX_TxCompliance : std_logic_vector((NO_OF_LANES - 1) downto 0);
signal GTX_RXP : std_logic_vector((NO_OF_LANES) - 1 downto 0);
signal GTX_RXN : std_logic_vector((NO_OF_LANES) - 1 downto 0);
-- outputs
signal GTX_TXP : std_logic_vector((NO_OF_LANES) - 1 downto 0);
signal GTX_TXN : std_logic_vector((NO_OF_LANES) - 1 downto 0);
signal GTX_RxData : std_logic_vector((NO_OF_LANES * 16) - 1 downto 0);
signal GTX_RxDataK : std_logic_vector((NO_OF_LANES * 2) - 1 downto 0);
signal GTX_RxPolarity : std_logic_vector((NO_OF_LANES) - 1 downto 0);
signal GTX_RxValid : std_logic_vector((NO_OF_LANES) - 1 downto 0);
signal GTX_RxElecIdle : std_logic_vector((NO_OF_LANES) - 1 downto 0);
signal GTX_RxResetDone : std_logic_vector((NO_OF_LANES - 1) downto 0);
signal GTX_RxChbondLevel : std_logic_vector((NO_OF_LANES * 3) - 1 downto 0);
signal GTX_RxStatus : std_logic_vector((NO_OF_LANES * 3) - 1 downto 0);
signal RXCHBOND : type_v6pcie10;
signal TXBYPASS8B10B : std_logic_vector(3 downto 0);
signal RXDEC8B10BUSE : std_logic;
signal GTX_PhyStatus : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal RESETDONE : type_v6pcie11;
signal GTXRESET : std_logic;
signal RXRECCLK : std_logic;
signal SYNC_DONE : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal OUT_DIV_RESET : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal PCS_RESET : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal TXENPMAPHASEALIGN : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal TXPMASETPHASE : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal TXRESETDONE : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal TXRATEDONE : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal PHYSTATUS_int : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal RATE_CLK_SEL : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal TXOCLK : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal TXDLYALIGNDISABLE : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal TXDLYALIGNRESET : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal GTX_RxResetDone_q : std_logic_vector((NO_OF_LANES - 1) downto 0);
signal TXRESETDONE_q : std_logic_vector((NO_OF_LANES - 1) downto 0);
signal daddr : std_logic_vector((NO_OF_LANES * 8 - 1) downto 0);
signal den : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal din : std_logic_vector((NO_OF_LANES * 16 - 1) downto 0);
signal dwe : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal drpstate : std_logic_vector((NO_OF_LANES * 4 - 1) downto 0);
signal drdy : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal dout : std_logic_vector((NO_OF_LANES * 16 - 1) downto 0);
signal write_drp_cb_fts : std_logic;
signal write_drp_cb_ts1 : std_logic;
-- X-HDL generated signals
signal v6pcie12 : std_logic;
signal v6pcie13 : std_logic;
signal v6pcie14 : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal v6pcie15 : std_logic;
signal v6pcie16 : type_v6pcie16;
signal v6pcie18 : std_logic_vector(1 downto 0);
signal v6pcie21 : std_logic_vector((NO_OF_LANES*4) - 1 downto 0);
signal v6pcie23 : std_logic_vector((NO_OF_LANES*32) - 1 downto 0);
signal v6pcie24 : std_logic_vector(1 downto 0);
signal v6pcie25 : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal v6pcie26 : std_logic_vector(19 downto 0);
signal v6pcie27 : std_logic_vector((NO_OF_LANES * 4) - 1 downto 0);
signal v6pcie28 : std_logic_vector((NO_OF_LANES * 4) - 1 downto 0);
signal v6pcie29 : std_logic_vector((NO_OF_LANES * 32) - 1 downto 0) := (others => '0');
signal v6pcie30 : std_logic_vector(2 downto 0);
-- Declare intermediate signals for referenced outputs
signal RxData_v6pcie3 : std_logic_vector((NO_OF_LANES * 16) - 1 downto 0);
signal RxDataK_v6pcie4 : std_logic_vector((NO_OF_LANES * 2) - 1 downto 0);
signal RxValid_v6pcie8 : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal RxElecIdle_v6pcie5 : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal RxStatus_v6pcie7 : std_logic_vector((NO_OF_LANES * 3) - 1 downto 0);
signal RxPLLLkDet_v6pcie6 : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal PhyStatus_v6pcie1 : std_logic_vector(NO_OF_LANES - 1 downto 0);
signal ChanIsAligned_v6pcie0 : std_logic_vector(NO_OF_LANES - 1 downto 0);
begin
--------------------------- Static signal Assignments ---------------------
tied_to_ground_i <= '0';
tied_to_ground_vec_i(31 downto 0) <= (others => '0');
tied_to_vcc_i <= '1';
-- Drive referenced outputs
RxData <= RxData_v6pcie3;
RxDataK <= RxDataK_v6pcie4;
RxValid <= RxValid_v6pcie8;
RxElecIdle <= RxElecIdle_v6pcie5;
RxStatus <= RxStatus_v6pcie7;
RxPLLLkDet <= RxPLLLkDet_v6pcie6;
PhyStatus <= PhyStatus_v6pcie1;
ChanIsAligned <= ChanIsAligned_v6pcie0;
GTX_TxData <= TxData;
GTX_TxDataK <= TxDataK;
GTX_TxElecIdle <= TxElecIdle;
GTX_TxCompliance <= TxCompliance;
GTX_RXP <= RX((NO_OF_LANES) - 1 downto 0);
GTX_RXN <= RXN((NO_OF_LANES) - 1 downto 0);
GTX_RxPolarity <= RxPolarity;
TXBYPASS8B10B <= "0000";
RXDEC8B10BUSE <= '1';
GTXRESET <= '0';
RxResetDone <= and_bw((GTX_RxResetDone_q((NO_OF_LANES) - 1 downto 0)));
TX((NO_OF_LANES - 1) downto 0) <= GTX_TXP((NO_OF_LANES - 1) downto 0);
TXN((NO_OF_LANES - 1) downto 0) <= GTX_TXN((NO_OF_LANES - 1) downto 0);
RXCHBOND(0) <= "0000";
TxData_dummy <= "0000000000000000";
TxDataK_dummy <= "00";
SyncDone <= and_bw((SYNC_DONE((NO_OF_LANES - 1) downto 0)));
TxOutClk <= TXOCLK(0);
write_drp_cb_fts <= plm_in_l0;
write_drp_cb_ts1 <= plm_in_rl or plm_in_dt;
-- pipeline to improve timing
process (PCLK)
begin
if (PCLK'event and PCLK = '1') then
GTX_RxResetDone_q((NO_OF_LANES - 1) downto 0) <= GTX_RxResetDone((NO_OF_LANES - 1) downto 0);
TXRESETDONE_q((NO_OF_LANES - 1) downto 0) <= TXRESETDONE((NO_OF_LANES - 1) downto 0);
end if;
end process;
GTXD : for i in 0 to (NO_OF_LANES - 1) generate
GTX_RxChbondLevel((3 * i) + 2 downto (3 * i)) <= (to_stdlogicvector((NO_OF_LANES - (i + 1)), 3));
GTX_DRP_CHANALIGN_FIX_3752 : GTX_DRP_CHANALIGN_FIX_3752_V6
generic map (
C_SIMULATION => to_integer(PL_FAST_TRAIN)
)
port map (
dwe => dwe(i),
din => din((16 * i) + 15 downto (16 * i)),
den => den(i),
daddr => daddr((8 * i) + 7 downto (8 * i)),
drpstate => drpstate((4 * i) + 3 downto (4 * i)),
write_ts1 => write_drp_cb_ts1,
write_fts => write_drp_cb_fts,
dout => dout((16 * i) + 15 downto (16 * i)),
drdy => drdy(i),
Reset_n => Reset_n,
drp_clk => DRPCLK
);
v6pcie12 <= not(Reset_n); --I
GTX_RX_VALID_FILTER : GTX_RX_VALID_FILTER_V6
generic map (
CLK_COR_MIN_LAT => 28
)
port map (
USER_RXCHARISK => RxDataK_v6pcie4((2 * i) + 1 downto 2 * i), --O
USER_RXDATA => RxData_v6pcie3((16 * i) + 15 downto (16 * i) + 0), --O
USER_RXVALID => RxValid_v6pcie8(i), --O
USER_RXELECIDLE => RxElecIdle_v6pcie5(i), --O
USER_RX_STATUS => RxStatus_v6pcie7((3 * i) + 2 downto (3 * i)), --O
USER_RX_PHY_STATUS => PhyStatus_v6pcie1(i), --O
GT_RXCHARISK => GTX_RxDataK((2 * i) + 1 downto 2 * i), --I
GT_RXDATA => GTX_RxData((16 * i) + 15 downto (16 * i) + 0), --I
GT_RXVALID => GTX_RxValid(i), --I
GT_RXELECIDLE => GTX_RxElecIdle(i), --I
GT_RX_STATUS => GTX_RxStatus((3 * i) + 2 downto (3 * i)), --I
GT_RX_PHY_STATUS => PHYSTATUS_int(i), --I
PLM_IN_L0 => plm_in_l0, --I
PLM_IN_RS => plm_in_rs, --I
USER_CLK => PCLK, --I
RESET => v6pcie12 --I
);
v6pcie14(i) <= (TXRESETDONE_q(i) and GTX_RxResetDone_q(i)); --I
GTX_TX_SYNC : GTX_TX_SYNC_RATE_V6
generic map (
C_SIMULATION => to_integer(PL_FAST_TRAIN)
)
port map (
ENPMAPHASEALIGN => TXENPMAPHASEALIGN(i), --O
PMASETPHASE => TXPMASETPHASE(i), --O
SYNC_DONE => SYNC_DONE(i), --O
OUT_DIV_RESET => OUT_DIV_RESET(i), --O
PCS_RESET => PCS_RESET(i), --O
USER_PHYSTATUS => PHYSTATUS_int(i), --O
TXALIGNDISABLE => TXDLYALIGNDISABLE(i), --O
DELAYALIGNRESET => TXDLYALIGNRESET(i), --O
USER_CLK => PCLK, --I
RESET => v6pcie12, --I
RATE => Rate, --I
RATEDONE => TXRATEDONE(i), --I
GT_PHYSTATUS => GTX_PhyStatus(i), --I
RESETDONE => v6pcie14(i) --I
);
v6pcie15 <= not(GTReset_n);
v6pcie16(i) <= ("10000000000" & OUT_DIV_RESET(i) & '0');
v6pcie18 <= ('0' & REFCLK);
GTX_RxDataK((2 * i) + 1 downto 2 * i) <= v6pcie21((4*i)+1 downto (4*i));
GTX_RxData((16 * i) + 15 downto (16 * i) + 0) <= v6pcie23((32*i)+15 downto (32*i));
v6pcie24 <= ('1' & Rate);
v6pcie25(i) <= not(GTReset_n) or local_pcs_reset or PCS_RESET(i);
v6pcie26 <= (others => '1');
v6pcie27((4 * i) + 3 downto (4 * i) + 0) <= ("000" & GTX_TxCompliance(i));
v6pcie28((4 * i) + 3 downto (4 * i) + 0) <= (TxDataK_dummy(1 downto 0) & GTX_TxDataK((2 * i) + 1 downto 2 * i));
v6pcie29((32 * i) + 31 downto (32 * i) + 0) <= (TxData_dummy(15 downto 0) & GTX_TxData((16 * i) + 15 downto (16 * i) + 0));
v6pcie30 <= (TxMargin & "00");
GTX : GTXE1
generic map (
TX_DRIVE_MODE => "PIPE",
TX_CLK_SOURCE => "RXPLL",
POWER_SAVE => "0000100100",
CM_TRIM => "01",
PMA_CDR_SCAN => x"640404C",
PMA_CFG => x"0040000040000000003",
RCV_TERM_GND => TRUE,
RCV_TERM_VTTRX => FALSE,
RX_DLYALIGN_EDGESET => "00010",
RX_DLYALIGN_LPFINC => "0110",
RX_DLYALIGN_OVRDSETTING => "10000000",
TERMINATION_CTRL => "10101",
TERMINATION_OVRD => TRUE,
TX_DLYALIGN_LPFINC => "0110",
TX_DLYALIGN_OVRDSETTING => "10000000",
TXPLL_CP_CFG => pll_cp_cfg_sel(REF_CLK_FREQ),
OOBDETECT_THRESHOLD => "011",
RXPLL_CP_CFG => pll_cp_cfg_sel(REF_CLK_FREQ),
-------------------------------------------------------------------------
-- TX_DETECT_RX_CFG => x"1832",
-------------------------------------------------------------------------
TX_TDCC_CFG => "11",
BIAS_CFG => x"00014",
AC_CAP_DIS => FALSE,
DFE_CFG => "00011011",
SIM_TX_ELEC_IDLE_LEVEL => "1",
SIM_RECEIVER_DETECT_PASS => TRUE,
RX_EN_REALIGN_RESET_BUF => FALSE,
TX_IDLE_ASSERT_DELAY => "110", -- TX-idle-set-to-idle (13 UI)
TX_IDLE_DEASSERT_DELAY => "100", -- TX-idle-to-diff (7 UI)
CHAN_BOND_SEQ_2_CFG => "11111", -- 5'b11111 for PCIE mode, 5'b00000 for other modes
CHAN_BOND_KEEP_ALIGN => TRUE,
RX_IDLE_HI_CNT => "1000",
RX_IDLE_LO_CNT => "0000",
RX_EN_IDLE_RESET_BUF => TRUE,
TX_DATA_WIDTH => 20,
RX_DATA_WIDTH => 20,
ALIGN_COMMA_WORD => 1,
CHAN_BOND_1_MAX_SKEW => 7,
CHAN_BOND_2_MAX_SKEW => 1,
CHAN_BOND_SEQ_1_1 => "0001000101", -- D5.2 (end TS2)
CHAN_BOND_SEQ_1_2 => "0001000101", -- D5.2 (end TS2)
CHAN_BOND_SEQ_1_3 => "0001000101", -- D5.2 (end TS2)
CHAN_BOND_SEQ_1_4 => "0110111100", -- K28.5 (COM)
CHAN_BOND_SEQ_1_ENABLE => "1111", -- order is 4321
CHAN_BOND_SEQ_2_1 => "0100111100", -- K28.1 (FTS)
CHAN_BOND_SEQ_2_2 => "0100111100", -- K28.1 (FTS)
CHAN_BOND_SEQ_2_3 => "0110111100", -- K28.5 (COM)
CHAN_BOND_SEQ_2_4 => "0100111100", -- K28.1 (FTS)
CHAN_BOND_SEQ_2_ENABLE => "1111", -- order is 4321
CHAN_BOND_SEQ_2_USE => TRUE,
CHAN_BOND_SEQ_LEN => 4, -- 1..4
RX_CLK25_DIVIDER => clk_div(REF_CLK_FREQ),
TX_CLK25_DIVIDER => clk_div(REF_CLK_FREQ),
CLK_COR_ADJ_LEN => 1, -- 1..4
CLK_COR_DET_LEN => 1, -- 1..4
CLK_COR_INSERT_IDLE_FLAG => FALSE,
CLK_COR_KEEP_IDLE => FALSE,
CLK_COR_MAX_LAT => 30,
CLK_COR_MIN_LAT => 28,
CLK_COR_PRECEDENCE => TRUE,
CLK_CORRECT_USE => TRUE,
CLK_COR_REPEAT_WAIT => 0,
CLK_COR_SEQ_1_1 => "0100011100", -- K28.0 (SKP)
CLK_COR_SEQ_1_2 => "0000000000",
CLK_COR_SEQ_1_3 => "0000000000",
CLK_COR_SEQ_1_4 => "0000000000",
CLK_COR_SEQ_1_ENABLE => "1111",
CLK_COR_SEQ_2_1 => "0000000000",
CLK_COR_SEQ_2_2 => "0000000000",
CLK_COR_SEQ_2_3 => "0000000000",
CLK_COR_SEQ_2_4 => "0000000000",
CLK_COR_SEQ_2_ENABLE => "1111",
CLK_COR_SEQ_2_USE => FALSE,
COMMA_10B_ENABLE => "1111111111",
COMMA_DOUBLE => FALSE,
DEC_MCOMMA_DETECT => TRUE,
DEC_PCOMMA_DETECT => TRUE,
DEC_VALID_COMMA_ONLY => TRUE,
MCOMMA_10B_VALUE => "1010000011",
MCOMMA_DETECT => TRUE,
PCI_EXPRESS_MODE => TRUE,
PCOMMA_10B_VALUE => "0101111100",
PCOMMA_DETECT => TRUE,
RXPLL_DIVSEL_FB => pll_div(REF_CLK_FREQ), -- 1..5, 8, 10
TXPLL_DIVSEL_FB => pll_div(REF_CLK_FREQ), -- 1..5, 8, 10
RXPLL_DIVSEL_REF => 1, -- 1..6, 8, 10, 12, 16, 20
TXPLL_DIVSEL_REF => 1, -- 1..6, 8, 10, 12, 16, 20
RXPLL_DIVSEL_OUT => 2, -- 1, 2, 4
TXPLL_DIVSEL_OUT => 2, -- 1, 2, 4
RXPLL_DIVSEL45_FB => 5,
TXPLL_DIVSEL45_FB => 5,
RX_BUFFER_USE => TRUE,
RX_DECODE_SEQ_MATCH => TRUE,
RX_LOS_INVALID_INCR => 8, -- power of 2: 1..128
RX_LOSS_OF_SYNC_FSM => FALSE,
RX_LOS_THRESHOLD => 128, -- power of 2: 4..512
RX_SLIDE_MODE => "OFF", -- 00=OFF 01=AUTO 10=PCS 11=PMA
RX_XCLK_SEL => "RXREC",
TX_BUFFER_USE => FALSE, -- Must be set to FALSE for use by PCIE
TX_XCLK_SEL => "TXUSR", -- Must be set to TXUSR for use by PCIE
TXPLL_LKDET_CFG => "101",
RX_EYE_SCANMODE => "00",
RX_EYE_OFFSET => x"3F",
PMA_RX_CFG => x"05ce044",
TRANS_TIME_NON_P2 => x"02", -- Reduced simulation time
TRANS_TIME_FROM_P2 => x"03c", -- Reduced simulation time
TRANS_TIME_TO_P2 => x"064", -- Reduced simulation time
TRANS_TIME_RATE => x"D7", -- Reduced simulation time
SHOW_REALIGN_COMMA => FALSE,
TX_PMADATA_OPT => '1', -- Lockup latch between PCS and PMA
PMA_TX_CFG => x"80082", -- Aligns posedge of USRCLK
TXOUTCLK_CTRL => "TXPLLREFCLK_DIV1"
)
port map (
COMFINISH => open,
COMINITDET => open,
COMSASDET => open,
COMWAKEDET => open,
DADDR => daddr((8 * i) + 7 downto (8 * i)),
DCLK => DRPCLK,
DEN => den(i),
DFECLKDLYADJ => "010011", -- Hex 13
DFECLKDLYADJMON => open,
DFEDLYOVRD => '1',
DFEEYEDACMON => open,
DFESENSCAL => open,
DFETAP1 => "01000",
DFETAP1MONITOR => open,
DFETAP2 => tied_to_ground_vec_i(4 downto 0),
DFETAP2MONITOR => open,
DFETAP3 => tied_to_ground_vec_i(3 downto 0),
DFETAP3MONITOR => open,
DFETAP4 => tied_to_ground_vec_i(3 downto 0),
DFETAP4MONITOR => open,
DFETAPOVRD => '1',
DI => din((16 * i) + 15 downto (16 * i)),
DRDY => drdy(i),
DRPDO => dout((16 * i) + 15 downto (16 * i)),
DWE => dwe(i),
GATERXELECIDLE => '0',
GREFCLKRX => tied_to_ground_i,
GREFCLKTX => tied_to_ground_i,
GTXRXRESET => v6pcie15,
GTXTEST => v6pcie16(i),
GTXTXRESET => v6pcie15,
LOOPBACK => "000",
MGTREFCLKFAB => open,
MGTREFCLKRX => v6pcie18,
MGTREFCLKTX => v6pcie18,
NORTHREFCLKRX => tied_to_ground_vec_i(1 downto 0),
NORTHREFCLKTX => tied_to_ground_vec_i(1 downto 0),
PHYSTATUS => GTX_PhyStatus(i),
PLLRXRESET => '0',
PLLTXRESET => '0',
PRBSCNTRESET => '0',
RXBUFRESET => '0',
RXBUFSTATUS => open,
RXBYTEISALIGNED => open,
RXBYTEREALIGN => open,
RXCDRRESET => '0',
RXCHANBONDSEQ => open,
RXCHANISALIGNED => ChanIsAligned_v6pcie0(i),
RXCHANREALIGN => open,
RXCHARISCOMMA => open,
RXCHARISK => v6pcie21((4 * i) + 3 downto (4 * i)),
RXCHBONDI => RXCHBOND(i),
RXCHBONDLEVEL => GTX_RxChbondLevel((3 * i) + 2 downto (3 * i)),
RXCHBONDMASTER => to_stdlogic(i = 0),
RXCHBONDO => RXCHBOND(i + 1),
RXCHBONDSLAVE => to_stdlogic(i > 0),
RXCLKCORCNT => open,
RXCOMMADET => open,
RXCOMMADETUSE => '1',
RXDATA => v6pcie23(((32 * i) + 31) downto (32 * i)),
RXDATAVALID => open,
RXDEC8B10BUSE => RXDEC8B10BUSE,
RXDISPERR => open,
RXDLYALIGNDISABLE => '1',
RXELECIDLE => GTX_RxElecIdle(i),
RXENCHANSYNC => '1',
RXENMCOMMAALIGN => '1',
RXENPCOMMAALIGN => '1',
RXENPMAPHASEALIGN => '0',
RXENPRBSTST => "000",
RXENSAMPLEALIGN => '0',
RXDLYALIGNMONENB => '1',
RXEQMIX => "0110000011",
RXGEARBOXSLIP => '0',
RXHEADER => open,
RXHEADERVALID => open,
RXLOSSOFSYNC => open,
RXN => GTX_RXN(i),
RXNOTINTABLE => open,
RXOVERSAMPLEERR => open,
RXP => GTX_RXP(i),
RXPLLLKDET => RxPLLLkDet_v6pcie6(i),
RXPLLLKDETEN => '1',
RXPLLPOWERDOWN => '0',
RXPLLREFSELDY => "000",
RXPMASETPHASE => '0',
RXPOLARITY => GTX_RxPolarity(i),
RXPOWERDOWN => PowerDown((2 * i) + 1 downto (2 * i)),
RXPRBSERR => open,
RXRATE => v6pcie24,
RXRATEDONE => open,
RXRECCLK => RXRECCLK,
RXRECCLKPCS => open,
RXRESET => v6pcie25(i),
RXRESETDONE => GTX_RxResetDone(i),
RXRUNDISP => open,
RXSLIDE => '0',
RXSTARTOFSEQ => open,
RXSTATUS => GTX_RxStatus((3 * i) + 2 downto (3 * i)),
RXUSRCLK => PCLK,
RXUSRCLK2 => PCLK,
RXVALID => GTX_RxValid(i),
SOUTHREFCLKRX => tied_to_ground_vec_i(1 downto 0),
SOUTHREFCLKTX => tied_to_ground_vec_i(1 downto 0),
TSTCLK0 => '0',
TSTCLK1 => '0',
TSTIN => v6pcie26,
TSTOUT => open,
TXBUFDIFFCTRL => "111",
TXBUFSTATUS => open,
TXBYPASS8B10B => TXBYPASS8B10B(3 downto 0),
TXCHARDISPMODE => v6pcie27((4 * i) + 3 downto (4 * i) + 0),
TXCHARDISPVAL => "0000",
TXCHARISK => v6pcie28((4 * i) + 3 downto (4 * i) + 0),
TXCOMINIT => '0',
TXCOMSAS => '0',
TXCOMWAKE => '0',
TXDATA => v6pcie29((32 * i) + 31 downto (32 * i) + 0),
TXDEEMPH => TxDeemph,
TXDETECTRX => TxDetectRx,
TXDIFFCTRL => "1111",
TXDLYALIGNDISABLE => TXDLYALIGNDISABLE(i),
TXDLYALIGNRESET => TXDLYALIGNRESET(i),
TXELECIDLE => GTX_TxElecIdle(i),
TXENC8B10BUSE => '1',
TXENPMAPHASEALIGN => TXENPMAPHASEALIGN(i),
TXENPRBSTST => tied_to_ground_vec_i(2 downto 0),
TXGEARBOXREADY => open,
TXHEADER => tied_to_ground_vec_i(2 downto 0),
TXINHIBIT => '0',
TXKERR => open,
TXMARGIN => v6pcie30,
TXN => GTX_TXN(i),
TXOUTCLK => TXOCLK(i),
TXOUTCLKPCS => open,
TXP => GTX_TXP(i),
TXPDOWNASYNCH => TXPdownAsynch,
TXPLLLKDET => open,
TXPLLLKDETEN => '0',
TXPLLPOWERDOWN => '0',
TXPLLREFSELDY => "000",
TXPMASETPHASE => TXPMASETPHASE(i),
TXPOLARITY => '0',
TXPOSTEMPHASIS => tied_to_ground_vec_i(4 downto 0),
TXPOWERDOWN => PowerDown((2 * i) + 1 downto (2 * i)),
TXPRBSFORCEERR => tied_to_ground_i,
TXPREEMPHASIS => tied_to_ground_vec_i(3 downto 0),
TXRATE => v6pcie24,
TXRESET => v6pcie25(i),
TXRESETDONE => TXRESETDONE(i),
TXRUNDISP => open,
TXSEQUENCE => tied_to_ground_vec_i(6 downto 0),
TXSTARTSEQ => tied_to_ground_i,
TXSWING => TxSwing,
TXUSRCLK => PCLK,
TXUSRCLK2 => PCLK,
USRCODEERR => tied_to_ground_i,
IGNORESIGDET => tied_to_ground_i,
PERFCLKRX => tied_to_ground_i,
PERFCLKTX => tied_to_ground_i,
RXDLYALIGNMONITOR => open,
RXDLYALIGNOVERRIDE => '0',
RXDLYALIGNRESET => tied_to_ground_i,
RXDLYALIGNSWPPRECURB => '1',
RXDLYALIGNUPDSW => '0',
TXDLYALIGNMONITOR => open,
TXDLYALIGNOVERRIDE => '0',
TXDLYALIGNUPDSW => '0',
TXDLYALIGNMONENB => '1',
TXRATEDONE => TXRATEDONE(i)
);
end generate;
end v6_pcie;
|
-- Copyright 2000. GSI Technology
-- GSI Appications
-- [email protected]
-- v 1.0 4/23/2002 Jeff Duagherty 1) based on G16272
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY G880E18BT IS
GENERIC (
CONSTANT A_size : integer := 19;
CONSTANT DQ_size : integer := 9;
CONSTANT bank_size : integer := 1024 * 512;-- *8M /4 bytes in parallel
--250MHZ
-- CONSTANT tKQpipe : time := 2.5 ns ;
-- CONSTANT tKQflow : time := 5.5 ns ;
-- CONSTANT tKQXpipe : time := 1.5 ns ;
-- CONSTANT tKQXflow : time := 3.0 ns );
--225MHZ
-- CONSTANT tKQpipe : time := 2.7 ns ;
-- CONSTANT tKQflow : time := 6.0 ns ;
-- CONSTANT tKQXpipe : time := 1.5 ns ;
-- CONSTANT tKQXflow : time := 3.0 ns );
--200MHZ
-- CONSTANT tKQpipe : time := 3.0 ns ;
-- CONSTANT tKQflow : time := 6.5 ns ;
-- CONSTANT tKQXpipe : time := 1.5 ns ;
-- CONSTANT tKQXflow : time := 3.0 ns );
--166MHZ
CONSTANT tKQpipe : time := 3.4 ns ;
CONSTANT tKQflow : time := 7.0 ns ;
CONSTANT tKQXpipe : time := 1.5 ns ;
CONSTANT tKQXflow : time := 3.0 ns );
--150MHZ
-- CONSTANT tKQpipe : time := 3.8 ns ;
-- CONSTANT tKQflow : time := 6.7 ns ;
-- CONSTANT tKQXpipe : time := 1.5 ns ;
-- CONSTANT tKQXflow : time := 3.0 ns );
--133MHZ
-- CONSTANT tKQpipe : time := 4.0 ns ;
-- CONSTANT tKQflow : time := 8.5 ns ;
-- CONSTANT tKQXpipe : time := 1.5 ns ;
-- CONSTANT tKQXflow : time := 3.0 ns );
PORT (
SIGNAL A88 : IN std_logic_vector(A_size - 1 DOWNTO 0);-- address
SIGNAL DQa : INOUT std_logic_vector(DQ_size DOWNTO 1) BUS;-- byte A data
SIGNAL DQb : INOUT std_logic_vector(DQ_size DOWNTO 1) BUS;-- byte B data
SIGNAL nBa : IN std_logic;-- bank A write enable
SIGNAL nBb : IN std_logic;-- bank B write enable
SIGNAL CK : IN std_logic;-- clock
SIGNAL nBW : IN std_logic;-- byte write enable
SIGNAL nGW : IN std_logic;-- Global write enable
SIGNAL nE1 : IN std_logic;-- chip enable 1
SIGNAL E2 : IN std_logic;-- chip enable 1
SIGNAL nE3 : IN std_logic;-- chip enable 1
SIGNAL nG : IN std_logic;-- output enable
SIGNAL nADV : IN std_logic;-- Advance not / load
SIGNAL nADSC : IN std_logic; -- ONLY FOR BURST DEVICES
SIGNAL nADSP : IN std_logic; -- ONLY FOR BURST DEVICES
SIGNAL ZZ : IN std_logic;-- power down
SIGNAL nFT : IN std_logic;-- Pipeline / Flow through
SIGNAL nLBO : IN std_logic);-- Linear Burst Order not
END G880E18BT;
LIBRARY GSI;
LIBRARY Std;
ARCHITECTURE BURST_8MEG_x18 OF G880E18BT IS
USE GSI.FUNCTIONS.ALL;
USE Std.textio.ALL;
component VHDL_BURST_CORE
generic (
CONSTANT bank_size : integer := 1024 * 512;-- *8M /4 bytes in parallel
CONSTANT A_size : integer := 19;
CONSTANT DQ_size : integer := 9);
port (
signal A : in std_logic_vector(A_size - 1 downto 0); -- address
signal DQa : inout std_logic_vector(DQ_size downto 1) bus; -- byte A data
signal DQb : inout std_logic_vector(DQ_size downto 1) bus; -- byte B data
signal DQc : inout std_logic_vector(DQ_size downto 1) bus; -- byte C data
signal DQd : inout std_logic_vector(DQ_size downto 1) bus; -- byte D data
signal DQe : inout std_logic_vector(DQ_size downto 1) bus; -- byte E data
signal DQf : inout std_logic_vector(DQ_size downto 1) bus; -- byte F data
signal DQg : inout std_logic_vector(DQ_size downto 1) bus; -- byte G data
signal DQh : inout std_logic_vector(DQ_size downto 1) bus; -- byte H data
signal nBa : in std_logic; -- bank A write enable
signal nBb : in std_logic; -- bank B write enable
signal nBc : in std_logic; -- bank C write enable
signal nBd : in std_logic; -- bank D write enable
signal nBe : in std_logic;
signal nBf : in std_logic;
signal nBg : in std_logic;
signal nBh : in std_logic;
signal CK : in std_logic; -- clock
signal nBW : in std_logic; -- byte write enable
signal nGW : in std_logic; -- Global write enable
signal nE1 : in std_logic; -- chip enable 1
signal E2 : in std_logic; -- chip enable 2
signal nE3 : in std_logic; -- chip enable 3
signal nG : in std_logic; -- output enable
signal nADV : in std_logic; -- Advance not / load
signal nADSC : in std_logic; -- ONLY FOR BURST DEVICES
signal nADSP : in std_logic; -- ONLY FOR BURST DEVICES
signal ZZ : in std_logic; -- power down
signal nFT : in std_logic; -- Pipeline / Flow through
signal nLBO : in std_logic; -- Linear Burst Order not
signal SCD : in std_logic; -- ONLY FOR BURST DEVICES
SIGNAL HighZ : std_logic_vector(DQ_size downto 1) ;
signal tKQ : time;
signal tKQX : time);
end component;
SIGNAL HighZ : std_logic_vector(DQ_size downto 1);
SIGNAL nBc : std_logic := '1';
SIGNAL nBd : std_logic := '1';
SIGNAL nBe : std_logic := '1';
SIGNAL nBf : std_logic := '1';
SIGNAL nBg : std_logic := '1';
SIGNAL nBh : std_logic := '1';
SIGNAL SCD : std_logic := '0';-- ONLY FOR BURST DEVICES
SIGNAL DQc : std_logic_vector(DQ_size DOWNTO 1);-- byte C data
SIGNAL DQd : std_logic_vector(DQ_size DOWNTO 1);-- byte D data
SIGNAL DQe : std_logic_vector(DQ_size DOWNTO 1);-- byte E data
SIGNAL DQf : std_logic_vector(DQ_size DOWNTO 1);-- byte F data
SIGNAL DQg : std_logic_vector(DQ_size DOWNTO 1);-- byte G data
SIGNAL DQh : std_logic_vector(DQ_size DOWNTO 1);-- byte H data
signal A : std_logic_vector(A_size - 1 downto 0);
signal tKQ : time;
signal tKQX : time;
begin
tKQ <= TERNARY(nFT, tKQpipe, tKQflow);
tKQX <= TERNARY(nFT, tKQXpipe, tKQXflow);
HighZ <= to_stdlogicvector( "ZZZZZZZZZZ" ,DQ_size);
A <= to_stdlogicvector(A88, A_size);
CORE_CALL : VHDL_BURST_CORE port map (
A, DQA, DQB, DQC, DQD, DQE, DQF, DQG, DQH, NBA, NBB, NBC, NBD, NBE, NBF, NBG, NBH, CK, NBW, NGW, NE1, E2, NE3, NG, NADV, NADSC, NADSP, ZZ, NFT, NLBO, SCD, HighZ, tKQ, tKQX);
END BURST_8MEG_x18;
|
-- Copyright 2000. GSI Technology
-- GSI Appications
-- [email protected]
-- v 1.0 4/23/2002 Jeff Duagherty 1) based on G16272
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY G880E18BT IS
GENERIC (
CONSTANT A_size : integer := 19;
CONSTANT DQ_size : integer := 9;
CONSTANT bank_size : integer := 1024 * 512;-- *8M /4 bytes in parallel
--250MHZ
-- CONSTANT tKQpipe : time := 2.5 ns ;
-- CONSTANT tKQflow : time := 5.5 ns ;
-- CONSTANT tKQXpipe : time := 1.5 ns ;
-- CONSTANT tKQXflow : time := 3.0 ns );
--225MHZ
-- CONSTANT tKQpipe : time := 2.7 ns ;
-- CONSTANT tKQflow : time := 6.0 ns ;
-- CONSTANT tKQXpipe : time := 1.5 ns ;
-- CONSTANT tKQXflow : time := 3.0 ns );
--200MHZ
-- CONSTANT tKQpipe : time := 3.0 ns ;
-- CONSTANT tKQflow : time := 6.5 ns ;
-- CONSTANT tKQXpipe : time := 1.5 ns ;
-- CONSTANT tKQXflow : time := 3.0 ns );
--166MHZ
CONSTANT tKQpipe : time := 3.4 ns ;
CONSTANT tKQflow : time := 7.0 ns ;
CONSTANT tKQXpipe : time := 1.5 ns ;
CONSTANT tKQXflow : time := 3.0 ns );
--150MHZ
-- CONSTANT tKQpipe : time := 3.8 ns ;
-- CONSTANT tKQflow : time := 6.7 ns ;
-- CONSTANT tKQXpipe : time := 1.5 ns ;
-- CONSTANT tKQXflow : time := 3.0 ns );
--133MHZ
-- CONSTANT tKQpipe : time := 4.0 ns ;
-- CONSTANT tKQflow : time := 8.5 ns ;
-- CONSTANT tKQXpipe : time := 1.5 ns ;
-- CONSTANT tKQXflow : time := 3.0 ns );
PORT (
SIGNAL A88 : IN std_logic_vector(A_size - 1 DOWNTO 0);-- address
SIGNAL DQa : INOUT std_logic_vector(DQ_size DOWNTO 1) BUS;-- byte A data
SIGNAL DQb : INOUT std_logic_vector(DQ_size DOWNTO 1) BUS;-- byte B data
SIGNAL nBa : IN std_logic;-- bank A write enable
SIGNAL nBb : IN std_logic;-- bank B write enable
SIGNAL CK : IN std_logic;-- clock
SIGNAL nBW : IN std_logic;-- byte write enable
SIGNAL nGW : IN std_logic;-- Global write enable
SIGNAL nE1 : IN std_logic;-- chip enable 1
SIGNAL E2 : IN std_logic;-- chip enable 1
SIGNAL nE3 : IN std_logic;-- chip enable 1
SIGNAL nG : IN std_logic;-- output enable
SIGNAL nADV : IN std_logic;-- Advance not / load
SIGNAL nADSC : IN std_logic; -- ONLY FOR BURST DEVICES
SIGNAL nADSP : IN std_logic; -- ONLY FOR BURST DEVICES
SIGNAL ZZ : IN std_logic;-- power down
SIGNAL nFT : IN std_logic;-- Pipeline / Flow through
SIGNAL nLBO : IN std_logic);-- Linear Burst Order not
END G880E18BT;
LIBRARY GSI;
LIBRARY Std;
ARCHITECTURE BURST_8MEG_x18 OF G880E18BT IS
USE GSI.FUNCTIONS.ALL;
USE Std.textio.ALL;
component VHDL_BURST_CORE
generic (
CONSTANT bank_size : integer := 1024 * 512;-- *8M /4 bytes in parallel
CONSTANT A_size : integer := 19;
CONSTANT DQ_size : integer := 9);
port (
signal A : in std_logic_vector(A_size - 1 downto 0); -- address
signal DQa : inout std_logic_vector(DQ_size downto 1) bus; -- byte A data
signal DQb : inout std_logic_vector(DQ_size downto 1) bus; -- byte B data
signal DQc : inout std_logic_vector(DQ_size downto 1) bus; -- byte C data
signal DQd : inout std_logic_vector(DQ_size downto 1) bus; -- byte D data
signal DQe : inout std_logic_vector(DQ_size downto 1) bus; -- byte E data
signal DQf : inout std_logic_vector(DQ_size downto 1) bus; -- byte F data
signal DQg : inout std_logic_vector(DQ_size downto 1) bus; -- byte G data
signal DQh : inout std_logic_vector(DQ_size downto 1) bus; -- byte H data
signal nBa : in std_logic; -- bank A write enable
signal nBb : in std_logic; -- bank B write enable
signal nBc : in std_logic; -- bank C write enable
signal nBd : in std_logic; -- bank D write enable
signal nBe : in std_logic;
signal nBf : in std_logic;
signal nBg : in std_logic;
signal nBh : in std_logic;
signal CK : in std_logic; -- clock
signal nBW : in std_logic; -- byte write enable
signal nGW : in std_logic; -- Global write enable
signal nE1 : in std_logic; -- chip enable 1
signal E2 : in std_logic; -- chip enable 2
signal nE3 : in std_logic; -- chip enable 3
signal nG : in std_logic; -- output enable
signal nADV : in std_logic; -- Advance not / load
signal nADSC : in std_logic; -- ONLY FOR BURST DEVICES
signal nADSP : in std_logic; -- ONLY FOR BURST DEVICES
signal ZZ : in std_logic; -- power down
signal nFT : in std_logic; -- Pipeline / Flow through
signal nLBO : in std_logic; -- Linear Burst Order not
signal SCD : in std_logic; -- ONLY FOR BURST DEVICES
SIGNAL HighZ : std_logic_vector(DQ_size downto 1) ;
signal tKQ : time;
signal tKQX : time);
end component;
SIGNAL HighZ : std_logic_vector(DQ_size downto 1);
SIGNAL nBc : std_logic := '1';
SIGNAL nBd : std_logic := '1';
SIGNAL nBe : std_logic := '1';
SIGNAL nBf : std_logic := '1';
SIGNAL nBg : std_logic := '1';
SIGNAL nBh : std_logic := '1';
SIGNAL SCD : std_logic := '0';-- ONLY FOR BURST DEVICES
SIGNAL DQc : std_logic_vector(DQ_size DOWNTO 1);-- byte C data
SIGNAL DQd : std_logic_vector(DQ_size DOWNTO 1);-- byte D data
SIGNAL DQe : std_logic_vector(DQ_size DOWNTO 1);-- byte E data
SIGNAL DQf : std_logic_vector(DQ_size DOWNTO 1);-- byte F data
SIGNAL DQg : std_logic_vector(DQ_size DOWNTO 1);-- byte G data
SIGNAL DQh : std_logic_vector(DQ_size DOWNTO 1);-- byte H data
signal A : std_logic_vector(A_size - 1 downto 0);
signal tKQ : time;
signal tKQX : time;
begin
tKQ <= TERNARY(nFT, tKQpipe, tKQflow);
tKQX <= TERNARY(nFT, tKQXpipe, tKQXflow);
HighZ <= to_stdlogicvector( "ZZZZZZZZZZ" ,DQ_size);
A <= to_stdlogicvector(A88, A_size);
CORE_CALL : VHDL_BURST_CORE port map (
A, DQA, DQB, DQC, DQD, DQE, DQF, DQG, DQH, NBA, NBB, NBC, NBD, NBE, NBF, NBG, NBH, CK, NBW, NGW, NE1, E2, NE3, NG, NADV, NADSC, NADSP, ZZ, NFT, NLBO, SCD, HighZ, tKQ, tKQX);
END BURST_8MEG_x18;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:45:28 03/02/2015
-- Design Name:
-- Module Name: reg_128 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity reg_128 is
port(clk : in std_logic;
rst : in std_logic;
data_in_0 : in std_logic_vector(31 downto 0);
data_in_1 : in std_logic_vector(31 downto 0);
data_in_2 : in std_logic_vector(31 downto 0);
data_in_3 : in std_logic_vector(31 downto 0);
data_out_0 : out std_logic_vector(31 downto 0);
data_out_1 : out std_logic_vector(31 downto 0);
data_out_2 : out std_logic_vector(31 downto 0);
data_out_3 : out std_logic_vector(31 downto 0));
end reg_128;
architecture Behavioral of reg_128 is
signal reg_32_0_s : std_logic_vector(31 downto 0);
signal reg_32_1_s : std_logic_vector(31 downto 0);
signal reg_32_2_s : std_logic_vector(31 downto 0);
signal reg_32_3_s : std_logic_vector(31 downto 0);
begin
pr_reg: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
reg_32_0_s <= (others => '0');
reg_32_1_s <= (others => '0');
reg_32_2_s <= (others => '0');
reg_32_3_s <= (others => '0');
else
reg_32_0_s <= data_in_0;
reg_32_1_s <= data_in_1;
reg_32_2_s <= data_in_2;
reg_32_3_s <= data_in_3;
end if;
end if;
end process;
data_out_0 <= reg_32_0_s;
data_out_1 <= reg_32_1_s;
data_out_2 <= reg_32_2_s;
data_out_3 <= reg_32_3_s;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:45:28 03/02/2015
-- Design Name:
-- Module Name: reg_128 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity reg_128 is
port(clk : in std_logic;
rst : in std_logic;
data_in_0 : in std_logic_vector(31 downto 0);
data_in_1 : in std_logic_vector(31 downto 0);
data_in_2 : in std_logic_vector(31 downto 0);
data_in_3 : in std_logic_vector(31 downto 0);
data_out_0 : out std_logic_vector(31 downto 0);
data_out_1 : out std_logic_vector(31 downto 0);
data_out_2 : out std_logic_vector(31 downto 0);
data_out_3 : out std_logic_vector(31 downto 0));
end reg_128;
architecture Behavioral of reg_128 is
signal reg_32_0_s : std_logic_vector(31 downto 0);
signal reg_32_1_s : std_logic_vector(31 downto 0);
signal reg_32_2_s : std_logic_vector(31 downto 0);
signal reg_32_3_s : std_logic_vector(31 downto 0);
begin
pr_reg: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
reg_32_0_s <= (others => '0');
reg_32_1_s <= (others => '0');
reg_32_2_s <= (others => '0');
reg_32_3_s <= (others => '0');
else
reg_32_0_s <= data_in_0;
reg_32_1_s <= data_in_1;
reg_32_2_s <= data_in_2;
reg_32_3_s <= data_in_3;
end if;
end if;
end process;
data_out_0 <= reg_32_0_s;
data_out_1 <= reg_32_1_s;
data_out_2 <= reg_32_2_s;
data_out_3 <= reg_32_3_s;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:45:28 03/02/2015
-- Design Name:
-- Module Name: reg_128 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity reg_128 is
port(clk : in std_logic;
rst : in std_logic;
data_in_0 : in std_logic_vector(31 downto 0);
data_in_1 : in std_logic_vector(31 downto 0);
data_in_2 : in std_logic_vector(31 downto 0);
data_in_3 : in std_logic_vector(31 downto 0);
data_out_0 : out std_logic_vector(31 downto 0);
data_out_1 : out std_logic_vector(31 downto 0);
data_out_2 : out std_logic_vector(31 downto 0);
data_out_3 : out std_logic_vector(31 downto 0));
end reg_128;
architecture Behavioral of reg_128 is
signal reg_32_0_s : std_logic_vector(31 downto 0);
signal reg_32_1_s : std_logic_vector(31 downto 0);
signal reg_32_2_s : std_logic_vector(31 downto 0);
signal reg_32_3_s : std_logic_vector(31 downto 0);
begin
pr_reg: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
reg_32_0_s <= (others => '0');
reg_32_1_s <= (others => '0');
reg_32_2_s <= (others => '0');
reg_32_3_s <= (others => '0');
else
reg_32_0_s <= data_in_0;
reg_32_1_s <= data_in_1;
reg_32_2_s <= data_in_2;
reg_32_3_s <= data_in_3;
end if;
end if;
end process;
data_out_0 <= reg_32_0_s;
data_out_1 <= reg_32_1_s;
data_out_2 <= reg_32_2_s;
data_out_3 <= reg_32_3_s;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc822.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s02b02x00p02n01i00822ent IS
END c01s02b02x00p02n01i00822ent;
ARCHITECTURE c01s02b02x00p02n01i00822arch OF c01s02b02x00p02n01i00822ent IS
BEGIN
if TRUE then -- illegal location for if statement
end if;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s02b02x00p02n01i00822 - Architecture statement can only have concurrent statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s02b02x00p02n01i00822arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc822.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s02b02x00p02n01i00822ent IS
END c01s02b02x00p02n01i00822ent;
ARCHITECTURE c01s02b02x00p02n01i00822arch OF c01s02b02x00p02n01i00822ent IS
BEGIN
if TRUE then -- illegal location for if statement
end if;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s02b02x00p02n01i00822 - Architecture statement can only have concurrent statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s02b02x00p02n01i00822arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc822.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s02b02x00p02n01i00822ent IS
END c01s02b02x00p02n01i00822ent;
ARCHITECTURE c01s02b02x00p02n01i00822arch OF c01s02b02x00p02n01i00822ent IS
BEGIN
if TRUE then -- illegal location for if statement
end if;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s02b02x00p02n01i00822 - Architecture statement can only have concurrent statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s02b02x00p02n01i00822arch;
|
library IEEE;
use IEEE.std_logic_1164.all;
--------------------------------------------------------------------------------
package body main_tb_pkg is
function done (
RESULTS : T_TESTRESULTS
) return std_logic is
variable T : std_logic := '1';
begin
for I in RESULTS'range loop
T := T and RESULTS(I).DONE;
end loop;
return T;
end function done;
function failures (
RESULTS : T_TESTRESULTS
) return natural is
variable C : natural := 0;
begin
for I in RESULTS'range loop
if RESULTS(I).PASS_nFAIL = '0' then
C := C + 1;
end if;
end loop;
return C;
end function failures;
end main_tb_pkg; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
entity boot_ram is
generic(memory_file : string := "boot.txt";
data_width: integer := 8; -- data width (fixed)
address_width: integer := 12; -- address width
bank: integer := 0); -- memory bank (0,1,2,3)
port(
clk : in std_logic; --clock
addr : in std_logic_vector(address_width - 1 downto 2); --address bus
cs_n : in std_logic; --chip select
we_n : in std_logic; --write enable
data_i: in std_logic_vector(data_width - 1 downto 0); --write data bus
data_o: out std_logic_vector(data_width - 1 downto 0) --read data bus
);
end boot_ram;
architecture memory of boot_ram is
type ram is array(2 ** address_width - 1 downto 0) of std_logic_vector(data_width - 1 downto 0);
signal ram1 : ram := (others => (others => '0'));
begin
process(clk)
variable data : std_logic_vector(data_width*4 -1 downto 0);
variable index : natural := 0;
file load_file : text open read_mode is "boot.txt";
variable hex_file_line : line;
begin
--Load in the ram executable image
if index = 0 then
while not endfile(load_file) loop
readline(load_file, hex_file_line);
hread(hex_file_line, data);
ram1(conv_integer(index)) <= data(((bank+1)*data_width)-1 downto bank*data_width);
index := index + 1;
end loop;
end if;
if (clk'event and clk = '1') then
if(cs_n = '0') then
if(we_n = '0') then
ram1(conv_integer(addr(address_width -1 downto 2))) <= data_i;
else
data_o <= ram1(conv_integer(addr(address_width -1 downto 2)));
end if;
end if;
end if;
end process;
end memory;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
entity boot_ram is
generic(memory_file : string := "boot.txt";
data_width: integer := 8; -- data width (fixed)
address_width: integer := 12; -- address width
bank: integer := 0); -- memory bank (0,1,2,3)
port(
clk : in std_logic; --clock
addr : in std_logic_vector(address_width - 1 downto 2); --address bus
cs_n : in std_logic; --chip select
we_n : in std_logic; --write enable
data_i: in std_logic_vector(data_width - 1 downto 0); --write data bus
data_o: out std_logic_vector(data_width - 1 downto 0) --read data bus
);
end boot_ram;
architecture memory of boot_ram is
type ram is array(2 ** address_width - 1 downto 0) of std_logic_vector(data_width - 1 downto 0);
signal ram1 : ram := (others => (others => '0'));
begin
process(clk)
variable data : std_logic_vector(data_width*4 -1 downto 0);
variable index : natural := 0;
file load_file : text open read_mode is "boot.txt";
variable hex_file_line : line;
begin
--Load in the ram executable image
if index = 0 then
while not endfile(load_file) loop
readline(load_file, hex_file_line);
hread(hex_file_line, data);
ram1(conv_integer(index)) <= data(((bank+1)*data_width)-1 downto bank*data_width);
index := index + 1;
end loop;
end if;
if (clk'event and clk = '1') then
if(cs_n = '0') then
if(we_n = '0') then
ram1(conv_integer(addr(address_width -1 downto 2))) <= data_i;
else
data_o <= ram1(conv_integer(addr(address_width -1 downto 2)));
end if;
end if;
end if;
end process;
end memory;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/31/2017 03:31:33 PM
-- Design Name:
-- Module Name: Debug_Controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library config;
use work.config.all;
entity Debug_Controller is
port (clk,RST: in STD_LOGIC;
HALT: out STD_LOGIC;
REGGIE: in regfile_arr;
PC_IN: in doubleword;
UART_RXD: in STD_LOGIC;
UART_TXD : out STD_LOGIC);
end Debug_Controller;
architecture Behavioral of Debug_Controller is
component UART_RX_CTRL is
port (UART_RX: in STD_LOGIC;
CLK: in STD_LOGIC;
DATA: out STD_LOGIC_VECTOR (7 downto 0);
READ_DATA: out STD_LOGIC;
RESET_READ: in STD_LOGIC
);
end component;
component UART_TX_CTRL is
port( SEND : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
READY : out STD_LOGIC;
UART_TX : out STD_LOGIC);
end component;
-- Types
type CHAR_ARRAY is array (integer range<>) of std_logic_vector(7 downto 0);
type UART_STATE_TYPE is (IDLE, RECEIVE, UNPAUSE, DECODE, REGISTERS, PC, STEP, STEP_HI, STEP_LO, SEND_CHAR, REGFILE, REGFILE_I, SEND_CHAR_2, SEND_CHAR_3, SEND_CHAR_4, WAIT_CHAR, KEEP_WAITING_CHAR, LD_REGISTERS_STR, RESET_LO, RESET_HI);
type BOUNDS is array (integer range<>) of integer;
-- Constants
constant MAX_STR_LEN : integer := 501;
constant MAX_REGISTER_LEN : integer := 23;
constant RESET_CNTR_MAX : std_logic_vector(17 downto 0) := "110000110101000000";-- 100,000,000 * 0.002 = 200,000 = clk cycles per 2 ms
-- Signals
signal uart_curr_state, uart_next_state : UART_STATE_TYPE := idle;
signal uartRdy, uartSend ,uartTX: std_logic;
signal uartData: std_logic_vector(7 downto 0);
signal sendStr : CHAR_ARRAY(0 to (MAX_STR_LEN - 1)) := ( others => (others => '0'));
signal reset_cntr : std_logic_vector (17 downto 0) := (others=>'0');
-- String counters
signal reggie_counter : integer := 0;
signal reggie_str_counter : integer := 12;
signal reggie_counter_counter : integer := 0;
signal strEnd, strIndex: natural := 0;
signal strConcatCtr: integer := 0;
signal pc_str_counter: integer := 0;
signal pc_reg: doubleword := (others => '0');
-- CPU halt interface
signal halt_l : std_logic := '1';
-- UART RX and TX signals
signal uart_data_in: STD_LOGIC_VECTOR(7 DOWNTO 0);
signal data_available, reset_read: STD_LOGIC;
signal rx_str : CHAR_ARRAY(30 DOWNTO 0);
signal rx_str_ctr : integer := 0;
signal d_clk: std_logic := '0';
begin
DEBUG_UART_TX: UART_TX_CTRL port map(SEND => uartSend,
DATA => uartData,
CLK => CLK,
READY => uartRdy,
UART_TX => UART_TXD );
DEBUG_UART_RX: UART_RX_CTRL
port map(
UART_RX => UART_RXD,
CLK => CLK,
DATA => uart_data_in,
READ_DATA => data_available,
RESET_READ => reset_read
);
--State Machine transition
DEBUG_FSM: process(clk, rst) begin
if(rst = '1') then
uart_curr_state <= IDLE;
elsif(rising_edge(clk)) then
uart_curr_state <= uart_next_state;
end if;
end process;
HALT <= halt_l;
-- Generate the debug clock d_clk
D_CLK_GEN: process(clk) begin
if(rising_edge(clk)) then
if(halt_l = '0') then
d_clk <= d_clk xor '1';
end if;
end if;
end process;
DEBUG_FSM_TRANSITION: process(clk, rst)
variable internal_register_int: integer;
variable has_r_been_pressed_yet: integer;
begin
if(rst = '1') then
strConcatCtr <= 0;
reggie_str_counter <= 0;
reset_read <= '1';
uart_next_state <= IDLE;
strIndex <= 0;
halt_l <= '1';
has_r_been_pressed_yet := 0;
elsif(rising_edge(clk)) then
case uart_curr_state is
-- State IDLE: Nothing happening
when IDLE =>
reggie_counter_counter <= 0;
reggie_str_counter <= 0;
strConcatCtr <= 0;
strEnd <= 25;
uartSend <= '0';
strIndex <= 0;
reset_read <= '0';
reggie_counter <= 0;
pc_str_counter <= 0;
uart_next_state <= IDLE;
-- Default go to IDLE
if(data_available = '1' AND uartRdy = '1' ) then -- If we have data and not outputing anything
rx_str(0) <= uart_data_in; -- Save the data
uart_next_state <= DECODE;
end if;
-- State DECODE: Decode what function the user is accessing
when DECODE =>
if(rx_str(0) = X"72") then
uart_next_state <= REGFILE;
reggie_counter <= 0;
strEnd <= 500;
elsif(rx_str(0) = X"30") then
internal_register_int := 0;
uart_next_state <= REGFILE;
elsif(rx_str(0) = X"31") then
internal_register_int := 12;
uart_next_state <= REGFILE;
elsif(rx_str(0) = X"32") then
internal_register_int := 13;
uart_next_state <= REGFILE;
elsif(rx_str(0) = X"33") then
internal_register_int := 14;
uart_next_state <= REGFILE;
elsif(rx_str(0) = X"34") then
internal_register_int := 15;
uart_next_state <= REGFILE;
elsif(rx_str(0) = X"73") then
uart_next_state <= STEP;
elsif(rx_str(0) = X"75") then
uart_next_state <= UNPAUSE;
elsif(rx_str(0) = X"70") then
uart_next_state <= PC;
strEnd <= 23;
pc_reg <= PC_IN;
else
uart_next_state <= IDLE;
end if;
-- State REGFILE: Print out the entire register file
-- TODO: it is now less crappy
-- To use type rxx, where xx is the register number to access.
-- reggie_counter_counter is the length of the string printed per register
when REGFILE =>
uart_next_state <= REGFILE;
if( reggie_counter_counter = 23) then
reggie_counter <= reggie_counter + 1;
end if;
if(reggie_counter >= 19) then
uart_next_state <= REGISTERS;
else
reggie_str_counter <= reggie_str_counter + 1;
case reggie_str_counter is
when 0 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"72";
reggie_counter_counter <= 0;
when 2 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(std_logic_vector(to_unsigned(reggie_counter, 5)));
reggie_counter_counter <= 1;
when 1 => if(reggie_counter = 32) then
sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(X"2");
elsif(reggie_counter > 15) then
sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(X"1");
else
sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(X"0");
end if;
reggie_counter_counter <= 2;
when 3 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"78";
reggie_counter_counter <= 2;
when 4 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(63 downto 60));
reggie_counter_counter <= 3;
when 5 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(59 downto 56));
reggie_counter_counter <= 4;
when 6 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(55 downto 52));
reggie_counter_counter <= 5;
when 7 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(51 downto 48));
reggie_counter_counter <= 6;
when 8 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(47 downto 44));
reggie_counter_counter <= 7;
when 9 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(43 downto 40));
reggie_counter_counter <= 8;
when 10 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(39 downto 36));
reggie_counter_counter <= 9;
when 11 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(35 downto 32));
reggie_counter_counter <= 10;
when 12 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(31 downto 28));
reggie_counter_counter <= 11;
when 13 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(27 downto 24));
reggie_counter_counter <= 12;
when 14 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(23 downto 20));
reggie_counter_counter <= 13;
when 15 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(19 downto 16));
reggie_counter_counter <= 14;
when 16 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(15 downto 12));
reggie_counter_counter <= 15;
when 17 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(11 downto 8));
reggie_counter_counter <= 16;
when 18 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(7 downto 4));
reggie_counter_counter <= 17;
when 19 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(reggie_counter)(3 downto 0));
reggie_counter_counter <= 18;
when 20 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"20";
reggie_counter_counter <= 19;
when 21 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"0A";
reggie_counter_counter <= 20;
when 22 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"0A";
reggie_counter_counter <= 21;
when 23 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"0A";
reggie_counter_counter <= 22;
when 24 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"0A";
reggie_counter_counter <= 23;
reggie_str_counter <= 0;
when others => sendStr(24) <= X"20";
end case;
end if;
when REGFILE_I =>
-- MSD to the left
if(internal_register_int > 31) then
uart_next_state <= IDLE; --Don't do nothing
else
uart_next_state <= REGFILE;
-- (reggie_counter_counter = 23) then
reggie_counter <= reggie_counter + 1;
end if;
if(reggie_str_counter > 23) then
uart_next_state <= REGISTERS;
else
reggie_str_counter <= reggie_str_counter + 1;
case reggie_str_counter is
when 0 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"72";
reggie_counter_counter <= 0;
when 1 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(std_logic_vector(to_unsigned(internal_register_int, 8)));
reggie_counter_counter <= 1;
when 2 => if(reggie_counter = 32) then
sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(X"2");
elsif(reggie_counter > 15) then
sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(X"1");
else
sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(X"0");
end if;
reggie_counter_counter <= 2;
when 3 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"78";
reggie_counter_counter <= 2;
when 4 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(63 downto 60));
reggie_counter_counter <= 3;
when 5 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(59 downto 56));
reggie_counter_counter <= 4;
when 6 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(55 downto 52));
reggie_counter_counter <= 5;
when 7 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(51 downto 48));
reggie_counter_counter <= 6;
when 8 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(47 downto 44));
reggie_counter_counter <= 7;
when 9 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(43 downto 40));
reggie_counter_counter <= 8;
when 10 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(39 downto 36));
reggie_counter_counter <= 9;
when 11 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(35 downto 32));
reggie_counter_counter <= 10;
when 12 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(31 downto 28));
reggie_counter_counter <= 11;
when 13 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(27 downto 24));
reggie_counter_counter <= 12;
when 14 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(23 downto 20));
reggie_counter_counter <= 13;
when 15 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(19 downto 16));
reggie_counter_counter <= 14;
when 16 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(15 downto 12));
reggie_counter_counter <= 15;
when 17 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(11 downto 8));
reggie_counter_counter <= 16;
when 18 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(7 downto 4));
reggie_counter_counter <= 17;
when 19 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= HEX_TO_ASCII(reggie(internal_register_int)(3 downto 0));
reggie_counter_counter <= 18;
when 20 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"20";
reggie_counter_counter <= 19;
when 21 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"0A";
reggie_counter_counter <= 20;
when 22 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"0A";
reggie_counter_counter <= 21;
when 23 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"0A";
reggie_counter_counter <= 22;
when 24 => sendStr(reggie_counter * MAX_REGISTER_LEN + reggie_str_counter) <= X"0A";
reggie_counter_counter <= 23;
reggie_str_counter <= 0;
when others => sendStr(24) <= X"20";
end case;
end if;
when PC =>
uart_next_state <= PC;
if(pc_str_counter > 21) then
uart_next_state <= SEND_CHAR;
else
pc_str_counter <= pc_str_counter + 1;
case pc_str_counter is
when 1 => sendStr(pc_str_counter) <= X"50";
when 2 => sendStr(pc_str_counter) <= X"43";
when 3 => sendStr(pc_str_counter) <= X"3A";
when 4 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(63 downto 60));
when 5 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(59 downto 56));
when 6 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(55 downto 52));
when 7 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(51 downto 48));
when 8 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(47 downto 44));
when 9 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(43 downto 40));
when 10 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(39 downto 36));
when 11 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(35 downto 32));
when 12 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(31 downto 28));
when 13 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(27 downto 24));
when 14 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(23 downto 20));
when 15 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(19 downto 16));
when 16 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(15 downto 12));
when 17 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(11 downto 8));
when 18 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(7 downto 4));
when 19 => sendStr(pc_str_counter) <= HEX_TO_ASCII(PC_reg(3 downto 0));
when 20 => sendStr(pc_str_counter) <= X"20";
when 21 => sendStr(pc_str_counter) <= X"0A";
when 22 => sendStr(pc_str_counter) <= X"0A";
when 23 => sendStr(pc_str_counter) <= X"0A";
when 24 => sendStr(pc_str_counter) <= X"0A";
when others => sendStr(24) <= X"20";
end case;
end if;
-- State STEP: Step one clock cycle
-- halt_l is 0, allows the CPU to continue for one clock cycle
when STEP =>
halt_l <= '0';
uart_next_state <= STEP_HI;
-- State STEP_HI: One step done
-- halt_l is 1, halts the processor
when STEP_HI =>
halt_l <= '1';
uart_next_state <= STEP_LO;
-- State STEP_LO: One step done
-- If the user wants to skip 2 clock cycles instead of one,
-- STEP_HI can set halt_l to 0 and STEP_LO can be set to 1
-- This can be
when STEP_LO =>
halt_l <= '1';
uart_next_state <= RESET_LO;
-- State REGISTERS: Once the strings are prepared, send the characters
when REGISTERS =>
uart_next_state <= SEND_CHAR;
-- State SEND_CHAR: Tell the UART controller to print things
when SEND_CHAR =>
strIndex <= strIndex + 1;
uartSend <= '1';
uartData <= sendStr(strIndex);
uart_next_state <= WAIT_CHAR;
-- State WAIT_CHAR: Checks if the entirety of the string
-- has been sent
when WAIT_CHAR =>
uart_next_state <= WAIT_CHAR;
if(strEnd <= strIndex) then
uart_next_state <= RESET_LO;
elsif(uartRdy = '1') then
uart_next_state <= SEND_CHAR;
end if;
-- State RESET_LO: Resets the RX_UART to flush whatever it
-- had as an input to prepare for the next function
when RESET_LO =>
reset_read <= '1';
uart_next_state <= RESET_HI;
-- State RESET_HI:
when RESET_HI =>
reset_read <= '0';
uart_next_state <= IDLE;
-- State UNPAUSE: Lifts the halt_l, allowing the CPU to run normally
when UNPAUSE =>
halt_l <= '0';
uart_next_state <= RESET_LO;
when OTHERS =>
uart_next_state <= IDLE;
end case;
end if;
end process;
end Behavioral; |
-- $Id: simbididly.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: simbididly - sim
-- Description: Bi-directional bus delay for test benches
--
-- Dependencies: -
-- Test bench: tb_simbididly
-- Target Devices: generic
-- Tool versions: xst 14.7; viv 2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-07-23 793 1.0.1 ensure non-zero DELAY
-- 2016-07-17 789 1.0 Initial version (use separate driver regs now)
-- 2016-07-16 787 0.1 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity simbididly is -- test bench bi-directional bus delay
generic (
DELAY : Delay_length; -- transport delay between A and B (>0ns!)
DWIDTH : positive := 16); -- data port width
port (
A : inout slv(DWIDTH-1 downto 0); -- port A
B : inout slv(DWIDTH-1 downto 0) -- port B
);
end entity simbididly;
architecture sim of simbididly is
type state_type is (
s_idle, -- s_idle: both ports high-z
s_a2b, -- s_a2b: A drives, B listens
s_b2a -- s_b2a: B drives, A listens
);
constant all_z : slv(DWIDTH-1 downto 0) := (others=>'Z');
signal R_STATE : state_type := s_idle;
signal R_A : slv(DWIDTH-1 downto 0) := (others=>'Z');
signal R_B : slv(DWIDTH-1 downto 0) := (others=>'Z');
begin
process
variable istate : state_type := s_idle;
begin
-- the delay model can enter into a delta cycle oszillation mode
-- when DELAY is 0 ns. So ensure the delay is non-zero
assert DELAY > 0 ns report "DELAY > 0 ns" severity failure;
while true loop
-- if idle check whether A or B port starts to drive bus
-- Note: both signal R_STATE and variable istate is updated
-- istate is needed to control the driver section below in the
-- same delta cycle based on the most recent state state
istate := R_STATE;
if now > 0 ns then -- to avoid startup problems
if R_STATE = s_idle then
if A /= all_z then
R_STATE <= s_a2b;
istate := s_a2b;
elsif B /= all_z then
R_STATE <= s_b2a;
istate := s_b2a;
end if;
end if;
end if;
case istate is
when s_a2b =>
R_B <= transport A after DELAY;
if A = all_z then R_STATE <= s_idle after DELAY; end if;
when s_b2a =>
R_A <= transport B after DELAY;
if B = all_z then R_STATE <= s_idle after DELAY; end if;
when others => null;
end case;
-- Note: the driver clash check is done by comparing an internal signal
-- with the external signal. If they differ this indicates a clash.
-- Just checking for 'x' gives false alarms when the bus is driven
-- with 'x', which can for example come from a memory model before
-- valid data is available.
if now > 0 ns then -- to avoid startup problems
case istate is
when s_a2b =>
assert B = R_B report "driver clash B port" severity error;
when s_b2a =>
assert A = R_A report "driver clash A port" severity error;
when others => null;
end case;
end if;
wait on A,B;
end loop;
end process;
A <= R_A;
B <= R_B;
end sim;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CLZ36.VHD ***
--*** ***
--*** Function: 36 bit Count Leading Zeros ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END fp_clz36;
ARCHITECTURE zzz of fp_clz36 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position, positionmux : positiontype;
signal zerogroup, firstzero : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mannode : STD_LOGIC_VECTOR (6 DOWNTO 1);
component fp_pos52
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
zerogroup(1) <= mantissa(36) OR mantissa(35) OR mantissa(34) OR mantissa(33) OR mantissa(32) OR mantissa(31);
zerogroup(2) <= mantissa(30) OR mantissa(29) OR mantissa(28) OR mantissa(27) OR mantissa(26) OR mantissa(25);
zerogroup(3) <= mantissa(24) OR mantissa(23) OR mantissa(22) OR mantissa(21) OR mantissa(20) OR mantissa(19);
zerogroup(4) <= mantissa(18) OR mantissa(17) OR mantissa(16) OR mantissa(15) OR mantissa(14) OR mantissa(13);
zerogroup(5) <= mantissa(12) OR mantissa(11) OR mantissa(10) OR mantissa(9) OR mantissa(8) OR mantissa(7);
zerogroup(6) <= mantissa(6) OR mantissa(5) OR mantissa(4) OR mantissa(3) OR mantissa(2) OR mantissa(1);
firstzero(1) <= zerogroup(1);
firstzero(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzero(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzero(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
firstzero(5) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND zerogroup(5);
firstzero(6) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4)) AND NOT(zerogroup(5))
AND zerogroup(6);
pone: fp_pos52
GENERIC MAP (start=>0)
PORT MAP (ingroup=>mantissa(36 DOWNTO 31),position=>position(1)(6 DOWNTO 1));
ptwo: fp_pos52
GENERIC MAP (start=>6)
PORT MAP (ingroup=>mantissa(30 DOWNTO 25),position=>position(2)(6 DOWNTO 1));
pthr: fp_pos52
GENERIC MAP (start=>12)
PORT MAP (ingroup=>mantissa(24 DOWNTO 19),position=>position(3)(6 DOWNTO 1));
pfor: fp_pos52
GENERIC MAP (start=>18)
PORT MAP (ingroup=>mantissa(18 DOWNTO 13),position=>position(4)(6 DOWNTO 1));
pfiv: fp_pos52
GENERIC MAP (start=>24)
PORT MAP (ingroup=>mantissa(12 DOWNTO 7),position=>position(5)(6 DOWNTO 1));
psix: fp_pos52
GENERIC MAP (start=>30)
PORT MAP (ingroup=>mantissa(6 DOWNTO 1),position=>position(6)(6 DOWNTO 1));
gma: FOR k IN 1 TO 6 GENERATE
positionmux(1)(k) <= position(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 6 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (position(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
leading <= positionmux(6)(6 DOWNTO 1);
END zzz;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CLZ36.VHD ***
--*** ***
--*** Function: 36 bit Count Leading Zeros ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END fp_clz36;
ARCHITECTURE zzz of fp_clz36 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position, positionmux : positiontype;
signal zerogroup, firstzero : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mannode : STD_LOGIC_VECTOR (6 DOWNTO 1);
component fp_pos52
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
zerogroup(1) <= mantissa(36) OR mantissa(35) OR mantissa(34) OR mantissa(33) OR mantissa(32) OR mantissa(31);
zerogroup(2) <= mantissa(30) OR mantissa(29) OR mantissa(28) OR mantissa(27) OR mantissa(26) OR mantissa(25);
zerogroup(3) <= mantissa(24) OR mantissa(23) OR mantissa(22) OR mantissa(21) OR mantissa(20) OR mantissa(19);
zerogroup(4) <= mantissa(18) OR mantissa(17) OR mantissa(16) OR mantissa(15) OR mantissa(14) OR mantissa(13);
zerogroup(5) <= mantissa(12) OR mantissa(11) OR mantissa(10) OR mantissa(9) OR mantissa(8) OR mantissa(7);
zerogroup(6) <= mantissa(6) OR mantissa(5) OR mantissa(4) OR mantissa(3) OR mantissa(2) OR mantissa(1);
firstzero(1) <= zerogroup(1);
firstzero(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzero(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzero(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
firstzero(5) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND zerogroup(5);
firstzero(6) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4)) AND NOT(zerogroup(5))
AND zerogroup(6);
pone: fp_pos52
GENERIC MAP (start=>0)
PORT MAP (ingroup=>mantissa(36 DOWNTO 31),position=>position(1)(6 DOWNTO 1));
ptwo: fp_pos52
GENERIC MAP (start=>6)
PORT MAP (ingroup=>mantissa(30 DOWNTO 25),position=>position(2)(6 DOWNTO 1));
pthr: fp_pos52
GENERIC MAP (start=>12)
PORT MAP (ingroup=>mantissa(24 DOWNTO 19),position=>position(3)(6 DOWNTO 1));
pfor: fp_pos52
GENERIC MAP (start=>18)
PORT MAP (ingroup=>mantissa(18 DOWNTO 13),position=>position(4)(6 DOWNTO 1));
pfiv: fp_pos52
GENERIC MAP (start=>24)
PORT MAP (ingroup=>mantissa(12 DOWNTO 7),position=>position(5)(6 DOWNTO 1));
psix: fp_pos52
GENERIC MAP (start=>30)
PORT MAP (ingroup=>mantissa(6 DOWNTO 1),position=>position(6)(6 DOWNTO 1));
gma: FOR k IN 1 TO 6 GENERATE
positionmux(1)(k) <= position(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 6 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (position(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
leading <= positionmux(6)(6 DOWNTO 1);
END zzz;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CLZ36.VHD ***
--*** ***
--*** Function: 36 bit Count Leading Zeros ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END fp_clz36;
ARCHITECTURE zzz of fp_clz36 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position, positionmux : positiontype;
signal zerogroup, firstzero : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mannode : STD_LOGIC_VECTOR (6 DOWNTO 1);
component fp_pos52
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
zerogroup(1) <= mantissa(36) OR mantissa(35) OR mantissa(34) OR mantissa(33) OR mantissa(32) OR mantissa(31);
zerogroup(2) <= mantissa(30) OR mantissa(29) OR mantissa(28) OR mantissa(27) OR mantissa(26) OR mantissa(25);
zerogroup(3) <= mantissa(24) OR mantissa(23) OR mantissa(22) OR mantissa(21) OR mantissa(20) OR mantissa(19);
zerogroup(4) <= mantissa(18) OR mantissa(17) OR mantissa(16) OR mantissa(15) OR mantissa(14) OR mantissa(13);
zerogroup(5) <= mantissa(12) OR mantissa(11) OR mantissa(10) OR mantissa(9) OR mantissa(8) OR mantissa(7);
zerogroup(6) <= mantissa(6) OR mantissa(5) OR mantissa(4) OR mantissa(3) OR mantissa(2) OR mantissa(1);
firstzero(1) <= zerogroup(1);
firstzero(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzero(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzero(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
firstzero(5) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND zerogroup(5);
firstzero(6) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4)) AND NOT(zerogroup(5))
AND zerogroup(6);
pone: fp_pos52
GENERIC MAP (start=>0)
PORT MAP (ingroup=>mantissa(36 DOWNTO 31),position=>position(1)(6 DOWNTO 1));
ptwo: fp_pos52
GENERIC MAP (start=>6)
PORT MAP (ingroup=>mantissa(30 DOWNTO 25),position=>position(2)(6 DOWNTO 1));
pthr: fp_pos52
GENERIC MAP (start=>12)
PORT MAP (ingroup=>mantissa(24 DOWNTO 19),position=>position(3)(6 DOWNTO 1));
pfor: fp_pos52
GENERIC MAP (start=>18)
PORT MAP (ingroup=>mantissa(18 DOWNTO 13),position=>position(4)(6 DOWNTO 1));
pfiv: fp_pos52
GENERIC MAP (start=>24)
PORT MAP (ingroup=>mantissa(12 DOWNTO 7),position=>position(5)(6 DOWNTO 1));
psix: fp_pos52
GENERIC MAP (start=>30)
PORT MAP (ingroup=>mantissa(6 DOWNTO 1),position=>position(6)(6 DOWNTO 1));
gma: FOR k IN 1 TO 6 GENERATE
positionmux(1)(k) <= position(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 6 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (position(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
leading <= positionmux(6)(6 DOWNTO 1);
END zzz;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CLZ36.VHD ***
--*** ***
--*** Function: 36 bit Count Leading Zeros ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END fp_clz36;
ARCHITECTURE zzz of fp_clz36 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position, positionmux : positiontype;
signal zerogroup, firstzero : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mannode : STD_LOGIC_VECTOR (6 DOWNTO 1);
component fp_pos52
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
zerogroup(1) <= mantissa(36) OR mantissa(35) OR mantissa(34) OR mantissa(33) OR mantissa(32) OR mantissa(31);
zerogroup(2) <= mantissa(30) OR mantissa(29) OR mantissa(28) OR mantissa(27) OR mantissa(26) OR mantissa(25);
zerogroup(3) <= mantissa(24) OR mantissa(23) OR mantissa(22) OR mantissa(21) OR mantissa(20) OR mantissa(19);
zerogroup(4) <= mantissa(18) OR mantissa(17) OR mantissa(16) OR mantissa(15) OR mantissa(14) OR mantissa(13);
zerogroup(5) <= mantissa(12) OR mantissa(11) OR mantissa(10) OR mantissa(9) OR mantissa(8) OR mantissa(7);
zerogroup(6) <= mantissa(6) OR mantissa(5) OR mantissa(4) OR mantissa(3) OR mantissa(2) OR mantissa(1);
firstzero(1) <= zerogroup(1);
firstzero(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzero(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzero(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
firstzero(5) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND zerogroup(5);
firstzero(6) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4)) AND NOT(zerogroup(5))
AND zerogroup(6);
pone: fp_pos52
GENERIC MAP (start=>0)
PORT MAP (ingroup=>mantissa(36 DOWNTO 31),position=>position(1)(6 DOWNTO 1));
ptwo: fp_pos52
GENERIC MAP (start=>6)
PORT MAP (ingroup=>mantissa(30 DOWNTO 25),position=>position(2)(6 DOWNTO 1));
pthr: fp_pos52
GENERIC MAP (start=>12)
PORT MAP (ingroup=>mantissa(24 DOWNTO 19),position=>position(3)(6 DOWNTO 1));
pfor: fp_pos52
GENERIC MAP (start=>18)
PORT MAP (ingroup=>mantissa(18 DOWNTO 13),position=>position(4)(6 DOWNTO 1));
pfiv: fp_pos52
GENERIC MAP (start=>24)
PORT MAP (ingroup=>mantissa(12 DOWNTO 7),position=>position(5)(6 DOWNTO 1));
psix: fp_pos52
GENERIC MAP (start=>30)
PORT MAP (ingroup=>mantissa(6 DOWNTO 1),position=>position(6)(6 DOWNTO 1));
gma: FOR k IN 1 TO 6 GENERATE
positionmux(1)(k) <= position(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 6 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (position(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
leading <= positionmux(6)(6 DOWNTO 1);
END zzz;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CLZ36.VHD ***
--*** ***
--*** Function: 36 bit Count Leading Zeros ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END fp_clz36;
ARCHITECTURE zzz of fp_clz36 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position, positionmux : positiontype;
signal zerogroup, firstzero : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mannode : STD_LOGIC_VECTOR (6 DOWNTO 1);
component fp_pos52
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
zerogroup(1) <= mantissa(36) OR mantissa(35) OR mantissa(34) OR mantissa(33) OR mantissa(32) OR mantissa(31);
zerogroup(2) <= mantissa(30) OR mantissa(29) OR mantissa(28) OR mantissa(27) OR mantissa(26) OR mantissa(25);
zerogroup(3) <= mantissa(24) OR mantissa(23) OR mantissa(22) OR mantissa(21) OR mantissa(20) OR mantissa(19);
zerogroup(4) <= mantissa(18) OR mantissa(17) OR mantissa(16) OR mantissa(15) OR mantissa(14) OR mantissa(13);
zerogroup(5) <= mantissa(12) OR mantissa(11) OR mantissa(10) OR mantissa(9) OR mantissa(8) OR mantissa(7);
zerogroup(6) <= mantissa(6) OR mantissa(5) OR mantissa(4) OR mantissa(3) OR mantissa(2) OR mantissa(1);
firstzero(1) <= zerogroup(1);
firstzero(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzero(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzero(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
firstzero(5) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND zerogroup(5);
firstzero(6) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4)) AND NOT(zerogroup(5))
AND zerogroup(6);
pone: fp_pos52
GENERIC MAP (start=>0)
PORT MAP (ingroup=>mantissa(36 DOWNTO 31),position=>position(1)(6 DOWNTO 1));
ptwo: fp_pos52
GENERIC MAP (start=>6)
PORT MAP (ingroup=>mantissa(30 DOWNTO 25),position=>position(2)(6 DOWNTO 1));
pthr: fp_pos52
GENERIC MAP (start=>12)
PORT MAP (ingroup=>mantissa(24 DOWNTO 19),position=>position(3)(6 DOWNTO 1));
pfor: fp_pos52
GENERIC MAP (start=>18)
PORT MAP (ingroup=>mantissa(18 DOWNTO 13),position=>position(4)(6 DOWNTO 1));
pfiv: fp_pos52
GENERIC MAP (start=>24)
PORT MAP (ingroup=>mantissa(12 DOWNTO 7),position=>position(5)(6 DOWNTO 1));
psix: fp_pos52
GENERIC MAP (start=>30)
PORT MAP (ingroup=>mantissa(6 DOWNTO 1),position=>position(6)(6 DOWNTO 1));
gma: FOR k IN 1 TO 6 GENERATE
positionmux(1)(k) <= position(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 6 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (position(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
leading <= positionmux(6)(6 DOWNTO 1);
END zzz;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CLZ36.VHD ***
--*** ***
--*** Function: 36 bit Count Leading Zeros ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END fp_clz36;
ARCHITECTURE zzz of fp_clz36 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position, positionmux : positiontype;
signal zerogroup, firstzero : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mannode : STD_LOGIC_VECTOR (6 DOWNTO 1);
component fp_pos52
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
zerogroup(1) <= mantissa(36) OR mantissa(35) OR mantissa(34) OR mantissa(33) OR mantissa(32) OR mantissa(31);
zerogroup(2) <= mantissa(30) OR mantissa(29) OR mantissa(28) OR mantissa(27) OR mantissa(26) OR mantissa(25);
zerogroup(3) <= mantissa(24) OR mantissa(23) OR mantissa(22) OR mantissa(21) OR mantissa(20) OR mantissa(19);
zerogroup(4) <= mantissa(18) OR mantissa(17) OR mantissa(16) OR mantissa(15) OR mantissa(14) OR mantissa(13);
zerogroup(5) <= mantissa(12) OR mantissa(11) OR mantissa(10) OR mantissa(9) OR mantissa(8) OR mantissa(7);
zerogroup(6) <= mantissa(6) OR mantissa(5) OR mantissa(4) OR mantissa(3) OR mantissa(2) OR mantissa(1);
firstzero(1) <= zerogroup(1);
firstzero(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzero(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzero(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
firstzero(5) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND zerogroup(5);
firstzero(6) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4)) AND NOT(zerogroup(5))
AND zerogroup(6);
pone: fp_pos52
GENERIC MAP (start=>0)
PORT MAP (ingroup=>mantissa(36 DOWNTO 31),position=>position(1)(6 DOWNTO 1));
ptwo: fp_pos52
GENERIC MAP (start=>6)
PORT MAP (ingroup=>mantissa(30 DOWNTO 25),position=>position(2)(6 DOWNTO 1));
pthr: fp_pos52
GENERIC MAP (start=>12)
PORT MAP (ingroup=>mantissa(24 DOWNTO 19),position=>position(3)(6 DOWNTO 1));
pfor: fp_pos52
GENERIC MAP (start=>18)
PORT MAP (ingroup=>mantissa(18 DOWNTO 13),position=>position(4)(6 DOWNTO 1));
pfiv: fp_pos52
GENERIC MAP (start=>24)
PORT MAP (ingroup=>mantissa(12 DOWNTO 7),position=>position(5)(6 DOWNTO 1));
psix: fp_pos52
GENERIC MAP (start=>30)
PORT MAP (ingroup=>mantissa(6 DOWNTO 1),position=>position(6)(6 DOWNTO 1));
gma: FOR k IN 1 TO 6 GENERATE
positionmux(1)(k) <= position(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 6 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (position(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
leading <= positionmux(6)(6 DOWNTO 1);
END zzz;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CLZ36.VHD ***
--*** ***
--*** Function: 36 bit Count Leading Zeros ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END fp_clz36;
ARCHITECTURE zzz of fp_clz36 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position, positionmux : positiontype;
signal zerogroup, firstzero : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mannode : STD_LOGIC_VECTOR (6 DOWNTO 1);
component fp_pos52
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
zerogroup(1) <= mantissa(36) OR mantissa(35) OR mantissa(34) OR mantissa(33) OR mantissa(32) OR mantissa(31);
zerogroup(2) <= mantissa(30) OR mantissa(29) OR mantissa(28) OR mantissa(27) OR mantissa(26) OR mantissa(25);
zerogroup(3) <= mantissa(24) OR mantissa(23) OR mantissa(22) OR mantissa(21) OR mantissa(20) OR mantissa(19);
zerogroup(4) <= mantissa(18) OR mantissa(17) OR mantissa(16) OR mantissa(15) OR mantissa(14) OR mantissa(13);
zerogroup(5) <= mantissa(12) OR mantissa(11) OR mantissa(10) OR mantissa(9) OR mantissa(8) OR mantissa(7);
zerogroup(6) <= mantissa(6) OR mantissa(5) OR mantissa(4) OR mantissa(3) OR mantissa(2) OR mantissa(1);
firstzero(1) <= zerogroup(1);
firstzero(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzero(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzero(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
firstzero(5) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND zerogroup(5);
firstzero(6) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4)) AND NOT(zerogroup(5))
AND zerogroup(6);
pone: fp_pos52
GENERIC MAP (start=>0)
PORT MAP (ingroup=>mantissa(36 DOWNTO 31),position=>position(1)(6 DOWNTO 1));
ptwo: fp_pos52
GENERIC MAP (start=>6)
PORT MAP (ingroup=>mantissa(30 DOWNTO 25),position=>position(2)(6 DOWNTO 1));
pthr: fp_pos52
GENERIC MAP (start=>12)
PORT MAP (ingroup=>mantissa(24 DOWNTO 19),position=>position(3)(6 DOWNTO 1));
pfor: fp_pos52
GENERIC MAP (start=>18)
PORT MAP (ingroup=>mantissa(18 DOWNTO 13),position=>position(4)(6 DOWNTO 1));
pfiv: fp_pos52
GENERIC MAP (start=>24)
PORT MAP (ingroup=>mantissa(12 DOWNTO 7),position=>position(5)(6 DOWNTO 1));
psix: fp_pos52
GENERIC MAP (start=>30)
PORT MAP (ingroup=>mantissa(6 DOWNTO 1),position=>position(6)(6 DOWNTO 1));
gma: FOR k IN 1 TO 6 GENERATE
positionmux(1)(k) <= position(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 6 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (position(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
leading <= positionmux(6)(6 DOWNTO 1);
END zzz;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CLZ36.VHD ***
--*** ***
--*** Function: 36 bit Count Leading Zeros ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END fp_clz36;
ARCHITECTURE zzz of fp_clz36 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position, positionmux : positiontype;
signal zerogroup, firstzero : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mannode : STD_LOGIC_VECTOR (6 DOWNTO 1);
component fp_pos52
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
zerogroup(1) <= mantissa(36) OR mantissa(35) OR mantissa(34) OR mantissa(33) OR mantissa(32) OR mantissa(31);
zerogroup(2) <= mantissa(30) OR mantissa(29) OR mantissa(28) OR mantissa(27) OR mantissa(26) OR mantissa(25);
zerogroup(3) <= mantissa(24) OR mantissa(23) OR mantissa(22) OR mantissa(21) OR mantissa(20) OR mantissa(19);
zerogroup(4) <= mantissa(18) OR mantissa(17) OR mantissa(16) OR mantissa(15) OR mantissa(14) OR mantissa(13);
zerogroup(5) <= mantissa(12) OR mantissa(11) OR mantissa(10) OR mantissa(9) OR mantissa(8) OR mantissa(7);
zerogroup(6) <= mantissa(6) OR mantissa(5) OR mantissa(4) OR mantissa(3) OR mantissa(2) OR mantissa(1);
firstzero(1) <= zerogroup(1);
firstzero(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzero(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzero(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
firstzero(5) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND zerogroup(5);
firstzero(6) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4)) AND NOT(zerogroup(5))
AND zerogroup(6);
pone: fp_pos52
GENERIC MAP (start=>0)
PORT MAP (ingroup=>mantissa(36 DOWNTO 31),position=>position(1)(6 DOWNTO 1));
ptwo: fp_pos52
GENERIC MAP (start=>6)
PORT MAP (ingroup=>mantissa(30 DOWNTO 25),position=>position(2)(6 DOWNTO 1));
pthr: fp_pos52
GENERIC MAP (start=>12)
PORT MAP (ingroup=>mantissa(24 DOWNTO 19),position=>position(3)(6 DOWNTO 1));
pfor: fp_pos52
GENERIC MAP (start=>18)
PORT MAP (ingroup=>mantissa(18 DOWNTO 13),position=>position(4)(6 DOWNTO 1));
pfiv: fp_pos52
GENERIC MAP (start=>24)
PORT MAP (ingroup=>mantissa(12 DOWNTO 7),position=>position(5)(6 DOWNTO 1));
psix: fp_pos52
GENERIC MAP (start=>30)
PORT MAP (ingroup=>mantissa(6 DOWNTO 1),position=>position(6)(6 DOWNTO 1));
gma: FOR k IN 1 TO 6 GENERATE
positionmux(1)(k) <= position(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 6 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (position(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
leading <= positionmux(6)(6 DOWNTO 1);
END zzz;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CLZ36.VHD ***
--*** ***
--*** Function: 36 bit Count Leading Zeros ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END fp_clz36;
ARCHITECTURE zzz of fp_clz36 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position, positionmux : positiontype;
signal zerogroup, firstzero : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mannode : STD_LOGIC_VECTOR (6 DOWNTO 1);
component fp_pos52
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
zerogroup(1) <= mantissa(36) OR mantissa(35) OR mantissa(34) OR mantissa(33) OR mantissa(32) OR mantissa(31);
zerogroup(2) <= mantissa(30) OR mantissa(29) OR mantissa(28) OR mantissa(27) OR mantissa(26) OR mantissa(25);
zerogroup(3) <= mantissa(24) OR mantissa(23) OR mantissa(22) OR mantissa(21) OR mantissa(20) OR mantissa(19);
zerogroup(4) <= mantissa(18) OR mantissa(17) OR mantissa(16) OR mantissa(15) OR mantissa(14) OR mantissa(13);
zerogroup(5) <= mantissa(12) OR mantissa(11) OR mantissa(10) OR mantissa(9) OR mantissa(8) OR mantissa(7);
zerogroup(6) <= mantissa(6) OR mantissa(5) OR mantissa(4) OR mantissa(3) OR mantissa(2) OR mantissa(1);
firstzero(1) <= zerogroup(1);
firstzero(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzero(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzero(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
firstzero(5) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND zerogroup(5);
firstzero(6) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4)) AND NOT(zerogroup(5))
AND zerogroup(6);
pone: fp_pos52
GENERIC MAP (start=>0)
PORT MAP (ingroup=>mantissa(36 DOWNTO 31),position=>position(1)(6 DOWNTO 1));
ptwo: fp_pos52
GENERIC MAP (start=>6)
PORT MAP (ingroup=>mantissa(30 DOWNTO 25),position=>position(2)(6 DOWNTO 1));
pthr: fp_pos52
GENERIC MAP (start=>12)
PORT MAP (ingroup=>mantissa(24 DOWNTO 19),position=>position(3)(6 DOWNTO 1));
pfor: fp_pos52
GENERIC MAP (start=>18)
PORT MAP (ingroup=>mantissa(18 DOWNTO 13),position=>position(4)(6 DOWNTO 1));
pfiv: fp_pos52
GENERIC MAP (start=>24)
PORT MAP (ingroup=>mantissa(12 DOWNTO 7),position=>position(5)(6 DOWNTO 1));
psix: fp_pos52
GENERIC MAP (start=>30)
PORT MAP (ingroup=>mantissa(6 DOWNTO 1),position=>position(6)(6 DOWNTO 1));
gma: FOR k IN 1 TO 6 GENERATE
positionmux(1)(k) <= position(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 6 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (position(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
leading <= positionmux(6)(6 DOWNTO 1);
END zzz;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CLZ36.VHD ***
--*** ***
--*** Function: 36 bit Count Leading Zeros ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END fp_clz36;
ARCHITECTURE zzz of fp_clz36 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position, positionmux : positiontype;
signal zerogroup, firstzero : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mannode : STD_LOGIC_VECTOR (6 DOWNTO 1);
component fp_pos52
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
zerogroup(1) <= mantissa(36) OR mantissa(35) OR mantissa(34) OR mantissa(33) OR mantissa(32) OR mantissa(31);
zerogroup(2) <= mantissa(30) OR mantissa(29) OR mantissa(28) OR mantissa(27) OR mantissa(26) OR mantissa(25);
zerogroup(3) <= mantissa(24) OR mantissa(23) OR mantissa(22) OR mantissa(21) OR mantissa(20) OR mantissa(19);
zerogroup(4) <= mantissa(18) OR mantissa(17) OR mantissa(16) OR mantissa(15) OR mantissa(14) OR mantissa(13);
zerogroup(5) <= mantissa(12) OR mantissa(11) OR mantissa(10) OR mantissa(9) OR mantissa(8) OR mantissa(7);
zerogroup(6) <= mantissa(6) OR mantissa(5) OR mantissa(4) OR mantissa(3) OR mantissa(2) OR mantissa(1);
firstzero(1) <= zerogroup(1);
firstzero(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzero(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzero(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
firstzero(5) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND zerogroup(5);
firstzero(6) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4)) AND NOT(zerogroup(5))
AND zerogroup(6);
pone: fp_pos52
GENERIC MAP (start=>0)
PORT MAP (ingroup=>mantissa(36 DOWNTO 31),position=>position(1)(6 DOWNTO 1));
ptwo: fp_pos52
GENERIC MAP (start=>6)
PORT MAP (ingroup=>mantissa(30 DOWNTO 25),position=>position(2)(6 DOWNTO 1));
pthr: fp_pos52
GENERIC MAP (start=>12)
PORT MAP (ingroup=>mantissa(24 DOWNTO 19),position=>position(3)(6 DOWNTO 1));
pfor: fp_pos52
GENERIC MAP (start=>18)
PORT MAP (ingroup=>mantissa(18 DOWNTO 13),position=>position(4)(6 DOWNTO 1));
pfiv: fp_pos52
GENERIC MAP (start=>24)
PORT MAP (ingroup=>mantissa(12 DOWNTO 7),position=>position(5)(6 DOWNTO 1));
psix: fp_pos52
GENERIC MAP (start=>30)
PORT MAP (ingroup=>mantissa(6 DOWNTO 1),position=>position(6)(6 DOWNTO 1));
gma: FOR k IN 1 TO 6 GENERATE
positionmux(1)(k) <= position(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 6 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (position(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
leading <= positionmux(6)(6 DOWNTO 1);
END zzz;
|
----------------------------------------------------------------------------------
-- Company: TU Vienna
-- Engineer: Georg Blemenschitz
--
-- Create Date: 19:43:36 01/31/2010
-- Design Name: SPI
-- Module Name: SPIShifter - RTL
-- Description: Shifter for SPI
--
-- Revision:
-- Revision 0.01 - File Created
--
-- Associated Testbench:
-- tb_SPIShifter.vhd
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SPIShifter is
Generic (
DataWidth : integer range 2 to 64 := 8);
Port (
Reset_n : in STD_LOGIC;
Clk : in STD_LOGIC;
-- SPI config param
LSBFE_i : in STD_LOGIC;
-- SPI input/output
MOSI_o : out STD_LOGIC;
MISO_i : in STD_LOGIC;
-- control signals
LdShifter_i : in STD_LOGIC;
EnShift_i : in STD_LOGIC;
EnSample_i : in STD_LOGIC;
-- data signals
Data_i : in STD_LOGIC_VECTOR(DataWidth-1 downto 0);
Data_o : out STD_LOGIC_VECTOR(DataWidth-1 downto 0));
end SPIShifter;
|
------------------------------------------------------------------------------
---- ----
---- gmzpu zwc component testbench ----
---- ----
---- http://github.com/sonologic/gmzpu ----
---- ----
---- Description: ----
---- This is the testbench for the gmZPU core ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- - "Koen Martens" <gmc sonologic.nl> ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2014 Koen Martens ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zwishbone_TB ----
---- File name: gmzpu_tb.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: n/a ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Modelsim ----
---- Simulation tools: Modelsim ----
---- Text editor: vim ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library gmzpu;
use gmzpu.zwishbone.all;
entity zwishbone_controller_decode_TB is
end entity zwishbone_controller_decode_TB;
architecture Behave of zwishbone_controller_decode_TB is
constant CLK_FREQ : positive:=50; -- 50 MHz clock
constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period
constant ADR_WIDTH : natural:=18;
constant IO_BIT : natural:=ADR_WIDTH-1;
constant ZWC_BIT : natural:=ADR_WIDTH-2;
constant IO_BIT_WIDTH : natural:=1;
constant ZWC_BIT_WIDTH : natural:=1;
constant BUSBIT_WIDTH : natural:=1;
constant CS_WIDTH : natural:=4;
constant DATA_WIDTH : natural:=32;
type sample is record
-- inputs
rst_i : std_logic;
adr_i : unsigned(ADR_WIDTH-1 downto 0);
re_i : std_logic;
we_i : std_logic;
dat_i : unsigned(DATA_WIDTH-1 downto 0);
wb_dat_i : unsigned(DATA_WIDTH-1 downto 0);
wb_ack_i : std_logic;
wb_stall_i : std_logic;
wb_err_i : std_logic;
wb_rty_i : std_logic;
-- outputs
wb_cyc_o : std_logic;
wb_stb_o : std_logic_vector((2**CS_WIDTH)-1 downto 0);
wb_we_o : std_logic;
wb_lock_o : std_logic;
busy_o : std_logic;
ready_o : std_logic;
dat_o : unsigned(DATA_WIDTH-1 downto 0);
irq_o : std_logic;
wb_dat_o : unsigned(DATA_WIDTH-1 downto 0);
wb_adr_o : unsigned(ADR_WIDTH-IO_BIT_WIDTH-ZWC_BIT_WIDTH-BUSBIT_WIDTH-CS_WIDTH-1 downto 0);
end record;
type sample_array is array(natural range <>) of sample;
constant test_data : sample_array :=
(
-- rst adr_i re we dat_i wb_dat_i ack stl err rty | cyc stb we lck bus rdy dat_o irq wb_dat_o wb_adr_o
('1',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
-- write config
('0',"000000000000000000",'0','1',X"12345678",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
-- read config
('0',"000000000000000000",'1','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','1','0',X"00000000",'0',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','1',X"00000001",'0',X"00000000","00000000000"),
-- bus write, stb 1 (device 0)
('0',"111000000000000000",'0','1',X"87654321",X"00000000",'0','0','0','0', '1',X"0001",'1','0','1','0',X"00000000",'0',X"87654321","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'1','0','0','0', '1',X"0000",'0','0','1','0',X"00000000",'0',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
-- bus read, stb 2 (device 1) (0x8803)
('0',"111000100000000011",'1','0',X"00000000",X"00000000",'0','0','0','0', '1',X"0002",'0','0','1','0',X"00000000",'0',X"00000000","00000000011"),
('0',"000000000000000000",'0','0',X"00000000",X"9abcdef0",'1','0','0','0', '1',X"0000",'0','0','0','1',X"9abcdef0",'0',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
-- write timeout compare reg (set to 2)
('0',"000000000000001000",'0','1',X"00000002",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
-- bus read, timeout (0x8803)
('0',"111000100000000011",'1','0',X"00000000",X"00000000",'0','0','0','0', '1',X"0002",'0','0','1','0',X"00000000",'0',X"00000000","00000000011"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '1',X"0000",'0','0','1','0',X"00000000",'0',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '1',X"0000",'0','0','1','0',X"00000000",'0',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '1',X"0000",'0','0','1','0',X"00000000",'0',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '1',X"0000",'0','0','1','0',X"00000000",'1',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'1',X"00000000","00000000000"),
-- cancel timeout status (write 0 to status reg)
('0',"000000000000000100",'0','1',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'1',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000"),
-- terminate
('0',"000000000000000000",'0','0',X"00000000",X"00000000",'0','0','0','0', '0',X"0000",'0','0','0','0',X"00000000",'0',X"00000000","00000000000")
);
signal clk : std_logic;
-- inputs
signal rst_i : std_logic;
signal adr_i : unsigned(ADR_WIDTH-1 downto 0);
signal re_i : std_logic;
signal we_i : std_logic;
signal dat_i : unsigned(DATA_WIDTH-1 downto 0);
signal wb_dat_i : unsigned(DATA_WIDTH-1 downto 0);
signal wb_ack_i : std_logic;
signal wb_stall_i : std_logic;
signal wb_err_i : std_logic;
signal wb_rty_i : std_logic;
signal wb_tgd_i : unsigned(DATA_WIDTH -1 downto 0);
-- outputs
signal wb_cyc_o : std_logic;
signal wb_stb_o : std_logic_vector((2**CS_WIDTH)-1 downto 0);
signal wb_we_o : std_logic;
signal wb_lock_o : std_logic;
signal busy_o : std_logic;
signal ready_o : std_logic;
signal dat_o : unsigned(DATA_WIDTH-1 downto 0);
signal irq_o : std_logic;
signal wb_dat_o : unsigned(DATA_WIDTH-1 downto 0);
signal wb_tgc_o : unsigned(DATA_WIDTH-1 downto 0);
signal wb_adr_o : unsigned(ADR_WIDTH-IO_BIT_WIDTH-ZWC_BIT_WIDTH-BUSBIT_WIDTH-CS_WIDTH-1 downto 0);
signal wb_tga_o : unsigned(ADR_WIDTH-IO_BIT_WIDTH-ZWC_BIT_WIDTH-BUSBIT_WIDTH-CS_WIDTH-1 downto 0);
signal wb_sel_o : std_logic_vector(DATA_WIDTH-1 downto 0);
-- decode
signal zw_we_i : std_logic;
signal zw_re_i : std_logic;
signal zw_adr_i : unsigned(ADR_WIDTH-3 downto 0);
begin
dut : zwishbone_controller
generic map(ADR_WIDTH => ADR_WIDTH-IO_BIT_WIDTH-ZWC_BIT_WIDTH, DATA_WIDTH => DATA_WIDTH, BUSBIT_WIDTH => BUSBIT_WIDTH, CS_WIDTH => CS_WIDTH)
port map(clk_i => clk, rst_i => rst_i,
busy_o => busy_o, ready_o => ready_o, adr_i => zw_adr_i, re_i => re_i, we_i => we_i,
dat_i => dat_i, dat_o => dat_o, irq_o => irq_o,
wb_dat_i => wb_dat_i, wb_dat_o => wb_dat_o, wb_tgd_i => wb_tgd_i,
wb_ack_i => wb_ack_i, wb_adr_o => wb_adr_o, wb_cyc_o => wb_cyc_o,
wb_stall_i => wb_stall_i, wb_err_i => wb_err_i, wb_lock_o => wb_lock_o,
wb_rty_i => wb_rty_i, wb_sel_o => wb_sel_o, wb_stb_o => wb_stb_o,
wb_tga_o => wb_tga_o, wb_tgc_o => wb_tgc_o, wb_we_o => wb_we_o);
wb_dat_o <= (others => 'L');
wb_adr_o <= (others => 'L');
dat_o <= (others => 'L');
zw_we_i <= we_i and adr_i(IO_BIT) and adr_i(ZWC_BIT);
zw_re_i <= re_i and adr_i(IO_BIT) and adr_i(ZWC_BIT);
zw_adr_i <= adr_i(ADR_WIDTH-3 downto 0);
process
variable cycle_count : integer:=0;
begin
for i in test_data'range loop
rst_i <= test_data(i).rst_i;
adr_i <= test_data(i).adr_i;
re_i <= test_data(i).re_i;
we_i <= test_data(i).we_i;
dat_i <= test_data(i).dat_i;
wb_dat_i <= test_data(i).wb_dat_i;
wb_tgd_i <= (others => 'Z'); --test_data(i).wb_tgd_i;
wb_ack_i <= test_data(i).wb_ack_i;
wb_stall_i <= test_data(i).wb_stall_i;
wb_err_i <= test_data(i).wb_err_i;
wb_rty_i <= test_data(i).wb_rty_i;
clk <= '1';
wait for CLK_S_PER;
clk <= '0';
wait for CLK_S_PER;
assert (dat_o = test_data(i).dat_o) report "dat_o output mismatch" severity error;
assert (busy_o = test_data(i).busy_o) report "busy_o output mismatch" severity error;
assert (ready_o = test_data(i).ready_o) report "ready_o output mismatch" severity error;
assert (irq_o = test_data(i).irq_o) report "irq_o output mismatch" severity error;
assert (wb_cyc_o = test_data(i).wb_cyc_o) report "wb_cyc_o output mismatch" severity error;
assert (wb_stb_o = test_data(i).wb_stb_o) report "wb_stb_o output mismatch" severity error;
assert (wb_we_o = test_data(i).wb_we_o) report "wb_we_o output mismatch" severity error;
assert (wb_adr_o = test_data(i).wb_adr_o) report "wb_adr_o output mismatch" severity error;
assert (wb_dat_o = test_data(i).wb_dat_o) report "wb_dat_o output mismatch" severity error;
--assert (irq_o = test_data(i).irq_o) report "irq_o output mismatch" severity error;
--assert (wb_ack_o = test_data(i).wb_ack_o) report "ack_o output mismatch" severity error;
-- assert (icr_o = test_data(i).icr_o) report "icr_o output mismatch" severity failure;
end loop;
clk <= '0';
wait;
end process;
end architecture Behave;
|
entity tb_uassoc03 is
end tb_uassoc03;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_uassoc03 is
signal i1 : std_logic_vector(3 downto 0);
signal i2 : std_logic_vector(7 downto 0);
signal o : std_logic_vector(3 downto 0);
begin
dut: entity work.uassoc03
port map (i1, i2, o);
process
begin
i1 <= "1100";
i2 <= b"1010_1010";
wait for 1 ns;
assert o = "0110" severity failure;
wait;
end process;
end behav;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 8e-07,
W => Wdiff_0,
Wdiff_0init => 2.55e-06,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 8e-07,
W => Wdiff_0,
Wdiff_0init => 2.55e-06,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.95e-06,
W => W_0,
W_0init => 3.95e-06
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 2.25e-06,
W => Wcm_2,
Wcm_2init => 7e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 2.25e-06,
W => Wcmout_2,
Wcmout_2init => 7.545e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 2.25e-06,
W => Wcm_2,
Wcm_2init => 7e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 2.25e-06,
W => Wcmout_2,
Wcmout_2init => 7.545e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 6.85e-06,
W => Wcm_1,
Wcm_1init => 1.035e-05,
scope => private
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 6.85e-06,
W => Wcmcout_1,
Wcmcout_1init => 5.77e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 2.95e-06,
W => (pfak)*(WBias),
WBiasinit => 9.35e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 2.95e-06,
W => (pfak)*(WBias),
WBiasinit => 9.35e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 2.95e-06,
W => WBias,
WBiasinit => 9.35e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.95e-06,
W => WBias,
WBiasinit => 9.35e-06
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.95e-06,
W => WBias,
WBiasinit => 9.35e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.95e-06,
W => WBias,
WBiasinit => 9.35e-06
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net7,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net7,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net7,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
|
PACKAGE fifo_pkg is
end package;
PACKAGE fifo_pkg is
end package;
|
--------------------------------------------------------------------------------
-- d_reg32 test bench
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity d_reg2_TB is
end d_reg2_TB;
architecture behavior of d_reg2_TB is
-- Component Declaration for the Unit Under Test (UUT)
component d_reg32
port(
clk : IN std_logic;
en : IN std_logic;
d : IN std_logic_vector(31 downto 0);
q : OUT std_logic_vector(31 downto 0)
);
end component;
-- Inputs
signal clk : std_logic := '0';
signal en : std_logic := '0';
signal d : std_logic_vector(31 downto 0) := x"aaaa5555";
-- Outputs
signal q : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut: d_reg32 PORT MAP (
clk => clk,
en => en,
d => d,
q => q
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 107 ns;
en <= '1';
wait;
end process;
end;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 15:20:13 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top led_controller_design_auto_pc_0 -prefix
-- led_controller_design_auto_pc_0_ led_controller_design_auto_pc_0_stub.vhdl
-- Design : led_controller_design_auto_pc_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity led_controller_design_auto_pc_0 is
Port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end led_controller_design_auto_pc_0;
architecture stub of led_controller_design_auto_pc_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awaddr[31:0],m_axi_awprot[2:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wvalid,m_axi_wready,m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_araddr[31:0],m_axi_arprot[2:0],m_axi_arvalid,m_axi_arready,m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rvalid,m_axi_rready";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axi_protocol_converter_v2_1_14_axi_protocol_converter,Vivado 2017.3";
begin
end;
|
entity case3 is
end;
architecture behav of case3 is
subtype bv4 is bit_vector (1 to 4);
type vec2 is array (natural range <>) of bv4;
constant vects : vec2 := (x"0", x"4", x"9", x"3", x"a");
begin
process
variable i : natural := 0;
begin
for i in vects'range loop
case bv4'(vects (i)) is
when "0100" =>
report "value is 4";
wait for 4 ns;
when "0011" =>
report "value is 3";
wait for 3 ns;
when others =>
report "unknown value";
wait for 1 ns;
end case;
end loop;
report "SUCCESS";
wait;
end process;
end behav;
|
entity case3 is
end;
architecture behav of case3 is
subtype bv4 is bit_vector (1 to 4);
type vec2 is array (natural range <>) of bv4;
constant vects : vec2 := (x"0", x"4", x"9", x"3", x"a");
begin
process
variable i : natural := 0;
begin
for i in vects'range loop
case bv4'(vects (i)) is
when "0100" =>
report "value is 4";
wait for 4 ns;
when "0011" =>
report "value is 3";
wait for 3 ns;
when others =>
report "unknown value";
wait for 1 ns;
end case;
end loop;
report "SUCCESS";
wait;
end process;
end behav;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03:48:33 01/13/2014
-- Design Name:
-- Module Name: C:/Users/Ruy/Desktop/LCSE_lab/alu/tb_alu.vhd
-- Project Name: alu
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: alu
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.PIC_pkg.all;
ENTITY tb_alu IS
END tb_alu;
ARCHITECTURE behavior OF tb_alu IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT alu
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
u_instruction : IN alu_op;
FlagZ : OUT std_logic;
FlagC : OUT std_logic;
FlagN : OUT std_logic;
FlagE : OUT std_logic;
Index : OUT std_logic_vector(7 downto 0);
Databus : INOUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Reset : std_logic := '0';
signal u_instruction : alu_op := nop;
--BiDirs
signal Databus : std_logic_vector(7 downto 0) := X"00";
--Outputs
signal FlagZ : std_logic;
signal FlagC : std_logic;
signal FlagN : std_logic;
signal FlagE : std_logic;
signal Index : std_logic_vector(7 downto 0);
-- Clock period definitions
constant Clk_period : time := 25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: alu PORT MAP (
Clk => Clk,
Reset => Reset,
u_instruction => u_instruction,
FlagZ => FlagZ,
FlagC => FlagC,
FlagN => FlagN,
FlagE => FlagE,
Index => Index,
Databus => Databus
);
Clk <= not Clk after Clk_period;
-- Stimulus process
stim_proc: process
begin
wait for 100 ns; -- Quitar reset y cargar A desde el bus de datos
Reset <= '1' after 1 ns;
wait for 25 ns;
Databus <= X"05" after 1 ns; -- 5
u_instruction <= op_lda after 1 ns;
wait for 50 ns; -- Cargar B desde el bus de datos
Databus <= X"FB" after 1 ns; -- -5
u_instruction <= op_ldb after 1 ns;
wait for 50 ns; -- Cargar ACC desde el bus de datos
Databus <= X"55" after 1 ns;
u_instruction <= op_ldacc after 1 ns;
wait for 50 ns; -- Cargar INDEX desde el bus de datos
Databus <= X"AA" after 1 ns;
u_instruction <= op_ldid after 1 ns;
wait for 50 ns; -- Suma
Databus <= X"00" after 1 ns;
u_instruction <= op_add after 1 ns;
wait for 50 ns; -- Resta
Databus <= X"00" after 1 ns;
u_instruction <= op_sub after 1 ns;
wait for 50 ns; -- Mueve ACC a INDEX
Databus <= X"00" after 1 ns;
u_instruction <= op_mvacc2id after 1 ns;
wait for 50 ns; -- Mueve ACC a A
Databus <= X"00" after 1 ns;
u_instruction <= op_mvacc2a after 1 ns;
wait for 50 ns; -- Mueve ACC a B
Databus <= X"00" after 1 ns;
u_instruction <= op_mvacc2b after 1 ns;
wait for 50 ns; -- XOR
Databus <= X"00" after 1 ns;
u_instruction <= op_xor after 1 ns;
wait for 50 ns; -- Compare <
Databus <= X"00" after 1 ns;
u_instruction <= op_cmpl after 1 ns;
wait for 50 ns; -- Compare =
Databus <= X"00" after 1 ns;
u_instruction <= op_cmpe after 1 ns;
wait for 50 ns; -- Carga en A
Databus <= X"FF" after 1 ns; -- FF
u_instruction <= op_lda after 1 ns;
wait for 50 ns; -- Carga en B
Databus <= X"80" after 1 ns; -- 80
u_instruction <= op_ldb after 1 ns;
wait for 50 ns; -- OR
Databus <= X"00" after 1 ns;
u_instruction <= op_or after 1 ns;
wait for 50 ns; -- AND
Databus <= X"00" after 1 ns;
u_instruction <= op_and after 1 ns;
wait for 50 ns; -- SUM
Databus <= X"00" after 1 ns;
u_instruction <= op_add after 1 ns;
wait for 50 ns; -- Compare >
Databus <= X"00" after 1 ns;
u_instruction <= op_cmpg after 1 ns;
wait for 50 ns; -- BIN 2 ASCII (con error)
Databus <= X"00" after 1 ns;
u_instruction <= op_bin2ascii after 1 ns;
wait for 50 ns; -- Carga en A
Databus <= X"08" after 1 ns;
u_instruction <= op_lda after 1 ns;
wait for 50 ns; -- BIN 2 ASCII (sin error)
Databus <= X"00" after 1 ns;
u_instruction <= op_bin2ascii after 1 ns;
wait for 50 ns; -- Carga ACC en A
Databus <= X"00" after 1 ns;
u_instruction <= op_mvacc2a after 1 ns;
wait for 50 ns; -- ASCII 2 BIN (sin error)
Databus <= X"00" after 1 ns;
u_instruction <= op_ascii2bin after 1 ns;
wait for 50 ns; -- Carga ACC en A
Databus <= X"00" after 1 ns;
u_instruction <= op_mvacc2a after 1 ns;
wait for 50 ns; -- Carga ACC en B
Databus <= X"00" after 1 ns;
u_instruction <= op_mvacc2b after 1 ns;
wait for 50 ns; -- Suma con acarreo de nibble
Databus <= X"00" after 1 ns;
u_instruction <= op_add after 1 ns;
wait for 50 ns; -- Saca ACC por el bus de datos
Databus <= (others => 'Z');
u_instruction <= op_oeacc after 1 ns;
wait;
end process;
END;
|
library ieee;
use ieee.std_logic_1164.all;
entity flopr is
port (
d: in std_logic_vector(31 downto 0);
rst, clk: in std_logic;
q: out std_logic_vector(31 downto 0));
end entity;
architecture behavior of flopr is
begin
process (clk, rst) begin
if (rst = '1') then
q <= (others => '0');
elsif (clk'event and clk = '1') then
q <= d;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity flopr is
port (
d: in std_logic_vector(31 downto 0);
rst, clk: in std_logic;
q: out std_logic_vector(31 downto 0));
end entity;
architecture behavior of flopr is
begin
process (clk, rst) begin
if (rst = '1') then
q <= (others => '0');
elsif (clk'event and clk = '1') then
q <= d;
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity flopr is
port (
d: in std_logic_vector(31 downto 0);
rst, clk: in std_logic;
q: out std_logic_vector(31 downto 0));
end entity;
architecture behavior of flopr is
begin
process (clk, rst) begin
if (rst = '1') then
q <= (others => '0');
elsif (clk'event and clk = '1') then
q <= d;
end if;
end process;
end architecture;
|
architecture RTL of FIFO is
begin
FOR_LABEL : for i in 0 to 7 generate
end generate FOR_LABEL;
IF_LABEL : if a = '1' generate
end generate IF_LABEL;
CASE_LABEL : case data generate
end generate CASE_LABEL;
-- Violations below
FOR_LABEL : for i in 0 to 7 generate
end generate;
IF_LABEL : if a = '1' generate
end generate;
CASE_LABEL : case data generate
end generate;
-- Nested generates
LABEL_1 : for i in 0 to 7 generate
LABEL_2 : if a = '1' generate
LABEL_3 : case data generate
end generate;
LABEL_4 : for i in 1 to 8 generate
end generate;
end generate;
LABEL_5 : if b = '1' generate
LABEL_6 : case data generate
end generate;
LABEL_7 : for i in 1 to 8 generate
end generate;
end generate;
end generate;
end;
|
-- -------------------------------------------------------------------------
-- High Level Design Compiler for Intel(R) FPGAs Version 17.0 (Release Build #595)
-- Quartus Prime development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2017 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly
-- subject to the terms and conditions of the Intel FPGA Software License
-- Agreement, Intel MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by Intel
-- and sold by Intel or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- ---------------------------------------------------------------------------
-- VHDL created from fp_div_0002
-- VHDL created on Thu Feb 15 13:09:40 2018
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_div_0002 is
port (
a : in std_logic_vector(31 downto 0); -- float32_m23
b : in std_logic_vector(31 downto 0); -- float32_m23
q : out std_logic_vector(31 downto 0); -- float32_m23
clk : in std_logic;
areset : in std_logic
);
end fp_div_0002;
architecture normal of fp_div_0002 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007";
signal GND_q : STD_LOGIC_VECTOR (0 downto 0);
signal VCC_q : STD_LOGIC_VECTOR (0 downto 0);
signal cstBiasM1_uid6_fpDivTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal expX_uid9_fpDivTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal fracX_uid10_fpDivTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal signX_uid11_fpDivTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal expY_uid12_fpDivTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal fracY_uid13_fpDivTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal signY_uid14_fpDivTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal paddingY_uid15_fpDivTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal updatedY_uid16_fpDivTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal fracYZero_uid15_fpDivTest_a : STD_LOGIC_VECTOR (23 downto 0);
signal fracYZero_uid15_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal fracYZero_uid15_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal cstAllOWE_uid18_fpDivTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal cstAllZWE_uid20_fpDivTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal excZ_x_uid23_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal excZ_x_uid23_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid24_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid24_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid25_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid25_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid26_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excI_x_uid27_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_x_uid28_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invExpXIsMax_uid29_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal InvExpXIsZero_uid30_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excR_x_uid31_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excZ_y_uid37_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal excZ_y_uid37_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid38_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal expXIsMax_uid38_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid39_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsZero_uid39_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal fracXIsNotZero_uid40_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excI_y_uid41_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excN_y_uid42_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal invExpXIsMax_uid43_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal InvExpXIsZero_uid44_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excR_y_uid45_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal signR_uid46_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal signR_uid46_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal expXmY_uid47_fpDivTest_a : STD_LOGIC_VECTOR (8 downto 0);
signal expXmY_uid47_fpDivTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal expXmY_uid47_fpDivTest_o : STD_LOGIC_VECTOR (8 downto 0);
signal expXmY_uid47_fpDivTest_q : STD_LOGIC_VECTOR (8 downto 0);
signal expR_uid48_fpDivTest_a : STD_LOGIC_VECTOR (10 downto 0);
signal expR_uid48_fpDivTest_b : STD_LOGIC_VECTOR (10 downto 0);
signal expR_uid48_fpDivTest_o : STD_LOGIC_VECTOR (10 downto 0);
signal expR_uid48_fpDivTest_q : STD_LOGIC_VECTOR (9 downto 0);
signal yAddr_uid51_fpDivTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal yPE_uid52_fpDivTest_b : STD_LOGIC_VECTOR (13 downto 0);
signal fracYPostZ_uid56_fpDivTest_qi : STD_LOGIC_VECTOR (0 downto 0);
signal fracYPostZ_uid56_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal lOAdded_uid58_fpDivTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal oFracXSE_bottomExtension_uid61_fpDivTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal oFracXSE_mergedSignalTM_uid63_fpDivTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal divValPreNormS_uid65_fpDivTest_b : STD_LOGIC_VECTOR (25 downto 0);
signal divValPreNormTrunc_uid66_fpDivTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal divValPreNormTrunc_uid66_fpDivTest_q : STD_LOGIC_VECTOR (25 downto 0);
signal norm_uid67_fpDivTest_b : STD_LOGIC_VECTOR (0 downto 0);
signal divValPreNormHigh_uid68_fpDivTest_in : STD_LOGIC_VECTOR (24 downto 0);
signal divValPreNormHigh_uid68_fpDivTest_b : STD_LOGIC_VECTOR (23 downto 0);
signal divValPreNormLow_uid69_fpDivTest_in : STD_LOGIC_VECTOR (23 downto 0);
signal divValPreNormLow_uid69_fpDivTest_b : STD_LOGIC_VECTOR (23 downto 0);
signal normFracRnd_uid70_fpDivTest_s : STD_LOGIC_VECTOR (0 downto 0);
signal normFracRnd_uid70_fpDivTest_q : STD_LOGIC_VECTOR (23 downto 0);
signal expFracRnd_uid71_fpDivTest_q : STD_LOGIC_VECTOR (33 downto 0);
signal rndOp_uid75_fpDivTest_q : STD_LOGIC_VECTOR (24 downto 0);
signal expFracPostRnd_uid76_fpDivTest_a : STD_LOGIC_VECTOR (35 downto 0);
signal expFracPostRnd_uid76_fpDivTest_b : STD_LOGIC_VECTOR (35 downto 0);
signal expFracPostRnd_uid76_fpDivTest_o : STD_LOGIC_VECTOR (35 downto 0);
signal expFracPostRnd_uid76_fpDivTest_q : STD_LOGIC_VECTOR (34 downto 0);
signal fracRPreExc_uid78_fpDivTest_in : STD_LOGIC_VECTOR (23 downto 0);
signal fracRPreExc_uid78_fpDivTest_b : STD_LOGIC_VECTOR (22 downto 0);
signal excRPreExc_uid79_fpDivTest_in : STD_LOGIC_VECTOR (31 downto 0);
signal excRPreExc_uid79_fpDivTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal expRExt_uid80_fpDivTest_b : STD_LOGIC_VECTOR (10 downto 0);
signal expUdf_uid81_fpDivTest_a : STD_LOGIC_VECTOR (12 downto 0);
signal expUdf_uid81_fpDivTest_b : STD_LOGIC_VECTOR (12 downto 0);
signal expUdf_uid81_fpDivTest_o : STD_LOGIC_VECTOR (12 downto 0);
signal expUdf_uid81_fpDivTest_n : STD_LOGIC_VECTOR (0 downto 0);
signal expOvf_uid84_fpDivTest_a : STD_LOGIC_VECTOR (12 downto 0);
signal expOvf_uid84_fpDivTest_b : STD_LOGIC_VECTOR (12 downto 0);
signal expOvf_uid84_fpDivTest_o : STD_LOGIC_VECTOR (12 downto 0);
signal expOvf_uid84_fpDivTest_n : STD_LOGIC_VECTOR (0 downto 0);
signal zeroOverReg_uid85_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal regOverRegWithUf_uid86_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal xRegOrZero_uid87_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal regOrZeroOverInf_uid88_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRZero_uid89_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXRYZ_uid90_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXRYROvf_uid91_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXIYZ_uid92_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXIYR_uid93_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRInf_uid94_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXZYZ_uid95_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excXIYI_uid96_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal excRNaN_uid97_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal concExc_uid98_fpDivTest_q : STD_LOGIC_VECTOR (2 downto 0);
signal excREnc_uid99_fpDivTest_q : STD_LOGIC_VECTOR (1 downto 0);
signal oneFracRPostExc2_uid100_fpDivTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal fracRPostExc_uid103_fpDivTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal fracRPostExc_uid103_fpDivTest_q : STD_LOGIC_VECTOR (22 downto 0);
signal expRPostExc_uid107_fpDivTest_s : STD_LOGIC_VECTOR (1 downto 0);
signal expRPostExc_uid107_fpDivTest_q : STD_LOGIC_VECTOR (7 downto 0);
signal invExcRNaN_uid108_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal sRPostExc_uid109_fpDivTest_q : STD_LOGIC_VECTOR (0 downto 0);
signal divR_uid110_fpDivTest_q : STD_LOGIC_VECTOR (31 downto 0);
signal os_uid114_invTables_q : STD_LOGIC_VECTOR (30 downto 0);
signal os_uid118_invTables_q : STD_LOGIC_VECTOR (20 downto 0);
signal yT1_uid126_invPolyEval_b : STD_LOGIC_VECTOR (11 downto 0);
signal rndBit_uid128_invPolyEval_q : STD_LOGIC_VECTOR (1 downto 0);
signal cIncludingRoundingBit_uid129_invPolyEval_q : STD_LOGIC_VECTOR (22 downto 0);
signal ts1_uid131_invPolyEval_a : STD_LOGIC_VECTOR (23 downto 0);
signal ts1_uid131_invPolyEval_b : STD_LOGIC_VECTOR (23 downto 0);
signal ts1_uid131_invPolyEval_o : STD_LOGIC_VECTOR (23 downto 0);
signal ts1_uid131_invPolyEval_q : STD_LOGIC_VECTOR (23 downto 0);
signal s1_uid132_invPolyEval_b : STD_LOGIC_VECTOR (22 downto 0);
signal rndBit_uid135_invPolyEval_q : STD_LOGIC_VECTOR (2 downto 0);
signal cIncludingRoundingBit_uid136_invPolyEval_q : STD_LOGIC_VECTOR (33 downto 0);
signal ts2_uid138_invPolyEval_a : STD_LOGIC_VECTOR (34 downto 0);
signal ts2_uid138_invPolyEval_b : STD_LOGIC_VECTOR (34 downto 0);
signal ts2_uid138_invPolyEval_o : STD_LOGIC_VECTOR (34 downto 0);
signal ts2_uid138_invPolyEval_q : STD_LOGIC_VECTOR (34 downto 0);
signal s2_uid139_invPolyEval_b : STD_LOGIC_VECTOR (33 downto 0);
signal topRangeX_uid149_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (17 downto 0);
signal topRangeY_uid150_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (17 downto 0);
signal aboveLeftX_uid155_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal aboveLeftY_bottomExtension_uid156_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (2 downto 0);
signal aboveLeftY_bottomRange_uid157_prodDivPreNormProd_uid60_fpDivTest_in : STD_LOGIC_VECTOR (5 downto 0);
signal aboveLeftY_bottomRange_uid157_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (5 downto 0);
signal aboveLeftY_mergedSignalTM_uid158_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (8 downto 0);
signal rightBottomX_bottomRange_uid161_prodDivPreNormProd_uid60_fpDivTest_in : STD_LOGIC_VECTOR (7 downto 0);
signal rightBottomX_bottomRange_uid161_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (7 downto 0);
signal rightBottomX_mergedSignalTM_uid162_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (8 downto 0);
signal rightBottomY_uid164_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (8 downto 0);
signal rightBottomX_uid168_prodDivPreNormProd_uid60_fpDivTest_in : STD_LOGIC_VECTOR (16 downto 0);
signal rightBottomX_uid168_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal rightBottomY_uid169_prodDivPreNormProd_uid60_fpDivTest_in : STD_LOGIC_VECTOR (5 downto 0);
signal rightBottomY_uid169_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal aboveLeftX_uid170_prodDivPreNormProd_uid60_fpDivTest_in : STD_LOGIC_VECTOR (7 downto 0);
signal aboveLeftX_uid170_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal aboveLeftY_uid171_prodDivPreNormProd_uid60_fpDivTest_in : STD_LOGIC_VECTOR (14 downto 0);
signal aboveLeftY_uid171_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (4 downto 0);
signal n0_uid177_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal n1_uid178_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal n0_uid179_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal n1_uid180_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (3 downto 0);
signal n0_uid185_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal n1_uid186_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal n0_uid187_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal n1_uid188_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (2 downto 0);
signal n0_uid193_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal n1_uid194_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal n0_uid195_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal n1_uid196_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (1 downto 0);
signal sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_a0 : STD_LOGIC_VECTOR (17 downto 0);
signal sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_b0 : STD_LOGIC_VECTOR (17 downto 0);
signal sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_s1 : STD_LOGIC_VECTOR (35 downto 0);
signal sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_reset : std_logic;
signal sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (35 downto 0);
signal sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_a0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_b0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_s1 : STD_LOGIC_VECTOR (17 downto 0);
signal sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_reset : std_logic;
signal sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (17 downto 0);
signal sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_a0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_b0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_s1 : STD_LOGIC_VECTOR (17 downto 0);
signal sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_reset : std_logic;
signal sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (17 downto 0);
signal sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_a0 : STD_LOGIC_VECTOR (1 downto 0);
signal sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_b0 : STD_LOGIC_VECTOR (1 downto 0);
signal sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_s1 : STD_LOGIC_VECTOR (3 downto 0);
signal sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_reset : std_logic;
signal sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (3 downto 0);
signal sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_a0 : STD_LOGIC_VECTOR (1 downto 0);
signal sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_b0 : STD_LOGIC_VECTOR (1 downto 0);
signal sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_s1 : STD_LOGIC_VECTOR (3 downto 0);
signal sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_reset : std_logic;
signal sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (3 downto 0);
signal lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_a : STD_LOGIC_VECTOR (36 downto 0);
signal lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (36 downto 0);
signal lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_o : STD_LOGIC_VECTOR (36 downto 0);
signal lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (36 downto 0);
signal lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_a : STD_LOGIC_VECTOR (13 downto 0);
signal lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (13 downto 0);
signal lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_o : STD_LOGIC_VECTOR (13 downto 0);
signal lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (13 downto 0);
signal lev1_a1_uid216_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (18 downto 0);
signal lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_a : STD_LOGIC_VECTOR (37 downto 0);
signal lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (37 downto 0);
signal lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_o : STD_LOGIC_VECTOR (37 downto 0);
signal lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (37 downto 0);
signal lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_a : STD_LOGIC_VECTOR (33 downto 0);
signal lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (33 downto 0);
signal lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_o : STD_LOGIC_VECTOR (33 downto 0);
signal lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (33 downto 0);
signal lev3_a0_uid221_prodDivPreNormProd_uid60_fpDivTest_q : STD_LOGIC_VECTOR (38 downto 0);
signal osig_uid222_prodDivPreNormProd_uid60_fpDivTest_in : STD_LOGIC_VECTOR (35 downto 0);
signal osig_uid222_prodDivPreNormProd_uid60_fpDivTest_b : STD_LOGIC_VECTOR (26 downto 0);
signal nx_mergedSignalTM_uid226_pT1_uid127_invPolyEval_q : STD_LOGIC_VECTOR (12 downto 0);
signal topRangeX_bottomExtension_uid239_pT1_uid127_invPolyEval_q : STD_LOGIC_VECTOR (3 downto 0);
signal topRangeX_mergedSignalTM_uid241_pT1_uid127_invPolyEval_q : STD_LOGIC_VECTOR (16 downto 0);
signal topRangeY_bottomExtension_uid243_pT1_uid127_invPolyEval_q : STD_LOGIC_VECTOR (4 downto 0);
signal topRangeY_mergedSignalTM_uid245_pT1_uid127_invPolyEval_q : STD_LOGIC_VECTOR (16 downto 0);
signal sm0_uid247_pT1_uid127_invPolyEval_a0 : STD_LOGIC_VECTOR (16 downto 0);
signal sm0_uid247_pT1_uid127_invPolyEval_b0 : STD_LOGIC_VECTOR (16 downto 0);
signal sm0_uid247_pT1_uid127_invPolyEval_s1 : STD_LOGIC_VECTOR (33 downto 0);
signal sm0_uid247_pT1_uid127_invPolyEval_reset : std_logic;
signal sm0_uid247_pT1_uid127_invPolyEval_q : STD_LOGIC_VECTOR (33 downto 0);
signal osig_uid248_pT1_uid127_invPolyEval_in : STD_LOGIC_VECTOR (32 downto 0);
signal osig_uid248_pT1_uid127_invPolyEval_b : STD_LOGIC_VECTOR (13 downto 0);
signal nx_mergedSignalTM_uid252_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (14 downto 0);
signal topRangeX_mergedSignalTM_uid264_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (16 downto 0);
signal topRangeY_uid266_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (16 downto 0);
signal aboveLeftX_uid272_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (7 downto 0);
signal aboveLeftY_bottomRange_uid274_pT2_uid134_invPolyEval_in : STD_LOGIC_VECTOR (5 downto 0);
signal aboveLeftY_bottomRange_uid274_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (5 downto 0);
signal aboveLeftY_mergedSignalTM_uid275_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (7 downto 0);
signal rightBottomX_uid283_pT2_uid134_invPolyEval_in : STD_LOGIC_VECTOR (6 downto 0);
signal rightBottomX_uid283_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (4 downto 0);
signal rightBottomY_uid284_pT2_uid134_invPolyEval_in : STD_LOGIC_VECTOR (5 downto 0);
signal rightBottomY_uid284_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (4 downto 0);
signal n0_uid293_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (3 downto 0);
signal n1_uid294_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (3 downto 0);
signal n0_uid301_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (2 downto 0);
signal n1_uid302_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (2 downto 0);
signal sm0_uid315_pT2_uid134_invPolyEval_a0 : STD_LOGIC_VECTOR (16 downto 0);
signal sm0_uid315_pT2_uid134_invPolyEval_b0 : STD_LOGIC_VECTOR (16 downto 0);
signal sm0_uid315_pT2_uid134_invPolyEval_s1 : STD_LOGIC_VECTOR (33 downto 0);
signal sm0_uid315_pT2_uid134_invPolyEval_reset : std_logic;
signal sm0_uid315_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (33 downto 0);
signal sm0_uid316_pT2_uid134_invPolyEval_a0 : STD_LOGIC_VECTOR (7 downto 0);
signal sm0_uid316_pT2_uid134_invPolyEval_b0 : STD_LOGIC_VECTOR (8 downto 0);
signal sm0_uid316_pT2_uid134_invPolyEval_s1 : STD_LOGIC_VECTOR (16 downto 0);
signal sm0_uid316_pT2_uid134_invPolyEval_reset : std_logic;
signal sm0_uid316_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (15 downto 0);
signal sm0_uid317_pT2_uid134_invPolyEval_a0 : STD_LOGIC_VECTOR (2 downto 0);
signal sm0_uid317_pT2_uid134_invPolyEval_b0 : STD_LOGIC_VECTOR (2 downto 0);
signal sm0_uid317_pT2_uid134_invPolyEval_s1 : STD_LOGIC_VECTOR (5 downto 0);
signal sm0_uid317_pT2_uid134_invPolyEval_reset : std_logic;
signal sm0_uid317_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (5 downto 0);
signal lowRangeA_uid318_pT2_uid134_invPolyEval_in : STD_LOGIC_VECTOR (0 downto 0);
signal lowRangeA_uid318_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (0 downto 0);
signal highABits_uid319_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (32 downto 0);
signal lev1_a0high_uid320_pT2_uid134_invPolyEval_a : STD_LOGIC_VECTOR (33 downto 0);
signal lev1_a0high_uid320_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (33 downto 0);
signal lev1_a0high_uid320_pT2_uid134_invPolyEval_o : STD_LOGIC_VECTOR (33 downto 0);
signal lev1_a0high_uid320_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (33 downto 0);
signal lev1_a0_uid321_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (34 downto 0);
signal lowRangeA_uid322_pT2_uid134_invPolyEval_in : STD_LOGIC_VECTOR (2 downto 0);
signal lowRangeA_uid322_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (2 downto 0);
signal highABits_uid323_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (31 downto 0);
signal lev2_a0high_uid324_pT2_uid134_invPolyEval_a : STD_LOGIC_VECTOR (33 downto 0);
signal lev2_a0high_uid324_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (33 downto 0);
signal lev2_a0high_uid324_pT2_uid134_invPolyEval_o : STD_LOGIC_VECTOR (33 downto 0);
signal lev2_a0high_uid324_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (32 downto 0);
signal lev2_a0_uid325_pT2_uid134_invPolyEval_q : STD_LOGIC_VECTOR (35 downto 0);
signal osig_uid326_pT2_uid134_invPolyEval_in : STD_LOGIC_VECTOR (32 downto 0);
signal osig_uid326_pT2_uid134_invPolyEval_b : STD_LOGIC_VECTOR (24 downto 0);
signal memoryC0_uid112_invTables_lutmem_reset0 : std_logic;
signal memoryC0_uid112_invTables_lutmem_ia : STD_LOGIC_VECTOR (17 downto 0);
signal memoryC0_uid112_invTables_lutmem_aa : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC0_uid112_invTables_lutmem_ab : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC0_uid112_invTables_lutmem_ir : STD_LOGIC_VECTOR (17 downto 0);
signal memoryC0_uid112_invTables_lutmem_r : STD_LOGIC_VECTOR (17 downto 0);
signal memoryC0_uid113_invTables_lutmem_reset0 : std_logic;
signal memoryC0_uid113_invTables_lutmem_ia : STD_LOGIC_VECTOR (12 downto 0);
signal memoryC0_uid113_invTables_lutmem_aa : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC0_uid113_invTables_lutmem_ab : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC0_uid113_invTables_lutmem_ir : STD_LOGIC_VECTOR (12 downto 0);
signal memoryC0_uid113_invTables_lutmem_r : STD_LOGIC_VECTOR (12 downto 0);
signal memoryC1_uid116_invTables_lutmem_reset0 : std_logic;
signal memoryC1_uid116_invTables_lutmem_ia : STD_LOGIC_VECTOR (17 downto 0);
signal memoryC1_uid116_invTables_lutmem_aa : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC1_uid116_invTables_lutmem_ab : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC1_uid116_invTables_lutmem_ir : STD_LOGIC_VECTOR (17 downto 0);
signal memoryC1_uid116_invTables_lutmem_r : STD_LOGIC_VECTOR (17 downto 0);
signal memoryC1_uid117_invTables_lutmem_reset0 : std_logic;
signal memoryC1_uid117_invTables_lutmem_ia : STD_LOGIC_VECTOR (2 downto 0);
signal memoryC1_uid117_invTables_lutmem_aa : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC1_uid117_invTables_lutmem_ab : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC1_uid117_invTables_lutmem_ir : STD_LOGIC_VECTOR (2 downto 0);
signal memoryC1_uid117_invTables_lutmem_r : STD_LOGIC_VECTOR (2 downto 0);
signal memoryC2_uid120_invTables_lutmem_reset0 : std_logic;
signal memoryC2_uid120_invTables_lutmem_ia : STD_LOGIC_VECTOR (11 downto 0);
signal memoryC2_uid120_invTables_lutmem_aa : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC2_uid120_invTables_lutmem_ab : STD_LOGIC_VECTOR (8 downto 0);
signal memoryC2_uid120_invTables_lutmem_ir : STD_LOGIC_VECTOR (11 downto 0);
signal memoryC2_uid120_invTables_lutmem_r : STD_LOGIC_VECTOR (11 downto 0);
signal invY_uid54_fpDivTest_merged_bit_select_in : STD_LOGIC_VECTOR (31 downto 0);
signal invY_uid54_fpDivTest_merged_bit_select_b : STD_LOGIC_VECTOR (25 downto 0);
signal invY_uid54_fpDivTest_merged_bit_select_c : STD_LOGIC_VECTOR (0 downto 0);
signal lowRangeA_uid213_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_b : STD_LOGIC_VECTOR (4 downto 0);
signal lowRangeA_uid213_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_c : STD_LOGIC_VECTOR (12 downto 0);
signal lowRangeA_uid218_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_b : STD_LOGIC_VECTOR (4 downto 0);
signal lowRangeA_uid218_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_c : STD_LOGIC_VECTOR (32 downto 0);
signal redist0_lOAdded_uid58_fpDivTest_q_2_q : STD_LOGIC_VECTOR (23 downto 0);
signal redist1_fracYPostZ_uid56_fpDivTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist2_yPE_uid52_fpDivTest_b_2_q : STD_LOGIC_VECTOR (13 downto 0);
signal redist3_yPE_uid52_fpDivTest_b_4_q : STD_LOGIC_VECTOR (13 downto 0);
signal redist4_yAddr_uid51_fpDivTest_b_2_q : STD_LOGIC_VECTOR (8 downto 0);
signal redist5_yAddr_uid51_fpDivTest_b_4_q : STD_LOGIC_VECTOR (8 downto 0);
signal redist6_expXmY_uid47_fpDivTest_q_8_q : STD_LOGIC_VECTOR (8 downto 0);
signal redist7_signR_uid46_fpDivTest_q_8_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist8_fracXIsZero_uid39_fpDivTest_q_8_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist9_expXIsMax_uid38_fpDivTest_q_8_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist10_excZ_y_uid37_fpDivTest_q_8_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist11_fracXIsZero_uid25_fpDivTest_q_2_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist12_expXIsMax_uid24_fpDivTest_q_8_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist13_excZ_x_uid23_fpDivTest_q_8_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist14_fracYZero_uid15_fpDivTest_q_6_q : STD_LOGIC_VECTOR (0 downto 0);
signal redist15_fracX_uid10_fpDivTest_b_6_q : STD_LOGIC_VECTOR (22 downto 0);
begin
-- fracY_uid13_fpDivTest(BITSELECT,12)@0
fracY_uid13_fpDivTest_b <= b(22 downto 0);
-- paddingY_uid15_fpDivTest(CONSTANT,14)
paddingY_uid15_fpDivTest_q <= "00000000000000000000000";
-- fracXIsZero_uid39_fpDivTest(LOGICAL,38)@0 + 1
fracXIsZero_uid39_fpDivTest_qi <= "1" WHEN paddingY_uid15_fpDivTest_q = fracY_uid13_fpDivTest_b ELSE "0";
fracXIsZero_uid39_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid39_fpDivTest_qi, xout => fracXIsZero_uid39_fpDivTest_q, clk => clk, aclr => areset );
-- redist8_fracXIsZero_uid39_fpDivTest_q_8(DELAY,343)
redist8_fracXIsZero_uid39_fpDivTest_q_8 : dspba_delay
GENERIC MAP ( width => 1, depth => 7, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid39_fpDivTest_q, xout => redist8_fracXIsZero_uid39_fpDivTest_q_8_q, clk => clk, aclr => areset );
-- cstAllOWE_uid18_fpDivTest(CONSTANT,17)
cstAllOWE_uid18_fpDivTest_q <= "11111111";
-- expY_uid12_fpDivTest(BITSELECT,11)@0
expY_uid12_fpDivTest_b <= b(30 downto 23);
-- expXIsMax_uid38_fpDivTest(LOGICAL,37)@0 + 1
expXIsMax_uid38_fpDivTest_qi <= "1" WHEN expY_uid12_fpDivTest_b = cstAllOWE_uid18_fpDivTest_q ELSE "0";
expXIsMax_uid38_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid38_fpDivTest_qi, xout => expXIsMax_uid38_fpDivTest_q, clk => clk, aclr => areset );
-- redist9_expXIsMax_uid38_fpDivTest_q_8(DELAY,344)
redist9_expXIsMax_uid38_fpDivTest_q_8 : dspba_delay
GENERIC MAP ( width => 1, depth => 7, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid38_fpDivTest_q, xout => redist9_expXIsMax_uid38_fpDivTest_q_8_q, clk => clk, aclr => areset );
-- excI_y_uid41_fpDivTest(LOGICAL,40)@8
excI_y_uid41_fpDivTest_q <= redist9_expXIsMax_uid38_fpDivTest_q_8_q and redist8_fracXIsZero_uid39_fpDivTest_q_8_q;
-- fracX_uid10_fpDivTest(BITSELECT,9)@0
fracX_uid10_fpDivTest_b <= a(22 downto 0);
-- redist15_fracX_uid10_fpDivTest_b_6(DELAY,350)
redist15_fracX_uid10_fpDivTest_b_6 : dspba_delay
GENERIC MAP ( width => 23, depth => 6, reset_kind => "ASYNC" )
PORT MAP ( xin => fracX_uid10_fpDivTest_b, xout => redist15_fracX_uid10_fpDivTest_b_6_q, clk => clk, aclr => areset );
-- fracXIsZero_uid25_fpDivTest(LOGICAL,24)@6 + 1
fracXIsZero_uid25_fpDivTest_qi <= "1" WHEN paddingY_uid15_fpDivTest_q = redist15_fracX_uid10_fpDivTest_b_6_q ELSE "0";
fracXIsZero_uid25_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid25_fpDivTest_qi, xout => fracXIsZero_uid25_fpDivTest_q, clk => clk, aclr => areset );
-- redist11_fracXIsZero_uid25_fpDivTest_q_2(DELAY,346)
redist11_fracXIsZero_uid25_fpDivTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracXIsZero_uid25_fpDivTest_q, xout => redist11_fracXIsZero_uid25_fpDivTest_q_2_q, clk => clk, aclr => areset );
-- expX_uid9_fpDivTest(BITSELECT,8)@0
expX_uid9_fpDivTest_b <= a(30 downto 23);
-- expXIsMax_uid24_fpDivTest(LOGICAL,23)@0 + 1
expXIsMax_uid24_fpDivTest_qi <= "1" WHEN expX_uid9_fpDivTest_b = cstAllOWE_uid18_fpDivTest_q ELSE "0";
expXIsMax_uid24_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid24_fpDivTest_qi, xout => expXIsMax_uid24_fpDivTest_q, clk => clk, aclr => areset );
-- redist12_expXIsMax_uid24_fpDivTest_q_8(DELAY,347)
redist12_expXIsMax_uid24_fpDivTest_q_8 : dspba_delay
GENERIC MAP ( width => 1, depth => 7, reset_kind => "ASYNC" )
PORT MAP ( xin => expXIsMax_uid24_fpDivTest_q, xout => redist12_expXIsMax_uid24_fpDivTest_q_8_q, clk => clk, aclr => areset );
-- excI_x_uid27_fpDivTest(LOGICAL,26)@8
excI_x_uid27_fpDivTest_q <= redist12_expXIsMax_uid24_fpDivTest_q_8_q and redist11_fracXIsZero_uid25_fpDivTest_q_2_q;
-- excXIYI_uid96_fpDivTest(LOGICAL,95)@8
excXIYI_uid96_fpDivTest_q <= excI_x_uid27_fpDivTest_q and excI_y_uid41_fpDivTest_q;
-- fracXIsNotZero_uid40_fpDivTest(LOGICAL,39)@8
fracXIsNotZero_uid40_fpDivTest_q <= not (redist8_fracXIsZero_uid39_fpDivTest_q_8_q);
-- excN_y_uid42_fpDivTest(LOGICAL,41)@8
excN_y_uid42_fpDivTest_q <= redist9_expXIsMax_uid38_fpDivTest_q_8_q and fracXIsNotZero_uid40_fpDivTest_q;
-- fracXIsNotZero_uid26_fpDivTest(LOGICAL,25)@8
fracXIsNotZero_uid26_fpDivTest_q <= not (redist11_fracXIsZero_uid25_fpDivTest_q_2_q);
-- excN_x_uid28_fpDivTest(LOGICAL,27)@8
excN_x_uid28_fpDivTest_q <= redist12_expXIsMax_uid24_fpDivTest_q_8_q and fracXIsNotZero_uid26_fpDivTest_q;
-- cstAllZWE_uid20_fpDivTest(CONSTANT,19)
cstAllZWE_uid20_fpDivTest_q <= "00000000";
-- excZ_y_uid37_fpDivTest(LOGICAL,36)@0 + 1
excZ_y_uid37_fpDivTest_qi <= "1" WHEN expY_uid12_fpDivTest_b = cstAllZWE_uid20_fpDivTest_q ELSE "0";
excZ_y_uid37_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_y_uid37_fpDivTest_qi, xout => excZ_y_uid37_fpDivTest_q, clk => clk, aclr => areset );
-- redist10_excZ_y_uid37_fpDivTest_q_8(DELAY,345)
redist10_excZ_y_uid37_fpDivTest_q_8 : dspba_delay
GENERIC MAP ( width => 1, depth => 7, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_y_uid37_fpDivTest_q, xout => redist10_excZ_y_uid37_fpDivTest_q_8_q, clk => clk, aclr => areset );
-- excZ_x_uid23_fpDivTest(LOGICAL,22)@0 + 1
excZ_x_uid23_fpDivTest_qi <= "1" WHEN expX_uid9_fpDivTest_b = cstAllZWE_uid20_fpDivTest_q ELSE "0";
excZ_x_uid23_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_x_uid23_fpDivTest_qi, xout => excZ_x_uid23_fpDivTest_q, clk => clk, aclr => areset );
-- redist13_excZ_x_uid23_fpDivTest_q_8(DELAY,348)
redist13_excZ_x_uid23_fpDivTest_q_8 : dspba_delay
GENERIC MAP ( width => 1, depth => 7, reset_kind => "ASYNC" )
PORT MAP ( xin => excZ_x_uid23_fpDivTest_q, xout => redist13_excZ_x_uid23_fpDivTest_q_8_q, clk => clk, aclr => areset );
-- excXZYZ_uid95_fpDivTest(LOGICAL,94)@8
excXZYZ_uid95_fpDivTest_q <= redist13_excZ_x_uid23_fpDivTest_q_8_q and redist10_excZ_y_uid37_fpDivTest_q_8_q;
-- excRNaN_uid97_fpDivTest(LOGICAL,96)@8
excRNaN_uid97_fpDivTest_q <= excXZYZ_uid95_fpDivTest_q or excN_x_uid28_fpDivTest_q or excN_y_uid42_fpDivTest_q or excXIYI_uid96_fpDivTest_q;
-- invExcRNaN_uid108_fpDivTest(LOGICAL,107)@8
invExcRNaN_uid108_fpDivTest_q <= not (excRNaN_uid97_fpDivTest_q);
-- signY_uid14_fpDivTest(BITSELECT,13)@0
signY_uid14_fpDivTest_b <= STD_LOGIC_VECTOR(b(31 downto 31));
-- signX_uid11_fpDivTest(BITSELECT,10)@0
signX_uid11_fpDivTest_b <= STD_LOGIC_VECTOR(a(31 downto 31));
-- signR_uid46_fpDivTest(LOGICAL,45)@0 + 1
signR_uid46_fpDivTest_qi <= signX_uid11_fpDivTest_b xor signY_uid14_fpDivTest_b;
signR_uid46_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => signR_uid46_fpDivTest_qi, xout => signR_uid46_fpDivTest_q, clk => clk, aclr => areset );
-- redist7_signR_uid46_fpDivTest_q_8(DELAY,342)
redist7_signR_uid46_fpDivTest_q_8 : dspba_delay
GENERIC MAP ( width => 1, depth => 7, reset_kind => "ASYNC" )
PORT MAP ( xin => signR_uid46_fpDivTest_q, xout => redist7_signR_uid46_fpDivTest_q_8_q, clk => clk, aclr => areset );
-- VCC(CONSTANT,1)
VCC_q <= "1";
-- sRPostExc_uid109_fpDivTest(LOGICAL,108)@8
sRPostExc_uid109_fpDivTest_q <= redist7_signR_uid46_fpDivTest_q_8_q and invExcRNaN_uid108_fpDivTest_q;
-- lOAdded_uid58_fpDivTest(BITJOIN,57)@6
lOAdded_uid58_fpDivTest_q <= VCC_q & redist15_fracX_uid10_fpDivTest_b_6_q;
-- redist0_lOAdded_uid58_fpDivTest_q_2(DELAY,335)
redist0_lOAdded_uid58_fpDivTest_q_2 : dspba_delay
GENERIC MAP ( width => 24, depth => 2, reset_kind => "ASYNC" )
PORT MAP ( xin => lOAdded_uid58_fpDivTest_q, xout => redist0_lOAdded_uid58_fpDivTest_q_2_q, clk => clk, aclr => areset );
-- oFracXSE_bottomExtension_uid61_fpDivTest(CONSTANT,60)
oFracXSE_bottomExtension_uid61_fpDivTest_q <= "00";
-- oFracXSE_mergedSignalTM_uid63_fpDivTest(BITJOIN,62)@8
oFracXSE_mergedSignalTM_uid63_fpDivTest_q <= redist0_lOAdded_uid58_fpDivTest_q_2_q & oFracXSE_bottomExtension_uid61_fpDivTest_q;
-- aboveLeftY_uid171_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,170)@6
aboveLeftY_uid171_prodDivPreNormProd_uid60_fpDivTest_in <= lOAdded_uid58_fpDivTest_q(14 downto 0);
aboveLeftY_uid171_prodDivPreNormProd_uid60_fpDivTest_b <= aboveLeftY_uid171_prodDivPreNormProd_uid60_fpDivTest_in(14 downto 10);
-- n1_uid180_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,179)@6
n1_uid180_prodDivPreNormProd_uid60_fpDivTest_b <= aboveLeftY_uid171_prodDivPreNormProd_uid60_fpDivTest_b(4 downto 1);
-- n1_uid188_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,187)@6
n1_uid188_prodDivPreNormProd_uid60_fpDivTest_b <= n1_uid180_prodDivPreNormProd_uid60_fpDivTest_b(3 downto 1);
-- n1_uid196_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,195)@6
n1_uid196_prodDivPreNormProd_uid60_fpDivTest_b <= n1_uid188_prodDivPreNormProd_uid60_fpDivTest_b(2 downto 1);
-- yAddr_uid51_fpDivTest(BITSELECT,50)@0
yAddr_uid51_fpDivTest_b <= fracY_uid13_fpDivTest_b(22 downto 14);
-- memoryC2_uid120_invTables_lutmem(DUALMEM,331)@0 + 2
memoryC2_uid120_invTables_lutmem_aa <= yAddr_uid51_fpDivTest_b;
memoryC2_uid120_invTables_lutmem_reset0 <= areset;
memoryC2_uid120_invTables_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M9K",
operation_mode => "ROM",
width_a => 12,
widthad_a => 9,
numwords_a => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
outdata_reg_a => "CLOCK0",
outdata_aclr_a => "CLEAR0",
clock_enable_input_a => "NORMAL",
power_up_uninitialized => "FALSE",
init_file => "fp_div_0002_memoryC2_uid120_invTables_lutmem.hex",
init_file_layout => "PORT_A",
intended_device_family => "MAX 10"
)
PORT MAP (
clocken0 => VCC_q(0),
aclr0 => memoryC2_uid120_invTables_lutmem_reset0,
clock0 => clk,
address_a => memoryC2_uid120_invTables_lutmem_aa,
q_a => memoryC2_uid120_invTables_lutmem_ir
);
memoryC2_uid120_invTables_lutmem_r <= memoryC2_uid120_invTables_lutmem_ir(11 downto 0);
-- topRangeY_bottomExtension_uid243_pT1_uid127_invPolyEval(CONSTANT,242)
topRangeY_bottomExtension_uid243_pT1_uid127_invPolyEval_q <= "00000";
-- topRangeY_mergedSignalTM_uid245_pT1_uid127_invPolyEval(BITJOIN,244)@2
topRangeY_mergedSignalTM_uid245_pT1_uid127_invPolyEval_q <= memoryC2_uid120_invTables_lutmem_r & topRangeY_bottomExtension_uid243_pT1_uid127_invPolyEval_q;
-- GND(CONSTANT,0)
GND_q <= "0";
-- yPE_uid52_fpDivTest(BITSELECT,51)@0
yPE_uid52_fpDivTest_b <= b(13 downto 0);
-- redist2_yPE_uid52_fpDivTest_b_2(DELAY,337)
redist2_yPE_uid52_fpDivTest_b_2 : dspba_delay
GENERIC MAP ( width => 14, depth => 2, reset_kind => "ASYNC" )
PORT MAP ( xin => yPE_uid52_fpDivTest_b, xout => redist2_yPE_uid52_fpDivTest_b_2_q, clk => clk, aclr => areset );
-- yT1_uid126_invPolyEval(BITSELECT,125)@2
yT1_uid126_invPolyEval_b <= redist2_yPE_uid52_fpDivTest_b_2_q(13 downto 2);
-- nx_mergedSignalTM_uid226_pT1_uid127_invPolyEval(BITJOIN,225)@2
nx_mergedSignalTM_uid226_pT1_uid127_invPolyEval_q <= GND_q & yT1_uid126_invPolyEval_b;
-- topRangeX_bottomExtension_uid239_pT1_uid127_invPolyEval(CONSTANT,238)
topRangeX_bottomExtension_uid239_pT1_uid127_invPolyEval_q <= "0000";
-- topRangeX_mergedSignalTM_uid241_pT1_uid127_invPolyEval(BITJOIN,240)@2
topRangeX_mergedSignalTM_uid241_pT1_uid127_invPolyEval_q <= nx_mergedSignalTM_uid226_pT1_uid127_invPolyEval_q & topRangeX_bottomExtension_uid239_pT1_uid127_invPolyEval_q;
-- sm0_uid247_pT1_uid127_invPolyEval(MULT,246)@2 + 2
sm0_uid247_pT1_uid127_invPolyEval_a0 <= STD_LOGIC_VECTOR(topRangeX_mergedSignalTM_uid241_pT1_uid127_invPolyEval_q);
sm0_uid247_pT1_uid127_invPolyEval_b0 <= STD_LOGIC_VECTOR(topRangeY_mergedSignalTM_uid245_pT1_uid127_invPolyEval_q);
sm0_uid247_pT1_uid127_invPolyEval_reset <= areset;
sm0_uid247_pT1_uid127_invPolyEval_component : lpm_mult
GENERIC MAP (
lpm_widtha => 17,
lpm_widthb => 17,
lpm_widthp => 34,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid247_pT1_uid127_invPolyEval_a0,
datab => sm0_uid247_pT1_uid127_invPolyEval_b0,
clken => VCC_q(0),
aclr => sm0_uid247_pT1_uid127_invPolyEval_reset,
clock => clk,
result => sm0_uid247_pT1_uid127_invPolyEval_s1
);
sm0_uid247_pT1_uid127_invPolyEval_q <= sm0_uid247_pT1_uid127_invPolyEval_s1;
-- osig_uid248_pT1_uid127_invPolyEval(BITSELECT,247)@4
osig_uid248_pT1_uid127_invPolyEval_in <= STD_LOGIC_VECTOR(sm0_uid247_pT1_uid127_invPolyEval_q(32 downto 0));
osig_uid248_pT1_uid127_invPolyEval_b <= STD_LOGIC_VECTOR(osig_uid248_pT1_uid127_invPolyEval_in(32 downto 19));
-- redist4_yAddr_uid51_fpDivTest_b_2(DELAY,339)
redist4_yAddr_uid51_fpDivTest_b_2 : dspba_delay
GENERIC MAP ( width => 9, depth => 2, reset_kind => "ASYNC" )
PORT MAP ( xin => yAddr_uid51_fpDivTest_b, xout => redist4_yAddr_uid51_fpDivTest_b_2_q, clk => clk, aclr => areset );
-- memoryC1_uid117_invTables_lutmem(DUALMEM,330)@2 + 2
memoryC1_uid117_invTables_lutmem_aa <= redist4_yAddr_uid51_fpDivTest_b_2_q;
memoryC1_uid117_invTables_lutmem_reset0 <= areset;
memoryC1_uid117_invTables_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M9K",
operation_mode => "ROM",
width_a => 3,
widthad_a => 9,
numwords_a => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
outdata_reg_a => "CLOCK0",
outdata_aclr_a => "CLEAR0",
clock_enable_input_a => "NORMAL",
power_up_uninitialized => "FALSE",
init_file => "fp_div_0002_memoryC1_uid117_invTables_lutmem.hex",
init_file_layout => "PORT_A",
intended_device_family => "MAX 10"
)
PORT MAP (
clocken0 => VCC_q(0),
aclr0 => memoryC1_uid117_invTables_lutmem_reset0,
clock0 => clk,
address_a => memoryC1_uid117_invTables_lutmem_aa,
q_a => memoryC1_uid117_invTables_lutmem_ir
);
memoryC1_uid117_invTables_lutmem_r <= memoryC1_uid117_invTables_lutmem_ir(2 downto 0);
-- memoryC1_uid116_invTables_lutmem(DUALMEM,329)@2 + 2
memoryC1_uid116_invTables_lutmem_aa <= redist4_yAddr_uid51_fpDivTest_b_2_q;
memoryC1_uid116_invTables_lutmem_reset0 <= areset;
memoryC1_uid116_invTables_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M9K",
operation_mode => "ROM",
width_a => 18,
widthad_a => 9,
numwords_a => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
outdata_reg_a => "CLOCK0",
outdata_aclr_a => "CLEAR0",
clock_enable_input_a => "NORMAL",
power_up_uninitialized => "FALSE",
init_file => "fp_div_0002_memoryC1_uid116_invTables_lutmem.hex",
init_file_layout => "PORT_A",
intended_device_family => "MAX 10"
)
PORT MAP (
clocken0 => VCC_q(0),
aclr0 => memoryC1_uid116_invTables_lutmem_reset0,
clock0 => clk,
address_a => memoryC1_uid116_invTables_lutmem_aa,
q_a => memoryC1_uid116_invTables_lutmem_ir
);
memoryC1_uid116_invTables_lutmem_r <= memoryC1_uid116_invTables_lutmem_ir(17 downto 0);
-- os_uid118_invTables(BITJOIN,117)@4
os_uid118_invTables_q <= memoryC1_uid117_invTables_lutmem_r & memoryC1_uid116_invTables_lutmem_r;
-- rndBit_uid128_invPolyEval(CONSTANT,127)
rndBit_uid128_invPolyEval_q <= "01";
-- cIncludingRoundingBit_uid129_invPolyEval(BITJOIN,128)@4
cIncludingRoundingBit_uid129_invPolyEval_q <= os_uid118_invTables_q & rndBit_uid128_invPolyEval_q;
-- ts1_uid131_invPolyEval(ADD,130)@4
ts1_uid131_invPolyEval_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((23 downto 23 => cIncludingRoundingBit_uid129_invPolyEval_q(22)) & cIncludingRoundingBit_uid129_invPolyEval_q));
ts1_uid131_invPolyEval_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((23 downto 14 => osig_uid248_pT1_uid127_invPolyEval_b(13)) & osig_uid248_pT1_uid127_invPolyEval_b));
ts1_uid131_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts1_uid131_invPolyEval_a) + SIGNED(ts1_uid131_invPolyEval_b));
ts1_uid131_invPolyEval_q <= ts1_uid131_invPolyEval_o(23 downto 0);
-- s1_uid132_invPolyEval(BITSELECT,131)@4
s1_uid132_invPolyEval_b <= STD_LOGIC_VECTOR(ts1_uid131_invPolyEval_q(23 downto 1));
-- rightBottomY_uid284_pT2_uid134_invPolyEval(BITSELECT,283)@4
rightBottomY_uid284_pT2_uid134_invPolyEval_in <= s1_uid132_invPolyEval_b(5 downto 0);
rightBottomY_uid284_pT2_uid134_invPolyEval_b <= rightBottomY_uid284_pT2_uid134_invPolyEval_in(5 downto 1);
-- n1_uid294_pT2_uid134_invPolyEval(BITSELECT,293)@4
n1_uid294_pT2_uid134_invPolyEval_b <= rightBottomY_uid284_pT2_uid134_invPolyEval_b(4 downto 1);
-- n1_uid302_pT2_uid134_invPolyEval(BITSELECT,301)@4
n1_uid302_pT2_uid134_invPolyEval_b <= n1_uid294_pT2_uid134_invPolyEval_b(3 downto 1);
-- redist3_yPE_uid52_fpDivTest_b_4(DELAY,338)
redist3_yPE_uid52_fpDivTest_b_4 : dspba_delay
GENERIC MAP ( width => 14, depth => 2, reset_kind => "ASYNC" )
PORT MAP ( xin => redist2_yPE_uid52_fpDivTest_b_2_q, xout => redist3_yPE_uid52_fpDivTest_b_4_q, clk => clk, aclr => areset );
-- nx_mergedSignalTM_uid252_pT2_uid134_invPolyEval(BITJOIN,251)@4
nx_mergedSignalTM_uid252_pT2_uid134_invPolyEval_q <= GND_q & redist3_yPE_uid52_fpDivTest_b_4_q;
-- rightBottomX_uid283_pT2_uid134_invPolyEval(BITSELECT,282)@4
rightBottomX_uid283_pT2_uid134_invPolyEval_in <= nx_mergedSignalTM_uid252_pT2_uid134_invPolyEval_q(6 downto 0);
rightBottomX_uid283_pT2_uid134_invPolyEval_b <= rightBottomX_uid283_pT2_uid134_invPolyEval_in(6 downto 2);
-- n0_uid293_pT2_uid134_invPolyEval(BITSELECT,292)@4
n0_uid293_pT2_uid134_invPolyEval_b <= rightBottomX_uid283_pT2_uid134_invPolyEval_b(4 downto 1);
-- n0_uid301_pT2_uid134_invPolyEval(BITSELECT,300)@4
n0_uid301_pT2_uid134_invPolyEval_b <= n0_uid293_pT2_uid134_invPolyEval_b(3 downto 1);
-- sm0_uid317_pT2_uid134_invPolyEval(MULT,316)@4 + 2
sm0_uid317_pT2_uid134_invPolyEval_a0 <= n0_uid301_pT2_uid134_invPolyEval_b;
sm0_uid317_pT2_uid134_invPolyEval_b0 <= n1_uid302_pT2_uid134_invPolyEval_b;
sm0_uid317_pT2_uid134_invPolyEval_reset <= areset;
sm0_uid317_pT2_uid134_invPolyEval_component : lpm_mult
GENERIC MAP (
lpm_widtha => 3,
lpm_widthb => 3,
lpm_widthp => 6,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=NO, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid317_pT2_uid134_invPolyEval_a0,
datab => sm0_uid317_pT2_uid134_invPolyEval_b0,
clken => VCC_q(0),
aclr => sm0_uid317_pT2_uid134_invPolyEval_reset,
clock => clk,
result => sm0_uid317_pT2_uid134_invPolyEval_s1
);
sm0_uid317_pT2_uid134_invPolyEval_q <= sm0_uid317_pT2_uid134_invPolyEval_s1;
-- aboveLeftY_bottomRange_uid274_pT2_uid134_invPolyEval(BITSELECT,273)@4
aboveLeftY_bottomRange_uid274_pT2_uid134_invPolyEval_in <= STD_LOGIC_VECTOR(s1_uid132_invPolyEval_b(5 downto 0));
aboveLeftY_bottomRange_uid274_pT2_uid134_invPolyEval_b <= STD_LOGIC_VECTOR(aboveLeftY_bottomRange_uid274_pT2_uid134_invPolyEval_in(5 downto 0));
-- aboveLeftY_mergedSignalTM_uid275_pT2_uid134_invPolyEval(BITJOIN,274)@4
aboveLeftY_mergedSignalTM_uid275_pT2_uid134_invPolyEval_q <= aboveLeftY_bottomRange_uid274_pT2_uid134_invPolyEval_b & oFracXSE_bottomExtension_uid61_fpDivTest_q;
-- aboveLeftX_uid272_pT2_uid134_invPolyEval(BITSELECT,271)@4
aboveLeftX_uid272_pT2_uid134_invPolyEval_b <= STD_LOGIC_VECTOR(nx_mergedSignalTM_uid252_pT2_uid134_invPolyEval_q(14 downto 7));
-- sm0_uid316_pT2_uid134_invPolyEval(MULT,315)@4 + 2
sm0_uid316_pT2_uid134_invPolyEval_a0 <= STD_LOGIC_VECTOR(aboveLeftX_uid272_pT2_uid134_invPolyEval_b);
sm0_uid316_pT2_uid134_invPolyEval_b0 <= '0' & aboveLeftY_mergedSignalTM_uid275_pT2_uid134_invPolyEval_q;
sm0_uid316_pT2_uid134_invPolyEval_reset <= areset;
sm0_uid316_pT2_uid134_invPolyEval_component : lpm_mult
GENERIC MAP (
lpm_widtha => 8,
lpm_widthb => 9,
lpm_widthp => 17,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid316_pT2_uid134_invPolyEval_a0,
datab => sm0_uid316_pT2_uid134_invPolyEval_b0,
clken => VCC_q(0),
aclr => sm0_uid316_pT2_uid134_invPolyEval_reset,
clock => clk,
result => sm0_uid316_pT2_uid134_invPolyEval_s1
);
sm0_uid316_pT2_uid134_invPolyEval_q <= sm0_uid316_pT2_uid134_invPolyEval_s1(15 downto 0);
-- topRangeY_uid266_pT2_uid134_invPolyEval(BITSELECT,265)@4
topRangeY_uid266_pT2_uid134_invPolyEval_b <= STD_LOGIC_VECTOR(s1_uid132_invPolyEval_b(22 downto 6));
-- topRangeX_mergedSignalTM_uid264_pT2_uid134_invPolyEval(BITJOIN,263)@4
topRangeX_mergedSignalTM_uid264_pT2_uid134_invPolyEval_q <= nx_mergedSignalTM_uid252_pT2_uid134_invPolyEval_q & oFracXSE_bottomExtension_uid61_fpDivTest_q;
-- sm0_uid315_pT2_uid134_invPolyEval(MULT,314)@4 + 2
sm0_uid315_pT2_uid134_invPolyEval_a0 <= STD_LOGIC_VECTOR(topRangeX_mergedSignalTM_uid264_pT2_uid134_invPolyEval_q);
sm0_uid315_pT2_uid134_invPolyEval_b0 <= STD_LOGIC_VECTOR(topRangeY_uid266_pT2_uid134_invPolyEval_b);
sm0_uid315_pT2_uid134_invPolyEval_reset <= areset;
sm0_uid315_pT2_uid134_invPolyEval_component : lpm_mult
GENERIC MAP (
lpm_widtha => 17,
lpm_widthb => 17,
lpm_widthp => 34,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid315_pT2_uid134_invPolyEval_a0,
datab => sm0_uid315_pT2_uid134_invPolyEval_b0,
clken => VCC_q(0),
aclr => sm0_uid315_pT2_uid134_invPolyEval_reset,
clock => clk,
result => sm0_uid315_pT2_uid134_invPolyEval_s1
);
sm0_uid315_pT2_uid134_invPolyEval_q <= sm0_uid315_pT2_uid134_invPolyEval_s1;
-- highABits_uid319_pT2_uid134_invPolyEval(BITSELECT,318)@6
highABits_uid319_pT2_uid134_invPolyEval_b <= STD_LOGIC_VECTOR(sm0_uid315_pT2_uid134_invPolyEval_q(33 downto 1));
-- lev1_a0high_uid320_pT2_uid134_invPolyEval(ADD,319)@6
lev1_a0high_uid320_pT2_uid134_invPolyEval_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((33 downto 33 => highABits_uid319_pT2_uid134_invPolyEval_b(32)) & highABits_uid319_pT2_uid134_invPolyEval_b));
lev1_a0high_uid320_pT2_uid134_invPolyEval_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((33 downto 16 => sm0_uid316_pT2_uid134_invPolyEval_q(15)) & sm0_uid316_pT2_uid134_invPolyEval_q));
lev1_a0high_uid320_pT2_uid134_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0high_uid320_pT2_uid134_invPolyEval_a) + SIGNED(lev1_a0high_uid320_pT2_uid134_invPolyEval_b));
lev1_a0high_uid320_pT2_uid134_invPolyEval_q <= lev1_a0high_uid320_pT2_uid134_invPolyEval_o(33 downto 0);
-- lowRangeA_uid318_pT2_uid134_invPolyEval(BITSELECT,317)@6
lowRangeA_uid318_pT2_uid134_invPolyEval_in <= sm0_uid315_pT2_uid134_invPolyEval_q(0 downto 0);
lowRangeA_uid318_pT2_uid134_invPolyEval_b <= lowRangeA_uid318_pT2_uid134_invPolyEval_in(0 downto 0);
-- lev1_a0_uid321_pT2_uid134_invPolyEval(BITJOIN,320)@6
lev1_a0_uid321_pT2_uid134_invPolyEval_q <= lev1_a0high_uid320_pT2_uid134_invPolyEval_q & lowRangeA_uid318_pT2_uid134_invPolyEval_b;
-- highABits_uid323_pT2_uid134_invPolyEval(BITSELECT,322)@6
highABits_uid323_pT2_uid134_invPolyEval_b <= STD_LOGIC_VECTOR(lev1_a0_uid321_pT2_uid134_invPolyEval_q(34 downto 3));
-- lev2_a0high_uid324_pT2_uid134_invPolyEval(ADD,323)@6
lev2_a0high_uid324_pT2_uid134_invPolyEval_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((33 downto 32 => highABits_uid323_pT2_uid134_invPolyEval_b(31)) & highABits_uid323_pT2_uid134_invPolyEval_b));
lev2_a0high_uid324_pT2_uid134_invPolyEval_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "000000000000000000000000000" & sm0_uid317_pT2_uid134_invPolyEval_q));
lev2_a0high_uid324_pT2_uid134_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(lev2_a0high_uid324_pT2_uid134_invPolyEval_a) + SIGNED(lev2_a0high_uid324_pT2_uid134_invPolyEval_b));
lev2_a0high_uid324_pT2_uid134_invPolyEval_q <= lev2_a0high_uid324_pT2_uid134_invPolyEval_o(32 downto 0);
-- lowRangeA_uid322_pT2_uid134_invPolyEval(BITSELECT,321)@6
lowRangeA_uid322_pT2_uid134_invPolyEval_in <= lev1_a0_uid321_pT2_uid134_invPolyEval_q(2 downto 0);
lowRangeA_uid322_pT2_uid134_invPolyEval_b <= lowRangeA_uid322_pT2_uid134_invPolyEval_in(2 downto 0);
-- lev2_a0_uid325_pT2_uid134_invPolyEval(BITJOIN,324)@6
lev2_a0_uid325_pT2_uid134_invPolyEval_q <= lev2_a0high_uid324_pT2_uid134_invPolyEval_q & lowRangeA_uid322_pT2_uid134_invPolyEval_b;
-- osig_uid326_pT2_uid134_invPolyEval(BITSELECT,325)@6
osig_uid326_pT2_uid134_invPolyEval_in <= STD_LOGIC_VECTOR(lev2_a0_uid325_pT2_uid134_invPolyEval_q(32 downto 0));
osig_uid326_pT2_uid134_invPolyEval_b <= STD_LOGIC_VECTOR(osig_uid326_pT2_uid134_invPolyEval_in(32 downto 8));
-- redist5_yAddr_uid51_fpDivTest_b_4(DELAY,340)
redist5_yAddr_uid51_fpDivTest_b_4 : dspba_delay
GENERIC MAP ( width => 9, depth => 2, reset_kind => "ASYNC" )
PORT MAP ( xin => redist4_yAddr_uid51_fpDivTest_b_2_q, xout => redist5_yAddr_uid51_fpDivTest_b_4_q, clk => clk, aclr => areset );
-- memoryC0_uid113_invTables_lutmem(DUALMEM,328)@4 + 2
memoryC0_uid113_invTables_lutmem_aa <= redist5_yAddr_uid51_fpDivTest_b_4_q;
memoryC0_uid113_invTables_lutmem_reset0 <= areset;
memoryC0_uid113_invTables_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M9K",
operation_mode => "ROM",
width_a => 13,
widthad_a => 9,
numwords_a => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
outdata_reg_a => "CLOCK0",
outdata_aclr_a => "CLEAR0",
clock_enable_input_a => "NORMAL",
power_up_uninitialized => "FALSE",
init_file => "fp_div_0002_memoryC0_uid113_invTables_lutmem.hex",
init_file_layout => "PORT_A",
intended_device_family => "MAX 10"
)
PORT MAP (
clocken0 => VCC_q(0),
aclr0 => memoryC0_uid113_invTables_lutmem_reset0,
clock0 => clk,
address_a => memoryC0_uid113_invTables_lutmem_aa,
q_a => memoryC0_uid113_invTables_lutmem_ir
);
memoryC0_uid113_invTables_lutmem_r <= memoryC0_uid113_invTables_lutmem_ir(12 downto 0);
-- memoryC0_uid112_invTables_lutmem(DUALMEM,327)@4 + 2
memoryC0_uid112_invTables_lutmem_aa <= redist5_yAddr_uid51_fpDivTest_b_4_q;
memoryC0_uid112_invTables_lutmem_reset0 <= areset;
memoryC0_uid112_invTables_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M9K",
operation_mode => "ROM",
width_a => 18,
widthad_a => 9,
numwords_a => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
outdata_reg_a => "CLOCK0",
outdata_aclr_a => "CLEAR0",
clock_enable_input_a => "NORMAL",
power_up_uninitialized => "FALSE",
init_file => "fp_div_0002_memoryC0_uid112_invTables_lutmem.hex",
init_file_layout => "PORT_A",
intended_device_family => "MAX 10"
)
PORT MAP (
clocken0 => VCC_q(0),
aclr0 => memoryC0_uid112_invTables_lutmem_reset0,
clock0 => clk,
address_a => memoryC0_uid112_invTables_lutmem_aa,
q_a => memoryC0_uid112_invTables_lutmem_ir
);
memoryC0_uid112_invTables_lutmem_r <= memoryC0_uid112_invTables_lutmem_ir(17 downto 0);
-- os_uid114_invTables(BITJOIN,113)@6
os_uid114_invTables_q <= memoryC0_uid113_invTables_lutmem_r & memoryC0_uid112_invTables_lutmem_r;
-- rndBit_uid135_invPolyEval(CONSTANT,134)
rndBit_uid135_invPolyEval_q <= "001";
-- cIncludingRoundingBit_uid136_invPolyEval(BITJOIN,135)@6
cIncludingRoundingBit_uid136_invPolyEval_q <= os_uid114_invTables_q & rndBit_uid135_invPolyEval_q;
-- ts2_uid138_invPolyEval(ADD,137)@6
ts2_uid138_invPolyEval_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((34 downto 34 => cIncludingRoundingBit_uid136_invPolyEval_q(33)) & cIncludingRoundingBit_uid136_invPolyEval_q));
ts2_uid138_invPolyEval_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((34 downto 25 => osig_uid326_pT2_uid134_invPolyEval_b(24)) & osig_uid326_pT2_uid134_invPolyEval_b));
ts2_uid138_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid138_invPolyEval_a) + SIGNED(ts2_uid138_invPolyEval_b));
ts2_uid138_invPolyEval_q <= ts2_uid138_invPolyEval_o(34 downto 0);
-- s2_uid139_invPolyEval(BITSELECT,138)@6
s2_uid139_invPolyEval_b <= STD_LOGIC_VECTOR(ts2_uid138_invPolyEval_q(34 downto 1));
-- invY_uid54_fpDivTest_merged_bit_select(BITSELECT,332)@6
invY_uid54_fpDivTest_merged_bit_select_in <= s2_uid139_invPolyEval_b(31 downto 0);
invY_uid54_fpDivTest_merged_bit_select_b <= invY_uid54_fpDivTest_merged_bit_select_in(30 downto 5);
invY_uid54_fpDivTest_merged_bit_select_c <= invY_uid54_fpDivTest_merged_bit_select_in(31 downto 31);
-- aboveLeftX_uid170_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,169)@6
aboveLeftX_uid170_prodDivPreNormProd_uid60_fpDivTest_in <= invY_uid54_fpDivTest_merged_bit_select_b(7 downto 0);
aboveLeftX_uid170_prodDivPreNormProd_uid60_fpDivTest_b <= aboveLeftX_uid170_prodDivPreNormProd_uid60_fpDivTest_in(7 downto 3);
-- n0_uid179_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,178)@6
n0_uid179_prodDivPreNormProd_uid60_fpDivTest_b <= aboveLeftX_uid170_prodDivPreNormProd_uid60_fpDivTest_b(4 downto 1);
-- n0_uid187_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,186)@6
n0_uid187_prodDivPreNormProd_uid60_fpDivTest_b <= n0_uid179_prodDivPreNormProd_uid60_fpDivTest_b(3 downto 1);
-- n0_uid195_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,194)@6
n0_uid195_prodDivPreNormProd_uid60_fpDivTest_b <= n0_uid187_prodDivPreNormProd_uid60_fpDivTest_b(2 downto 1);
-- sm1_uid211_prodDivPreNormProd_uid60_fpDivTest(MULT,210)@6 + 2
sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_a0 <= n0_uid195_prodDivPreNormProd_uid60_fpDivTest_b;
sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_b0 <= n1_uid196_prodDivPreNormProd_uid60_fpDivTest_b;
sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_reset <= areset;
sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 2,
lpm_widthb => 2,
lpm_widthp => 4,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=NO, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_a0,
datab => sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_b0,
clken => VCC_q(0),
aclr => sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_reset,
clock => clk,
result => sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_s1
);
sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_q <= sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_s1;
-- lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest(ADD,219)@8
lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_a <= STD_LOGIC_VECTOR("0" & lowRangeA_uid218_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_c);
lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000" & sm1_uid211_prodDivPreNormProd_uid60_fpDivTest_q);
lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_o <= STD_LOGIC_VECTOR(UNSIGNED(lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_a) + UNSIGNED(lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_b));
lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_q <= lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_o(33 downto 0);
-- rightBottomY_uid169_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,168)@6
rightBottomY_uid169_prodDivPreNormProd_uid60_fpDivTest_in <= lOAdded_uid58_fpDivTest_q(5 downto 0);
rightBottomY_uid169_prodDivPreNormProd_uid60_fpDivTest_b <= rightBottomY_uid169_prodDivPreNormProd_uid60_fpDivTest_in(5 downto 1);
-- n1_uid178_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,177)@6
n1_uid178_prodDivPreNormProd_uid60_fpDivTest_b <= rightBottomY_uid169_prodDivPreNormProd_uid60_fpDivTest_b(4 downto 1);
-- n1_uid186_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,185)@6
n1_uid186_prodDivPreNormProd_uid60_fpDivTest_b <= n1_uid178_prodDivPreNormProd_uid60_fpDivTest_b(3 downto 1);
-- n1_uid194_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,193)@6
n1_uid194_prodDivPreNormProd_uid60_fpDivTest_b <= n1_uid186_prodDivPreNormProd_uid60_fpDivTest_b(2 downto 1);
-- rightBottomX_uid168_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,167)@6
rightBottomX_uid168_prodDivPreNormProd_uid60_fpDivTest_in <= invY_uid54_fpDivTest_merged_bit_select_b(16 downto 0);
rightBottomX_uid168_prodDivPreNormProd_uid60_fpDivTest_b <= rightBottomX_uid168_prodDivPreNormProd_uid60_fpDivTest_in(16 downto 12);
-- n0_uid177_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,176)@6
n0_uid177_prodDivPreNormProd_uid60_fpDivTest_b <= rightBottomX_uid168_prodDivPreNormProd_uid60_fpDivTest_b(4 downto 1);
-- n0_uid185_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,184)@6
n0_uid185_prodDivPreNormProd_uid60_fpDivTest_b <= n0_uid177_prodDivPreNormProd_uid60_fpDivTest_b(3 downto 1);
-- n0_uid193_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,192)@6
n0_uid193_prodDivPreNormProd_uid60_fpDivTest_b <= n0_uid185_prodDivPreNormProd_uid60_fpDivTest_b(2 downto 1);
-- sm0_uid210_prodDivPreNormProd_uid60_fpDivTest(MULT,209)@6 + 2
sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_a0 <= n0_uid193_prodDivPreNormProd_uid60_fpDivTest_b;
sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_b0 <= n1_uid194_prodDivPreNormProd_uid60_fpDivTest_b;
sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_reset <= areset;
sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 2,
lpm_widthb => 2,
lpm_widthp => 4,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=NO, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_a0,
datab => sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_b0,
clken => VCC_q(0),
aclr => sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_reset,
clock => clk,
result => sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_s1
);
sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_q <= sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_s1;
-- lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest(ADD,214)@8
lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_a <= STD_LOGIC_VECTOR("0" & lowRangeA_uid213_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_c);
lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_b <= STD_LOGIC_VECTOR("0000000000" & sm0_uid210_prodDivPreNormProd_uid60_fpDivTest_q);
lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_o <= STD_LOGIC_VECTOR(UNSIGNED(lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_a) + UNSIGNED(lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_b));
lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_q <= lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_o(13 downto 0);
-- rightBottomY_uid164_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,163)@6
rightBottomY_uid164_prodDivPreNormProd_uid60_fpDivTest_b <= lOAdded_uid58_fpDivTest_q(23 downto 15);
-- rightBottomX_bottomRange_uid161_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,160)@6
rightBottomX_bottomRange_uid161_prodDivPreNormProd_uid60_fpDivTest_in <= invY_uid54_fpDivTest_merged_bit_select_b(7 downto 0);
rightBottomX_bottomRange_uid161_prodDivPreNormProd_uid60_fpDivTest_b <= rightBottomX_bottomRange_uid161_prodDivPreNormProd_uid60_fpDivTest_in(7 downto 0);
-- rightBottomX_mergedSignalTM_uid162_prodDivPreNormProd_uid60_fpDivTest(BITJOIN,161)@6
rightBottomX_mergedSignalTM_uid162_prodDivPreNormProd_uid60_fpDivTest_q <= rightBottomX_bottomRange_uid161_prodDivPreNormProd_uid60_fpDivTest_b & GND_q;
-- sm1_uid209_prodDivPreNormProd_uid60_fpDivTest(MULT,208)@6 + 2
sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_a0 <= rightBottomX_mergedSignalTM_uid162_prodDivPreNormProd_uid60_fpDivTest_q;
sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_b0 <= rightBottomY_uid164_prodDivPreNormProd_uid60_fpDivTest_b;
sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_reset <= areset;
sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 9,
lpm_widthb => 9,
lpm_widthp => 18,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_a0,
datab => sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_b0,
clken => VCC_q(0),
aclr => sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_reset,
clock => clk,
result => sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_s1
);
sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_q <= sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_s1;
-- lowRangeA_uid213_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select(BITSELECT,333)@8
lowRangeA_uid213_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_b <= sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_q(4 downto 0);
lowRangeA_uid213_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_c <= sm1_uid209_prodDivPreNormProd_uid60_fpDivTest_q(17 downto 5);
-- lev1_a1_uid216_prodDivPreNormProd_uid60_fpDivTest(BITJOIN,215)@8
lev1_a1_uid216_prodDivPreNormProd_uid60_fpDivTest_q <= lev1_a1high_uid215_prodDivPreNormProd_uid60_fpDivTest_q & lowRangeA_uid213_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_b;
-- aboveLeftY_bottomRange_uid157_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,156)@6
aboveLeftY_bottomRange_uid157_prodDivPreNormProd_uid60_fpDivTest_in <= lOAdded_uid58_fpDivTest_q(5 downto 0);
aboveLeftY_bottomRange_uid157_prodDivPreNormProd_uid60_fpDivTest_b <= aboveLeftY_bottomRange_uid157_prodDivPreNormProd_uid60_fpDivTest_in(5 downto 0);
-- aboveLeftY_bottomExtension_uid156_prodDivPreNormProd_uid60_fpDivTest(CONSTANT,155)
aboveLeftY_bottomExtension_uid156_prodDivPreNormProd_uid60_fpDivTest_q <= "000";
-- aboveLeftY_mergedSignalTM_uid158_prodDivPreNormProd_uid60_fpDivTest(BITJOIN,157)@6
aboveLeftY_mergedSignalTM_uid158_prodDivPreNormProd_uid60_fpDivTest_q <= aboveLeftY_bottomRange_uid157_prodDivPreNormProd_uid60_fpDivTest_b & aboveLeftY_bottomExtension_uid156_prodDivPreNormProd_uid60_fpDivTest_q;
-- aboveLeftX_uid155_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,154)@6
aboveLeftX_uid155_prodDivPreNormProd_uid60_fpDivTest_b <= invY_uid54_fpDivTest_merged_bit_select_b(25 downto 17);
-- sm0_uid208_prodDivPreNormProd_uid60_fpDivTest(MULT,207)@6 + 2
sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_a0 <= aboveLeftX_uid155_prodDivPreNormProd_uid60_fpDivTest_b;
sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_b0 <= aboveLeftY_mergedSignalTM_uid158_prodDivPreNormProd_uid60_fpDivTest_q;
sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_reset <= areset;
sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 9,
lpm_widthb => 9,
lpm_widthp => 18,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_a0,
datab => sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_b0,
clken => VCC_q(0),
aclr => sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_reset,
clock => clk,
result => sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_s1
);
sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_q <= sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_s1;
-- topRangeY_uid150_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,149)@6
topRangeY_uid150_prodDivPreNormProd_uid60_fpDivTest_b <= lOAdded_uid58_fpDivTest_q(23 downto 6);
-- topRangeX_uid149_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,148)@6
topRangeX_uid149_prodDivPreNormProd_uid60_fpDivTest_b <= invY_uid54_fpDivTest_merged_bit_select_b(25 downto 8);
-- sm0_uid207_prodDivPreNormProd_uid60_fpDivTest(MULT,206)@6 + 2
sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_a0 <= topRangeX_uid149_prodDivPreNormProd_uid60_fpDivTest_b;
sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_b0 <= topRangeY_uid150_prodDivPreNormProd_uid60_fpDivTest_b;
sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_reset <= areset;
sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_component : lpm_mult
GENERIC MAP (
lpm_widtha => 18,
lpm_widthb => 18,
lpm_widthp => 36,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "UNSIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES, MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_a0,
datab => sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_b0,
clken => VCC_q(0),
aclr => sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_reset,
clock => clk,
result => sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_s1
);
sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_q <= sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_s1;
-- lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest(ADD,211)@8
lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_a <= STD_LOGIC_VECTOR("0" & sm0_uid207_prodDivPreNormProd_uid60_fpDivTest_q);
lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_b <= STD_LOGIC_VECTOR("0000000000000000000" & sm0_uid208_prodDivPreNormProd_uid60_fpDivTest_q);
lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_o <= STD_LOGIC_VECTOR(UNSIGNED(lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_a) + UNSIGNED(lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_b));
lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_q <= lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_o(36 downto 0);
-- lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest(ADD,216)@8
lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_a <= STD_LOGIC_VECTOR("0" & lev1_a0_uid212_prodDivPreNormProd_uid60_fpDivTest_q);
lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_b <= STD_LOGIC_VECTOR("0000000000000000000" & lev1_a1_uid216_prodDivPreNormProd_uid60_fpDivTest_q);
lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_o <= STD_LOGIC_VECTOR(UNSIGNED(lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_a) + UNSIGNED(lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_b));
lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_q <= lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_o(37 downto 0);
-- lowRangeA_uid218_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select(BITSELECT,334)@8
lowRangeA_uid218_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_b <= lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_q(4 downto 0);
lowRangeA_uid218_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_c <= lev2_a0_uid217_prodDivPreNormProd_uid60_fpDivTest_q(37 downto 5);
-- lev3_a0_uid221_prodDivPreNormProd_uid60_fpDivTest(BITJOIN,220)@8
lev3_a0_uid221_prodDivPreNormProd_uid60_fpDivTest_q <= lev3_a0high_uid220_prodDivPreNormProd_uid60_fpDivTest_q & lowRangeA_uid218_prodDivPreNormProd_uid60_fpDivTest_merged_bit_select_b;
-- osig_uid222_prodDivPreNormProd_uid60_fpDivTest(BITSELECT,221)@8
osig_uid222_prodDivPreNormProd_uid60_fpDivTest_in <= lev3_a0_uid221_prodDivPreNormProd_uid60_fpDivTest_q(35 downto 0);
osig_uid222_prodDivPreNormProd_uid60_fpDivTest_b <= osig_uid222_prodDivPreNormProd_uid60_fpDivTest_in(35 downto 9);
-- divValPreNormS_uid65_fpDivTest(BITSELECT,64)@8
divValPreNormS_uid65_fpDivTest_b <= osig_uid222_prodDivPreNormProd_uid60_fpDivTest_b(26 downto 1);
-- updatedY_uid16_fpDivTest(BITJOIN,15)@0
updatedY_uid16_fpDivTest_q <= GND_q & paddingY_uid15_fpDivTest_q;
-- fracYZero_uid15_fpDivTest(LOGICAL,16)@0 + 1
fracYZero_uid15_fpDivTest_a <= STD_LOGIC_VECTOR("0" & fracY_uid13_fpDivTest_b);
fracYZero_uid15_fpDivTest_qi <= "1" WHEN fracYZero_uid15_fpDivTest_a = updatedY_uid16_fpDivTest_q ELSE "0";
fracYZero_uid15_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracYZero_uid15_fpDivTest_qi, xout => fracYZero_uid15_fpDivTest_q, clk => clk, aclr => areset );
-- redist14_fracYZero_uid15_fpDivTest_q_6(DELAY,349)
redist14_fracYZero_uid15_fpDivTest_q_6 : dspba_delay
GENERIC MAP ( width => 1, depth => 5, reset_kind => "ASYNC" )
PORT MAP ( xin => fracYZero_uid15_fpDivTest_q, xout => redist14_fracYZero_uid15_fpDivTest_q_6_q, clk => clk, aclr => areset );
-- fracYPostZ_uid56_fpDivTest(LOGICAL,55)@6 + 1
fracYPostZ_uid56_fpDivTest_qi <= redist14_fracYZero_uid15_fpDivTest_q_6_q or invY_uid54_fpDivTest_merged_bit_select_c;
fracYPostZ_uid56_fpDivTest_delay : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracYPostZ_uid56_fpDivTest_qi, xout => fracYPostZ_uid56_fpDivTest_q, clk => clk, aclr => areset );
-- redist1_fracYPostZ_uid56_fpDivTest_q_2(DELAY,336)
redist1_fracYPostZ_uid56_fpDivTest_q_2 : dspba_delay
GENERIC MAP ( width => 1, depth => 1, reset_kind => "ASYNC" )
PORT MAP ( xin => fracYPostZ_uid56_fpDivTest_q, xout => redist1_fracYPostZ_uid56_fpDivTest_q_2_q, clk => clk, aclr => areset );
-- divValPreNormTrunc_uid66_fpDivTest(MUX,65)@8
divValPreNormTrunc_uid66_fpDivTest_s <= redist1_fracYPostZ_uid56_fpDivTest_q_2_q;
divValPreNormTrunc_uid66_fpDivTest_combproc: PROCESS (divValPreNormTrunc_uid66_fpDivTest_s, divValPreNormS_uid65_fpDivTest_b, oFracXSE_mergedSignalTM_uid63_fpDivTest_q)
BEGIN
CASE (divValPreNormTrunc_uid66_fpDivTest_s) IS
WHEN "0" => divValPreNormTrunc_uid66_fpDivTest_q <= divValPreNormS_uid65_fpDivTest_b;
WHEN "1" => divValPreNormTrunc_uid66_fpDivTest_q <= oFracXSE_mergedSignalTM_uid63_fpDivTest_q;
WHEN OTHERS => divValPreNormTrunc_uid66_fpDivTest_q <= (others => '0');
END CASE;
END PROCESS;
-- norm_uid67_fpDivTest(BITSELECT,66)@8
norm_uid67_fpDivTest_b <= STD_LOGIC_VECTOR(divValPreNormTrunc_uid66_fpDivTest_q(25 downto 25));
-- rndOp_uid75_fpDivTest(BITJOIN,74)@8
rndOp_uid75_fpDivTest_q <= norm_uid67_fpDivTest_b & paddingY_uid15_fpDivTest_q & VCC_q;
-- cstBiasM1_uid6_fpDivTest(CONSTANT,5)
cstBiasM1_uid6_fpDivTest_q <= "01111110";
-- expXmY_uid47_fpDivTest(SUB,46)@0 + 1
expXmY_uid47_fpDivTest_a <= STD_LOGIC_VECTOR("0" & expX_uid9_fpDivTest_b);
expXmY_uid47_fpDivTest_b <= STD_LOGIC_VECTOR("0" & expY_uid12_fpDivTest_b);
expXmY_uid47_fpDivTest_clkproc: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXmY_uid47_fpDivTest_o <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
expXmY_uid47_fpDivTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXmY_uid47_fpDivTest_a) - UNSIGNED(expXmY_uid47_fpDivTest_b));
END IF;
END PROCESS;
expXmY_uid47_fpDivTest_q <= expXmY_uid47_fpDivTest_o(8 downto 0);
-- redist6_expXmY_uid47_fpDivTest_q_8(DELAY,341)
redist6_expXmY_uid47_fpDivTest_q_8 : dspba_delay
GENERIC MAP ( width => 9, depth => 7, reset_kind => "ASYNC" )
PORT MAP ( xin => expXmY_uid47_fpDivTest_q, xout => redist6_expXmY_uid47_fpDivTest_q_8_q, clk => clk, aclr => areset );
-- expR_uid48_fpDivTest(ADD,47)@8
expR_uid48_fpDivTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((10 downto 9 => redist6_expXmY_uid47_fpDivTest_q_8_q(8)) & redist6_expXmY_uid47_fpDivTest_q_8_q));
expR_uid48_fpDivTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "00" & cstBiasM1_uid6_fpDivTest_q));
expR_uid48_fpDivTest_o <= STD_LOGIC_VECTOR(SIGNED(expR_uid48_fpDivTest_a) + SIGNED(expR_uid48_fpDivTest_b));
expR_uid48_fpDivTest_q <= expR_uid48_fpDivTest_o(9 downto 0);
-- divValPreNormHigh_uid68_fpDivTest(BITSELECT,67)@8
divValPreNormHigh_uid68_fpDivTest_in <= divValPreNormTrunc_uid66_fpDivTest_q(24 downto 0);
divValPreNormHigh_uid68_fpDivTest_b <= divValPreNormHigh_uid68_fpDivTest_in(24 downto 1);
-- divValPreNormLow_uid69_fpDivTest(BITSELECT,68)@8
divValPreNormLow_uid69_fpDivTest_in <= divValPreNormTrunc_uid66_fpDivTest_q(23 downto 0);
divValPreNormLow_uid69_fpDivTest_b <= divValPreNormLow_uid69_fpDivTest_in(23 downto 0);
-- normFracRnd_uid70_fpDivTest(MUX,69)@8
normFracRnd_uid70_fpDivTest_s <= norm_uid67_fpDivTest_b;
normFracRnd_uid70_fpDivTest_combproc: PROCESS (normFracRnd_uid70_fpDivTest_s, divValPreNormLow_uid69_fpDivTest_b, divValPreNormHigh_uid68_fpDivTest_b)
BEGIN
CASE (normFracRnd_uid70_fpDivTest_s) IS
WHEN "0" => normFracRnd_uid70_fpDivTest_q <= divValPreNormLow_uid69_fpDivTest_b;
WHEN "1" => normFracRnd_uid70_fpDivTest_q <= divValPreNormHigh_uid68_fpDivTest_b;
WHEN OTHERS => normFracRnd_uid70_fpDivTest_q <= (others => '0');
END CASE;
END PROCESS;
-- expFracRnd_uid71_fpDivTest(BITJOIN,70)@8
expFracRnd_uid71_fpDivTest_q <= expR_uid48_fpDivTest_q & normFracRnd_uid70_fpDivTest_q;
-- expFracPostRnd_uid76_fpDivTest(ADD,75)@8
expFracPostRnd_uid76_fpDivTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((35 downto 34 => expFracRnd_uid71_fpDivTest_q(33)) & expFracRnd_uid71_fpDivTest_q));
expFracPostRnd_uid76_fpDivTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "0000000000" & rndOp_uid75_fpDivTest_q));
expFracPostRnd_uid76_fpDivTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracPostRnd_uid76_fpDivTest_a) + SIGNED(expFracPostRnd_uid76_fpDivTest_b));
expFracPostRnd_uid76_fpDivTest_q <= expFracPostRnd_uid76_fpDivTest_o(34 downto 0);
-- excRPreExc_uid79_fpDivTest(BITSELECT,78)@8
excRPreExc_uid79_fpDivTest_in <= expFracPostRnd_uid76_fpDivTest_q(31 downto 0);
excRPreExc_uid79_fpDivTest_b <= excRPreExc_uid79_fpDivTest_in(31 downto 24);
-- invExpXIsMax_uid43_fpDivTest(LOGICAL,42)@8
invExpXIsMax_uid43_fpDivTest_q <= not (redist9_expXIsMax_uid38_fpDivTest_q_8_q);
-- InvExpXIsZero_uid44_fpDivTest(LOGICAL,43)@8
InvExpXIsZero_uid44_fpDivTest_q <= not (redist10_excZ_y_uid37_fpDivTest_q_8_q);
-- excR_y_uid45_fpDivTest(LOGICAL,44)@8
excR_y_uid45_fpDivTest_q <= InvExpXIsZero_uid44_fpDivTest_q and invExpXIsMax_uid43_fpDivTest_q;
-- excXIYR_uid93_fpDivTest(LOGICAL,92)@8
excXIYR_uid93_fpDivTest_q <= excI_x_uid27_fpDivTest_q and excR_y_uid45_fpDivTest_q;
-- excXIYZ_uid92_fpDivTest(LOGICAL,91)@8
excXIYZ_uid92_fpDivTest_q <= excI_x_uid27_fpDivTest_q and redist10_excZ_y_uid37_fpDivTest_q_8_q;
-- expRExt_uid80_fpDivTest(BITSELECT,79)@8
expRExt_uid80_fpDivTest_b <= STD_LOGIC_VECTOR(expFracPostRnd_uid76_fpDivTest_q(34 downto 24));
-- expOvf_uid84_fpDivTest(COMPARE,83)@8
expOvf_uid84_fpDivTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((12 downto 11 => expRExt_uid80_fpDivTest_b(10)) & expRExt_uid80_fpDivTest_b));
expOvf_uid84_fpDivTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "0000" & cstAllOWE_uid18_fpDivTest_q));
expOvf_uid84_fpDivTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid84_fpDivTest_a) - SIGNED(expOvf_uid84_fpDivTest_b));
expOvf_uid84_fpDivTest_n(0) <= not (expOvf_uid84_fpDivTest_o(12));
-- invExpXIsMax_uid29_fpDivTest(LOGICAL,28)@8
invExpXIsMax_uid29_fpDivTest_q <= not (redist12_expXIsMax_uid24_fpDivTest_q_8_q);
-- InvExpXIsZero_uid30_fpDivTest(LOGICAL,29)@8
InvExpXIsZero_uid30_fpDivTest_q <= not (redist13_excZ_x_uid23_fpDivTest_q_8_q);
-- excR_x_uid31_fpDivTest(LOGICAL,30)@8
excR_x_uid31_fpDivTest_q <= InvExpXIsZero_uid30_fpDivTest_q and invExpXIsMax_uid29_fpDivTest_q;
-- excXRYROvf_uid91_fpDivTest(LOGICAL,90)@8
excXRYROvf_uid91_fpDivTest_q <= excR_x_uid31_fpDivTest_q and excR_y_uid45_fpDivTest_q and expOvf_uid84_fpDivTest_n;
-- excXRYZ_uid90_fpDivTest(LOGICAL,89)@8
excXRYZ_uid90_fpDivTest_q <= excR_x_uid31_fpDivTest_q and redist10_excZ_y_uid37_fpDivTest_q_8_q;
-- excRInf_uid94_fpDivTest(LOGICAL,93)@8
excRInf_uid94_fpDivTest_q <= excXRYZ_uid90_fpDivTest_q or excXRYROvf_uid91_fpDivTest_q or excXIYZ_uid92_fpDivTest_q or excXIYR_uid93_fpDivTest_q;
-- xRegOrZero_uid87_fpDivTest(LOGICAL,86)@8
xRegOrZero_uid87_fpDivTest_q <= excR_x_uid31_fpDivTest_q or redist13_excZ_x_uid23_fpDivTest_q_8_q;
-- regOrZeroOverInf_uid88_fpDivTest(LOGICAL,87)@8
regOrZeroOverInf_uid88_fpDivTest_q <= xRegOrZero_uid87_fpDivTest_q and excI_y_uid41_fpDivTest_q;
-- expUdf_uid81_fpDivTest(COMPARE,80)@8
expUdf_uid81_fpDivTest_a <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR("0" & "00000000000" & GND_q));
expUdf_uid81_fpDivTest_b <= STD_LOGIC_VECTOR(STD_LOGIC_VECTOR((12 downto 11 => expRExt_uid80_fpDivTest_b(10)) & expRExt_uid80_fpDivTest_b));
expUdf_uid81_fpDivTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid81_fpDivTest_a) - SIGNED(expUdf_uid81_fpDivTest_b));
expUdf_uid81_fpDivTest_n(0) <= not (expUdf_uid81_fpDivTest_o(12));
-- regOverRegWithUf_uid86_fpDivTest(LOGICAL,85)@8
regOverRegWithUf_uid86_fpDivTest_q <= expUdf_uid81_fpDivTest_n and excR_x_uid31_fpDivTest_q and excR_y_uid45_fpDivTest_q;
-- zeroOverReg_uid85_fpDivTest(LOGICAL,84)@8
zeroOverReg_uid85_fpDivTest_q <= redist13_excZ_x_uid23_fpDivTest_q_8_q and excR_y_uid45_fpDivTest_q;
-- excRZero_uid89_fpDivTest(LOGICAL,88)@8
excRZero_uid89_fpDivTest_q <= zeroOverReg_uid85_fpDivTest_q or regOverRegWithUf_uid86_fpDivTest_q or regOrZeroOverInf_uid88_fpDivTest_q;
-- concExc_uid98_fpDivTest(BITJOIN,97)@8
concExc_uid98_fpDivTest_q <= excRNaN_uid97_fpDivTest_q & excRInf_uid94_fpDivTest_q & excRZero_uid89_fpDivTest_q;
-- excREnc_uid99_fpDivTest(LOOKUP,98)@8
excREnc_uid99_fpDivTest_combproc: PROCESS (concExc_uid98_fpDivTest_q)
BEGIN
-- Begin reserved scope level
CASE (concExc_uid98_fpDivTest_q) IS
WHEN "000" => excREnc_uid99_fpDivTest_q <= "01";
WHEN "001" => excREnc_uid99_fpDivTest_q <= "00";
WHEN "010" => excREnc_uid99_fpDivTest_q <= "10";
WHEN "011" => excREnc_uid99_fpDivTest_q <= "00";
WHEN "100" => excREnc_uid99_fpDivTest_q <= "11";
WHEN "101" => excREnc_uid99_fpDivTest_q <= "00";
WHEN "110" => excREnc_uid99_fpDivTest_q <= "00";
WHEN "111" => excREnc_uid99_fpDivTest_q <= "00";
WHEN OTHERS => -- unreachable
excREnc_uid99_fpDivTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
-- expRPostExc_uid107_fpDivTest(MUX,106)@8
expRPostExc_uid107_fpDivTest_s <= excREnc_uid99_fpDivTest_q;
expRPostExc_uid107_fpDivTest_combproc: PROCESS (expRPostExc_uid107_fpDivTest_s, cstAllZWE_uid20_fpDivTest_q, excRPreExc_uid79_fpDivTest_b, cstAllOWE_uid18_fpDivTest_q)
BEGIN
CASE (expRPostExc_uid107_fpDivTest_s) IS
WHEN "00" => expRPostExc_uid107_fpDivTest_q <= cstAllZWE_uid20_fpDivTest_q;
WHEN "01" => expRPostExc_uid107_fpDivTest_q <= excRPreExc_uid79_fpDivTest_b;
WHEN "10" => expRPostExc_uid107_fpDivTest_q <= cstAllOWE_uid18_fpDivTest_q;
WHEN "11" => expRPostExc_uid107_fpDivTest_q <= cstAllOWE_uid18_fpDivTest_q;
WHEN OTHERS => expRPostExc_uid107_fpDivTest_q <= (others => '0');
END CASE;
END PROCESS;
-- oneFracRPostExc2_uid100_fpDivTest(CONSTANT,99)
oneFracRPostExc2_uid100_fpDivTest_q <= "00000000000000000000001";
-- fracRPreExc_uid78_fpDivTest(BITSELECT,77)@8
fracRPreExc_uid78_fpDivTest_in <= expFracPostRnd_uid76_fpDivTest_q(23 downto 0);
fracRPreExc_uid78_fpDivTest_b <= fracRPreExc_uid78_fpDivTest_in(23 downto 1);
-- fracRPostExc_uid103_fpDivTest(MUX,102)@8
fracRPostExc_uid103_fpDivTest_s <= excREnc_uid99_fpDivTest_q;
fracRPostExc_uid103_fpDivTest_combproc: PROCESS (fracRPostExc_uid103_fpDivTest_s, paddingY_uid15_fpDivTest_q, fracRPreExc_uid78_fpDivTest_b, oneFracRPostExc2_uid100_fpDivTest_q)
BEGIN
CASE (fracRPostExc_uid103_fpDivTest_s) IS
WHEN "00" => fracRPostExc_uid103_fpDivTest_q <= paddingY_uid15_fpDivTest_q;
WHEN "01" => fracRPostExc_uid103_fpDivTest_q <= fracRPreExc_uid78_fpDivTest_b;
WHEN "10" => fracRPostExc_uid103_fpDivTest_q <= paddingY_uid15_fpDivTest_q;
WHEN "11" => fracRPostExc_uid103_fpDivTest_q <= oneFracRPostExc2_uid100_fpDivTest_q;
WHEN OTHERS => fracRPostExc_uid103_fpDivTest_q <= (others => '0');
END CASE;
END PROCESS;
-- divR_uid110_fpDivTest(BITJOIN,109)@8
divR_uid110_fpDivTest_q <= sRPostExc_uid109_fpDivTest_q & expRPostExc_uid107_fpDivTest_q & fracRPostExc_uid103_fpDivTest_q;
-- xOut(GPOUT,4)@8
q <= divR_uid110_fpDivTest_q;
END normal;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2009.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p10n01i02009ent IS
END c07s02b02x00p10n01i02009ent;
ARCHITECTURE c07s02b02x00p10n01i02009arch OF c07s02b02x00p10n01i02009ent IS
BEGIN
TESTING: PROCESS
type rec_type is
record
i : integer;
end record;
variable j, k : rec_type;
BEGIN
j.i := 2;
k.i := 1;
if (k<j) then -- Failure_here
NULL;
end if;
assert FALSE
report "***FAILED TEST: c07s02b02x00p10n01i02009 - Ordering operators are defined only for scalar type or any discrete array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p10n01i02009arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2009.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p10n01i02009ent IS
END c07s02b02x00p10n01i02009ent;
ARCHITECTURE c07s02b02x00p10n01i02009arch OF c07s02b02x00p10n01i02009ent IS
BEGIN
TESTING: PROCESS
type rec_type is
record
i : integer;
end record;
variable j, k : rec_type;
BEGIN
j.i := 2;
k.i := 1;
if (k<j) then -- Failure_here
NULL;
end if;
assert FALSE
report "***FAILED TEST: c07s02b02x00p10n01i02009 - Ordering operators are defined only for scalar type or any discrete array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p10n01i02009arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2009.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p10n01i02009ent IS
END c07s02b02x00p10n01i02009ent;
ARCHITECTURE c07s02b02x00p10n01i02009arch OF c07s02b02x00p10n01i02009ent IS
BEGIN
TESTING: PROCESS
type rec_type is
record
i : integer;
end record;
variable j, k : rec_type;
BEGIN
j.i := 2;
k.i := 1;
if (k<j) then -- Failure_here
NULL;
end if;
assert FALSE
report "***FAILED TEST: c07s02b02x00p10n01i02009 - Ordering operators are defined only for scalar type or any discrete array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p10n01i02009arch;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/25/2014
--! Module Name: EPROC_IN8_ALIGN_BLOCK
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.all;
use work.centralRouter_package.all;
--! continuously aligns 8bit bit-stream to two commas
entity EPROC_IN8_ALIGN_BLOCK is
port (
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
bytes : in word10b_4array_type;
bytes_rdy : in std_logic;
------------
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
------------
busyOut : out std_logic
);
end EPROC_IN8_ALIGN_BLOCK;
architecture Behavioral of EPROC_IN8_ALIGN_BLOCK is
signal bytes_r : word10b_4array_type := ((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0'));
signal send_state : std_logic := '0';
signal dataOUT_s : std_logic_vector(9 downto 0) := (others => '0');
signal dataOUTrdy_s, bytes_rdy_r : std_logic := '0';
signal byte_count : std_logic_vector(1 downto 0) := "00";
begin
-------------------------------------------------------------------------------------------
-- clock1
-- input register
-------------------------------------------------------------------------------------------
process(bitCLKx2, rst)
begin
if rst = '1' then
bytes_rdy_r <= '0';
elsif rising_edge(bitCLKx2) then
if bytes_rdy = '1' then
bytes_rdy_r <= not bytes_rdy_r;
else
bytes_rdy_r <= '0';
end if;
end if;
end process;
--
input_latch: process(bitCLKx2)
begin
if rising_edge(bitCLKx2) then
if bytes_rdy = '1' then
bytes_r <= bytes;
end if;
end if;
end process;
--
--
process(bitCLKx2, rst)
begin
if rst = '1' then
send_state <= '0';
elsif rising_edge(bitCLKx2) then
if bytes_rdy = '1' then
send_state <= '1';
else
if byte_count = "11" then
send_state <= '0';
end if;
end if;
end if;
end process;
--
process(bitCLKx2)
begin
if rising_edge(bitCLKx2) then
if send_state = '1' then
byte_count <= byte_count + 1;
else
byte_count <= "00";
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------------
process(bitCLKx4)
begin
if rising_edge(bitCLKx4) then
if send_state = '1' then
dataOUTrdy_s <= not dataOUTrdy_s;
else
dataOUTrdy_s <= '0';
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------------
out_select_proc: process(byte_count, bytes_r)
begin
case (byte_count) is
when "00" => dataOUT_s <= bytes_r(0);
when "01" => dataOUT_s <= bytes_r(1);
when "10" => dataOUT_s <= bytes_r(2);
when "11" => dataOUT_s <= bytes_r(3);
when others =>
end case;
end process;
--
-------------------------------------------------------------------------------------------
-- dataOUT_s (@bitCLKx4) & dataOUTrdy_s (@bitCLKx4, 2nd clock) can be used when
-- decoder is moved up
-------------------------------------------------------------------------------------------
dec_8b10: entity work.dec_8b10_wrap
port map(
RESET => rst,
RBYTECLK => bitCLKx4,
ABCDEIFGHJ_IN => dataOUT_s,
HGFEDCBA => dataOUT(7 downto 0),
ISK => dataOUT(9 downto 8),
BUSY => busyOut
);
--
dataOUTrdy <= dataOUTrdy_s;
--
end Behavioral;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/25/2014
--! Module Name: EPROC_IN8_ALIGN_BLOCK
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.all;
use work.centralRouter_package.all;
--! continuously aligns 8bit bit-stream to two commas
entity EPROC_IN8_ALIGN_BLOCK is
port (
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
bytes : in word10b_4array_type;
bytes_rdy : in std_logic;
------------
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic;
------------
busyOut : out std_logic
);
end EPROC_IN8_ALIGN_BLOCK;
architecture Behavioral of EPROC_IN8_ALIGN_BLOCK is
signal bytes_r : word10b_4array_type := ((others=>'0'),(others=>'0'),(others=>'0'),(others=>'0'));
signal send_state : std_logic := '0';
signal dataOUT_s : std_logic_vector(9 downto 0) := (others => '0');
signal dataOUTrdy_s, bytes_rdy_r : std_logic := '0';
signal byte_count : std_logic_vector(1 downto 0) := "00";
begin
-------------------------------------------------------------------------------------------
-- clock1
-- input register
-------------------------------------------------------------------------------------------
process(bitCLKx2, rst)
begin
if rst = '1' then
bytes_rdy_r <= '0';
elsif rising_edge(bitCLKx2) then
if bytes_rdy = '1' then
bytes_rdy_r <= not bytes_rdy_r;
else
bytes_rdy_r <= '0';
end if;
end if;
end process;
--
input_latch: process(bitCLKx2)
begin
if rising_edge(bitCLKx2) then
if bytes_rdy = '1' then
bytes_r <= bytes;
end if;
end if;
end process;
--
--
process(bitCLKx2, rst)
begin
if rst = '1' then
send_state <= '0';
elsif rising_edge(bitCLKx2) then
if bytes_rdy = '1' then
send_state <= '1';
else
if byte_count = "11" then
send_state <= '0';
end if;
end if;
end if;
end process;
--
process(bitCLKx2)
begin
if rising_edge(bitCLKx2) then
if send_state = '1' then
byte_count <= byte_count + 1;
else
byte_count <= "00";
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------------
process(bitCLKx4)
begin
if rising_edge(bitCLKx4) then
if send_state = '1' then
dataOUTrdy_s <= not dataOUTrdy_s;
else
dataOUTrdy_s <= '0';
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------------
out_select_proc: process(byte_count, bytes_r)
begin
case (byte_count) is
when "00" => dataOUT_s <= bytes_r(0);
when "01" => dataOUT_s <= bytes_r(1);
when "10" => dataOUT_s <= bytes_r(2);
when "11" => dataOUT_s <= bytes_r(3);
when others =>
end case;
end process;
--
-------------------------------------------------------------------------------------------
-- dataOUT_s (@bitCLKx4) & dataOUTrdy_s (@bitCLKx4, 2nd clock) can be used when
-- decoder is moved up
-------------------------------------------------------------------------------------------
dec_8b10: entity work.dec_8b10_wrap
port map(
RESET => rst,
RBYTECLK => bitCLKx4,
ABCDEIFGHJ_IN => dataOUT_s,
HGFEDCBA => dataOUT(7 downto 0),
ISK => dataOUT(9 downto 8),
BUSY => busyOut
);
--
dataOUTrdy <= dataOUTrdy_s;
--
end Behavioral;
|
-------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: spectrum_sense.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Specturm sensing by implementing a FFT, magnitude calculation,
-- and threshold detection. The entire pipeline is single
-- precision floating point and based on Xilinx IP.
-- Maximum FFT size of 4096.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity spectrum_sense is
port (
-- Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- Control and Status Registers
status_addr : in std_logic_vector(7 downto 0);
status_data : out std_logic_vector(31 downto 0);
status_stb : in std_logic;
ctrl_addr : in std_logic_vector(7 downto 0);
ctrl_data : in std_logic_vector(31 downto 0);
ctrl_stb : in std_logic;
-- AXIS Stream Slave Interface (Time Domain / FFT Input)
axis_slave_tvalid : in std_logic;
axis_slave_tready : out std_logic;
axis_slave_tdata : in std_logic_vector(63 downto 0);
axis_slave_tid : in std_logic_vector(2 downto 0);
axis_slave_tlast : in std_logic;
axis_slave_irq : out std_logic; -- Not used
-- AXIS Stream Master Interface (Frequency Domain / FFT Output)
axis_master_tvalid : out std_logic;
axis_master_tready : in std_logic;
axis_master_tdata : out std_logic_vector(63 downto 0);
axis_master_tdest : out std_logic_vector(2 downto 0);
axis_master_tlast : out std_logic;
axis_master_irq : out std_logic; -- Strobes when threshold exceeded
-- Sideband signals
threshold_not_exceeded : out std_logic;
threshold_not_exceeded_stb : out std_logic;
threshold_exceeded : out std_logic;
threshold_exceeded_stb : out std_logic);
end entity;
architecture RTL of spectrum_sense is
-------------------------------------------------------------------------------
-- Function / Procedure Declaration
-------------------------------------------------------------------------------
function float2real(fpin: std_logic_vector(31 downto 0)) return real is
constant xdiv : real := 2.0**23;
variable exp : integer;
variable mant : integer;
variable multexp : real;
variable mantdec : real;
variable res : real;
begin
exp := to_integer(unsigned(fpin(30 downto 23))) - 127;
multexp := 2.0**exp;
mant := to_integer(unsigned('1' & fpin(22 downto 0)));
mantdec := real(mant)/xdiv;
res := mantdec*multexp;
-- Check sign
if (fpin(31) = '1') then
res := -res;
end if;
return(res);
end function;
-------------------------------------------------------------------------------
-- Component Declaration
-------------------------------------------------------------------------------
component fft_axis
port (
aclk : in std_logic;
aresetn : in std_logic;
s_axis_config_tdata : in std_logic_vector(23 downto 0);
s_axis_config_tvalid : in std_logic;
s_axis_config_tready : out std_logic;
s_axis_data_tdata : in std_logic_vector(63 downto 0);
s_axis_data_tvalid : in std_logic;
s_axis_data_tready : out std_logic;
s_axis_data_tlast : in std_logic;
m_axis_data_tdata : out std_logic_vector(63 downto 0);
m_axis_data_tuser : out std_logic_vector(15 downto 0);
m_axis_data_tvalid : out std_logic;
m_axis_data_tready : in std_logic;
m_axis_data_tlast : out std_logic;
event_frame_started : out std_logic;
event_tlast_unexpected : out std_logic;
event_tlast_missing : out std_logic;
event_status_channel_halt : out std_logic;
event_data_in_channel_halt : out std_logic;
event_data_out_channel_halt : out std_logic);
end component;
component add_floating_point
port (
aclk : in std_logic;
aresetn : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tready : out std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_a_tlast : in std_logic;
s_axis_a_tuser : in std_logic_vector(15 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tready : out std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tready : in std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0);
m_axis_result_tlast : out std_logic;
m_axis_result_tuser : out std_logic_vector(15 downto 0));
end component;
component multiply_floating_point
port (
aclk : in std_logic;
aresetn : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tready : out std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_a_tlast : in std_logic;
s_axis_a_tuser : in std_logic_vector(15 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tready : out std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tready : in std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0);
m_axis_result_tlast : out std_logic;
m_axis_result_tuser : out std_logic_vector(15 downto 0));
end component;
component sqrt_floating_point
port (
aclk : in std_logic;
aresetn : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tready : out std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_a_tlast : in std_logic;
s_axis_a_tuser : in std_logic_vector(15 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tready : in std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0);
m_axis_result_tlast : out std_logic;
m_axis_result_tuser : out std_logic_vector(15 downto 0));
end component;
component gteq_floating_point
port (
aclk : in std_logic;
aresetn : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tready : out std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_a_tlast : in std_logic;
s_axis_a_tuser : in std_logic_vector(47 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tready : out std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tready : in std_logic;
m_axis_result_tdata : out std_logic_vector(7 downto 0);
m_axis_result_tlast : out std_logic;
m_axis_result_tuser : out std_logic_vector(47 downto 0));
end component;
component edge_detect is
generic (
EDGE : string := "R"); -- "R"ising, "F"alling, "B"oth, or "N"one.
port (
clk : in std_logic; -- Clock
reset : in std_logic; -- Active high reset
input_detect : in std_logic; -- Input data
edge_detect_stb : out std_logic); -- Edge detected strobe
end component;
-----------------------------------------------------------------------------
-- Signals Declaration
-----------------------------------------------------------------------------
type slv_256x32 is array(0 to 255) of std_logic_vector(31 downto 0);
signal ctrl_reg : slv_256x32 := (others=>(others=>'0'));
signal status_reg : slv_256x32 := (others=>(others=>'0'));
signal ctrl_stb_dly : std_logic;
signal axis_master_tdest_hold : std_logic_vector(2 downto 0);
signal axis_master_tdest_safe : std_logic_vector(2 downto 0);
signal rst : std_logic;
signal enable_fft : std_logic;
signal config_tvalid : std_logic;
signal config_tdata : std_logic_vector(23 downto 0);
signal output_mode : std_logic_vector(1 downto 0);
signal output_mode_safe : std_logic_vector(1 downto 0);
signal enable_threshold_irq : std_logic;
signal clear_threshold_latched : std_logic;
signal enable_thresh_sideband : std_logic;
signal enable_not_thresh_sideband : std_logic;
signal index_fft : std_logic_vector(15 downto 0);
signal axis_slave_tvalid_fft : std_logic;
signal axis_slave_tready_fft : std_logic;
signal axis_master_tdata_fft : std_logic_vector(63 downto 0);
signal axis_master_tvalid_fft : std_logic;
signal axis_master_tready_fft : std_logic;
signal axis_master_tlast_fft : std_logic;
signal axis_master_tlast_fft_dly : std_logic_vector(3 downto 0);
signal axis_config_tdata : std_logic_vector(23 downto 0);
signal axis_config_tvalid : std_logic;
signal axis_config_tready : std_logic;
signal event_frame_started : std_logic;
signal event_tlast_unexpected : std_logic;
signal event_tlast_missing : std_logic;
signal event_status_channel_halt : std_logic;
signal event_data_in_channel_halt : std_logic;
signal event_data_out_channel_halt : std_logic;
signal index_real_sqr : std_logic_vector(15 downto 0);
signal axis_real_tready : std_logic;
signal axis_real_sqr_tvalid : std_logic;
signal axis_real_sqr_tready : std_logic;
signal axis_real_sqr_tdata : std_logic_vector(31 downto 0);
signal axis_real_sqr_tlast : std_logic;
signal axis_imag_sqr_tvalid : std_logic;
signal axis_imag_sqr_tready : std_logic;
signal axis_imag_sqr_tdata : std_logic_vector(31 downto 0);
signal index_mag_sqr : std_logic_vector(15 downto 0);
signal axis_mag_sqr_tlast : std_logic;
signal axis_mag_sqr_tvalid : std_logic;
signal axis_mag_sqr_tready : std_logic;
signal axis_mag_sqr_tdata : std_logic_vector(31 downto 0);
signal index_mag : std_logic_vector(15 downto 0);
signal axis_mag_tlast : std_logic;
signal axis_mag_tvalid : std_logic;
signal axis_mag_tready : std_logic;
signal axis_mag_tdata : std_logic_vector(31 downto 0);
signal axis_mag_tuser : std_logic_vector(47 downto 0);
signal index_threshold : std_logic_vector(15 downto 0);
signal threshold_mag : std_logic_vector(31 downto 0);
signal axis_threshold_tlast : std_logic;
signal axis_threshold_tvalid : std_logic;
signal axis_threshold_tready : std_logic;
signal axis_threshold_tdata : std_logic_vector(7 downto 0);
signal axis_threshold_tuser : std_logic_vector(47 downto 0);
signal threshold_latched : std_logic;
signal threshold : std_logic_vector(31 downto 0);
signal threshold_exceeded_int : std_logic;
signal threshold_exceeded_reg : std_logic;
signal threshold_exceeded_index : std_logic_vector(15 downto 0);
signal threshold_exceeded_mag : std_logic_vector(31 downto 0);
signal update_threshold_stb : std_logic;
signal fft_load : std_logic;
-- Debug signals
-- signal fft_in_real : real;
-- signal fft_in_imag : real;
-- signal fft_out_real : real;
-- signal fft_out_imag : real;
begin
rst <= NOT(rst_n);
axis_slave_irq <= '0';
-- Output AXI-S Master Signals
axis_master_tvalid <= axis_master_tvalid_fft when output_mode_safe = "00" else
axis_threshold_tvalid when output_mode_safe = "01" else
'0';
axis_master_tlast <= axis_master_tlast_fft when output_mode_safe = "00" else
axis_threshold_tlast when output_mode_safe = "01" else
'0';
axis_master_tdata <= axis_master_tdata_fft when output_mode_safe = "00" else
axis_threshold_tdata(0) & (62 downto 48 => '0') & axis_threshold_tuser;
axis_master_tdest <= axis_master_tdest_safe;
inst_fft_axis : fft_axis
port map (
aclk => clk,
aresetn => rst_n,
s_axis_config_tdata => axis_config_tdata,
s_axis_config_tvalid => axis_config_tvalid,
s_axis_config_tready => axis_config_tready,
s_axis_data_tdata => axis_slave_tdata,
s_axis_data_tvalid => axis_slave_tvalid_fft,
s_axis_data_tready => axis_slave_tready_fft,
s_axis_data_tlast => axis_slave_tlast,
m_axis_data_tdata => axis_master_tdata_fft,
m_axis_data_tuser => index_fft,
m_axis_data_tvalid => axis_master_tvalid_fft,
m_axis_data_tready => axis_master_tready_fft,
m_axis_data_tlast => axis_master_tlast_fft,
event_frame_started => event_frame_started,
event_tlast_unexpected => event_tlast_unexpected,
event_tlast_missing => event_tlast_missing,
event_status_channel_halt => event_status_channel_halt,
event_data_in_channel_halt => event_data_in_channel_halt,
event_data_out_channel_halt => event_data_out_channel_halt);
-- It is possible we may want to only detect a signal without saving the FFT output.
-- In the case that we have no destination for the FFT output, this logic overrides the
-- FFT output AXI-Stream handshaking signals tvalid and tready to make sure the FFT core
-- does not stall.
axis_slave_tvalid_fft <= axis_slave_tvalid when enable_fft = '1' AND fft_load = '1' else '0';
axis_slave_tready <= axis_slave_tready_fft AND fft_load;
axis_master_tready_fft <= axis_master_tready when output_mode_safe = "00" else
axis_real_tready when output_mode_safe = "01" else
'1';
-- Counteract Xilinx's annoying behavior to partially preload the FFT. This is not necesary
-- unless the sampling rate is high enough that FFT takes longer to execute than it takes
-- to buffer the samples.
proc_fft_load : process(clk,rst_n)
begin
if (rst_n = '0') then
fft_load <= '1';
else
if rising_edge(clk) then
if (enable_fft = '1') then
if (fft_load = '1' AND axis_slave_tlast = '1' AND axis_slave_tvalid = '1') then
fft_load <= '0';
end if;
if (fft_load = '0' AND axis_master_tlast_fft = '1' AND axis_master_tvalid_fft = '1') then
fft_load <= '1';
end if;
-- Reset on error
if (event_tlast_missing = '1' OR event_tlast_unexpected = '1') then
fft_load <= '1';
end if;
else
fft_load <= '1';
end if;
end if;
end if;
end process;
real_squared_multiply_floating_point : multiply_floating_point
port map (
aclk => clk,
aresetn => rst_n,
s_axis_a_tvalid => axis_master_tvalid_fft,
s_axis_a_tready => axis_real_tready,
s_axis_a_tdata => axis_master_tdata_fft(31 downto 0),
s_axis_a_tlast => axis_master_tlast_fft,
s_axis_a_tuser => index_fft,
s_axis_b_tvalid => axis_master_tvalid_fft,
s_axis_b_tready => open,
s_axis_b_tdata => axis_master_tdata_fft(31 downto 0),
m_axis_result_tvalid => axis_real_sqr_tvalid,
m_axis_result_tready => axis_real_sqr_tready,
m_axis_result_tdata => axis_real_sqr_tdata,
m_axis_result_tlast => axis_real_sqr_tlast,
m_axis_result_tuser => index_real_sqr);
imag_squared_multiply_floating_point : multiply_floating_point
port map (
aclk => clk,
aresetn => rst_n,
s_axis_a_tvalid => axis_master_tvalid_fft,
s_axis_a_tready => open,
s_axis_a_tdata => axis_master_tdata_fft(63 downto 32),
s_axis_a_tlast => '0',
s_axis_a_tuser => (others=>'0'),
s_axis_b_tvalid => axis_master_tvalid_fft,
s_axis_b_tready => open,
s_axis_b_tdata => axis_master_tdata_fft(63 downto 32),
m_axis_result_tvalid => axis_imag_sqr_tvalid,
m_axis_result_tready => axis_imag_sqr_tready,
m_axis_result_tdata => axis_imag_sqr_tdata,
m_axis_result_tlast => open,
m_axis_result_tuser => open);
magnitude_squared_add_floating_point : add_floating_point
port map (
aclk => clk,
aresetn => rst_n,
s_axis_a_tvalid => axis_real_sqr_tvalid,
s_axis_a_tready => axis_real_sqr_tready,
s_axis_a_tdata => axis_real_sqr_tdata,
s_axis_a_tlast => axis_real_sqr_tlast,
s_axis_a_tuser => index_real_sqr,
s_axis_b_tvalid => axis_imag_sqr_tvalid,
s_axis_b_tready => axis_imag_sqr_tready,
s_axis_b_tdata => axis_imag_sqr_tdata,
m_axis_result_tvalid => axis_mag_sqr_tvalid,
m_axis_result_tready => axis_mag_sqr_tready,
m_axis_result_tdata => axis_mag_sqr_tdata,
m_axis_result_tlast => axis_mag_sqr_tlast,
m_axis_result_tuser => index_mag_sqr);
magnitude_sqrt_floating_point : sqrt_floating_point
port map (
aclk => clk,
aresetn => rst_n,
s_axis_a_tvalid => axis_mag_sqr_tvalid,
s_axis_a_tready => axis_mag_sqr_tready,
s_axis_a_tdata => axis_mag_sqr_tdata,
s_axis_a_tlast => axis_mag_sqr_tlast,
s_axis_a_tuser => index_mag_sqr,
m_axis_result_tvalid => axis_mag_tvalid,
m_axis_result_tready => axis_mag_tready,
m_axis_result_tdata => axis_mag_tdata,
m_axis_result_tlast => axis_mag_tlast,
m_axis_result_tuser => index_mag);
threshold_gteq_floating_point : gteq_floating_point
port map (
aclk => clk,
aresetn => rst_n,
s_axis_a_tvalid => axis_mag_tvalid,
s_axis_a_tready => axis_mag_tready,
s_axis_a_tdata => axis_mag_tdata,
s_axis_a_tlast => axis_mag_tlast,
s_axis_a_tuser => axis_mag_tuser,
s_axis_b_tvalid => axis_mag_tvalid,
s_axis_b_tready => open,
s_axis_b_tdata => threshold,
m_axis_result_tvalid => axis_threshold_tvalid,
m_axis_result_tready => axis_threshold_tready,
m_axis_result_tdata => axis_threshold_tdata,
m_axis_result_tlast => axis_threshold_tlast,
m_axis_result_tuser => axis_threshold_tuser);
axis_mag_tuser <= index_mag & axis_mag_tdata;
axis_threshold_tready <= axis_master_tready when output_mode_safe = "01" else
'1';
threshold_mag <= axis_threshold_tuser(31 downto 0);
index_threshold <= axis_threshold_tuser(47 downto 32);
-- TODO: Restructuring this code could give up to a 15% reduction in the latency of reporting threshold
-- exceeded. Right now threshold exceeded is updated at the end of a FFT cycle, mostly to
-- support the threshold not exceeded cases. Allowing it to update as soon as the threshold is
-- exceeded can provide a speed up. The threshold not exceeded logic will have to be changed
-- though.
proc_latch_threshold : process(clk,enable_fft)
begin
if (enable_fft = '0') then
threshold_latched <= '0';
threshold_exceeded_int <= '0';
threshold_exceeded_reg <= '0';
threshold_exceeded <= '0';
threshold_exceeded_stb <= '0';
threshold_not_exceeded <= '0';
threshold_not_exceeded_stb <= '0';
threshold_exceeded_index <= (others=>'0');
threshold_exceeded_mag <= (others=>'0');
axis_master_irq <= '0';
else
if rising_edge(clk) then
-- If the threshold is exceeded, latch the magnitude and index. This can be updated
if (axis_threshold_tvalid = '1' AND axis_threshold_tdata(0) = '1' AND threshold_latched = '0') then
threshold_latched <= '1';
threshold_exceeded_int <= '1';
threshold_exceeded_index <= index_threshold;
threshold_exceeded_mag <= threshold_mag;
end if;
-- Set sideband signals at the end of every frame based on the threshold exceeded state
if (update_threshold_stb = '1') then
-- Update threshold exceeded status register
threshold_exceeded_reg <= threshold_exceeded_int;
-- IRQ
if (enable_threshold_irq = '1') then
axis_master_irq <= threshold_exceeded_int;
end if;
-- Exceeds threshold
if (enable_thresh_sideband = '1') then
threshold_exceeded <= threshold_exceeded_int;
threshold_exceeded_stb <= threshold_exceeded_int;
end if;
-- Not Exceed Threshold
if (enable_not_thresh_sideband = '1') then
threshold_not_exceeded <= NOT(threshold_exceeded_int);
threshold_not_exceeded_stb <= NOT(threshold_exceeded_int);
end if;
else
axis_master_irq <= '0';
threshold_exceeded_stb <= '0';
threshold_not_exceeded_stb <= '0';
end if;
-- Reset threshold exceeded on start of a new frame
if (update_threshold_stb = '1' AND clear_threshold_latched = '1') then
threshold_latched <= '0';
threshold_exceeded_int <= '0';
end if;
end if;
end if;
end process;
update_threshold_edge_detect : edge_detect
generic map (
EDGE => "R")
port map (
clk => clk,
reset => rst,
input_detect => axis_threshold_tlast,
edge_detect_stb => update_threshold_stb);
-------------------------------------------------------------------------------
-- Control and status registers.
-------------------------------------------------------------------------------
proc_ctrl_status_reg : process(clk,rst_n)
begin
if (rst_n = '0') then
ctrl_stb_dly <= '0';
ctrl_reg <= (others=>(others=>'0'));
axis_master_tdest_safe <= (others=>'0');
output_mode_safe <= (others=>'0');
else
if rising_edge(clk) then
ctrl_stb_dly <= ctrl_stb;
-- Update control registers only when accelerator 0 is accessed
if (ctrl_stb = '1') then
ctrl_reg(to_integer(unsigned(ctrl_addr(7 downto 0)))) <= ctrl_data;
end if;
-- Output status register
if (status_stb = '1') then
status_data <= status_reg(to_integer(unsigned(status_addr(7 downto 0))));
end if;
-- The destination should only update when no data is being transmitted over the AXI bus.
if (enable_fft = '0') then
axis_master_tdest_safe <= axis_master_tdest_hold;
end if;
-- We can only update the mode when the FFT is complete or disabled. This prevents mode switches in the middle
-- of a AXI transfer which may corrupt it.
if (update_threshold_stb = '1' OR enable_fft = '0') then
output_mode_safe <= output_mode;
end if;
end if;
end if;
end process;
-- Control Registers
-- Bank 0 (Enable FFT and destination)
enable_fft <= ctrl_reg(0)(0);
axis_master_tdest_hold <= ctrl_reg(0)(31 downto 29);
-- Bank 1 (FFT Configuration)
axis_config_tdata <= "000" & "000000000000" & '1' & "000" & ctrl_reg(1)(4 downto 0);
axis_config_tvalid <= '1' when (ctrl_addr = std_logic_vector(to_unsigned(1,8)) AND
ctrl_reg(1)(5) = '1' AND ctrl_stb_dly = '1') else
'0';
-- output_mode: 00 - Normal FFT frequency output
-- 01 - Threshold result, Index, & Magnitude
-- 10,11 - Discard output. Useful for running the FFT when we only want to trigger on
-- the threshold being exceeded without having to send the FFT output somewhere.
output_mode <= ctrl_reg(1)(9 downto 8);
enable_threshold_irq <= ctrl_reg(1)(10);
enable_thresh_sideband <= ctrl_reg(1)(11);
enable_not_thresh_sideband <= ctrl_reg(1)(12);
clear_threshold_latched <= ctrl_reg(1)(13);
-- Bank 2 (Theshold value)
threshold <= ctrl_reg(2)(31 downto 0);
-- Status Registers
-- Bank 0 (Enable FFT and destination Readback)
status_reg(0)(0) <= enable_fft;
status_reg(0)(31 downto 29) <= axis_master_tdest_safe;
-- Bank 1 (FFT Configuration Readback)
status_reg(1)(4 downto 0) <= axis_config_tdata(4 downto 0);
status_reg(1)(5) <= axis_config_tvalid;
status_reg(1)(9 downto 8) <= output_mode_safe;
status_reg(1)(10) <= enable_threshold_irq;
status_reg(1)(11) <= enable_thresh_sideband;
status_reg(1)(12) <= enable_not_thresh_sideband;
status_reg(1)(13) <= clear_threshold_latched;
-- Bank 2 (Theshold comparison value)
status_reg(2)(31 downto 0) <= threshold;
-- Bank 3 (Threshold exceeded index and flag)
status_reg(3)(15 downto 0) <= threshold_exceeded_index;
status_reg(3)(31) <= threshold_exceeded_reg;
-- Bank 4 (Magnitude that exceeded the threshold)
status_reg(4)(31 downto 0) <= threshold_exceeded_mag;
-- Debug
-- fft_in_real <= float2real(axis_slave_tdata(63 downto 32));
-- fft_in_imag <= float2real(axis_slave_tdata(31 downto 0));
-- fft_out_real <= float2real(axis_master_tdata_fft(63 downto 32));
-- fft_out_imag <= float2real(axis_master_tdata_fft(31 downto 0));
end architecture; |
-------------------------------------------------------------------------------
-- Copyright 2013-2014 Jonathon Pendlum
--
-- This is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
-- File: spectrum_sense.vhd
-- Author: Jonathon Pendlum ([email protected])
-- Description: Specturm sensing by implementing a FFT, magnitude calculation,
-- and threshold detection. The entire pipeline is single
-- precision floating point and based on Xilinx IP.
-- Maximum FFT size of 4096.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity spectrum_sense is
port (
-- Clock and Reset
clk : in std_logic;
rst_n : in std_logic;
-- Control and Status Registers
status_addr : in std_logic_vector(7 downto 0);
status_data : out std_logic_vector(31 downto 0);
status_stb : in std_logic;
ctrl_addr : in std_logic_vector(7 downto 0);
ctrl_data : in std_logic_vector(31 downto 0);
ctrl_stb : in std_logic;
-- AXIS Stream Slave Interface (Time Domain / FFT Input)
axis_slave_tvalid : in std_logic;
axis_slave_tready : out std_logic;
axis_slave_tdata : in std_logic_vector(63 downto 0);
axis_slave_tid : in std_logic_vector(2 downto 0);
axis_slave_tlast : in std_logic;
axis_slave_irq : out std_logic; -- Not used
-- AXIS Stream Master Interface (Frequency Domain / FFT Output)
axis_master_tvalid : out std_logic;
axis_master_tready : in std_logic;
axis_master_tdata : out std_logic_vector(63 downto 0);
axis_master_tdest : out std_logic_vector(2 downto 0);
axis_master_tlast : out std_logic;
axis_master_irq : out std_logic; -- Strobes when threshold exceeded
-- Sideband signals
threshold_not_exceeded : out std_logic;
threshold_not_exceeded_stb : out std_logic;
threshold_exceeded : out std_logic;
threshold_exceeded_stb : out std_logic);
end entity;
architecture RTL of spectrum_sense is
-------------------------------------------------------------------------------
-- Function / Procedure Declaration
-------------------------------------------------------------------------------
function float2real(fpin: std_logic_vector(31 downto 0)) return real is
constant xdiv : real := 2.0**23;
variable exp : integer;
variable mant : integer;
variable multexp : real;
variable mantdec : real;
variable res : real;
begin
exp := to_integer(unsigned(fpin(30 downto 23))) - 127;
multexp := 2.0**exp;
mant := to_integer(unsigned('1' & fpin(22 downto 0)));
mantdec := real(mant)/xdiv;
res := mantdec*multexp;
-- Check sign
if (fpin(31) = '1') then
res := -res;
end if;
return(res);
end function;
-------------------------------------------------------------------------------
-- Component Declaration
-------------------------------------------------------------------------------
component fft_axis
port (
aclk : in std_logic;
aresetn : in std_logic;
s_axis_config_tdata : in std_logic_vector(23 downto 0);
s_axis_config_tvalid : in std_logic;
s_axis_config_tready : out std_logic;
s_axis_data_tdata : in std_logic_vector(63 downto 0);
s_axis_data_tvalid : in std_logic;
s_axis_data_tready : out std_logic;
s_axis_data_tlast : in std_logic;
m_axis_data_tdata : out std_logic_vector(63 downto 0);
m_axis_data_tuser : out std_logic_vector(15 downto 0);
m_axis_data_tvalid : out std_logic;
m_axis_data_tready : in std_logic;
m_axis_data_tlast : out std_logic;
event_frame_started : out std_logic;
event_tlast_unexpected : out std_logic;
event_tlast_missing : out std_logic;
event_status_channel_halt : out std_logic;
event_data_in_channel_halt : out std_logic;
event_data_out_channel_halt : out std_logic);
end component;
component add_floating_point
port (
aclk : in std_logic;
aresetn : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tready : out std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_a_tlast : in std_logic;
s_axis_a_tuser : in std_logic_vector(15 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tready : out std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tready : in std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0);
m_axis_result_tlast : out std_logic;
m_axis_result_tuser : out std_logic_vector(15 downto 0));
end component;
component multiply_floating_point
port (
aclk : in std_logic;
aresetn : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tready : out std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_a_tlast : in std_logic;
s_axis_a_tuser : in std_logic_vector(15 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tready : out std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tready : in std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0);
m_axis_result_tlast : out std_logic;
m_axis_result_tuser : out std_logic_vector(15 downto 0));
end component;
component sqrt_floating_point
port (
aclk : in std_logic;
aresetn : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tready : out std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_a_tlast : in std_logic;
s_axis_a_tuser : in std_logic_vector(15 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tready : in std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0);
m_axis_result_tlast : out std_logic;
m_axis_result_tuser : out std_logic_vector(15 downto 0));
end component;
component gteq_floating_point
port (
aclk : in std_logic;
aresetn : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tready : out std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_a_tlast : in std_logic;
s_axis_a_tuser : in std_logic_vector(47 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tready : out std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tready : in std_logic;
m_axis_result_tdata : out std_logic_vector(7 downto 0);
m_axis_result_tlast : out std_logic;
m_axis_result_tuser : out std_logic_vector(47 downto 0));
end component;
component edge_detect is
generic (
EDGE : string := "R"); -- "R"ising, "F"alling, "B"oth, or "N"one.
port (
clk : in std_logic; -- Clock
reset : in std_logic; -- Active high reset
input_detect : in std_logic; -- Input data
edge_detect_stb : out std_logic); -- Edge detected strobe
end component;
-----------------------------------------------------------------------------
-- Signals Declaration
-----------------------------------------------------------------------------
type slv_256x32 is array(0 to 255) of std_logic_vector(31 downto 0);
signal ctrl_reg : slv_256x32 := (others=>(others=>'0'));
signal status_reg : slv_256x32 := (others=>(others=>'0'));
signal ctrl_stb_dly : std_logic;
signal axis_master_tdest_hold : std_logic_vector(2 downto 0);
signal axis_master_tdest_safe : std_logic_vector(2 downto 0);
signal rst : std_logic;
signal enable_fft : std_logic;
signal config_tvalid : std_logic;
signal config_tdata : std_logic_vector(23 downto 0);
signal output_mode : std_logic_vector(1 downto 0);
signal output_mode_safe : std_logic_vector(1 downto 0);
signal enable_threshold_irq : std_logic;
signal clear_threshold_latched : std_logic;
signal enable_thresh_sideband : std_logic;
signal enable_not_thresh_sideband : std_logic;
signal index_fft : std_logic_vector(15 downto 0);
signal axis_slave_tvalid_fft : std_logic;
signal axis_slave_tready_fft : std_logic;
signal axis_master_tdata_fft : std_logic_vector(63 downto 0);
signal axis_master_tvalid_fft : std_logic;
signal axis_master_tready_fft : std_logic;
signal axis_master_tlast_fft : std_logic;
signal axis_master_tlast_fft_dly : std_logic_vector(3 downto 0);
signal axis_config_tdata : std_logic_vector(23 downto 0);
signal axis_config_tvalid : std_logic;
signal axis_config_tready : std_logic;
signal event_frame_started : std_logic;
signal event_tlast_unexpected : std_logic;
signal event_tlast_missing : std_logic;
signal event_status_channel_halt : std_logic;
signal event_data_in_channel_halt : std_logic;
signal event_data_out_channel_halt : std_logic;
signal index_real_sqr : std_logic_vector(15 downto 0);
signal axis_real_tready : std_logic;
signal axis_real_sqr_tvalid : std_logic;
signal axis_real_sqr_tready : std_logic;
signal axis_real_sqr_tdata : std_logic_vector(31 downto 0);
signal axis_real_sqr_tlast : std_logic;
signal axis_imag_sqr_tvalid : std_logic;
signal axis_imag_sqr_tready : std_logic;
signal axis_imag_sqr_tdata : std_logic_vector(31 downto 0);
signal index_mag_sqr : std_logic_vector(15 downto 0);
signal axis_mag_sqr_tlast : std_logic;
signal axis_mag_sqr_tvalid : std_logic;
signal axis_mag_sqr_tready : std_logic;
signal axis_mag_sqr_tdata : std_logic_vector(31 downto 0);
signal index_mag : std_logic_vector(15 downto 0);
signal axis_mag_tlast : std_logic;
signal axis_mag_tvalid : std_logic;
signal axis_mag_tready : std_logic;
signal axis_mag_tdata : std_logic_vector(31 downto 0);
signal axis_mag_tuser : std_logic_vector(47 downto 0);
signal index_threshold : std_logic_vector(15 downto 0);
signal threshold_mag : std_logic_vector(31 downto 0);
signal axis_threshold_tlast : std_logic;
signal axis_threshold_tvalid : std_logic;
signal axis_threshold_tready : std_logic;
signal axis_threshold_tdata : std_logic_vector(7 downto 0);
signal axis_threshold_tuser : std_logic_vector(47 downto 0);
signal threshold_latched : std_logic;
signal threshold : std_logic_vector(31 downto 0);
signal threshold_exceeded_int : std_logic;
signal threshold_exceeded_reg : std_logic;
signal threshold_exceeded_index : std_logic_vector(15 downto 0);
signal threshold_exceeded_mag : std_logic_vector(31 downto 0);
signal update_threshold_stb : std_logic;
signal fft_load : std_logic;
-- Debug signals
-- signal fft_in_real : real;
-- signal fft_in_imag : real;
-- signal fft_out_real : real;
-- signal fft_out_imag : real;
begin
rst <= NOT(rst_n);
axis_slave_irq <= '0';
-- Output AXI-S Master Signals
axis_master_tvalid <= axis_master_tvalid_fft when output_mode_safe = "00" else
axis_threshold_tvalid when output_mode_safe = "01" else
'0';
axis_master_tlast <= axis_master_tlast_fft when output_mode_safe = "00" else
axis_threshold_tlast when output_mode_safe = "01" else
'0';
axis_master_tdata <= axis_master_tdata_fft when output_mode_safe = "00" else
axis_threshold_tdata(0) & (62 downto 48 => '0') & axis_threshold_tuser;
axis_master_tdest <= axis_master_tdest_safe;
inst_fft_axis : fft_axis
port map (
aclk => clk,
aresetn => rst_n,
s_axis_config_tdata => axis_config_tdata,
s_axis_config_tvalid => axis_config_tvalid,
s_axis_config_tready => axis_config_tready,
s_axis_data_tdata => axis_slave_tdata,
s_axis_data_tvalid => axis_slave_tvalid_fft,
s_axis_data_tready => axis_slave_tready_fft,
s_axis_data_tlast => axis_slave_tlast,
m_axis_data_tdata => axis_master_tdata_fft,
m_axis_data_tuser => index_fft,
m_axis_data_tvalid => axis_master_tvalid_fft,
m_axis_data_tready => axis_master_tready_fft,
m_axis_data_tlast => axis_master_tlast_fft,
event_frame_started => event_frame_started,
event_tlast_unexpected => event_tlast_unexpected,
event_tlast_missing => event_tlast_missing,
event_status_channel_halt => event_status_channel_halt,
event_data_in_channel_halt => event_data_in_channel_halt,
event_data_out_channel_halt => event_data_out_channel_halt);
-- It is possible we may want to only detect a signal without saving the FFT output.
-- In the case that we have no destination for the FFT output, this logic overrides the
-- FFT output AXI-Stream handshaking signals tvalid and tready to make sure the FFT core
-- does not stall.
axis_slave_tvalid_fft <= axis_slave_tvalid when enable_fft = '1' AND fft_load = '1' else '0';
axis_slave_tready <= axis_slave_tready_fft AND fft_load;
axis_master_tready_fft <= axis_master_tready when output_mode_safe = "00" else
axis_real_tready when output_mode_safe = "01" else
'1';
-- Counteract Xilinx's annoying behavior to partially preload the FFT. This is not necesary
-- unless the sampling rate is high enough that FFT takes longer to execute than it takes
-- to buffer the samples.
proc_fft_load : process(clk,rst_n)
begin
if (rst_n = '0') then
fft_load <= '1';
else
if rising_edge(clk) then
if (enable_fft = '1') then
if (fft_load = '1' AND axis_slave_tlast = '1' AND axis_slave_tvalid = '1') then
fft_load <= '0';
end if;
if (fft_load = '0' AND axis_master_tlast_fft = '1' AND axis_master_tvalid_fft = '1') then
fft_load <= '1';
end if;
-- Reset on error
if (event_tlast_missing = '1' OR event_tlast_unexpected = '1') then
fft_load <= '1';
end if;
else
fft_load <= '1';
end if;
end if;
end if;
end process;
real_squared_multiply_floating_point : multiply_floating_point
port map (
aclk => clk,
aresetn => rst_n,
s_axis_a_tvalid => axis_master_tvalid_fft,
s_axis_a_tready => axis_real_tready,
s_axis_a_tdata => axis_master_tdata_fft(31 downto 0),
s_axis_a_tlast => axis_master_tlast_fft,
s_axis_a_tuser => index_fft,
s_axis_b_tvalid => axis_master_tvalid_fft,
s_axis_b_tready => open,
s_axis_b_tdata => axis_master_tdata_fft(31 downto 0),
m_axis_result_tvalid => axis_real_sqr_tvalid,
m_axis_result_tready => axis_real_sqr_tready,
m_axis_result_tdata => axis_real_sqr_tdata,
m_axis_result_tlast => axis_real_sqr_tlast,
m_axis_result_tuser => index_real_sqr);
imag_squared_multiply_floating_point : multiply_floating_point
port map (
aclk => clk,
aresetn => rst_n,
s_axis_a_tvalid => axis_master_tvalid_fft,
s_axis_a_tready => open,
s_axis_a_tdata => axis_master_tdata_fft(63 downto 32),
s_axis_a_tlast => '0',
s_axis_a_tuser => (others=>'0'),
s_axis_b_tvalid => axis_master_tvalid_fft,
s_axis_b_tready => open,
s_axis_b_tdata => axis_master_tdata_fft(63 downto 32),
m_axis_result_tvalid => axis_imag_sqr_tvalid,
m_axis_result_tready => axis_imag_sqr_tready,
m_axis_result_tdata => axis_imag_sqr_tdata,
m_axis_result_tlast => open,
m_axis_result_tuser => open);
magnitude_squared_add_floating_point : add_floating_point
port map (
aclk => clk,
aresetn => rst_n,
s_axis_a_tvalid => axis_real_sqr_tvalid,
s_axis_a_tready => axis_real_sqr_tready,
s_axis_a_tdata => axis_real_sqr_tdata,
s_axis_a_tlast => axis_real_sqr_tlast,
s_axis_a_tuser => index_real_sqr,
s_axis_b_tvalid => axis_imag_sqr_tvalid,
s_axis_b_tready => axis_imag_sqr_tready,
s_axis_b_tdata => axis_imag_sqr_tdata,
m_axis_result_tvalid => axis_mag_sqr_tvalid,
m_axis_result_tready => axis_mag_sqr_tready,
m_axis_result_tdata => axis_mag_sqr_tdata,
m_axis_result_tlast => axis_mag_sqr_tlast,
m_axis_result_tuser => index_mag_sqr);
magnitude_sqrt_floating_point : sqrt_floating_point
port map (
aclk => clk,
aresetn => rst_n,
s_axis_a_tvalid => axis_mag_sqr_tvalid,
s_axis_a_tready => axis_mag_sqr_tready,
s_axis_a_tdata => axis_mag_sqr_tdata,
s_axis_a_tlast => axis_mag_sqr_tlast,
s_axis_a_tuser => index_mag_sqr,
m_axis_result_tvalid => axis_mag_tvalid,
m_axis_result_tready => axis_mag_tready,
m_axis_result_tdata => axis_mag_tdata,
m_axis_result_tlast => axis_mag_tlast,
m_axis_result_tuser => index_mag);
threshold_gteq_floating_point : gteq_floating_point
port map (
aclk => clk,
aresetn => rst_n,
s_axis_a_tvalid => axis_mag_tvalid,
s_axis_a_tready => axis_mag_tready,
s_axis_a_tdata => axis_mag_tdata,
s_axis_a_tlast => axis_mag_tlast,
s_axis_a_tuser => axis_mag_tuser,
s_axis_b_tvalid => axis_mag_tvalid,
s_axis_b_tready => open,
s_axis_b_tdata => threshold,
m_axis_result_tvalid => axis_threshold_tvalid,
m_axis_result_tready => axis_threshold_tready,
m_axis_result_tdata => axis_threshold_tdata,
m_axis_result_tlast => axis_threshold_tlast,
m_axis_result_tuser => axis_threshold_tuser);
axis_mag_tuser <= index_mag & axis_mag_tdata;
axis_threshold_tready <= axis_master_tready when output_mode_safe = "01" else
'1';
threshold_mag <= axis_threshold_tuser(31 downto 0);
index_threshold <= axis_threshold_tuser(47 downto 32);
-- TODO: Restructuring this code could give up to a 15% reduction in the latency of reporting threshold
-- exceeded. Right now threshold exceeded is updated at the end of a FFT cycle, mostly to
-- support the threshold not exceeded cases. Allowing it to update as soon as the threshold is
-- exceeded can provide a speed up. The threshold not exceeded logic will have to be changed
-- though.
proc_latch_threshold : process(clk,enable_fft)
begin
if (enable_fft = '0') then
threshold_latched <= '0';
threshold_exceeded_int <= '0';
threshold_exceeded_reg <= '0';
threshold_exceeded <= '0';
threshold_exceeded_stb <= '0';
threshold_not_exceeded <= '0';
threshold_not_exceeded_stb <= '0';
threshold_exceeded_index <= (others=>'0');
threshold_exceeded_mag <= (others=>'0');
axis_master_irq <= '0';
else
if rising_edge(clk) then
-- If the threshold is exceeded, latch the magnitude and index. This can be updated
if (axis_threshold_tvalid = '1' AND axis_threshold_tdata(0) = '1' AND threshold_latched = '0') then
threshold_latched <= '1';
threshold_exceeded_int <= '1';
threshold_exceeded_index <= index_threshold;
threshold_exceeded_mag <= threshold_mag;
end if;
-- Set sideband signals at the end of every frame based on the threshold exceeded state
if (update_threshold_stb = '1') then
-- Update threshold exceeded status register
threshold_exceeded_reg <= threshold_exceeded_int;
-- IRQ
if (enable_threshold_irq = '1') then
axis_master_irq <= threshold_exceeded_int;
end if;
-- Exceeds threshold
if (enable_thresh_sideband = '1') then
threshold_exceeded <= threshold_exceeded_int;
threshold_exceeded_stb <= threshold_exceeded_int;
end if;
-- Not Exceed Threshold
if (enable_not_thresh_sideband = '1') then
threshold_not_exceeded <= NOT(threshold_exceeded_int);
threshold_not_exceeded_stb <= NOT(threshold_exceeded_int);
end if;
else
axis_master_irq <= '0';
threshold_exceeded_stb <= '0';
threshold_not_exceeded_stb <= '0';
end if;
-- Reset threshold exceeded on start of a new frame
if (update_threshold_stb = '1' AND clear_threshold_latched = '1') then
threshold_latched <= '0';
threshold_exceeded_int <= '0';
end if;
end if;
end if;
end process;
update_threshold_edge_detect : edge_detect
generic map (
EDGE => "R")
port map (
clk => clk,
reset => rst,
input_detect => axis_threshold_tlast,
edge_detect_stb => update_threshold_stb);
-------------------------------------------------------------------------------
-- Control and status registers.
-------------------------------------------------------------------------------
proc_ctrl_status_reg : process(clk,rst_n)
begin
if (rst_n = '0') then
ctrl_stb_dly <= '0';
ctrl_reg <= (others=>(others=>'0'));
axis_master_tdest_safe <= (others=>'0');
output_mode_safe <= (others=>'0');
else
if rising_edge(clk) then
ctrl_stb_dly <= ctrl_stb;
-- Update control registers only when accelerator 0 is accessed
if (ctrl_stb = '1') then
ctrl_reg(to_integer(unsigned(ctrl_addr(7 downto 0)))) <= ctrl_data;
end if;
-- Output status register
if (status_stb = '1') then
status_data <= status_reg(to_integer(unsigned(status_addr(7 downto 0))));
end if;
-- The destination should only update when no data is being transmitted over the AXI bus.
if (enable_fft = '0') then
axis_master_tdest_safe <= axis_master_tdest_hold;
end if;
-- We can only update the mode when the FFT is complete or disabled. This prevents mode switches in the middle
-- of a AXI transfer which may corrupt it.
if (update_threshold_stb = '1' OR enable_fft = '0') then
output_mode_safe <= output_mode;
end if;
end if;
end if;
end process;
-- Control Registers
-- Bank 0 (Enable FFT and destination)
enable_fft <= ctrl_reg(0)(0);
axis_master_tdest_hold <= ctrl_reg(0)(31 downto 29);
-- Bank 1 (FFT Configuration)
axis_config_tdata <= "000" & "000000000000" & '1' & "000" & ctrl_reg(1)(4 downto 0);
axis_config_tvalid <= '1' when (ctrl_addr = std_logic_vector(to_unsigned(1,8)) AND
ctrl_reg(1)(5) = '1' AND ctrl_stb_dly = '1') else
'0';
-- output_mode: 00 - Normal FFT frequency output
-- 01 - Threshold result, Index, & Magnitude
-- 10,11 - Discard output. Useful for running the FFT when we only want to trigger on
-- the threshold being exceeded without having to send the FFT output somewhere.
output_mode <= ctrl_reg(1)(9 downto 8);
enable_threshold_irq <= ctrl_reg(1)(10);
enable_thresh_sideband <= ctrl_reg(1)(11);
enable_not_thresh_sideband <= ctrl_reg(1)(12);
clear_threshold_latched <= ctrl_reg(1)(13);
-- Bank 2 (Theshold value)
threshold <= ctrl_reg(2)(31 downto 0);
-- Status Registers
-- Bank 0 (Enable FFT and destination Readback)
status_reg(0)(0) <= enable_fft;
status_reg(0)(31 downto 29) <= axis_master_tdest_safe;
-- Bank 1 (FFT Configuration Readback)
status_reg(1)(4 downto 0) <= axis_config_tdata(4 downto 0);
status_reg(1)(5) <= axis_config_tvalid;
status_reg(1)(9 downto 8) <= output_mode_safe;
status_reg(1)(10) <= enable_threshold_irq;
status_reg(1)(11) <= enable_thresh_sideband;
status_reg(1)(12) <= enable_not_thresh_sideband;
status_reg(1)(13) <= clear_threshold_latched;
-- Bank 2 (Theshold comparison value)
status_reg(2)(31 downto 0) <= threshold;
-- Bank 3 (Threshold exceeded index and flag)
status_reg(3)(15 downto 0) <= threshold_exceeded_index;
status_reg(3)(31) <= threshold_exceeded_reg;
-- Bank 4 (Magnitude that exceeded the threshold)
status_reg(4)(31 downto 0) <= threshold_exceeded_mag;
-- Debug
-- fft_in_real <= float2real(axis_slave_tdata(63 downto 32));
-- fft_in_imag <= float2real(axis_slave_tdata(31 downto 0));
-- fft_out_real <= float2real(axis_master_tdata_fft(63 downto 32));
-- fft_out_imag <= float2real(axis_master_tdata_fft(31 downto 0));
end architecture; |
architecture rtl of fifo is
variable sig8 : record_type_3
(
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)
(
elementA(7 downto 0)
,
elementB(3 downto 0)
),
element3(3 downto 0)
(elementC(4 downto 1), elementD(1 downto 0)),
element5
(
elementE
(3 downto
0)
(6
downto 0)
,
elementF(7 downto 0)
),
element6(4 downto
0),
element7(7 downto 0));
variable sig9 : t_data_struct
(data(7 downto 0));
variable sig9 : t_data_struct
(
data(7 downto 0)
);
begin
end architecture rtl;
|
-------------------------------------------------------------------------------
--! @project Unrolled (3) hardware implementation of Asconv1286
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FullDiffusionLayer is
port(
X0In : in std_logic_vector(63 downto 0);
X1In : in std_logic_vector(63 downto 0);
X2In : in std_logic_vector(63 downto 0);
X3In : in std_logic_vector(63 downto 0);
X4In : in std_logic_vector(63 downto 0);
X0Out : out std_logic_vector(63 downto 0);
X1Out : out std_logic_vector(63 downto 0);
X2Out : out std_logic_vector(63 downto 0);
X3Out : out std_logic_vector(63 downto 0);
X4Out : out std_logic_vector(63 downto 0));
end entity FullDiffusionLayer;
architecture structural of FullDiffusionLayer is
begin
Diff0: entity work.DiffusionLayer
generic map(SHIFT1 => 19,SHIFT2 => 28)
port map(X0In,X0Out);
Diff1: entity work.DiffusionLayer
generic map(SHIFT1 => 61,SHIFT2 => 39)
port map(X1In,X1Out);
Diff2: entity work.DiffusionLayer
generic map(SHIFT1 => 1,SHIFT2 => 6)
port map(X2In,X2Out);
Diff3: entity work.DiffusionLayer
generic map(SHIFT1 => 10,SHIFT2 => 17)
port map(X3In,X3Out);
Diff4: entity work.DiffusionLayer
generic map(SHIFT1 => 7,SHIFT2 => 41)
port map(X4In,X4Out);
end architecture structural;
|
package pkg is
procedure proc;
end package;
package body pkg is
procedure proc is
type nested_prot_t is protected
procedure proc;
end protected;
type nested_prot_t is protected body
procedure proc is
begin
end procedure;
end protected body;
variable nested_prot : nested_prot_t;
begin
nested_prot.proc;
end procedure;
end package body;
entity ent is
end;
architecture behav of ent is
begin
work.pkg.proc;
end;
|
package pkg is
procedure proc;
end package;
package body pkg is
procedure proc is
type nested_prot_t is protected
procedure proc;
end protected;
type nested_prot_t is protected body
procedure proc is
begin
end procedure;
end protected body;
variable nested_prot : nested_prot_t;
begin
nested_prot.proc;
end procedure;
end package body;
entity ent is
end;
architecture behav of ent is
begin
work.pkg.proc;
end;
|
package pkg is
procedure proc;
end package;
package body pkg is
procedure proc is
type nested_prot_t is protected
procedure proc;
end protected;
type nested_prot_t is protected body
procedure proc is
begin
end procedure;
end protected body;
variable nested_prot : nested_prot_t;
begin
nested_prot.proc;
end procedure;
end package body;
entity ent is
end;
architecture behav of ent is
begin
work.pkg.proc;
end;
|
--------------------------------------------------------------------------------
--
-- AMD 2910 Benchmark (Functional blocks) (Algorithmic Behaviour of Funct blocks)
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Feb 19, 1992
--
-- Verification Information:
--
-- Verified By whom? Date Simulator
-- -------- ------------ -------- ------------
-- Syntax yes Champaka Ramachandran Sept17, 92 ZYCAD
-- Functionality yes Champaka Ramachandran Sept17, 92 ZYCAD
--------------------------------------------------------------------------------
--library ZYCAD;
use work.types.all;
use work.MVL7_functions.all;
use work.synthesis_types.all;
entity control is
port (
I : in MVL7_VECTOR(3 downto 0);
CCEN_BAR : in MVL7;
CC_BAR : in MVL7;
Rzero_bar : in MVL7;
PL_BAR : out MVL7;
VECT_BAR : out MVL7;
MAP_BAR : out MVL7;
R_sel : out MVL7;
D_sel : out MVL7;
uPC_sel : out MVL7;
stack_sel : out MVL7;
decr : out MVL7;
load : out MVL7;
clear : out MVL7;
push : out MVL7;
pop : out MVL7
);
end control;
architecture control of control is
begin
------------------------------------------------------------------------------
ctrl:block
signal fail : MVL7;
begin
fail <= cc_bar and not(ccen_bar);
D_sel <= '1' WHEN ( I = "0010") or
( Rzero_bar = '1' and I = "1001") or
( Rzero_bar = '0' and fail = '1' and I = "1111") or
( ( fail = '0') and
( ( I = "0001" ) or ( I = "0011" ) or
( I = "0101" ) or ( I = "0110" ) or
( I = "0111" ) or ( I = "1011" )
)
) ELSE
'0';
uPC_sel <= '1' WHEN ( I = "0100" ) or ( I = "1100" ) or ( I = "1110") or
( ( fail = '1') and ( ( I = "0001" ) or ( I = "0011" ) or
( I = "0110" ) or ( I = "1010" ) or
( I = "1011" ) or ( I = "1110" )
)
) or
( ( Rzero_bar = '0') and
( ( I = "1000" ) or ( I = "1001") )
) or
( (fail = '0') and
( ( I = "1111" ) or ( I = "1101") )
) ELSE
'0';
stack_sel <= '1' WHEN ( Rzero_bar = '1' and I = "1000") or
( fail = '0' and I = "1010") or
( fail = '1' and I = "1101") or
( Rzero_bar = '1' and fail = '1' and I = "1111") ELSE
'0';
R_sel <= '1' WHEN (( fail = '1') and (( I = "0101" ) or ( I = "0111"))) ELSE
'0';
push <= '1' WHEN ( (fail = '0') and ( I = "0001") ) or
( I = "0100" ) or
( I = "0101") ELSE
'0';
pop <= '1' WHEN ( (fail = '0') and ( ( I = "1010" ) or ( I = "1011" ) or
( I = "1101" ) or ( I = "1111" )
)
) or
( (Rzero_bar = '0') and
( (I = "1000" ) or ( I = "1111") )
) ELSE
'0';
load <= '1' WHEN ( (I = "1100") or
( I = "0100" and fail = '0')) ELSE
'0';
decr <= '1' WHEN ( (Rzero_bar = '1') and
( (I = "1000" ) or ( I = "1001" ) or ( I = "1111") )
) ELSE
'0';
MAP_BAR <= '0' WHEN I = "0010" ELSE
'1';
VECT_BAR <= '0' WHEN I = "0110" ELSE
'1';
PL_BAR <= '1' WHEN ( I = "0010" ) or ( I = "0110") ELSE
'0';
clear <= '1' WHEN I = "0000" ELSE
'0';
end block ctrl;
------------------------------------------------------------------------------
end control;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2223.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02223ent IS
END c07s02b06x00p01n01i02223ent;
ARCHITECTURE c07s02b06x00p01n01i02223arch OF c07s02b06x00p01n01i02223ent IS
BEGIN
TESTING: PROCESS
variable BOOLV : BOOLEAN := FALSE;
variable k : integer;
BEGIN
k := BOOLV mod BOOLV;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02223 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02223arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2223.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02223ent IS
END c07s02b06x00p01n01i02223ent;
ARCHITECTURE c07s02b06x00p01n01i02223arch OF c07s02b06x00p01n01i02223ent IS
BEGIN
TESTING: PROCESS
variable BOOLV : BOOLEAN := FALSE;
variable k : integer;
BEGIN
k := BOOLV mod BOOLV;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02223 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02223arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2223.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02223ent IS
END c07s02b06x00p01n01i02223ent;
ARCHITECTURE c07s02b06x00p01n01i02223arch OF c07s02b06x00p01n01i02223ent IS
BEGIN
TESTING: PROCESS
variable BOOLV : BOOLEAN := FALSE;
variable k : integer;
BEGIN
k := BOOLV mod BOOLV;
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02223 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02223arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Tx_queue is
generic(
HEAD_AWIDTH : natural := 5;
FIFO_AWIDTH : natural := 2;
RAM_TYPE : string := "DIS_RAM"
);
port (
clk : in std_logic;
reset : in std_logic;
-- Tx Output
queue_empty : out std_logic;
head_raddr : in std_logic_vector(HEAD_AWIDTH - 1 downto 0);
head_rdata : out std_logic_vector(7 downto 0);
head_rd_block : in std_logic;
-- zcpsm
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0)
);
end entity;
architecture arch_Tx_queue of Tx_queue is
component fifo_block
generic(
DWIDTH : INTEGER;
BLOCK_AWIDTH : INTEGER;
FIFO_AWIDTH : INTEGER;
RAM_TYPE : STRING);
port(
clk : in std_logic;
reset : in std_logic;
clr : in std_logic;
wr_block : in std_logic;
wr_clk : in std_logic;
wren : in std_logic;
waddr : in std_logic_vector((BLOCK_AWIDTH-1) downto 0);
wdata : in std_logic_vector((DWIDTH-1) downto 0);
rd_block : in std_logic;
rd_clk : in std_logic;
raddr : in std_logic_vector((BLOCK_AWIDTH-1) downto 0);
rdata : out std_logic_vector((DWIDTH-1) downto 0);
full : out std_logic;
empty : out std_logic);
end component;
component zcpsm2fifo
generic(
BLOCK_AWIDTH : INTEGER;
DWIDTH : INTEGER);
port(
clk : in std_logic;
reset : in std_logic;
zcpsm_clk : in std_logic;
zcpsm_ce : in std_logic;
zcpsm_port_id : in std_logic_vector(3 downto 0);
zcpsm_write_strobe : in std_logic;
zcpsm_out_port : in std_logic_vector(7 downto 0);
zcpsm_read_strobe : in std_logic;
zcpsm_in_port : out std_logic_vector(7 downto 0);
fifo_wr_block : out std_logic;
fifo_wren : out std_logic;
fifo_waddr : out std_logic_vector((BLOCK_AWIDTH-1) downto 0);
fifo_wdata : out std_logic_vector((DWIDTH-1) downto 0);
fifo_full : in std_logic;
fifo_empty : in std_logic);
end component;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_wren : std_logic;
signal fifo_waddr : std_logic_vector(HEAD_AWIDTH - 1 downto 0);
signal fifo_wdata : std_logic_vector(7 downto 0);
signal fifo_wr_block : std_logic;
begin
u_queue : fifo_block
generic map(
DWIDTH => 8,
BLOCK_AWIDTH => HEAD_AWIDTH,
FIFO_AWIDTH => FIFO_AWIDTH,
RAM_TYPE => RAM_TYPE
)
port map(
clk => clk,
reset => reset,
clr => '0',
wr_block => fifo_wr_block,
wr_clk => zcpsm_clk,
wren => fifo_wren,
waddr => fifo_waddr,
wdata => zcpsm_out_port,
rd_block => head_rd_block,
rd_clk => clk,
raddr => head_raddr,
rdata => head_rdata,
empty => fifo_empty,
full => fifo_full
);
u_zcpsm_intf : zcpsm2fifo
generic map(
BLOCK_AWIDTH => HEAD_AWIDTH,
DWIDTH => 8
)
port map(
clk => clk,
reset => reset,
zcpsm_clk => zcpsm_clk,
zcpsm_ce => zcpsm_ce,
zcpsm_port_id => zcpsm_port_id,
zcpsm_write_strobe => zcpsm_write_strobe,
zcpsm_out_port => zcpsm_out_port,
zcpsm_read_strobe => zcpsm_read_strobe,
zcpsm_in_port => zcpsm_in_port,
fifo_wr_block => fifo_wr_block,
fifo_wren => fifo_wren,
fifo_waddr => fifo_waddr,
fifo_wdata => fifo_wdata,
fifo_full => fifo_full,
fifo_empty => fifo_empty
);
queue_empty <= fifo_empty;
end arch_Tx_queue;
|
library verilog;
use verilog.vl_types.all;
entity SeqSideEightBitAdder is
port(
SW : in vl_logic_vector(15 downto 0);
KEY0 : in vl_logic;
SAVE : in vl_logic;
ADD : in vl_logic;
LEDR : out vl_logic_vector(8 downto 0);
HEX0 : out vl_logic_vector(6 downto 0);
HEX1 : out vl_logic_vector(6 downto 0)
);
end SeqSideEightBitAdder;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_epc:2.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_epc_v2_0;
USE axi_epc_v2_0.axi_epc;
ENTITY cpu_axi_epc_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
prh_clk : IN STD_LOGIC;
prh_rst : IN STD_LOGIC;
prh_cs_n : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
prh_addr : OUT STD_LOGIC_VECTOR(0 TO 31);
prh_ads : OUT STD_LOGIC;
prh_be : OUT STD_LOGIC_VECTOR(0 TO 3);
prh_rnw : OUT STD_LOGIC;
prh_rd_n : OUT STD_LOGIC;
prh_wr_n : OUT STD_LOGIC;
prh_burst : OUT STD_LOGIC;
prh_rdy : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
prh_data_i : IN STD_LOGIC_VECTOR(0 TO 31);
prh_data_o : OUT STD_LOGIC_VECTOR(0 TO 31);
prh_data_t : OUT STD_LOGIC_VECTOR(0 TO 31)
);
END cpu_axi_epc_0_0;
ARCHITECTURE cpu_axi_epc_0_0_arch OF cpu_axi_epc_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF cpu_axi_epc_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_epc IS
GENERIC (
C_S_AXI_CLK_PERIOD_PS : INTEGER;
C_PRH_CLK_PERIOD_PS : INTEGER;
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_NUM_PERIPHERALS : INTEGER;
C_PRH_MAX_AWIDTH : INTEGER;
C_PRH_MAX_DWIDTH : INTEGER;
C_PRH_MAX_ADWIDTH : INTEGER;
C_PRH_CLK_SUPPORT : INTEGER;
C_PRH0_BASEADDR : STD_LOGIC_VECTOR;
C_PRH0_HIGHADDR : STD_LOGIC_VECTOR;
C_PRH0_FIFO_ACCESS : INTEGER;
C_PRH0_FIFO_OFFSET : INTEGER;
C_PRH0_AWIDTH : INTEGER;
C_PRH0_DWIDTH : INTEGER;
C_PRH0_DWIDTH_MATCH : INTEGER;
C_PRH0_SYNC : INTEGER;
C_PRH0_BUS_MULTIPLEX : INTEGER;
C_PRH0_ADDR_TSU : INTEGER;
C_PRH0_ADDR_TH : INTEGER;
C_PRH0_ADS_WIDTH : INTEGER;
C_PRH0_CSN_TSU : INTEGER;
C_PRH0_CSN_TH : INTEGER;
C_PRH0_WRN_WIDTH : INTEGER;
C_PRH0_WR_CYCLE : INTEGER;
C_PRH0_DATA_TSU : INTEGER;
C_PRH0_DATA_TH : INTEGER;
C_PRH0_RDN_WIDTH : INTEGER;
C_PRH0_RD_CYCLE : INTEGER;
C_PRH0_DATA_TOUT : INTEGER;
C_PRH0_DATA_TINV : INTEGER;
C_PRH0_RDY_TOUT : INTEGER;
C_PRH0_RDY_WIDTH : INTEGER;
C_PRH1_BASEADDR : STD_LOGIC_VECTOR;
C_PRH1_HIGHADDR : STD_LOGIC_VECTOR;
C_PRH1_FIFO_ACCESS : INTEGER;
C_PRH1_FIFO_OFFSET : INTEGER;
C_PRH1_AWIDTH : INTEGER;
C_PRH1_DWIDTH : INTEGER;
C_PRH1_DWIDTH_MATCH : INTEGER;
C_PRH1_SYNC : INTEGER;
C_PRH1_BUS_MULTIPLEX : INTEGER;
C_PRH1_ADDR_TSU : INTEGER;
C_PRH1_ADDR_TH : INTEGER;
C_PRH1_ADS_WIDTH : INTEGER;
C_PRH1_CSN_TSU : INTEGER;
C_PRH1_CSN_TH : INTEGER;
C_PRH1_WRN_WIDTH : INTEGER;
C_PRH1_WR_CYCLE : INTEGER;
C_PRH1_DATA_TSU : INTEGER;
C_PRH1_DATA_TH : INTEGER;
C_PRH1_RDN_WIDTH : INTEGER;
C_PRH1_RD_CYCLE : INTEGER;
C_PRH1_DATA_TOUT : INTEGER;
C_PRH1_DATA_TINV : INTEGER;
C_PRH1_RDY_TOUT : INTEGER;
C_PRH1_RDY_WIDTH : INTEGER;
C_PRH2_BASEADDR : STD_LOGIC_VECTOR;
C_PRH2_HIGHADDR : STD_LOGIC_VECTOR;
C_PRH2_FIFO_ACCESS : INTEGER;
C_PRH2_FIFO_OFFSET : INTEGER;
C_PRH2_AWIDTH : INTEGER;
C_PRH2_DWIDTH : INTEGER;
C_PRH2_DWIDTH_MATCH : INTEGER;
C_PRH2_SYNC : INTEGER;
C_PRH2_BUS_MULTIPLEX : INTEGER;
C_PRH2_ADDR_TSU : INTEGER;
C_PRH2_ADDR_TH : INTEGER;
C_PRH2_ADS_WIDTH : INTEGER;
C_PRH2_CSN_TSU : INTEGER;
C_PRH2_CSN_TH : INTEGER;
C_PRH2_WRN_WIDTH : INTEGER;
C_PRH2_WR_CYCLE : INTEGER;
C_PRH2_DATA_TSU : INTEGER;
C_PRH2_DATA_TH : INTEGER;
C_PRH2_RDN_WIDTH : INTEGER;
C_PRH2_RD_CYCLE : INTEGER;
C_PRH2_DATA_TOUT : INTEGER;
C_PRH2_DATA_TINV : INTEGER;
C_PRH2_RDY_TOUT : INTEGER;
C_PRH2_RDY_WIDTH : INTEGER;
C_PRH3_BASEADDR : STD_LOGIC_VECTOR;
C_PRH3_HIGHADDR : STD_LOGIC_VECTOR;
C_PRH3_FIFO_ACCESS : INTEGER;
C_PRH3_FIFO_OFFSET : INTEGER;
C_PRH3_AWIDTH : INTEGER;
C_PRH3_DWIDTH : INTEGER;
C_PRH3_DWIDTH_MATCH : INTEGER;
C_PRH3_SYNC : INTEGER;
C_PRH3_BUS_MULTIPLEX : INTEGER;
C_PRH3_ADDR_TSU : INTEGER;
C_PRH3_ADDR_TH : INTEGER;
C_PRH3_ADS_WIDTH : INTEGER;
C_PRH3_CSN_TSU : INTEGER;
C_PRH3_CSN_TH : INTEGER;
C_PRH3_WRN_WIDTH : INTEGER;
C_PRH3_WR_CYCLE : INTEGER;
C_PRH3_DATA_TSU : INTEGER;
C_PRH3_DATA_TH : INTEGER;
C_PRH3_RDN_WIDTH : INTEGER;
C_PRH3_RD_CYCLE : INTEGER;
C_PRH3_DATA_TOUT : INTEGER;
C_PRH3_DATA_TINV : INTEGER;
C_PRH3_RDY_TOUT : INTEGER;
C_PRH3_RDY_WIDTH : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
prh_clk : IN STD_LOGIC;
prh_rst : IN STD_LOGIC;
prh_cs_n : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
prh_addr : OUT STD_LOGIC_VECTOR(0 TO 31);
prh_ads : OUT STD_LOGIC;
prh_be : OUT STD_LOGIC_VECTOR(0 TO 3);
prh_rnw : OUT STD_LOGIC;
prh_rd_n : OUT STD_LOGIC;
prh_wr_n : OUT STD_LOGIC;
prh_burst : OUT STD_LOGIC;
prh_rdy : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
prh_data_i : IN STD_LOGIC_VECTOR(0 TO 31);
prh_data_o : OUT STD_LOGIC_VECTOR(0 TO 31);
prh_data_t : OUT STD_LOGIC_VECTOR(0 TO 31)
);
END COMPONENT axi_epc;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF cpu_axi_epc_0_0_arch: ARCHITECTURE IS "axi_epc,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF cpu_axi_epc_0_0_arch : ARCHITECTURE IS "cpu_axi_epc_0_0,axi_epc,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF cpu_axi_epc_0_0_arch: ARCHITECTURE IS "cpu_axi_epc_0_0,axi_epc,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_epc,x_ipVersion=2.0,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_S_AXI_CLK_PERIOD_PS=10000,C_PRH_CLK_PERIOD_PS=10000,C_FAMILY=zynq,C_INSTANCE=axi_epc_inst,C_S_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_NUM_PERIPHERALS=1,C_PRH_MAX_AWIDTH=32,C_PRH_MAX_DWIDTH=32,C_PRH_MAX_ADWIDTH=32,C_PRH_CLK_SUPPORT=0,C_PRH0_BASEADDR=0x80600000,C_PRH0_HIGHADDR=0x8060FFFF,C_PRH0_FIFO_ACCESS=0,C_PRH0_FIFO_OFFSET=0,C_PRH0_AWIDTH=32,C_PRH0_DWIDTH=32,C_PRH0_DWIDTH_MATCH=0,C_PRH0_SYNC=1,C_PRH0_BUS_MULTIPLEX=0,C_PRH0_ADDR_TSU=0,C_PRH0_ADDR_TH=0,C_PRH0_ADS_WIDTH=0,C_PRH0_CSN_TSU=0,C_PRH0_CSN_TH=0,C_PRH0_WRN_WIDTH=0,C_PRH0_WR_CYCLE=0,C_PRH0_DATA_TSU=0,C_PRH0_DATA_TH=0,C_PRH0_RDN_WIDTH=0,C_PRH0_RD_CYCLE=0,C_PRH0_DATA_TOUT=0,C_PRH0_DATA_TINV=0,C_PRH0_RDY_TOUT=0,C_PRH0_RDY_WIDTH=100000,C_PRH1_BASEADDR=0xB000FFFF,C_PRH1_HIGHADDR=0xBFFFFFFF,C_PRH1_FIFO_ACCESS=0,C_PRH1_FIFO_OFFSET=0,C_PRH1_AWIDTH=32,C_PRH1_DWIDTH=32,C_PRH1_DWIDTH_MATCH=0,C_PRH1_SYNC=0,C_PRH1_BUS_MULTIPLEX=0,C_PRH1_ADDR_TSU=0,C_PRH1_ADDR_TH=0,C_PRH1_ADS_WIDTH=0,C_PRH1_CSN_TSU=0,C_PRH1_CSN_TH=0,C_PRH1_WRN_WIDTH=0,C_PRH1_WR_CYCLE=0,C_PRH1_DATA_TSU=0,C_PRH1_DATA_TH=0,C_PRH1_RDN_WIDTH=0,C_PRH1_RD_CYCLE=0,C_PRH1_DATA_TOUT=0,C_PRH1_DATA_TINV=0,C_PRH1_RDY_TOUT=0,C_PRH1_RDY_WIDTH=0,C_PRH2_BASEADDR=0xC000FFFF,C_PRH2_HIGHADDR=0xCFFFFFFF,C_PRH2_FIFO_ACCESS=0,C_PRH2_FIFO_OFFSET=0,C_PRH2_AWIDTH=32,C_PRH2_DWIDTH=32,C_PRH2_DWIDTH_MATCH=0,C_PRH2_SYNC=0,C_PRH2_BUS_MULTIPLEX=0,C_PRH2_ADDR_TSU=0,C_PRH2_ADDR_TH=0,C_PRH2_ADS_WIDTH=0,C_PRH2_CSN_TSU=0,C_PRH2_CSN_TH=0,C_PRH2_WRN_WIDTH=0,C_PRH2_WR_CYCLE=0,C_PRH2_DATA_TSU=0,C_PRH2_DATA_TH=0,C_PRH2_RDN_WIDTH=0,C_PRH2_RD_CYCLE=0,C_PRH2_DATA_TOUT=0,C_PRH2_DATA_TINV=0,C_PRH2_RDY_TOUT=0,C_PRH2_RDY_WIDTH=0,C_PRH3_BASEADDR=0xD000FFFF,C_PRH3_HIGHADDR=0xDFFFFFFF,C_PRH3_FIFO_ACCESS=0,C_PRH3_FIFO_OFFSET=0,C_PRH3_AWIDTH=32,C_PRH3_DWIDTH=32,C_PRH3_DWIDTH_MATCH=0,C_PRH3_SYNC=0,C_PRH3_BUS_MULTIPLEX=0,C_PRH3_ADDR_TSU=0,C_PRH3_ADDR_TH=0,C_PRH3_ADS_WIDTH=0,C_PRH3_CSN_TSU=0,C_PRH3_CSN_TH=0,C_PRH3_WRN_WIDTH=0,C_PRH3_WR_CYCLE=0,C_PRH3_DATA_TSU=0,C_PRH3_DATA_TH=0,C_PRH3_RDN_WIDTH=0,C_PRH3_RD_CYCLE=0,C_PRH3_DATA_TOUT=0,C_PRH3_DATA_TINV=0,C_PRH3_RDY_TOUT=0,C_PRH3_RDY_WIDTH=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF prh_clk: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF CLK";
ATTRIBUTE X_INTERFACE_INFO OF prh_rst: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF RST";
ATTRIBUTE X_INTERFACE_INFO OF prh_cs_n: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF CS_N";
ATTRIBUTE X_INTERFACE_INFO OF prh_addr: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF ADDR";
ATTRIBUTE X_INTERFACE_INFO OF prh_ads: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF ADS";
ATTRIBUTE X_INTERFACE_INFO OF prh_be: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF BE";
ATTRIBUTE X_INTERFACE_INFO OF prh_rnw: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF RNW";
ATTRIBUTE X_INTERFACE_INFO OF prh_rd_n: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF RD_N";
ATTRIBUTE X_INTERFACE_INFO OF prh_wr_n: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF WR_N";
ATTRIBUTE X_INTERFACE_INFO OF prh_burst: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF BURST";
ATTRIBUTE X_INTERFACE_INFO OF prh_rdy: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF RDY";
ATTRIBUTE X_INTERFACE_INFO OF prh_data_i: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF DATA_I";
ATTRIBUTE X_INTERFACE_INFO OF prh_data_o: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF DATA_O";
ATTRIBUTE X_INTERFACE_INFO OF prh_data_t: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF DATA_T";
BEGIN
U0 : axi_epc
GENERIC MAP (
C_S_AXI_CLK_PERIOD_PS => 10000,
C_PRH_CLK_PERIOD_PS => 10000,
C_FAMILY => "zynq",
C_INSTANCE => "axi_epc_inst",
C_S_AXI_ADDR_WIDTH => 32,
C_S_AXI_DATA_WIDTH => 32,
C_NUM_PERIPHERALS => 1,
C_PRH_MAX_AWIDTH => 32,
C_PRH_MAX_DWIDTH => 32,
C_PRH_MAX_ADWIDTH => 32,
C_PRH_CLK_SUPPORT => 0,
C_PRH0_BASEADDR => X"80600000",
C_PRH0_HIGHADDR => X"8060FFFF",
C_PRH0_FIFO_ACCESS => 0,
C_PRH0_FIFO_OFFSET => 0,
C_PRH0_AWIDTH => 32,
C_PRH0_DWIDTH => 32,
C_PRH0_DWIDTH_MATCH => 0,
C_PRH0_SYNC => 1,
C_PRH0_BUS_MULTIPLEX => 0,
C_PRH0_ADDR_TSU => 0,
C_PRH0_ADDR_TH => 0,
C_PRH0_ADS_WIDTH => 0,
C_PRH0_CSN_TSU => 0,
C_PRH0_CSN_TH => 0,
C_PRH0_WRN_WIDTH => 0,
C_PRH0_WR_CYCLE => 0,
C_PRH0_DATA_TSU => 0,
C_PRH0_DATA_TH => 0,
C_PRH0_RDN_WIDTH => 0,
C_PRH0_RD_CYCLE => 0,
C_PRH0_DATA_TOUT => 0,
C_PRH0_DATA_TINV => 0,
C_PRH0_RDY_TOUT => 0,
C_PRH0_RDY_WIDTH => 100000,
C_PRH1_BASEADDR => X"B000FFFF",
C_PRH1_HIGHADDR => X"BFFFFFFF",
C_PRH1_FIFO_ACCESS => 0,
C_PRH1_FIFO_OFFSET => 0,
C_PRH1_AWIDTH => 32,
C_PRH1_DWIDTH => 32,
C_PRH1_DWIDTH_MATCH => 0,
C_PRH1_SYNC => 0,
C_PRH1_BUS_MULTIPLEX => 0,
C_PRH1_ADDR_TSU => 0,
C_PRH1_ADDR_TH => 0,
C_PRH1_ADS_WIDTH => 0,
C_PRH1_CSN_TSU => 0,
C_PRH1_CSN_TH => 0,
C_PRH1_WRN_WIDTH => 0,
C_PRH1_WR_CYCLE => 0,
C_PRH1_DATA_TSU => 0,
C_PRH1_DATA_TH => 0,
C_PRH1_RDN_WIDTH => 0,
C_PRH1_RD_CYCLE => 0,
C_PRH1_DATA_TOUT => 0,
C_PRH1_DATA_TINV => 0,
C_PRH1_RDY_TOUT => 0,
C_PRH1_RDY_WIDTH => 0,
C_PRH2_BASEADDR => X"C000FFFF",
C_PRH2_HIGHADDR => X"CFFFFFFF",
C_PRH2_FIFO_ACCESS => 0,
C_PRH2_FIFO_OFFSET => 0,
C_PRH2_AWIDTH => 32,
C_PRH2_DWIDTH => 32,
C_PRH2_DWIDTH_MATCH => 0,
C_PRH2_SYNC => 0,
C_PRH2_BUS_MULTIPLEX => 0,
C_PRH2_ADDR_TSU => 0,
C_PRH2_ADDR_TH => 0,
C_PRH2_ADS_WIDTH => 0,
C_PRH2_CSN_TSU => 0,
C_PRH2_CSN_TH => 0,
C_PRH2_WRN_WIDTH => 0,
C_PRH2_WR_CYCLE => 0,
C_PRH2_DATA_TSU => 0,
C_PRH2_DATA_TH => 0,
C_PRH2_RDN_WIDTH => 0,
C_PRH2_RD_CYCLE => 0,
C_PRH2_DATA_TOUT => 0,
C_PRH2_DATA_TINV => 0,
C_PRH2_RDY_TOUT => 0,
C_PRH2_RDY_WIDTH => 0,
C_PRH3_BASEADDR => X"D000FFFF",
C_PRH3_HIGHADDR => X"DFFFFFFF",
C_PRH3_FIFO_ACCESS => 0,
C_PRH3_FIFO_OFFSET => 0,
C_PRH3_AWIDTH => 32,
C_PRH3_DWIDTH => 32,
C_PRH3_DWIDTH_MATCH => 0,
C_PRH3_SYNC => 0,
C_PRH3_BUS_MULTIPLEX => 0,
C_PRH3_ADDR_TSU => 0,
C_PRH3_ADDR_TH => 0,
C_PRH3_ADS_WIDTH => 0,
C_PRH3_CSN_TSU => 0,
C_PRH3_CSN_TH => 0,
C_PRH3_WRN_WIDTH => 0,
C_PRH3_WR_CYCLE => 0,
C_PRH3_DATA_TSU => 0,
C_PRH3_DATA_TH => 0,
C_PRH3_RDN_WIDTH => 0,
C_PRH3_RD_CYCLE => 0,
C_PRH3_DATA_TOUT => 0,
C_PRH3_DATA_TINV => 0,
C_PRH3_RDY_TOUT => 0,
C_PRH3_RDY_WIDTH => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
prh_clk => prh_clk,
prh_rst => prh_rst,
prh_cs_n => prh_cs_n,
prh_addr => prh_addr,
prh_ads => prh_ads,
prh_be => prh_be,
prh_rnw => prh_rnw,
prh_rd_n => prh_rd_n,
prh_wr_n => prh_wr_n,
prh_burst => prh_burst,
prh_rdy => prh_rdy,
prh_data_i => prh_data_i,
prh_data_o => prh_data_o,
prh_data_t => prh_data_t
);
END cpu_axi_epc_0_0_arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity 1bit_adder_subtractor is
Port ( mode : in STD_LOGIC;
cin : in STD_LOGIC;
a : in STD_LOGIC;
b : in STD_LOGIC;
s : out STD_LOGIC;
cout : out STD_LOGIC);
end 1bit_adder_subtractor;
architecture Behavioral of 1bit_adder_subtractor is
begin
s <= (a xor b) xor cin;
cout <= (cin and b) or ((cin or b) and (a xor mode));
end Behavioral;
|
----------------------------------------------------------------------------
-- Increment_PC
-- This unit is a simple Adder, which increment the current value of PC,
-- coming from the PC register, by 4(since the addresses in memory must be
-- word-aligned). The output of this unit feed the MUX_branch unit.
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.globals.all;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
entity increment_pc is
port (
-- INPUTS
from_pc : in std_logic_vector(31 downto 0); -- address coming from PC register that shoudl be incremented
-- OUTPUTS
to_mux_branch : out std_logic_vector(31 downto 0) -- address to the MUX_branch unit incremented by 4
);
end increment_pc;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
architecture behavioral of increment_pc is
begin
to_mux_branch <= std_logic_vector(unsigned(from_pc) + X"0000004");
end behavioral;
|
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